Transcend 512 MB DDR DDR500 Unbuffer Non-ECC Memory
Contents
1. No Name No Name No Name No Name 01 VREF 47 DQS8 93 VSS 139 VSS 02 DQO 48 AO 94 DQ4 140 DM8 03 VSS 49 CB2 95 DQ5 141 A10 04 DQ1 50 VSS 96 VDDQ 142 CB6 05 DQSO 51 CB3 97 DMO 143 VDDQ 06 DQ2 52 BA1 98 DQ6 144 CB7 07 VDD 53 DQ32 99 DQ7 145 VSS 08 DQ3 54 VDDQ 100 VSS 146 DQ36 09 NC 55 DQ33 101 NC 147 DQ37 10 NC 56 DQS4 102 NC 148 VDD 11 VSS 57 DQ34 103 NC 149 DM4 12 DQ8 58 VSS 104 VDDQ 150 DQ38 13 DQ9 59 BAO 105 DQ12 151 DQ39 14 DQS1 60 DQ35 106 DQ13 152 VSS 15 VDDQ 61 DQ40 107 DM1 153 DQ44 16 CK1 62 VDDQ 108 VDD 154 RAS 17 ICK1 63 ANE 109 DQ14 155 DQ45 18 VSS 64 DQ41 110 DQ15 156 VDDQ 19 DQ10 65 ICAS 111 CKE1 157 CSO 20 DQ11 66 VSS 112 VDDQ 158 CS1 21 CKEO 67 DQS5 113 159 DM5 22 VDDQ 68 DQ42 114 DQ20 160 VSS 23 DQ16 69 DQ43 115 A12 161 DQ46 24 DQ17 70 VDD 116 VSS 162 DQ47 25 DQS2 71 NC 117 DQ21 163 NC 26 VSS 72 DQ48 118 A11 164 VDDQ 27 A9 73 DQ49 119 DM2 165 DQ52 28 DQ18 74 VSS 120 VDD 166 DQ53 29 AT 75 121 DQ22 167 30 VDDQ 76 CK2 122 A8 168 VDD 31 DQ19 77 VDDQ 123 DQ23 169 DM6 32 5 78 DQS6 124 VSS 170 DQ54 33 DQ24 79 DQ50 125 A6 171 DQ55 34 VSS 80 DQ51 126 DQ28 172 VDDQ 35 DQ25 81 VSS 127 DQ29 173 36 DQS3 82 NC 128 VDDQ 174 DQ60 37 A4 83 DQ56 129 DM3 175 DQ61 38 VDD 84 DQ57 130 A3 176 VSS 39 DQ26 85 VDD 131 DQ30 177 DM7 40 DQ27 86 DQS7 132 VSS 178 0862 41 A2 87 DQ58 133 DQ31 179 DQ63 42 VSS 88 DQ59 134 CB4 180 VDDQ 43 A12. Transcend Information Inc
3. 28 Minimum Row Active to Row Activate delay tRRD 10ns 28 29 Minimum RAS to CAS Delay tRCD 15ns 3C 30 Minimum active to Precharge time tRAS 40ns 28 31 Module ROW density 256MB 40 32 Command Address Input Setup Time 0 6ns 60 33 Command Address Input Hold Time 0 6ns 60 34 Data Signal Input Setup Time 0 4ns 40 35 Data Signal Input Hold Time 0 4ns 40 36 40 Superset Information 00 DDR SDRAM Minimum Active to Active Auto Refresh 41 00 Time tRC 42 DDR SDRAM Minimum Auto Refresh to 00 Transcend Information Inc T 184PIN DDR500 Unbuffered DIMM TS64MLD64V5F 512MB With 32Mx8 CL3 Active Auto Refresh Command Period tRFC 43 DDR SDRAM Maximum Device Cycle Time tCK max 00 AA DDR SDRAM DQS DQ Skew for DQS and associated 00 DQ signals tDQSQ max 45 DDR SDRAM Read Data Hold Skew Factor tQHS 00 46 PLL Relock Time 00 47 61 Superset Information 00 62 SPD Data Revision Code REV 1 0 00 63 Checksum for Bytes 0 62 A9 A9 64 71 Manufacturers JEDEC ID Transcend TF 4 72 Manufacturing Location T 54 54 53 36 34 40 4C 73 90 Manufacturers Part Number TS64MLD64V5F 44 36 34 56 35 46 20 20 20 20 20 20 91 92 Revision Code 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number By Manufacturer Variable 99 127 Manufacturer Specific Data 128 255 Unused Storage Locations Undefined
4. Input High Logic 1 Voltage DQ DQS and DM signals VIH AC VREF 0 31 V Input Low Logic 0 Voltage DQ DQS and DM signals VIL AC VREF 0 31 V Input Differential Voltage CK and CK inputs VID AC 0 7 VDDQ 0 6 V 1 Input Crossing Point Voltage CK and CK inputs VIX AC 0 5 VDDQ 0 2 0 5 VDDQ 0 2 V 2 1 VID is the magnitude of the difference between the input level on CK and the input on CK 2 The value of VIX is expected to equal 0 5 V DDQ of the transmitting device and must track variations in the DC level of the same 3 These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation The AC and DC input specifications are relative to a VREF envelope that has been bandwidth limited 20MHz AC OPERATING TEST CONDITIONS Vpp 2 6 2 6 0 to 70 C Value 0 5 VDDQ VREF 0 31 VREF 0 31 nput timing measurement reference level VREF Output timing measurement reference level VT Output load condition See Load Circuit VIT 0 5 VDDQ lt Output pei ZO S ohm Hr VREF 7 z05 VDDQ CLoAp 30pF Output Load circuit INPUT OUTPUT CAPACITANCE voo 2 6V Vona 2 6V TA 25 C f MHz Parameter Symbol Input capacitance A0 A12 BAO BA1 RAS CAS Input capacitance CKEO Input capacitance CSO Input capacitance CKO CK2 Input capacitance DMO DM7 Data and DQS input out
5. 89 VSS 135 CB5 181 SAO 44 CBO 90 NC 136 VDDQ 182 SA1 45 CB1 91 SDA 137 CKO 183 SA2 46 VDD 92 SCL 138 CKO 184 VDDSPD Please refer Block Diagram Transcend Information Inc 3 TS64MLD64V5F 184PIN DDR500 Unbuffered DIMM 512MB With 32Mx8 CL3 Block Diagram 0 12 0 12 BAO BA1 BAO BA1 DQ0 DQ7 DQ0 DQ63 RAS ICAS 50 CKEO RAS 0 12 1 1 m DQ0 DQ7 DQ0 DQ7 32Mx8 RAS IRAS 2 5 DDR 5 DDR wg SDRAM we SPRAM 0 12 CK1 CK1 CKO CKO CK2 CK2 0 12 BAO BA1 DQ0 DQ7 RAS ICAS DQS4 RAS ICAS IWE ICS ICS1 CKE1 0 12 BAO BA1 DQ0 DQ7 0 12 BAO BA1 DQ0 DQ7 RAS 32Mx8 ICAS ppg SDRAM x 9 x CK1 CK1 CKO CKO CK2 CK2 Cnn i ea ie 94 R Serial EEPROM SCL SCL SDA SDA IWE A0 A1 A2 5 SA0 5 1 SA2 CKE 0 12 BAO BA1 9 DQ0 DQ7 RAS 0 12 0 12 BAO BA1 BAO BA1 DQ0 DQ7 DQ0 DQ7 32Mx8 H RAS 32 8 JRAS 32 8 DDR DDR DDR SDRAM CAS spRAM ICAS SDRAM IWE x ICS i 0 Sav CKE DM2 DQS2 A0 A12 x A0 A12 x BAOBA1 9 9 DQ0 DQ7 DQ0 DQ7 IRAS IRA
6. 184PIN DDR500 Unbuffered DIMM TS64MLD64V5F 512MB With 32Mx8 CL3 Description Placement The TS64MLD64V5F is a 32M x 64bits Double Data Rate SDRAM high density for DDR500 The TS64MLD64V5F consists of 16pcs CMOS 32Mx8 bits Double Data Rate SDRAMs in 66 TSOP II 400mil packages and 2048 bits serial EEPROM on a 184 pin printed circuit board The TS64MLD64V5F is a Dual In Line Memory Module and is intended for mounting into 184 pin edge connector Du DDR500 amp 512MB sockets Synchronous design allows precise cycle control with the use of system clock Data I O transactions are possible tA Q www transcend com gt 5 x x B B a 8 5 R Q 8 on both edges of DQS Range of operation frequencies programmable latencies allow the same device to be w useful for a variety of high bandwidth high performance memory system applications aere 005 Features Power supply VDD 2 6V 0 1V VDDQ 2 6V 0 1V e clock Freq 250MHZ PEUT e Double data rate architecture two data transfers De clock cycle Mh e Differential clock inputs CK and CK e DLL DQ DQS transition with CK transition d n e Auto and Self Refresh 7 8us refresh interval e Data I O transactions on both edge of data strobe PCB 09 1860 e Edge aligned data output center aligned data e Serial Presence Detect SPD w
7. ESENCE DETECT SPECIFICATION Serial Presence Detect Byte No Function Described ane 2d Vendor Part Specification 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type DDR SDRAM 07 3 of Row Addresses on this Assembly 13 OD 4 of Column Addresses on this Assembly 10 5 of Module Rows on this Assembly 2 bank 02 6 Data Width of this Assembly 64bits 40 7 Data Width of this Assembly 0 00 8 VDDQ and Interface Standard of this Assembly SSTL 2 04 9 DDR SDRAM Cycle Time at CAS Latency 3 4ns 40 10 DDR SDRAM Access Time from Clock at CL 3 0 65ns 65 11 DIMM configuration type non parity Parity ECC Non ECC 00 12 Refresh Rate Type 7 8us Self Refresh 82 13 Primary DDR SDRAM Width X8 08 14 Error Checking DDR SDRAM Width X0 00 Min Clock Delay for Back to Back Random Column Address 2 16 Burst Lengths Supported 2 4 8 OE 17 of banks on each DDR SDRAM device 4 bank 04 18 CAS Latency supported 3 10 19 CS Latency 0 CLK 01 20 WE Latency 1 CLK 02 21 DDR SDRAM Module Attributes end 20 Clock Input 22 DDR SDRAM Device Attributes General 00 23 DDR SDRAM Cycle Time CL 2 5 00 24 DDR SDRAM Access from Clock CL 2 5 00 25 DDR SDRAM Cycle Time CL 2 0 0 26 DDR SDRAM Access from Clock CL 2 0 0 27 Minimum Row Precharge Time tRP 15ns 3C
8. S ICAS 32Mx8 ICAS 32Mx8 DDR DDR ANE SDRAM SDRAM ICS ICS 2 CKE 2 g CKE DM6 DM7 DQS6 DQS7 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend Information Inc 184PIN DDR500 Unbuffered DIMM TS64MLD64V5F 512MB With 32Mx8 CL3 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 0 5 3 6 V Voltage on VDD supply to Vss VDD VDDQ 1 0 3 6 V Storage temperature TSTG 55 150 C Power dissipation PD 24 W Short circuit current los 50 mA Mean time between failure MTBF 50 year Temperature Humidity Burning THB 85 C 85 Static Stress C Temperature Cycling Test TC 0 C 125 C Cycling C Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C Parameter S
9. e accordingly 5 The specific requirement is that DQS be valid HIGH LOW or at some point on a valid transition on or before this CK edge A valid transition is defined as monotonic and meeting the input slew rate specifications of the device When no writes were previously in progress on the bus DQS will be transitioning from High Z to logic LOW If a previous write was in progress DQS could be HIGH LOW or transitioning from HIGH to LOW at this time depending on tDQSS 6 A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device 7 For command address input slew rate 2 0 5 V ns 8 For CK amp CK slew rate 2 0 5 V ns 9 These parameters guarantee device timing but they are not necessarily tested on each device They may be guaranteed by device design or tester correlation 10 Slew Rate is measured between VOH ac and VOL ac 11 Min tCL tCH refers to the smaller of the actual clock low time and the actual clock high time as provided to the device i e this value can be greater than the minimum specification limits for tCL and tCH For example tCL and tCH are 50 of the period less the half period jitter tJIT HP of the clock source and less the half period jitter due to crosstalk tJIT crosstalk into 12 tQH tHP tQHS where tHP minimum half clock period for any given cycle and is defined by clock high or clock low tCH tCL tQHS accounts for 1 The pulse duration distortion of on chi
10. e issued only at all banks precharge state A new command can be issued 2 clock cycles after EMRS or MRS 3 Auto refresh functions are same as the CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at all banks precharge state 4 1 Bank select addresses If both BAO and are Low at read write row active and precharge bank A is selected If both BAO is High and 1 is Low at read write row active and precharge bank B is selected If both BAO is Low and 1 is High at read write row active and precharge bank C is selected If both BAO and are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAO and BA1 are ignored and all banks are selected During burst write with auto precharge new read write command cannot be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst Burst stop command is valid at every burst length DM sampled at the rising and falling edges of the DQS and Data in is masked at the both edges Write DM latency is 0 This combination is not defined for any function which means No Operation NOP in DDR SDRAM Gorey ened Transcend Information Inc 10 184PIN DDR500 Unbuffered DIMM TS64MLD64V5F 512MB With 32Mx8 CL3 SERIAL PR
11. f the difference between the input level on CK and the input level on CK 4 These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 250MHZ 5 The value of Vix is expected to equal 0 5 VDDQ of the transmitting device and must track variations in the dc level of the same Transcend Information Inc 5 184PIN DDR500 Unbuffered DIMM TS64MLD64V5F 512MB With 32Mx8 CL3 DC CHARACTERISTICS Recommended operating condition unless otherwise noted VDD 2 7V TA 10 C Parameter Symbol Max Unit Note Operating current One bank Active Precharge tRC tRCmin DQ DM and DQS inputs changing twice per clock cycle IDDO 1 440 mA Address and control inputs changing once per clock cycle Operating current One bank operation One bank open Burst 4 Reads refer to the following page for detailed test condition PP nee nh Precharge power down standby current All banks idle power down mode CKE VIL max VIN VREF for DQ DQS and DM IDDA 99 ne Precharge Floating standby current CS gt VIH min All banks idle CKE gt VIH min Address and other control inputs changing once per clock IDD2F 480 mA cycle VIN VREF for DQ DQS and DM Active power down standby current one bank active power down mode CKE lt VIL max VIN VREF
12. for DQ DQS and DM dd 39 n Active standby current CS gt VIH min CKE gt VIH min one bank active active precharge tRC tRASmax DQ DQS and DM inputs changing twice per clock cycle address and other control inputs changing once per clock cycle IDD3N 1 200 mA Operating current burst read Burst length 2 reads continuous burst One bank active address and control inputs changing once per clock cycle IDD4R 2 080 mA 50 of data changing at every burst lout 0 mA Operating current burst write Burst length 2 writes continuous burst One bank active address and control inputs changing once per clock cycle DQ DM and DQS inputs changing twice per clock cycle 50 of input data changing at every burst IDD4W 2 360 mA Auto refresh current tRC tRFC min 10 tCK for DDR500 at 250MHz distributed refresh DD 2209 Self refresh current lt 0 2 External clock should be on IDD6 48 mA Operating current Four bank operation Four bank interleaving with BL 4 Refer to the following page for detailed test condition 2009 m Note 1 Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading capacitor Transcend Information Inc 6 184PIN DDR500 Unbuffered DIMM TS64MLD64V5F 512MB With 32Mx8 CL3 AC OPERATING CONDITIONS Parameter Symbol Min Max Unit Note
13. ith serial EEPROM SSTL 2 compatible inputs and outputs MRS cycle with address key programs CAS Latency Access from column address 3 Burst Length 2 4 8 Data Sequence Sequential amp Interleave Transcend Information Inc 1 TS64MLD64V5F 184PIN DDR500 Unbuffered DIMM 512MB With 32Mx8 CL3 Pin Identification Symbol Function 0 12 BAO BA1 Address input Dimensions Side Millimeters Inches 133 35 0 20 5 250 0 008 B 72 40 2 850 C 6 35 0 250 D 2 20 0 087 E 30 48 0 20 1 200 0 008 F 19 80 0 800 G 4 00 0 157 H 12 00 0 472 1 27 0 10 0 050 0 004 7 5 Max 0 3 Max K 32 28 0 30 1 271 0 012 Refer Placement Transcend Information Inc DQ0 DQ63 Data Input Output DQS0 DQS7 Data strobe input output CKO CKO CK1 CK1 Clock Input CK2 CK2 CKEO CKE1 Clock Enable Input 50 CS1 Chip Select Input RAS Row Address Strobe ICAS Column Address Strobe AVE Write Enable DMO DM7 Data in Mask VDD 2 5 Voltage power supply 2 5 Voltage Power Supply for VDDQ DQS VREF Power Supply for Reference 2 5 Voltage Serial EEPROM VDDSPD Power Supply SA0 SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output VSS Ground NC No Connection 184PIN DDR500 Unbuffered DIMM TS64MLD64V5F 512MB With 32Mx8 CL3 Pinouts
14. om CK CK tHZ tAC max ns 3 Data out low impedance time from CK CK tLZ tAC min tAC max ns 3 Mode register set cycle time tMRD 2 ns DQ amp DM setup time to DQS tDS 0 4 ns DQ amp DM hold time to DQS tDH 0 4 ns DQ amp DM input pulse width tDIPW 1 75 ns 9 Transcend Information Inc 184PIN DDR500 Unbuffered DIMM TS64MLD64V5F 512MB With 32Mx8 CL3 Control amp Address input pulse width for each input tIPW 2 2 ns 9 Refresh interval time tREF 7 8 us 6 Output DQS valid window TQH tHP tOHS ns 12 Clock half period tHP tCLmin tCHmin ns 11 12 Data hold skew factor tQHS 0 5 ns 12 Auto Precharge write recovery precharge time ns 14 Exit self refresh to non read command tXSNR 75 ns Exit self refresh to read command tXSRD 200 ns Note 1 VID is the magnitude of the difference between the input level CK and the input level on CK 2 The value of VIX is expected to equal 0 5 VDDQ of the transmitting device and must track variations in the dc level of the same 3 tHZ and tLZ transitions occur in the same access time windows as valid data transitions These parameters are not referenced to a specific voltage level but specify when the device output in no longer driving HZ or begins driving LZ 4 The maximum limit for this parameter is not a device limit The device will operate with a greater value for this parameter but sys tem performance bus turnaround will degrad
15. p clock circuits and 2 The worst case push out of DQS on one transition followed by the worst case pull in of DQ on the next transition both of which are separately due to data pin skew and output pattern effects and p channel to n channel variation of the output drivers 13 tDQSQ Consists of data pin skew and output pattern effects and p channel to n channel variation of the output drivers for any given cycle 14 tDAL tWR tCK tRP tCK 15 In all circumstances tXSNR can be satisfied using tXSNR tRFCmin 1 tCK 16 The only time that the clock frequency is allowed to change is during self refresh mode Transcend Information Inc 184PIN DDR500 Unbuffered DIMM TS64MLD64V5F 512MB With 32Mx8 CL3 SIMPLIFIED TRUTH TABLE V Valid X Don t Care H Logic High L Logic Low COMMAND TE Ee eas Arras Ars Av Extended Mode Register Set OP CODE OP CODE Auto Refresh Refresh TP Refresh Exit LI Read amp Auto Precharge Disable Column Address Column Address Auto Precharge Enable Ao As Write amp Auto Precharge Disable pena Column Address Auto Precharge mee 5 Precharae Bank Selection 9 All Banks SSS Active Power Down Precharge Power Down Mode DM No Operation Command Note 1 OP Code Operand Code A0 A12 amp BAO BA1 Program keys EMRS MRS 2 EMRS MRS can b
16. put capacitance DQ0 DQ63 Transcend Information Inc 7 TS64MLD64V5F AC TIMING PARAMETERS amp SPECIFICATIONS These AC characteristics were tested on the Component 184PIN DDR500 Unbuffered DIMM 512MB With 32Mx8 CL3 Parameter Symbol Min Max Unit Note Row cycle time tRC 55 ns Refresh row cycle time tRFC 70 ns Row active time tRAS 40 70K ns RAS to CAS delay tRCD 15 ns Row active to Row active delay tRP 15 ns Row active to Row active delay tRRD 10 ns Write recovery time tWR 15 ns Last data in to Read command tWTR 2 tCK Clock cycle time tCK 4 10 ns 16 Clock high level width tCH 0 45 0 55 tCK Clock low level width tCL 0 45 0 55 tCK DQS out access time from CK CK tDQSCK 0 55 0 55 ns Output data access time from CK CK tAC 0 65 0 65 ns Data strobe edge to output data edge tDQSQ 0 4 ns 13 Read Preamble tRPRE 0 9 1 1 tCK Read Postamble tRPST 0 4 0 6 tCK CK to valid DQS in tDQSS 0 72 1 28 tCK Write preamble setup time tWPRES 0 ps 5 Write preamble tWPRE 0 25 tCK Write postamble tWPST 0 4 0 6 tCK 4 DQS falling edge to CK rising setup time tDSS 0 2 tCK DQS falling edge from CK rising hold time tDSH 0 2 tCK DQS in high level width tDQSH 0 35 tCK DQS in low level width tDQSL 0 35 tCK Address and Control input setup time tIS 0 6 ns 7 10 Address and Control input hold time tIH 0 6 ns 7 10 Data out high impedance time fr
17. ymbol Min Max Unit Note Supply voltage VDD 2 5 2 7 V Supply voltage VDDQ 2 5 2 7 V Reference voltage VREF VDDQ 2 50mV 2 50 V 1 Termination voltage VTT VREF 0 04 VREF 0 04 V 2 Input logic high voltage VIH DC VREF 0 15 VDDQ 0 3 V 4 Input logic low voltage VIL DC 0 3 VREF 0 15 V 4 Input Voltage Level CK and CK inputs VIN DC 0 3 VDDQ 0 3 V Input Differential Voltage CK and CK inputs VID DC 0 3 VDDQ 0 6 V 3 Input crossing point voltage CK and CK inputs VIX DC 1 15 1 35 V 5 Input leakage current 2 2 uA Output leakage current loz 5 5 uA Output High Current Normal strength driver VOUT VTT 0 84V PH m Output Low Current Normal strength driver VOUT VTT 0 84V id mm me Output High Current Half strength driver VOUT VTT 0 45V SE i ns Output High Current Half strength driver lat 9 A VOUT VTT 0 45V Note 1 Includes 25mV margin for DC offset on VREF and a combined total of x 50mV margin for all AC noise and DC offset on VREF bandwidth limited to 20MHz The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF both of which may result in VREF noise VREF should be de coupled with an inductance of lt 3nH 2 VTT is not applied directly to the device VTT is a system supply for signal termination resistors is expected to be set equal to VREF and must track variations in the DC level of VREF 3 VID is the magnitude o
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