Transcend 512MB DDR333 Unbuffer Non-ECC Memory
Contents
1. eS Supply voltage 11 1 VD 23 27 V O Supply voltage 1 1 1 Vra 23 27 v amp 4 Reference voltage VREF VpDa 2 50mV Vobo 2 0mV V 1 Termination voltage VTT VREF 0 04 VREF 0 04 V 2 Input logic high voltage VIH p VREF 0 15 Voo03 V 4 Input logic low voltage ViL c 03 45 V 4 Input Voltage Level CK CK VIN c 03 V 036 000 906 Input leakage current 1 Wu 4 2 2 QvA Output leakage current 1 loz 5 95 JuA O Output High Current Normal strength driver VOUT VTT 0 84V ii Mos Output Low Current Normal strength driver VOUT VTT 0 84V i ie i Output High Current Half strength driver jeu A VOUT VTT 0 45V Note 1 Includes 25mV margin for DC offset on VREF and a combined total of 50mV margin for all AC noise and DC offset on VREF bandwidth limited to 20MHz The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF both of which may result in VREF noise VREF should be de coupled with an inductance of 3nH 2 VIT is not applied directly to the device VTT is a system supply for signal termination resistors is expected to be set equal to VREF and must track variations in the DC level of VREF 3 VID is the magnitude of the di2. 7 m 09 1397 TS64MLD64V3F5 Dimensions Side I O mm o Millimeters 133 35 0 20 72 39 6 35 2 20 30 48 0 20 19 80 4 00 12 00 1 27 0 10 Refer Placement Transcend Information Inc Inches 5 250 0 008 2 850 0 250 0 087 1 20 0 008 0 779 0 157 0 472 0 050 0 004 184PIN DDR333 Unbuffered DIMM 512MB With 32Mx8 CL2 5 Pin Identification Symbol Function A0 A12 BAO Address input DQ0 DQ63 DQS0 DQS7 CK1 CK1 CK2 CK2 CKEO CKE1 CS0 CS1 RAS CAS AVE DMO DM7 VDD VDDQ VREF VDDSPD SA0 SA2 SCL SDA VSS NC Data Input Output Data strobe input output Clock Input Clock Enable Input Chip Select Input Row Address Strobe Column Address Strobe Write Enable Data in Mask 2 5 Voltage power supply 2 5 Voltage Power Supply for DQS Power Supply for Reference 2 5 Voltage Serial EEPROM Power Supply Address in EEPROM serial PD Clock Serial PD Add Data input output Ground No Connection 184PIN DDR333 Unbuffered DIMM TS64M LD64V3F5 512MB With 32Mx8 CL2 5 Pinouts Please refer Block Diagram Transcend Information Inc 3 184PIN DDR333 Unbuffered DIMM TS64M LD64V3F5 512MB With 32Mx8 CL2 5 Block Diagram A0 A12 BAO BA1 BAO BA1 000 0063 000 007 RAS CAS an B ANE n CK1 CK1 CKO CK
3. O1 o O DDR SDRAM Device Attributes General 0 2V voltage tolerance DDRSDRAMCydeTimeCL 1 0 o 0 o DDR SDRAM Access from Clock CL 1 5 22 23 24 2 25 26 1 27 ini 28 29 30 2 31 32 33 34 35 36 61 Supersetinformation o 62 SPD Data Revision Code LED Transcend Information Inc 10 TS64MLD64V3F5 184PIN DDR333 Unbuffered DIMM 512MB With 32Mx8 CL2 5 63 Checksum for Bytes 0 62 HEN NN NENNEN gt 64 71 Manufacturers ID 7F 4 72 Manufacturing Location 54 sa 53 34 40 ac 73 90 Manufacturers Part Number TS64MLD64V3F5 ras 20 20 20 20 20 9192 RevisionCode Z 0 oo Variable Variable 99 127 ManufacturerSpecificData o Transcend Information Inc 1
4. Control input setup time S 075 n Address and Control input hold time UH 075 n Data out high impedance time from CK CK n Data out low impedance time from CK CK n Mode register set cycle time tMRD 12 DQ amp DM setup time to 20 ts 045 XA in DQ amp DM hold time to tH 045 X2 nm DQ amp DM input pulse width 175 3 nm xit self refresh to non read command tXSNR 75 ns xit self refresh to read command tXSRD 200 tCK Refresh interval time tREF 78 J vu tHP tCLmin or DQS write postamble time iuc Aor MEN tCK Note 1 Maximum burst refresh of 8 2 The specific requirement is that DQS be valid High or Low on or before this CK edge The case shown DQS going from High Z to logic Low applies when no writes were previously in progress on the bus If a previous write was in progress DQS could be High at this time depending on tDQSS 3 The Maximum limit for this parameter is not a device limit The device will operate with a great value for this parameter but system performance bus turnaround will degrade accordingly 1 Transcend Information Inc 8 184PIN DDR333 Unbuffered DIMM TS64M LD64V3F5 512MB With 32Mx8 CL2 5 SIMPLIFIED TRUTH TABLE V Valid X Don t Care H Logic High L Logic Low COMMAND IcAs Ao Ao Art Ar Ca Extended Mode Register Set LEER HEU E OP CODE Refresh
5. down mode CKE lt VIL max tCK tCK min VIN VREF for DQ DQS and DM IDD3P 560 3 Active standby current CS gt VIH min CKE gt VIH min one bank active active precharge tRC tRASmax tCK tCK min DQ DQS and DM inputs changing twice per clock cycle address and other control inputs changing once per clock cycle IDD3N 880 Operating current burst read Burst length 2 reads continuous burst One bank active address and control inputs changing once per clock cycle CL 2 5 at tCK min 50 of data changing at every burst lout 0 mA IDD4R 1800 3 gt Operating current burst write Burst length 2 writes continuous burst One bank active address and control inputs changing once per clock cycle CL 2 5 at tCK tCK min DQ DM and DQS inputs changing twice per clock cycle 50 of input data changing at every burst IDD4W 1800 Auto refresh current tRC tRFC min IDD5 Self refresh current lt 0 2V Operating current Four bank operation Four bank interleaving with BL 4 IDD7 3040 mA Refer to the following page for detailed test condition 1880 mA DA gt gt Note Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap Transcend Information Inc 6 184PIN DDR333 Unbuffered DIMM TS64M LD64V3F5 512MB With 32Mx8 CL2 5 AC OPERATING CONDITIONS Parameter Symbo
6. O EXE H CK2 CK2 _ L A0 A12 BAO BA1 000 007 _ RAS gi z DDR SDRAM 8 A0 A12 A0 A12 BAO BA1 BAO BA1 BAO BA1 a 000 007 000 007 000 007 RAS RAS RAS EHE CS1 EL E CS m CK1 CK1 iul CKO CKO CK2 CK2 a a A0 A12 lt BAO BA1 DQ0 DQ7 RAS Serial EEPROM ICAS gun m ScL SCL SDA SDA IWE SDRAM SDRAM A0 A1 A2 SAO SA1 SA2 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assumes no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend Information Inc 4 184PIN DDR333 Unbuffered DIMM TS64M LD64V3F5 512MB With 32Mx8 CL2 5 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Voltage on any pin relative to Vss VIN VOUT 0 5 3 6 Voltage on VDD supply to Vss VDD VDDQ 1 0 3 6 Storage temperature Trg st Power dissipation Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability D OPERATING ecommended operatin Vss OV 0 to 70 CO Ita 7
7. Refresh o E Refresh Self y Refresh Exit Bank Active amp Row Addr ao Eves Row Address Read amp Auto Precharge Disable Column Address Column Address Auto Precharge Enable Ao Ac Write amp Auto Precharge Disable Column Address Column Address Auto Precharge Enable Burst Stop Burst Stop Precharaa Bank Selection 9 All Banks Active Power Down Precharge Power Down Mode Note 1 Code Operand Code 0 A12 amp Program keys EMRS MRS 2 EMRS MRS can be issued only at all banks precharge state 3 Auto refresh functions are same as the CBR refresh of DRAM The automatic precharge without row precharge command is meant by Auto Auto self refresh can be issued only at all banks precharge state 4 Bank select addresses If both BAO and are Low at read write row active and precharge bank A is selected If both is High and is Low at read write row active and precharge bank B is selected If both BAO is Low and BAT is High at read write row active and precharge bank C is selected If both BAO and BA1 are High at read write row active and precharge bank D is selected 5 If A10 AP is High at row precharge BAO and are ignored and all banks are selected 6 During burst write with auto precharge new read write command cannot be issued Another bank read write command can be issued after the end of burst N
8. TS64MLD64V3F5 Description The TS64MLD64V3F5 is a 64Mx64bits Double Data Rate SDRAM high density for DDR333 The TS64MLD64V3F5 consists of 16pcs CMOS 32Mx8 bits Double Data Rate SDRAMs in 66 pin 400mil packages and a 2048 bits serial EEPROM on a 184 pin printed circuit board The TS64MLD64V3F5 is a Dual In Line Memory Module and is intended for mounting into 184 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock Data transactions are possible on both edges of DQS Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features RoHS compliant products Power supply VDD 2 5V 0 2V VDDQ 2 5V 0 2V Max clock Freq 166MHZ Double data rate architecture two data transfers per clock cycle Differential clock inputs CK and CK Burst Mode Operation Auto and Self Refresh Data I O transactions on both edge of data strobe Edge aligned data output center aligned data input serial Presence Detect SPD with serial EEPROM SSTL 2 compatible inputs and outputs MRS cycle with address key programs CAS Latency Access from column address 2 5 Burst Length 2 4 8 Data Sequence Sequential amp Interleave Transcend Information Inc 184PIN DDR333 Unbuffered DIMM 512MB With 32Mx8 CL 2 5 Placement
9. d Mi Max Umit Input High Logic 1 Voltage DQ 00 and DM signals VREF 031 nput Low Logic 0 Voltage DQ DQS and DM signals VIL AC _ 0 31 Input Differential Voltage CK and CK inputs VID AC VDDQ 0 6 Input Crossing Point Voltage CK and CK inputs VIX AC 0 5 VDDQ 0 2 0 5 VDDQ 02 Note 1 VIH max 4 2V The overshoot voltage duration is lt 3ns at VDD 2 VIL min 1 5V The undershoot voltage duration is lt 3ns at VSS 3 VID is the magnitude of the difference between the input level on CK and the input on CK 4 The Value of VIX is expected to equal 0 5 VDDQ of the transmitting device and must track variations in the DC level of the same AC OPERATING TEST CONDITIONS VDD 2 5 VDDQ 2 5 TA 0 to 70 C Parameter Vaw Unt Noe Input reference voltage for Clock 0 5 VDDQ S Input signal maximum peak swing _ 18 0 InputLevels VIHVIL VREFSOMREFOS input timing measurement referencelevel VREE J V Doo Output timing measurement reference lev tt Doo Output load condition SeeloadCircut VTT 0 5 VDDQ 0 5 VDDQ CLoAD 30pF Output Load circuit Input Output CAPACITANCE Voo 2 5V Vona 2 5V TA 25 C f 1MHz Input capacitance A0 A12 BAO BA1 RAS CAS ANE Input capacitance CKEO CKE1 Input capacitance CSO CS1 Input capacitance CLKO CLK1 CLK2 Da
10. ew row active of the associated bank can be issued at tRP after the end of burst Burst stop command is valid at every burst length DM sampled at the rising and falling edges of the DQS and Data in is masked at the both edges Write DM latency is O This combination is not defined for any function which means No Operation NOP in DDR SDRAM eS Transcend Information Inc 9 184PIN DDR333 Unbuffered DIMM TS64M LD64V3F5 512MB With 32Mx8 CL2 5 Serial Presence Detect Specification Serial Presence Detect Byte No Function Described Standard Vendor Part Specification 0 jofBytes Written into Serial Memory 128bytes 1 Total ofBytes of S P D Memory 256bytes OB 3 _ ofRowAddresses onthisAssembly OD 6 Data Width ofthis Assembly 64bts 7 DataWidth ofthisAssembly O0 8 VDDQandInterface Standard of this Assembly SSTL25V 04 9 _ SDRAM Cycle Time at CAS Latency 2 5 6ns 11 DIMM configuration type non parity Parity Non ECC 1 00 13 JPrimryDDRSDRAMWidth O Y x8 08 14 EmorCheckng DDR SDRAM Width l 00 Min Clock Delay for Back to CAS Latency supported OC CS Latency 0 CLK WE Latency 1 CLK Registered address amp control inputs and on card DLL 18 19 20 NO NO DDR SDRAM Module Attributes gt gt A NIN O
11. fference between the input level on CK and the input level on CK 4 These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ 5 The value of VIX is expected to equal 0 5 VDDQ of the transmitting device and must track variations in the dc level of the same Transcend Information Inc 5 184PIN DDR333 Unbuffered DIMM TS64M LD64V3F5 512MB With 32Mx8 CL2 5 DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Symbo Operating current One bank Active Precharge tRC tRCmin tCK tCK min DQ DM and DQS inputs changing twice per clock cycle Address and control inputs changing once per clock cycle 3 1160 3 gt Operating current One bank Active Read Precharge Burst 2 tRC tRC min CL 2 5 tCK tCK min VIN VREF fro DQ DQS and DM IDD1 1400 mA Percharge power down standby current All banks idle power down mode lt tCK tCK min VIN VREF for DQ DQS and DM Precharge Floating standby current CS gt VIH min All banks idle gt VIH min tCK 166Mhz for DDR333 Address and other control inputs changing once per clock cycle VIN VREF for DQ DQS and DM IDD2P 48 3 gt IDD2F 400 ES gt Active power down standby current one bank active power
12. ta and DQS input output capacitance 000 0063 Input capacitance DMO DM7 Transcend Information Inc 7 184PIN DDR333 Unbuffered DIMM TS64M LD64V3F5 512MB With 32Mx8 CL2 5 AC Timming Parameters amp Specifications These AC characteristics were tested on the Component Parameter Symbol Min Max Row cycle time tRC 60 X J nm Refresh row cycle time RFC __72__ 0h n Row active time 70K n RAS to CAS delay tRCD 18 n Row active to Row active delay RP 18 n Row active to Row active delay tRRD 12 n Write recovery time WR 15 X ns ast data in to Read command WIR 1 tCK Col Address to Col Address delay om tCK Clock cycle time tek 6 A Clock high level width tCK Clock low level width tCK DQS out access time from CK CK t DQSCK 06 06 n Output data access time from CK CK 0 7 n Data strobe edge to output data edge 0950 045 ns Read Preamble tRPRE 09 141 t Read Postamble tRPST 04 O06 tCK CK to valid DQS in 1 25 tCK DQS in setup time WPRES 0 Xa X ms DQS in hold time WPREH 025 DQS falling edge to CK rising setup time 055 02 tCK DQS falling edge from CK rising hold time tDSH 02 tCK DQS in high level width tbQSH 0 35 t DQS in low level width tbQSL 0 35 DQS in cycle time tSC 09 141 J tCK Address and
Download Pdf Manuals
Related Search