Transcend 128MB SDRAM PC133 Unbuffer Non-ECC Memory
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1. 168PIN PC133 Unbuffered DIMM TS16MLS64V6C 128MB with 8Mx16 CL3 Block Diagram 7 A0 A11 A0 A11 AO A11 A0 A11 HORT BADEN BAO BA1 BAO BA1 BAO BA1 BA0 BA1 DQ0 DQ63 DQ0 DQ15 DQ0 DQ15 Oa ea m DQ0 DQ15 IRAS s IRAS _ RAS a aMxi6 _ 8Mx16 8Mx16 ICAS ICAS LCAS E SDRAM SDRAM SDRAM MWE MWE _ WE E pea Eies ii ble ae ie CLKO clk 2 8 CLK 263 Q Q CKEO cke 9 5 cke 85 Dame DQM7 DQM2 DQM3 K ESNE CLK2 A0 A11 A0 A11 A0 A11 BA0 BA1 BA0 BA1 BA0 BA1 DQ0 DQ15 DQ0 DQ15 DQ0 DQ15 DQ0 DQ15 IRAS eas 8Mx16 8Mx16 SDRAM SDRAM MWE ICS1 ICS CLK1 CLK 5 CKE1 CKE 2 DQM4 DQM5 DQM6 DQMO DQM1 DQM2 ICS3 CLK3 SDA AO A1 A2 SA0 SA1 SA2 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend information Inc 4 TS16MLS64V6C ABSOLUTE MAXIMUM RATINGS 168PIN PC133 Unbuffered DIMM 128MB with 8Mx16 CL3 Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 1 0 4 6 V Voltage on VDD supply to Vss VDD VDDQ 1 0 4 6 V Storage temperature TSTG 55 150 C Power dissipation PD 8 W Short circuit current los 50 mA Mean time between failur2. Stop Bank Selection Precharge Both Banks Clock Suspend or Active Power Down Precharge Power Down Mode No Operation Command a a Valid X Don t Care H Logic High L Logic Low Note 1 OP Code Operand Code Ao A11 BAo BA1 Program keys MRS 2 MRS can be issued only at both banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at both banks precharge state 4 BAo BA1 Bank select address If both BAo and BA1 are Low at read write row active and precharge bank A is selected If both BAo is Low and BA1 is High at read write row active and precharge bank B is selected If both BAo is High and BA1 is Low at read write row active and precharge bank C is selected If both BAo and BA1 are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAo and BA are ignored and both banks are selected 5 During burst read or write with auto precharge new read write command can not be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst Burst stop command is valid at every burst length 7 DQM sampled at positive going edged
3. 01 21 SDRAM Module Attributes Non Buffer 00 22 SDRAM Device Attributes General Prec All Auto Prec R W OE Burst 23 SDRAM Cycle Time 2 highest CL 10ns AO 24 SDRAM Access from Clock 2 highest CL 6ns 60 25 SDRAM Cycle Time 3 highest CL 0 00 26 SDRAM Access from Clock 3 highest CL 0 00 27 Minimum Row Precharge Time 20 14 28 Minimum Row Active to Row Activate 15 OF 29 Minimum RAS to CAS Delay 20 14 30 Minimum RAS Pulse Width 45 2D 31 Density of Each Bank on Module 64MB 10 32 Command Address Setup Time 1 5ns 15 33 Command Address Hold Time 0 8ns 08 34 Data Signal Setup Time 1 5ns 15 35 Data Signal Hold Time 0 8ns 08 36 61 Superset Information 00 62 SPD Data Revision Code JEDEC2 02 63 Checksum for Bytes 0 62 97 97 64 71 Manufacturers JEDEC ID Code per JEP 108E Transcend TF 4F 72 Manufacturing Location T 54 54 53 31 36 4D 4C 73 90 Manufacturers Part Number TS16MLS64V6C 53 36 34 56 36 43 20 20 20 20 20 20 91 92 Revision Code 0 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number By Manufacturer Variable Transcend information Inc 10 TS1 6M LS64V6C 168PIN PC133 Unbuffered DIMM 128MB with 8Mx16 CL3 99 125 Manufacturer Specific Data 0 126 Intel Specification Frequency 100MHz 64 127 Intel Specification CAS Latency Clock Signal Support CL 28 amp 3 Clock 0 3 F6 128 Unused Storage Locations Open FF Transcend i
4. Masking Read Write Serial Presence Detect SPD with serial EEPROM LVTTL compatible inputs and outputs PCB 09 7130 Single 3 3V 0 3V power supply e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Scramble Sequential amp Interleave All inputs are sampled at the positive going edge of the system clock Transcend information Inc 1 TS16MLS64V6C Dimensions Side Millimeters 133 35 0 40 65 67 23 49 8 89 3 00 31 75 0 20 19 80 15 80 l 1 27 0 10 I O n m o O w Refer Placement Inches 5 250 0 016 2 585 0 925 0 350 0 118 1 250 0 008 0 788 0 622 0 050 0 004 Transcend information Inc 168PIN PC133 Unbuffered DIMM 128MB with 8Mx16 CL3 Pin Identification Symbol Function A0 A11 Address inputs BAO BA1 Select Bank DQ0 DQ63 data inputs outputs CLKO CLK2 Clock Input CKEO Clock Enable Input CS0 CS2 Chip Select Input IRAS Row address strobe ICAS Column address strobe INWE Write Enable DQMO 7 DQM Vcc Power Supply Vss Ground SDA Serial Address Data I O SA0 2 Address in EEPROM WP Write protection SCL Serial Clock NC No Connection 168PIN PC133 Unbuffered DIMM TS16MLS64V6C 128MB with 8Mx16 CL3 Pinouts Name Vss DQO DQ1 DQ2 DQ3 DQ4 A10 AP 80 BA1 Vcc Vcc CLKO Please refer Block Diagram Transcend information Inc 3
5. O CS3 CIN5 10 13 pF Input capacitance DQM0 DQM7 CIN6 10 15 pF Data input output capacitance DQ0 DQ63 COUT 13 18 pF Transcend information Inc 5 TS16MLS64V6C DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C 168PIN PC133 Unbuffered DIMM 128MB with 8Mx16 CL3 Parameter Symbol Test Condition CAS Latency Value Unit Note Operating Current Burst Length 1 Icc1 52 A 1 One Bank Active tRc gt tRc min i loL OmA Precharge Standby Current Icc2P CKE lt VIL max tcc 15ns 16 mA in power down mode Icc2PS CKE amp CLK lt VIL max tcc lt 16 Icc2N CKE2ViIH min CS2ViIH min tcc 15ns 160 Precharge Standby Current Input signals are changed one time during 30ns mA in non power down mode icc2NS_ CKE gt VIH min CLK lt ViL max tcc 80 Input signals are stable Active Standby Current Icc3P CKE lt ViL max tcc 15ns 40 mA in power down mode Icc3PS ICKE amp CLK lt VIL max tcc lt 40 Icc3N ta Active Standby Current CKEVininin tOS gt MIND toc dens SiG Input signals are changed one time during 30ns in non power down mode he PIK ACUE lec3NS OKE gt ViH min CLK lt ViL max tcc mis Input signals are stable 200 Operating Current Icc4 uate see sgo 1 mA BUSE ede tecp 2CLKs Refresh Current ICCc5 tRc tRC min 920 mA 2 Self Refresh Current ICC6 CKE lt 0 2V 7 7 mA Note Module IDD was calculate
6. TS16MLS64V6C rN PAM wt tte CLS Description Placement The TS16MLS64V6C is a 16M x 64 bits Synchronous Dynamic RAM high density for PC 133 The TS16MLS64VEC consists of 8pcs CMOS 8Mx16 bits Synchronous DRAMs in TSOP II 400mil packages and a 2048 bits serial EEPROM on a 168 pin printed circuit board The TS16MLS64V6EC is a Dual In Line Memory Module and is intended for mounting into 168 pin edge ANnNAANAANANNANNANAANAnAAAN AOONHOANAANAANAANNNANAAANA TIT NOLLAAN NOLE ONELA TIT TIOCOTOOOTOOOOooo nann ANNNMNANAANAANANANNANAAAAA THOUIO0OU0T WOU DOUUUUUUUUUUUUUU TUUU UUU connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies DODANANAONANNNOONANANNANANN DODOONANNONANANNNNANNNANNNN programmable latencies allow the same device to be useful for a variety of high bandwidth high performance TIT NOLLAAN ELOLE MONOLL TIT LON NOUNOU LOOL O EE EER memory system applications ANAnANANNANNANNANNANAAANAN INONONANNANNAANANAANAANANA TTT OO OOTOOTOOoooo TOTO OOOO TT ACoA ALm Features E e Performance Range PC 133 O D 1 e Conformed to JEDEC Standard Spec a _ t e Burst Mode Operation H I gt e Auto and Self Refresh _C e CKE Power Down Mode e DQM Byte
7. d on the basis of component IDD and can be differently measured according to DQ loading cap Transcend information Inc 168PIN PC133 Unbuffered DIMM TS16MLS64V6C 128MB with 8Mx16 CL3 AC OPERATING TEST CONDITIONS voo 3 3V 0 3V TA 0 to 70 C Parameter ae AC Input levels VIH VIL 2 4 0 4 oO Vtt 1 4V 1200 Ohm 50 Ohm Output gt Von DC 2 4V lon 2mA Output Z0 50 Ohm Vou DC 0 4V lo 2mA 50pF sopF 71117 ZIT TTT es Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit 870 Ohm OPERATING AC PARAMETER AC operating conditions unless otherwise noted Parameter Symbol Value Unit Note Row active to row active delay tRRD min 15 ns 1 RAS to CAS delay tRCD min 20 ns 1 Row precharge time tRP min 20 ns 1 Row active time tees ult n ns l tRAS max 100 us Row cycle time tRC min 65 ns 1 Last data in to row precharge tRDL min 2 CLK 2 Last data in to Active delay tDAL min 2CLK tRP Last data in to new col address delay tCDL min 1 CLK 2 Last data in to burst stop tBDL min 1 CLK 2 Col address to col address delay tccD min 1 CLK 3 Number of valid output data CAS latency 3 2 ea 4 Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete wr
8. e MTBF 50 year Temperature Humidity Burning THB 85 C 85 Static Stress C Temperature Cycling Test TC 0 C 125 C Cycling C Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C Parameter Symbol Min Typ Max Unit Note Supply voltage VDD 3 0 3 3 3 6 V Input high voltage VIH 2 0 3 0 VDD 0 3 V 1 Input low voltage VIL 0 3 0 0 8 V 2 Output high voltage VOH 2 4 V IOH 2mA Output low voltage VOL 0 4 V IOL 2mA Input leakage current Inputs HL 8 8 uA 3 Note 1 VIH max 5 6V AC The overshoot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt VIN lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri State outputs CAPACITANCE TA 25 C f 1MHz Parameter Symbol Min Max Unit Input capacitance Ao A11 BAo BA CIN1 25 45 pF Input capacitance RAS CAS WE CIN2 25 45 pF Input capacitance CKEO CKE 1 CIN3 15 25 pF Input capacitance CLKO CLK3 CIN4 10 15 pF Input capacitance CS
9. ite 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop Transcend information Inc 7 TS1 6M _LS64V6C 168PIN PC133 Unbuffered DIMM 128MB with 8Mx16 CL3 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module a pro Tene a CLK high pulse width tcH Oef CLK low pulse width a nput setup time nput hold time CLK to output in Low Z e CLK to output 7 Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf 1ns If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter ns ns ns ns ns ns ns ns ns Transcend information Inc 8 168PIN PC133 Unbuffered DIMM TS16MLS64V6C 128MB with 8Mx16 CL3 SIMPLIFIED TRUTH TABLE ee CKEn 1 mas icas we vam Baoa awar E Register Mode Register Set Mode Registers H x v fe AE OP CODE Auto EFN Refresh Self Refresh Bank Active amp Row Adar o Active amp Row Addr Read amp Auto Precharge Disable Column Address Column Address Auto Precharge Enable Ao As Write amp Auto Precharge Disable Column Address Column Address Auto Precharge Enable Ao As Burst
10. nformation Inc 11
11. of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 O Transcend information Inc 9 TS16MLS64V6C Serial Presence Detect Specification 168PIN PC133 Unbuffered DIMM 128MB with 8Mx16 CL3 Serial Presence Detect Byte No Function Described Standard Specification Vendor Part 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 of Row Addresses on this Assembly AO A11 oC 4 of Column Addresses on this Assembly A0 A8 09 5 of Module Banks on this Assembly 2 bank 02 6 Data Width of this Assembly 64bits 40 7 Data Width Continuation 0 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM Cycle Time highest CAS latency 7 5ns 75 10 SDRAM Access from Clock highest CL 5 4ns 54 11 DIMM configuration type non parity ECC None 00 12 Refresh Rate Type 15 625us Self Refresh 80 13 Primary SDRAM Width X16 10 14 Error Checking SDRAM Width 64bit 00 15 Min Clock Delay Back to Back Random Address 1 clock 01 16 Burst Lengths Supported 1 2 4 8 amp Full page 8F 17 Number of banks on each SDRAM device 4 bank 04 18 CAS Latency 2 amp 3 06 19 CS Latency 0 clock 01 20 Write Latency 0 clock
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