Transcend 64MB SDRAM PC133 Unbuffer Non-ECC Memory
Contents
1. High at row precharge BAo and BAi are ignored and both banks are selected 5 During burst read or write with auto precharge new read write command cannot be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst 6 Burst stop command is valid at every burst length 7 DQM sampled at positive going edged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 Transcend Information Inc 9 TS8MLS64V6C Serial Presence Detect Specification 168 Pin PC133 Unbuffered DIMM 64MB With 8Mx16 CL3 Serial Presence Detect Byte No Function Described Sian g a Vendor Part Specification 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 of Row Addresses on this Assembly AO A11 OC 4 of Column Addresses on this Assembly A0 A8 09 5 of Module Banks on this Assembly 1 bank 01 6 Data Width of this Assembly 64bits 40 7 Data Width Continuation 0 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM Cycle Time highest CAS latency 7 5ns 75 10 SDRAM Access from Clock highest CL 5 4ns 52. in to new col address delay tCDL min 1 CLK 2 Last data in to burst stop tBDL min 1 CLK 2 Col address to col address delay tCCD min 1 CLK 3 Number of valid es ae ea 4 output data z 7 Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop Transcend Information Inc 7 168 Pin PC133 Unbuffered DIMM TS8M LS64V6C 64MB With 8Mx16 CL3 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module Parameter Symbol ee eee tcc 1000 ns CLK cycle time CLK to valid tSAC output delay Output data tOH hold time LK high pulse width tCH 5 ns LK low pulse width tCL ns nput setup time tss i ns nput hold time tSH ns LK to output in Low Z ns CLK to output tSHZ 5A ns Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than 1ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf Ins If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend Information Inc 8 168 Pin PC133 U
3. time during 30ns in non power down mode Bank Acti fone BanieOcive Icc3NS_ CKE gt ViH min CLK lt ViL max tcc Input signals are stable IOL 0 mA Operating Current Bust Mode Page Burst tccp 2CLKs C Self Refresh Current ICC6 CKE lt 0 2V mA L 3 2 Note 1 Measured with outputs open 2 Refresh period is 64ms 3 Unless otherwise noticed input swing is CMOS VIH VIL VDDOQ VSSQ Transcend Information Inc 6 168 Pin PC133 Unbuffered DIMM TS8M LS64V6C 64MB With 8Mx16 CL3 AC OPERATING TEST CONDITIONS Vpp 3 3V 0 3V TA 0 to 70 C Parameter AC Input levels VIH VIL Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition 3 3V Vit 1 4V oO 1200 Ohm 50 Ohm gt Vox DC 2 4V loH 2MA Output O _Z0 50 Ohm Va DC 0 4V lo 2mA 50pF 50pF 870 Ohm P TT Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit OPERATING AC PARAMETER AC operating conditions unless otherwise noted Parameter Symbol Value Unit Note Row active to row active delay tRRD min 15 ns 1 RAS to CAS delay tRCD min 20 ns 1 Row precharge time tRP min 20 ns 1 Row active time atl 23 1 tRAS max 100 us Row cycle time tRC min 65 ns 1 Last data in to row precharge tRDL min 2 CLK 2 Last data in to Active delay tDAL min 2CLK tRP Last data
4. 155 156 157 158 159 160 161 162 163 164 165 166 167 168 64MB With 8Mx16 CL3 Name Vss CKEO CS3 DQM6 DQM7 A13 Transcend Information Inc TS8MLS64V6C Block Diagram 168 Pin PC133 Unbuffered DIMM 64MB With 8Mx16 CL3 ICSO ICS CS D D DMO WS m DM1 WN wy DQ 32 w 1 00 DQ 4 WA 1 00 DQ 33 WS 1 0 1 DQ 41 W 101 DQ 34 SWS 10 2 DQ 42 W 1 02 cae Ww 9 3 DI BN 193 39 W 04 wn 1 104 DQ 38 WY 105 DQ 46 WW T 0 5 DQ 37 WY 106 DQ45 W 1 06 BQ36 WY 07 U DQ4 WN4 107 U 3 D D pm wy P DMS WY xy DQ7 WS 1 08 DQ 15 W 108 DQ6 WS 1109 DO BOW 109 DQ 5 WS 1 010 DQ 13 W716 10 DQ 4 WS 1 011 DQ RWS 1011 DQ0 SWS 1012 DQ 8 W710 12 DQ1 WS 10 13 DQ 9M WS 110 13 DOs WA TON BS POA 10 14 DQ3 WS 11015 WT 110 15 CS2 T ICS ICS D D DM2 W4 y DM3 WY y D5 w voo wr 100 DO 50 1 01 PSS AN I O 1 DQ 49 W 1 02 DO 58s 7w 1 02 TEMPS PEN 15 D53 WA 105 BO BANA 105 DQ54 w 106 D 61 w 106 DQ 55 WY 1 07 U DO 60 w 107 U 2 4 D D DM6 WH Mm DM7 WN mMm 19 w 1 08 DQ 24 108 RENN V09 DQ 25 w 1 09 DO 17 w 1 0 10 DQ 26 Ww 1 0 10 DO 16 1 0 11 DQ 27 WA 1 0 11 DQ w 10 12 DQ 31 w 1 0 12 BA IB PEN R BO RW 10 15 BO 38 WA VO 15 AO A12 BAO amp 1 UL U4 EEPROM RAS ________ U1 U4 SCL ICAS ________ U1 U4 gt w we i gt SDA WE 5 U1 U4 4
5. 168 Pin PC133 Unbuffered DIMM TS8M LS64V6C 64MB With 8Mx16 CL3 Description Placement The TS8MLS64VEC is an 8M bit x 64 Synchronous Dynamic RAM high density for PC 133 The O TS8MLS64V6C consists of 4pcs CMOS 8Mx16 bits Synchronous DRAMs in TSOP II 400mil packages and a 2048 bits serial EEPROM on a 168 pin printed circuit board The TS8MLS64V6EC is a Dual In Line Memory Module and is intended for mounting into 168 pin edge jnnnnnnnnnnnnnnnnnnnnnnnnnn UOUOUO0OTOUOOTUOUOOOoUo jgnnnnnnnnnnnnnnnnnnnnnnnnn UOUOUOUOCUOOTUOUOUOOUo connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies INONONONAAAANAAAANAAAANAANLL programmable latencies allow the same device to be useful for a variety of h igh bandwidth h igh NL ALANA nannan performance memory system applications NOUOUCOOOUOUO0OTOUOOOoooo ITI Aoi onion Features e RoHS Production compliant e Performance Range PC 133 poe ear e Conformed to JEDEC Standard Spec 7S e Burst Mode Operation e Auto and Self Refresh e CKE Power Down Mode e DQM Byte Masking Read Write e Serial Presence Detect SPD with serial EEPROM e LVTTL compatible inputs and outputs PCB 09 7132 e Single 3 3V 0 3V power supply e MR
6. 4 11 DIMM configuration type non parity ECC None 00 12 Refresh Rate Type 15 625us Self Refresh 80 13 Primary SDRAM Width X16 10 14 Error Checking SDRAM Width None 00 15 Min Clock Delay Back to Back Random Address 1 clock 01 16 Burst Lengths Supported 1 2 4 8 amp Full page 8F 17 Number of banks on each SDRAM device 4 bank 04 18 CAS Latency 3 04 19 CS Latency 0 clock 01 20 Write Latency 0 clock 01 21 SDRAM Module Attributes Non Buffer 00 22 SDRAM Device Attributes General Prec All Auto Prec OE R W Burst 23 SDRAM Cycle Time 2 highest CL 0 00 24 SDRAM Access from Clock 2 highest CL 0 00 25 SDRAM Cycle Time 3 highest CL 0 00 26 SDRAM Access from Clock 3 highest CL 0 00 27 Minimum Row Precharge Time 20ns 14 28 Minimum Row Active to Row Activate 15ns OF 29 Minimum RAS to CAS Delay 20ns 14 30 Minimum RAS Pulse Width 45ns 2D 31 Density of Each Bank on Module 64MB 10 32 Command Address Setup Time 1 5ns 15 33 Command Address Hold Time 0 8ns 08 34 Data Signal Setup Time 1 5ns 15 35 Data Signal Hold Time 0 8ns 08 36 61 Superset Information 00 62 SPD Data Revision Code JEDEC 2 02 63 Checksum for Bytes 0 62 94 94 64 71 Manufacturers JEDEC ID Code per JEP 108E Transcend 7F 4F 72 Manufacturing Location T 54 73 90 Manufacturers Part Number TS8MLS64V6C 54 53 38 4D 4C 53 36 34 56 36 43 20 20 20 20 20 20 20 91 92 Revision Code 0 Transcend Information Inc 10 168 Pin PC133 Unbuffer
7. 70 Ohms AO Al A2 CKEQ U U4 J od SAO SAI SA2 DQn 10 OBIS Ose DQpin of SDRAM VDD gt Ul U4 UI1 U3 10 Ohms has O1uF 01uF CK0 2 CK1 3 i U2 U4 AIOT VSS gt Ul U4 7 15pF P Tt ZN This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend Information Inc 168 Pin PC133 Unbuffered DIMM TS8M LS64V6C 64MB With 8Mx16 CL3 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Vawe nit Voltage on any pin relative to Vss 1 0 4 6 Voltage on VDD supply to Vss 1 0 4 6 Storage temperature Power dissipation Pa i Short circuit current Operating Temperature TA 0 70 C Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss OV TA 0 to 70 C Supply voltage Input high voltage i Input low voltage w 03 o 08g v v Output high voltage ne ee N E Output low voltage Note 1
8. S cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Sequence Sequential amp Interleave e All inputs are sampled at the positive going edge of the system clock Transcend Information Inc 1 TS8MLS64V6C 168 Pin PC133 Unbuffered DIMM 64MB With 8Mx16 CL3 Dimensions Pin Identification Side _Millimeters Inches Symbol DAA B 65 67 2 585 DQ0 DQ63 Data Input Output G 23 49 0 925 D 8 89 0 350 CLKO CLK2 Clock Input E 3 00 0 118 CKEO Clock Enable Input F 31 75 0 20 1 25040 008 CSO CS2 Chip Select Input G 19 80 0 788 H 15 80 0 622 RAS Row Address Strobe 1272010 0 050 0 004 CAS Column Address Strobe Refer Placement WE Write Enable DQM0 DQM7 Data DQ Mask SA0 SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output Vcc 3 3 Voltage Power Supply Vss Ground NC No Connection Transcend Information Inc TS8MLS64V6C Pinouts Name No Name Vss DQO DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 DQ8 Vss DQ9 DQ10 DQ11 DQ12 DQ13 Vcc DQ14 DQ15 A10 AP 80 BA1 Vcc Vcc CLKO Please refer Block Diagram Name Vss DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 DQ40 Vss DQ41 DQ42 DQ43 DQ44 DQ45 Vcc DQ46 DQ47 CB4 CB5 168 Pin PC133 Unbuffered DIMM Pin 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154
9. VIH max 5 6V AC The overshoot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt VIN lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri State outputs CAPACITANCE Vpp 3V TA 23 C f 1MHz VREF 1 4 200mV Parameter Input capacitance Ao A11 BAo BA1 Input capacitance RAS CAS WE Input capacitance CKEO Input capacitance CLKO CLK2 Input capacitance CSO CS2 Input capacitance DQM0 DQM7 Data input output capacitance DQ0 DQ63 Transcend Information Inc 5 168 Pin PC133 Unbuffered DIMM TS8M LS64V6C 64MB With 8Mx16 CL3 DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Parameter Symbol Test Condition Operating Current Burst Length 1 tRC tRC min One Bank Active Pareconak Precharge Standby Current locaP _ CKE lt viimany tcc 10ns in power down mode Icc2ePS CKE amp CLK lt ViL max tcc CKE ViH min CS gt VIH min tcc 10ns Icc2N Input signals are changed one time during 30ns Precharge Standby Current in non power down mode CKE ViH min CLK lt ViL max tec Icc2NS Input signals a stable Active Standby Current locaP_ oKE lt viimaxy tcc 10ns in power down mode IccsPS_ CKE amp CLK lt ViIL max tCC Icc3N CKE2ViH min CS gt ViH min tcc 10ns Active Standby Current Input signals are changed one
10. ed DIMM TS8M LS64V6C 64MB With 8Mx16 CL3 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number By Manufacturer Variable 99 125 Manufacturer Specific Data 0 126 Intel Specification Frequency 100MHz 64 127 _ Intel Specification CAS Latency Clock Signal Support CL 2 amp 3 Clock 0 2 C6 128 Unused Storage Locations Open FF Transcend Information Inc 11
11. nbuffered DIMM TS8M LS64V6C 64MB With 8Mx16 CL3 SIMPLIFIED TRUTH TABLE V Valid X Don t Care H Logic High L Logic Low COMMAND exert oxen es mas icas we vam Baos amar ATS not Pes err eee beta aectrtaie row Refresh Auto Refresh si Refresh Sel E ae es PEE et Read amp Auto Auto Precharge Disable Disable E Ea L H L H X V Column Address Se Precharge Enable Write amp Auto Precharge Disable L H L L X V Column column Address Auto Auto Precharge Enable Enable ony 0 A8 x L H L H H Ox XX Se X x E Both Banks xX H ha X No Operation Command PE a Note 1 OP Code Operand Code Ao A11 BAo BA1 Program keys MRS 2 MRS can be issued only at both banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at both banks precharge state 4 BAo BA1 Bank select address If both BAo and BA1 are Low at read write row active and precharge bank A is selected If both BAo is Low and BA1 is High at read write row active and precharge bank B is selected If both BAo is High and BA1 is Low at read write row active and precharge bank C is selected If both BAo and BA1 are High at read write row active and precharge bank D is selected If A1o AP is
Download Pdf Manuals
Related Search