Transcend JetRam 128MB SDRAM 168pin DIMM
Contents
1. 59 Vcc 101 DQ45 143 Vcc 18 Vcc 60 DQ20 102 Vcc 144 DQ52 19 0014 61 103 0046 145 NC 20 DQ15 62 NC 104 DQ47 146 NC 21 NC 63 NC 105 NC 147 NC 22 NC 64 Vss 106 NC 148 Vss 23 Vss 65 0021 107 Vss 149 0053 24 66 0022 108 150 0054 25 67 0023 109 151 0055 26 Vcc 68 Vss 110 Vcc 152 Vss 27 AVE 69 DQ24 111 CAS 153 DQ56 28 DQMO 70 DQ25 112 4 154 0057 29 DQM1 71 DQ26 113 5 155 0058 30 CSO 72 DQ27 114 NC 156 DQ59 31 NC 73 Vcc 115 RAS 157 Vcc 32 Vss 74 DQ28 116 Vss 158 DQ60 33 75 0029 117 A1 159 0961 34 A2 76 0030 118 160 0062 35 4 77 0031 119 5 161 0063 36 78 Vss 120 A7 162 Vss 37 A8 79 CLK2 121 A9 163 NC 38 A10 80 NC 122 BAO 164 NC 39 BA1 81 NC 123 11 165 40 Vcc 82 SDA 124 Vcc 166 SA1 41 Vcc 83 SCL 125 167 5 2 42 CLKO 84 Vcc 126 NC 168 Vcc Transcend Information Inc 3 128MB 168Pin PC133 CL3 JM31 7S643A 75 SDRAM DIMM With 16Mx8 3 3VOLT JM317S643A 75 Block Diagram 0 11 0 11 E RAS RAS CAS WE ICSO CKEO ICS2 0 11 DQ0 DQ7 SDRAM CLKO CLK2 Serial EEPROM A0 A1 A2 SA0 SA1S 2 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assumes no liability in connection with the use of this product Transcend reserves the right to make ch2. Input singals are changed one time during 30ns 240 Active Standby Current in non power down mode One Bank Active CKE ViH min CLK lt VIL max mA ICC3NS Input singals are stable 160 loL 0 mA Operating Current Page Burst 4 600 1 2CLKs Refresh Current 5 tRC gt tRC min 1160 mA 2 Self Refresh Current 6 lt 0 2 16 mA Note 1 Measured with outputs open 2 Refresh period is 64ms 3 Unless otherwise noticed input swing level is CMOS ViH ViLZVDDQ VSSQ Transcend Information Inc 7 128MB 168Pin PC133 CL3 JM31 7S643A 75 SDRAM DIMM With 16Mx8 3 3VOLT OPERATING TEST CONDITIONS von 3 3V 0 3V 0 to 70 Parameter Value Unit AC Input levels ViH VIL 2 4 0 4 V Input timing measurement reference level 1 4 V Input rise and fall time tr tf 1 1 ns Output timing measurement reference level 1 4 V Output load condition See Fig 2 qe o PAM 1200 Ohm 50 Ohm gt Vou DC 2 4V 2 Output O 20 50 0hm 9 Vot DC 0 4V lo 2mA 5 LL 870 Ohm e 777 WW UH Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit OPERATING AC PARAMETER operating conditions unless otherwise noted Parameter Symbol Value Unit Note Row active to row active delay tRRD min 15 ns 1 RAS to CAS delay tRCD min 20
3. ns 1 Row precharge time tRP min 20 ns 1 Row active time ns tRAS max 100 us Row cycle time tRC min 65 ns 1 Last data in to new col address delay tCDL min 1 CLK 2 Last data in to row precharge tRDL min 2 CLK 2 Last data in to burst stop tBDL min 1 CLK 2 Col address to col address delay 1 CLK 3 Number of valid CAS latency 3 2 4 output data Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 case of row precharge interrupt auto precharge and read burst stop Transcend Information Inc 8 128MB 168Pin PC133 CL3 JM31 7S643A 75 SDRAM DIMM With 16Mx8 3 3VOLT AC CHARACTERISTICS operating conditions unless otherwise noted Refer to the individual component not the whole module Parameter Symbol value Min Valure Max Unit Note CLK cycle time tcc 7 5 1000 ns 1 CLK to valid output delay tSAC 5 4 ns 1 2 Output data hold time toH 3 0 ns 2 CLK high pulse width tCH 2 5 ns 3 CLK low pulse width 2 5 ns 3 Input setup time 155 1 5 ns 3 Input hold time tSH 0 8 ns 3 CLK to output in Low Z 1512 1 ns 2 CLK to output ie ae FN 5 4 in Hi Z Note 1 Parameters depend on programmed CAS
4. 128MB 168Pin PC133 CL3 JM31 7S643A 75 SDRAM DIMM With 16Mx8 3 3VOLT Description Placement The JM317S643A 75 is a 16M bit x 64 Synchronous Dynamic RAM high density for PC 133 The Ah JM317S643A 75 consists of 8pcs CMOS 16 8 bits Synchronous DRAMs in TSOP II 400mil packages and a 2048 bits serial EEPROM on a 168 pin printed circuit board The JM317S643A 75 is a Dual In Line Memory Module and is intended for mounting into 168 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock transactions are possible on every clock cycle Range of operation frequencies programmable latencies allows the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Performance Range 133 Conformed to JEDEC Standard 4 clocks Burst Mode Operation Auto and Self Refresh CKE Power Down Mode DQM Byte Masking Read Write e Serial Presence Detect SPD with serial EEPROM Rr e LVTTL compatible inputs and outputs Single 3 3V 0 3V power supply MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Sequence Sequential amp Interleave PCB 09 7303 All inputs are sampled at the positive going edge of System clock Transcend Information Inc 1 JM317S643A 75 128MB 168Pin PC133 CL3 SDRAM DIMM With
5. 16Mx8 3 3VOLT Dimensions Pin Identification Side Millimeters Inches Symbol Function A 133 35 0 40 5 250 0 016 0 11 0 1 Address input B 65 67 2 585 DQ0 DQ63 Data Input Output C 23 49 0 925 D 8 89 0 350 CLKO CLK2 Clock Input E 3 00 0 118 CKEO Clock Enable Input F 29 21 0 20 1 150 0 008 CS0 CS2 Chip Select Input G 19 80 0 788 RAS Row Address Strobe H 15 80 0 622 1 27 0 10 0 050 0 004 CAS Column Address Strobe Refer Placement ANE Write Enable DQM0 DQM7 Data DQ Mask SA0 SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output Vcc 3 3 Voltage Power Supply Vss Ground NC No Connection Refer Block Diagram AND Pinouts Transcend Information Inc 128MB 168Pin PC133 CL3 JM31 7S643A 75 SDRAM DIMM With 16Mx8 3 3VOLT Pinouts Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name 01 Vss 43 Vss 85 Vss 127 Vss 02 DQO 44 NC 86 DQ32 128 CKEO 03 001 45 CS2 87 0033 129 NC 04 002 46 DQM2 88 DQ34 130 DQM6 05 DQ3 47 DQM3 89 DQ35 131 DQM7 06 Vcc 48 NC 90 Vcc 132 NC 07 DQ4 49 Vcc 91 0036 133 Vcc 08 005 50 92 0037 134 NC 09 DQ6 51 NC 93 DQ38 135 NC 10 DQ7 52 NC 94 DQ39 136 NC 11 008 53 95 0040 137 12 Vss 54 Vss 96 Vss 138 Vss 13 DQ9 55 DQ16 97 DQ41 139 0048 14 DQ10 56 DQ17 98 DQ42 140 DQ49 15 0011 57 0018 99 0043 141 0050 16 0012 58 0019 100 0044 142 0051 17 0013
6. anges in specifications at any time without prior notice Transcend Information Inc 4 JM317S643A 75 ABSOLUTE MAXIMUM RATINGS 128MB 168Pin PC133 CL3 SDRAM DIMM With 16Mx8 3 3VOLT Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 1 0 4 6 V Voltage on VDD supply to Vss VDD VDDQ 1 0 4 6 V Storage temperature TsTG 55 150 Power dissipation PD 8 W Short circuit current los 50 mA Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss OV 0 to 70 C Parameter Symbol Min Type Max Unit Note Supply voltage VDD 3 0 3 3 3 6 V Input high voltage VIH 2 0 3 0 VDD 0 3 V 1 Input low voltage VIL 0 3 0 0 8 V 2 Output high voltage VOH 2 4 V 2 Output low voltage VOL 0 4 V IOL 2mA Input leakage current Inputs 10 10 uA 3 Note 1 max 5 6V AC The overshoot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt VIN lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional buffe
7. ck 27 highest CL 0 00 25 SDRAM Cycle Time 3 highest CL 0 00 26 SDRAM Access from Clock 3 highest CL 0 00 27 Minimum Row Precharge Time 20ns 14 28 Minimum Row Active to Row Activate 15ns OF 29 Minimum RAS to CAS Delay 20ns 14 30 Minimum RAS Pulse Width 45ns 2D 31 Density of Each Bank on Module 128MB 20 32 Command Address Setup Time 1 5ns 15 33 Command Address Hold Time 0 8ns 08 34 Data Signal Setup Time 1 5ns 15 35 Data Signal Hold Time 0 8ns 08 36 61 Information 00 62 SPD Data Revision Code JEDEC2 02 63 Checksum for Bytes 0 62 9D 64 71 Manufacturers ID Dode per 108 Transcend 72 Man Manufacturers ufacturing Location 00 73 90 Number 00 91 92 Revision Code 00 93 94 Manufacturing Date 00 95 98 Assembly Serial Number 00 Transcend Information Inc 11 128MB 168Pin PC133 CL3 JM31 7S643A 75 SDRAM DIMM With 16Mx8 3 3VOLT 99 125 Specific Data 00 126 Intel Specification Frequency 64 127 Specification CAS Latency Clock Signal Support CL 3 Clock 0 3 128 Unused Storage Locations Open FF Transcend Information Inc 12
8. latency 2 clock rising time is longer than 1ns tr 2 0 5 ns should be added to the paremeter 3 Assumed input rise and fall time tr amp tf 1ns If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend Information Inc 9 128MB 168Pin PC133 CL3 JM31 7S643A 75 SDRAM DIMM With 16Mx8 3 3VOLT SIMPLIFIED TRUTH TABLE Register Mode Register Set H X L L L L X OP CODE 1 2 Auto Refresh H H L L L H 3 Entry L 3 Refresh Self L H H H 3 Refresh i etres Exit L H H X X X X X 3 Bank Active amp Row Addr H X L L H H X V Row Adress Auto Precharge Disable L Column 4 Read amp 3 H x x Adress Column Address Auto Precharge Enable H 4 5 i Auto Precharge Disable L Column 4 hine amp 9 H X L H L L V Adress Column Address Auto Precharge Enable H Ao As 4 5 Burst Stop H X H H X X 6 Bank Selection V L Precharge Both Banks H X L H X X H X Clock Suspend or Entry H L 5 5 x X Active Power L V V V X Down Exit L H X X X X X H X X X Entry H L x Precharge Power L H H Down Mode Exit H X X X L H X L V V V DOM H X V X 7 No Operation Command H X X X L H H V Valid X Don t Care H Logic High L Logic Low Transcend I
9. nformation Inc 10 JM317S643A 75 Serial Presence Detect Specification 128MB 168Pin PC133 CL3 SDRAM DIMM With 16Mx8 3 3VOLT Serial Presence Detect Byte No Function Described Standard Vendor Part Specification 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 of Row Addresses on this Assembly 12 0C 4 of Column Addresses on this Assembly 10 0A 5 of Module Banks on this Assembly 1 bank 01 6 Data Width of this Assembly 64615 40 7 Data Width Continuation 0 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM Cycle Time highest CAS latency 7 5ns 75 10 SDRAM Access from Clock highest CL 5 4ns 54 11 DIMM configuration type non parity ECC None 00 15 625us Self 12 Refresh Rate Type Refresh 80 13 Primary SDRAM Width X8 08 14 Error Checking SDRAM Width none 00 15 Min Clock Delay Back to Back Random Address 1 clock 01 16 Burst Lengths Supported 1 2 4 8 amp Full page 8F 17 Number of banks on each SDRAM device 4 bank 04 18 CAS Latency 3 04 19 CS Latency 0 clock 01 20 Write Latency 0 clock 01 21 SDRAM Module Attributes Non Buffer 00 22 SDRAM Device Attributes General Prec All Auto Prec R W Burst 23 SDRAM Cycle Time 27 highest CL 0 00 24 _ Access from Clo
10. rs with Tri State outputs Transcend Information Inc 128MB 168Pin PC133 CL3 JM31 7564 75 SDRAM DIMM With 16Mx8 3 3VOLT CAPACITANCE 25 f 1MHz Parameter Symbol Min Max Unit Input capacitance Ao A11 BAo BA1 CIN1 30 45 pF Input capacitance RAS CAS WE CIN2 30 45 pF Input capacitance CKEO CIN3 30 45 pF Input capacitance CLKO CLK2 CINA 22 30 pF Input capacitance CS0 CS2 CIN5 15 25 pF Input capacitance DQM0 DQM7 CIN6 6 8 pF Data input output capacitance 200 0063 COUT 6 8 pF Transcend Information Inc 6 128MB 168Pin PC133 CL3 JM31 7564 75 SDRAM DIMM With 16Mx8 3 3VOLT DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 Parameter Symbol Test Condition Value Unit Note Operating Current Purst 5 960 mA 1 One Bank Active loL 0mA Precharge Standby Current CC2P CKEsViL max tcc 10ns 8 in power down mode Icc2PS CKE amp CLK lt ViL max tcc lt 8 mA CKE ViH min CS2ViH min tcc 10ns ICC2N Input singals are changed one time during 30ns 160 Precharge Standby Current in non power down mode CKE ViH min lt tcc mA ICC2NS Input singals are stable 56 Active Standby Current Icc3P CKEsViL max tcc 10ns 40 in power down mode IccaPS CKE amp CLKsViL max 40 CKE ViH min CS2ViH min tcc 10ns
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