Transcend 256MB, Jetram, DDR, DIMM,400MHz, CL2
Contents
1. not referenced to a specific voltage level but specify when the device output in no longer driving HZ or begins driving LZ 4 The maximum limit for this parameter is not a device limit The device will operate with a greater value for this parameter but sys tem performance bus turnaround will degrade accordingly 5 The specific requirement is that DQS be valid HIGH LOW or at some point on a valid transition on or before this CK edge A valid transition is defined as monotonic and meeting the input slew rate specifications of the device When no writes were previously in progress on the bus DQS will be transitioning from High Z to logic LOW If a previous write was in progress DQS could be HIGH LOW or transitioning from HIGH to LOW at this time depending on tDQSS 6 A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device 7 For command address input slew rate gt 0 5 V ns 8 For CK amp CK slew rate gt 0 5 V ns 9 These parameters guarantee device timing but they are not necessarily tested on each device They may be guaranteed by device design or tester correlation 10 Slew Rate is measured between VOH ac and VOL 11 Min tCL tCH refers to the smaller of the actual clock low time and the actual clock high time as provided to the device i e this value can be greater than the minimum specification limits for tCL and tCH For example tCL and are 50 of the period less t2. rising setup time tDSS 0 2 DQS falling edge from CK rising hold time tDSH 0 2 tCK DQS in high level width tDQSH 0 35 tCK DQS in low level width tDQSL 0 35 tCK Address and Control input setup time tIS 0 6 ns 7 10 Address and Control input hold time tIH 0 6 ns 7 10 Data out high impedance time from CK CK tHZ 0 6 0 6 ns 3 Data out low impedance time from CK CK tLZ 0 6 0 6 ns 3 Mode register set cycle time tMRD 10 ns DQ amp DM setup time to DQS tDS 0 4 ns DQ amp DM hold time to DQS tDH 0 4 ns DQ amp DM input pulse width tDIPW 1 65 ns 9 Transcend Information Inc 184PIN 004 400 Unbuffered DIMM JM334 D643A 50 256MB With 32Mx8 CL2 5 Control amp Address input pulse width for each input 2 2 ns 9 Refresh interval time tREF 7 8 us 6 Output DQS valid window TQH tHP 0 55 ns 12 Clock half period tHP tCLmin tCHmin ns 11 12 Data hold skew factor tQHS 0 5 ns 12 Auto Precharge write recovery precharge time tDAL ns 14 Exit self refresh to non read command tXSNR 75 ns Exit self refresh to read command tXSRD 10 tCK Note 1 VID is the magnitude of the difference between the input level on CK and the input level on CK 2 The value of VIX is expected to equal 0 5 VDDQ of the transmitting device and must track variations in the dc level of the same 3 tHZ and tLZ transitions occur in the same access time windows as valid data transitions These parameters are
3. 87 DQ58 133 0031 179 0063 42 VSS 88 DQ59 134 CB4 180 VDDQ 43 Al 89 VSS 135 CB5 181 SAO 44 CBO 90 NC 136 VDDQ 182 SAI 45 CB1 91 SDA 137 CKO 183 SA2 46 VDD 92 SCL 138 CKO 184 VDDSPD Please refer Block Diagram Transcend Information Inc 3 184PIN DDR400 Unbuffered DIMM JM334 D643A 50 256MB With 32Mx8 CL2 5 Block Diagram A0 A12 BAO BA1 DQ0 DQ63 000 007 RAS RAS 32MX8 RAS 32MX8 DDR D DDR CAS CAS SDRAM CAS SDRAM CK1 CK1 CKO CKO CK2 CK2 BAO BA1 000 007 RAS Serial EEPROM SCL SCL SDA SDA AO A1 A2 SA1 SA2 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend Information Inc 4 184PIN DDR400 Unbuffered DIMM JM334 D643A 50 256MB With 32Mx8 CL2 5 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 0 5 3 6 V Voltage on VDD supply to Vss VDD VDDQ 1 0 3 6 V Storage temperature TSTG 55 150 C Power dissipation PD 12 Short circuit current los 50 mA Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommend
4. F should be de coupled with an inductance of lt 3nH 2 VTT is not applied directly to the device VTT is a system supply for signal termination resistors is expected to be set equal to VREF and must track variations in the DC level of VREF 3 ViD is the magnitude of the difference between the input level on CK and the input level on CK 4 These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ 5 The value of VIX is expected to equal 0 5 VDDQ of the transmitting device and must track variations in the dc level of the same Transcend Information Inc 5 184PIN 00 400 Unbuffered DIMM JM334 D643A 50 256MB With 32Mx8 CL2 5 DC CHARACTERISTICS Recommended operating condition unless otherwise noted VDD 2 7V TA 10 C Parameter Symbol Max Unit Note Operating current One bank Active Precharge tRC tRCmin DQ DM and DQS inputs changing twice per clock cycle IDDO 840 mA Address and control inputs changing once per clock cycle Operating current One bank operation One bank open Burst 4 Reads refer to the following page for detailed test condition D s Percharge power down standby current All banks idle power down mode CKE lt VIL max VIN VREF for DQ DQS and DM a2 MA Precharge F
5. JM334D643A 50 184PIN DDR400 Unbuffered DIMM 256MB With 32Mx8 CL2 5 Description The JM334D643A 50 is a 32M x 64bits Double Data Rate SDRAM high density for DDR400 The JM334D643A 50 consists of 8pcs CMOS 32Mx8 bits Double Data Rate SDRAMs in 66 pin TSOP II 400mil packages and a 2048 bits serial EEPROM on a 184 pin printed circuit board The JM334D643A 50 is a Dual In Line Memory Module and is intended for mounting into 184 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock Data I O transactions are possible on both edges of DQS Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Power supply VDD 2 6V 0 1V VDDQ 2 6V 0 1V e Max clock Freq 200MHZ e Double data rate architecture two data transfers per clock cycle e Differential clock inputs CK and e DLLaligns DQ and DGS transition with CK transition e Auto and Self Refresh 7 8us refresh interval e Data I O transactions on both edge of data strobe e Edge aligned data output center aligned data e Serial Presence Detect SPD with serial EEPROM e SSTL 2 compatible inputs and outputs e MRS cycle with address key programs CAS Latency Access from column address 2 5 Burst Length 2 4 8 Data Sequence Sequential amp Interleave VETT EET HERE E
6. Precharge Enable oH Ao As Burst Stop X Brech rg Bank Selection H L 9 All Banks DIERERES Active Power Down Fu eiim m a 3EJET EPET Entry B Darna DM x No Operation Command X OP Code Operand Code 0 A12 amp Program keys EMRS MRS EMRS MRS can be issued only at all banks precharge state A new command can be issued 2 clock cycles after EMRS or MRS 1 2 3 Auto refresh functions are same as the CBR refresh of DRAM The automatically precharge without row precharge command is meant 4 Note by Auto Auto self refresh can be issued only at all banks precharge state BA1 Bank select addresses If both BAO and BA1 are Low at read write row active and precharge bank A is selected If both is High and 1 is Low at read write row active and precharge bank is selected If both is Low and 1 is High at read wie Ow active and precharge bank is selected If both BAO and BA1 are High at read write row active and precharge bank is selected If A10 AP is High at row precharge BAO and BA1 are ignored and all banks are selected During burst write with auto precharge new read write command cannot be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst Burst stop command is valid at e
7. TE HAE HT HH HV AANA DODOA OWON OWONU WOON WOON MOMMA AANA DONON OOA OONA WOON MUON MAMME E UJ DONNI MI MAUA CUE ONON OWONU WOOO OOU MOMENI AANA DONON OON OWONU MODU WOON MOMMA o r 4 E PCB 09 2430 Transcend Information Inc JM334D643A 50 184PIN DDR400 Unbuffered DIMM 256MB With 32Mx8 CL2 5 Pin Identification Symbol Function A0 A12 BA1 Address input Dimensions Side Millimeters Inches 133 35 0 20 5 250 0 008 72 39 2 850 6 35 0 250 D 2 20 0 087 E 29 46 0 20 1 160 0 008 19 80 0 800 G 4 00 0 157 H 12 00 0 472 1 27 0 10 0 050 0 004 Refer Placement Transcend Information Inc 0090 0063 Data Input Output DQS0 DQS7 Data strobe input output CKO CKO CK1 CK1 Clock Input 2 CK2 CKEO Clock Enable Input CSO Chip Select Input RAS Row Address Strobe CAS Column Address Strobe ANE Write Enable DMO0 DM7 Data in Mask VDD 2 6 Voltage power supply 2 6 Voltage Power Supply for VDDQ DQS VREF Power Supply for Reference 42 5 Voltage Serial EEPROM VDDSPD Power Supply SA0 SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output VSS Ground NC No Connection 184PIN DDR400 Unbuffer
8. ed DIMM JM334 D643A 50 256MB With 32Mx8 CL2 5 DOR Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name 01 VREF 47 DQS8 93 VSS 139 VSS 02 000 48 94 004 140 DM8 03 VSS 49 CB2 95 DQ5 141 A10 04 001 50 VSS 96 VDDQ 142 CB6 05 DQSO 51 97 DMO 143 VDDQ 06 DQ2 52 BA1 98 DQ6 144 CB7 07 VDD 53 DQ32 99 DQ7 145 VSS 08 DQ3 54 VDDQ 100 VSS 146 DQ36 09 NC 55 DQ33 101 NC 147 0037 10 56 0054 102 NC 148 VDD 11 VSS 57 DQ34 103 NC 149 DM4 12 DQ8 58 VSS 104 VDDQ 150 0038 13 009 59 105 0012 151 0039 14 0051 60 0035 106 0013 152 VSS 15 VDDQ 61 DQ40 107 DM1 153 0044 16 1 62 VDDQ 108 VDD 154 RAS 17 CK1 63 ANE 109 0014 155 0045 18 VSS 64 DQ41 110 0015 156 VDDQ 19 0010 65 CAS 111 CKE1 157 CSO 20 DQ11 66 VSS 112 VDDQ 158 CS1 21 CKEO 67 DQS5 113 NC 159 DM5 22 VDDQ 68 DQ42 114 0020 160 VSS 23 0016 69 0043 115 A12 161 0046 24 0017 70 VDD 116 VSS 162 0047 25 DQS2 71 NC 117 0021 163 NC 26 VSS 72 DQ48 118 11 164 VDDQ 27 A9 73 DQ49 119 DM2 165 DQ52 28 DQ18 74 VSS 120 VDD 166 0053 29 A7 75 CK2 121 0022 167 NC 30 VDDQ 76 CK2 122 A8 168 VDD 31 0019 77 VDDQ 123 0023 169 DM6 32 78 DQS6 124 VSS 170 0054 33 0024 79 0050 125 171 0055 34 VSS 80 DQ51 126 0028 172 VDDQ 35 0025 81 VSS 127 0029 173 NC 36 0053 82 128 VDDQ 174 0060 37 4 83 0056 129 DM3 175 0061 38 VDD 84 DQ57 130 176 VSS 39 0026 85 VDD 131 0030 177 DM7 40 0027 86 0057 132 VSS 178 0062 41 A2
9. ed operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS Recommended operating conditions Voltage referenced to Vss OV TA 0 to 70 C Parameter Symbol Min Max Unit Note Supply voltage VDD 2 5 2 7 V Supply voltage VDDQ 2 5 2 7 V Reference voltage VREF 000 2 50 VDDQ 2 50mV V 1 Termination voltage VTT VREF 0 04 VREF 0 04 V 2 Input logic high voltage VIH DC VREF 0 15 VDDQ 0 3 V 4 Input logic low voltage VIL DC 0 3 VREF 0 15 V 4 Input Voltage Level CK and CK inputs VIN DC 0 3 VDDQ 0 3 V Input Differential Voltage CK and CK inputs VID DC 0 3 VDDQ 0 6 V 3 Input crossing point voltage CK and CK inputs VIX DC 1 15 1 35 V 5 Input leakage current 2 2 uA Output leakage current loz 5 5 uA Output High Current Normal strength driver _ VOUT VTT 0 84V ak m Output Low Current Normal strength driver VOUT VTT 0 84V x eR me Output High Current Half strength driver VOUT 0 45V i mA Output High Current Half strength driver lo 9 VOUT VTT 0 45V Note 1 Includes 25mV margin for DC offset on VREF and a combined total of 50mV margin for all AC noise and DC offset on VREF bandwidth limited to 20MHz The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF both of which may result in VREF noise VRE
10. he half period jitter tJIT HP of the clock source and less the half period jitter due to crosstalk tJIT crosstalk into 12 tQH tHP tQHS where minimum half clock period for any given cycle and is defined by clock high or clock low tCH tCL tQHS accounts for 1 The pulse duration distortion of on chip clock circuits and 2 The worst case push out of DQS on one transition followed by the worst case pull in of DQ on the next transition both of which are separately due to data pin skew and output pattern effects and p channel to n channel variation of the output drivers 13 tDQSQ Consists of data skew and output pattern effects and p channel to n channel variation of the output drivers for any given cycle 14 tDAL tWR tCK tRP tCK 15 In all circumstances tXSNR can be satisfied using tXSNR tRFCmin 1 tCkK 16 The only time that the clock frequency is allowed to change is during self refresh mode Transcend Information Inc 184PIN 00 400 Unbuffered DIMM JM334 D643A 50 256MB With 32Mx8 CL2 5 SIMPLIFIED TRUTH TABLE V Valid X Don t Care H Logic High L Logic Low Extended me O e Register Register Set X L Lt Lt OP CODE ee ia E ee E He EET PE AL E o HERR TITIO m Read amp Auto Precharge Disable Com ress Column Address Auto Precharge Enable i Auto Precharge Disable Column Wies ete ade e eae eel Auto
11. it Output Q INPUT OUTPUT CAPACITANCE Vpp 2 6V 2 6V 25 C f 1MHz Input capacitance A0 A12 BAO BA1 RAS CAS Input capacitance CKEO Input capacitance 50 Input capacitance CK0 CK2 Input capacitance DMO DM7 Data and DQS input output capacitance 000 0063 Transcend Information Inc 7 JM334D643A 50 184PIN DDR400 Unbuffered DIMM 256MB With 32Mx8 CL2 5 AC TIMING PARAMETERS amp SPECIFICATIONS These AC characteristics were tested on the Component Parameter Symbol Min Max Unit Note Row cycle time tRC 55 ns Refresh row cycle time tRFC 65 ns Row active time tRAS 40 70K ns RAS to CAS delay tRCD 15 ns Row active to Row active delay tRP 15 ns Row active to Row active delay tRRD 10 ns Write recovery time tWR 10 ns Last data in to Read command tWTR 2 tCK Clock cycle time tCK 5 10 ns 16 Clock high level width tCH 0 45 0 55 tCK Clock low level width tCL 0 45 0 55 tCK DQS out access time CK CK tDQSCK 0 5 0 5 ns Output data access time from CK CK tAC 0 7 0 7 ns Data strobe edge to output data edge tDQSQ 0 35 ns 13 Read Preamble tRPRE 0 9 1 1 Read Postamble tRPST 0 4 0 6 tCK CK to valid DQS in tDQSS 0 72 1 25 tCK Write preamble setup time tWPRES 0 ps 5 Write preamble tWPRE 0 25 tCK Write postamble tWPST 0 4 0 6 4 00 falling edge to CK
12. loating standby current CS gt VIH min All banks idle CKE gt VIH min Address and other control inputs changing once per clock IDD2F 240 mA cycle VIN VREF for DQ DQS and DM Active power down standby current one bank active power down mode CKE lt VIL max VIN VREF for DQ DQS and DM IDD3P 440 mA Active standby current CS gt VIH min CKE gt VIH min one bank active active precharge tRC tRASmax DQ DQS and DM inputs changing twice per clock cycle address and other control inputs changing once per clock cycle IDD3N 600 mA Operating current burst read Burst length 2 reads continuous burst One bank active address and control inputs changing once per clock cycle IDD4R 1480 mA 50 of data changing at every burst lout 0 mA Operating current burst write Burst length 2 writes continuous burst One bank active address and control inputs changing once per clock cycle DQ DM and DQS inputs changing twice per clock cycle 50 of input data changing at every burst IDD4W 1760 mA Auto refresh current tRC tRFC min 10 tCK for DDR400 at 200MHz distributed refresh ID IE is Self refresh current CKE lt 0 2V External clock should be on IDD6 24 mA Operating current Four bank operation Four bank interleaving with BL 4 Refer to the following page for detailed test condition ixi 2800 Note 1 Module IDD was calculated on the basis
13. ncy supported 2 5 2 0C 19 CS Latency 0 CLK 01 20 WE Latency 1 CLK 02 21 DDR SDRAM Module Attributes 20 Clock Input 22 DDR SDRAM Device Attributes General Fast concurrent AP 00 23 DDR SDRAM Cycle Time CL 2 0 6ns 60 24 DDR SDRAM Access from Clock CL 2 0 0 7ns 70 25 DDR SDRAM Cycle Time CL 1 5 00 26 DDR SDRAM Access from Clock CL 1 5 00 27 Minimum Row Precharge Time tRP 15ns 3C 28 Minimum Row Active to Row Activate delay tRRD 10ns 28 29 Minimum RAS to CAS Delay tRCD 15ns 3C 30 Minimum active to Precharge time tRAS 40ns 28 31 Module ROW density 256MB 40 32 Command Address Input Setup Time 0 6ns 60 33 Command Address Input Hold Time 0 6ns 60 34 Data Signal Input Setup Time 0 4ns 40 35 Data Signal Input Hold Time 0 4ns 40 36 40 Superset Information 00 DDR SDRAM Minimum Active to Active Auto Refresh 41 00 Time tRC 42 DDR SDRAM Minimim Auto Refresh to 00 Active Auto Refresh Period tRFC Transcend Information Inc 1 JM334D643A 50 184PIN DDR400 Unbuffered DIMM 256MB With 32Mx8 CL2 5 43 DDR SDRAM Maximum Device Cycle Time tCK max 00 44 DDR SDRAM DQS DQ Skew for DQS and 00 associated DQ signals 0050 max 45 DDR SDRAM Read Data Hold Skew Factor tQHS 00 46 PLL Relock Time 00 47 61 Superset Information 00 62 SPD Data Revision Code 00 63 Checksum for Bytes 0 62 8F 8F 64 71 Manufacturers ID Tran
14. of component IDD and can be differently measured according to DQ loading capacitor Transcend Information Inc 6 184PIN DDR400 Unbuffered DIMM JM334 D643A 50 256MB With 32Mx8 CL2 5 AC OPERATING CONDITIONS Parameter Symbol Min Max Unit Note Input High Logic 1 Voltage DQ DQS and DM signals VIH AC VREF 0 31 V Input Low Logic 0 Voltage DQ DQS and DM signals VIL AC VREF 0 31 V Input Differential Voltage CK and CK inputs VID AC 0 7 VDDQ 0 6 V 1 Input Crossing Point Voltage CK and CK inputs VIX AC 0 5 VDDQ 0 2 0 5 VDDQ 0 2 V 2 Note 1 VID is the magnitude of the difference between the input level on CK and the input on CK 2 The value of VIX is expected to equal 0 5 V DDQ of the transmitting device and must track variations in the DC level of the same 3 These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation The AC and DC input specifications are relative to a VREF envelope that has been bandwidth limited 20MHz AC OPERATING TEST CONDITIONS Vpp 2 6 Vopa 2 6 TA 0 to 70 C Parameter nput reference voltage for Clock nput signal maximum peak swing nput Levels VIH VIL nput timing measurement reference level Output timing measurement reference level Output load condition See Load Circuit VTT 0 5 VDDQ reson ZO 500hm 0 5 VDDQ CLoAp 30pF Output Load circu
15. scend 7F 4F 72 Manufacturing Location 00 73 90 Manufacturers Part Number 00 91 92 Revision Code 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number By Manufacturer Variable 99 127 Manufacturer Specific Data 128 255 Unused Storage Locations Undefined Transcend Information Inc 2
16. very burst length DM sampled at the rising and falling edges of the DQS and Data in is masked at the both edges Write DM latency is 0 This combination is not defined for any function which means No Operation NOP in DDR SDRAM Transcend Information Inc 10 184PIN 00 400 Unbuffered DIMM JM334 D643A 50 256MB With 32Mx8 CL2 5 SERIAL PRESENCE DETECT SPECIFICATION Serial Presence Detect Byte No Function Described Standard Specification Vendor Part 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type DDR SDRAM 07 3 of Row Addresses on this Assembly 13 OD 4 of Column Addresses on this Assembly 10 OA 5 of Module Rows on this Assembly 1 bank 01 6 Data Width of this Assembly 64bits 40 7 Data Width of this Assembly 0 00 8 VDDQ and Interface Standard of this Assembly SSTL 2 04 9 DDR SDRAM Cycle Time at CAS Latency 2 5 5ns 50 10 DDR SDRAM Access Time from Clock at CL 2 5 0 7ns 70 11 DIMM configuration type non parity Parity ECC Non ECC 00 12 Refresh Rate Type 7 8us Self Refresh 82 13 Primary DDR SDRAM Width X8 08 14 Error Checking DDR SDRAM Width 00 Min Clock Delay for Back to 19 Back Random Column Address 0 16 Burst Lengths Supported 2 4 8 OE 17 of banks on each DDR SDRAM device 4 bank 04 18 CAS Late
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