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Samsung M471B5273BH1-CF8 memory module

1. Vpp Vop Es Ns al vit F1 ven we z oo DE wyivvacet a d ses Sos e SES EES EES fo a DQS3 v Das 2400 Beg 20 pas 2400 pas 2400 m DOE DQS3 w DOS 1 Das c 176 Das t1 DaS 1 Lw DQS4 DM3 w DM Zaw DM Zaw DM ZQ I DM ZU w DM4 DQ 24 31 W DQ 0 7 4 DQJo 7 DQ 0 7 XY DQ 0 7 W DQ 32 39 D11 El D3 D4 E D12 S z z z z Ed Ed Ed Ed d d E d S S E E TO wes nn of os nn Un NY ME H sis oaz
2. 4 le 1 00 0 10 24 80 21 00 2X g 1 80 6120 10 M c A B MS OPTIONAL HOLES Iw H Ese 2X 4 00 al A B 20 10 MIC 0 60 kk gt 0 45 0 03 y y a 4 00 0 10 255 j TI uM 1 00 0 10 0 25 MAX Detail A Detail B The used device is 256M x8 DDR3 SDRAM FBGA DDR3 SDRAM Part NO KAB2G0846B HC 29 of 29 Rev 1 03 June 2009 ELECTRONICS
3. Speed DDR3 1066 DDR3 1333 Units Note Parameter Symbol MIN MAX MIN MAX Clock Timing Minimum Clock Cycle Time DLL off mode E 8 8 ns 6 Average Clock Period tCK avg See Speed Bins Table ps Clock Period TTE FE JE FPE IE Average high pulse width tCH avg 0 47 0 53 0 47 0 53 tCK avg Average low pulse width tCL avg 0 47 0 53 0 47 0 53 tCK avg Clock Period Jitter tJIT per 90 90 80 80 ps Clock Period Jitter during DLL locking period tJIT per Ick 80 80 70 70 ps Cycle to Cycle Period Jitter tJIT cc 180 160 ps Cycle to Cycle Period Jitter during DLL locking period tJIT cc Ick 160 140 ps Cumulative error across 2 cycles ERR 2per 132 132 118 118 ps Cumulative error across 3 cycles ERR 3per 157 157 140 140 ps Cumulative error across 4 cycles ERR 4per 175 175 155 155 ps Cumulative error across 5 cycles ERR 5per 188 188 168 168 ps Cumulative error across 6 cycles ERR 6per 200 200 177 177 ps Cumulative error across 7 cycles ERR 7per 209 209 186 186 ps Cumulative error across 8 cycles ERR 8per 217 217 193 193 ps Cumulative error across 9 cycles ERR 9per 224 224 200 200 ps Cumulative error across 10 cycles tERR 10per 231 231 205 205 ps Cumulative error across 11 cycles tERR 11per 237 237 210 210 ps Cumulative error across 12 cycles tERR
4. Speed DDR3 1066 CL nRCD nRP 7 7 7 Units Note Parameter Symbol min max Internal read command to first data tAA 13 125 20 ns ACT to internal read or write delay time tRCD 13 125 ns PRE command period tRP 13 125 ns ACT to ACT or REF command period tRC 50 625 ns ACT to PRE command period tRAS 37 5 9 tREFI ns 8 7 CWL 5 tCK AVG 2 5 3 3 ns 1 2 3 6 SH CWL 6 tCK AVG Reserved ns 1 2 3 4 nem CWL 5 tCK AVG Reserved ns 4 CWL 6 tCK AVG 1 875 2 5 ns 1 2 3 4 TEM CWL 5 tCK AVG Reserved ns 4 CWL 6 tCK AVG 1 875 2 5 ns 1 2 3 Supported CL Settings 6 7 8 nCK Supported CWL Settings 5 6 nCK DDR3 1333 Speed Bins Speed DDR3 1333 CL nRCD nRP 9 9 9 Units Note Parameter Symbol min max Internal read command to first data tAA 13 5 13 125 59 20 ns ACT to internal read or write delay time tRCD 13 5 13 125 59 ns PRE command period tRP 13 5 13 125 59 ns ACT to ACT or REF command period tRC 49 5 49 125 gt 9 P ns ACT to PRE command period tRAS 36 9 tREFI ns 8 CWL 5 tCK AVG 2 5 3 3 ns 1 2 3 7 CL 6 CWL 6 tCK AVG Reserved ns 1 2 3 4 7 CWL 7 tCK AVG Reserved ns 4 CWL 5 tCK AVG Reserved ns 4 CL 7 CWL 6 tCK AVG ud SER ns 1 2 3 4 7 Optional Note 5 9 CWL 7 tCK AVG Reserved ns 1 2 3 4 CWL 5 tCK AVG Reserved ns 4 CL 8 CWL 6 tCK AVG 1 875 2 5 ns 1 2 3 7 CWL 7 tCK AVG Reserved ns 1 2 3 4 aes CWL 5 6 tCK AVG Reserved ns 4 CWL 7 tCK AVG 1 5 1 875 ns 1 2 3 4 CWL 5 6 tCK AVG Reserved
5. JEDEC standard 1 5V 0 075V Power Supply Vona 1 5V 0 075V 400 MHz fcx for 800Mb sec pin 533MHz fcx for 1066Mb sec pin 667MHz fck for 1333Mb sec pin 8independent internal bank Programmable CAS Latency 6 7 8 9 Programmable Additive Latency Posted CAS 0 CL 2 or CL 1 clock Programmable CAS Write Latency CWL 5 DDR3 800 6 DDR3 1066 7 DDR3 1333 8 bit pre fetch Burst Length 8 Interleave without any limit sequential with starting address 000 only 4 with tCCD 4 which does not allow seamless read or write either On the fly using A12 or MRS Bi directional Differential Data Strobe nternal self calibration Internal self calibration through ZQ pin RZQ 240 ohm 1 On Die Termination using ODT pin Average Refresh Period 7 8us at lower than Tease 85 C 3 9us at 85 C lt Tease lt 95 C Asynchronous Reset 3 0 Address Configuration Organization Row Address Column Address Bank Address Auto Precharge 256x8 2Gb based Module A0 A14 A0 A9 BAO BA2 A10 AP ELECTRONICS 5 of 29 Rev 1 03 June 2009 Unbuffered SoDIMM DDR3 SDRAM 4 0 x64 DIMM Pin Configurations Front side Back Side Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 VREFDQ 2 V
6. The dc tolerance limits and ac noise limits for the reference voltages Veerca and VrerpO are illustrate in Figure 1 It shows a valid reference voltage Vrer t as a function of time V amp ge stands for Vperca and Vggepg likewise VreF DC is the linear average of VeeF t over a very long period of time e g 1 sec This average has to meet the min max requirements of Veer Fur thermore Vergf t may temporarily deviate from VeeF DC by no more than 1 Vpp A voltage Vref ac noise j P i 4 Vnet DC max VDD 2 VRef DC min Figure 1 Illustration of VREF DC tolerance and VREF ac noise limits The voltage levels for setup and hold time measurements V y AC V DC Vi AC and V DC are dependent on Vggr Vngr shall be understood as Vgge DC as defined in Figure 1 This clarifies that dc variations of Veer affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured System timing and voltage budgets need to account for Vgge DC deviations from the optimum position within the data eye of the input signals This also clarifies that the DRAM setup hold specification and derating values need to include time and voltage associated with Vgge ac noise Timing and voltage effects due to ac noise on Vggr up to the specified limit 1 of Vpp are included in DRAM timings and their associated deratings 12 o
7. e p10 e D5 ve D7 V4 v5 Vi VREFCA D0 D15 SCL SCL VREFDa f DO D15 SA0 A0 PD ll TE wa Vi ve SPD SDA Von ZE DO D15 DO je D2 te e D13 e D15 SA Al EL V5 A2 WP Vss 444 D0 D15 SPD seu CL E d cko DO D7 Di e D11 tee D4 z D14 cki DR D15 V2 v9 V a MN CK0 DO D7 CK1 D8 D15 Address and Controllines RESET D0 D7 Note 1 DQ wiring may differ from that shown however DO DM DOS and DOS relationships are maintained as shown 9 of 29 Rev 1 03 June 2009 ELECTRONICS Unbuffered SoDIMM DDR3 SDRAM 8 0 Absolute Maximum Ratings 8 1 Absolute Maximum DC Ratings Symbol Parameter Rating Units Notes Vpp Voltage on Vpp pin relative to Vss 0 4 V 1 975 V V 1 3 Vppo Voltage on Vppg pin relative to Vss 0 4 V 1 975 V V 1 3 Vin Vout Voltage on any pin relative to Vss 0 4 V 1 975 V V 1 TsrG Storage Temperature 55 to 100 C 1 2 Note 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Storage Temperature is the case surf
8. Wie az Wie x Oz Wye xv OZ lesse ssi atlas SO Ss SS SSS assi sis seg e ba o LU DOS wv DOS 2400 DQS 2400 Das 2400 I pas 2400 Ha DQS6 DQS1 w Das ps pas E EC Das cd __ pas aa Lu Dase DM1 w DM SAL DM DM L DM I w DM6 DQ 8 15 W DQ 0 7 pao F DQ 0 7 Go 397 X w DQ 48 55 o o o o Es E E E o Si Q n S S S S n n WES nin ub nin wes nln Un Lx oz Wie oz Lx oz xix oz PERE l 60 7 aisle l 0 Blase SIS 50 el l 69 La D 3 DQS0 w Das 2 pas 2400 Das 2400 L Das 2400 w DQS7 paso w Das 1 DOS t1 DOS t1 _ pas 1 Lw Das7 DMO w DM Zaw DM ZQ Rank0 DM za L DM ZQ w gt DM7 DQ 0 7 W DQ 0 7 LL daQi 7 Rank DQ 0 7 DQ 0 7 HW DQ 56 63 DO E S D15 cS D7 S i E E i o o o Oe mes oi IE 2 3 xix oz Wie oz Z PERE l 690 el S z Es In DQS2 w pas 2400 Das 2400 pas 2400 Das 2400 ww DQS5 DQS2 w Das M Das pu Das ere L bas p Lw Dass DM2 w DM DM L DM DM a gt DM5 DQ 16 23 A DQ 0 7 Y Dajo 7 DQ 0 7 DQ 0 7 HW DQ 40 47 D2 S D10 S 13 S E Zz 2 2 E Es E E E Es d d a E S E E ni 3 qo Mm nin fir essa nin wez Wie az Wie SD Wye az Wee OZ isles 51550 BERE d ot HERE d ot PRSE d ot D e e e m og v2 Vi v8 D9 re D3 po ei D12 Lei D6 va eea Mu V3 v7 VppsPb 4 SPD J vs
9. or Power Down Exit PDX tCKSRX max 5nCK max 5nCK or Reset Exit 10ns 10ns 25 of 29 Rev 1 03 June 2009 Unbuffered SoDIMM Timing Parameters by Speed Bin Cont DDR3 SDRAM ELECTRONICS Speed DDR3 1066 DDR3 1333 Units Note Parameter Symbol MIN MAX MIN MAX Power Down Timing Exit Power Down with DLL on to any valid command Exit Prercharge Power max max Down with DLL E DP 3nCK 3nCK 6ns frozen to commands not requiring a locked DLL 7 5ns See Precharge Power Down with DLL frozen to commands requiring a locked tXPDLL a onc 10nCK 2 24ns 24ns max max CKE minimum pulse width tCKE 3nCK 3nCK 5 625ns 5 625ns Command pass disable delay tCPDED 1 1 nCK Power Down Entry to Exit Timing tPD tCKE min 9 tREFI tCKE min 9 tREFI tCK 15 Timing of ACT command to Power Down entry tACTPDEN 1 1 nCK 20 Timing of PRE command to Power Down entry tPRPDEN 1 1 nCK 20 Timing of RD RDA command to Power Down entry tRDPDEN RL 4 1 RL 4 1 un Mem we Afs T Tamil E erg Down entry WRAPDEN WL 4 WR 1 WL 4 WR 1 nCK 10 M command to Power Down entry tWRPDEN aa WEN nCK 9 Timing of WRA command to Power Down entry IWRAPDEN WL 2 WR 1 E WL 2 WR 1 nCK 10 BLAMRS Timing of REF command to Power Down entry tREFPDEN 1 1 20 21 Timing of MRS command to Power Down ent
10. tRP tRC and tRAS for corresponding Bin ns e ACTIVE to ACTIVE command period for 1KB page size RRD 4nCK 7 5ns S AnCK rei e e ACTIVE to ACTIVE command period for 2KB page size RRD an CK 10ns i 4n eR Se n e Four activate window for 1KB page size FAW 37 5 30 ns e Four activate window for 2KB page size FAW 50 45 ns e Command and Address setup time to CK CK referenced to Vin AC Vy AC levels tlS base 125 65 ps b 16 Ge and Address hold time from CK CK referenced to Vj AC Vi AC lev tlH base 200 140 ps b 16 Command and Address setup time to CK CK referenced to Vi AC Vi AC levels yc 125 150 654125 ps b 16 27 Control amp Address Input pulse width for each input tIPW 780 620 ps 28 Calibration Timing Power up and RESET calibration time tZQinitl 512 512 nCK Normal operation Full calibration time tZQoper 256 256 nCK Normal operation short calibration time tZQCS 64 64 nCK 23 Reset Timing Exit Reset from CKE HIGH to a valid command tXPR Wk ee bi ns dd C Self Refresh Timing Exit Self Refresh to commands not requiring a locked DLL tXS Mn i in uh t rs Exit Self Refresh to commands requiring a locked DLL tXSDLL tDLLK min tDLLK min nCK Minimum CKE low width for Self refresh entry to exit timing tCKESR tCKE min 1tCK tCKE min 1tCK Valid Clock Requirement after Self Refresh Entry SRE or Power Down Entry PDE tCKSRE uo cn Valid Clock Requirement before Self Refresh Exit SRX
11. 12per 242 242 215 215 ps Cumulative error across n 13 14 49 50 cycles tERR nper Ee E i BIG PIN De as ps 24 Absolute clock HIGH pulse width tCH abs 0 43 0 43 tCK avg 25 Absolute clock Low pulse width tCL abs 0 43 0 43 tCK avg 26 Data Timing DQS DQS to DQ skew per group per access tDQSQ 150 125 ps 13 DQ output hold time from DOS DOS tQH 0 38 0 38 tCK avg 13 9 DQ low impedance time from CK CK tLZ DQ 600 300 500 250 ps 13 14 f DQ high impedance time from CK CK tHZ DQ 300 250 ps 13 14 f Data setup time to DQS DQS referenced to V H AC V AC levels tDS base 25 30 ps d 17 Data hold time to DOS DOS referenced to Viu AC V AC levels tDH base 100 B 65 ps d 17 DQ and DM Input pulse width for each input tDIPW 490 400 ps 28 Data Strobe Timing DQS DQS READ Preamble tRPRE 0 9 Note 19 0 9 Note 19 tCK 13 19 g DQS DOS differential READ Postamble tRPST 0 3 Note 11 0 3 Note 11 tCK 11 13 b DQS DAS output high time tQSH 0 38 0 4 tCK avg 13 g Das DAS output low time tQSL 0 38 0 4 tCK avg 13 9 DQS DQS WRITE Preamble tWPRE 0 9 0 9 tCK DQS DQS WRITE Postamble tWPST 0 3 0 3 tCK Das DOS rising edge output access time from rising CK CK tDQSCK 300 300 255 255 ps 13 f Das DOS low impedance time Referenced from RL 1 tLZ DQS 600 300 500 250 ps 13 14 f Das DAS high impedance time Referenced from RL BL 2 tHZ DQS 300 250 ps 13 14 f DQS DQS differential input low pulse w
12. Overshoot and Undershoot Specification 14 of 29 Rev 1 03 June 2009 ELECTRONICS Unbuffered SoDIMM DDR3 SDRAM 10 3 4 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe each cross point voltage of differential input signals CK CK and DOS DQS must meet the requirements in below table The differential input cross point voltage Vu is measured from the actual cross point of true and complement signal to the mid level between of Vpp and Vas Figure 4 Vix Definition Cross point voltage for differential input signals CK DQS Vpp CK DOS CK DQS Vss DDR3 800 1066 1333 Symbol Parameter Unit Notes Min Max Vix Differential Input Cross Point Voltage relative to Vpp 2 for CK CK aiu Dm my 175 175 mV 1 Vix Differential Input Cross Point Voltage relative to Vpp 2 for DQS DQS 150 150 mV Note 1 Extended range for Vix is only allowed for clock and if single ended clock input signals CK and CK are monotonic have a single ended swing VseL Varu Of at least Vpp 2 250 mV and the differential slew rate of CK CK is larger than 3 V ns 10 4 Slew Rate Definition for Single Ended Input Signals See Address Command Setup Hold and Derating for single ended slew rate definitions for address and command signals See Data Setup Hold and Slew Rate Derat
13. Single ended signal parameter 15 tREFI depends on Toper 16 tIS base and tiH base values are for 1V ns CMD ADD single ended slew rate and 2V ns CK CK differential slew rate Note for DQ and DM signals Vrer DC VrEFDQ DO FOr input only pins except RESET VreF DC VrEFCA DO See Address Command Setup Hold and Derating 17 tDS base and tDH base values are for 1V ns DQ single ended slew rate and 2V ns DOS DAS differential slew rate Note for DQ and DM signals VreF DC VreFDQ DO For input only pins except RESET VreF DC VrEFCA DO See Data Setup Hold and Slew Rate Derating 18 Start of internal write transaction is defined as follows For BL8 fixed by MRS and on the fly Rising clock edge 4 clock cycles after WL For BC4 on the fly Rising clock edge 4 clock cycles after WL For BC4 fixed by MRS Rising clock edge 2 clock cycles after WL 19 The maximum read preamble is bound by tLZDQS min on the left side and tDQSCK max on the right side See Device Operation 20 CKE is allowed to be registered low while operations such as row activation precharge autoprecharge or refresh are in progress but power down IDD spec will not be applied until finishing those operations 21 Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN min is satisfied there are cases where additional time such as tXPDLL min is also required See Device Operation 22 Defined between end of MPR read b
14. c Precharge Power Down Mode set MRO A12 0B for Slow Exit or MRO A12 18B for Fast Exit d Auto Self Refresh ASR set MR2 A6 OB to disable or 1B to enable feature e Self Refresh Temperature Range SRT set MR2 A7 0B for normal or 1B for extended temperature range f Refer to DRAM supplier data sheet and or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device 9 IDD current measure method and detail patterns are described on DDR3 component datasheet 19 of 29 Rev 1 03 June 2009 ELECTRONICS Unbuffered SoDIMM DDR3 SDRAM 12 1 IDD SPEC Table M471B5273BH1 4GB 512Mx64 Module Symbol er cue Unit Notes Y DDR3 1066 CL 7 DDR3 1333 CL 9 IDDO 880 920 mA IDD1 1000 1040 mA IDD2PO slow exit 192 192 mA IDD2P1 fast exit 480 560 mA IDD2N 640 640 mA IDD2Q 560 640 mA IDD3P fast exit 560 560 mA IDD3N 760 800 mA IDDAR 1320 1480 mA IDD4W 1360 1520 mA IDD5B 1800 1800 mA IDD6 192 192 mA IDD7 2160 2560 mA 13 0 Input Output Capacitance 13 1 2Rx16 1GB SoDIMM M471B5273BH1 DDR3 1066 DDR3 1333 Parameter Symbol Units Notes Min Max Min Max Input output capacitance DQ DM DQS DOS TDS TDQS s i TBD i TBD pF Input capacitance CK and CK CCK TBD TBD pF Input capacitance All other input only pins S ZER i TBD pF Input output capacitance of ZQ pin CZQ TBD TBD pF 20 o
15. inputs DD DD DD DD i Note 1 For input only pins except RESET Vggre VrercA DC 2 See Overshoot and Undershoot specifications section 3 The AC peak noise on Veer may not allow Vggr to deviate from Vgge DC by more than 1 Vpp for reference approx 15mV 4 For reference approx Vpp 2 x 15mV Single Ended AC and DC input levels for DQ and DM DDR3 1066 DDR3 1333 Symbol Parameter Unit Notes Min Max Min Max Vu po DC100 DC input logic high Vggr 100 Vpp Vrer 100 Von mV 1 Vit pa DC100 DC input logic low Vss Vrer 100 Vss Vrer 100 mV 1 Vu po AC175 AC input logic high Voer 175 Voer 150 mV 1 2 5 Vu po AC175 AC input logic low Ver 175 Vrer 150 mV 1 2 5 Vu po AC150 AC input logic high Veer 150 Note mV 1 2 5 Vit po AC150 AC input logic low Note 2 Vrer 150 E z mV 1 2 5 Veerpa DC UO Reference Voltage DQ 0 49 Vpp 0 51 Vpp 0 49 Vpp 0 51 Vpp V 3 4 Note 1 For input only pins except RESET Vggr Vrerpa DC 2 See Overshoot and Undershoot specifications section 3 The AC peak noise on Vref may not allow Vggr to deviate from Vgge DC by more than 1 Vpp for reference approx Vpp 2 15mV 4 For reference approx 15mV 5 Single ended swing requirement for DQS DQS is 350mV peak to peak Differential swing requirement for DQS DQS is 700mV peak to peak ELECTRONICS 11 of 29 Rev 1 03 June 2009 Unbuffered SoDIMM DDR3 SDRAM 10 2 Vref Tolerances
16. ns 4 CL 10 1 5 1 875 ns 1 2 3 CWL 7 tCK AVG Optional ns 5 Supported CL Settings 6 7 8 9 nCK Supported CWL Settings 5 6 7 nCK 22 of 29 ELECTRONICS Rev 1 03 June 2009 Unbuffered SoDIMM DDR3 SDRAM 14 3 1 Speed Bin Table Notes Absolute Specification Toper Vppo Vpp 1 5V 0 075 V Note 1 The CL setting and CWL setting result in tCK AVG MIN and tCK AVG MAX requirements When making a selection of tCK AVG both need to be ful filled Requirements from CL setting as well as requirements from CWL setting 2 tCK AVG MIN limits Since CAS Latency is not purely analog data and strobe output are synchronized by the DLL all possible intermediate frequen cies may not be guaranteed An application should use the next smaller JEDEC standard tCK AVG value 2 5 1 875 1 5 or 1 25 ns when calculat ing CL nCK tAA ns tCK AVG ns rounding up to the next SupportedCL 3 tCK AVG MAX limits Calculate tCK AVG tAA MAX CL SELECTED and round the resulting tCK AVG down to the next valid speed bin i e 3 3ns or 2 5ns or 1 875 ns or 1 25 ns This result is tCK AVG MAX corresponding to CL SELECTED 4 Reserved settings are not allowed User must program a different value 5 Optional settings allow certain devices in the industry to support this setting however it is not a mandatory feature Refer to supplier s data sheet and or the DIMM SPD information if and how this setting is supported 6 Any
17. 0 DQS7 o sourced by the controller and is centered in the data window In Read mode the data strobe is sourced by the DDR3 DQS0 DQS7 SDRAMs and is sent at the leading edge of the data window DQS signals are complements and timing is relative to the crosspoint of respective DQS and DQS Vpp VppsPD S Vos upply Power supplies for core I O Serial Presence Detect Temp sensor and ground for the module V REFDQ Supply Reference voltage for SSTL15 inputs VREFCA SDA lO This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and Temp sensor A resistor must be connected from the SDA bus line to Vppspp on the system planar to act as a pull up SCL Input This signal is used to clock data into and out of the SPD EEPROM and Temp sensor SA0 SA1 Input Address pins used to select the Serial Presence Detect and Temp sensor base address TEST 1 0 The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules RESET Input RESET In Active Low This signal resets the DDR3 SDRAM ELECTRONICS 8 of 29 Rev 1 03 June 2009 Unbuffered SoDIMM DDR3 SDRAM 7 0 Function Block Diagram 7 1 4GB 512Mx64 Module Populated as 2 ranks of x8 DDR3 SDRAMs
18. 1 SA1 202 SCL 65 Vss 66 Vss 133 Vss 134 Vss 203 Vor 204 Ver 67 DQ26 68 DQ30 135 DQS4 136 DM4 69 DQ27 70 DQ31 137 DQS4 138 Vss Note 1 NC No Connect NU Not Usable RFU Reserved Future Use 2 TEST pin 125 is reserved for bus analysis probes and is NC on normal memory modules 3 This address might be connected to NC balls of the DRAMs depending on density either way they will be connected to the termination resistor SAMSUNG ELECTRONICS CO Ltd reserves the right to change products and specifications without notice ELECTRONICS 6 of 29 Rev 1 03 June 2009 Unbuffered SoDIMM 5 0 Pin Description DDR3 SDRAM Pin Name Description Number Pin Name Description Number CKO CK1 Clock Inputs positive line 2 DQO DQ63 Data Input Output 64 CK0 CK1 Clock Inputs negative line 2 DM0 DM7 ci E Greg 8 CKEO CKE1 Clock Enables 2 DQSO DQS7 Data strobes RAS Row Address Strobe 1 DQSO DQS7 Data strobes complement CAS Column Address Strobe 1 RESET Reset Pin 1 WE Write Enable 4 TEST aceon specific test pin No connect 4 So S1 Chip Selects 2 Vpp Core and UO Power 18 psc Address Inputs 14 Vss Ground 52 A10 AP Address Input Autoprecharge 1 VREFDO Input Output Reference 2 VREFCA A12 BC Address Input Burst chop 1 Vppspp SPD and Temp sensor Power 1 BAO BA2 SDRAM Bank Addresses 3 Ver Termination Voltage ODTO ODT1 On die termination control 2 NC Reserved for future u
19. 4 0 x64 DIMM Pin Configurations Front side Back Side eeerreeeeeeeeeeneee 6 50 Pin DESEription c 7 6 0 Input Output Functional Description ori ii 8 7 0 Function Block Diagram EE 9 7 1 4GB 512Mx64 Module Populated as 2 ranks of x8 DDR3 SDRAMS eere nnn 9 8 0 Absolute Maximum Ratings diia 10 8 1 Absolute Maximum DC RatingS ege 10 8 2 DRAM Component Operating Temperature Range omoncocococononanonononencaranannnnnnnnnnararararannnnanananararananaes 10 9 0 AC amp DC Operating Ke Dt TE 10 9 1 Recommended DC Operating Conditions SSTL 15 occccconcncnnoncnconanannnnnnnconnnnnconnnnnrrnnnanrrrnnnnrrrnannnnnas 10 10 0 AC amp DC Input Measurement Levels eeeeeeeeeessssseeseeeeeeenn nennen nnne nnne nnn nnns 11 10 1 AC amp DC Logic Input Levels for Single ended Signals EE EEN eene eene nennen nnn nnn 11 10 2 VRer Tolerances E ERNE 12 10 3 AC and DC Logic Input Levels for Differential Signals cesse eeeee eene enne nennen nnn nnn 13 10 3 1 Differential Signals Definition szcssencncanaa s ounce nauta ren tadu au rana wn EE DNE I NM RN EE ODE EAE DMN nnmnnn nnmnnn 13 10 3 2 Differential Swing Requirement for Clock CK CK and Strobe DOS DQS enn 13 10 3 3 Single ended Requirements for Differential Signals onomonononccnonananonono
20. AC output low measurement level for output SR V1 0 1 x Vppa V 1 Note 1 The swing of 0 1 x Vppq is based on approximately 50 of the static single ended output high or low swing with a driver impedance of 40 and an effective test load of 25O to Vrr Vppo 2 11 2 Differential AC and DC Output Levels Differential AC and DC output levels Symbol Parameter DDR3 800 1066 1333 Units Notes Vougir AC AC differential output high measurement level for output SR 0 2 x VDDQ V 1 Voigig AC AC differential output low measurement level for output SR 0 2 x VDDQ V 1 Note 1 The swing of 0 2xVppq is based on approximately 50 of the static single ended output high or low swing with a driver impedance of 400 and an effective test load of 25O to Vrr Vppo 2 at each of the differential outputs 11 3 Single ended Output Slew Rate With the reference load for timing measurements output slew rate for falling and rising edges is defined and measured between Vo AC and V y AC for single ended signals as shown in below Single ended Output slew rate definition Measured Description Defined by From To VoH AC VoL AC Single ended output slew rate for rising edge VoL AC VoH AC MOHtAC VOL AC Delta TRse VoH AC Vo_ AC Single ended output slew rate for falling edge Vou AC Vo AC VoHlAC VoL AC Delta TFse Note
21. DDR3 1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization 7 Any DDR3 1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization 8 Any DDR3 1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization 9 For devices supporting optional downshift to CL 7 and CL 9 tAA tRCD tRP min must be 13 125 ns or lower SPD settings must be programmed to match For example DDR3 1333 CL9 devices supporting downshift to DDR3 1066 CL7 should program 13 125 ns in SPD bytes for tAAmin Byte 16 tRCDmin Byte 18 and tRPmin Byte 20 DDR3 1600 CL 11 devices supporting downshift to DDR3 1333 CL9 or DDR3 1066 CL7 should program 13 125 ns in SPD bytes for tAAmin Byte16 tRCDmin Byte 18 and tRPmin Byte 20 Once tRP Byte 20 is programmed to 13 125ns tRCmin Byte 21 23 also should be programmed accordingly For example 49 125ns tRASmin tRPmin 36ns 13 125ns for DDR3 1333 CL9 and 48 125ns tRASmin tRPmin 35ns 13 125ns for DDR3 1600 CL 11 23 of 29 Rev 1 03 June 2009 ELECTRONICS Unbuffered SoDIMM DDR3 SDRAM 15 0 Timing Parameters for DDR3 1066 and DDR3 1333 Timing Parameters by Speed Bin
22. DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Active Standby Current IDD3N CKE High External clock On tCK CL AC Timing Table BL 82 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling according to Table 34 Data IO FLOATING DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode Registers ODT Sig nal stable at 0 Active Power Down Current IDD3P CKE Low External clock On tCK CL AC Timing Table BL 82 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO FLOATING DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Operating Burst Read Current CKE High External clock On tCK CL AC Timing Table BL 89 AL 0 CS High between RD Command Address Bank Address Inputs partially tog IDD4R gling Data IO seamless read data burst with different data between one burst and the next one according to Table 36 DM stable at 0 Bank Activity all banks open RD commands cycling through banks 0 0 1 1 2 2 see Table 7 on page 10 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 IDDQ4R Operating Burst Read IDDQ Current optional Same definition like for IDDAR however measuring IDDQ current instead of IDD current Operating Burst Write Current IDDAW CKE High External c
23. Output like in DQ which stands for Data in Query Output diff Singe ended Signals Vonaitt AC Vit Votair AC delta TFdiff delta TRdiff Figure 7 Differential output slew rate definition 17 of 29 Rev 1 03 June 2009 ELECTRONICS Unbuffered SoDIMM DDR3 SDRAM 12 0 IDD specification definition Symbol Description Operating One Bank Active Precharge Current IDDO CKE High External clock On tCK nRC nRAS CL AC Timing Table BL 89 AL 0 CS High between ACT and PRE Command Address Bank Address Inputs partially toggling Data IO FLOATING DM stable at 0 Bank Activity Cycling with one bank active at a time 0 0 1 1 2 2 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Operating One Bank Active Read Precharge Current IDD4 CKE High External clock On tCK nRC nRAS nRCD CL AC Timing Table BL 83 AL 0 CS High between ACT RD and PRE Command Address Bank Address Inputs Data IO partially toggling DM stable at 0 Bank Activity Cycling with one bank active at a time 0 0 1 1 2 2 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Precharge Standby Current IDD2N CKE High External clock On tCK CL AC Timing Table BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling Data IO FLOATING DM stable at 0 Bank Activity all banks closed O
24. Output slew rate is verified by design and characterization and may not be subject to production test Single ended output slew rate DDR3 1066 DDR3 1333 Parameter Symbol Units Min Max Min Max Single ended output slew rate SRQse 2 5 5 2 5 5 V ns Description SR Slew Rate Q Query Output like in DQ which stands for Data in Query Output se Singe ended Signals For Ron RZQ 7 setting delta TFse delta TRse Figure 6 Single ended output slew rate definition 16 of 29 Rev 1 03 June 2009 ELECTRONICS Unbuffered SoDIMM DDR3 SDRAM 11 4 Differential Output Slew Rate With the reference load for timing measurements output slew rate for falling and rising edges is defined and measured between Vo qig AC and Vonairt AC for differential signals as shown in below Differential Output slew rate definition Measured Description Defined by From To Vongait AC Vot ai AC Differential output slew rate for rising edge Vo gig AC Vougit AC oa Dart Delta TRdiff Vonait AC VoLaig AC Differential output slew rate for falling edge Vouair AC VoLdirl AC oa art Delta TFdiff Note Output slew rate is verified by design and characterization and may not be subject to production test Differential Output slew rate DDR3 1066 DDR3 1333 Parameter Symbol Units Min Max Min Max Differential output slew rate SRQse 5 10 5 10 Vins Description SR Slew Rate Q Query
25. S for corresponding Bin EEN REENEN 22 14 3 1 Speed Bin Table Notes asin ic 23 uc Rev 1 03 June 2009 ELECTRONICS Unbuffered SoDIMM DDR3 SDRAM 15 0 Timing Parameters for DDR3 1066 and DDR3 1333 ccccceseeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeneneeennes 24 15 1 Jitter hu rq 27 15 2 Timing Parameter c get 28 16 0 Physical DinniG LI m M 29 16 1 256Mbx8 based 512Mx64 Module 2 Ranks 3 of 29 Rev 1 03 June 2009 ELECTRONICS Unbuffered SoDIMM Revision History DDR3 SDRAM Revision Month Year History 1 0 December 2008 First Release 1 01 February 2009 Corrected Module Physical Dimensions 1 02 February 2009 Added Tolerances to Physical Dimensions 1 03 June 2009 Corrected Typo ELECTRONICS 4 of 29 Rev 1 03 June 2009 Unbuffered SoDIMM 1 0 DDR3 Unbuffered SoDIMM Ordering Information DDR3 SDRAM Part Number Density Organization Component Composition Bad of Height M471B5273BH1 CF8 H9 4GB 512Mx64 256Mx8 K4B2G0846B HC 16 2 30mm Note HH F8 H9 F8 1066Mbps 7 7 7 H9 1333Mbps 9 9 9 2 0 Key Features DDR3 1066 DDR3 1333 Speed Unit 7 7 7 9 9 9 tCK min 1 875 1 5 ns CAS Latency 7 9 tCK tRCD min 13 125 13 5 ns tRP min 13 125 13 5 ns tRAS min 37 5 36 ns tRC min 50 625 49 5 ns
26. Unbuffered SoDIMM DDR3 SDRAM DDR3 SDRAM Specification 204pin Unbuffered SODIMM based on 2Gb B die 64 bit Non ECC 78FBGA with Lead Free amp Halogen Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS AND IS SUBJECT TO CHANGE WITHOUT NOTICE NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHER WISE TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL OGY ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS AS IS BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND 1 For updates or additional information about Samsung products contact your nearest Samsung office 2 Samsung products are not intended for use in life support critical care medical safety equipment or similar applications where Product failure could result in loss of life or personal or physical harm or any military or defense application or any governmental procurement to which special terms or provisions may apply Samsung Electronics reserves the right to change products or specification without notice 1 of 29 Rev 1 03 June 2009 ELECTRONICS Unbuffered SoDIMM DDR3 SDRAM Table Contents 1 0 DDR3 Unbuffered SoDIMM Ordering Information eese 5 2 0 Key Features 5 K r Xe gnum 5
27. ace temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 3 Vpp and Vppo must be within 300mV of each other at all times and Veer must be not greater than 0 6 x Vppq When Vpp and Vppg are less than 500mV Veer may be equal to or less than 300mV 8 2 DRAM Component Operating Temperature Range Symbol Parameter rating Unit Notes TOPER Operating Temperature Range 0 to 95 C 1 2 3 Note 1 Operating Temperature Toper is the case surface temperature on the center top side of the DRAM For measurement conditions please refer to the JEDEC document JESD51 2 2 The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported During operation the DRAM case tem perature must be maintained between 0 85 C under all operating conditions 3 Some applications require operation of the Extended Temperature Range between 85 C and 95 C case temperature Full specifications are guaran teed in this range but the following additional conditions apply a Refresh commands must be doubled in frequency therefore reducing the refresh interval tREFI to 3 9us It is also possible to specify a component with 1X refresh tREFI to 7 8us in the Extended Temperature Range b If Self Refresh operation is required in the Extended Temperature Range then it is mandatory to either use the Manual Self Refresh mode with Extended Temperature Range
28. capability MR2 A6 Ob and MR2 A7 1b or enable the optional Auto Self Refresh mode MR2 A6 1b and MR2 A7 0b 9 0 AC amp DC Operating Conditions 9 1 Recommended DC Operating Conditions SSTL 15 Rating Symbol Parameter Units Notes Min Typ Max Vpp Supply Voltage 1 425 1 5 1 575 V 1 2 VDDQ Supply Voltage for Output 1 425 1 5 1 575 V 1 2 Note 1 Under all conditions Vppo must be less than or equal to Von 2 Vppq tracks with Vpp AC parameters are measured with Vpp and Vppg tied together 10 of 29 Rev 1 03 June 2009 ELECTRONICS Unbuffered SoDIMM DDR3 SDRAM 10 0 AC amp DC Input Measurement Levels 10 1 AC amp DC Logic Input Levels for Single ended Signals Single Ended AC and DC input levels for Command and Address DDR3 800 1066 DDR3 1333 Symbol Parameter Unit Notes Min Max Min Max Vin ca DC DC input logic high Vrer 100 Vpp Vngr 100 Von mV 1 Vit ca DC DC input logic low Vss Vngr 100 Vss Vngr 100 mV 1 Vin ca AC AC input logic high Ver 175 Vngr 175 mV 1 2 Vu cA AC AC input logic low Vngr 175 Vngr 175 mV 1 2 Vin cA AC 150 AC input logic high Vngr 150 Vngr 150 mV 1 2 Vit ca AC150 AC input logic low Vngr 150 S Vggr 150 mV 12 Reference Voltage for ADD Vi DC j 0 49 V 0 51 V 0 49 V 0 51 V V 3 4 RErcA DC CMD
29. dge 27 The tlS base AC150 specifications are adjusted from the tlS base specification by adding an additional 100 ps of derating to accommodate for the lower alter nate threshold of 150 mV and another 25 ps to account for the earlier reference point 175 mv 150 mV 1 V ns 28 Pulse width of a input signal is defined as the width between the first crossing of VeeF DC and the consecutive crossing of Vgge DC 29 tDQSL describes the instantaneous differential input low pulse width on DQS DQS as measured from one falling edge to the next consecutive rising edge 30 tDQSH describes the instantaneous differential input high pulse width on DQS DQS as measured from one rising edge to the next consecutive falling edge 31 tDQSH act tDQSL act 1 tCK act with tXYZ act being the actual measured value of the respective timing parameter in the application 32 tDSH act tDSS act 1 tCK act with tXYZ act being the actual measured value of the respective timing parameter in the application 28 of 29 Rev 1 03 June 2009 ELECTRONICS Unbuffered SoDIMM DDR3 SDRAM 16 0 Physical Dimensions 16 1 256Mbx8 based 512Mx64 Module 2 Ranks Units Millimeters 67 60 o 10 C A B 63 60 gt l Max 3 8 30 00 0 15 20 00
30. e measured from a command address signal CKE CS RAS CAS WE ODT BAO AO Al etc transition edge to its respective clock signal CK CK crossing The spec values are not affected by the amount of clock jitter applied i e tJIT per tJIT cc etc as the setup and hold are relative to the clock signal crossing that latches the command address That is these param eters should be met whether clock jitter is present or not Specific Note c These parameters are measured from a data strobe signal DQS L U DQS L U crossing to its respective clock signal CK CK cross ing The spec values are not affected by the amount of clock jitter applied i e tJIT per tJIT cc etc as these are relative to the clock signal crossing That is these parameters should be met whether clock jitter is present or not Specific Note d These parameters are measured from a data signal DM L U DQ L U 0 DQ L U 1 etc transition edge to its respective data strobe signal DQS L U DQS L U crossing Specific Note e For these parameters the DDR3 SDRAM device supports tnPARAM nCK RU tPARAM ns tCK avg ns which is in clock cycles assuming all input clock jitter specifications are satisfied For example the device will support tnRP RU tRP tCK avg which is in clock cycles if all input clock jitter specifications are met This means For DDR3 800 6 6 6 of which tRP 15ns the device will support tnRP RU tRP tCK avg 6 as long as
31. f 29 Rev 1 03 June 2009 ELECTRONICS Unbuffered SoDIMM DDR3 SDRAM 14 0 Electrical Characteristics and AC timing 0 C lt Tcase lt 95 C Vopa 1 5V 0 075V Vpp 1 5V 0 075V 14 1 Refresh Parameters by Device Density Parameter Symbol 1Gb 2Gb 4Gb 8Gb Units Note All Bank Refresh to active refresh cmd time tRFC 110 160 300 350 ns Date TcASE lt 85 C 7 8 7 8 7 8 7 8 us Average periodic refresh interval tREFI 85 C lt TcASE lt 95 C 3 9 3 9 3 9 3 9 us 1 Note 1 Users should refer to the DRAM supplier data sheet and or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this material 14 2 Speed Bins and CL tRCD tRP tRC and tRAS for Corresponding Bin Speed DDR3 1066 DDR3 1333 Bin CL tRCD tRP 7 7 7 9 9 9 Units Note Parameter min min CL 7 9 tCK tRCD 13 13 13 5 ns tRP 13 13 13 5 ns tRAS 37 5 36 ns tRC 50 63 49 5 ns tRRD 7 5 6 0 ns tFAW 37 5 30 ns 21 of 29 Rev 1 03 June 2009 ELECTRONICS Unbuffered SoDIMM DDR3 SDRAM 14 3 Speed Bins and CL tRCD tRP tRC and tRAS for corresponding Bin DDR3 SDRAM Speed Bins include tCK tRCD tRP tRAS and tRC for each corresponding bin DDR3 1066 Speed Bins
32. f 29 Rev 1 03 June 2009 ELECTRONICS Unbuffered SoDIMM 10 3 AC and DC Logic Input Levels for Differential Signals 10 3 1 Differential Signals Definition r4 tDVAC DDR3 SDRAM A Vi DIFF AC MIN Vu DIEEMIN 0 0 half cycle Vi DIFF MAX Vi DIFF AC MAX Differential Input Voltage i e DQS DQS CK CK time gt Figure 2 Definition of differential ac swing and time above ac level tDVAC 10 3 2 Differential Swing Requirement for Clock CK CK and Strobe DQS DQS DDR3 800 1066 1333 Symbol Parameter unit Note min max Vom differential input high 0 2 note 3 V 1 Vit airt differential input low note 3 0 2 V 1 VindifrlAC differential input high ac 2 x Vi AC Vger note 3 V 2 ViLai AC differential input low ac note 3 2 x Vrer ViL AC V 2 Notes 1 Used to define a differential signal slew rate 2 for CK CK use Vun AC of ADD CMD and Vrerca for DQS DQS DQSL DASL DQSU DQSU use Vu AC of DQs and Vggrpo if a reduced ac high or ac low level is used for a signal group then the reduced level applies also here 3 These values are not defined however they single ended signals CK CK DQS DQS DQSL DQSL DQSU DQSU need to be within the respective limits Vj DC max Vi DC min for single ended signals as well as the limitations for overshoot and undershoot Refer to overshoot and Under sheet Specification Al
33. idth tDQSL 0 45 0 55 0 45 0 55 tCK avg 29 31 DQS DQS differential input high pulse width tDQSH 0 45 0 55 0 45 0 55 tCK avg 30 31 Das DOS rising edge to CK CK rising edge tDQSS 0 25 0 25 0 25 0 25 tCK avg C Dos DOS falling edge setup time to CK CK rising edge tDSS 0 2 0 2 tCK avg c 32 DQS DQS falling edge hold time to CK CK rising edge tDSH 0 2 0 2 tCK avg c 32 24 of 29 Rev 1 03 June 2009 ELECTRONICS Unbuffered SoDIMM Timing Parameters by Speed Bin Cont DDR3 SDRAM ELECTRONICS Speed DDR3 1066 DDR3 1333 Units Note Parameter Symbol MIN MAX MIN MAX Command and Address Timing DLL locking time tDLLK 512 512 nCK internal READ Command to PRECHARGE Command delay RTP 4nCK 7 ns 4nCK 7 5ns e max max Delay from start of internal write transaction to internal read command WTR 4nCK 7 5ns 4nCK 7 5ns e 18 WRITE recovery time tWR 15 15 ns e 18 Mode Register Set command cycle time MRD 4 4 nCK Mode Register Set command update delay tMOD 12nCK 1 5ns 12nCK 1 5ns CAS to CAS command delay CCD 4 4 nCK Auto precharge write recovery precharge time tDAL min WR roundup tRP tCK AVG nCK Multi Purpose Register Recovery Time tMPRR 1 1 nCK 22 ACTIVE to PRECHARGE command period RAS See Speed Bins and CL tRCD
34. ile ADD CMD and DQ signal requirements are with respect to Ver the single ended components of differential signals have a requirement with respect to Vpp 2 this is nominally the same The transition of single ended signals through the ac levels is used to measure setup time For single ended components of differential signals the requirement to reach Vsg max Vseymin has no bearing on timing but adds a restriction on the common mode characteristics of these signals Single ended levels for CK DQS DQSL DQSU CK DQS DQSL or DQSU Symbol Parameter Min DOR3800 1066 1333 Max Unit Notes Un Single ended high level for strobes Vpp 2 0 175 Note3 V 1 Single ended high level for CK CK Vpp 2 0 175 Note3 V 1 Ven Single ended low level for strobes Note3 Vpp 2 0 175 V 1 Single ended low level for CK CK Note3 Vpp 2 0 175 V 1 Notes 1 For CK CK use V y V AC of ADD CMD for strobes DOS DOS DQSL DQSL DQSU DQSU use V V AC of DQs 2 VI AC IVi AC for DQs is based on Vggepo Viu AC Vi AC for ADD CMD is based on Vperca if a reduced ac high or ac low level is used for a signal group then the reduced level applies also here m 3 These values are not defined however the single ended signals CK CK DQS DQS DQSL DQSL DQSU DQSU need to be within the respective limits Vj DC max Vu DC min for single ended signals as well as the limitations for overshoot and undershoot Refer to
35. ing for single ended slew rate definitions for data signals 10 5 Slew rate definition for Differential Input Signals Input slew rate for differential signals CK CK and DOS DQS are defined and measured as shown in below Differential input slew rate definition Measured Description Defined b n From To Y Mugs a Na Differential input slew rate for rising edge CK CK and DQS DQS Vii diffmax V IHdiffmin T Tham elta i n mu Mii Vivas Differential input slew rate for falling edge CK CK and DQS DQS ViHdiffmin ViLdiifmax T in Tam elta TFdi Note The differential signal i e CK CK and DOS DQS must be linear between these thresholds delta TFdiff delta TRdiff ViHdiffmin Vit diffmax Figure 5 Differential input slew rate definition for DQS DQS and CK CK ELECTRONICS 15 of 29 Rev 1 03 June 2009 Unbuffered SoDIMM DDR3 SDRAM 11 0 AC amp DC Output Measurement Levels 11 1 Single Ended AC and DC Output Levels Single Ended AC and DC output levels Symbol Parameter DDR3 800 1066 1333 Units Notes Vou DC DC output high measurement level for IV curve linearity 0 8 x VDDQ Vom DC DC output mid measurement level for IV curve linearity 0 5 x VDDQ Vo DC DC output low measurement level for IV curve linearity 0 2 x VDDQ V VoH AC AC output high measurement level for output SR Ver 0 1 x Vppo V 1 Vo AC
36. lock On tCK CL AC Timing Table BL Sal AL 0 CS High between WR Command Address Bank Address Inputs partially tog gling Data IO seamless write data burst with different data between one burst and the next one DM stable at 0 Bank Activity all banks open WR com mands cycling through banks 0 0 1 1 2 2 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at HIGH Burst Refresh Current IDD5B CKE High External clock On tCK CL nRFC AC Timing Table BL 88 AL 0 CS High between REF Command Address Bank Address Inputs par tially toggling according to Table 38 Data lO FLOATING DM stable at 0 Bank Activity REF command every nRFC see Table 38 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Self Refresh Current Normal Temperature Range IDD6 TCASE 0 85 C Auto Self Refresh ASR Disabled Self Refresh Temperature Range SRT Normal CKE Low External clock Off CK and CK LOW CL AC Timing Table BL 89 AL 0 CS Command Address Bank Address Data IO FLOATING DM stable at 0 Bank Activity Self Refresh opera tion Output Buffer and RTT Enabled in Mode Registers ODT Signal FLOATING 18 of 29 Rev 1 03 June 2009 ELECTRONICS Unbuffered SoDIMM DDR3 SDRAM Symbol Description Self Refresh Current Extended Temperature Range optional IDD6ET TCASE 0 95 C Auto Self Refresh ASR Disabled Self Refresh Temperat
37. lowed time before ringback tDVAC for CK CK and DQS DQS Slew Rate Vins tDVAC ps Nu al AC 350mV tDVAC ps Nu oml AC 300mV min max min max gt 4 0 75 175 4 0 57 170 3 0 50 167 2 0 38 163 1 8 34 162 1 6 29 161 1 4 22 159 1 2 13 155 1 0 0 150 lt 1 0 0 150 13 of 29 ELECTRONICS Rev 1 03 June 2009 Unbuffered SoDIMM DDR3 SDRAM 10 3 3 Single ended Requirements for Differential Signals Each individual component of a differential signal CK DOS DQSL DQSU CK DOS DQSL or DQSU has also to comply with certain requirements for single ended signals CK and CK have to approximately reach Vggymin Vsg max approximately equal to the ac levels V y AC V AC for ADD CMD signals in every half cycle DOS DQSL DQSU DOS DQSL have to reach Vsgymin Map max approximately the ac levels Vj AC Vij AC for DQ signals in every half cycle proceeding and following a valid transition Note that the applicable ac levels for ADD CMD and DQ s might be different per speed bin etc E g if Vij150 AC Vi 150 AC is used for ADD CMD signals then these ac levels apply also for the single ended signals CK and CK Vpp or Vppa VsEH min VsEH Vpp 2 or Vppo 2 CK or DOS VseL max VSEL ss OF Vssq time Figure 3 Single ended requirement for differential signals Note that wh
38. min tJIT per act min 0 9 x tCK avg act tUlT per act min 0 9 x 2500 ps 72 ps 2178 ps Similarly tQH min derated OH min tJIT per act min 0 38 x tCK avg act tUlT per act min 0 38 x 2500 ps 72 ps 878 ps Caution on the min max usage 27 of 29 Rev 1 03 June 2009 ELECTRONICS Unbuffered SoDIMM DDR3 SDRAM 15 2 Timing Parameter Notes 1 Actual value dependant upon measurement level definitions which are TBD 2 Commands requiring a locked DLL are READ and RAP and synchronous ODT commands 3 The max values are system dependent 4 WR as programmed in mode register 5 Value must be rounded up to next higher integer value 6 There is no maximum cycle time limit besides the need to satisfy the refresh interval tREFI 7 For definition of RTT turn on time tAON see Device Operation amp Timing Deagram Datasheet 8 For definition of RTT turn off time tAOF see Device Operation amp Timing Deagram Datasheet 9 tWR is defined in ns for calculation of tWRPDEN it is necessary to round up tWR tCK to the next integer 10 WR in clock cycles as programmed in MRO 11 The maximum read postamble is bound by tDQSCK min plus tQSH min on the left side and tHZ DQS max on the right side Device Operation 12 Output timing deratings are relative to the SDRAM input clock When the device is operated with input clock jitter this parameter needs to be derated by TBD 13 Value is only valid for RON34 14
39. n for DQ DM DQS and DQS signals if enabled via the DDR3 SDRAM mode register During a Bank Activate command cycle defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK During a Read or Write command cycle defines the column address when sampled at the AO0 A9 cross point of the rising edge of CK and falling edge of CK In addition to the column address AP is used to invoke A10 AP autoprecharge operation at the end of the burst read or write cycle If AP is high autoprecharge is selected and BAO A11 Input BAn defines the bank to be precharged If AP is low autoprecharge is disabled During a Precharge command cycle A12 BC AP is used in conjunction with BAO BAn to control which bank s to precharge If AP is high all banks will be pre A13 A15 charged regardless of the state of BAO BAn inputs If AP is low then BAO BAn are used to define which bank to pre charge A12 BC is sampled during READ and WRITE commands to determine if burst chop on the fly will be performed HIGH no burst chop LOW burst chopped DQ0 DQ63 1 0 Data Input Output pins DM0 DM7 impii The data write masks associated with one data byte In Write mode DM operates as a byte mask by allowing input p data to be written if it is low but blocks the write operation if it is high In Read mode DM lines have no effect The data strobes associated with one data byte sourced with data transfers In Write mode the data strobe is DQS
40. nonononcnnananannnnnnarannnnnnnnos 14 10 3 4 Differential Input Cross Point Voltage e eeeeeeeeeeeee ENER ERR RE ENEE EEN ER ER RE ENEE KEEN RER nnn 15 10 4 Slew Rate Definition for Single Ended Input Signals RER ERERER KEREN ERR R KREE ENEE RRE R KREE ER ENEE REENEN 15 10 5 Slew rate definition for Differential Input Signals cocococononenenenencnnananananonononononrnnananonnnnnnnnanarnrannnnos 15 11 0 AC amp DC Output Measurement Levels eeeeseseseseeeeeeeeeee nennen nennen nnns 16 11 1 Single Ended AC and DC Output Levels eeeeeeeeeeee eee enne nnne n nnne nnn nnn n nnn nnn nnn n nnn nnn 16 11 2 Differential AC and DC Output Levels iii A nnmnnn nnmnnn nennen 16 11 3 Single ended Output Slew Rate 4 ceeeeeeeee eese eene nennen nnn nnns n nnn nn nnn nnnm nnmnnn nnmnnn nn nnn 16 11 4 Differential Output Slew E 17 12 0 IDD specification definition miii ta 18 12 1 IDD Ez d exp Eom Ces EE ra S EES ENER NEE EE dE Ee 20 13 0 Input Output Capacitance AAA 20 13 1 2RX16 1GB SODIMM EE 20 14 0 Electrical Characteristics and AC timing eeeeeeeeneneeeeeeneeneennennnennnnennnnnnnnnn 21 14 1 Refresh Parameters by Device Density REENEN nnne nnn rra nnn nn nnn nnn nnn nnn nn nnn 21 14 2 Speed Bins and CL tRCD tRP tRC and tRAS for Corresponding Bin eeueeese 21 14 3 Speed Bins and CL tRCD tRP tRC and tRA
41. ry tMRSPDEN tMOD min tMOD min ODT Timing ODT high time without write command or with write command and BC4 ODTH4 4 4 nCK ODT high time with Write command and BL8 ODTH8 6 6 nCK Asynchronous RTT turn on delay Power Down with DLL frozen tAONPD 2 8 5 2 8 5 ns Asynchronous RTT turn off delay Power Down with DLL frozen tAOFPD 2 8 5 2 8 5 ns ODT turn on tAON 300 300 250 250 ps Tf RTT NOM and RTT WR turn off time from ODTLoff reference tAOF 0 3 0 7 0 3 0 7 tCK avg DI RTT dynamic change skew tADC 0 3 0 7 0 3 0 7 tCK avg f Write Leveling Timing First DQS pulse rising edge after tDQSS margining mode is programmed tWLMRD 40 40 tCK 3 DQS DQS delay after DOG margining mode is programmed tWLDQSEN 25 25 tCK 3 Setup time for tDQSS latch tWLS 245 195 ps m leveling hold time from rising DOS DOS crossing to rising CK CK cross tWLH 245 195 ps Write leveling output delay tWLO 0 9 0 9 ns Write leveling output error tWLOE 0 2 0 2 ns 26 of 29 Rev 1 03 June 2009 Unbuffered SoDIMM DDR3 SDRAM 15 1 Jitter Notes Specific Note a Unit tCK avg represents the actual tCK avg of the input clock under operation Unit nCK represents one clock cycle of the input clock counting the actual clock edges ex tMRD 4 nCK means if one Mode Register Set command is registered at Tm another Mode Register Set command may be registered at Tm 4 even if Tm 4 Tm is 4 x tCK avg tERR Aper min Specific Note b These parameters ar
42. se 3 SCL Serial Presence Detect SPD Clock Input 1 Total 204 SDA SPD Data Input Output 1 SA0 SA1 SPD Address 2 The Vpp and Vppg pins are tied common to a single power plane on these designs ELECTRONICS 7 of 29 Rev 1 03 June 2009 Unbuffered SoDIMM DDR3 SDRAM 6 0 Input Output Functional Description Symbol Type Function CKO CK1 The system clock inputs All address and command lines are sampled on the cross point of the rising edge of CK and DD DTP Input falling edge of CK A Delay Locked Loop DLL circuit is driven from the clock inputs and output timing for read opera CKO CK1 i tions is synchronized to the input clock CKE0 CKE1 ioui Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low By deactivating the clocks p CKE low initiates the Power Down mode or the Self Refresh mode _ Enables the associated DDR3 SDRAM command decoder when low and disables the command decoder when high S0 S1 Input When the command decoder is disabled new commands are ignored but previous operations continue Rank 0 is selected by S0 Rank 1 is selected by S1 E When sampled at the cross point of the rising edge of CK and falling edge of CK signals CAS RAS and WE define RAS CAS WE Input the operation to be executed by the SDRAM BA0 BA2 Input Selects which DDR3 SDRAM internal bank of eight is activated ODTO ODT1 Input Asserts on die terminatio
43. ss 71 Vss 72 Vss 139 Vss 140 DQ38 3 Vss 4 DQ4 KEY 141 DQ34 142 DQ39 5 DQO 6 DQ5 73 CKEO 74 CKE1 143 DQ35 144 Vss 7 Dat 8 Vss 75 Vpp 76 Vpp 145 Vss 146 DQ44 9 Vss 10 DQSO 77 NC 78 A153 147 DQ40 148 DQ45 11 DMO 12 DQSO 79 BA2 80 A143 149 DQ41 150 Vss 13 Vss 14 Vss 81 Von 82 Vpp 151 Vss 152 DQS5 15 DQ2 16 DQ6 83 A12 BC 84 A11 153 DM5 154 DQS5 17 DQ3 18 DQ7 85 A9 86 A7 155 Vss 156 Vss 19 Vss 20 Vss 87 Vpp 88 Vpp 157 DQ42 158 DQ46 21 DQ8 22 DQ12 89 A8 90 A6 159 DQ43 160 DQ47 23 DQ9 24 DQ13 91 A5 92 A4 161 Vss 162 Vss 25 Vss 26 Vss 93 Vpp 94 Vpp 163 DQ48 164 DQ52 27 DQS1 28 DM1 95 A3 96 A2 165 DQ49 166 DQ53 29 DOS1 30 RESET 97 A1 98 A0 167 Vss 168 Vas 31 Vss 32 Vss 99 Vpp 100 Vpp 169 DQS6 170 DM6 33 DQ10 34 DQ14 101 CKO 102 CK1 171 DQS6 172 Vss 35 DQ11 36 DQ15 103 CKO 104 CK1 173 Vss 174 DQ54 37 Vss 38 Vss 105 Vpp 106 Vpp 175 DQ50 176 DQ55 39 DQ16 40 DQ20 107 A10 AP 108 BA1 177 DQ51 178 Vss 41 DQ17 42 DQ21 109 BAO 110 RAS 179 Vss 180 DQ60 43 Vss 44 Vss 111 Vpp 112 Vpp 181 DQ56 182 DQ61 45 DQs2 46 DM2 113 WE 114 So 183 DQ57 184 Vss 47 DQS2 48 Vss 115 CAS 116 ODTO 185 Vss 186 DQS7 49 Vss 50 DQ22 117 Vpp 118 Vpp 187 DM7 188 DQS7 50 DQ18 52 DQ23 119 A133 120 ODT1 189 Vss 190 Vss 53 DQ19 54 Vss 121 Si 122 NC 191 DQ58 192 DQ62 55 Vss 56 DQ28 123 Vpp 124 Vpp 193 DQ59 194 DQ63 57 DQ24 58 DQ29 125 TEST 126 VREFCA 195 Vss 196 Vss 59 DQ25 60 Vss 127 Vss 128 Vss 197 SA0 198 NC 61 Vss 62 DQS3 129 DQ32 130 DQ36 199 Vppspp 200 SDA 63 DM3 64 DQS3 131 DQ33 132 DQ37 20
44. the input clock jitter specifications are met i e Precharge command at Tm and Active command at Tm 6 is valid even if Tm 6 Tm is less than 15ns due to input clock jitter Specific Note f When the device is operated with input clock jitter this parameter needs to be derated by the actual tERR mper act of the input clock where 2 lt m lt 12 output deratings are relative to the SDRAM input clock For example if the measured jitter into a DDR3 800 SDRAM has tERR mper act min 172 ps and tERR mper act max 193 ps then tDQSCK min derated tDQSCK min tERR mper act max 400 ps 193 ps 593 ps and tDQSCK max derated tDQSCK max tERR mper act min 400 ps 172 ps 572 ps Similarly tLZ DQ for DDR3 800 derates to tLZ DQ min derated 800 ps 193 ps 993 ps and tLZ DQ max derated 400 ps 172 ps 572 ps Caution on the min max usage Note that tERR mper act min is the minimum measured value of tERR nper where 2 lt n lt 12 and tERR mper act max is the maximum measured value of tERR nper where 2 lt n lt 12 Specific Note g When the device is operated with input clock jitter this parameter needs to be derated by the actual tJIT per act of the input clock out put deratings are relative to the SDRAM input clock For example if the measured jitter into a DDR3 800 SDRAM has tCK avg act 2500 ps tJIT per act min 72 ps and tJIT per act max 93 ps then tRPRE min derated tRPRE
45. ure Range SRT Extended CKE Low External clock Off CK and CK LOW CL AC Timing Table BL 89 AL 0 CS Command Address Bank Address Data IO FLOATING DM stable at 0 Bank Activity Extended Tempera ture Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal FLOATING Auto Self Refresh Current optional IDD6TC TCASE 0 95 C Auto Self Refresh ASR Enabled Self Refresh Temperature Range SRT Normal CKE Low External clock Off CK and CK LOW CL AC Timing Table BL 89 AL 0 CS Command Address Bank Address Data IO FLOATING DM stable at 0 Bank Activity Auto Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal FLOATING Operating Bank Interleave Read Current CKE High External clock On tCK nRC nRAS nRCD nRRD nFAW CL AC Timing Table BL 83 AL CL 1 CS High between ACT and RDA Com IDD7 mand Address Bank Address Inputs partially toggling Data IO read data bursts with different data between one burst and the next one DM stable at 0 Bank Activity two times interleaved cycling through banks 0 1 7 with different addressing see Table 39 Output Buffer and RTT Enabled in Mode Reg isters ODT Signal stable at 0 a Burst Length BL8 fixed by MRS set MRO A 1 0 00B b Output Buffer Enable set MR1 A 12 0B set MR1 A 5 1 01B RTT_Nom enable set MR1 A 9 6 2 011B RTT_Wr enable set MR2 A 10 9 10B
46. urst and MRS which reloads MPR or disables MPR function 23 One ZQCS command can effectively correct a minimum of 0 5 96 ZQCorrection of RON and RTT impedance error within 64 nCK for all speed bins assuming the maximum sensitivities specified in the Output Driver Voltage and Temperature Sensitivity and ODT Voltage and Temperature Sensitivity tables The appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters One method for calculating the interval between ZQCS commands given the temperature Tdriftrate and voltage Vdriftrate drift rates that the SDRAM is sub ject to in the application is illustrated The interval could be defined by the following formula ZQCorrection TSens x Tdriftrate VSens x Vdriftrate where TSens max dRTTdT dRONdTM and VSens max dRTTdV dRONdVM define the SDRAM temperature and voltage sensitivities For example if TSens 1 5 C VSens 0 1596 mV Tdriftrate 1 C sec and Vdriftrate 15 mV sec then the interval between ZQCS commands is calcu lated as 0 5 1 5 x 1 0 15 x 15 0 133 128ms 24 n from 13 cycles to 50 cycles This row defines 38 parameters 25 tCH abs is the absolute instantaneous clock high pulse width as measured from one rising edge to the following falling edge 26 tCL abs is the absolute instantaneous clock low pulse width as measured from one falling edge to the following rising e
47. utput Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Precharge Standby ODT Current DD2NT CKE High External clock On tCK CL AC Timing Table BL 89 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling Data lO FLOATING DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal toggling DDQ2NT Precharge Standby ODT IDDQ Current optional Same definition like for IDD2NT however measuring IDDQ current instead of IDD current Precharge Power Down Current Slow Exit IDD2PO CKE Low External clock On tCK CL AC Timing Table BL 89 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO FLOATING DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Precharge Power Down Mode Slow Exit Precharge Power Down Current Fast Exit IDD2P4 CKE Low External clock On tCK CL AC Timing Table BL 89 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data 10 FLOATING DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Precharge Power Down Mode Fast Exit Precharge Quiet Standby Current IDD2Q CKE High External clock On tCK CL AC Timing Table BL 8 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO FLOATING

Samsung M471B5273BH1-CF8 memory module

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