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Lenovo Intel Xeon E5205

1. Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 7 of 20 Sheet 8 of 20 Pin Name N M o Direction Pin Name iig Ku dnd Direction RESERVED AM2 VCC AD8 Power Other RESET G23 Common Clk Input VCC AE11 Power Other RS0 B3 Common Clk Input VCC AE12 Power Other RS1 F5 Common Clk Input VCC AE14 Power Other RS2 A3 Common Clk Input VCC AE15 Power Other RSP H4 Common Clk Input VCC AE18 Power Other SKTOCC AE8 Power Other Output VCC AE19 Power Other SMI P2 CMOS ASync Input VCC AE21 Power Other STPCLK M3 CMOS ASync Input VCC AE22 Power Other TCK AE1 TAP Input VCC AE23 Power Other TDI AD1 TAP Input VCC AE9 Power Other TDO AF1 TAP Output VCC AF11 Power Other TESTHI08 G3 Power Other Input VCC AF12 Power Other TESTHI09 G4 Power Other Input VCC AF14 Power Other TESTHI10 P1 Power Other Input VCC AF15 Power Other TESTHI11 L2 Power Other Input VCC AF18 Power Other TESTHI12 AE3 Power Other Input VCC AF19 Power Other THERMTRIP M2 Open Drain Output VCC AF21 Power Other TMS AC1 TAP Input VCC AF22 Power Other TRDY E3 Common Clk Input VCC AF8 Power Other TRST AG1 TAP Input VCC AF9 Power Other VCC AA8 Power Other VCC AG11 Power Other VCC AB8 Power Other VCC AG12 Power Other VCC AC23 Power Other VCC AG14 Power Other VCC AC24 Power Other VCC AG15 Power Other VCC AC25 Power Other VCC AG18 Power Other VCC AC26 Power Other VCC AG
2. Power W Tcase_max CC 0 42 9 5 44 3 10 45 8 15 47 2 20 48 7 25 50 1 30 51 6 35 53 0 40 54 5 45 55 9 50 57 4 55 58 8 60 60 2 65 61 7 70 63 1 75 64 6 80 66 0 Dual Core I ntel Xeon Processor L5200 Series Thermal Specifications Core Thermal Minimum Maximum Design Power TcasE TcasE Notes Frequency W CO GC Launch to FMB 40 5 See Figure 6 3 Table 6 7 1 2 3 4 5 Notes 1 These values are specified at Vcc max for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds Vcc MAX at specified ICC Please refer to the loadline specifications in Section 2 13 i 2 Thermal Design Power TDP should be used for processor thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at maximum Tease 3 These specifications are based pre silicon estimates and simulations These specifications will be updated with characterized data from silicon measurements in a future release of this document L5200 Series may be shipped under multiple VIDs for each frequency 5 FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements Power specifications are defined at all VIDs found in Table 2 12 The Dual Core Intel Xeon Processor Therma
3. 64 intel Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 17 of 20 Sheet 18 of 20 Pin No Pin Name e Direction Pin No Pin Name m Direction M3 STPCLK CMOS Async Input R2 VSS Power Other M30 VCC Power Other R23 vss Power Other M4 A07 Source Sync Input Output R24 vss Power Other M5 A03 Source Sync Input Output R25 VSS Power Other M6 REQ2 Source Sync Input Output R26 vss Power Other M7 VSS Power Other R27 VSS Power Other M8 VCC Power Other R28 VSS Power Other N1 PWRGOOD Power Other Input R29 VSS Power Other N2 IGNNE CMOS Async Input R3 FERR PBE Open Drain Output N23 VCC Power Other R30 VSS Power Other N24 VCC Power Other R4 A08 Source Sync Input Output N25 VCC Power Other R5 vss Power Other N26 VCC Power Other R6 ADSTBO Source Sync Input Output N27 VCC Power Other R7 VSS Power Other N28 VCC Power Other R8 VCC Power Other N29 VCC Power Other T1 RESERVED N3 VSS Power Other T2 RESERVED N30 VCC Power Other T23 VCC Power Other N4 A36 Source Sync Input Output T24 VCC Power Other N5 RESERVED T25 VCC Power Other N6 VSS Power Other T26 VCC Power Other N7 VSS Power Other T27 VCC Power Other N8 VCC Power Other T28 VCC Power Other P1 TESTHI10 Power Other Input T29 VCC Power Other P2 SMI CMOS
4. Icc A Vcc Max V Vcc Typ V Vcc Min V Notes 1 2 3 0 VID 0 000 VID 0 015 VID 0 030 5 VID 0 006 VID 0 021 VID 0 036 10 VID 0 013 VID 0 028 VID 0 043 15 VID 0 019 VID 0 034 VID 0 049 20 VID 0 025 VID 0 040 VID 0 055 25 VID 0 031 VID 0 046 VID 0 061 30 VID 0 038 VID 0 053 VID 0 068 35 VID 0 044 VID 0 059 VID 0 074 40 VID 0 050 VID 0 065 VID 0 080 45 VID 0 056 VID 0 071 VID 0 086 6 50 VID 0 063 VID 0 077 VID 0 093 6 55 VID 0 069 VID 0 084 VID 0 099 5 5 60 VID 0 075 VID 0 090 VID 0 105 5 6 65 VID 0 081 VID 0 096 VID 0 111 5 6 70 VID 0 087 VID 0 103 VID 0 118 5 6 75 VID 0 094 VID 0 109 VID 0 124 5 6 80 VID 0 100 VID 0 115 VID 0 130 4 5 6 85 VID 0 106 VID 0 121 VID 0 136 4 5 6 90 VID 0 113 VID 0 128 VID 0 143 4 5 6 Notes 1 The Vcc min and Vcc max loadlines represent static and transient limits Please see Section 2 13 2 for Mee overshoot specifications 2 This table is intended to aid in reading discrete points on Figure 2 5 and Figure 2 6 31 Figure 2 5 4 5 6 Dual Core Intel Xeon Processor 5200 Series Electrical Specifications The loadlines specify voltage limits at the die measured at the VCC_DIE_SENSE and VSS DIE SENSE lands and across the VCC DIE SENSE2 and VSS DIE SENSE2 lands Voltage regulation feedback for voltage regulator circuits must also be
5. Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 13 of 20 Sheet 14 of 20 Pin No Pin Name ue aa Direction Pin No Pin Name Di Direction F10 VSS Power Other G2 RESERVED F11 D23 Source Sync Input Output G20 DSTBN2 Source Sync Input Output F12 D24 Source Sync Input Output G21 D44 Source Sync Input Output F13 VSS Power Other G22 D47 Source Sync Input Output F14 D28 Source Sync Input Output G23 RESET Common Clk Input F15 D30 Source Sync Input Output G24 RESERVED F16 VSS Power Other G25 RESERVED F17 D37 Source Sync Input Output G26 RESERVED F18 D38 Source Sync Input Output G27 RESERVED F19 VSS Power Other G28 BCLK1 CIk Input F2 RESERVED G29 BSELO CMOS Async Output F20 D41 Source Sync Input Output G3 TESTHI08 Power Other Input F21 D43 Source Sync Input Output G30 BSEL2 CMOS Async Output F22 VSS Power Other G4 TESTHI 09 Power Other Input F23 RESERVED G5 PECI Power Other Input Output F24 RESERVED G6 RESERVED F25 RESERVED G7 DEFER Common Clk Input F26 RESERVED G8 BPRI A Common Clk Input F27 VTT_SEL Power Other Output G9 D16 Source Sync Input Output F28 BCLK0 CIk Input H1 GTLREF_DATA Power Other Input F29 RESERVED H10 VSS Power Other F3 BRO Common Clk Input Output H11 VSS Power Other F30 VIT Power Other H12 VSS Power Other F4 VSS Power Other H13 VSS Power Other F5 RS1 Common Clk Input H14 VSS Power Other F6 RESERVED H1
6. EE enee gt a i ssa 550 mV E 500 t 550 0 5 VHavg 700 o 450 a 2 400 E 250 0 5 VHavg 700 350 300 250 200 T T T T T T T T T T T T T T T T T T 1 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg mV Figure 2 12 Differential Rising and Falling Edge Rates Rise Edge Rate Fall Edge Rate gt REFCLK minus See E U Gu xu l ke ea cu ka eu s L i MV e eene o EE RENAN SEE L I i I I E t 4 Differential Measurement Points for Rise and Fall Time 38 Mechanical Specifications n te 3 Figure 3 1 3 1 Note Mechanical Specifications The Dual Core Intel Xeon Processor 5200 Series is packaged in a Flip Chip Land Grid Array FC LGA package that interfaces to the baseboard via a LGA771 socket The package consists of a processor core mounted on a pinless substrate with 771 lands An integrated heat spreader IHS is attached to the package substrate and core and serves as the interface for processor component thermal solutions such as a heatsink Figure 3 1 shows a sketch of the processor package components and how they are assembled together Refer to the LGA771 Socket Design Guidelines for complete details on the LGA771 socket The package components shown in Figure 3 1 include the following Integrated Heat Spreader IHS Thermal Interface Material TI M Processor Core
7. A 35 17 ADSTB1 AP 1 0 1 0 AP 1 0 Address Parity are driven by the request initiator along with ADS A 37 3 and the transaction type on the REQ 4 0 signals A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low This allows parity to be high when all the covered signals are high AP 1 0 must be connected to the appropriate pins of all Dual Core Intel Xeon Processor 5200 Series FSB agents The following table defines the coverage model of these signals Request Signals Subphase 1 Subphase 2 A 37 24 APO AP1 A 23 3 AP1 APO REQ 4 0 AP1 APO 67 Bi intel Table 5 1 Signal Definitions Sheet 2 of 8 Name Type Description Notes BCLK 1 0 l The differential bus clock pair BCLK 1 0 Bus Clock determines the 3 FSB frequency All processor FSB agents must receive these signals to drive their outputs and latch their inputs All external timing parameters are specified with respect to the rising edge of BCLK0 crossing Vcnoss BINIT 1 0 BINIT Bus Initialization may be observed and driven by all 3 processor FSB agents and if used must connect the appropriate pins of all such agents If the BINIT driver is enabled during power on configuration BINIT is asserted to signal any bus condition that prevents reliable future operation If BINIT ob
8. Figure 8 2 Boxed Dual Core Intel Xeon Processor 5200 Series 2U Passive Heat Sink 100 El Boxed Processor Specifications n te Figure 8 3 8 2 8 2 1 2U Passive Dual Core Intel Xeon Processor 5200 Series Thermal Solution Exploded View a Heat sink screw springs TAT Heat sink e Heat sink screws i o Heat sink standoffs Thermal Interface Material Motherboard an n processor i r Protective Tape d CEK spring Chassis pan Notes 1 The heat sinks represented in these images are for reference only and may not represent the final boxed processor heat sinks 2 The screws springs and standoffs will be captive to the heat sink This image shows all of the components in an exploded view 3 It is intended that the CEK spring will ship with the base board and be pre attached prior to shipping Mechanical Specifications This section documents the mechanical specifications of the boxed processor Boxed Processor Heat Sink Dimensions CEK The boxed processor will be shipped with an unattached thermal solution Clearance is required around the thermal solution to ensure unimpeded airflow for proper cooling The physical space requirements and dimensions for the boxed processor and assembled heat sink are shown in Figure 8 4 through Figure 8 8 Figure 8 9 through Figure 8 10 are the mechanical drawings for the 4 pin b
9. 80 75 70 65 60 Sustained Current A 50 0 01 0 1 1 10 100 1000 Time Duration s Notes 1 2 Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than lec mme Not 10096 tested Specified by design characterization Figure 2 3 Dual Core Intel Xeon Processor X5200 Series Load Current versus Time Sustained Current A 0 01 0 1 1 10 100 1000 Time Duration s Notes 1 2 30 Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than Icc TDC Not 10096 tested Specified by design characterization m e Dual Core Intel Xeon Processor 5200 Series Electrical Specifications n tel Figure 2 4 Table 2 13 Dual Core Intel Xeon Processor L5200 Series Load Current versus Time 60 lt ss c e 50 O 45 o E 40 G 3 35 o 30 0 01 0 1 1 10 100 1000 Time Duration s Notes 1 Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than Icc TDC 2 Not 10096 tested Specified by design characterization Dual Core I ntel Xeon Processor E5200 Series andDual Core I ntel Xeon Processor X5200 Series and Dual Core Intel Xeon Processor L5200 Series Vcc Static and Transient Tolerance
10. 26 2 13 Processor DC Specifications 3 4 uu uu ua ir ai hl aa hadi hl Dak wan E WA meses ens 27 2 13 1 Flexible Motherboard Guidelines FMB meme 27 2 13 2 VCC Overshoot Specification kk kk kk aka 35 213 3 Die Voltage Validatlon aene sun ka kirandin n Aa UU awa er EE CER e ERR ka 35 2 14 AGTL FSB Specifications iieri Ee ee dee kaban Ex erede ba nee ka na Naa nan PAAR ba E iets 36 3 Mechanical Specifications ceste ENNEN ER ENER NEE ENER k EEN 39 3 1 Package Mechanical Drawings rr kk kay ak kak 39 3 2 Processor Component Keepout Zones 43 3 3 Package Loading Specifications rr kk kk kk ens 43 3 4 Package Handling Guidelines meme memes 44 3 5 Package Insertion Gpechflcations a r mmn kk k 44 3 6 Processor Mass Specifications ee mmm memes nens 44 347 Processor Materials eoo Ee hber di eir o dure es 44 3 8 Processor Mar Kil 0S ex xa bkan eret has ba alba tenes ER Mains awasqa ka a NEE RR ERNE 44 3 9 Processor and Coordinates LL sanal E ee eodem ciel ee nal lya Pu bin apa day n naa 45 4 Land Eisting Der guz E E AA 47 4 1 Dual Core Intel Xeon Processor 5200 Series Pin Assignments 47 4 1 1 Land Listing by Land Name 47 4 1 2 Land Listing by Land Number 57 5 Signal Definitions repre l nan aliyan demin adi leap Kur Ente CERE y E
11. Priority Agent The priority agent is the host bridge to the processor and is typically known as the chipset Symmetric Agent A symmetric agent is a processor which shares the same I O subsystem and memory array and runs the same operating system as another processor in a system Systems using symmetric agents are known as Symmetric Multiprocessing SMP systems I ntegrated Heat Spreader IHS A component of the processor package used to enhance the thermal performance of the package Component thermal solutions interface with the processor at the IHS surface Thermal Design Power TDP Processor thermal solutions should be designed to meet this target It is the highest expected sustainable power while running known power intensive applications TDP is not the maximum power that the processor can dissipate I ntel 64 Architecture An enhancement to Intel s IA 32 architecture that allows the processor to execute operating systems and applications written to take advantage of the 64 bit extension technology Enhanced Intel SpeedStep Technology Technology that provides power management capabilities to servers and workstations Platform Environment Control Interface PECI A proprietary one wire bus interface that provides a communication channel between Intel processor and external thermal monitoring devices for use in fan speed control PECI 1 2 1 3 intel communicates readings from the processor s digital thermom
12. 6 2 1 1 Measure from the edge of the top surface of processor IHS 14 75mm 7 Measure Tcase geometric center of the top surface of the IHS 14 75mm 37 5 mm x 37 5mm Substrate Note Figure is not to scale and is for reference only Processor Thermal Features Intel Thermal Monitor Features Dual Core Intel Xeon Processor 5200 Series provides two thermal monitor features Intel Thermal Monitor 1 and Intel Thermal Monitor 2 The Intel Thermal Monitor 1 and Intel amp Thermal Monitor 2 must both be enabled in BIOS for the processor to be operating within specifications When both are enabled Intel Thermal Monitor 2 will be activated first and Intel Thermal Monitor 1 will be added if Intel Thermal Monitor 2 is not effective Intel Thermal Monitor 1 The Intel amp Thermal Monitor 1 feature helps control the processor temperature by activating the Thermal Control Circuit TCC when the processor silicon reaches its maximum operating temperature The TCC reduces processor power consumption as needed by modulating starting and stopping the internal processor core clocks The temperature at which the Intel amp Thermal Monitor 1 activates the thermal control circuit is not user configurable and is not software visible Bus traffic is snooped in the normal manner and interrupt requests are latched and serviced during the time that the clocks are on while the TCC is active 85 e n tel Therm
13. RIOR WRIT HE MODIFIED 41 Mechanical Specifications Figure 3 4 Dual Core Intel Xeon Processor 5200 Series Package Drawing Sheet 3 of 3 H f l D B BOTTOM VIEW DE VIE Ne ER ZH N s JW S r y d DZ SN 42 m Mechanical Specifications n tel 3 2 3 3 Table 3 1 Processor Component Keepout Zones The processor may contain components on the substrate that define component keepout zone requirements Decoupling capacitors are typically mounted to either the topside or landside of the package substrate See Figure 3 4 for keepout zones Package Loading Specifications Table 3 1 provides dynamic and static load specifications for the processor package These mechanical load limits should not be exceeded during heatsink assembly mechanical stress testing or standard drop and shipping conditions The heatsink attach solutions must not include continuous stress onto the processor with the exception of a uniform load to maintain the heatsink to processor thermal interface Also any mechanical system or component testing should not exceed these limits The processor package substrate should not be used as a mechanical reference or load bearing surface for thermal or mechanical solutions Package Loading Specifications Parameter Boa
14. t ve u 00g va 161 2 ONS i 100172 ERD CIRS 69 6L t002 END t 92 6 1828 ere 60 S8 Cosy gel Na 803 NMOHS QUVOB 1531 1NOd33y adis AuviWidd QHVOSH3HLON 083931 Figure 8 5 Top Side Board Keepout Zones Part 2 Boxed Processor Specifications 103 Boxed Processor Specifications Bottom Side Board Keepout Zones Figure 8 6 009 2696 1002 F F T tug IN scan Q38011Y 1N3432V1d LN3NOdMO Q8Y0883H10N ON 002 2 338383434 404 NMOHS QNVOB 1S31 SW8031Y1l4 NI 303 N1d33N 1H913H 1N3NOdMO XVN MM rS 2 SNYOILVTd 3AO8Y NY NZ N04 Nid33y 149134 IN3NOdMOO XVN WW 8 m 9W1W4S 3015Y0v8 e 0 6 002 Z 7 EH X 100711 RZ 9rd P IDN 12 62 006 1 00 1 C0 sn Hee ose 68 s woo AINO 002 S3S04804 NOI 1VMISQTI 803 GK WS JNI1100 9814S H TH wei mm lfnod333 301S39V8 GuVOSH3HION TT 3903013865 wi e 104 em D Boxed Processor Specifications Figure 8 7 Board Mounting Hole Keepout Zones ES o j ES lt zje Ge Ni ME s H mr d Ee 2 EA ls TI SL A o ls S S EG a o 5 tn D D bei e d SC f E g E Elo z
15. 4 Pin Base Board Fan Header For Active CEK Heat Sink 83QV3HNI dr u3 nw oNiMvsQ 3002 39v9 a HE JO 133H5 9NIAVH mt LON 00 DZ emt 830V3H Nid f 118 25056 Y VI T YLNYS 4309 61185 X08 04 AIG 393110 NOISSIN 0027 Q NOI1d 192530 1N3N18Y 430 1811 S1UVd YIBWNN NOI123fOUd 319NY GYIHL r661 Me PIA IRC H TA 3ONYQNODOY NI Han V 2070 um SOF tlf Cart 2632883101 SYILINITIIN NI JYV SNOT SNIN IO 01 ONY AN 1 NI 1312345 3S1083810 53180 ASSY 834 ALO 100 200 00 luvd ON MII d01 92 WS PIA ISNY 334 9N1NVH3101 ONY NINOISN3HIO v An O APG IN 30 9N11VM 111118VMWV14 10 WAWININ Y JAVH 11VHS 94 Q3HSINIT3 ALI TIL GVWWY T3 AYOAL 80100 2 NOTAN v1 1443194 8310N5310N I Nid SH We 00 F Ez v9 0 Xb y 20 DN G E XP ON OINI BNO LC 2 0729 1 X5 DEN 90 6 N011Y380480 131NI JO 1N39N09 N1111 80184 3H LhOHLIA 03IJ100N YO G31Y14010 03986001438 039012910 39 LON LYM 51N31N02 SLI ANY 30N301JN02 NI 035012510 SI LI MOILVMHOJNI IVILNJQI INOI NOLLVHOdHOD DI SNIVINOO SNIMYNO SIN sall wel HHOYBINI dP con G j 108 Boxed Processor Specifications n tel 8 2 2 8 2 2 1 8 2 3 8 3 8 3 1 Boxed Processor Heat Sink Weight Thermal Solution Weight The 1U passive 3U active combination heat sink solution and the 2U passive heat sink solution will not exceed a mass of 1050 grams Note that this is per processor a
16. 45 3 7 Processor Land Coordinates Bottom View 46 6 1 Dual Core Intel Xeon Processor E5200 Series Thermal Profile 77 6 2 Dual Core Intel Xeon Processor X5200 Series Thermal Profiles A and B 79 6 3 Dual Core Intel Xeon Processor L5200 Series Thermal Profile 81 6 4 Dual Core Intel Xeon Processor L5238 Thermal Profile 82 6 5 Dual Core Intel Xeon Processor 5215 Thermal Profile 83 6 6 Case Temperature TCASE Measurement Location 85 6 7 Intel Thermal Monitor 2 Frequency and Voltage Ordering hk llk kE E 87 6 8 Dual Core Intel Xeon Processor 5200 Series PECI Topology 89 6 9 Conceptual Fan Control Diagram of PECI based Platforms 90 751 Stop Clock State Machine oo em eei ide i Zera a a e ee 95 8 1 Boxed Dual Core Intel Xeon Processor 5200 Series 1U Passive 3U Active Combination Heat Sink With Removable Fan 100 8 2 Boxed Dual Core Intel Xeon Processor 5200 Series 2U Passive Heat Sink 100 8 3 2U Passive Dual Core Intel Xeon Processor 5200 Series Thermal Solution Exploded View r rr 101 8 4 Top Side Board Keepout Zones Part 1 kk nnns 102 8 5 Top Side Board Keepo
17. Both the bits 0 and 1 are logic 0 and pulled to ground on the Dual Core Intel Xeon Processor 5200 Series package PROCHOT O PROCHOT Processor Hot will go active when the processor s temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature This indicates that the Thermal Control Circuit TCC has been activated if enabled The TCC will remain active until shortly after the processor deasserts PROCHOT See Section 6 2 3 for more details PWRGOOD l PWRGOOD Power Good is an input The processor requires this 2 signal to be a clean indication that all processor clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD It must also meet the minimum pulse width specification in Table 2 17 and be followed by a 1 10 ms RESET pulse The PWRGOOD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation REQ 4 0 1 0 REQ 4 0 Request Command must connect the appropria
18. CA VSS Power Other E13 D26 Source Sync Input Output C5 D01 Source Sync Input Output E14 VSS Power Other C6 D03 Source Sync Input Output E15 D33 Source Sync Input Output C7 VSS Power Other E16 D34 Source Sync Input Output C8 DSTBNO Source Sync Input Output E17 VSS Power Other c9 RESERVED E18 D39 Source Sync Input Output D1 RESERVED E19 D40 Source Sync Input Output D10 D22 Source Sync Input Output E2 VSS Power Other D11 D15 Source Sync Input Output E20 VSS Power Other D12 VSS Power Other E21 D42 Source Sync Input Output D13 D25 Source Sync Input Output E22 D45 Source Sync Input Output D14 RESERVED E23 RESERVED D15 VSS Power Other E24 RESERVED D16 RESERVED E25 VSS Power Other D17 D49 Source Sync Input Output E26 VSS Power Other D18 VSS Power Other E27 VSS Power Other D19 DBI2 Source Sync Input Output E28 VSS Power Other D2 ADS Common Clk Input Output E29 VSS Power Other D20 D48 Source Sync Input Output E3 TRDY Common Clk Input D21 VSS Power Other E30 VTT Power Other D22 D46 Source Sync Input Output E4 HITM Common Clk Input Output D23 VCCPLL Power Other Input E5 RESERVED D24 VSS Power Other E6 RESERVED D25 VTT Power Other E7 RESERVED D26 VTT Power Other E8 vss Power Other D27 VTT Power Other E9 D19 Source Sync Input Output D28 VIT Power Other F1 VSS Power Other 62 intel
19. Commonly used terms are explained here for clarification Dual Core Intel Xeon Processor 5200 Series Intel 64 bit microprocessor intended for dual processor servers and workstations based on Intel s 45 nanometer process in the PC LGA 771 package with two processor cores For this document processors is used as the generic term for the Dual Core Intel Xeon Processor 5200 Series processor The term processors and Dual Core Intel Xeon Processor 5200 Series processor are inclusive of Dual Core Intel Xeon Processor X5200 Series Dual Core Intel Xeon Processor E5200 Series and Dual Core Intel Xeon Processor L5200 Series Dual Core I ntel Xeon Processor 5200 Series ntel 64 bit microprocessor intended for dual processor servers and workstations based on Intel s 45 nanometer process in the PC LGA 771 package with two processor cores For this document processors is used as the generic term for the Dual Core Intel Xeon Processor 5200 Series processor The term processors and Dual Core Intel Xeon Processor 5200 Series processor are inclusive of Dual Core Intel Xeon Processor X5200 Series Dual Core Intel Xeon Processor E5200 Series and Dual Core Intel Xeon Processor L5200 Series Dual Core I ntel Xeon Processor X5200 Series An accelerated performance version of the Dual Core Intel Xeon Processor 5200 Series processor For this document Dual Core Intel Xe
20. MS ID1 MS IDO Description Dual Core Intel Xeon Processor 5200 Series Dual Core Intel Xeon Processor 5100 series Quad Core Intel Xeon Processor 5300 series 0 0 0 1 1 0 1 1 Quad Core Intel amp Xeon Processor 5400 Series Note The MS ID 1 0 signals are provided to indicate the Market Segment for the processor and may be used for future processor compatibility or for keying Reserved Unused and Test Signals All Reserved signals must remain unconnected Connection of these signals to Vec Vm Vss or to any other signal including each other can result in component malfunction or incompatibility with future processors See Chapter 4 for a land listing of the processor and the location of all Reserved signals For reliable operation always connect unused inputs or bidirectional signals to an appropriate signal level Unused active high inputs should be connected through a resistor to ground Vss Unused outputs can be left unconnected however this may interfere with some TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bidirectional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability Resistor values should be within 2096 of the impedance of the baseboard trace for FSB signals unless otherwise noted in the appropriate platform design guidelines For unused AGTL
21. Other VCC w8 Power Other VCC M8 Power Other VCC Y23 Power Other VCC N23 Power Other VCC Y24 Power Other VCC N24 Power Other VCC Y25 Power Other VCC N25 Power Other VCC Y26 Power Other vcc N26 Powe Other vcc Y27 Power Other 52 Land Listing intel Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 13 of 20 Sheet 14 of 20 Pin Name Ne ur Eka Direction Pin Name N aa Direction VCC Y28 Power Other VSS AB29 Power Other VCC Y29 Power Other VSS AB30 Power Other VCC Y30 Power Other VSS AB7 Power Other VCC Y8 Power Other VSS AC3 Power Other VCC_DIE_SENSE AN3 Power Other Output VSS AC6 Power Other VCC DIE SENSE2 AL8 Power Other Output VSS AC7 Power Other VCCPLL D23 Power Other Input VSS AD4 Power Other VID_SELECT AN7 Power Other Output vss AD7 Power Other VID1 AL5 CMOS Async Output vss AE10 Power Other VID2 AM3 CMOS Async Output VSS AE13 Power Other VID3 AL6 CMOS Async Output VSS AE16 Power Other VIDA AKA CMOS Async Output VSS AE17 Power Other VID5 ALA CMOS Async Output VSS AE2 Power Other VID6 AM5 CMOS Async Output VSS AE20 Power Other VSS A12 Power Other vss AE24 Power Other VSS A15 Power Other vss AE25 Power Other VSS A18 Power Other vss AE26 Power Other VSS A2 Power Other vss AE27 Power Other VSS A21 Power Other vss AE28 Power Other VS
22. VI D3 VI D2 VID1 Vcc MAX 7A 1 1 1 1 0 1 0 8500 3C 0 di 1 1 1 0 1 2375 78 1 1 1 1 0 0 0 8625 3A 0 1 1 1 0 1 1 2500 76 1 1 1 0 1 1 0 8750 38 0 1 1 1 0 0 1 2625 74 1 1 1 0 1 0 0 8875 36 0 1 1 0 1 1 1 2750 72 1 1 1 0 0 1 0 9000 34 0 1 1 0 1 0 1 2875 70 1 1 1 0 0 0 0 9125 32 0 1 1 0 0 1 1 3000 6E 1 1 0 1 1 1 0 9250 30 0 1 1 0 0 0 1 3125 6C 1 1 0 1 1 0 0 9375 2E 0 1 0 1 1 1 1 3250 6A 1 1 0 1 0 1 0 9500 2C 0 1 0 1 1 0 1 3375 68 1 1 0 1 0 0 0 9625 2A 0 1 0 1 0 1 1 3500 66 1 1 0 0 1 1 0 9750 28 0 1 0 1 0 0 1 3625 64 1 1 0 0 1 0 0 9875 26 0 1 0 0 1 1 1 3750 62 1 1 0 0 0 1 1 0000 24 0 1 0 0 1 0 1 3875 60 1 1 0 0 0 0 1 0125 22 0 1 0 0 0 1 1 4000 5E 1 0 1 1 I 1 1 0250 20 0 1 0 0 0 0 1 4125 5C 1 0 1 1 1 0 1 0375 1E 0 0 1 1 1 1 1 4250 5A 1 0 1 1 0 1 1 0500 1C 0 0 1 1 1 0 1 4375 58 1 0 1 1 0 0 1 0625 1A 0 0 1 1 0 1 1 4500 56 1 0 1 0 1 1 1 0750 18 0 0 1 1 0 0 1 4625 54 1 0 1 0 1 0 1 0875 16 0 0 1 0 1 1 1 4750 52 1 0 1 0 0 1 1 1000 14 0 0 1 0 1 0 1 4875 50 1 0 1 0 0 0 1 1125 12 0 0 1 0 0 1 1 5000 4E 1 0 0 1 1 1 1 1250 10 0 0 1 0 0 0 1 5125 4C 1 0 0 1 1 0 1 1375 OE 0 0 0 1 1 1 1 5250 4A 1 0 0 1 0 1 1 1500 0C 0 0 0 1 1 0 1 5375 48 1 0 0 1 0 0 1 1625 0A 0 0 0 1 0 1 1 5500 46 1 0 0 0 1 1 1 1750 08 0 0 0 1 0 0 1 5625 44 1 0 0 0 1 0 1 1875 06 0 0 0 0 1 1 1 5750 42 1 0 0 0 0 1 1 2000 04 0 0 0 0 1 0 1 5875 40 1 0 0 0 0 0 1 2125 02 0 0 0 0 0 1 1 6000 3E 0 1 1 1 1 1 1 2250 00 0 0 0 0 0 0 OFF1 Notes 1 When the 111111 VID pattern is observed the voltage regulat
23. Xeon Processor 5200 Series based multiprocessor systems the LAI is critical in providing the ability to probe and capture FSB signals There are two sets of considerations to keep in mind when designing a Dual Core Intel Xeon Processor 5200 Series based system that can make use of an LAI mechanical and electrical 113 e n tel Debug Tools Specifications 9 3 1 9 3 2 114 Mechanical Considerations The LAI is installed between the processor socket and the processor The LAI plugs into the socket while the processor plugs into a socket on the LAI Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer The maximum volume occupied by the LAI known as the keepout volume as well as the cable egress restrictions should be obtained from the logic analyzer vendor System designers must make sure that the keepout volume remains unobstructed inside the system Note that it is possible that the keepout volume reserved for the LAI may include differerent requirements from the space normally occupied by the heatsink If this is the case the logic analyzer vendor will provide a cooling solution as part of the LAI Electrical Considerations The LAI will also affect the electrical performance of the FSB therefore it is critical to obtain electrical load models from each of the logic analyzer vendors to be able to run system level simulations to prove that their
24. die Package Substrate Landside capacitors Package Lands Processor Package Assembly Sketch us Core die TM Substrate ____ Package Lands LS p MES Capacitors err LGA771 Socket System Board Note This drawing is not to scale and is for reference only Package Mechanical Drawings The package mechanical drawings are shown in Figure 3 2 through Figure 3 4 The drawings include dimensions necessary to design a thermal solution for the processor including Package reference and tolerance dimensions total height length width and so forth IHS parallelism and tilt Land dimensions Top side and back side component keepout dimensions Reference datums All drawing dimensions are in mm in 39 m e n tel Mechanical Specifications Figure 3 2 Dual Core Intel Xeon Processor 5200 Series Package Drawing Sheet 1 of 3 EMTS MODEL Pa TO RONT OO Note Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal Mechanical Design Guidelines 40 Mechanical Specifications Figure 3 3 Dual Core Intel Xeon Processor 5200 Series Package Drawing Sheet 2 of 3 ED IN TEN ONT DENT INFORMATION IT IS ORATION
25. 0 10 Vir V r 0 10 V 3 6 Vou Output High Voltage Vr 0 10 N A Vit V 4 6 Ron Buffer On Resistance 8 25 10 25 12 25 Q 5 lu Input Leakage Current N A N A 100 HA 7 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Mu is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value 3 Viu is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value 4 VIH and Vor may experience excursions above V However input signal drivers must comply with the signal quality specifications 5 This is the pull down driver resistance Refer to processor O Buffer Models for I V characteristics Measured at 0 31 V Ron min 0 158 R q Ron typ 0 167 R Ron max 0 175 Rrr 6 GTLREF should be generated from V with a 1 tolerance resistor divider The V referred to in these specifications is the instantaneous Vrr 7 Specified when on die Ry and Roy are turned off Viy between 0 and Vmr Table 2 15 CMOS Signal I nput Output Group and TAP Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes Vu Input Low Voltage 0 10 0 00 0 3 Vr V 2 3 Vin Input High Voltage 0 7 V V Vor 0 1 V 2 VoL Output Low Voltage 0 10 0 0 1 Vir V 2 Vou Output High Voltage 0 9 V V Vrr 0 1 V 2 loL Output Low Current 1
26. 0 700 0 700 A vCROSS Range of Crossing N A N A 0 140 V 2 10 Points 2 11 Dual Core Intel Xeon Processor 5200 Series Electrical Specifications n tel Table 2 19 FSB Differential BCLK Specifications Sheet 2 of 2 Figure 2 9 Symbol Parameter Min Typ Max Unit Figure Notes1 Vos Overshoot N A N A 1 150 V 2 10 4 Vus Undershoot 0 300 N A N A V 2 10 5 VRBM Ringback Margin 0 200 N A N A V 2 10 6 VTR Threshold Region Vcnoss N A VcRoss V 2 10 7 0 100 0 100 lu Input Leakage Current N A N A 100 HA 10 ERRefclk diffRrise Differential Rising and 0 6 4 V ns 2 12 12 ERRefclk diff Fall falling edge rates Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLKO is equal to the falling edge of BCLK1 3 Viavg is the statistical average of the Vy measured by the oscilloscope 4 Overshoot is defined as the absolute value of the maximum voltage 5 Undershoot is defined as the absolute value of the minimum voltage 6 Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback 7 Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches It includes input threshold hysteresis 8 T
27. 155 V 8 13 AC specification VccPLL PLL supply voltage DC AC 1 455 1 500 1 605 V 12 specification lec Icc for Dual Core Intel 90 A 4 5 6 9 Xeon Processor X5200 Series with multiple VID Launch FMB lec Icc for Dual Core Intel 75 A 4 5 6 9 Xeon Processor E5200 Series with multiple VID Launch FMB lec Icc for Dual Core Intel 50 A 4 5 6 9 Xeon Processor L5200 Series with multiple VID Launch FMB lec Icc for Dual Core Intel 42 A 4 5 6 9 Xeon Processor L5238 with multiple VID Launch FMB cc_RESET Icc RESET for Dual Core 90 A 17 Intel Xeon Processor X5200 Series with multiple VID Launch FMB cc_RESET lcc_reseT for Dual Core 75 A 17 Intel Xeon Processor E5200 Series with multiple VID Launch FMB cc_RESET lcc_reseT for Dual Core 50 A 17 Intel Xeon Processor L5200 Series with multiple VID Launch FMB cc_RESET Icc neser for Dual Core 42 A 17 Intel Xeon Processor L5238 with multiple VID Launch FMB I Icc for Vr supply before Vec 4 5 A 15 stable lcc for Vr supply after Vec 4 6 stable 28 e Dual Core Intel Xeon Processor 5200 Series Electrical Specifications n tel Table 2 12 Voltage and Current Specifications Sheet 2 of 2 Symbol Parameter Min Typ Max Unit Notes 1 11 lec toc Thermal Design Current 70 A 6 14 TDC Dual Core Intel Xeon Processor X5200 Series Lau
28. 2 defines the possible combinations of the signals and the frequency associated with each combination The required frequency is determined by the processors chipset and clock synthesizer AII FSB agents must operate at the same frequency For more information about these signals including termination recommendations refer to the appropriate platform design guideline 68 Signal Definitions Table 5 1 intel Signal Definitions Sheet 3 of 8 Name D 63 0 Type 1 0 Description D 63 0 Data are the data signals These signals provide a 64 bit data path between the processor FSB agents and must connect the appropriate pins on all such agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and will thus be driven four times in a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN 3 0 Each group of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to strobes and DBI Data Group sak e BS DBI D 15 0 0 D 31 16 1 D 47 32 2 D 63 48 3 w N ll o Furthermore the DBI signals determine the polarity of the data signals Each group of 16 data signals corresponds to one DBI signal When the DBI signal is active the corresponding data group is inverted and therefore sampled active high Not
29. 2B 253667 Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A 253668 Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B 253669 Intel 64 and IA 32 Intel Architectures Optimization Reference Manual 248966 2 Intel 64 and IA 32 Intel Architectures Software Developer s Manual 252046 2 Documentation Changes Dual Core Intel Xeon Processor 5200 Series Specification Update 318586 2 Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 315889 2 11 0 Design Guidelines Dual Core Intel Xeon Processor 5200 Series Thermal Mechanical Design 318675 2 Guidelines TMDG Dual Core Intel Xeon Processor 5200 Series in Embedded Thermal Mechanical 1 Design Guidelines TMDG LGA771 Socket Mechanical Design Guide 313871 2 Dual Core Intel Xeon Processor 5200 Series Boundary Scan Description 318588 2 Language BSDL Model Notes 1 2 Contact your Intel representative for the latest revision of these documents Document is available publicly at http developer intel com 13 m e Dual Core Intel Xeon Processor 5200 Series Electrical Specifications n tel 2 2 1 2 2 Dual Core Intel Xeon Processor 5200 Series Electrical Specifications Front Side Bus and GTLREF Most Dual Core Intel Xeon Processor 5200 Series FSB signals use Assisted Gunning Transceiver Logic AGTL signaling technology This technology provides improved noise marg
30. 4 5 Notes 1 These values are specified at Vcc max for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds Vcc max at specified ICC Please refer to the loadline specifications in Section 2 13 gt 2 Thermal Design Power TDP should be used for processor thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at maximum Teaser 3 These specifications are based pre silicon estimates and simulations These specifications will be updated with characterized data from silicon measurements in a future release of this document 4 Power specifications are defined at all VIDs found in Table 2 12 The Dual Core Intel Xeon Processor L5238 may be shipped under multiple VIDs for each frequency 5 FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements Figure 6 4 Dual Core Intel Xeon Processor L5238 Thermal Profile Thermal Profile 1 00 Short term Thermal Profile may only be used for short term excursions to higher ambient temperatures not to exceed 360 hours per year 90 Tcase max TDP wee M rm rm rm pm m mr rm eee rm m m m e m m m ERR as p 80 E _ o _ 70 Tcase 0 741 P 60 me e S L lt 50 Nominal 40 Tca
31. 70 N A 4 70 mA 4 lou Output High Current 1 70 N A 4 70 mA 5 lu Input Leakage Current N A N A 100 HA 6 Notes Unless otherwise noted all specifications in this table apply to all processor frequencies The Vy referred to in these specifications refers to instantaneous Vy Refer to the processor I O Buffer Models for I V characteristics Measured at 0 1 Vy Measured at 0 9 Vr For Vin between 0 V and Ver Measured when the driver is tristated m OT US n Table 2 16 Open Drain Output Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes VoL Output Low Voltage 0 N A 0 20 Vr V Vou Output High Voltage 0 95 Viz Vit 1 05 Ver V 3 lot Output Low Current 16 N A 50 mA 2 lio Leakage Current N A N A x 200 HA 4 34 Bi Dual Core Intel Xeon Processor 5200 Series Electrical Specifications n tel 2 13 2 Table 2 17 Figure 2 8 2 13 3 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Measured at 0 2 Vr 3 Voy is determined by value of the external pullup resistor to Vr Refer to platform design guide for details 4 For ViN between 0 V and Vor Vcc Overshoot Specification The Dual Core Intel Xeon Processor 5200 Series can tolerate short transient overshoot events where Vcc exceeds the VID voltage when transitioning from a high to low current load condition This overshoot cannot exceed VID Vos
32. Async Input T3 VSS Power Other P23 VSS Power Other T30 VCC Power Other P24 VSS Power Other T4 A11 Source Sync Input Output P25 VSS Power Other T5 A09 Source Sync Input Output P26 vss Power Other T6 vss Power Other P27 vss Power Other T7 vss Power Other P28 vss Power Other T8 VCC Power Other P29 vss Power Other U1 vss Power Other P3 INIT CMOS Async Input U2 AP0 Common Clk Input Output P30 VSS Power Other U23 VCC Power Other P4 vss Power Other U24 VCC Power Other P5 A37 Source Sync Input Output U25 VCC Power Other P6 A04 Source Sync Input Output U26 VCC Power Other P7 VSS Power Other U27 VCC Power Other P8 VCC Power Other U28 VCC Power Other R1 RESERVED U29 VCC Power Other 65 intel Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 19 of 20 Sheet 20 of 20 Pin No Pin Name ni ue Direction Pin No Pin Name AN Direction U3 AP1 Common CIk Input Output Y2 vss Power Other U30 VCC Power Other Y23 VCC Power Other U4 A13 Source Sync Input Output Y24 VCC Power Other U5 A12 Source Sync Input Output Y25 VCC Power Other U6 A10 Source Sync Input Output Y26 VCC Power Other U7 VSS Power Other Y27 VCC Power Other U8 VCC Power Other Y28 VCC Power Other V1 MS_ID1 Power Other Output Y29 VCC Power Other V2 LL IDO Powe
33. Circuit TCC would only be activated for very brief periods of time when running the most power intensive applications Refer to the Dual Core Intel Xeon Processor 5200 Series Thermal Mechanical Design Guidelines TMDG for details on system thermal solution design thermal profiles and environmental considerations The Dual Core Intel Xeon Processor L5238 supports a Thermal Profile with nominal and short term conditions designed to meet NEBS level 3 compliance see Figure 6 4 Operation at either thermal profile should result in virtually no TCC activation Refer to the Dual Core Intel Xeon Processor 5200 Series in Embedded Thermal Mechanical Design Guidelines TMDG The Dual Core Intel Xeon Processor X5200 Series supports a dual Thermal Profile either of which can be implemented Both ensure adherence to the Intel reliability requirements Thermal Profile A see Figure 6 2 Table 6 4 is representative of a volumetrically unconstrained thermal solution that is industry enabled 2U heatsink In this scenario it is expected that the Thermal Control Circuit TCC would only be activated for very brief periods of time when running the most power intensive applications Thermal Profile B see Figure 6 2 Table 6 5 is indicative of a constrained thermal environment that is 1U form factor Because of the reduced cooling capability represented by this thermal solution the probability of TCC activation and performance loss is increas
34. E26 Power Other vss K5 Power Other vss E27 Power Other vss K7 Power Other vss E28 Power Other vss L23 Power Other vss E29 Power Other vss L24 Power Other vss E8 Power Other vss L25 Power Other vss F1 Power Other vss L26 Power Other vss F10 Power Other vss L27 Power Other vss F13 Power Other vss L28 Power Other vss F16 Power Other vss L29 Power Other vss F19 Power Other vss L3 Power Other vss F22 Power Other vss L30 Power Other vss F4 Power Other vss L6 Power Other vss F7 Power Other vss L7 Power Other 55 intel tard sina Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 19 of 20 Sheet 20 of 20 Pin Name eg SE Direction Pin Name N e Direction Wss j PweyOhe vss V6 Power Other vss M7 Power Other vss V7 Power Other vss N3 Power Other vss w4 Power Other vss N6 Power Other vss w7 Power Other vss N7 Power Other vss Y2 Power Other vss P23 Power Other vss Y5 Power Other vss P24 Power Other vss Y7 Power Other vss P25 Power Other VSS_DIE_SENSE AN4 Power Other Output vss P26 Power Other VSS_DIE_SENSE2 AL7 Power Other Output wes Ion Power tber v A25 Power Other vss P28 Power Other VTT A26 Power Other vss P29 Power Other VTT B25 Power Other Ivss Jean Powe Other VIT B26 Power Other vss P4 Power Other VTT B27 Power Other vss
35. FSB frequency is not altered only the internal core frequency is changed When entering the low power state the processor will first switch to the lower bus to core frequency ratio and then transition to the lower voltage VID While in the Extended HALT state the processor will process bus snoops Extended HALT Maximum Power Sheet 1 of 2 Symbol Parameter Min Typ Max Unit Notes 1 PEXTENDED HALT Extended HALT State 12 w 2 Dual Core Intel Xeon Power Processor E5205 PEXTENDED_HALT Extended HALT State 8 w 2 Dual Core Intel Xeon Power Processor X5200 Series PEXTENDED_HALT Extended HALT State 12 w 2 Dual Core Intel Xeon Power Processor E5230 Features Table 7 2 Figure 7 1 intel Extended HALT Maximum Power Sheet 2 of 2 Symbol Parameter Min Typ Max Unit Notes 1 PEXTENDED_HALT Extended HALT State 8 w 2 Dual Core Intel Xeon Power Processor E5240 PEXTENDED_HALT Extended HALT State 6 w 2 Dual Core Intel Xeon Power Processor L5200 Series PEXTENDED_HALT Extended HALT State 6 w 3 Dual Core Intel Xeon Power Processor L5238 Notes 1 Processors running in the lowest bus ratio supported as shown in Table 2 1 will enter the HALT State when the processor has executed the HALT or MWAIT instruction since the processor is already operating in the lowest core frequency and voltage operating point 2 The specification is at Tcase 389C and no
36. Intel Xeon Processor March 2008 L5238 Added product information for Dual Core Intel Xeon Processor e 003 L5200 Series April 2008 Corrected L1 cache size 004 Exposed L5215 August 2008 Rev to keep in sync with Quad Core Intel Xeon Processor 5400 005 Series Datasheet August 2008 No content changes Dual Core Intel Xeon Processor 5200 Series Datasheet Dual Core Intel Xeon Processor 5200 Series Datasheet intel Introduction The Dual Core Intel Xeon Processor 5200 Series is a server workstation processor utilizing two 45 nm Hi k next generation Intel Core microarchitecture cores The processor is manufactured on Intel s 45 nanometer process technology combining high performance with the power efficiencies of a low power microarchitecture The Dual Core Intel Xeon Processor 5200 Series maintains the tradition of compatibility with IA 32 software Some key features include on die primary 32 kB instruction cache and 32 kB write back data cache in each core and 6 MB Level 2 cache with Intel Advanced Smart Cache architecture The processors Data Prefetch Logic speculatively fetches data to the L2 cache before an L1 cache requests occurs resulting in reduced effective bus latency and improved performance The 1333 MHz Front Side Bus FSB is a quad pumped bus running off a 333 MHz system clock making 10 66 GBytes per second data transfer rates possible The 1600 MHz Front Side Bus FSB is a quad pumped bus running of
37. K29 VCC Power Other H9 VSS Power Other K3 A20M CMOS Async Input J1 VTT_OUT Power Other Output K30 VCC Power Other J10 VCC Power Other K4 REQ0 Source Sync Input Output J11 VCC Power Other K5 VSS Power Other J12 VCC Power Other K6 REQ3 Source Sync Input Output J13 VCC Power Other K7 VSS Power Other J14 VCC Power Other K8 VCC Power Other J15 VCC Power Other L1 LINT1 CMOS Async Input J16 DP0 Common Clk Input Output L2 TESTHI11 Power Other Input J17 DP3 Common CIk Input Output L23 VSS Power Other J18 VCC Power Other L24 VSS Power Other J 19 VCC Power Other L25 VSS Power Other J2 RESERVED L26 VSS Power Other J20 VCC Power Other L27 VSS Power Other J21 VCC Power Other L28 VSS Power Other J22 VCC Power Other L29 VSS Power Other J23 VCC Power Other L3 VSS Power Other J24 VCC Power Other L30 VSS Power Other J25 VCC Power Other L4 A06 Source Sync Input Output J26 VCC Power Other L5 A05 Source Sync Input Output J27 VCC Power Other L6 vss Power Other J28 VCC Power Other L7 vss Power Other J29 VCC Power Other L8 VCC Power Other J3 RESERVED M1 VSS Power Other J30 VCC Power Other M2 THERMTRIP Open Drain Output J4 VSS Power Other M23 VCC Power Other J5 REQ1 Source Sync Input Output M24 VCC Power Other J6 REQ4 Source Sync Input Output M25 VCC Power Other J7 VSS Power Other M26 VCC Power Other J8 VCC Power Other M27 VCC Power Other J9 VCC Power Other M28 VCC Power Other K1 LI NTO CMOS Async Input M29 VCC Power Other
38. Once activated THERMTRIP remains latched until PWRGOOD is de asserted While the de assertion of the PWRGOOD signal will de assert THERMTRIP if the processor s junction temperature remains at or above the trip level THERMTRIP will again be asserted within 10 us of the assertion of PWRGOOD TMS TMS Test Mode Select is a J TAG specification support signal used by debug tools See the Debug Port Design Guide for Intel 5000 Series Chipset Memory Controller Hub MCH Systems External Version for further information TRDY TRDY Target Ready is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins of all FSB agents TRST TRST Test Reset resets the Test Access Port TAP logic TRST must be driven low during power on Reset VccPLL The Dual Core Intel Xeon Processor 5200 Series implements an on die PLL filter solution The Vccp input is used as a PLL supply voltage VCC_DIE_SENSE VCC_DIE_SENSE2 VCC_DIE_SENSE and VCC_DIE_SENSE2 provides an isolated low impedance connection to the processor core power and ground This signal should be connected to the voltage regulator feedback signal which insures the output voltage that is processor voltage remains within specification Please see the applicable platform design guide for implementation details VID 6 1 VID 6 1 Voltage ID pins
39. Power Other AL4 VID5 CMOS Async Output AK23 VSS Power Other AL5 VID1 CMOS Async Output AK24 VSS Power Other AL6 VID3 CMOS Async Output AK25 vcc Power Other AL7 VSS_DIE_ Power Other AK26 vcc Power Other Sare AK27 vss Power Other SC Kid RE AK28 VSS Power Other AL9 VCC Power Other AK29 vss Power Other AM1 vss Power Other AK3 RESERVED AM10 VSS Power Other AK30 VSS Power Other AM11 VCC Power Other AK4 VID4 CMOS Async Output AM12 VCC Power Other AK5 VSS Power Other AM13 vss Power Other AK6 FORCEPR CMOS Async Input AM14 VCC Power Other AK7 vss Power Other AMIS VCC Power Other AK8 VCC Power Other AM16 VSS Power Other AK9 VCC Power Other AM17 VSS Power Other AL1 RESERVED AM18 VCC Power Other AL10 vss Power Other AM19 VCC Power Other AL11 VCC Power Other AM2 RESERVED AL12 VCC Power Other AM20 VSS Power Other AL13 VSS Power Other AM21 VCC Power Other AL14 VCC Power Other AM22 VCC Power Other AL15 VCC Power Other AM23 VSS Power Other AL16 VSS Power Other AM24 VSS Power Other AL17 vss Power Other AM25 VCC Power Other 60 intel Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 9 of 20 Sheet 10 of 20 Pin No Pin Name m Direction Pin No Pin Name m Direction AM26 VCC Power Other B10 D10 Source Sync Inp
40. VSS DIE SENSE2 lands with an oscilloscope set to 100 MHz bandwidth 1 5 pF maximum probe capacitance and 1 MO minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe 4 The processor must not be subjected to any static Vcc level that exceeds the Vcc max associated with any particular current Failure to adhere to this specification can shorten processor lifetime 5 Icc max Specification is based on maximum Vcc loadline Refer to Figure 2 5 Figure 2 6 and Figure 2 11 for details The processor is capable of drawing I cc max for up to 10 ms Refer to Figure 2 1 for further details on the average processor current draw over various time durations 6 FMBisthe flexible motherboard guideline These guidelines are for estimation purposes only See Section 2 13 1 for further details on FMB guidelines 7 This specification represents the total current for GTLREF DATA and GTLREF ADD 8 Vmr must be provided via a separate voltage source and must not be connected to Vcc This specification is measured at the land 9 Minimum Vcc and maximum lI cc are specified at the maximum processor case temperature TCASE shown in Figure 6 1 and Figure 6 2 29 15 16 17 Dual Core Intel Xeon Processor 5200 Series Electrical Specifications This specification refers to the total reduction of the load line due to VID transitions below the specif
41. a Phillips screwdriver to attach to the chassis pan When installing the CEK the CEK screws should be tightened until they will no longer turn easily This should represent approximately 6 8 inch pounds of torque More than that may damage the retention mechanism components Electrical Requirements Fan Power Supply Active CEK The 4 pin PWM controlled thermal solution is being offered to help provide better control over pedestal chassis acoustics This is achieved though more accurate measurement of processor die temperature through the processor s Digital Thermal Sensors Fan RPM is modulated through the use of an ASIC located on the baseboard that sends out a PWM control signal to the 4th pin of the connector labeled as Control This thermal solution requires a constant 12 V supplied to pin 2 of the active thermal solution and does not support variable voltage control or 3 pin PWM control See Table 8 2 for details on the 4 pin active heat sink solution connectors If the 4 pin active fan heat sink solution is connected to an older 3 pin baseboard CPU fan header it will default back to a thermistor controlled mode allowing compatibility with legacy 3 wire designs When operating in thermistor controlled mode fan RPM is automatically varied based on the TINLET temperature measured by a thermistor located at the fan inlet of the heat sink solution 109 Table 8 1 Table 8 2 Figure 8 11 Table 8 3 8 3 2 8 3 2 1 110 n
42. also the function of the thermal design of the entire system and ultimately the responsibility of the system integrator The processor temperature specifications are found in Chapter 6 of this document 1U Passive 3U Active Combination Heat Sink Solution 1U Rack Passive In the 1U configuration it is assumed that a chassis duct will be implemented to provide a minimum airflow of 15 cfm at 0 38 in H20 25 5 m3 hr at 94 6 Pa of flow impedance The duct should be carefully designed to minimize the airflow bypass Boxed Processor Specifications n tel 8 3 2 2 8 3 2 3 8 4 around the heatsink It is assumed that a 40 C Tj A is met This requires a superior chassis design to limit the Tpjse at or below 5 C with an external ambient temperature of 35 C These specifications apply to both copper and aluminum heatsink solutions Following these guidelines allows the designer to meet Dual Core Intel Xeon Processor 5200 Series Thermal Profile and conform to the thermal requirements of the processor 1U Passive 3U Active Combination Heat Sink Solution Pedestal Active The active configuration of the combination solution is designed to help pedestal chassis users to meet the thermal processor requirements without the use of chassis ducting It may be still be necessary to implement some form of chassis air guide or air duct to meet the T 4 temperature of 40 C depending on the pedestal chassis layout Also while the acti
43. aluminum extruded 2U passive heatsink The 1U passive 3U active combination solution in the active fan configuration is primarily designed to be used in a pedestal chassis where sufficient air inlet space is present and strong side directional airflow is not an issue The 1U passive 3U active combination solution with the fan removed and the 2U passive thermal solution require the use of chassis ducting and are targeted for use in rack mount or pedestal servers The retention solution used for these products is called the Common Enabling Kit or CEK The CEK base is compatible with both thermal solutions and uses the same hole locations as the Intel Xeon processor with 800 MHz system bus The 1U passive 3U active combination solution will utilize a removable fan capable of 4 pin pulse width modulated PWM control Use of a 4 pin PWM controlled active thermal solution helps customers meet acoustic targets in pedestal platforms through the motherboards s ability to directly control the RPM of the processor heat sink fan See Section 8 3 for more details on fan speed control and see Section 6 3 for more on the PWM and PECI interface along with Digital Thermal Sensors DTS Figure 8 1 through Figure 8 3 are representations of the two heat sink solutions 99 m e n tel j Boxed Processor Specifications Figure 8 1 Boxed Dual Core Intel Xeon Processor 5200 Series 1U Passive 3U Active Combination Heat Sink With Removable Fan
44. and Figure 3 7 show the top and bottom view of the processor land coordinates respectively The coordinates are referred to throughout the document to identify processor lands Figure 3 6 Processor Land Coordinates Top View Voc Vss 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 2 5 4 3 2 ooommorecarzzomxac z ze Socket 771 Quadrants Address Common Clock Async moommorcezrzzvonAaccz 2 5b5nnb5rbRPEZ V Clocks Data s 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1615 1413121110 9 8 7 6 5 4 3 2 1 45 e n tel Mechanical Specifications Figure 3 7 Processor Land Coordinates Bottom View Vcc Vss 12345 t 8 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 AN x AN AM AM AL AL AK AK AJ AJ AH AH AG AG AF AF AE AE AD AD AC Address Common Clock Async Socket 771 Quadrants Bottom View gt u O om m E amp X r amp Z0 J 4 C lt lt 5 gt gt gt gt o g m m O0 tr er SZ nm e See o Pa A 1234526 7 8 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Data Vir Clocks 46 Land Listing 4 Land Listing Dual Core Intel Xeon Processor 5200 Series This section provides sorted land list in Table 4 1 and Table 4 2 Table 4 1 is a listing of all processor lands ordered alphabetically by land name Table 4 2 i
45. are used to support automatic selection of power supply voltages Vcc These are CMOS signals that are driven by the processor and must be pulled up through a resistor Conversely the voltage regulator output must be disabled prior to the voltage supply for these pins becomes invalid The VID pins are needed to support processor voltage specification variations See Table 2 4 for definitions of these pins The VR must supply the voltage that is requested by these pins or disable itself 73 intel Table 5 1 Signal Definitions Signal Definitions Sheet 8 of 8 74 Name Type Description Notes VID SELECT O VID_SELECT is an output from the processor which selects the appropriate VID table for the Voltage Regulator This signal is not connected to the processor die This signal is a no connect on the Dual Core Intel Xeon Processor 5200 Series package VSS_DIE_SENSE O VSS_DIE_SENSE and VSS_DIE_SENSE2 provides an isolated low VSS DIE SENSE2 impedance connection to the processor core power and ground This WT signal should be connected to the voltage regulator feedback signal which insures the output voltage that is processor voltage remains within specification Please see the applicable platform design guide for implementation details VTT P The FSB termination voltage input pins Refer to Table 2 12 for further details VTT_OUT O The VTT_OUT signals are included in order to provide a local V
46. design guidelines Dual Core Intel Xeon Processor 5200 Series Electrical Specifications 2 4 Table 2 1 2 4 1 intel Front Side Bus Clock BCLK 1 0 and Processor Clocking BCLK 1 0 directly controls the FSB interface speed as well as the core frequency of the processor As in previous processor generations the Dual Core Intel Xeon Processor 5200 Series core frequency is a multiple of the BCLK 1 0 frequency The processor bus ratio multiplier is set during manufacturing The default setting is for the maximum speed of the processor It is possible to override this setting using software see the Intel amp 64 and IA 32 Architectures Software Developer s Manual This permits operation at lower frequencies than the processor s tested frequency The processor core frequency is configured during reset by using values stored internally during manufacturing The stored value sets the highest bus fraction at which the particular processor can operate If lower speeds are desired the appropriate ratio can be configured via the CLOCK FLEX MAX MSR For details of operation at core frequencies lower than the maximum rated processor speed refer to the Intel 64 and Intel 64 and IA 32 Architectures Software Developer s Manual Clock multiplying within the processor is provided by the internal phase locked loop PLL which requires a constant frequency BCLK 1 0 input with exceptions for spread spectrum clocking Processor DC spe
47. for some signals that require termination to Vu on the motherboard VTT_SEL O The VTT_SEL signal is used to select the correct V voltage level for the processor VIT SEL is connected to VSS on the Dual Core Intel Xeon Processor 5200 Series package Notes 1 For this processor land on the Dual Core Intel Xeon Processor 5200 Series the maximum number of symmetric agents is one Maximum number of priority agents is zero 2 Forthis processor land on the Dual Core Intel Xeon Processor 5200 Series the maximum number of symmetric agents is two Maximum number of priority agents is zero 3 For this processor land on the Dual Core Intel Xeon Processor 5200 Series the maximum number of symmetric agents is two Maximum number of priority agents is one 8 Bi Thermal Specifications n tel 6 6 1 Note 6 1 1 Thermal Specifications Package Thermal Specifications The Dual Core Intel Xeon Processor 5200 Series requires a thermal solution to maintain temperatures within its operating limits Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system As processor technology changes thermal management becomes increasingly crucial when building computer systems Maintaining the proper thermal environment is key to reliable long term system operation A complete solution includes both component and system
48. gt au Direction Pin Name N e aw Direction Iwer ja PoweryOther vcc N27 Power Other VCC J15 Power Other VCC N28 Power Other VCC J18 Power Other VCC N29 Power Other VCC J19 Power Other VCC N30 Power Other VCC J20 Power Other VCC N8 Power Other VCC J21 Power Other VCC P8 Power Other VCC J22 Power Other VCC R8 Power Other VCC J23 Power Other VCC T23 Power Other VCC J24 Power Other VCC T24 Power Other Iwer os Powerothe vcc T25 Power Other VCC J26 Power Other VCC T26 Power Other VCC J27 Power Other VCC T27 Power Other Ivc os Poweyother vcc T28 Power Other VCC J29 Power Other VCC T29 Power Other VCC J30 Power Other VCC T30 Power Other VCC J8 Power Other VCC T8 Power Other VCC J9 Power Other VCC U23 Power Other VCC K23 Power Other VCC U24 Power Other VCC K24 Power Other VCC U25 Power Other VCC K25 Power Other VCC U26 Power Other VCC K26 Power Other VCC U27 Power Other VCC K27 Power Other VCC U28 Power Other VCC K28 Power Other VCC U29 Power Other VCC K29 Power Other VCC U30 Power Other Iw Ko Powe Other fve U8 Power Other VCC K8 Power Other VCC v8 Power Other VCC L8 Power Other VCC W23 Power Other VCC M23 Power Other VCC W24 Power Other VCC M24 Power Other VCC w25 Power Other VCC M25 Power Other VCC W26 Power Other VCC M26 Power Other VCC W27 Power Other VCC M27 Power Other VCC W28 Power Other VCC M28 Power Other VCC w29 Power Other VCC M29 Power Other VCC W30 Power Other VCC M30 Power
49. hi AR gr E RE b n q 67 5 1 Signal Defihl tl EE 67 6 Thermal Specifications L LLLL LL Eka kk kaka kak kk kak kak 75 6 1 Package Thermal Gpecflcations kk kk kk kk kak kk kak 75 6 1 1 Thermal Spaecifical ti 0S sa uuu uu u uu uuu bda vas n kan la ERENNERT dn nadin w y 75 61 2 Thermal Metrology toe HERR W W W da h k ba A eee a nd sa 84 6 2 Processor Thermal Feat res lara nina ki xarna kak xaki nan 2 r w pak xa r meses 85 Dual Core Intel Xeon Processor 5200 Series Datasheet 3 ntel 6 2 1 Intel Thermal Monitor Features 85 6 2 2 On Demand Mode 87 6 2 3 PROCHOT Signal ia rex Y kasa aah w X ER ER RA QR RENE W k wakasapa duka 88 6 2 4 FORCEPR Signal us ukuway yaaa aqa tienes exea E ln K n mated A ERES 88 6 2 5 THERMTRIP Signal 2i dc nne dit na a ea d Rak en nayan W NEE SEN dE REENEN nea ke 88 6 3 Platform Environment Control Interface PECH 89 6 351 E Nu ug ee ge In EE 89 6 3 2 PECI Specifications J L uu sk kake hs kla amar tied bdaba din EAR Dia nian b ka GERE 90 diiit e 93 7 1 Power On Configuration Options meme kaka enemies 93 7 2 Clock Control and Low Power States 93 4 2 1 Normal State EE 94 7 2 2 HALT or Extended HALT Gtete kk kk kk kk kak kak kk kk a kk kk 94 RE WEE ee Elle 96 7 2 4 Extended HALT Snoop or HALT Snoop State Stop Grant Snoop Stateuuu u uk Ec ARRA T TERRAE DN ON aa E
50. intel Dual Core Intel Xeon Processor 5200 Series Datasheet August 2008 318590 005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Dual Core Intel Xeon Processor 5200 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request 64 bit computing on Intel architecture requires a computer system with a
51. max Vos max S the maximum allowable overshoot above VID These specifications apply to the processor die voltage as measured across the VCC_DIE_SENSE and VSS_DIE_SENSE lands and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands Vcc Overshoot Specifications Symbol Parameter Min Max Units Figure Notes Vos_MAX Magnitude of Vcc overshoot above VID 50 mv 2 8 Tos Max Time duration of Vcc overshoot above VID 25 us 2 8 Vcc Overshoot Example Waveform Example Overshoot Waveform VID 0 050 Vos o D gt VID 0 000 Tos 0 5 10 15 20 25 Time us Tos Overshoot time above VID Vos Overshoot above VID Notes 1 VOS is the measured overshoot voltage 2 TOS isthe measured time duration above VID Die Voltage Validation Core voltage VCC overshoot events at the processor must meet the specifications in Table 2 17 when measured across the VCC_DIE_SENSE and VSS_DIE_SENSE lands and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands Overshoot events that are lt 10 ns in duration may be ignored These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope 35 Table 2 18 Table 2 19 36 Dual Core Intel Xeon Processor 5200 Series Electrical Specifications AGTL FSB Specifications Routing topologies are dependent on the processors supported and the chipset used in the design Please refer
52. processor chipset BIOS operating system device drivers and applications enabled for Intel 64 architecture Processors will not operate including 32 bit operation without an Intel 64 architecture enabled BIOS Performance will vary depending on your hardware and software configurations Consult with your system vendor for more information Intel Virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM and for some uses certain computer system software enabled for it Functionality performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update Software applications may not be compatible with all operating systems Please check with your application vendor Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Intel Pentium Intel Xeon Intel SpeedStep Technology Intel Core and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Other names and brands may be claimed as the property of others Copyright O 2007 2008 Intel Corporation 2 Dual Core Intel Xeon Processor 5200 Series Datasheet Contents 1 Bi de TT d LEE 9 fu Een ge lu te e Le KEE 10 1 2 State of Data sl q stage Sg ed eege ege pupas Ga e dee 13 SC GE En Le 13 2 Dual Core Inte
53. to the appropriate platform design guidelines for specific implementation details In most cases termination resistors are not required as these are integrated into the processor silicon See Table 2 8 for details on which signals do not include on die termination Please refer to Table 2 18 for Ry values Valid high and low levels are determined by the input buffers via comparing with a reference voltage called GTLREF DATA and GTLREF ADD GTLREF DATA is the reference voltage for the FSB 4X data signals GTLREF ADD is the reference voltage for the FSB 2X address signals and common clock signals Table 2 18 lists the GTLREF DATA and GTLREF ADD specifications The AGTL reference voltages GTLREF DATA and GTLREF ADD must be generated on the baseboard using high precision voltage divider circuits Refer to the appropriate platform design guidelines for implementation details AGTL Bus Voltage Definitions Symbol Parameter Min Typ Max Units Notes GTLREF DATA Data Bus Reference 0 98 0 667 1 02 0 667 V 2 3 Voltage 0 667 Var V1 Vu GTLREF ADD Address Bus Reference 0 98 0 667 1 02 0 667 V 2 3 Voltage 0 667 Vr V Vr R r Termination 43 49 55 Q 4 5 Resistance pull up for Data Signals Rr Termination 40 49 58 Q 4 6 Resistance pull up for Common Clock and Address Signals Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencie
54. tool will work in the system Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution they provide
55. transfers between the host and client devices Also data transfer speeds across the PECI interface are negotiable within a wide range 2Kbps to 2Mbps The PECI interface on the Dual Core Intel Xeon Processor 5200 Series is disabled by default and must be enabled through BIOS Dual Core I ntel Xeon Processor 5200 Series PECI Topology Processor Socket 0 Pin G5 PZ Processor Socket 1 PECI Host Controller Pin G5 HE TcoNTROL and TCC Activation on PECI based Systems Fan speed control solutions based on PECI utilize a Tcowrno value stored in the processor A32 TEMPERATURE TARGET MSR The TcoNTRo MSR uses the same offset temperature format as PECI though it contains no sign bit Thermal management devices should infer the TconTtroL value as negative Thermal management algorithms should utilize the relative temperature value delivered over PECI in conjunction with the TcoNTROL MSR value to control or optimize fan speeds Figure 6 9 shows a conceptual fan control diagram using PECI temperatures The relative temperature value reported over PECI represents the data below the onset of thermal control circuit TCC activation as needed by PROCHOT assertions As the temperature approaches TCC activation the PECI value approaches zero TCC activates at a PECI count of zero 89 e n tel Thermal Specifications Figure 6 9 Conceptual Fan Control Diagram of PECI ba
56. voltage regulator m e Dual Core Intel Xeon Processor 5200 Series Electrical Specifications n tel The Dual Core Intel Xeon Processor 5200 Series provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage Vcc This will represent a DC shift in the load line It should be noted that a low to high or high to low voltage state change may result in as many VID transitions as necessary to reach the target core voltage Transitions above the specified VID are not permitted Table 2 12 includes VID step sizes and DC shift ranges Minimum and maximum voltages must be maintained as shown in Table 2 13 The VRM or EVRD utilized must be capable of regulating its output to the value defined by the new VID DC specifications for dynamic VID transitions are included in Table 2 12 and Table 2 13 Refer to the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for further details Power source characteristics must be guaranteed to be stable whenever the supply to the voltage regulator is stable 19 m n tel Dual Core Intel Xeon Processor 5200 Series Electrical Specifications Table 2 3 Voltage Identification Definition HEX VID6 VID5 VID4 VID3 VID2 VID1 Vcc_ MAX HEX VI D6 VID5 VI D4
57. 14 AG5 Source Sync Input Output A32 AH4 Source Sync Input Output A33 AH5 Source Sync Input Output A34 AIS Source Sync Input Output A35 AJ6 Source Sync Input Output A36 N4 Source Sync Input Output A37 P5 Source Sync Input Output ADS D2 Common Clk Input Output ADSTBO R6 Source Sync Input Output ADSTB1 AIDS Source Sync Input Output AP0 U2 Common Clk Input Output AP1 U3 Common Clk Input Output BCLK0 F28 CIk Input BCLK1 G28 Clk Input BINIT AD3 Common Clk Input Output BNR C2 Common Clk Input Output BPMO AJ2 Common Clk Input Output BPM1 AJ1 Common Clk Output BPM2 AD2 Common Clk Output BPM3 AG2 Common Clk Input Output BPM4 AF2 Common Clk Output BPM5 AG3 Common Clk Input Output BPRI G8 Common Clk Input BRO F3 Common Clk Input Output BR1 H5 Common Clk Input BSELO G29 CMOS ASync Output BSEL1 H30 CMOS ASync Output BSEL2 G30 CMOS Async Output DOO B4 Source Sync Input Output 47 intel Land Listing Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 3 of 20 Sheet 4 of 20 Pin Name N EE Direction Pin Name iig a md Direction D01 C5 Source Sync Input Output D41 F20 Source Sync Input Output DO2 A4 Source Sync Input Output D42 E21 Source Sync Input Output DO3 C6 Source Sync Input Output D43 F21 Source Sync Input Output DO4 A5 Source Sync Input Output D44 G21 Source Sync Inpu
58. 19 Power Other VCC AC27 Power Other VCC AG21 Power Other VCC AC28 Power Other VCC AG22 Power Other VCC AC29 Power Other VCC AG25 Power Other VCC AC30 Power Other VCC AG26 Power Other VCC AC8 Power Other VCC AG27 Power Other VCC AD23 Power Other VCC AG28 Power Other VCC AD24 Power Other VCC AG29 Power Other VCC AD25 Power Other VCC AG30 Power Other VCC AD26 Power Other VCC AG8 Power Other VCC AD27 Power Other VCC AG9 Power Other VCC AD28 Power Other VCC AH11 Power Other VCC AD29 Power Other VCC AH12 Power Other VCC AD30 Power Other VCC AH14 Power Other 50 intel Land Listing Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 9 of 20 Sheet 10 of 20 Pin Name Me or ias Direction Pin Name n a Direction VCC AH15 Power Other VCC AL15 Power Other VCC AH18 Power Other VCC AL18 Power Other VCC AH19 Power Other VCC AL19 Power Other VCC AH21 Power Other VCC AL21 Power Other VCC AH22 Power Other VCC AL22 Power Other VCC AH25 Power Other VCC AL25 Power Other VCC AH26 Power Other VCC AL26 Power Other VCC AH27 Power Other VCC AL29 Power Other VCC AH28 Power Other VCC AL30 Power Other VCC AH29 Power Other VCC AL9 Power Other VCC AH30 Power Other VCC AM11 Power Other VCC AH8 Power Other VCC AM12 Power Other VCC AH9 Power Other V
59. 200 Series Electrical Specifications 2 3 1 2 3 2 2 3 3 16 Twenty two lands are specified as Vm which provide termination for the FSB and provides power to the I O buffers The platform must implement a separate supply for these lands which meets the V4 specifications outlined in Table 2 12 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the Dual Core Intel Xeon Processor 5200 Seriesis capable of generating large average current swings between low and full power states This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate Larger bulk storage Cpguik such as electrolytic capacitors supply voltage during longer lasting changes in current demand by the component such as coming out of an idle condition Similarly they act as a storage well for current when entering an idle condition from a running condition Care must be taken in the baseboard design to ensure that the voltage provided to the processor remains within the specifications listed in Table 2 12 Failure to do so can result in timing violations or reduced lifetime of the component For further information and guidelines refer to the appropriate platform design guidelines Vcc Decoupling Vcc regulator solutions need to provide bulk capacitance with a low Effective Series Resistance ESR and the baseboard designer must assure a low interconnect resistance from the reg
60. 24 Power Other vss AL10 Power Other vss AG7 Power Other vss AL13 Power Other vss AH1 Power Other vss AL16 Power Other vss AH10 Power Other vss AL17 Power Other es fahm Power 0ther vss AL20 Power Other vss AH16 Power Other vss AL23 Power Other vss AH17 Power Other vss AL24 Power Other es aH20 Power Other vss AL27 Power Other vss AH23 Power Other vss AL28 Power Other vss AH24 Power Other vss AL3 Power Other vss AH3 Power Other vss AM1 Power Other vss AH6 Power Other vss AMIO Power Other vss AH7 Power Other vss AM13 Power Other VSS AJ10 Power Other VSS AM16 Power Other VSS AJ13 Power Other VSS AM17 Power Other VSS AJ16 Power Other VSS AM20 Power Other VSS AJ17 Power Other VSS AM23 Power Other VSS AJ20 Power Other VSS AM24 Power Other VSS AJ23 Power Other VSS AM27 Power Other Ivss A24 Powe rother vss AM28 Power Other VSS AJ27 Power Other VSS AMA Power Other VSS AJ28 Power Other VSS AM7 Power Other VSS AJ29 Power Other VSS AN1 Power Other VSS AJ30 Power Other VSS AN10 Power Other VSS AJ4 Power Other VSS AN13 Power Other VSS AJ7 Power Other vss AN16 Power Other VSS AK10 Power Other VSS AN17 Power Other vss AK13 Power Other vss AN2 Power Other vss AK16 Power Other vss AN20 Power Other vss AK17 Power Other vss AN23 Power Other vss AK2 Power Other vss AN24 Power Other vss AK20 Power Other vss B1 Power Other vss AK23 Power Other vss B11 Power Other vss AK24 Power Other vs
61. 5 DP1 Common CIk Input Output F7 VSS Power Other H16 DP2 Common Clk Input Output F8 D17 Source Sync Input Output H17 vss Power Other F9 D18 Source Sync Input Output H18 VSS Power Other G1 VSS Power Other H19 VSS Power Other G10 RESERVED H2 GTLREF_ADD Power Other Input G11 DBI1 Source Sync Input Output H20 VSS Power Other G12 DSTBN1 Source Sync Input Output H21 vss Power Other G13 D27 Source Sync Input Output H22 VSS Power Other G14 D29 Source Sync Input Output H23 VSS Power Other G15 D31 Source Sync Input Output H24 VSS Power Other G16 D32 Source Sync Input Output H25 VSS Power Other G17 D36 Source Sync Input Output H26 VSS Power Other G18 D35 Source Sync Input Output H27 vss Power Other G19 DSTBP2 Source Sync Input Output H28 VSS Power Other 63 intel Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 15 of 20 Sheet 16 of 20 Pin No Pin Name uu umi Direction Pin No Pin Name WEE Direction H29 vss Power Other K2 vss Power Other H3 vss Power Other K23 VCC Power Other H30 BSEL1 CMOS Async Output K24 VCC Power Other H4 RSP Common Clk Input K25 VCC Power Other H5 BR1 Common Clk Input K26 VCC Power Other H6 VSS Power Other K27 VCC Power Other H7 vss Power Other K28 VCC Power Other H8 vss Power Other
62. B The electrical interface that connects the processor to the chipset Also referred to as the processor system bus or the system bus All memory and I O transactions as well as interrupt messages pass between the processor and chipset over the FSB Dual Independent Bus DIB A front side bus architecture with one processor on each of several processor buses rather than a processor bus shared between two processor agents The DIB architecture provides improved performance by allowing increased FSB speeds and bandwidth Flexible Motherboard Guidelines FMB Estimate of the maximum values the Dual Core Intel Xeon Processor 5200 Series will have over certain time periods Actual specifications for future processors may differ Functional Operation Refers to the normal operating conditions in which all processor specifications including DC AC FSB signal quality mechanical and thermal are satisfied Storage Conditions Refers to a non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor lands should not be connected to any supply voltages have any I Os biased or receive any clocks Upon exposure to free air that is unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material
63. CC AM14 Power Other VCC AJ11 Power Other VCC AMIS Power Other VCC AJ12 Power Other VCC AM18 Power Other VCC AJ14 Power Other VCC AM19_ Power Other VCC AJ15 Power Other VCC AM21 Power Other VCC AJ18 Power Other VCC AM22 Power Other VCC AJ19 Power Other VCC AM25 Power Other VCC AJ21 Power Other VCC AM26 Power Other VCC AJ22 Power Other VCC AM29 Power Other VCC AJ25 Power Other VCC AM30 Power Other VCC AJ26 Power Other VCC AM8 Power Other VCC AJ8 Power Other VCC AM9 Power Other VCC AJ9 Power Other VCC AN11 Power Other VCC AK11 Power Other VCC AN12 Power Other VCC AK12 Power Other VCC AN14 Power Other VCC AK14 Power Other VCC AN15 Power Other VCC AK15 Power Other VCC AN18 Power Other VCC AK18 Power Other VCC AN19 Power Other VCC AK19 Power Other VCC AN21 Power Other VCC AK21 Power Other VCC AN22 Power Other VCC AK22 Power Other VCC AN25 Power Other VCC AK25 Power Other VCC AN26 Power Other VCC AK26 Power Other VCC AN8 Power Other VCC AK8 Power Other VCC AN9 Power Other VCC AK9 Power Other VCC J10 Power Other VCC AL11 Power Other VCC J11 Power Other VCC AL12 Power Other VCC J12 Power Other VCC AL14 Power Other VCC J13 Power Other 51 intel tard sina Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 11 of 20 Sheet 12 of 20 Pin Name N
64. DEI EE 96 7 3 Enhanced Intel SpeedStep Technology 97 Boxed Processor Spechficattons memes 99 CS ERR ol ele e e EE 99 8 2 Mechanical Specifications kk kk kk yak kak kak ka kya 101 8 2 1 Boxed Processor Heat Sink Dimensions CEK kk 101 8 2 2 Boxed Processor Heat Sink Weight r e 109 8 2 3 Boxed Processor Retention Mechanism and Heat Sink Support ei EE 109 8 3 Electrical Requitetments ecu exce rx aa et rea FUSE NERE adore K r R W n DAR ER k n S R k xwa kn 2 n 109 8 3 1 Fan Power Supply Active CEK uu sun nial crblnl Wela nakine na daa nail can n n 109 8 3 2 Boxed Processor Cooling Reoguirements kk kk kk 110 8 4 Boxed Processor Contents assia kaka aa nennen nennen ka nn nnn nn nnn 111 Debug Tools Specifications LLL kk kk kk kak kk kk enn 113 9 1 Debug Port System Requirements rr r eene 113 9 2 Target System Implementation kk nennen mener 113 9 2 1 System lmplementation memes 113 9 3 Logic Analyzer Interface LA 113 9 3 1 Mechanical Considerations r rr kak ka 114 9 3 2 Electrical Considerations r r rr kak ka 114 Dual Core Intel Xeon Processor 5200 Series Datasheet Figures 2 l Input Device Hyster siS u ul Eire ibas eie EH ER dE EEN dar bia 25 2 2 Dual Core Intel Xeon Processor E5200 Series Load Current versus Time 30 2 3 Dual Core Intel Xeon Processor X5200 Seri
65. EPR does not automatically assert PROCHOT As mentioned previously the PROCHOT signal is asserted when a high temperature situation is detected A minimum pulse width of 500 us is recommended when FORCEPR is asserted by the system Sustained activation of the FORCEPR signal may cause noticeable platform performance degradation Refer to the appropriate platform design guidelines for details on implementing the FORCEPR signal feature THERMTRI P Signal Regardless of whether or not Intel Thermal Monitor 1 or Intel Thermal Monitor 2 is enabled in the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached an elevated temperature refer to the THERMTRI P definition in Table 5 1 At this point the FSB signal THERMTRIP will go active and stay active as described in Table 5 1 THERMTRIP activation is independent of processor activity and does not generate any bus cycles Intel also recommends the removal of Var Bi Thermal Specifications n tel 6 3 6 3 1 Figure 6 8 6 3 1 1 Platform Environment Control I nterface PECI I ntroduction PECI offers an interface for thermal monitoring of Intel processor and chipset components It uses a single wire thus alleviating routing congestion issues Figure 6 8 shows an example of the PECI topology in a system with Dual Core Intel Xeon Processor 5200 Series PECI uses CRC checking on the host side to ensure reliable
66. MWAIT instruction that processor core is halted however the other processor continues normal operation The processor will transition to the Normal state upon the occurrence of SMI BINIT INIT LINT 1 0 NMI INTR or an interrupt delivered over the front side bus RESET will cause the processor to immediately initialize itself The return from a System Management Interrupt SMI handler can be to either Normal Mode or the HALT state See the Intel 64 and IA 32 Architecture Software Developer s Manual The system can generate a STPCLK while the processor is in the HALT state When the system deasserts STPCLK the processor will return execution to the HALT state While in HALT state the processor will process front side bus snoops and interrupts Extended HALT State Extended HALT state is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT state has been enabled via the BIOS When one of the processor cores executes the HALT instruction that processor core is halted however the other processor core continues normal operation The Extended HALT state is a lower power state than the HALT state or Stop Grant state The Extended HALT state must be enabled for the processor to remain within its specifications The processor will automatically transition to a lower core frequency and voltage operating point before entering the Extended HALT state Note that the processor
67. N3 VCC_DIE_ Power Other Output C11 D11 Source Sync Input Output SENSE C12 D14 Source Sync Input Output AN4 eee Power Other Output Gi SE Power other AN5 RESERVED C14 D52 Source Sync Input Output AN6 RESERVED C15 D51 Source Sync Input Output AN7 VID SELECT Power Other Output C16 vss Power Other AN8 VCC Power Other C17 DSTBP3 Source Sync Input Output AN9 VCC Power Other C18 D54 Source Sync Input Output B1 VSS Power Other C19 vss Power Other 61 intel Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 11 of 20 Sheet 12 of 20 Pin No Pin Name nx cu Direction Pin No Pin Name AE TA Direction C2 BNR Common Clk Input Output D29 VTT Power Other C20 DBI3 Source Sync Input Output D3 VSS Power Other C21 D58 Source Sync Input Output D30 VTT Power Other C22 VSS Power Other D4 HIT Common Clk Input Output C23 RESERVED D5 VSS Power Other C24 vss Power Other D6 vss Power Other C25 VIT Power Other D7 D20 Source Sync Input Output C26 VTT Power Other D8 D12 Source Sync Input Output C27 VTT Power Other D9 vss Power Other C28 VTT Power Other El RESERVED Power Other C29 VIT Power Other E10 D21 Source Sync Input Output C3 LOCK Common Clk Input Output E11 VSS Power Other C30 VIT Power Other E12 DSTBP1 Source Sync Input Output
68. NE INIT PWRGOOD SMI STPCLK TCK TDI TMS TRST 23 m n tel Dual Core Intel Xeon Processor 5200 Series Electrical Specifications 2 9 2 10 2 10 1 24 CMOS Asynchronous and Open Drain Asynchronous Signals Legacy input signals such as A20M IGNNE INIT SMI and STPCLK utilize CMOS input buffers Legacy output signals such as FERR PBE IERR PROCHOT and THERMTRIP utilize open drain output buffers All of the CMOS and Open Drain signals are required to be asserted deasserted for at least eight BCLKs in order for the processor to recognize the proper signal state See Section 2 13 for the DC specifications See Chapter 6 for additional timing requirements for entering and leaving the low power states Test Access Port TAP Connection Due to the voltage levels supported by other components in the Test Access Port TAP logic it is recommended that the processor s be first in the TAP chain followed by any other components within the system A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage Similar considerations must be made for TCK TDO TMS and TRST Two copies of each signal may be required with each driving a different voltage level Platform Environmental Control I nterface PECI DC Specifications PECI is an Intel proprietary one wire interface that provides a com
69. P7 Power Other VTT B28 Power Other vss R2 Power Other VTT B29 Power Other vss R23 Power Other VTT B30 Power Other vss R24 Power Other VTT C25 Power Other vss R25 Power Other VTT C26 Power Other vss R26 Power Other VTT C27 Power Other vss R27 Power Other VTT C28 Power Other vss R28 Power Other VTT C29 Power Other vss R29 Power Other VTT C30 Power Other vss R30 Power Other VTT D25 Power Other ss R Powe Other VIT D26 Power Other vss R7 Power Other VTT D27 Power Other vss T3 Power Other VTT D28 Power Other vss T6 Power Other VTT D29 Power Other vss T7 Power Other VTT D30 Power Other vss U1 Power Other VTT E30 Power Other vss U7 Power Other VTT F30 Power Other vss V23 Power Other VTT_OUT AA1 Power Other Output VSS V24 Power Other VTT_OUT J Power Other Output VSS V25 Power Other VTT_SEL F27 Power Other Output vss V26 Power Other VSS V27 Power Other VSS V28 Power Other VSS V29 Power Other VSS v3 Power Other VSS v30 Power Other 56 intel Table 4 2 Land Listing by Land Number Sheet 2 of 20 Pin No Pin Name JN Direction AA7 VSS Power Other AA8 VCC Power Other AB1 VSS Power Other AB2 IERR Open Drain Output AB23 VSS Power Other AB24 VSS Power Other AB25 VSS Pow
70. Power Other AH19 VCC Power Other AJ 28 VSS Power Other AH2 RESERVED AJ 29 VSS Power Other AH20 VSS Power Other AJ3 RESERVED AH21 VCC Power Other AJ 30 VSS Power Other AH22 VCC Power Other AJ4 VSS Power Other AH23 VSS Power Other AJ5 A34 Source Sync Input Output AH24 VSS Power Other AJ6 A35 Source Sync Input Output AH25 VCC Power Other AJ7 VSS Power Other AH26 VCC Power Other AJ 8 VCC Power Other 59 intel Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 7 of 20 Sheet 8 of 20 Pin No Pin Name na um Direction Pin No Pin Name ue v Direction AJ9 VCC Power Other AL18 VCC Power Other AK1 RESERVED AL19 VCC Power Other AK10 VSS Power Other AL2 PROCHOT Open Drain Output AK11 VCC Power Other AL20 VSS Power Other AK12 VCC Power Other AL21 VCC Power Other AK13 VSS Power Other AL22 VCC Power Other AK14 VCC Power Other AL23 vss Power Other AK15 VCC Power Other AL24 VSS Power Other AK16 VSS Power Other AL25 VCC Power Other AK17 VSS Power Other AL26 VCC Power Other AK18 VCC Power Other AL27 VSS Power Other AK19 VCC Power Other AL28 vss Power Other AK2 VSS Power Other AL29 VCC Power Other AK20 VSS Power Other AL3 VSS Power Other AK21 VCC Power Other AL30 VCC Power Other AK22 VCC
71. RDY assertion of the corresponding I O write bus transaction INIT INIT Initialization when asserted resets integer registers inside all processors without affecting their internal caches or floating point registers Each processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal and must connect the appropriate pins of all processor FSB agents LINT 1 0 LINT 1 0 Local APIC Interrupt must connect the appropriate pins of all FSB agents When the APIC functionality is disabled the LINTO INTR signal becomes INTR a maskable interrupt request signal and LINT1 NMI becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous These signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these pins as LINT 1 0 is the default configuration LL_ID 1 0 The LL_ID 1 0 signals are used to select the correct loadline slope for the processor These signals are not connected to the processor die LOCK 1 0 LOCK indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins of all proce
72. S A24 Power Other vss AE29 Power Other VSS A6 Power Other vss AE30 Power Other VSS A9 Power Other vss AE5 Power Other vss AA23 Power Other vss AE7 Power Other vss AA24 Power Other vss AF7 Power Other vss AA25 Power Other vss AF10 Power Other vss AA26 Power Other vss AF13 Power Other vss AA27 Power Other vss AF16 Power Other vss AA28 Power Other vss AF17 Power Other vss AA29 Power Other vss AF20 Power Other vss AA3 Power Other vss AF23 Power Other vss AA30 Power Other vss AF24 Power Other vss AA6 Power Other vss AF25 Power Other vss AA7 Power Other vss AF26 Power Other vss AB1 Power Other vss AF27 Power Other vss AB23 Power Other vss AF28 Power Other vss AB24 Power Other vss AF29 Power Other vss AB25 Power Other vss AF3 Power Other vss AB26 Power Other vss AF30 Power Other vss AB27 Power Other vss AF6 Power Other vss AB28 Power Other vss AG10 Power Other 53 intel T Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 15 of 20 Sheet 16 of 20 Pin Name N RL Direction Pin Name iig uu dnd Direction es AG13 Power 0ther vss AK28 Power Other vss AG16 Power Other vss AK29 Power Other vss AG17 Power Other vss AK30 Power Other vss AG20 Power Other vss AK5 Power Other vss AG23 Power Other vss AK7 Power Other vss AG
73. The Thermal Monitor feature is intended to help protect the processor in the event that an application exceeds the TDP recommendation for a sustained time period For more details on this feature refer to Section 6 2 To ensure maximum flexibility for future requirements systems should be designed to the Flexible Motherboard FMB guidelines even if a processor with lower power dissipation is currently planned Intel Thermal Monitor 1 and Intel Thermal Monitor 2 feature must be enabled for the processor to remain within its specifications Thermal Specifications n tel Table 6 1 Figure 6 1 Dual Core I ntel Xeon Processor E5200 Series Thermal Specifications Core Thermal Minimum Maximum Frequency Design Power TcasE TCASE Notes W C C Launch to FMB 65 5 See Figure 6 1 Table 6 2 1 2 3 4 5 Notes 1 These values are specified at Vcc max for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static Vcc and Icc combination wherein Vcc exceeds Vcc max at specified ICC Please refer to the loadline specifications in Chapter 2 13 1 i 2 Thermal Design Power TDP should be used for the processor thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at maximum Tease 3 These specifications are based on silicon characterization 4 Power specifications are defined at all VI D
74. U 50 Y 0 235 x 42 2 45 40 0 10 20 30 40 50 60 70 80 Power W Notes 1 The Dual Core Intel Xeon Processor X5200 Series Thermal Profile is representative of a volumetrically constrained platform Please refer to Table 6 4 and Table 6 5 for discrete points that constitute the thermal profile 2 Implementation of the Dual Core Intel Xeon Processor X5200 Series Thermal Profile should result in virtually no TCC activation Furthermore utilization of thermal solutions that do not meet the processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss See Section 6 2 for details on TCC activation 3 Refer to the Dual Core Intel Xeon Processor 5200 Series Thermal Mechanical Design Guidelines TMDG for system and environmental implementation details Dual Core I ntel Xeon Processor X5200 Series Thermal A Profile Table Sheet 1 of 2 Power W Tcase_max C 0 42 2 5 43 4 10 44 6 15 45 7 20 46 9 25 48 1 30 49 3 35 50 4 40 51 6 45 52 3 79 intel Table 6 4 Table 6 5 Table 6 6 80 Thermal Specifications Dual Core Intel Xeon Processor X5200 Series Thermal A Profile Table Sheet 2 of 2 Power W Tcase_max CC 50 54 0 55 55 1 60 56 3 65 57 5 70 58 7 75 59 8 80 61 0 Dual Core Intel Xeon Processor X5200 Series Thermal B Profile Table
75. a the BIOS The processor will remain in the lower bus to core frequency ratio and VID operating point of the Extended HALT state Extended HALT Snoop State While in the Extended HALT Snoop state snoops and interrupt transactions are handled the same way as in the HALT Snoop state After the snoop is serviced or the interrupt is latched the processor will return to the Extended HALT state Enhanced Intel SpeedStep Technology Dual Core Intel Xeon Processor 5200 Series supports Enhanced Intel SpeedStep Technology This technology enables the processor to switch between multiple frequency and voltage points which results in platform power savings Enhanced Intel SpeedStep Technology requires support for dynamic VID transitions in the platform Switching between voltage frequency states is software controlled For more configuration details also refer to the Intel 64 and IA 32 Architectures Software Developer s Manual Not all Dual Core Intel Xeon Processor 5200 Series are capable of supporting Enhanced Intel SpeedStep Technology More details on which processor frequencies will support this feature will be provided in the Dual Core Intel Xeon Processor 5200 Series Specification Update Enhanced Intel SpeedStep Technology creates processor performance states P states or voltage frequency operating points which are lower power capability states within the Normal state see Figure 7 1 for the Stop Clock State Machine for suppor
76. able 2 15 Table 2 12 through Table 2 17 list the DC specifications for the processor and are valid only while meeting specifications for case temperature TcAsg as specified in Chapter 6 Thermal Specifications clock frequency and input voltages Care should be taken to read all notes associated with each parameter Flexible Motherboard Guidelines FMB The Flexible Motherboard FMB guidelines are estimates of the maximum values the Dual Core Intel Xeon Processor 5200 Series will have over certain time periods The values are only estimates and actual specifications for future processors may differ Processors may or may not have specifications equal to the FMB value in the foreseeable future System designers should meet the FMB values to ensure their systems will be compatible with future Dual Core Intel Xeon Processor 5200 Series 27 m n tel Dual Core Intel Xeon Processor 5200 Series Electrical Specifications Table 2 12 Voltage and Current Specifications Sheet 1 of 2 Symbol Parameter Min Typ Max Unit Notes 1 11 VID VID range 0 850 1 3500 V Vcc Vcc for processor core See Table 2 13 and Figure 2 5 V 2 3 4 6 9 Launch FMB Figure 2 6 and Figure 2 6 Vcc boot Default VCC Voltage for 1 10 V 2 H initial power up Vvip STEP VID step size during a 12 5 mv i transition VvID_SHIFT Total allowable DC load line 450 mv 10 shift from VID steps Vr FSB termination voltage DC 1 045 1 10 1
77. age 0 275 V 0 500 Var V Positive edge threshold Vp voltage 0 550 V 0 725 Ver V High level output source l source Vou 0 75 Ver 6 0 N A mA Low level output sink lsi 0 5 1 0 mA sink VoL 0 25 V High impedance state leakage lleak to Ver N A 50 HA 2 Vieak Vor High impedance leakage to lleak GND N A 10 HA 2 Vieak Vor Chus Bus capacitance per node N A 10 pF 3 Signal noise immunity above Vnoise 300 MHz 0 1 Voy N A Vp p Note 1 Vy supplies the PECI interface PECI behavior does not affect V min max specifications 2 The leakage specification applies to powered devices on the PECI bus 3 One node is counted for each client and one node for the system host Extended trace lengths might appear as additional nodes I nput Device Hysteresis The input buffers in both client and host models must use a Schmitt triggered input design for improved noise immunity Use Figure 2 1 as a guide for input buffer design Input Device Hysteresis Mg Maximum Vp c Minimum Vp Minimum Valid Input Hysteresis Signal Range Maximum Vw Minimum Vy PECI Low Range PECI Ground 25 m n tel Dual Core Intel Xeon Processor 5200 Series Electrical Specifications 2 11 Note 2 12 26 Mixing Processors Intel supports and validates dual processor configurations only in which both processors operate with the same FSB frequenc
78. age to be delivered to the processor Vcc pins VID signals are open drain outputs which must be pulled up to V m Please refer to Table 2 15 for the DC specifications for these signals A voltage range is provided in Table 2 12 and changes with frequency The specifications have been set such that one voltage regulator can operate with all supported frequencies Individual processor VID values may be calibrated during manufacturing such that two devices at the same core frequency may have different default VID settings This is reflected by the VID range values provided in Table 2 3 The Dual Core Intel Xeon Processor 5200 Series uses six voltage identification signals VID 6 1 to support automatic selection of power supply voltages Table 2 3 specifies the voltage level corresponding to the state of VID 6 1 A 1 in this table refers to a high voltage level and a O refers to a low voltage level If the processor Socket is empty VID 6 1 111111 or the voltage regulation circuit cannot supply the voltage that is requested the voltage regulator must disable itself See the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for further details Although the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines defines VID 7 0 VID7 and VIDO are not used on the Dual Core Intel Xeon Processor 5200 Series VID7 is always hard wired low at the
79. al Specifications 6 2 1 2 Note 86 When the Intel Thermal Monitor 1 is enabled and a high temperature situation exists that is TCC is active the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor typically 30 50 Cycle times are processor speed dependent and will decrease as processor core frequencies increase A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the TCC goes inactive and clock modulation ceases With thermal solutions designed to the Dual Core Intel Xeon Processor E5200 Series Dual Core Intel Xeon Processor L5200 Series and Dual Core Intel Xeon Processor X5200 Series Thermal Profile it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable Refer to the Dual Core Intel Xeon Processor 5200 Series Thermal Mechanical Design Guidelines TMDG for information on designing a thermal solution The duty cycle for the TCC when activated by the Intel Thermal Monitor 1 is factory configured and cannot
80. be deasserted once the processor is in the Stop Grant state All processor cores will enter the Stop Grant state once the STPCLK pin is asserted Additionally all processor cores must be in the Stop Grant state before the deassertion of STPCLK Since the AGTL signal pins receive power from the front side bus these pins should not be driven allowing the level to return to V r for minimum power drawn by the termination resistors in this state In addition all other input pins on the front side bus should be driven to the inactive state BINIT will not be serviced while the processor is in Stop Grant state The event will be latched and can be serviced by software upon exit from the Stop Grant state RESET will cause the processor to immediately initialize itself but the processor will stay in Stop Grant state A transition back to the Normal state will occur with the de assertion of the STPCLK signal A transition to the Grant Snoop state will occur when the processor detects a snoop on the front side bus see Section 7 2 4 1 While in the Stop Grant state SMI INIT BINIT and LINT 1 0 will be latched by the processor and only serviced when the processor returns to the Normal state Only one occurrence of each event will be recognized upon return to the Normal state While in Stop Grant state the processor will process snoops on the front side bus and it will latch interrupts delivered on the front side bus The PBE signa
81. be modified The Intel amp Thermal Monitor 1 does not require any additional hardware software drivers or interrupt handling routines Intel Thermal Monitor 2 The Dual Core Intel Xeon Processor 5200 Series adds supports for an Enhanced Thermal Monitor capability known as Intel Thermal Monitor 2 This mechanism provides an efficient means for limiting the processor temperature by reducing the power consumption within the processor Intel Thermal Monitor 2 requires support for dynamic VID transitions in the platform Not all Dual Core Intel Xeon Processor 5200 Series are capable of supporting Intel Thermal Monitor 2 More detail on which processor frequencies will support Intel Thermal Monitor 2 will be provided in future releases of the Dual Core Intel Xeon Processor 5200 Series Thermal Mechanical Design Guidelines TMDG when available For more details also refer to the Intel 64 and A 32 Architectures Software Developer s Manual When Intel Thermal Monitor 2 is enabled and a high temperature situation is detected the Thermal Control Circuit TCC will be activated for both processor cores The TCC causes the processor to adjust its operating frequency via the bus multiplier and input voltage via the VID signals This combination of reduced frequency and VID results in a reduction to the processor power consumption A processor enabled for Intel Thermal Monitor 2 includes two operating points each consist
82. ble 2 18 and the appropriate platform design guidelines for additional details HIT HITM 1 0 1 0 HIT Snoop Hit and HITM Hit Modified convey transaction snoop operation results Any FSB agent may assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together Signal Definitions Table 5 1 intel Signal Definitions Sheet 5 of 8 Name IERR Type O Description IERR Internal Error is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the processor FSB This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor will keep IERR asserted until the assertion of RESET This signal does not have on die termination Notes IGNNE Z IGNNE Ignore Numeric Error is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating point instructions If GNNE is deasserted the processor generates an exception on a noncontrol floating point instruction if a previous floating point instruction caused an error GNNE has no effect when the NE bit in control register 0 CRO is set IGNNEZ is an asynchronous signal However to ensure recognition of this signal following an I O write instruction it must be valid along with the T
83. cifications for the BCLK 1 0 inputs are provided in Table 2 19 These specifications must be met while also meeting signal integrity requirements as outlined in Table 2 19 The Dual Core Intel Xeon Processor 5200 Series utilizes differential clocks Table 2 1 contains processor core frequency to FSB multipliers and their corresponding core frequencies Core Frequency to FSB Multiplier Configuration Core Frequency to Core Frequency Core Frequency Core Frequency ECB aie with 400 000 MHz with 333 333 MHz with 266 666 MHz Notes p Bus Clock Bus Clock Bus Clock 1 6 2 40 GHz 2 GHz 1 60 GHz 1 2 3 4 1 7 2 80 GHz 2 33 GHz 1 87 GHz 1 2 3 1 7 5 3 GHz 2 50 GHz 2 GHz 1 2 3 1 8 3 20 GHz 2 66 GHz 2 13 GHz 1 2 3 1 8 5 3 40 GHz 2 83 GHz 2 27 GHz 1 2 3 1 9 3 60 GHz 3 GHz 2 40 GHz 1 2 3 1 9 5 3 80 GHz 3 16 GHz 2 53 GHz 1 2 3 Notes 1 Individual processors operate only at or below the frequency marked on the package 2 Listed frequencies are not necessarily committed production frequencies 3 For valid processor core frequencies see Dual Core Intel Xeon Processor 5200 Series Specification Update 4 The lowest bus ratio supported by the Dual Core Intel Xeon Processor 5200 Series is 1 6 Front Side Bus Frequency Select Signals BSEL 2 0 Upon power up the FSB frequency is set to the maximum supported by the individual processor BSEL 2 0 are CMOS outputs which must be pulled up to Ver an
84. d are used to select the FSB frequency Please refer to Table 2 14 for DC specifications Table 2 2 defines the possible combinations of the signals and the frequency associated with each combination The frequency is determined by the processor s chipset and clock synthesizer All FSB agents must operate at the same core and FSB frequency See the appropriate platform design guidelines for further details 17 m n tel Dual Core Intel Xeon Processor 5200 Series Electrical Specifications Table 2 2 2 4 2 2 5 18 BSEL 2 0 Frequency Table BSEL2 BSEL1 BSELO Bus Clock Frequency 0 0 0 266 66 MHz 0 0 1 Reserved 0 1 0 Reserved 0 1 1 Reserved 1 0 0 333 33 MHz 1 0 1 Reserved 1 1 0 400 MHz 1 1 1 Reserved PLL Power Supply An on die PLL filter solution is implemented on the Dual Core Intel Xeon Processor 5200 Series The Vccp input is used for this configuration in Dual Core Intel Xeon Processor 5200 Series based platforms Please refer to Table 2 12 for DC specifications Refer to the appropriate platform design guidelines for decoupling and routing guidelines Voltage Identification VI D The Voltage Identification VID specification for the Dual Core Intel Xeon Processor 5200 Series is defined by the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines The voltage set by the VID signals is the reference VR output volt
85. dDual Core Intel Xeon Processor X5200 Series and Dual Core Intel amp Xeon Processor L5200 Series VCC Static and Transient ToleframC i i ky lklkakk xalka kalak kk ka ka ka ar yaaa ka nnn nn nnns 31 2 14 AGTL Signal Group DC Gpeclcations rr mene 34 2 15 CMOS Signal Input Output Group and TAP Signal Group Metteg Le 34 2 16 Open Drain Output Signal Group DC Specifications rr 34 2 17 VCC Overshoot Specifications s xx a li al lad la aka ka aka ak kak kl kala a a kulak al arka a a a a ak eene ened 35 2 18 AGTL Bus Voltage Definitions ika yi kay kla ka klanan anak kuma kak ba w badan kaba ka h ra kal w n a kan kala 36 2 19 FSB Differential BCLK Specifications Lk hk WC hkkkk kk kk kk kk kk kak nen 36 3 1 Package Loading Gpechficattons rasara kakkakak mmm menn 43 3 2 Package Handling Guidelines k Kh kW kkklk kk kk kk kk kaka kak kk kaka 44 3 3 Processor Materials u uu u r uuu asa saa apanan pk aha eese nennen nenne aa j aaa qawa k aa 44 4 1 Land Listing by Land Name ra rr mms sese sie emen is esee nnn 47 4 2 Land Listing by Land Number 57 551 Signal Definitions u uuu et RARO CR RUE ee Ed EE a DER beji da 67 6 1 Dual Core Intel Xeon Processor E5200 Series Thermal Specifications 77 6 2 Dual Core Intel Xeon Processor E5200 Series Thermal Profile Table 78 6 3 Dual Core Intel Xeon Processor X5200 Series Thermal Specificatio
86. dual processor system will have up to 2010 grams total mass in the heat sinks This large mass will require a minimum chassis stiffness to be met in order to withstand force during shock and vibration See Chapter 3 for details on the processor weight Boxed Processor Retention Mechanism and Heat Sink Support CEK Baseboards and chassis designed for use by a system integrator should include holes that are in proper alignment with each other to support the boxed processor Refer to the Server System Infrastructure Specification SSI EEB 3 6 TEB 2 1 or CEB 1 1 These specification can be found at http www ssiforum org Figure 8 3 illustrates the Common Enabling Kit CEK retention solution The CEK is designed to extend air cooling capability through the use of larger heat sinks with minimal airflow blockage and bypass CEK retention mechanisms can allow the use of much heavier heat sink masses compared to legacy limits by using a load path directly attached to the chassis pan The CEK spring on the secondary side of the baseboard provides the necessary compressive load for the thermal interface material The baseboard is intended to be isolated such that the dynamic loads from the heat sink are transferred to the chassis pan via the stiff screws and standoffs The retention scheme reduces the risk of package pullout and solder joint failures All components of the CEK heat sink solution will be captive to the heat sink and will only require
87. e Table 2 3 The processor continues to execute instructions during the voltage transition Operation at the lower voltage reduces the power consumption of the processor A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the operating frequency and voltage transition back to the normal system operating point Transition of the VID code will occur first in order to insure proper operation once the processor reaches its normal operating frequency Refer to Figure 6 7 for an illustration of this ordering Intel Thermal Monitor 2 Frequency and Voltage Ordering True Temperature Frequency Vcc d Time V T hysterisis The PROCHOT signal is asserted when a high temperature situation is detected regardless of whether Intel Thermal Monitor 1 or Intel Thermal Monitor 2 is enabled On Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption This mechanism is referred to as On Demand mode and is distinct from the Intel Thermal Monitor 1 and Intel Thermal Monitor 2 features On Demand mode is intended as a means to reduce system level power consumption Systems utilizi
88. ed Additionally utilization of a thermal solution that does not meet Thermal Profile B will violate the thermal specifications and may result in permanent damage to the processor Intel has developed these thermal profiles to allow customers to choose the thermal solution and environmental parameters that best suit their platform implementation Refer to the Dual Core Intel Xeon Processor 5200 Series Thermal Mechanical Design Guidelines TMDG for details on system thermal solution design thermal profiles and environmental considerations The upper point of the thermal profile consists of the Thermal Design Power TDP defined in Table 6 1 for the Dual Core Intel Xeon Processor E5200 Series Table 6 3 for the Dual Core Intel Xeon Processor X5200 Series and Table 6 6 for the Dual Core Intel Xeon Processor L5200 Series and the associated Tcase values The lower point of the thermal profile is the Tease max at 0 W power or no power draw Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods Intel recommends that complete thermal solution designs target the Thermal Design Power TDP indicated in Table 6 2 for the Dual Core Intel Xeon Processor E5200 Series Table 6 4 and Table 6 5 for the Dual Core Intel Xeon Processor X5200 Series for the Dual Core Intel Xeon Processor L5200 Series instead of the maximum processor power consumption
89. ed OR Table 2 7 outlines the signals which include on die termination Rrr Table 2 8 outlines non AGTL signals including open drain signals Table 2 9 provides signal reference voltages AGTL Signal Description Table AGTL signals with Ryr AGTL signals with no RTT A 37 3 ADS ADSTB 1 0 AP 1 0 BINIT BNR BPRI D 63 0 DBI 3 0 DBSY DEFER DP 3 0 DRDY DSTBN 3 0 DSTBP 3 0 HIT HITM LOCK MCERR REQ 4 0 RS 2 0 RSP TRDY BPM 5 0 RESET BR 1 0 Non AGTL Signal Description Table Signals with R77 FORCEPR 1 PROCHOT 2 Signals with no Rer A20M BCLK 1 0 BSEL 2 0 FERR PBE GTLREF_ADD GTLREF_DATA IERR IGNNE INIT LINTO INTR LINT1 NMI LL_ID 1 0 MS ID 1 0 PECI PWRGOOD SKTOCC SMI STPCLK TCK TDI TDO TESTHI 12 8 THERMTRIP TMS TRDY TRST VCC_DIE_SENSE VCC DIE SENSE2 VID 6 1 VID SELECT VSS DIE SENSE VSS DIE SENSE2 VIT SEL Notes 1 These signals have RTT in the package with a 80 Q pullup to Vmr 2 These signals have RTT in the package with a 50 Q pullup to Ver Signal Reference Voltages GTLREF CMOS A 37 3 ADS ADSTB 1 0 AP 1 0 BINIT BNR BPM 5 0 BPRI BR 1 0 D 63 0 DBI 3 0 DBSY DEFER DP 3 0 DRDY DSTBN 3 0 DSTBP 3 0 FORCEPR HIT HITM LOCK MCERR RESET REQ 4 0 RS 2 0 RSP TRDY A20M LINTO INTR LINT1 NMI IGN
90. ed to call out specifications that are unique to the Dual Core Intel Xeon Processor L5238 SKU Dual Core Intel Xeon Processor L5215 Intel 64 bit microprocessor intended for dual processor server blades and embedded servers The Dual Core Intel Xeon Processor L5215 is a lower voltage and lower power version of the Dual Core Intel Xeon Processor L5200 Series supporting higher case temperatures It supports a Thermal Profile with nominal and short term conditions designed to meet Network Equipment Building System NEBS level 3 compliance For this document Dual Core Intel Xeon Processor L5215 is used to call out specifications that are unique to the Dual Core Intel Xeon Processor L5215 SKU FC LGA Flip Chip Land Grid Array Package The Dual Core Intel Xeon Processor 5200 Series package is a Land Grid Array consisting of a processor core 11 12 ntel mounted on a pinless substrate with 771 lands and includes an integrated heat spreader IHS LGA771 socket The Dual Core Intel Xeon Processor 5200 Series interfaces to the baseboard through this surface mount 771 Land socket See the LGA771 Socket Design Guidelines for details regarding this socket Processor core Processor core with integrated L1 cache L2 cache and system bus interface are shared between the two cores on the die All AC timing and signal integrity specifications are at the pads of the system bus interface Front Side Bus FS
91. el Xeon Processor 5200 Series supports a Dual Independent Bus DIB architecture with one processor on each bus up to two processor sockets in a system The DIB architecture provides improved performance by allowing increased FSB speeds and bandwidth The Dual Core Intel Xeon Processor 5200 Series will be packaged in an FC LGA Land Grid Array package with 771 lands for improved power delivery It utilizes a surface mount LGA771 socket that supports Direct Socket Loading DSL Dual Core Intel Xeon Processor 5200 Series of Processor L1 Cache ES ss is Md Package Cores q y 2 6 MB shared 1600 MHz FC LGA 32 KB instruction per core 1333 MHz 771 Lands 32 KB data per core 1066 MHz The Dual Core Intel Xeon Processor 5200 Series based platforms implement independent core voltage Vcc power planes for each processor FSB termination voltage Vor is shared and must connect to all FSB agents The processor core voltage utilizes power delivery guidelines specified by VRM EVRD 11 0 and its associated load line see Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for further details VRM EVRD 11 0 will support the power requirements of all frequencies of the Dual Core Intel Xeon Processor 5200 Series including Flexible Motherboard Guidelines FMB see Section 2 13 1 Refer to the appropriate platform design guidelines for implementation details The Dual Core Intel Xeon Pr
92. environmental implementation details 82 Thermal Specifications n tel Table 6 9 Dual Core Intel Xeon Processor L5238 Thermal Profile Table Power W Nominal Tcase_max CC Short term Tcase_ max C 0 45 60 5 49 64 10 52 67 15 56 71 20 60 75 25 64 79 30 67 82 35 71 86 Table 6 10 Dual Core Intel Xeon Processor L5215 Thermal Specifications Core Thermal Minimum Maximum F Design Power TcasE TcasE Notes requency W C C Launch to FMB 20 5 See Figure 6 5 Table 6 11 1 2 3 4 5 Notes 1 These values are specified at Vcc max for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds Vcc max at specified ICC Please refer to the loadline specifications in Section 2 13 D 2 Thermal Design Power TDP should be used for processor thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at maximum Teaser 3 These specifications are based pre silicon estimates and simulations These specifications will be updated with characterized data from silicon measurements in a future release of this document 4 Power specifications are defined at all VI Ds found in Table 2 12 The Dual Core Intel Xeon Processor L5215 may be shipped under multiple VI Ds for each frequency 5 FMB or Flexible Motherboard
93. er Other AB26 VSS Power Other AB27 VSS Power Other AB28 VSS Power Other AB29 VSS Power Other AB3 MCERR Common Clk Input Output AB30 VSS Power Other AB4 A26 Source Sync Input Output AB5 A24 Source Sync Input Output AB6 A17 Source Sync Input Output AB7 vss Power Other AB8 VCC Power Other AC1 TMS TAP Input AC2 DBR Power Other Output AC23 VCC Power Other AC24 VCC Power Other AC25 VCC Power Other AC26 VCC Power Other AC27 VCC Power Other AC28 VCC Power Other AC29 VCC Power Other AC3 vss Power Other AC30 VCC Power Other AC4 RESERVED AC5 A25 Source Sync Input Output AC6 VSS Power Other AC7 VSS Power Other AC8 VCC Power Other AD1 TDI TAP Input AD2 BPM2 Common Clk Output AD23 VCC Power Other AD24 VCC Power Other AD25 VCC Power Other Land Listing 4 1 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 1 of 20 Pin No Pin Name ur ox Direction A10 D08 Source Sync Input Output A11 D09 Source Sync Input Output A12 vss Power Other A13 RESERVED A14 D50 Source Sync Input Output A15 vss Power Other A16 DSTBN3 Source Sync Input Output A17 D56 Source Sync Input Output A18 vss Power Other A19 D61 Source Sync Input Output A2 vss Power Other A20 RESERVED A21 vss Power Other A22 D62 Source Sync Input Output A23 RESERVED A24 vss Power Other A25 VTT Power Other A26 VTT Power Other A3 RS2 Common Clk Input A4 D02 Source Sync Input Output A5 D04 So
94. es DBI 3 0 1 0 DBI 3 0 Data Bus Inversion are source synchronous and indicate the polarity of the D 63 0 signals The DBI 3 0 signals are activated when the data on the data bus is inverted If more than half the data bits within within a 16 bit group would have been asserted electronically low the bus agent may invert the data bus signals for that particular sub phase for that 16 bit group DBI 3 0 Assignment to Data Bus Bus Signal Data Bus Signals DBIO D 15 0 DBI1 D 31 16 DBI2 D 47 32 DBI3 D 63 48 DBR DBR is used only in systems where no debug port connector is implemented on the system board DBR is used by a debug port interposer so that an in target probe can drive system reset If a debug port connector is implemented in the system DBR is a no connect on the Dual Core Intel Xeon Processor 5200 Series package DBR is not a processor signal DBSY 1 0 DBSY Data Bus Busy is asserted by the agent responsible for driving data on the processor FSB to indicate that the data bus is in use The data bus is released after DBSY is deasserted This signal must connect the appropriate pins on all processor FSB agents DEFER DEFER is asserted by an agent to indicate that a transaction cannot be guaranteed in order completion Assertion of DEFER is normally the responsibility of the addressed memory or I O agent This signal must connect the app
95. es Load Current versus Time 30 2 4 Dual Core Intel Xeon Processor L5200 Series Load Current versus Time 31 2 5 Dual Core Intel amp Xeon Processor E5200 Series VCC Static and Transient Tolerance Load Lines a emen 32 2 6 Dual Core Intel Xeon Processor X5200 Series VCC Static and Transient Tolerance Load Lines rr r rr kak kk kaka 33 2 7 Dual Core Intel Xeon Processor L5200 Series VCC Static and Transient Tolerance Load Lines u cciam RR CERE RE NRRTNTEREMQRXRG WWW ERER a B 33 2 8 VCC Overshoot Example Waverorm r kk kk kk kk kk kk kk kk ka k ya ka kak kaka ke 35 2 9 Electrical Test Circuit e ec na kak cada A kbk a al nh d wira n AW A W ka nia M HWR ERN dA 37 2 10 Differential Clock Waveform kak kk eee kak kaka kk kak kk kak EEE EES 38 2 11 Differential Clock Crosspoint Gpechfication r rr e 38 2 12 Differential Rising and Falling Edge Rates rr me 38 3 1 Processor Package Assembly Sketch 39 3 2 Dual Core Intel Xeon Processor 5200 Series Package Drawing Sheet 1 of 3 40 3 3 Dual Core Intel Xeon Processor 5200 Series Package Drawing Sheet 2 of 3 41 3 4 Dual Core Intel Xeon Processor 5200 Series Package Drawing Sheet 3 of 3 42 3 5 Processor Top side Markings Example rr memes 45 3 6 Processor Land Coordinates Top View
96. es Software Developer s Manual for specific register and programming details PROCHOT is designed to assert at or a few degrees higher than maximum Tease when dissipating TDP power and cannot be interpreted as an indication of processor case temperature This temperature delta accounts for processor package lifetime and manufacturing variations and attempts to ensure the Thermal Control Circuit is not activated below maximum Tease when dissipating TDP power There is no defined or fixed correlation between the PROCHOT trip temperature or the case temperature Thermal solutions must be designed to the processor specifications and cannot be adjusted based on experimental measurements of Tcase or PROCHOT FORCEPR Signal The FORCEPR force power reduction input can be used by the platform to cause the Dual Core Intel Xeon Processor 5200 Series to activate the TCC If the Thermal Monitor is enabled the TCC will be activated upon the assertion of the FORCEPR signal Assertion of the FORCEPR signal will activate TCC for all processor cores The TCC will remain active until the system deasserts FORCEPR FORCEPRZ is an asynchronous input FORCEPR can be used to thermally protect other system components To use the VR as an example when FORCEPR is asserted the TCC circuit in the processor will activate reducing the current consumption of the processor and the corresponding temperature of the VR It should be noted that assertion of FORC
97. eter PECI replaces the thermal diode available in previous processors Intel Virtualization Technology Processor virtualization which when used in conjunction with Virtual Machine Monitor software enables multiple robust independent software environments inside a single platform VRM Voltage Regulator Module DC DC converter built onto a module that interfaces with a card edge socket and supplies the correct voltage and current to the processor based on the logic state of the processor VID bits EVRD Enterprise Voltage Regulator Down DC DC converter integrated onto the system board that provides the correct voltage and current to the processor based on the logic state of the processor VID bits Vcc The processor core power supply Vss The processor ground Ver FSB termination voltage State of Data The the data contained within this document is the most accurate information available by publication date of this document References Material and concepts available in the following documents may be beneficial when reading this document Document Document Number Notes AP 485 Intel Processor Identification and the CPUID Instruction 241618 2 Intel 64 and IA 32 Architectures Software Developer s Manual Volume 1 253665 2 Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2A 253666 Intel 64 and IA 32 Architectures Software Developer s Manual Volume
98. exceed 96 hours per instance 360 hours per year and a maximum of 15 instances per year as compliant with NEBS Level 3 5 Utilization of a thermal solution that exceeds the Short Term Thermal Profile or which operates at the Short Term Thermal Profile for a duration longer than the limits specified in Note 4 above do not meet the processor thermal specifications and may result in permanent damage to the processor 6 Refer to the Dual Core Intel Xeon Processor 5200 Series in Embedded Thermal Mechanical Design Guidelines TMDG for system and environmental implementation details Dual Core Intel Xeon Processor L5215 Thermal Profile Table Power W Nominal Tcase_max C Short term Tcase_max C 0 45 60 2 48 63 4 51 66 6 54 69 8 57 72 10 60 75 12 63 78 14 66 81 16 69 84 18 72 87 20 75 90 Thermal Metrology The minimum and maximum case temperatures TcAsg are specified in Table 6 2 Table 6 4 Table 6 5 Table 6 7 and Table 6 9 are measured at the geometric top center of the processor integrated heat spreader IHS Figure 6 6 illustrates the location where TcAse temperature measurements should be made For detailed guidelines on temperature measurement methodology refer to the Dual Core Intel Xeon Processor 5200 Series Thermal Mechanical Design Guidelines TMDG m Thermal Specifications n tel Figure 6 6 Case Temperature TcAsg Measurement Location 6 2 6 2 1
99. f a 400 MHz system clock making 12 80 GBytes per second data transfer rates possible Enhanced thermal and power management capabilities are implemented including Intel Thermal Monitor 1 Intel amp Thermal Monitor 2 and Enhanced Intel SpeedStep Technology These technologies are targeted for dual processor configurations in enterprise environments Intel Thermal Monitor 1 and Intel Thermal Monitor provide efficient and effective cooling in high temperature situations Enhanced Intel SpeedStep Technology provides power management capabilities to servers and workstations Dual Core Intel Xeon Processor 5200 Series features include Intel Wide Dynamic Execution enhanced floating point and multi media units Streaming SIMD Extensions 2 SSE2 Streaming SIMD Extensions 3 SSE3 and Streaming SIMD Extensions 4 1 SSE4 1 Advanced Dynamic Execution improves speculative execution and branch prediction internal to the processor The floating point and multi media units include 128 bit wide registers and a separate register for data movement SSE3 instructions provide highly efficient double precision floating point SIMD integer and memory management operations The Dual Core Intel Xeon Processor 5200 Series support Intel 64 Architecture as an enhancement to Intel s IA 32 architecture This enhancement allows the processor to execute operating systems and applications written to take advantage of the 64 bit extension technology Furthe
100. gt K PE e 2 m e e s co 105 e n tel Boxed Processor Specifications Figure 8 8 Volumetric Height Keep Ins a e m lt 06 po NOT SCALE DRAWING SHEET 5 OF s n R 8 2 als 3 an ie Tal F xx 1 8 EE 3 r lt lt x 6 99 215 88 9 3 50 96 52 3 800 VOLUMETRIC HEIGHT KEEPINS 106 ntel Boxed Processor Specifications 4 Pin Fan Cable Connector For Active CEK Heat Sink Figure 8 9 SOF w 1833883101 EUR M R A4 6118 25056 V vg YINYS dil09 61185 X08 0 d Q8 3931100 NOISSIN 002 o NO 14132930 ASSV_ 3d ALO Y3QWON Lyvd ON Mil SR E Ws PI ISNY 83d 9NI2NY33101 ONY 9NINOISN3WIO P Aren JO ONILYY ALITIGYWNYTS TA W WININ V JAVH TIVHS Luvd Q3HSIN LJ ALI TIL OYWHVT AYOAL 8010 NOTAN IWIYJLYN I 8310N 40 9 Y2 V V N011235 ird er TIANI 40 1N35N02 N3LLI3 amp HOI Yd m 0T8 0l 80 6 1 INO Nid 03N1902 YS 0 XE ANOHLIA G31 4100 XO 031Y14810 0301004434 018019810 30 LON m 0 E t 0091 Kr 107 Boxed Processor Specifications ntel Figure 8 10
101. guidelines provide a design target for meeting all planned processor frequency requirements Figure 6 5 Dual Core Intel Xeon Processor L5215 Thermal Profile Thermal Profile 1 00 Short term Thermal Profile may only be used for short term excursions to higher ambient temperatures not to exceed 360 hours per year Toase max TDP m we _ 80 m mee Q 70 Tes 15 P 60 _ 7 _ DI s _ _ o A 8 60 T E Tese 1 5 P 45 50 Nominal Short Term 40 30 0 5 10 15 20 Power W Notes 1 Dual Core Intel Xeon Processor L5215 Thermal Profile is representative of a volumetrically constrained platform Please refer to Table 6 11 for discrete points that constitute the thermal profile 83 Table 6 11 6 1 2 84 Thermal Specifications 2 Implementation of the Dual Core Intel Xeon Processor L5215 Thermal Profile should result in virtually no TCC activation Furthermore utilization of thermal solutions that do not meet the processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss See Section 6 2 for details on TCC activation 3 The Nominal Thermal Profile must be used for all normal operating conditions or for products that do not require NEBS Level 3 compliance 4 The Short Term Thermal Profile may only be used for short term excursions to higher ambient operating temperatures not to
102. he crossing point must meet the absolute and relative crossing point specifications simultaneously 9 Vyayg Can be measured directly using Vtop on Agilent and High on Tektronix oscilloscopes 10 For Vin between 0 V and Vu 11 AVcnoss is defined as the total variation of all crossing voltages as defined in note 3 12 Measured from 200 mV to 200 mV on the differential waveform derived from REFCLK minus REFCLK The signal must be monotonic through the measurement region for rise and fall time The 400 mV measurement window is centered on the differential zero crossing See Figure 2 12 Electrical Test Circuit Buffer Vit Vit Rtt 55 Ohms 55 Ohms 160 ps in 600 mils 0 3nH 0 9nH 0 6nH gt Y OYN WWW WEN 1 3pF 0 2pF Long Package gt Rioad AC Timings specified at this point Buffer pad 37 m n tel Dual Core Intel Xeon Processor 5200 Series Electrical Specifications Figure 2 10 Differential Clock Waveform ux c LENT MX ER cl Overshoot BCLK1 LL VH Rising Edge mI MEM MEER DD u an Ringback KS R Crossing Ringback Threshold j Voltage Margin Region pA 1 m Falling Edge EEN Bd ids ud di sores dcs es eerte Ringback BeO E LL WE EE T OO N Undershoot Ti lt P 2 Tp T1 BCLK 1 0 period Figure 2 11 Differential Clock Crosspoint Specification 650 e
103. ied VID Individual processor VID values may be calibrated during manufacturing such that two devices at the same frequency may have different VID settings This specification applies to the VCCPLL land Baseboard bandwidth is limited to 20 MHz lec toc is the sustained DC equivalent current that the processor is capable of drawing indefinitely and should be used for the voltage regulator temperature assessment The voltage regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the processor of a thermal excursion Please see the applicable design guidelines for further details The processor is capable of drawing Icc tpc indefinitely Refer to Figure 2 1 for further details on the average processor current draw over various time durations This parameter is based on design characterization and is not tested This is the maximum total current drawn from the V plane by only one processor with Ry enabled This specification does not include the current coming from on board termination Rrr through the signal line Refer to the appropriate platform design guide and the Voltage Regulator Design Guidelines to determine the total lr drawn by the system This parameter is based on design characterization and is not tested lec vit our iS specified at 1 1 V Icc reset is specified while PWRGOOD and RESET are asserted Figure 2 2 Dual Core Intel Xeon Processor E5200 Series Load Current versus Time
104. ing of a specific operating frequency and voltage which is identical for both processor cores The first operating point represents the normal operating condition for the processor Under this condition the core frequency to system bus multiplier utilized by the processor is that contained in the CLOCK_FLEX_MAX MSR and the VID that is specified in Table 2 3 The second operating point consists of both a lower operating frequency and voltage The lowest operating frequency is determined by the lowest supported bus ratio 1 6 for the Dual Core Intel Xeon Processor 5200 Series When the TCC is activated the processor automatically transitions to the new frequency This transition occurs rapidly on the order of 5 us During the frequency transition the processor is unable to Bi Thermal Specifications n tel Figure 6 7 6 2 2 service any bus requests and consequently all bus traffic is blocked Edge triggered interrupts will be latched and kept pending until the processor resumes operation at the new frequency Once the new operating frequency is engaged the processor will transition to the new core operating voltage by issuing a new VID code to the voltage regulator The voltage regulator must support dynamic VID steps in order to support Intel Thermal Monitor 2 During the voltage change it will be necessary to transition through multiple VID codes to reach the target operating voltage Each step will be one VID table entry se
105. input or I O signals use pull up resistors of the same value as the on die termination resistors Rrr For details see Table 2 18 TAP CMOS Asynchronous inputs and CMOS Asynchronous outputs do not include on die termination Inputs and utilized outputs must be terminated on the baseboard Unused outputs may be terminated on the baseboard or left unconnected Note that leaving unused outputs unterminated may interfere with some TAP functions complicate debug probing and prevent boundary scan testing Signal termination for these signal types is discussed in the appropriate platform design guidelines The TESTHI signals must be tied to the processor V using a matched resistor where a matched resistor has a resistance value within 2096 of the impedance of the board transmission line traces For example if the trace impedance is 509 then a value between 400 and 600 is required 21 m n tel Dual Core Intel Xeon Processor 5200 Series Electrical Specifications The TESTHI signals must use individual pull up resistors as detailed below A matched resistor must be used for each signal TESTHI8 cannot be grouped with other TESTHI signals TESTHI9 cannot be grouped with other TESTHI signals TESTHI10 cannot be grouped with other TESTHI signals TESTHI11 cannot be grouped with other TESTHI signals TESTHI12 cannot be grouped with other TESTHI signals 2 7 Front Side Bus Signal Groups The FSB signals have been combi
106. ins and reduced ringing through low voltage swings and controlled edge rates AGTL buffers are open drain and require pull up resistors to provide the high logic level and termination AGTL output buffers differ from GTL buffers with the addition of an active PMOS pull up transistor to assist the pull up resistors during the first clock of a low to high voltage transition Platforms implement a termination voltage level for AGTL signals defined as V m Because platforms implement separate power planes for each processor and chipset separate Vcc and V supplies are necessary This configuration allows for improved noise tolerance as processor frequency increases Speed enhancements to data and address buses have made signal integrity considerations and platform design methods even more critical than with previous processor families Design guidelines for the processor FSB are detailed in the appropriate platform design guidelines refer to Section 1 3 The AGTL inputs require reference voltages GTLREF_DATA and GTLREF_ADD which are used by the receivers to determine if a signal is a logical 0 or a logical 1 GTLREF_DATA is used for the 4X front side bus signaling group and GTLREF_ADD is used for the 2X and common clock front side bus signaling groups Both GTLREF_DATA and GTLREF_ADD must be generated on the baseboard See Table 2 18 for GTLREF_DATA and GTLREF_ADD specifications Refer to the applicable platform design guidelines for detail
107. l Xeon Processor 5200 Series Electrical Specifications 15 2 1 Front Side Bus and GTLREF een eaten n nnns 15 2 2 Power and Ground La dsu s si ceste reor EAR hie nane an h Feb A Ek E REEDER 15 2 3 Decoupling Guidelil S sissi cika dun nn aka nan banka ia kay emen seneeemememesi e senis 16 2 3 1 VCC Deco pling ee ios Vek aa ban Ee e kenl sana n hinl nne cs ede 16 2 3 25 VIE D GOUDIIR Le VE 16 2 3 3 Front Side Bus AGTL Decoupling r rr 16 2 4 Front Side Bus Clock BCLK 1 0 and Processor Clocking 17 2 4 1 Front Side Bus Frequency Select Signals BSEL 2 0 17 2 4 2 BEL Power Supply iie RR ad da Er M dan der nar Wa kak R w 18 2 5 Voltage Identification ID 18 2 6 Reserved Unused and Test Gigonals r rr nmm mmn 21 2 7 Front Side Bus Signal Groups 22 2 8 CMOS Asynchronous and Open Drain Asynchronous Gionals EEE 24 2 9 Test Access Port TAP Connection 24 2 10 Platform Environmental Control Interface PECI DC Specifications 24 2 10 1 DC Characteristics 2x xen su sa aspa ads wa Da ARR HR k a h ME EAR MEET Ee 24 2 10 2 Input Device Hysteresis sssssssssssse memes eee ener 25 2551 Mixing PrOCESSONS siut coh Db EE qa te err x re LU Nd RA ME HET EDU E cade 26 2 12 Absolute Maximum and Minimum Rating
108. l Specifications n tel Figure 6 3 Dual Core Intel Xeon Processor L5200 Series Thermal Profile Tcase C Thermal Profile Y 0 354 x 41 8 0 10 20 30 40 Power W Notes 1 Dual Core Intel Xeon Processor L5200 Series Thermal Profile is representative of a volumetrically constrained platform Please refer to Table 6 7 for discrete points that constitute the thermal profile 2 Implementation of the Dual Core Intel Xeon Processor L5200 Series Thermal Profile should result in virtually no TCC activation Furthermore utilization of thermal solutions that do not meet the processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss See Section 6 2 for details on TCC activation 3 Refer to the Dual Core Intel Xeon Processor 5200 Series Thermal Mechanical Design Guidelines TMDG for system and environmental implementation details Table 6 7 Dual Core Intel Xeon Processor L5200 Series Thermal Profile Table Power W Tcase Max C 0 41 8 5 43 6 10 45 3 15 47 1 20 48 9 25 50 7 30 52 4 35 54 2 40 56 0 81 e n tel Thermal Specifications Table 6 8 Dual Core Intel Xeon Processor L5238 Thermal Specifications Core Thermal Minimum Maximum Design Power TcasE TcasE Notes Frequency W CO GC Launch to FMB 35 5 See Figure 6 4 Table 6 8 1 2 3
109. l can be driven when the processor is in Stop Grant state PBE will be asserted if there is any pending interrupt latched within the processor Pending interrupts that are blocked by the EFLAGS IF bit being clear will still cause assertion of PBE Assertion of PBE indicates to system logic that it should return the processor to the Normal state Extended HALT Snoop or HALT Snoop State Stop Grant Snoop State The Extended HALT Snoop state is used in conjunction with the Extended HALT state If the Extended HALT state is not enabled in the BIOS the default Snoop state entered will be the HALT Snoop state Refer to the sections below for details on HALT Snoop state Stop Grant Snoop state and Extended HALT Snoop state HALT Snoop State Stop Grant Snoop State The processor will respond to snoop or interrupt transactions on the front side bus while in Stop Grant state or in HALT state During a snoop or interrupt transaction the processor enters the HALT Grant Snoop state The processor will stay in this state until the snoop on the front side bus has been serviced whether by the processor or another agent on the front side bus or the interrupt has been latched After the snoop is serviced or the interrupt is latched the processor will return to the Stop Grant state or HALT state as appropriate Features 7 2 4 2 7 3 Note intel The Extended HALT Snoop state is the default Snoop state when the Extended HALT state is enabled vi
110. l clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input Notes TCK TCK Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI TDI Test Data In transfers serial test data into the processor TDI provides the serial input needed for J TAG specification support TDO TESTHI 12 8 THERMTRIP TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for J TAG specification support TESTHI 12 8 must be connected to a V power source through a resistor for proper processor operation Refer to Section 2 6 for TESTHI grouping restrictions Assertion of THERMTRIP Thermal Trip indicates the processor junction temperature has reached a temperature beyond which permanent silicon damage may occur Measurement of the temperature is accomplished through an internal thermal sensor Upon assertion of THERMTRIP the processor will shut off its internal clocks thus halting program execution in an attempt to reduce the processor junction temperature To protect the processor its core voltage Vcc must be removed following the assertion of THERMTRI P Intel also recommends the removal of Ver when THERMTRIP is asserted Driving of the THERMTRI P signals is enabled within 10 us of the assertion of PWRGOOD and is disabled on de assertion of PWRGOOD
111. l processor FSB agents A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low While RS 2 0 000 RSP is also high since this indicates it is not being driven by any agent guaranteeing correct parity SKTOCC O SKTOCC Socket occupied will be pulled to ground by the processor to indicate that the processor is present There is no connection to the processor silicon for this signal SMI l SMI System Management Interrupt is asserted asynchronously by 2 system logic On accepting a System Management Interrupt processors save the current state and enter System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler If SMI is asserted during the deassertion of RESET the processor will tri state its outputs See Section 7 1 72 Signal Definitions Table 5 1 intel Signal Definitions Sheet 7 of 8 Name STPCLK Type l Description STPCLK Stop Clock when asserted causes processors to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the FSB and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is deasserted the processor restarts its interna
112. level thermal management features Component level thermal solutions can include active or passive heatsinks attached to the processor integrated heat spreader IHS Typical system level thermal solutions may consist of system fans combined with ducting and venting This section provides data necessary for developing a complete thermal solution For more information on designing a component level thermal solution refer to the Dual Core Intel Xeon Processor 5200 Series Thermal Mechanical Design Guidelines TMDG The boxed processor will ship with a component thermal solution Refer to Chapter 8 for details on the boxed processor Thermal Specifications To allow the optimal operation and long term reliability of Intel processor based systems the processor must remain within the minimum and maximum case temperature TCASE specifications as defined by the applicable thermal profile see Table 6 1 and Figure 6 1 for the Dual Core Intel Xeon Processor E5200 Series Table 6 3 and Figure 6 2 for the Dual Core Intel Xeon Processor X5200 Series Table 6 6 and Figure 6 3 for the Dual Core Intel Xeon Processor L5200 Series and Table 6 8 and Figure 6 4 for the Dual Core Intel Xeon Processor L5238 Thermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system For more details on thermal solution design please refer to the Dual Core Intel Xeon Processor 5200 Serie
113. lt power on condition that ensures proper processor operation during the time frame when reliable data is not available via PECI To protect platforms from potential operational or safety issues due to an abnormal condition on PECI the Host controller should take action to protect the system from possible damage It is recommended that the PECI host controller take appropriate action to protect the client processor device if valid temperature readings have not been obtained in response to three consecutive gettemp s or for a one second time interval The host controller may also implement an alert to software in the event of a critical or continuous fault condition PECI GetTempO Error Code Support The error codes supported for the processor GetTemp0 command are listed in Table 6 12 below Table 6 12 GetTempO Error Codes Error Code Description 0x8000h General sensor error 0x8002h Sensor is operational but has detected a temperature below its operational range underflow 91 92 Thermal Specifications Features 7 7 1 Table 7 1 7 2 intel Features Power On Configuration Options Several configuration options can be configured by hardware The Dual Core Intel Xeon Processor 5200 Series samples its hardware configuration at reset on the active to inactive transition of RESET For specifics on these options please refer to Table 7 1 The sampled information configures the processo
114. mance BPM 5 0 should connect the BPM 2 1 o appropriate pins of all FSB agents BPM0 1 0 BPM4 provides PRDY Probe Ready functionality for the TAP port PRDY is a processor output used by debug tools to determine processor debug readiness BPM5 provides PREQ Probe Request functionality for the TAP port PREQ is used by debug tools to request debug operation of the processors BPM 5 4 must be bussed to all bus agents Please refer to the appropriate platform design guidelines for more detailed information BPRI l BPRI Bus Priority Request is used to arbitrate for ownership of the 3 processor FSB It must connect the appropriate pins of all processor FSB agents Observing BPRI active as asserted by the priority agent causes all other agents to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by deasserting BPRI BR 1 0 I O The BR 1 0 signals are sampled on the active to inactive transition 3 of RESET The signal which the agent samples asserted determines its agent ID BRO drives the BREQO signal in the system and is used by the processor to request the bus These signals do not have on die termination and must be terminated BSEL 2 0 O The BCLK 1 0 frequency select signals BSEL 2 0 are used to select the processor input clock frequency Table 2
115. minal Vcc The VID setting represents the maximum expected VID when running in HALT state 3 The specification is at Tcase 409C and nominal Vcc The VID setting represents the maximum expected VID when running in HALT state The processor exits the Extended HALT state when a break event occurs When the processor exits the Extended HALT state it will first transition the VID to the original value and then change the bus to core frequency ratio back to the original value Stop Clock State Machine HALT or MWAIT Instruction and HALT Bus Cycle Generated N Stat Extended HALT or HALT State he j ii INIT BINIT INTR NMI SMI BCLK running DEE RESET FSB interrupts Snoops and interrupts allowed A A lt Snoop Snoop STPCLK amp STPCLK A Event Event Asserted De asserted Occurs Serviced Extended HALT Snoop or HALT Snoop State BCLK running Service snoops to caches Y Stop Grant State SE Stop Grant Snoop State BCLK running BCLK running Snoop Event Serviced Snoops and interrupts allowed Service snoops to caches 95 intel 7 2 4 7 2 4 1 96 Stop Grant State When the STPCLK pin is asserted the Stop Grant state of the processor is entered no later than 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle Once the STPCLK pin has been asserted it may only
116. munication channel between Intel processors and chipset components to external thermal monitoring devices The Dual Core Intel Xeon Processor 5200 Series contains Digital Thermal Sensor DTS sprinkled both inside and outside the cores in a die These sensors are implemented as analog to digital converters calibrated at the factory for reasonable accuracy to provide a digital representation of relative processor temperature PECI provides an interface to relay the highest DTS temperature within a die to external devices for thermal fan speed control More detailed information may be found in the Platform Environment Control Interface PECI Specification DC Characteristics The PECI interface operates at a nominal voltage set by Vr The set of DC electrical specifications shown in Table 2 10 is used with devices normally operating from a Ver interface supply V r nominal levels will vary between processor families All PECI devices will operate at the V level determined by the processor installed in the system For specific nominal V levels refer to the appropriate processor EMTS Dual Core Intel Xeon Processor 5200 Series Electrical Specifications n tel Table 2 10 PECI DC Electrical Limits 2 10 2 Figure 2 1 Symbol Definition and Conditions Min Max Units Notes1 Vin Input Voltage Range 0 150 Vr V Vhysteresis Hysteresis 0 1 Vr N A V Negative edge threshold Va volt
117. n Name RT Direction AG18 VCC Power Other AH27 VCC Power Other AG19 VCC Power Other AH28 VCC Power Other AG2 BPM3 Common Clk Input Output AH29 VCC Power Other AG20 VSS Power Other AH3 VSS Power Other AG21 VCC Power Other AH30 VCC Power Other AG22 VCC Power Other AH4 A32 Source Sync Input Output AG23 VSS Power Other AH5 A33 Source Sync Input Output AG24 vss Power Other AH6 vss Power Other AG25 VCC Power Other AH7 vss Power Other AG26 VCC Power Other AH8 VCC Power Other AG27 VCC Power Other AH9 VCC Power Other AG28 VCC Power Other AJ1 BPM1 Common Clk Output AG29 VCC Power Other AJ10 VSS Power Other AG3 BPM5 Common Clk Input Output AJ11 VCC Power Other AG30 VCC Power Other AJ12 VCC Power Other AG4 A30 Source Sync Input Output AJ 13 VSS Power Other AG5 A314 Source Sync Input Output AJ14 VCC Power Other AG6 A29 Source Sync Input Output AJ15 VCC Power Other AG7 VSS Power Other AJ16 VSS Power Other AG8 VCC Power Other AJ17 VSS Power Other AG9 VCC Power Other AJ18 VCC Power Other AH1 VSS Power Other AJ19 VCC Power Other AH10 VSS Power Other AJ2 BPM0 Common Clk Input Output AH11 VCC Power Other AJ20 VSS Power Other AH12 VCC Power Other AJ21 VCC Power Other AH13 VSS Power Other AJ 22 VCC Power Other AH14 VCC Power Other AJ 23 VSS Power Other AH15 VCC Power Other AJ 24 VSS Power Other AH16 vss Power Other AJ25 VCC Power Other AH17 VSS Power Other AJ 26 VCC Power Other AH18 VCC Power Other AJ27 VSS
118. n Output RESERVED C9 FORCEPR AK6 CMOS ASync Input RESERVED C23 GTLREF_ADD H2 Power Other Input RESERVED D1 GTLREF_DATA H1 Power Other Input RESERVED D14 HIT D4 Common Clk Input Output RESERVED D16 HITM E4 Common Clk Input Output RESERVED E1 IERR AB2 Open Drain Output RESERVED E23 IGNNE N2 CMOS ASync Input RESERVED E24 INIT P3 CMOS ASync Input RESERVED E5 LINTO K1 CMOS ASync Input RESERVED E6 LINT1 L1 CMOS ASync Input RESERVED E7 LL IDO V2 Power Other Output RESERVED F2 LL ID1 AA2 Power Other Output RESERVED F23 LOCK C3 Common Clk Input Output RESERVED F29 MCERR AB3 Common Clk Input Output RESERVED F6 MS IDO W1 Power Other Output RESERVED G10 MS_ID1 V1 Power Other Output RESERVED G2 PECI G5 Power Other Input Output RESERVED G6 PROCHOT AL2 Open Drain Output RESERVED J2 PWRGOOD N1 CMOS ASync Input RESERVED J3 REQO K4 Source Sync Input Output RESERVED N5 REQ1 J5 Source Sync Input Output RESERVED R1 REQ2 M6 Source Sync Input Output RESERVED T1 REQ3 K6 Source Sync Input Output RESERVED T2 REQ4 J6 Source Sync Input Output RESERVED W2 RESERVED AM6 RESERVED Y1 RESERVED A13 RESERVED Y3 RESERVED A20 RESERVED AL1 RESERVED A23 RESERVED AK1 RESERVED AC4 RESERVED G27 RESERVED AE4 RESERVED G26 RESERVED AE6 RESERVED G24 RESERVED AH2 RESERVED F24 RESERVED AJ3 RESERVED F26 RESERVED AK3 RESERVED F25 RESERVED AM2 RESERVED G25 RESERVED AN5 RESERVED w3 49 intel Land Listing
119. nch FMB lec toc Thermal Design Current 60 A 6 14 TDC Dual Core Intel Xeon Processor E5200 Series Launch FMB lec Toc Thermal Design Current 38 A 6 14 TDC Dual Core Intel Xeon Processor L5200 Series Launch FMB lec mme Thermal Design Current 35 A 6 14 TDC Dual Core Intel Xeon Processor L5238 Launch FMB lcc vrr out DC current that may be 580 mA 16 Dm drawn from Var our per land lcc_GTLREF lcc for 200 HA 7 GTLREF_DATA and GTLREF_ADD Icc_vccpLL lec for PLL supply 130 mA 12 Itcc Icc for Dual Core Intel 90 A Xeon Processor X5200 Series during active therma control circuit TCC Ircc I cc for Dual Core Intel 75 A Xeon Processor E5200 Series during active therma control circuit TCC Ircc Icc for Dual Core Intel 50 A Xeon Processor L5200 Series during active therma control circuit TCC Itcc Icc for Dual Core Intel 42 A Xeon Processor L5238 during active thermal control circuit TCC Notes 1 Unless otherwise noted all specifications in this table are based on final silicon characterization data 2 These voltages are targets only A variable voltage source should exist on systems in the event that a different voltage is required See Section 2 5 for more information 3 The voltage specification requirements are measured across the VCC DIE SENSE and VSS DIE SENSE lands and across the VCC DIE SENSE2 and
120. ned into groups by buffer type AGTL input signals have differential input buffers which use GTLREF_DATA and GTLREF_ADD as reference levels In this document the term AGTL Input refers to the AGTL input group as well as the AGTL I O group when receiving Similarly AGTL Output refers to the AGTL output group as well as the AGTL I O group when driving AGTL asynchronous outputs can become active anytime and include an active PMOS pull up transistor to assist during the first clock of a low to high voltage transition With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters One set is for common clock signals whose timings are specified with respect to rising edge of BCLK0 ADS HIT HITM and so forth and the second set is for the source synchronous signals which are relative to their respective strobe lines data and address as well as rising edge of BCLK0 Asynchronous signals are still present A20M IGNNE and so forth and can become active at any time during the clock cycle Table 2 6 identifies which signals are common clock source synchronous and asynchronous Table 2 6 FSB Signal Groups Sheet 1 of 2 Signal Group Type Signals1 AGTL Common Clock Input Synchronous to BPRI DEFER RESET RS 2 0 RSP BCLK 1 0 TRDY AGTL Common Clock Output Synchronous to BPM4 BPM 2 1 BCLK 1 0 AGTL Common Clock I O S
121. ng the Dual Core Intel amp Xeon Processor 5200 Series must not rely on software usage of this mechanism to limit the processor temperature If bit 4 of the 1A32 CLOCK MODULATION MSR is set to a 1 the processor will immediately reduce its power consumption via modulation starting and stopping of the internal core clock independent of the processor temperature When using On Demand mode the duty cycle of the clock modulation is programmable via 87 e n tel Thermal Specifications 6 2 3 6 2 4 6 2 5 88 bits 3 1 of the same IA32_ CLOCK MODULATION MSR In On Demand mode the duty cycle can be programmed from 12 5 on 87 5 off to 87 5 on 12 5 off in 12 5 increments On Demand mode may be used in conjunction with the Thermal Monitor however if the system tries to enable On Demand mode at the same time the TCC is engaged the factory configured duty cycle of the TCC will override the duty cycle selected by the On Demand mode PROCHOT Signal An external signal PROCHOT processor hot is asserted when the processor die temperature of any processor cores reaches its factory configured trip point If Thermal Monitor is enabled note that Thermal Monitor must be enabled for the processor to be operating within specification the TCC will be active when PROCHOT is asserted The processor can be configured to generate an interrupt upon the assertion or de assertion of PROCHOT Refer to the Intel 64 and IA 32 Architectur
122. ns 78 6 4 Dual Core Intel Xeon Processor X5200 Series Thermal A Profile Table 79 6 5 Dual Core Intel Xeon Processor X5200 Series Thermal B Profile Table 80 6 6 Dual Core Intel Xeon Processor L5200 Series Thermal Specifications 80 6 7 Dual Core Intel Xeon Processor L5200 Series Thermal Profile Table 81 6 8 Dual Core Intel Xeon Processor L5238 Thermal Specifications 82 6 9 Dual Core Intel Xeon Processor L5238 Thermal Profile Table 83 6 10 Dual Core Intel Xeon Processor L5215 Thermal Specifications 83 6 11 Dual Core Intel Xeon Processor L5215 Thermal Profile Table 84 6 12 GetTempO Error Codes i lsa cuna sa kai ka n Leka ki zin d wa nnne nean ann nean nn nnn nnne 91 7 1 Power On Configuration Option Landes 93 7 2 Extended HALT Maximum Power 94 8 1 PWM Fan Frequency Specifications for 4 Pin Active CEK Thermal Solution 110 8 2 Fan Specifications for 4 Pin Active CEK Thermal Solution 110 8 3 Fan Cable Connector Pin Out for 4 Pin Active CEK Thermal Solution 110 6 Dual Core Intel Xeon Processor 5200 Series Datasheet Revision History Revision Description Date 001 Initial release November 2007 002 Added product information for Dual Core
123. ntel Xeon Processor L5200 Series Vcc Static and Transient Tolerance Load Lines Vcc V 0 000 0 010 0 020 0 030 0 040 4 0 050 4 0 060 0 070 4 0 080 4 0 090 0 100 Icc A Vcc Maximum Vcc Typical Vcc Minimum 33 n tel Dual Core Intel Xeon Processor 5200 Series Electrical Specifications Notes 1 The Vcc min and Vcc max loadlines represent static and transient limits Please see Section 2 13 2 for VCC overshoot specifications 2 Refer to Table 2 12 for processor VID information 3 Refer to Table 2 13 for VccStatic and Transient Tolerance 4 The load lines specify voltage limits at the die measured at the VCC DIE SENSE and VSS DIE SENSE lands and the VCC DIE SENSE2 and VSS DIE SENSE2 lands Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC DIE SENSE and VSS DIE SENSE lands and VCC DIE SENSE2 and VSS DIE SENSE2 lands Refer to the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for socket load line guidelines and VR implementation Please refer to the appropriate platform design guide for details on VR implementation Table 2 14 AGTL Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes Vu Input Low Voltage 0 10 0 GTLREF 0 10 V 2 4 6 Vin Input High Voltage GTLREF
124. oard fan header and 4 pin connector used for the active CEK fan heat sink solution 101 Boxed Processor Specifications 5 30 1 133 5 muavag me asi RB DOE siet ak Q3MOTTY SLN3NOGHOD GYVOBYIHION ON 100433W YIONI4 Q8Y08 9N1848 X32 mmm 120051 NOI12 JU 1H913H 1N3NOdWOO QNYOBU3HLON XVW NNII ert Q 0380111V 1N3N32V1d IN3NOdMO QNYOGUJHION ON Q Y NO112181538 1H913H IN3NOdNOO XVM MM O L SL2 0O V3UV ATGWISSYSIO MNISIV3H AWO S3S0430d4 803 AYVONI NO112181S38 18913H 1N3NOdNO2 XVM MN 0 L SLZ 0 V38V WNISIV3H O N0112141538 1H913H LNINOJWOJ XVM NM 0 91170 ll 083931 x dd r TT ZZ W V E NN N EE TEBER dj x e T8 u SHIO YO 2 LHS 33 3N11100 MNISIV3H N0112131539 189138 SL2 0 3831381834 TIVE 130108 134005 803 9NINVNO NIIIN SHIQ 803 Z LHS 33S 3811100 XNISIV3H 3298383338 403 NMOHS QuvOB 1531 SWIG 3803 Z LHS 335 d 3N11100 A18W3SSYSIQ HIE gt q M0138I V IWLULEITIDE DD Ta 3ds Aug 135012510 38 10N AVW 0114183630 Am me IY1N02 9WIAYHO SIHI Figure 8 4 Top Side Board Keepout Zones Part 1 102 S9NI1N0ON Ni SS TTT HF TITTTTTTTITTITTIT TIT DIT P E a F S ch E E GON Il 992 L _ N NWN EL le Li Ural TU TERRE IT TI TIRS in im mi 0s2 EX tos e t 907 M
125. ocessor 5200 Series supports either 1333 MHz or 1600 MHz Front Side Bus operations The FSB utilizes a split transaction deferred reply protocol and Source Synchronous Transfer SST of address and data to improve performance The processor transfers data four times per bus clock 4X data transfer rate as in AGP 4X Along with the 4X data bus the address bus can deliver addresses two times per bus clock and is referred to as a double clocked or a 2X address bus In addition the Request Phase completes in one clock cycle The FSB is also used to deliver interrupts Signals on the FSB use Assisted Gunning Transceiver Logic AGTL level voltages Section 2 1 contains the electrical specifications of the FSB while implementation details are fully described in the appropriate platform design guidelines refer to Section 1 3 Terminology A symbol after a signal name refers to an active low signal indicating a signal is in the asserted state when driven to a low level For example when RESET is low a reset has been requested Conversely when NMI is high a nonmaskable interrupt has occurred In the case of signals where the name does not imply an active state but describes part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 HLHL refers to a hex A and D 3 0 LHLH also refers to a hex A H High logic level L Low logic level intel
126. of the processor socket Package I nsertion Specifications The Dual Core Intel Xeon Processor 5200 Series can be inserted and removed 15 times from an LGA771 socket which meets the criteria outlined in the LGA771 Socket Design Guidelines Processor Mass Specifications The typical mass of the Dual Core Intel Xeon Processor 5200 Series is 21 5 grams 0 76 oz This includes all components which make up the entire processor product Processor Materials The Dual Core Intel Xeon Processor 5200 Series is assembled from several components The basic material properties are described in Table 3 3 Processor Materials Component Material Integrated Heat Spreader IHS Nickel over copper Substrate Fiber reinforced resin Substrate Lands Gold over nickel Processor Markings Figure 3 5 shows the topside markings on the processor This diagram aids in the identification of the Dual Core Intel Xeon Processor 5200 Series Mechanical Specifications Figure 3 5 Processor Top side Markings Example GROUP1LINE1 GROUP1LINE2 GROUP1LINE3 GROUP1LINE4 GROUP1LINE5 x ATPO S N Legend GROUP1LINE1 GROUP1LINE2 GROUP1LINE3 GROUP1LINE4 GROUP1LINE5 Mark Text Production Mark 3400DP 6M 1600 Intel amp Xeon Proc SXXX COO i M 06 FPO Note 2D matrix is required for engineering samples only encoded with ATPO S N 3 9 Processor Land Coordinates Figure 3 6
127. olve both issues The boxed processor will include the following items Dual Core Intel Xeon Processor 5200 Series Unattached heat sink solution Four screws four springs and four heat sink standoffs all captive to the heat sink Foam air bypass pad and skirt included with 1U passive 3U active solution Thermal interface material pre applied on heat sink Installation and warranty manual ntel Inside Logo Other items listed in Figure 8 3 that are required to complete this solution will be shipped with either the chassis or boards They are as follows CEK Spring supplied by baseboard vendors Chassis standoffs supplied by chassis vendors 111 112 Boxed Processor Specifications Debug Tools Specifications n tel 9 9 1 Note 9 2 9 2 1 9 3 Debug Tools Specifications Please refer to the appropriate platform design guidelines for information regarding debug tool specifications Section 1 3 provides collateral details Debug Port System Requirements The Dual Core Intel Xeon Processor 5200 Series debug port is the command and control interface for the In Target Probe ITP debugger The ITP enables run time control of the processors for system debug The debug port which is connected to the FSB is a combination of the system J TAG and execution signals There are several mechanical electrical and functional constraints on the debug port that must be followed The mechanical constrain
128. on Processor X5200 Series is used to call out specifications that are unique to the Dual Core Intel Xeon Processor X5200 Series SKU Dual Core I ntel Xeon Processor E5200 Series A mainstream performance version of the Dual Core Intel amp Xeon Processor 5200 Series processor For this document Dual Core Intel Xeon Processor E5200 Series is used to call out specifications that are unique to the Dual Core Intel Xeon Processor E5200 Series SKU Dual Core I ntel Xeon Processor L5200 Series Intel 64 bit microprocessor intended for dual processor server blades and embedded servers The Dual Core Intel Xeon Processor L5200 Series is a lower voltage and lower power version of the Dual Core Intel Xeon Processor 5200 Series For this document Dual Core Intel Xeon Processor L5200 Series is used to call out specifications that are unique to the Dual Core Intel Xeon Processor L5200 Series SKU Dual Core Intel Xeon Processor L5238 Intel 64 bit microprocessor intended for dual processor server blades and embedded servers The Dual Core Intel Xeon Processor L5238 is a lower voltage and lower power version of the Dual Core Intel Xeon Processor L5200 Series supporting higher case temperatures It supports a Thermal Profile with nominal and short term conditions designed to meet Network Equipment Building System NEBS level 3 compliance For this document Dual Core Intel Xeon Processor L5238 is us
129. or X5200 Series Thermal Specifications Core Thermal Minimum Maximum Design Power T T Notes Frequency 1 W EO EO Launch to FMB 80 5 See Figure 6 2 Table 6 4 1 2 3 4 5 and Table 6 5 Notes 1 These values are specified at Vcc max for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds Vcc max at specified ICC Please refer to the loadline specifications in Section 2 13 i 2 Thermal Design Power TDP should be used for the processor thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at maximum Tease 3 These specifications are based on silicon characterization 4 Power specifications are defined at all VIDs found in Table 2 12 The Dual Core Intel Xeon Processor X5200 Series may be shipped under multiple VI Ds for each frequency 5 FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requi rements Thermal Specifications n tel Figure 6 2 Table 6 4 Dual Core Intel Xeon Processor X5200 Series Thermal Profiles A and B TCASE MAX is a thermal solution design point In actuality units will not significantly exceed TCASE_MAX_A due to TCC activation 70 5 Thermal Profile B 1U 55 Y 0 289 x 42 9 n Thermal Profile A 2
130. or for temperature data and the rate at which fan speed is changed Depending on the designer s specific requirements the DTS sample rate and alpha beta filter may have no effect on the fan control algorithm PECI Specifications PECI Device Address The PECI device address for socket 0 is 0x30 and socket 1 is 0x31 Please note that each address also supports two domains DomainO and Domain1 For more information on PECI domains please refer to the Platform Environment Control Interface PECI Specification PECI Command Support PECI command support is covered in detail in Platform Environment Control Interface Specification Please refer to this document for details on supported PECI command function and codes m Thermal Specifications n tel 6 3 2 3 6 3 2 4 PECI Fault Handling Requirements PECI is largely a fault tolerant interface including noise immunity and error checking improvements over other comparable industry standard interfaces The PECI client is as reliable as the device that it is embedded in and thus given operating conditions that fall under the specification the PECI will always respond to requests and the protocol itself can be relied upon to detect any transmission failures There are however certain scenarios where PECI is known to be unresponsive Prior to a power on RESET and during RESET assertion PECI is not guaranteed to provide reliable thermal data System designs should implement a defau
131. or output should be disabled 2 Shading denotes the expected VID range of the Dual Core Intel Xeon Processor 5200 Series 3 The VID range includes VID transitions that may be initiated by thermal events assertion of the FORCEPR signal see Section 6 2 4 Extended HALT state transitions see Section 7 2 2 or Enhanced Intel SpeedStep Technology transitions see Section 7 3 The Extended HALT state must be enabled for the processor to remain within its specifications 4 Once the VRM EVRD is operating after power up if either the Output Enable signal is de asserted or a specific VI D off code is received the VRM EVRD must turn off its output the output should go to high impedance within 500 ms and latch off until power is cycled Refer to Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines 20 Dual Core Intel Xeon Processor 5200 Series Electrical Specifications Table 2 4 Table 2 5 2 6 Loadline Selection Truth Table for LL 1D 1 0 LL ID1 LL IDO Description 0 0 Reserved 0 1 Dual Core Intel Xeon Processor 5100 series Dual Core Intel Xeon Processor 5200 Series and Quad Core Intel Xeon Processor 5400 Series 1 0 Reserved I 1 Quad Core Intel Xeon processor 5300 series Note The LL_ID 1 0 signals are used to select the correct loadline slope for the processor Market Segment Selection Truth Table for MS ID 1 0
132. power state than the HALT state or Stop Grant state The Extended HALT state must be enabled via the BI OS for the processor to remain within its specifications For processors that are already running at the lowest bus to core frequency ratio for its nominal operating point the processor will transition to the HALT state instead of the Extended HALT state The Stop Grant state requires chipset and BIOS support on multiprocessor systems In a multiprocessor system all the STPCLK signals are bussed together thus all processors are affected in unison When the STPCLK signal is asserted the processor enters the Stop Grant state issuing a Stop Grant Special Bus Cycle SBC for each processor die The chipset needs to account for a variable number of processors asserting the Stop Grant SBC on the bus before allowing the processor to be transitioned into one of the lower processor power states 93 intel 7 2 2 1 7 2 2 2 Table 7 2 94 Normal State This is the normal operating state for the processor HALT or Extended HALT State The Extended HALT state CIE is enabled via the BIOS The Extended HALT state must be enabled for the processor to remain within its specifications The Extended HALT state requires support for dynamic VID transitions in the platform HALT State HALT is a low power state entered when the processor have executed the HALT or MWAIT instruction When one of the processor cores execute the HALT or
133. r Other AE12 VCC Power Other AF21 VCC Power Other AE13 VSS Power Other AF22 VCC Power Other AE14 VCC Power Other AF23 VSS Power Other AE15 VCC Power Other AF24 VSS Power Other AE16 VSS Power Other AF25 VSS Power Other AE17 VSS Power Other AF26 VSS Power Other AE18 VCC Power Other AF27 VSS Power Other AE19 VCC Power Other AF28 VSS Power Other AE2 VSS Power Other AF29 VSS Power Other AE20 VSS Power Other AF3 VSS Power Other AE21 VCC Power Other AF30 VSS Power Other AE22 VCC Power Other AF4 A28 Source Sync Input Output AE23 VCC Power Other AF5 A27 Source Sync Input Output AE24 VSS Power Other AF6 VSS Power Other AE25 VSS Power Other AF7 VSS Power Other AE26 VSS Power Other AF8 VCC Power Other AE27 vss Power Other AF9 VCC Power Other AE28 VSS Power Other AG1 TRST TAP Input AE29 VSS Power Other AG10 VSS Power Other AE3 TESTHI 12 Power Other Input AG11 VCC Power Other AE30 VSS Power Other AG12 VCC Power Other AE4 RESERVED AG13 VSS Power Other AE5 VSS Power Other AG14 VCC Power Other AE6 RESERVED AG15 VCC Power Other AE7 vss Power Other AG16 VSS Power Other AE8 SKTOCC Power Other Output AG17 VSS Power Other 58 intel Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 5 of 20 Sheet 6 of 20 Pin No Pin Name EC aa Direction Pin No Pi
134. r Other Output Y3 RESERVED V23 vss Power Other Y30 VCC Power Other V24 VSS Power Other Y4 A20 Source Sync Input Output V25 VSS Power Other Y5 vss Power Other V26 VSS Power Other Y6 A19 Source Sync Input Output V27 vss Power Other Y7 vss Power Other V28 VSS Power Other Y8 VCC Power Other V29 vss Power Other v3 VSS Power Other V30 vss Power Other v4 A15 Source Sync Input Output V5 Al4 Source Sync Input Output V6 vss Power Other V7 VSS Power Other V8 VCC Power Other W1 MS IDO Power Other Output w2 RESERVED w23 VCC Power Other w24 VCC Power Other W25 VCC Power Other W26 VCC Power Other W27 VCC Power Other w28 VCC Power Other W29 VCC Power Other w3 RESERVED w30 VCC Power Other w4 vss Power Other w5 A16 Source Sync Input Output W6 A18 Source Sync Input Output w7 vss Power Other w8 VCC Power Other Y1 RESERVED 66 Signal Definitions 5 5 1 Table 5 1 Signal Definitions Signal Definitions Signal Definitions Sheet 1 of 8 Name Type Description Notes A 37 3 1 0 A 37 3 Address define a 238 byte physical memory address space In sub phase 1 of the address phase these signals transmit the address of a transaction In sub phase 2 these signals transmit transaction type information These signals must connect the appropriate pins of all agents on the FSB A 37 3 are protected by parity signals AP 1 0 A 37 3 are source synchronous signal
135. r details on Intel 64 Architecture and its programming model can be found in the Intel 64 and A 32 Architectures Software Developer s Manual at http www intel com products processor manuals In addition the Dual Core Intel Xeon Processor 5200 Series supports the Execute Disable Bit functionality When used in conjunction with a supporting operating system Execute Disable allows memory to be marked as executable or non executable This feature can prevent some classes of viruses that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system Further details on Execute Disable can be found at http www intel com cd ids developer asmo na eng 149308 htm The Dual Core Intel Xeon Processor 5200 Series support Intel Virtualization Technology for hardware assisted virtualization within the processor Intel Virtualization Technology is a set of hardware enhancements that can improve virtualization solutions Intel Virtualization Technology is used in conjunction with Virtual Machine intel Table 1 1 1 1 10 Monitor software enabling multiple independent software environments inside a single platform Further details on Intel Virtualization Technology can be found at http developer intel com technology platform technology virtualization index htm The Dual Core Intel Xeon Processor 5200 Series is intended for high performance server and workstation systems The Dual Core Int
136. r for subsequent operation These configuration options cannot be changed except by another reset All external resets reconfigure the processor for configuration purposes the processor does not distinguish between a warm reset PWRGOOD signal remains asserted and a power on reset Power On Configuration Option Lands Configuration Option Land Name Notes Output tri state SMI 1 2 Execute BIST Built In Self Test A3 1 2 Disable MCERR observation A9 1 2 Disable BINI T observation A10 1 2 Symmetric agent arbitration ID BR 1 0 1 2 Notes 1 Asserting this signal during RESET will select the corresponding option 2 Address lands not identified in this table as configuration options should not be asserted during RESET Disabling of any of the cores within the Dual Core Intel Xeon Processor 5200 Series must be handled by configuring the EXT_CONFIG Model Specific Register MSR This MSR will allow for the disabling of a single core per die within the package Clock Control and Low Power States The Dual Core Intel Xeon Processor 5200 Series supports the Extended HALT state also referred to as C1E in addition to the HALT state and Stop Grant state to reduce power consumption by stopping the clock to internal sections of the processor depending on each particular state See Figure 7 1 for a visual representation of the processor low power states The Extended HALT state is a lower
137. rd Min Max Unit Notes Thickness 1 57 mm 80 311 N 0 062 18 70 Ibf Static Compressive 2 16 mm 111 311 N 12 39 Load 0 085 25 70 Ibf sn 2 54 mm 133 311 N 0 100 30 70 Ibf 311 N max static compressive load 222 N dynamic N Dynamic loading NA NA 1 3 4 5 6 Compressive Load 70 Ibf max static compressive load lbf 50 Ibf dynamic loading 1 57 mm Transient Bend Limits 2 NA 750 me 1 3 7 8 0 062 Notes 1 These specifications apply to uniform compressive loading in a direction perpendicular to the IHS top surface 2 This is the minimum and maximum static force that can be applied by the heatsink and retention solution to maintain the heatsink and processor interface 3 These specifications are based on limited testing for design characterization Loading limits are for the LGA771 socket 4 Dynamic compressive load applies to all board thickness 5 Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement 6 Test condition used a heatsink mass of 1 Ibm with 50 g acceleration measured at heatsink mass The dynamic portion of this specification in the product application can have flexibility in specific values but the ultimate product of mass times acceleration should not exceed this dynamic load 7 Transient bend is defined as the transient board deflection during manufacturing such as board assembly and system integration It is a relatively slow bending event compared to shock and
138. ropriate pins of all processor FSB agents DP 3 0 1 0 DP 3 0 Data Parity provide parity protection for the D 63 0 signals They are driven by the agent responsible for driving D 63 0 and must connect the appropriate pins of all processor FSB agents 69 intel Table 5 1 70 Signal Definitions Signal Definitions Sheet 4 of 8 Name DRDY Type 1 0 Description DRDY Data Ready is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi common clock data transfer DRDY may be deasserted to insert idle clocks This signal must connect the appropriate pins of all processor FSB agents Notes DSTBN 3 0 DSTBP 3 0 1 0 1 0 Data strobe used to latch in D 63 0 Signals Associated Strobes D 15 0 DBIO DSTBNO D 31 16 DBI1 D 47 32 DBI2 D 63 48 DBI3 DSTBN1 DSTBN2 DSTBN3 Data strobe used to latch in D 63 0 Signals Associated Strobes D 15 0 DBIO DSTBPO D 31 16 DBI1 DSTBP1 D 47 32 DBI2 DSTBP2 D 63 48 DBI3 DSTBP3 FERR PBE FERR PBE floating point error pending break event is a multiplexed signal and its meaning is qualified by STPCLK When STPCLK is not asserted FERR PBE indicates a floating point error and will be asserted when the processor detects an unmasked floating point e
139. rror When STPCLK is not asserted FERR PBE is similar to the ERROR signal on the Intel387 coprocessor and is included for compatibility with systems using MS DOS type floating point error reporting When STPCLK is asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The assertion of FERR PBE indicates that the processor should be returned to the Normal state For additional information on the pending break event functionality including the identification of support of the feature and enable disable information refer to Vol 3 of the Intel 64 and 1A 32 Architectures Software Developer s Manual and the Intel Processor Identification and the CPUID Instruction application note FORCEPR The FORCEPR force power reduction input can be used by the platform to cause the Dual Core Intel Xeon Processor 5200 Series to activate the Thermal Control Circuit TCC GTLREF_ADD GTLREF_ADD determines the signal reference level for AGTL address and common clock input lands GTLREF_ADD is used by the AGTL receivers to determine if a signal is a logical 0 or a logical 1 Please refer to Table 2 18 and the appropriate platform design guidelines for additional details GTLREF_DATA GTLREF_DATA determines the signal reference level for AGTL data input lands GTLREF_DATA is used by the AGTL receivers to determine if a signal is a logical 0 or a logical 1 Please refer to Ta
140. rshoot or undershoot on any signal will likely result in permanent damage to the processor 3 Storage temperature is applicable to storage conditions only In this scenario the processor must not receive a clock and no lands can be connected to a voltage bias Storage within these limits will not affect the long term reliability of the device For functional operation please refer to the processor case temperature specifications 4 This rating applies to the processor and does not include any tray or packaging 5 Failure to adhere to this specification can affect the long term reliability of the processor Processor DC Specifications The processor DC specifications in this section are defined at the processor die pads unless noted otherwise See Chapter 4 for the Dual Core Intel Xeon Processor 5200 Series land listings and Chapter 5 for signal definitions Voltage and current specifications are detailed in Table 2 12 For platform planning refer to Table 2 13 which provides Vcc static and transient tolerances This same information is presented graphically in Figure 2 5 and Figure 2 6 The FSB clock signal group is detailed in Table 2 19 BSEL 2 0 and VID 6 1 signals are specified in Table 2 14 The DC specifications for the AGTL signals are listed in Table 2 15 Legacy signals and Test Access Port TAP signals follow DC specifications similar to GTL The DC specifications for the PWRGOOD input and TAP signal group are listed in T
141. s 2 The tolerances for this specification have been stated generically to enable system designer to calculate the minimum values across the range of Vy 3 GTLREF DATA and GTLREF ADD is generated from V on the baseboard by a voltage divider of 1 resistors The minimum and maximum specifications account for this resistor tolerance Refer to the appropriate platform design guidelines for implementation details The Vr referred to in these specifications is the instantaneous V 4 Rrristhe on die termination resistance measured at Vo of the AGTL output driver Measured at 0 31 Vr R is connected to V on die Refer to processor I O Buffer Models for I V characteristics 5 This specified range is also applicable for the DP 3 0 and DRDY Common Clock signals Refer to Table 2 6 and Table 2 7 for AGTL signal grouping and details on signals that include on die termination 6 The DP 3 0 and DRDY Common Clock signals are not included in this range Refer to Table 2 6 and Table 2 7 for AGTL signal grouping and details on signals that include on die termination FSB Differential BCLK Specifications Sheet 1 of 2 Symbol Parameter Min Typ Max Unit Figure Notes VL Input Low Voltage 0 150 0 0 0 150 V 2 10 Vu Input High Voltage 0 660 0 710 0 850 V 2 10 VcRoss abs Absolute Crossing Point 0 250 0 350 0 550 V 2 2 9 VcRossirel Relative Crossing Point 0 250 N A 0 550 V 2 10 3 8 9 11 0 5 0 5 2 11 Viav E VHav iq
142. s Termination resistors Rrr for AGTL signals are provided on the processor silicon and are terminated to Vy The on die termination resistors are always enabled on the Dual Core Intel Xeon Processor 5200 Series to control reflections on the transmission line Intel chipsets also provide on die termination thus eliminating the need to terminate the bus on the baseboard for most AGTL signals Some FSB signals do not include on die termination Rrr and must be terminated on the baseboard See Table 2 8 for details regarding these signals The AGTL bus depends on incident wave switching Therefore timing calculations for AGTL signals are based on flight time as opposed to capacitive deratings Analog signal simulation of the FSB including trace lengths is highly recommended when designing a system Contact your Intel Field Representative to obtain the Dual Core Intel Xeon Processor 5200 Series signal integrity models which includes buffer and package models Power and Ground Lands For clean on chip processor core power distribution the processor has 223 Vcc power and 273 Vss ground inputs All Vcc lands must be connected to the processor power plane while all Vss lands must be connected to the system ground plane The processor Vcc lands must be supplied with the voltage determined by the processor Voltage IDentification VID signals See Table 2 3 for VID definitions 15 m n tel Dual Core Intel Xeon Processor 5
143. s Thermal Mechanical Design Guidelines TMDG The Dual Core Intel Xeon Processor 5200 Series implements a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control and to assure processor reliability Selection of the appropriate fan speed is based on the relative temperature data reported by the processor s Platform Environment Control Interface PECI bus as described in Section 6 3 If the value reported via PECI is less than Tconrno then the case temperature is permitted to exceed the Thermal Profile If the value reported via PECI is greater than or equal to TconTtroL then the processor case temperature must remain at or below the temperature as specified by the thermal profile The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit TCC activation as indicated by PROCHOT see Section 6 2 Processor Thermal Features Systems that implement fan speed control must be designed to use this data Systems that do not alter the fan speed only need to guarantee the case temperature meets the thermal profile specifications 75 e n tel Thermal Specifications The Dual Core Intel Xeon Processor E5200 Series and Dual Core Intel amp Xeon Processor L5200 Series supports a single Thermal Profile see Figure 6 1 Table 6 1Table 6 6 With this Thermal Profile it is expected that the Thermal Control
144. s a listing of all processor lands ordered by land number 4 1 Pin Assignments 4 1 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 1 of 20 Pin Name Ag id Direction A03 M5 Source Sync Input Output A04 P6 Source Sync Input Output A05 L5 Source Sync Input Output A06 L4 Source Sync Input Output A07 M4 Source Sync Input Output A08 R4 Source Sync Input Output A09 T5 Source Sync Input Output A10 U6 Source Sync Input Output A11 T4 Source Sync Input Output A12 U5 Source Sync Input Output A13 U4 Source Sync Input Output A14 V5 Source Sync Input Output A15 VA Source Sync Input Output A16 w5 Source Sync Input Output A17 AB6 Source Sync Input Output A18 W Source Sync Input Output A19 Y6 Source Sync Input Output A20 Y4 Source Sync Input Output A20M K3 CMOS ASync Input A21 AA4 Source Sync Input Output A22 AD6 Source Sync Input Output A23 AA5 Source Sync Input Output A24 AB5 Source Sync Input Output A25 AC5 Source Sync Input Output A26 AB4 Source Sync Input Output A27 AF5 Source Sync Input Output A28 AF4 Source Sync Input Output A29 AG6 Source Sync Input Output A30 AG4 Source Sync Input Output Table 4 1 Land Listing by Land Name Sheet 2 of 20 Pin Name ED iar aw Direction A3
145. s and are latched into the receiving buffers by ADSTB 1 0 On the active to inactive transition of RESET the processors sample a subset of the A 37 3 lands to determine their power on configuration See Section 7 1 A20M If A20M Address 20 Mask is asserted the processor masks physical address bit 20 A20 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 MB boundary Assertion of A20M is only supported in real mode A20M is an asynchronous signal However to ensure recognition of this signal following an I O write instruction it must be valid along with the TRDY assertion of the corresponding I O write bus transaction ADS 1 0 ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 37 3 lands All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction This signal must be connected to the appropriate pins on all Dual Core Intel Xeon Processor 5200 Series FSB agents ADSTB 1 0 1 0 Address strobes are used to latch A 37 3 and REQ 4 0 on their rising and falling edge Strobes are associated with signals as shown below Signals Associated Strobes REQ 4 0 A 16 3 ADSTBO A 37 36
146. s B14 Power Other Iss ja Poweyoher vss B17 Power Other 54 intel Land Listing Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 17 of 20 Sheet 18 of 20 Pin Name Ne ar aka Direction Pin Name ie d Direction VSS B20 Power Other vss G1 Power Other vss B24 Power Other vss H10 Power Other vss B5 Power Other vss H11 Power Other vss B8 Power Other vss H12 Power Other vss C10 Power Other vss H13 Power Other vss C13 Power Other vss H14 Power Other vss C16 Power Other vss H17 Power Other vss C19 Power Other vss H18 Power Other vss C22 Power Other vss H19 Power Other vss C24 Power Other vss H20 Power Other vss CA Power Other vss H21 Power Other vss C7 Power Other vss H22 Power Other vss D12 Power Other vss H23 Power Other vss D15 Power Other vss H24 Power Other vss D18 Power Other vss H25 Power Other vss D21 Power Other vss H26 Power Other vss D24 Power Other vss H27 Power Other vss D3 Power Other vss H28 Power Other vss D5 Power Other vss H29 Power Other vss D6 Power Other vss H3 Power Other vss D9 Power Other vss H6 Power Other vss E11 Power Other vss H7 Power Other vss E14 Power Other VSS H8 Power Other VSS E17 Power Other VSS H9 Power Other VSS E2 Power Other VSS J4 Power Other VSS E20 Power Other VSS J7 Power Other vss E25 Power Other vss K2 Power Other vss
147. s found in Table 2 3 The Dual Core Intel Xeon Processor E5200 Series may be shipped under multiple VI Ds for each frequency 5 FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements Dual Core I ntel Xeon Processor E5200 Series Thermal Profile 70 65 4 60 4 55 4 Tcase C Thermal Profile Y 0 354 x 43 45 40 T T r r r 0 10 20 30 40 50 60 Power W Notes 1 Please refer to Table 6 2 for discrete points that constitute the thermal profile 2 Implementation of the Dual Core Intel Xeon Processor E5200 Series Thermal Profile should result in virtually no TCC activation Furthermore utilization of thermal solutions that do not meet the processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss 3 Refer to the Dual Core Intel Xeon Processor 5200 Series Thermal Mechanical Design Guidelines TMDG for system and environmental implementation details 77 intel Table 6 2 Table 6 3 78 Thermal Specifications Dual Core I ntel Xeon Processor E5200 Series Thermal Profile Table Power W TcasE MAX C 0 43 0 5 44 8 10 46 5 15 48 3 20 50 1 25 51 9 30 53 6 35 55 4 40 57 2 45 58 9 50 60 7 55 62 5 60 64 2 65 66 0 Dual Core I ntel Xeon Process
148. se 0 741 P 45 Short Term 30 0 5 10 15 20 25 30 35 Power W Notes 1 Dual Core Intel Xeon Processor L5238 Thermal Profile is representative of a volumetrically constrained platform Please refer to Table 6 9 for discrete points that constitute the thermal profile 2 Implementation of the Dual Core Intel Xeon Processor L5238 Thermal Profile should result in virtually no TCC activation Furthermore utilization of thermal solutions that do not meet the processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss See Section 6 2 for details on TCC activation 3 The Nominal Thermal Profile must be used for all normal operating conditions or for products that do not require NEBS Level 3 compliance 4 The Short Term Thermal Profile may only be used for short term excursions to higher ambient operating temperatures not to exceed 96 hours per instance 360 hours per year and a maximum of 15 instances per year as compliant with NEBS Level 3 5 Utilization of a thermal solution that exceeds the Short Term Thermal Profile or which operates at the Short Term Thermal Profile for a duration longer than the limits specified in Note 4 above do not meet the processor thermal specifications and may result in permanent damage to the processor 6 Refer to the Dual Core Intel Xeon Processor 5200 Series in Embedded Thermal Mechanical Design Guidelines TMDG for system and
149. sed Platforms 6 3 1 2 6 3 2 6 3 2 1 6 3 2 2 90 TcowrRoL TCC Activation Setting Temperature Fan Speed RPM Temperature not intended to depict actual implementation Processor Thermal Data Sample Rate and Filtering The Digital Thermal Sensor DTS provides an improved capability to monitor device hot spots which inherently leads to more varying temperature readings over short time intervals The DTS sample interval range can be modified and a data filtering algorithm can be activated to help moderate this The DTS sample interval range is 82us default to 20 ms max This value can be set in BIOS To reduce the sample rate requirements on PECI and improve thermal data stability vs time the processor DTS also implements an averaging algorithm that filters the incoming data This is an alpha beta filter with coefficients of 0 5 and is expressed mathematically as Current filtered temp Previous filtered temp 2 new sensor temp 2 This filtering algorithm is fixed and cannot be changed It is on by default and can be turned off in BIOS Host controllers should utilize the min max sample times to determine the appropriate sample rate based on the controller s fan control algorithm and targeted response rate The key items to take into account when settling on a fan control algorithm are the DTS sample rate whether the temperature filter is enabled how often the PECI host will poll the process
150. servation is enabled during power on configuration see Section 7 1 and BINIT is sampled asserted symmetric agents reset their bus LOCK activity and bus request arbitration state machines The bus agents do not reset their 1 O Queue OO and transaction tracking state machines upon observation of BINIT assertion Once the BINIT assertion has been observed the bus agents will re arbitrate for the FSB and attempt completion of their bus queue and IOQ entries If BINIT observation is disabled during power on configuration a priority agent may handle an assertion of BINIT as appropriate to the error handling architecture of the system BNR IO BNR Block Next Request is used to assert a bus stall by any bus 3 agent who is unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions Since multiple agents might need to request a bus stall at the same time BNR is a wired OR signal which must connect the appropriate pins of all processor FSB agents In order to avoid wired OR glitches associated with simultaneous edge transitions driven by multiple drivers BNR is activated on specific clock edges and sampled on specific clock edges BPM5 1 0 BPM 5 0 Breakpoint Monitor are breakpoint and performance 2 BPM4 O monitor signals They are outputs from the processor which indicate BPM3 1 0 the status of breakpoints and programmable counters used for monitoring processor perfor
151. ssor FSB agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the processor FSB it will wait until it observes LOCK deasserted This enables symmetric agents to retain ownership of the processor FSB throughout the bus locked operation and ensure the atomicity of lock MCERR 1 0 MCERR Machine Check Error is asserted to indicate an unrecoverable error without a bus protocol violation It may be driven by all processor FSB agents MCERR assertion conditions are configurable at a system level Assertion options are defined by the following options Enabled or disabled e Asserted if configured for internal errors along with IERR Asserted if configured by the request initiator of a bus transaction after it observes an error Asserted by any bus agent when it observes an error in a bus transaction For more details regarding machine check architecture refer to the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3 71 Bi intel Se Table 5 1 Signal Definitions Sheet 6 of 8 Name Type Description Notes MS_ID 1 0 O These signals are provided to indicate the Market Segment for the processor and may be used for future processor compatibility or for keying These signals are not connected to the processor die
152. t Output DO5 B6 Source Sync Input Output D45 E22 Source Sync Input Output D063 B7 Source Sync Input Output D46 D22 Source Sync Input Output DO7 A7 Source Sync Input Output D47 G22 Source Sync Input Output DO8 A10 Source Sync Input Output D48 D20 Source Sync Input Output DO9 All Source Sync Input Output D49 D17 Source Sync Input Output D10 B10 Source Sync Input Output D50 Al4 Source Sync Input Output D11 C11 Source Sync Input Output D51 C15 Source Sync Input Output D12 D8 Source Sync Input Output D52 C14 Source Sync Input Output D13 B12 Source Sync Input Output D53 B15 Source Sync Input Output D14 C12 Source Sync Input Output D543 C18 Source Sync Input Output D15 D11 Source Sync Input Output D55 B16 Source Sync Input Output D16 G9 Source Sync Input Output D56 A17 Source Sync Input Output D17 F8 Source Sync Input Output D57 B18 Source Sync Input Output D18 F9 Source Sync Input Output D58 C21 Source Sync Input Output D19 E9 Source Sync Input Output D59 B21 Source Sync Input Output D20 D7 Source Sync Input Output D60 B19 Source Sync Input Output D21 E10 Source Sync Input Output D61 A19 Source Sync Input Output D22 D10 Source Sync Input Output D62 A22 Source Sync Input Output D23 F11 Source Sync Input Output D63 B22 Source Sync Input Output D24 F12 Source Sync Input Output DBI0 A8 Source Sync Input Output D25 D13 Source Sync Input Output DBI1 G11 Source Sync Input Output D26 E13 Source Sync Input Output DBI2 D19 So
153. t requires the debug port connector to be installed in the system with adequate physical clearance Electrical constraints exist due to the mixed high and low speed signals of the debug port for the processor While the J TAG signals operate at a maximum of 75 MHz the execution signals operate at the common clock FSB frequency The functional constraint requires the debug port to use the J TAG system via a handshake and multiplexing scheme In general the information in this chapter may be used as a basis for including all run control tools in Dual Core Intel Xeon Processor 5200 Series based system designs including tools from vendors other than Intel The debug port and JTAG signal chain must be designed into the processor board to utilize the XDP for debug purposes except for interposer solutions Target System I mplementation System Implementation Specific connectivity and layout guidelines for the Debug Port are provided in the appropriate platform design guidelines Logic Analyzer Interface LAI Intel is working with two logic analyzer vendors to provide logic analyzer interfaces LAIs for use in debugging Dual Core Intel Xeon Processor 5200 Series systems Tektronix and Agilent should be contacted to obtain specific information about their logic analyzer interfaces The following information is general in nature Specific information must be obtained from the logic analyzer vendor Due to the complexity of Dual Core Intel
154. t within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of time then when returned to conditions within the functional operating condition limits it will either not function or its reliability will be severely degraded Although the processor contains protective circuitry to resist damage from static electric discharge precautions should always be taken to avoid high static voltages or electric fields Dual Core Intel Xeon Processor 5200 Series Electrical Specifications n tel Table 2 11 Processor Absolute Maximum Ratings 2 13 2 13 1 Symbol Parameter Min Max Unit Notes 2 Vcc Core voltage with respect to Vss 0 30 1 35 V Vr FSB termination voltage with respect to Vss 0 30 1 45 V TcASE Processor case temperature See See C Chapter 6 Chapter 6 TsTORAGE Storage temperature 40 85 SE 3 4 5 Notes 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 2 Overshoot and undershoot voltage guidelines for input output and I O signals are outlined in Chapter 3 Excessive ove
155. taken from processor VCC DIE SENSE and VSS DIE SENSE lands and VCC DIE SENSE2 and VSS DIE SENSE2 lands Refer to the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for socket load line guidelines and VR implementation Please refer to the appropriate platform design guide for details on VR implementation I cc values greater than 75A are not applicable for the Dual Core Intel Xeon Processor E5200 Series lcc values greater than 50A are not applicable for the Dual Core Intel Xeon Processor L5200 Series lI cc values greater than 42A are not applicable for the Dual Core Intel Xeon Processor L5238 Dual Core Intel Xeon Processor E5200 Series Vcc Static and Transient Tolerance Load Lines Vcc V VID 0 000 VID 0 020 4 VID 0 040 4 VID 0 060 VID 0 080 VID 0 100 4 VID 0 120 4 VID 0 140 Icc A 35 40 45 50 55 60 65 70 75 Vcc Typical Voc Minimum Voc Maximum 32 Dual Core Intel Xeon Processor 5200 Series Electrical Specifications Figure 2 6 Dual Core Intel Xeon Processor X5200 Series Vcc Static and Transient Tolerance Load Lines Figure 2 7 Vcc V VID 0 000 VID 0 020 VID 0 040 VID 0 060 VID 0 080 VID 0 100 VID 0 120 VID 0 140 J VID 0 160 10 15 lcc A 2 5 30 35 4 6 5 5 6 6 7075 A 8 9 Minimum Dual Core I
156. te pins of 3 all processor FSB agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to ADSTB 1 0 Refer to the AP 1 0 signal description for details on parity checking of these signals RESET l Asserting the RESET signal resets all processors to known states 3 and invalidates their internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least 1 ms after VCC and BCLK have reached their proper specifications On observing active RESET all FSB agents will deassert their outputs within two clocks RESET must not be kept asserted for more than 10 ms while PWRGOOD is asserted A number of bus signals are sampled at the active to inactive transition of RESET for power on configuration These configuration options are described in the Section 7 1 This signal does not have on die termination and must be terminated on the system board RS 2 0 l RS 2 0 Response Status are driven by the response agent the 3 agent responsible for completion of the current transaction and must connect the appropriate pins of all processor FSB agents RSP l RSP Response Parity is driven by the response agent the agent 3 responsible for completion of the current transaction during assertion of RS 2 0 the signals for which RSP provides parity protection It must connect to the appropriate pins of al
157. ted P states Enhanced Intel SpeedStep Technology enables real time dynamic switching between frequency and voltage points It alters the performance of the processor by changing the bus to core frequency ratio and voltage This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system The Dual Core Intel amp Xeon Processor 5200 Series has hardware logic that coordinates the requested voltage VID between the processor cores The highest voltage that is requested for either of the processor cores is selected for that processor package Note that the front side bus is not altered only the internal core frequency is changed In order to run at reduced power consumption the voltage is altered in step with the bus ratio The following are key features of Enhanced Intel SpeedStep Technology Multiple voltage frequency operating points provide optimal performance at reduced power consumption Voltage frequency selection is software controlled by writing to processor MSR s Model Specific Registers thus eliminating chipset dependency If the target frequency is higher than the current frequency Vcc is incremented in steps 12 5 mV by placing a new value on the VID signals and the processor shifts to the new frequency Note that the top frequency for the processor can not be exceeded f the target frequency is lower than the current freq
158. tel Boxed Processor Specifications The fan power header on the baseboard must be positioned to allow the fan heat sink power cable to reach it The fan power header identification and location must be documented in the suppliers platform documentation or on the baseboard itself The baseboard fan power header should be positioned within 177 8 mm 7 in from the center of the processor socket PWM Fan Frequency Specifications for 4 Pin Active CEK Thermal Solution Description Min Frequency Nominal Frequency Max Frequency Unit PWM Control Frequency Range 21 000 25 000 28 000 Hz Fan Specifications for 4 Pin Active CEK Thermal Solution SEN Typ Max Max Description Min Steady Steady Startup Unit 12 V 12 volt fan power supply 10 8 12 12 13 2 V IC Fan Current Draw N A 1 1 25 1 5 A SENSE SENSE frequency 2 2 2 2 puses per an Fan Cable Connector Pin Out for 4 Pin Active CEK Thermal Solution PIN 3 PIN4 PIN 2 e Fan Cable Connector Pin Out for 4 Pin Active CEK Thermal Solution Pin Number Signal Color 1 Ground Black 2 Power 12 V Yellow 3 Sense 2 pulses per revolution Green 4 Control 21 KHz 28 KHz Blue Boxed Processor Cooling Requirements As previously stated the boxed processor will be available in two product configurations Each configuration will require unique design considerations Meeting the processor s temperature specifications is
159. uency the processor shifts to the new frequency and Vcc is then decremented in steps 12 5 mV by changing the target VID through the VID signals 97 Features Boxed Processor Specifications n tel 8 8 1 Boxed Processor Specifications Introduction Intel boxed processors are intended for system integrators who build systems from components available through distribution channels The Dual Core Intel Xeon Processor 5200 Series will be offered as an Intel boxed processor Intel will offer the Dual Core Intel Xeon Processor 5200 Series with two heat sink configurations available for each processor frequency 1U passive 3U active combination solution and a 2U passive only solution The 1U passive 3U active combination solution is based on a 1U passive heat sink with a removable fan that will be pre attached at shipping This heat sink solution is intended to be used as either a 1U passive heat sink or a 3U active heat sink Although the active combination solution with removable fan mechanically fits into a 2U keepout its use is not recommended in that configuration Dual Core Intel Xeon Processor X5200 Series will include a copper 1U passive 3U active combination solution or a copper 2U passive heatsink The Dual Core Intel Xeon Processor E5200 Series and Dual Core Intel Xeon Processor L5200 Series with 65W and lower TDPs will include an aluminum extruded 1U passive 3U active combination solution or an
160. ulator EVRD or VRM pins to the LGA771 socket Bulk decoupling must be provided on the baseboard to handle large voltage swings The power delivery solution must insure the voltage and current specifications are met as defined in Table 2 12 For further information regarding power delivery decoupling and layout guidelines refer to the appropriate platform design guidelines V Decoupling Bulk decoupling must be provided on the baseboard Decoupling solutions must be sized to meet the expected load To insure optimal performance various factors associated with the power delivery solution must be considered including regulator type power plane and trace sizing and component placement A conservative decoupling solution consists of a combination of low ESR bulk capacitors and high frequency ceramic capacitors For further information regarding power delivery decoupling and layout guidelines refer to the appropriate platform design guidelines Front Side Bus AGTL Decoupling The Dual Core Intel Xeon Processor 5200 Series integrates signal termination on the die as well as a portion of the required high frequency decoupling capacitance on the processor package However additional high frequency capacitance must be added to the baseboard to properly decouple the return currents from the FSB Bulk decoupling must also be provided by the baseboard for proper AGTL bus operation Decoupling guidelines are described in the appropriate platform
161. urce Sync Input Output A6 vss Power Other A7 D07 Source Sync Input Output A8 DBI0 Source Sync Input Output A9 vss Power Other AA1 VTT_OUT Power Other Output AA2 LL ID1 Power Other Output AA23 vss Power Other AA24 vss Power Other AA25 vss Power Other AA26 vss Power Other AA27 vss Power Other AA28 vss Power Other AA29 vss Power Other AA3 vss Power Other AA30 vss Power Other AA4 A21 Source Sync Input Output AA5 A23 Source Sync Input Output AA6 vss Power Other 57 intel Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 3 of 20 Sheet 4 of 20 Pin No Pin Name ui uad Direction Pin No Pin Name e s Direction AD26 vcc Power Other AE9 VCC Power Other AD27 VCC Power Other AF1 TDO TAP Output AD28 VCC Power Other AF10 VSS Power Other AD29 VCC Power Other AF11 VCC Power Other AD3 BINI T Common Clk Input Output AF12 VCC Power Other AD30 VCC Power Other AF13 vss Power Other AD4 VSS Power Other AF14 VCC Power Other AD5 ADSTB1 Source Sync Input Output AF15 VCC Power Other AD6 A22 Source Sync Input Output AF16 VSS Power Other AD7 VSS Power Other AF17 VSS Power Other AD8 VCC Power Other AF18 VCC Power Other AE1 TCK TAP Input AF19 VCC Power Other AE10 VSS Power Other AF2 BPM4 Common Clk Output AE11 VCC Power Other AF20 VSS Powe
162. urce Sync Input Output D27 G13 Source Sync Input Output DBI3 C20 Source Sync Input Output D28 F14 Source Sync Input Output DBR AC2 Power Other Output D29 G14 Source Sync Input Output DBSY B2 Common Clk Input Output D30 F15 Source Sync Input Output DEFER G7 Common Clk Input D31 G15 Source Sync Input Output DPO J16 Common CIk Input Output D32 G16 Source Sync Input Output DP1 H15 Common Clk Input Output D33 E15 Source Sync Input Output DP2 H16 Common Clk Input Output D34 E16 Source Sync Input Output DP3 J17 Common CIk Input Output D35 G18 Source Sync Input Output DRDY C Common CIk Input Output D36 G17 Source Sync Input Output DSTBNO C8 Source Sync Input Output D37 F17 Source Sync Input Output DSTBN1 G12 Source Sync Input Output D38 F18 Source Sync Input Output DSTBN2 G20 Source Sync Input Output D39 E18 Source Sync Input Output DSTBN3 A16 Source Sync Input Output D40 E19 Source Sync Input Output DSTBPO B9 Source Sync Input Output 48 intel Land Listing Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 5 of 20 Sheet 6 of 20 Pin Name Ne Ea Direction Pin Name ge es Direction DSTBP1 E12 Source Sync Input Output RESERVED AN6 DSTBP2 G19 Source Sync Input Output RESERVED B13 DSTBP3 C17 Source Sync Input Output RESERVED B23 FERR PBE R3 Open Drai
163. ut Output AM27 vss Power Other B11 VSS Power Other AM28 VSS Power Other B12 D13 Source Sync Input Output AM29 VCC Power Other B13 RESERVED AM3 VID2 CMOS Async Output B14 vss Power Other AM30 VCC Power Other B15 D53 Source Sync Input Output AM4 VSS Power Other B16 D55 Source Sync Input Output AM5 VID6 CMOS Async Output B17 vss Power Other AM6 RESERVED B18 D57 Source Sync Input Output AM7 vss Power Other B19 D60 Source Sync Input Output AM8 VCC Power Other B2 DBSY Common Clk Input Output AM9 VCC Power Other B20 VSS Power Other AN1 VSS Power Other B21 D59 Source Sync Input Output AN10 VSS Power Other B22 D63 Source Sync Input Output AN11 VCC Power Other B23 RESERVED AN12 VCC Power Other B24 VSS Power Other AN13 VSS Power Other B25 VIT Power Other AN14 VCC Power Other B26 VIT Power Other AN15 VCC Power Other B27 VIT Power Other AN16 VSS Power Other B28 VIT Power Other AN17 VSS Power Other B29 VIT Power Other AN18 VCC Power Other B3 RSO Common Clk Input AN19 VCC Power Other B30 VIT Power Other AN2 VSS Power Other B4 D00 Source Sync Input Output AN20 vss Power Other B5 vss Power Other AN21 VCC Power Other B6 D05 Source Sync Input Output AN22 VCC Power Other B7 DO6 Source Sync Input Output AN23 VSS Power Other B8 VSS Power Other AN24 VSS Power Other B9 DSTBPO Source Sync Input Output AN25 VCC Power Other C1 DRDY Common Clk Input Output AN26 VCC Power Other C10 VSS Power Other A
164. ut Zones Part 2 emen nnns 103 8 6 Bottom Side Board Keepout Zones 104 8 7 Board Mounting Hole Keepout Zones kk kk kak kk kaka kk 105 8 8 Volumetric Height Keep Ins Mhk LA NAwl lkkkl lk kk kk kk kaka kk kaka 106 8 9 4 Pin Fan Cable Connector For Active CEK Heat Sink 107 8 10 4 Pin Base Board Fan Header For Active CEK Heat Sink 108 8 11 Fan Cable Connector Pin Out for 4 Pin Active CEK Thermal Solution 110 Dual Core Intel Xeon Processor 5200 Series Datasheet 5 Tables 1 1 Dual Core Intel Xeon Processor 5200 Series r ne 10 2 1 Core Frequency to FSB Multiplier Configuration rr 17 2 2 BSEL 2 0 Frequency Table 18 2 3 Voltage Identification Definition ee eee nner tenia 20 2 4 Loadline Selection Truth Table for LL_ID 1 0 cee kk 21 2 5 Market Segment Selection Truth Table for MS ID 1 0 seem Ree 21 2 6 Ee E TB Group EE 22 2 7 AGTL Signal Description Table 23 2 8 Non AGTL Signal Description Table 23 2 9 Signal Reference Voltages Tr kk kaka kaka kak ak kaka ens 23 2 10 PECI DC Electrical Limits i ki ci k vik ndannyna a nemen ny xak kal paq k 4 aa Xan a wa kana 25 2 11 Processor Absolute Maximum Rating 27 2 12 Voltage and Current Specifications kk ene 28 2 13 Dual Core Intel Xeon Processor E5200 Series an
165. ve thermal solution design will mechanically fit into a 2U volumetric it may not provide adequate airflow This is due to the requirement of additional space at the top of the thermal solution to allow sufficient airflow into the heat sink fan Use of the active configuration in a 2U rackmount chassis is not recommended It is recommended that the ambient air temperature outside of the chassis be kept at or below 35 C The air passing directly over the processor thermal solution should not be preheated by other system components Meeting the processor s temperature specification is the responsibility of the system integrator 2U Passive Heat Sink Solution 2U Rack or Pedestal In the 2U passive configuration it is assumed that a chassis duct will be implemented to provide a minimum airflow of 27 cfm at 0 182 in H20 45 9 m3 hr at 45 3 Pa of flow impedance The duct should be carefully designed to minimize the airflow bypass around the heatsink These specifications apply to both copper and aluminum heatsink solutions The T 4 temperature of 40 C should be met This may require the use of superior design techniques to keep Tn sg at or below 5 C based on an ambient external temperature of 35 C Boxed Processor Contents A direct chassis attach method must be used to avoid problems related to shock and vibration The board must not bend beyond specification in order to avoid damage The boxed processor contains the components necessary to s
166. vibration tests 8 For more information on the transient bend limits please refer to the MAS document titled Manufacturing with Intel components using 771 land LGA package that interfaces with the motherboard via a LGA771 socket 9 Refer to the Dual Core Intel Xeon Processor 5200 Series Thermal Mechanical Design Guidelines TMDG for information on heatsink clip load metrology 43 Table 3 2 3 5 3 6 3 7 Table 3 3 3 8 44 Mechanical Specifications Package Handling Guidelines Table 3 2 includes a list of guidelines on a package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate These package handling loads may be experienced during heatsink removal Package Handling Guidelines Parameter Maximum Recommended Units Notes Shear 311 N 1 4 5 70 Ibf Tensile 111 N 2 4 5 25 Ibf Torque 3 95 N m 3 4 5 35 LBF in Notes 1 A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface 2 Atensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface 3 Atorque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface 4 These guidelines are based on limited testing for design characterization and incidental applications one time only 5 Handling guidelines are for the package only and do not include the limits
167. y core frequency power segments and have the same internal cache sizes Mixing components operating at different internal clock frequencies is not supported and will not be validated by Intel Combining processors from different power segments is also not supported Processors within a system must operate at the same frequency per bits 12 8 of the CLOCK_FLEX_MAX MSR however this does not apply to frequency transitions initiated due to thermal events Extended HALT Enhanced Intel SpeedStep Technology transitions or assertion of the FORCEPR signal See Chapter 6 Not all operating systems can support dual processors with mixed frequencies Mixing processors of different steppings but the same model as per CPUID instruction is supported Details regarding the CPUID instruction are provided in the AP 485 Intel Processor Identification and the CPUID Instruction application note Absolute Maximum and Minimum Ratings Table 2 11 specifies absolute maximum and minimum ratings only which lie outside the functional limits of the processor Only within specified operation limits can functionality and long term reliability be expected At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits bu
168. ynchronous to ADS AP 1 0 BINIT 2 BNR 2 BPM5 BCLK 1 0 BPM3 BPMO BR 1 0 DBSY DP 3 0 DRDY HIT 2 HITM 2 LOCK MCERR 2 AGTL Source Synchronous Synchronous to assoc 1 0 strobe Signals Associated Strobe REQ 4 0 A 16 3 ADSTBO A 37 36 A 35 17 ADSTB1 D 15 0 DBIO DSTBPO DSTBNO D 31 16 DBI1 DSTBP1 DSTBN1 D 47 32 DBI2 DSTBP2 DSTBN2 D 63 48 DBI3 DSTBP3 DSTBN3 AGTL Strobes I O Synchronous to ADSTB 1 0 DSTBP 3 0 DSTBN 3 0 BCLK 1 0 Open Drain Output Asynchronous FERR PBE IERR PROCHOT THERMTRIP TDO 22 Dual Core Intel Xeon Processor 5200 Series Electrical Specifications Table 2 6 Table 2 7 Table 2 8 Table 2 9 FSB Signal Groups Sheet 2 of 2 intel Signal Group Type Signals CMOS Asynchronous Input Asynchronous A20M FORCEPR IGNNEZ INIT LINTO INTR LINT1 NMI PWRGOOD SMI STPCLK CMOS Asynchronous Output Asynchronous BSEL 2 0 VID 6 1 FSB Clock Clock BCLK 1 0 TAP Input Synchronous to TCK TCK TDI TMS TRST TAP Output Synchronous to TCK TDO Power Other Power Other GTLREF_ADD GTLREF_DATA LL ID 1 0 MS ID 1 0 PECI RESERVED SKTOCC TESTHI 12 8 Vcc VCC DIE SENSE VCC DIE SENSE2 VCCPLL VID SELECT VSS DIE SENSE VSS DIE SENSE2 Vss Vm VIT OUT VIT SEL Notes 1 Refer to Chapter 5 for signal descriptions 2 These signals may be driven simultaneously by multiple agents Wir

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