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Intel Core 2 Duo E8230

1. Writing the Local Vector Table LVT when an Interrupt is Pending May Cause an Unexpected Interrupt If a local interrupt is pending when the LVT entry is written an interrupt may be taken on the new interrupt vector even if the mask bit is set An interrupt may immediately be generated with the new vector when a LVT entry is written even if the new LVT entry has the mask bit set If there is no Interrupt Service Routine ISR set up for that vector the system will GP fault If the ISR does not do an End of Interrupt EOI the bit for the vector Intel Core 2 Duo Processor Specification Update Errata Workaround Status AW 26 Problem Implication Workaround Status AW27 Problem Implication Workaround Status AW28 Problem Intel Core 2 will be left set in the in service register and mask all interrupts at the same or lower priority Any vector programmed into an LVT entry must have an ISR associated with it even if that vector was programmed as masked This ISR routine must do an EOI to clear any unexpected interrupts that may occur The ISR associated with the spurious vector does not generate an EOI therefore the spurious vector should not be used when writing the LVT For the steppings affected see the Summary Tables of Changes Pending x87 FPU Exceptions MF Following STI May Be Serviced Before Higher Priority Interrupts Interrupts that are pending prior to the execution
2. No Fix Cause a System Hang or a Machine Check Exception AW40 X X X X No Fix A WB Store Following a REP STOS MOVS or FXSAVE May Lead to Memory Ordering Violations VM Exit with Exit Reason TPR Below Threshold Can Cause AW41 X Fixed the Blocking by MOV POP SS and Blocking by STI Bits to be Cleared in the Guest Interruptibility State Field Using Memory Type Aliasing with cacheable and WC BINA x No FIX Memory Types May Lead to Memory Ordering Violations VM Exit Caused by a SIPI Results in Zero to be Saved to the ANE i an No Fix Guest RIP Field in the VMCS AW44 X X Fixed NMIs May Not Be Blocked by a VM Entry Failure Intel Core 2 Duo Processor Specification Update Summary Tables of Changes intel NO co MO EO RO Plan ERRATA AW45 X X Fixed Partial Streaming Load Instruction Sequence May Cause the Processor to Hang AW46 X X Fixed Self Cross Modifying Code May Not be Detected or May Cause a Machine Check Exception gt Data TLB Eviction Condition in the Middle of a Cacheline AW mixga Split Load Operation May Cause the Processor to Hang Update of Read Write R W or User Supervisor U S or AW48 X X Fixed Present P Bits without TLB Shootdown May Cause Unexpected Processor Behavior RSM Instruction Execution under Certain Conditions May AW49 X X Fixed Cause Processor Hang or Unexpected Instruction Execution Results AWSO X X X X
3. Specification Update Errata AW68 Problem Implication Workaround Status AW69 Problem Implication Workaround Status AW70 Problem Implication Intel Core 2 INIT Incorrectly Resets IA32 LSTAR MSR In response to an INIT reset initiated either via the INIT pin or an IPI Inter Processor Interrupt the processor should leave MSR values unchanged Due to this erratum IA32 LSTAR MSR C0000082H which is used by the iA32e SYSCALL instruction is being cleared by an INIT reset If software programs a value in IA32 LSTAR to be used by the SYSCALL instruction and the processor subsequently receives an INIT reset the SYSCALL instructions will not behave as intended Intel has not observed this erratum in any commercially available software It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes Corruption of CS Segment Register During RSM While Transitioning From Real Mode to Protected Mode During the transition from real mode to protected mode if an SMI System Management Interrupt occurs between the MOV to CRO that sets PE Protection Enable bit O and the first far JMP the subsequent RSM Resume from System Management Mode may cause the lower two bits of CS segment register to be corrupted The corruption of the bottom two bits of the CS segment register will have no impact unless software explicitly examines t
4. VM Entry May Use Wrong Address to Access Virtual APIC Page When XFEATURE ENABLED MASK register XCRO bit 1 SSE is 1 a VM entry executed with the use TPR shadow VM execution control set to 1 may use the wrong address to access data on the virtual APIC page An affected VM entry may exhibit the following behaviors 1 it may use wrong areas of the virtual APIC page to determine whether VM entry fails or whether it induces a VM exit due to the TPR threshold or 2 it may clear wrong areas of the virtual APIC page It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes XRSTORE Instruction May Cause Extra Memory Reads An XRSTOR instruction will cause non speculative accesses to XSAVE memory area locations containing the FCW FSW and FOP FTW Floating Point FP registers even though the 64 bit restore mask specified in the EDX EAX register pair does not indicate to restore the x87 FPU state Page faults data breakpoint triggers etc may occur due to the unexpected non speculative accesses to these memory locations It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes CPUID Instruction May Return Incorrect Brand String When a CPUID instruction is executed with EAX 8000 0002H 8000 0003H or 8000 0004H the returned EAX EBX ECX and or EDX values may be incorrect When this
5. www intel com design processor specupdt 252046 htm 8 Intel Core 2 Duo Processor Specification Update 49
6. Duo Processor Specification Update 33 Status AWA4 Problem Implication Workaround Status AWA5 Problem Implication Workaround Status AW46 34 intel Errata should 1 save from the VMCS using VMREAD the value of RIP before any VM entry to the wait for SIPI state and 2 restore to the VMCS using VMWRITE that value before the next VM entry that resumes the guest in any state other than wait for SIPI For the steppings affected see the Summary Tables of Changes NMIs May Not Be Blocked by a VM Entry Failure The Intel 64 and A 32 Architectures Software Developer s Manual Volume 3B System Programming Guide Part 2 specifies that following a VM entry failure during or after loading guest state the state of blocking by NMI is what it was before VM entry If non maskable interrupts NMIs are blocked and the virtual NMIs VM execution control set to 1 this erratum may result in NMIs not being blocked after a VM entry failure during or after loading guest state VM entry failures that cause NMIs to become unblocked may cause the processor to deliver an NMI to software that is not prepared for it VMM software should configure the virtual machine control structure VMCS so that VM entry failures do not occur For the steppings affected see the Summary Tables of Changes Partial Streaming Load Instruction Sequence May Cause the Processor to Hang Under some rare conditions
7. Management Mode returns to execution flow that results in a Code Segment Limit or Canonical Fault the GP fault may be serviced before a higher priority Interrupt or Exception e g NMI Non Maskable Interrupt Debug break DB Machine Check MC etc Operating systems may observe a GP fault being serviced before higher priority Interrupts and Exceptions Intel has not observed this erratum on any commercially available software None identified For the steppings affected see the Summary Tables of Changes Store Ordering May be Incorrect between WC and WP Memory Types According to Intel 64 and IA 32 Intel Architecture Software Developer s Manual Volume 3A Methods of Caching Available WP Write Protected stores should drain the WC Write Combining buffers in the same way as UC Uncacheable memory type stores do Due to this erratum WP stores may not drain the WC buffers Memory ordering may be violated between WC and WP stores None identified For the steppings affected see the Summary Tables of Changes EFLAGS CRO CR4 and the EXF4 Signal May be Incorrect after Shutdown When the processor is going into shutdown due to an RSM inconsistency failure EFLAGS CRO and CR4 may be incorrect In addition the EXF4 signal may still be asserted This may be observed if the processor is taken out of shutdown by NMI A processor that has been taken out of shutdown may have an incorrect EFLAGS CRO and CR4 In addition the EX
8. Processor Specification Update m Specification Changes Specification Changes The Specification Changes listed in this section apply to the following documents e Intel Core 2 Duo Processor E8000 and E7000 Series Datasheet e Intel 64 and IA 32 Architectures Software Developer s Manual volumes 1 2A 2B 3A and 3B All Specification Changes will be incorporated into a future version of the appropriate processor documentation Intel Core 2 Duo Processor Specification Update 47 i n tel Specification Clarifications Specification Clarifications AW1 48 The Specification Clarifications listed in this section apply to the following documents e Intel Core 2 Duo Processor E8000 and E7000 Series Datasheet e Intel 64 and IA 32 Architectures Software Developer s Manual volumes 1 2A 2B 3A and 3B All Specification Clarifications will be incorporated into a future version of the appropriate processor documentation Clarification of TRANSLATION LOOKASIDE BUFFERS TLBS Invalidation Section 10 9 INVALIDATING THE TRANSLATION LOOKASIDE BUFFERS TLBS of the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide will be modified to include the presence of page table structure caches such as the page directory cache which Intel processors implement This information is needed to aid operating systems in managing page table structure invalidations properly Intel will u
9. Quad processor Q6000 sequence Dual Core Intel Xeon processor 7100 series Intel Celeron processor 400 sequence Intel Pentium dual core processor Quad Core Intel Xeon processor 3200 series Dual Core Intel Xeon processor 3000 series Intel Pentium dual core desktop processor E2000 sequence Intel Celeron processor 500 series Intel Xeon processor 7200 7300 series Intel Celeron processor 200 series Intel Core 2 Extreme processor QX9650 and Intel Core 2 Quad processor Q9000 series Intel Core 2 Duo processor E8000 series Quad Core Intel Xeon processor 5400 series Dual Core Intel Xeon processor 5200 series Intel Core 2 Duo Processor and Intel Core 2 Extreme Processor on 45 nm Process Quad Core Intel Xeon processor 3300 series Dual Core Intel Xeon E3110 Processor Intel Celeron dual core processor E1000 series Intel Core 2 Extreme Processor QX9775A Intel Atom processor Z5xx series Intel Atom processor 200 series Intel Atom processor N series Intel Atom Processor 300 series The Specification Updates for the Pentium processor Pentium Pro processor and other Intel products do not use this convention NO co MO EO RO Plan ERRATA AW1 x X x X No Fix EFLAGS Discrepancy on Page Faults after a Translation Change AW2 x x x X No Fix INVLPG Operation for Large 2M 4M Pages May be Incomplete under Certain C
10. String Global Instruction TLB Entries May Not be Invalidated on a nes No FIX ym Exit or VM Entry When Intel Deep Power Down State is Being Used eee x d Nori IA32_FIXED_CTR2 May Return Incorrect Cycle Counts Intel Core 2 Duo Processor Specification Update 13 n tel Summary Tables of Changes NO co MO EO RO Plan ERRATA Enabling PECI via the PECI_CTL MSR incorrectly nU X i No Fix writes CPUID FEATURE MASK1 MSR AW68 X x No Fix INIT Incorrectly Resets IA32_LSTAR MSR Corruption of CS Segment Register During RSM While ANOR x x X PERI Transitioning From Real Mode to Protected Mode LBR BTS BTM May Report a Wrong Address when an AND x No Fix Exception Interrupt Occurs in 64 bit Mode The XRSTOR Instruction May Fail to Cause a General AWI No Fix Protection Exception The XSAVE Instruction May Erroneously Set Reserved Bits AW72 X X NOFIX in the XSTATE_BV Field AW73 X X No Fix Store Ordering Violation When Using XSAVE Memory Ordering Violation With Stores Loads Crossing a Aw74 X X X X NoFix cacheline Boundary Unsynchronized Cross Modifying Code Operations Can AW73 5 Pii Ee Cause Unexpected Instruction Execution Results A Page Fault May Not be Generated When the PS bit is set AW76 X X X X NoFIX i iapMIAE or PDPTE Number SPECIFICATION CHANGES There are no Specification Changes in th
11. Summary Tables of Changes IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception In IA 32e mode it is possible to get an Alignment Check Exception ZAC on the IRET instruction even though alignment checks were disabled at the start of the IRET This can only occur if the IRET instruction is returning from CPL3 code to CPL3 code IRETs from CPLO 1 2 are not affected This erratum can occur if the EFLAGS value on the stack has the AC flag set and the interrupt handler s stack is misaligned In IA 32e mode RSP is aligned to a 16 byte boundary before pushing the stack frame In IA 32e mode under the conditions given above an IRET can get a AC even if alignment checks are disabled at the start of the IRET This erratum can only be observed with a software generated stack frame Software should not generate misaligned stack frames for use with IRET For the steppings affected see the Summary Tables of Changes PSI Signal Asserted During Reset Power Status Indicator PSI is a feature that when available may be used to enable voltage regulator power savings while idle and in the Deeper Sleep State C4 state Under proper operation the processor will assert the PSI signal to indicate that the voltage regulator can enter a higher efficiency mode of operation The processor will incorrectly assert the PSI signal while the RESET signal is asserted This PSI assertion will extend beyond the deassertion of the RESE
12. erratum occurs the processor may report an incorrect brand string It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes Intel Core 2 Duo Processor Specification Update 41 intel AW65 Problem Implication Workaround Status AW66 Problem Implication Workaround Status AW67 Problem Implication Workaround Status 42 Global Instruction TLB Entries May Not be Invalidated on a VM Exit or VM Entry If a VMM is using global page entries CR4 PGE is enabled and any present page directories or page table entries are marked global then on a VM entry the instruction TLB Translation Lookaside Buffer entries caching global page translations of the VMM may not be invalidated In addition if a guest is using global page entries then on a VM exit the instruction TLB entries caching global page translations of the guest may not be invalidated Stale global instruction linear to physical page translations may be used by a VMM after a VM exit or a guest after a VM entry It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes When Intel Deep Power Down State is Being Used IA32 FIXED CTR2 May Return Incorrect Cycle Counts When the processor is operating at an N 2 core to front side bus ratio after exiting an Intel Deep Power Down St
13. guidelines given in the section Handling VM Exits Due to Exceptions of Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Programming Guide For the steppings affected see the Summary Tables of Changes A VM Exit Occuring in IA 32e Mode May Not Produce a VMX Abort When Expected If a VM exit occurs while the processor is in IA 32e mode and the host address space size VM exit control is 0 a VMX abort should occur Due to this erratum the expected VMX aborts may not occur and instead the VM Exit will occur normally The conditions required to observe this erratum are a VM entry that returns from SMM with the IA 32e guest VM entry control set to 1 in the SMM VMCS and the host address space size VM exit control cleared to 0 in the executive VMCS A VM Exit will occur when a VMX Abort was expected An SMM VMM should always set the IA 32e guest VM entry control in the SMM VMCS to be the value that was in the LMA bit IA32 EFER LMA LMA bit 10 in the IA32 EFER MSR C0000080H at the time of the last SMM VM exit If this guideline is followed that value will be 1 only if the host address space size VM exit control is 1 in the executive VMCS Intel Core 2 Duo Processor Specification Update Errata Status AW57 Problem Implication Workaround Status AWSS Problem Implication Workaround Status AW59 Problem For the steppings affected see the
14. if an instruction that masks the interrupt flag e g CLI is executed soon after an uncacheable write to the Task Priority Register TPR that lowers the APIC priority the interrupt masking operation may take effect before the actual priority has been lowered This may cause interrupts whose priority is lower than the initial TPR but higher than the final TPR to not be serviced until the interrupt enabled flag is finally set i e by STI instruction Interrupts will remain pending and are not lost In this example the processor may allow interrupts to be accepted but may delay their service This non synchronization can be avoided by issuing an APIC register read after the APIC register write This will force the store to the APIC register before any subsequent instructions are executed No commercial operating system is known to be impacted by this erratum For the steppings affected see the Summary Tables of Changes Last Branch Records LBR Updates May be Incorrect after a Task Switch A Task State Segment TSS task switch may incorrectly set the LBR_FROM value to the LBR_TO value The LBR_FROM will have the incorrect address of the Branch Instruction None identified For the steppings affected see the Summary Tables of Changes Intel Core 2 Duo Processor Specification Update Errata AW15 Problem Implication Workaround Status AW16 Problem Implication Workaround Status AW17 Probl
15. range coherent with all TLB Translation Lookaside Buffers and paging structures caches in the processor in conjunction with a complex sequence of internal processor micro architectural events and store operations may lead to unexpected processor behavior This erratum may lead to livelock shutdown or other unexpected processor behavior Intel has not observed this erratum with any commercially available software None identified For the steppings affected see the Summary Tables of Changes RSM Instruction Execution under Certain Conditions May Cause Processor Hang or Unexpected Instruction Execution Results Intel Core 2 Duo Processor Specification Update 35 intel Problem Implication Workaround Status AWBO Problem Implication Workaround Status AW51 Problem Implication Workaround Status AW52 Problem 36 RSM instruction execution under certain conditions triggered by a complex sequence of internal processor micro architectural events may lead to processor hang or unexpected instruction execution results In the above sequence the processor may live lock or hang or RSM instruction may restart the interrupted processor context through a nondeterministic EIP offset in the code segment resulting in unexpected instruction execution unexpected exceptions or system hang Intel has not observed this erratum with any commercially available software It is possible for the B
16. the same time may experience a memory ordering issue if multiple loads access this shared data shortly thereafter Exposure to this problem requires the use of a data write which spans a cache line boundary This erratum may cause loads to be observed out of order Intel has not observed this erratum with any commercially available software or system Software should ensure at least one of the following is true when modifying shared data by multiple agents e The shared data is aligned e Proper semaphores or barriers are used in order to prevent concurrent data accesses For the steppings affected see the Summary Tables of Changes General Protection ZGP Fault May Not Be Signaled on Data Segment Limit Violation above 4 G Limit In 32 bit mode memory accesses to flat data segments base 00000000h that occur above the 4G limit Offffffffh may not signal a GP fault When such memory accesses occur in 32 bit mode the system may not issue a GP fault Software should ensure that memory accesses in 32 bit mode do not occur above the 4G limit Offffffffh For the steppings affected see the Summary Tables of Changes An Asynchronous MCE During a Far Transfer May Corrupt ESP If an asynchronous machine check occurs during an interrupt call through gate FAR RET or IRET and in the presence of certain internal conditions ESP may be corrupted If the MCE Machine Check Exception handler is called without a stack switch then a tri
17. use of MOV SS POP SS in conjunction with MOV r e SP r e BP will avoid the failure since the MOV r e SP r e BP will not generate a floating point exception Developers of debug tools should be aware of the potential incorrect debug event signaling created by this erratum For the steppings affected see the Summary Tables of Changes LER MSRs May be Incorrectly Updated The LER Last Exception Record MSRs MSR_LER_FROM_LIP 1DDH and MSR_LER_TO_LIP 1DEH may contain incorrect values after any of the following e Either STPCLK NMI NonMaskable Interrupt or external interrupts e CMP or TEST instructions with an uncacheable memory operand followed by a conditional jump e STI POP SS MOV SS instructions followed by CMP or TEST instructions and then by a conditional jump When the conditions for this erratum occur the value of the LER MSRs may be incorrectly updated None identified For the steppings affected see the Summary Tables of Changes IA32 MC1 STATUS MSR Bit 60 Does Not Reflect Machine Check Error Reporting Enable Correctly IA32 MC1 STATUS MSR 405H bit 60 EN Error Enabled is supposed to indicate whether the enable bit in the IA32 MC1 CTL MSR 404H was set at the time of the last update to the IA32 MC1 STATUS MSR Due to this erratum IA32 MC1 STATUS MSR bit 60 instead reports the current value of the IA32 MC1 CTL MSR enable bit Intel Core 2 Duo Processor Specification Update 37 intel a Implicati
18. E or SFENCE instruction between the string FXSAVE operation and following store order sensitive code such as that used for synchronization For the steppings affected see the Summary Tables of Changes VM Exit with Exit Reason TPR Below Threshold Can Cause the Blocking by MOV POP SS and Blocking by STI Bits to be Cleared in the Guest Interruptibility State Field As specified in Section VM Exits Induced by the TPR Shadow in the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B a VM exit occurs immediately after any VM entry performed with the use TPR shadow activate secondary controls and virtualize APIC accesses VM execution controls all set to 1 and with the value of the TPR shadow bits 7 4 in byte 80H of the virtual APIC page less than the TPR threshold VM execution control field Due to this erratum such a VM exit will clear bit O blocking by STI and bit 1 blocking by MOV POP SS of the interruptibility state field of the guest state area of the VMCS bit O blocking by STI and bit 1 blocking by MOV POP SS should be left unmodified Since the STI MOV SS and POP SS instructions cannot modify the TPR shadow bits 1 0 of the interruptibility state field will usually be zero before any VM entry meeting the preconditions of this erratum behavior is correct in this case However if VMM software raises the value of the TPR threshold Intel Core 2 Duo Processor Specifica
19. F4 signal may still be asserted None identified For the steppings affected see the Summary Tables of Changes Intel Core 2 Duo Processor Specification Update Errata AW21 Problem Implication Workaround Status AW22 Problem Premature Execution of a Load Operation Prior to Exception Handler Invocation If any of the below circumstances occur it is possible that the load portion of the instruction will have executed before the exception handler is entered 1 If an instruction that performs a memory load causes a code segment limit violation 2 If a waiting X87 floating point FP instruction or MMX technology MMX instruction that performs a memory load has a floating point exception pending 3 If an MMX or SSE SSE2 SSE3 SSSE3 extensions SSE instruction that performs a memory load and has either CRO EM 1 Emulation bit set or a floating point Top of Stack FP TOS not equal to 0 or a DNA exception pending In normal code execution where the target of the load operation is to write back memory there is no impact from the load being prematurely executed or from the restart and subsequent re execution of that instruction by the exception handler If the target of the load is to uncached memory that has a system side effect restarting the instruction may cause unexpected system behavior due to the repetition of the side effect Particularly while CRO TS bit 3 is set a MOVD MOVQ with MMX
20. IOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes Benign Exception after a Double Fault May Not Cause a Triple Fault Shutdown According to the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A Exception and Interrupt Reference if another exception occurs while attempting to call the double fault handler the processor enters shutdown mode However due to this erratum only Contributory Exceptions and Page Faults will cause a triple fault shutdown whereas a benign exception may not If a benign exception occurs while attempting to call the double fault handler the processor may hang or may handle the benign exception Intel has not observed this erratum with any commercially available software None identified For the steppings affected see the Summary Tables of Changes Short Nested Loops That Span Multiple 16 Byte Boundaries May Cause a Machine Check Exception or a System Hang Under a rare set of timing conditions and address alignment of instructions in a short nested loop sequence software that contains multiple conditional jump instructions and spans multiple 16 byte boundaries may cause a machine check exception or a system hang Due to this erratum a machine check exception or a system hang may occur It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes An Ena
21. Intel 64 and 1A 32 Architectures Software Developer s Manual Volume 3A System Programming Guide Intel 64 and 1A 32 Architectures Software Developer s Manual Volume 3B System Programming Guide 6 Intel Core 2 Duo Processor Specification Update dida intel Nomenclature S Spec Number is a five digit code used to identify products Products are differentiated by their unique characteristics e g core speed L2 cache size package type etc as described in the processor identification information table Care should be taken to read all notes associated with each S Spec number QDF Number is a several digit code that is used to distinguish between engineering samples These processors are used for qualification and early design validation The functionality of these parts can range from mechanical only to fully functional The NDA specification update has a processor identification information table that lists these QDF numbers and the corresponding product sample details Errata are design defects or errors Errata may cause the processor s behavior to deviate from published specifications Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices Specification Changes are modifications to the current published specifications These changes will be incorporated in the next release of the specifications Specification Clarifications d
22. Intel Core 2 Duo Processor E8000 and E7000 Series Specification Update on 45 nm Process in the 775 land LGA Package June 2009 Notice The Intel Core 2 Duo processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are documented in this Specification Update Document Number 318733 016 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS OTHERWISE AGREED IN WRITING BY INTEL THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence
23. NIT Does Not Clear Global Entries in the TLB INIT may not flush a TLB entry when Duo Processor Specification Update 27 Implication Workaround Status AW29 Problem Implication Workaround Status AW30 Problem Implication Workaround Status AW31 28 intel Errata e The processor is in protected mode with paging enabled and the page global enable flag is set PGE bit of CR4 register e G bit for the page table entry is set e TLB entry is present in TLB when INIT occurs Software may encounter unexpected page fault or incorrect address translation due to a TLB entry erroneously left in TLB after INIT Write to CR3 CR4 setting bits PSE PGE or PAE or CRO setting bits PG or PE registers before writing to memory early in BIOS code to clear all the global entries from TLB For the steppings affected see the Summary Tables of Changes Split Locked Stores May not Trigger the Monitoring Hardware Logical processors normally resume program execution following the MWAIT when another logical processor performs a write access to a WB cacheable address within the address range used to perform the MONITOR operation Due to this erratum a logical processor may not resume execution until the next targeted interrupt event or O S timer tick following a locked store that spans across cache lines within the monitored address range The logical processor that executed the MWAIT instruction may no
24. No Fix Benign Exception after a Double Fault May Not Cause a Triple Fault Shutdown Short Nested Loops That Span Multiple 16 Byte Boundaries Pe Plan Fix May Cause a Machine Check Exception or a System Hang An Enabled Debug Breakpoint or Single Step Trap May Be AW52 X X X X No Fix Taken after MOV SS POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point Exception AW53 X X X X No Fix LER MSRs May be Incorrectly Updated IA32 MC1 STATUS MSR Bit 60 Does Not Reflect Machine Aia x No Fix Check Error Reporting Enable Correctly A VM Exit Due to a Fault While Delivering a Software AWS NO EIX Interrupt May Save Incorrect Data into the VMCS A VM Exit Occuring in IA 32e Mode May Not Produce a VMX AAS Nene Abort When Expected AWS57 X X X X No Fix IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception AW58 X X X X Plan Fix PSI Signal Asserted During Reset Thermal Interrupts are Dropped During and While Exiting AWS3 x No Fix Intel Deep Power Down State VM Entry May Fail When Attempting to Set AW60 X X X X NoFX 1432 DEBUGCTL FREEZE_WHILE_SMM_EN Processor May Hold off Delay a PECI Transaction Longer ANS No Fix than Specified by the PECI Protocol AW62 X No Fix VM Entry May Use Wrong Address to Access Virtual APIC Page AW63 X X No Fix XRSTOR Instruction May Cause Extra Memory Reads AW64 X X Plan Fix CPUID Instruction May Return Incorrect Brand
25. Page Fault PF or an access that results in either A or D bits being set in a Page Table Entry PTE Stale translations may remain valid in TLB after a PTE update resulting in unpredictable system behavior Intel has not observed this erratum with any commercially available software Software should ensure that the memory type specified in the MTRRs is the same for the entire address range of the large page For the steppings affected see the Summary Tables of Changes Intel Core 2 Duo Processor Specification Update Errata AW3 Problem Implication Workaround Status AWA Problem Implication Workaround Status AW5 Problem Implication Workaround Status AWSG Problem Intel Core 2 Store to WT Memory Data May be Seen in Wrong Order by Two Subsequent Loads When data of Store to WT memory is used by two subsequent loads of one thread and another thread performs cacheable write to the same address the first load may get the data from external memory or L2 written by another core while the second load will get the data straight from the WT Store Software that uses WB to WT memory aliasing may violate proper store ordering Do not use WB to WT aliasing For the steppings affected see the Summary Tables of Changes Non Temporal Data Store May be Observed in Wrong Program Order When non temporal data is accessed by multiple read operations in one thread while another thre
26. STI May Be AW26 A No Fix Serviced Before Higher Priority Interrupts i VERW VERR LSL LAR Instructions May Unexpectedly BNET A NOT Update the Last Exception Record LER MSR AW28 X X X X No Fix INIT Does Not Clear Global Entries in the TLB AW29 X X X X No Fix Split Locked Stores May not Trigger the Monitoring Hardware AW30 X X x X No Fix Programming the Digital Thermal Sensor DTS Threshold May Cause Unexpected Thermal Interrupts Writing Shared Unaligned Data that Crosses a Cache Line AW31 X X X X No Fix without Proper Semaphores or Barriers May Expose a Memory Ordering Issue General Protection GP Fault May Not Be Signaled on AW32 x No TIE Data Segment Limit Violation above 4 G Limit AW33 X X X X No Fix d ad MCE During a Far Transfer May Corrupt CPUID Reports Architectural Performance AW34 X X X X Plan Fix Monitoring Version 2 is Supported When Only Version 1 Capabilities are Available AW35 X X x X No Fix BO B3 Bits in DR6 May Not be Properly Cleared After Code Breakpoint An xTPR Update Transaction Cycle if Enabled May be AW36 X X X X No Fix Issued to the FSB after the Processor has Issued a Stop Grant Special Cycle Performance Monitoring Event IA32 FIXED CTR2 May Not AW37 X X Fixed Function Properly when Max Ratio is a Non Integer Core to Bus Ratio Instruction Fetch May Cause a Livelock During Snoops of AW383 x No Fix the L1 Data Cache 7 Use of Memory Aliasing with Inconsistent Memory Type may ANS
27. T signal for a short duration maximum of one millisecond When this erratum occurs on a platform designed to support PSI the voltage regulator will transition to mode of operation that may not be capable of supplying the necessary voltage and current required by the processor Do not use PSI signal without blocking the assertion during the error period as specified from RESET assertion to a maximum of ims from the deasserted edge For the steppings affected see the Summary Tables of Changes Thermal Interrupts are Dropped During and While Exiting Intel Deep Power Down State Thermal interrupts are ignored while the processor is in Intel Deep Power Down State as well as during a small window of time while exiting from Intel Deep Power Down State During this window if the PROCHOT signal is driven or the internal value of the sensor reaches the programmed thermal trip point then the associated thermal interrupt may be lost Intel Core 2 Duo Processor Specification Update 39 intel Implication Workaround Status AW6O0 Problem Implication Workaround Status AW61 Problem Implication Workaround 40 In the event of a thermal event while a processor is waking up from Intel Deep Power Down State the processor will initiate an appropriate throttle response However the associated thermal interrupt generated may be lost None identified For the steppings affected see the Summary T
28. XMM register operands may issue a memory load before getting the DNA exception Code which performs loads from memory that has side effects can effectively workaround this behavior by using simple integer based load instructions when accessing side effect memory and by ensuring that all code is written such that a code segment limit violation cannot occur as a part of reading from side effect memory For the steppings affected see the Summary Tables of Changes Performance Monitoring Events for Retired Instructions COH May Not Be Accurate The INST RETIRED performance monitor may miscount retired instructions as follows e Repeat string and repeat I O operations are not counted when a hardware interrupt is received during or after the last iteration of the repeat flow e VMLAUNCH and VMRESUME instructions are not counted e HLT and MWAIT instructions are not counted The following instructions if executed during HLT or MWAIT events are also not counted a RSM from a C state SMI during an MWAIT instruction Intel Core 2 Duo Processor Specification Update 25 intel Implication Workaround Status AW23 Problem Implication Workaround Status AW 24 Problem Implication Workaround Status AW25 Problem Implication 26 b RSM from an SMI during a HLT instruction There may be a smaller than expected value in the INST_RETIRED performance monitoring counter The extent to
29. a specific instruction ADD AND BTC BTR BTS CMPXCHG DEC INC NEG NOT OR ROL ROR SAL SAR SHL SHR SHLD SHRD SUB XOR and XADD causes a page fault the value saved for EFLAGS may incorrectly contain the arithmetic flag values that the EFLAGS register would have held had the instruction completed without fault This can occur even if the fault causes a VM exit or if its delivery causes a nested fault None identified Although the EFLAGS value saved may contain incorrect arithmetic flag values Intel has not identified software that is affected by this erratum This erratum will have no further effects once the original instruction is restarted because the instruction will produce the same results as if it had initially completed without a page fault If the page fault handler inspects the arithmetic portion of the saved EFLAGS value then system software should perform a synchronized paging structure modification and TLB invalidation For the steppings affected see the Summary Tables of Changes INVLPG Operation for Large 2M 4M Pages May be Incomplete under Certain Conditions The INVLPG instruction may not completely invalidate Translation Look aside Buffer TLB entries for large pages 2M 4M when both of the following conditions exist e Address range of the page being invalidated spans several Memory Type Range Registers MTRRs with different memory types specified e INVLPG operation is preceded by a Page Assist Event
30. ables of Changes VM Entry May Fail When Attempting to Set IA32 DEBUGCTL FREEZE WHILE SMM EN If bit 14 FREEZE WHILE SMM EN is set in the IA32_DEBUGCTL field in the guest state area of the VMCS VM entry may fail as described in Section VM Entry Failures During or After Loading Guest State of Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Programming Guide Part 2 The exit reason will be 80000021H and the exit qualification will be zero Note that the FREEZE WHILE SMM EN bit in the guest IA32 DEBUGCTL field may be set due to a VMWRITE to that field or due to a VM exit that occurs while IA32 DEBUGCTL FREEZE WHILE SMM EN 1 A VMM will not be able to properly virtualize a guest using the FREEZE WHILE SMM feature It is possible for the BIOS to contain a workaround for this erratum Alternatively the following software workaround may be used If a VMM wants to use the FREEZE WHILE SMM feature it can configure an entry in the VM entry MSR load area for the IA32 DEBUGCTL MSR 1D9H the value in the entry should set the FREEZE WHILE SMM EN bit In addition the VMM should use VMWRITE to clear the FREEZE WHILE SMM EN bit in the guest IA32_DEBUGCTL field before every VM entry It is necessary to do this before every VM entry because each VM exit will save that bit as 1 This workaround prevents the VM entry failure and sets the FREEZE WHILE SMM EN bit in the IA32 DEBUGCTL MSR For the steppings a
31. ad performs a cacheable write operation to the same address the data stored may be observed in wrong program order i e later load operations may read older data Software that uses non temporal data without proper serialization before accessing the non temporal data may observe data in wrong program order Software that conforms to the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A section Buffering of Write Combining Memory Locations will operate correctly For the steppings affected see the Summary Tables of Changes Page Access Bit May be Set Prior to Signaling a Code Segment Limit Fault If code segment limit is set close to the end of a code page then due to this erratum the memory page Access bit A bit may be set for the subsequent page prior to general protection fault on code segment limit When this erratum occurs a non accessed page which is present in memory and follows a page that contains the code segment limit may be tagged as accessed Erratum can be avoided by placing a guard page non present or non executable page as the last page of the segment or after the page that includes the code segment limit For the steppings affected see the Summary Tables of Changes Updating Code Page Directory Attributes without TLB Invalidation May Result in Improper Handling of Code PF Code PF Page Fault exception is normally handled in lower priority order relative to both code DB De
32. anges The Processor May Report a TS Instead of a GP Fault A jump to a busy TSS Task State Segment may cause a TS invalid TSS exception instead of a GP fault general protection exception Operation systems that access a busy TSS may get invalid TSS fault instead of a GP fault Intel has not observed this erratum with any commercially available software None identified For the steppings affected see the Summary Tables of Changes Intel Core 2 Duo Processor Specification Update 21 intel AW12 Problem Implication Workaround Status AW13 Problem Implication Workaround Status AW14 Problem Implication Workaround Status 22 Code Segment Limit Violation May Occur on 4 Gigabyte Limit Check Code Segment limit violation may occur on 4 Gigabyte limit check when the code streamwraps around in a way that one instruction ends at the last byte of the segment and the next instruction begins at 0x0 This is a rare condition that may result in a system hang Intel has not observed this erratum with any commercially available software or system Avoid code that wraps around segment limit For the steppings affected see the Summary Tables of Changes A Write to an APIC Register Sometimes May Appear to Have Not Occurred With respect to the retirement of instructions stores to the uncacheable memory based APIC register space are handled in a non synchronized way For example
33. ate the internal increment value for IA32 FIXED CTR2 Fixed Function Performance Counter 2 30BH will not take into account the half ratio setting Due to this erratum IA32 FIXED CTR2 MSR will not return reliable counts after returning from an Intel Deep Power Down State It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes Enabling PECI via the PECI CTL MSR Does Not Enable PECI and May Corrupt the CPUID Feature Flags Writing PECI_CTL MSR Platform Environment Control Interface Control Register will not update the PECI_CTL MSR 5A0H instead it will write to the VMM Feature Flag Mask MSR CPUID FEATURE MASK1 478H Due to this erratum PECI Platform Environment Control Interface will not be enabled as expected by the software In addition due to this erratum processor features reported in ECX following execution of leaf 1 of CPUID EAX 1 may be masked Software utilizing CPUID leaf 1 to verify processor capabilities may not work as intended It is possible for the BIOS to contain a workaround for this erratum Do not initialize PECI before processor update is loaded Also load processor update as soon as possible after RESET as documented in the RS Wolfdale Processor Family Bios Writers Guide Section 14 8 3 Bootstrap Processor Initialization Requirements For the steppings affected see the Summary Tables of Changes Intel Core 2 Duo Processor
34. atio Neiere da iia 15 Component Identification Informati0N ococccccncnnnncnnnnnnnnnnnnenanennnnnnnnrnnenrnnrrrnrrrrnrarenrnnrranraraninnes 16 Errata e Tine 18 Specification Changes siria a de dida AAA 47 Specification Clarifications ibid irradia aa FAR MANUS RIEN EM a 48 Documentation Changes inei nica a a 49 8 4 Intel Core 2 Duo Processor Specification Update Revision History Revision Description Number 001 m m m Initial release of ntel Core 2 Duo Desktop Processor E8000 Jan 7 2008 Series Specification Update e Added Erratum AW51 Feb 1 2008 Added Errata AW52 to AW54 Feb 13 2008 e Changed document title to include E7000 series AS Ath April 20 200 e Included E7200 and E8300 processor information pri 202008 e Included MO stepping information e Added new errata AW55 AW57 May 14 2008 Added Spec Clarification AW1 Updated Erratum AW18 Deleted Erratum AW53 and replaced with a new erratum Jul 16 2008 Added Errata AW58 AW60 Included E7300 processor on MO stepping 007 Included E8600 processo on EM stepping Aug 10 2008 Included EO stepping information Added new Errata AW61 AW70 e Included E8400 and E8500 processor on EO stepping Sept 10 2 EM e Added E7400 information Oct 20 2008 e Updated Erratum AW35 Nov 12 2008 e Added Erratum AW75 Dec 17 2008 e Updated Erratum AW72 012 Jan 19 2009 EN e Added E7500 processor information anla 013 e Corrected the Errata ID nu
35. bled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point Exception A MOV SS POP SS instruction should inhibit all interrupts including debug breakpoints until after execution of the following instruction This is intended to allow the sequential execution of MOV SS POP SS and MOV r e SP Intel Core 2 Duo Processor Specification Update Errata Implication Workaround Status AW53 Problem Implication Workaround Status AW54 Problem r e BP instructions without having an invalid stack during interrupt handling However an enabled debug breakpoint or single step trap may be taken after MOV SS POP SS if this instruction is followed by an instruction that signals a floating point exception rather than a MOV r e SP r e BP instruction This results in a debug exception being signaled on an unexpected instruction boundary since the MOV SS POP SS and the following instruction should be executed atomically This can result in incorrect signaling of a debug exception and possibly a mismatched Stack Segment and Stack Pointer If MOV SS POP SS is not followed by a MOV r e SP r e BP there may be a mismatched Stack Segment and Stack Pointer on any exception Intel has not observed this erratum with any commercially available software or system As recommended in the 1432 Intel Architecture Software Developer s Manual the
36. bug Exception and code Segment Limit Duo Processor Specification Update 19 intel Implication Workaround Status AW7 Problem Implication Workaround Status AWS Problem Implication 20 Violation GP General Protection Fault Due to this erratum code PF may be handled incorrectly if all of the following conditions are met e A PDE Page Directory Entry is modified without invalidating the corresponding TLB Translation Look aside Buffer entry e Code execution transitions to a different code page such that both o The target linear address corresponds to the modified PDE o The PTE Page Table Entry for the target linear address has an A Accessed bit that is clear e One of the following simultaneous exception conditions is present following the code transition o Code DB and code PF o Code Segment Limit Violation GP and code PF Software may observe either incorrect processing of code PF before code Segment Limit Violation GP or processing of code PF in lieu of code DB None identified For the steppings affected see the Summary Tables of Changes Storage of PEBS Record Delayed Following Execution of MOV SS or STI When a performance monitoring counter is configured for PEBS Precise Event Based Sampling overflow of the counter results in storage of a PEBS record in the PEBS buffer The information in the PEBS record represents the state of the next instruction to be executed f
37. chnology Intel Pentium 4 processor on 90 nm process 64 bit Intel Xeon processor with 800 MHz system bus 1 MB and 2 MB L2 cache versions Mobile Intel Pentium 4 processor M 64 bit Intel Xeon processor MP with up to 8MB L3 cache Mobile Intel Celeron processor on 13 micron process in Micro FCPGA package Intel Celeron M processor Intel Pentium M processor on 90nm process with 2 MB L2 cache and Intel processor A100 and A110 with 512 KB L2 cache Intel Pentium M processor Mobile Intel Pentium 4 processor with 533 MHz system bus Intel Pentium D processor 900 sequence and Intel Pentium processor Extreme Edition 955 965 Intel Pentium 4 processor 6x1 sequence Intel R Celeron R processor in 478 pin package Intel R Celeron R D processor on 65nm process Intel Core Duo processor and Intel Core Solo processor on 65nm process Dual Core Intel Xeon processor LV Dual Core Intel Xeon processor 5100 series Intel Core 2 Duo Processor Specification Update 10 AAA AAB AAC AAD AAE AAF AAG AAH Summary Tables of Changes Intel Core 2 Duo Solo processor for Intel Centrino Duo processor technology Intel Core 2 Extreme processor X6800 and Intel Core 2 Duo desktop processor E6000 and E4000 sequence Quad Core Intel Xeon processor 5300 series Intel Core 2 Extreme quad core processor QX6000 sequence and Intel Core 2
38. ds Crossing a Cacheline Boundary When two logical processors are accessing the same data that is crossing a cacheline boundary without serialization with a specific set of processor internal conditions it is possible to have an ordering violation between memory store and load operations Due to this erratum proper load store ordering may not be followed when multiple logical processors are accessing the same data that crosses a cacheline boundary without serialization It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes Unsynchronized Cross Modifying Code Operations Can Cause Unexpected Instruction Execution Results The act of one processor or system bus master writing data into a currently executing code segment of a second processor with the intent of having the second processor execute that data as code is called cross modifying code XMC XMC that does not force the second processor to execute a synchronizing instruction prior to execution of the new code is called unsynchronized XMC Software using unsynchronized XMC to modify the instruction byte stream of a processor can see unexpected or unpredictable execution behavior from the processor that is executing the modified code In this case the phrase unexpected or unpredictable execution behavior encompasses the generation of most of the exceptions listed in the Intel Architecture Software De
39. e 2 Duo Processor Specification Update Component Identification nformation Table 1 Intel Core 2 Duo Processor Identification Information intel L2 Cache Core Processor Processor Speed S Spec stepping Size Signature Number Core Bus Package Notes bytes 2 53 GHz E 1 2 3 6 7 8 9 SLAPC MO 3 MB 10676h E7200 1066 MHz 775 land LGA 10 11 12 13 2 66 GHz f 1 2 3 6 7 8 9 SLB9X MO 3 MB 10676h E7300 1066 MHz 775 land LGA 10 11 12 13 6 MB 2 66 GHz T 1 2 3 6 7 8 9 SLAQR CO 2 x 3MB 10676h E8190 1333 MHz 775 land LGA 10 11 12 13 6 MB 2 66 GHz j 1 2 3 4 5 6 7 SLAPP CO 2 x 3MB 10676h E8200 1333 MHz 775 land LGA 8 9 10 11 12 13 6 MB 2 83 GHz i 1 2 3 4 5 6 7 SLAPJ CO 2 x 3MB 10676h E8300 1333 MHz 775 land LGA 8 9 10 11 12 13 6 MB 3 00 GHz 1 2 3 4 5 6 7 SLAPL CO 2 x 3MB 10676h E8400 1333 MHz 775 land LGA 8 9 10 11 12 13 6 MB 3 16 GHz 1 2 3 4 5 0 7 SLAPK CO 2 x 3MB 10676h E8500 1333 MHz 775 land LGA 8 9 10 11 12 13 2 80 GHz f 1 2 3 6 7 8 9 SLB9Y RO 3 MB 1067Ah E7400 1066 MHz 775 land LGA 10 11 12 13 2 93 GHz E 1 2 3 6 7 8 9 SLB9Z RO 3 MB 1067Ah E7500 1066 MHz 775 land LGA 10 11 12 13 GHz iby Dy Sy Gin Oy Ty Sy SLGTD RO 3 MB 1067Ah E7600 1066 MHz 775 land LGA 9 10 11 12 13 6 MB 3 00 GHz E 1 2 3 4 5 6 7 SLB9J EO 2 x 3MB 1067Ah E8400 1333 MHz 775 la
40. e Incorrectly Set Some of the BO B3 bits breakpoint conditions detect flags bits 3 0 in DR6 may be incorrectly set for non enabled breakpoints when the following sequence happens 1 MOV or POP instruction to SS Stack Segment selector 2 Next instruction is FP Floating Point that gets FP assist 3 Another instruction after the FP instruction completes successfully 4 A breakpoint occurs due to either a data breakpoint on the preceding instruction or a code breakpoint on the next instruction Due to this erratum a non enabled breakpoint triggered on step 1 or step 2 may be reported in BO B3 after the breakpoint occurs in step 4 Due to this erratum BO B3 bits in DR6 may be incorrectly set for non enabled breakpoints Software should not execute a floating point instruction directly after a MOV SS or POP SS instruction For the steppings affected see the Summary Tables of Changes An xTPR Update Transaction Cycle if Enabled May be Issued to the FSB after the Processor has Issued a Stop Grant Special Cycle According to the FSB Front Side Bus protocol specification no FSB cycles should be issued by the processor once a Stop Grant special cycle has been issued to the bus If xTPR update transactions are enabled by clearing the IA32 MISC ENABLES bit 23 at the time of Stop Clock assertion an xTPR update transaction cycle may be issued to the FSB after the processor has issued a Stop Grant Acknowledge transaction When t
41. ecution Technology is a security technology under development by Intel and requires for operation a computer system with Intel Virtualization Technology an Intel Trusted Execution Technology enabled Intel processor chipset BIOS Authenticated Code Modules and an Intel or other Intel Trusted Execution Technology compatible measured virtual machine monitor In addition Intel Trusted Execution Technology requires the system to contain a TPMv1 2 as defined by the Trusted Computing Group and specific software for some uses A Intel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families See http www intel com products processor number for details Intel the Intel logo Celeron Pentium Xeon Intel SpeedStep Intel Core and Core Inside are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Other names and brands may be claimed as the property of others Copyright 2008 2009 Intel Corporation All rights reserved 2 Intel Core 2 Duo Processor Specification Update Intel Core 2 Duo Processor Specification Update Contents Contents reciia A tensa gads a a Zs ape nila Aa w abet biere AAEE aiden E EENEN EOE E ain nine ea memes 4 REVISION MISO Yair EE 5 Preface ii A a O o a ii 6 Summary Tables Of Changes s m ici ri A AA A a ee aenan s 8 Identification Inform
42. em Implication REP MOVS STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead to Memory Ordering Violations Under certain conditions as described in the Software Developers Manual section Out of Order Stores For String Operations in Pentium 4 Intel Xeon and P6 Family Processors the processor performs REP MOVS or REP STOS as fast strings Due to this erratum fast string REP MOVS REP STOS instructions that cross page boundaries from WB WC memory types to UC WP WT memory types may start using an incorrect data size or may observe memory ordering violations Upon crossing the page boundary the following may occur dependent on the new page memory type e UC the data size of each write will now always be 8 bytes as opposed to the original data size e WP the data size of each write will now always be 8 bytes as opposed to the original data size and there may be a memory ordering violation e WT there may be a memory ordering violation Software should avoid crossing page boundaries from WB or WC memory type to UC WP or WT memory type within a single REP MOVS or REP STOS instruction that will execute with fast strings enabled For the steppings affected see the Summary Tables of Changes Upper 32 bits of From Address Reported through BTMs or BTSs May be Incorrect When a far transfer switches the processor from 32 bit mode to IA 32e mode
43. em Implication Workaround Status AW41 Problem Implication 32 This erratum has not been observed with commercially available software Although it is possible to have a single physical page mapped by two different linear addresses with different memory types Intel has strongly discouraged this practice as it may lead to undefined results Software that needs to implement memory aliasing should manage the memory type consistency For the steppings affected see the Summary Tables of Changes A WB Store Following a REP STOS MOVS or FXSAVE May Lead to Memory Ordering Violations Under certain conditions as described in the Software Developers Manual section Out of Order Stores For String Operations in Pentium 4 Intel Xeon and P6 Family Processors the processor may perform REP MOVS or REP STOS as write combining stores referred to as fast strings for optimal performance FXSAVE may also be internally implemented using write combining stores Due to this erratum stores of a WB write back memory type to a cache line previously written by a preceding fast string FXSAVE instruction may be observed before string FXSAVE stores A write back store may be observed before a previous string or FXSAVE related store Intel has not observed this erratum with any commercially available software Software desiring strict ordering of string FXSAVE operations relative to subsequent write back stores should add an MFENC
44. escribe a specification in greater detail or further highlight a specification s impact to a complex design situation These clarifications will be incorporated in the next release of the specifications Documentation Changes include typos errors or omissions from the current published specifications These changes will be incorporated in the next release of the specifications Note Errata remain in the specification update throughout the product s lifecycle or until a particular stepping is no longer commercially available Under these circumstances errata removed from the specification update are archived and available upon request Specification changes specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation datasheets manuals etc 8 Intel Core 2 Duo Processor Specification Update 7 Summary Tables of Changes Summary Tables of Changes The following table indicates the Specification Changes Errata Specification Clarifications or Documentation Changes which apply to the listed MCH steppings Intel intends to fix some of the errata in a future stepping of the component and to account for the other outstanding issues through documentation or Specification Changes as noted This table uses the following notations Codes Used in Summary Table Stepping X No mark or Blank Bo
45. ffected see the Summary Tables of Changes Processor May Hold off Delay a PECI Transaction Longer than Specified by the PECI Protocol PECI Platform Environment Control Interface transactions may be held off longer than the PECI protocol hold off limit while the processor is exiting C states This may occur if STPCLK has been asserted by the system the beginning of a PECI message coincides with a C state transition and the processor is executing a long instruction flow Note that the processor can still complete the PECI transaction if the host chooses to process the remainder of the message Due to this erratum the processor may violate the PECI hold off protocol PECI hosts can choose to either complete or not complete PECI transactions when the processor goes beyond the hold off limit The processor generates Intel Core 2 Duo Processor Specification Update Errata Status AW62 Problem Implication Workaround Status AW63 Problem Implication Workaround Status AWG64 Problem Implication Workaround Status the PECI hold off indication by keeping the PECI bus high when the PECI host sends the first bit of the address timing negotiation phase If the PECI host does not choose to complete the transaction it should consider the transaction a failure and retry 1ms after the processor deactivates the hold off indication For the steppings affected see the Summary Tables of Changes
46. he CS segment register between enabling protected mode and the first far JMP Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide Part 1 in the section titled Switching to Protected Mode recommends the far JMP immediately follows the write to CRO to enable protected mode Intel has not observed this erratum with any commercially available software None identified For the steppings affected see the Summary Tables of Changes LBR BTS BTM May Report a Wrong Address when an Exception Interrupt Occurs in 64 bit Mode An exception interrupt event should be transparent to the LBR Last Branch Record BTS Branch Trace Store and BTM Branch Trace Message mechanisms However during a specific boundary condition where the exception interrupt occurs right after the execution of an instruction at the lower canonical boundary 0x00007FFFFFFFFFFF in 64 bit mode the LBR return registers will save a wrong return address with bits 63 to 48 incorrectly sign extended to all 1 s Subsequent BTS and BTM operations which report the LBR will also be incorrect LBR BTS and BTM may report incorrect information in the event of an exception interrupt Duo Processor Specification Update 43 intel Workaround Status AW71 Problem Implication Workaround Status AW72 Problem Implication Workaround Status AW73 Problem 44 None identified For the steppi
47. his erratum occurs in systems using C states C2 Stop Grant State and higher the result could be a system hang Intel Core 2 Duo Processor Specification Update Errata Workaround Status AW37 Problem Implication Workaround Status AW38 Problem Implication Workaround Status AW39 Problem BIOS must leave the xTPR update transactions disabled default For the steppings affected see the Summary Tables of Changes Performance Monitoring Event IA32 FIXED CTR2 May Not Function Properly when Max Ratio is a Non Integer Core to Bus Ratio Performance Counter IA32 FIXED CTR2 MSR 30BH event counts CPU reference clocks when the core is not in a halt state This event is not affected by core frequency changes e g P states TM2 transitions but counts at the same frequency as the Time Stamp Counter IA32 TIME STAMP COUNTER MSR 10H Due to this erratum the IA32 FIXED CTR2 will not function properly when the non integer core to bus ratio multiplier feature is used and when a non zero value is written to IA32 FIXED CTR2 Non integer core to bus ratio enables additional operating frequencies This feature can be detected by IA32 PLATFORM ID MSR 17H bit 23 The Performance Monitoring Event IA32 FIXED CTR2 may result in an inaccurate count when the non integer core to bus multiplier feature is used If writing to IA32 FIXED CTR2 and using a non integer core to bus ratio multiplier alway
48. is Specification Update revision Number SPECIFICATION CLARIFICATIONS awi clarification of TRANSLATION LOOKASIDE BUFFERS TLBS Invalidation Number DOCUMENTATION CHANGES Tere are no Documentation Changes in this Specification Update revision Intel Core 2 Duo Processor Specification Update Identification I nformation Identification Information Figure 1 Processor Package Example INTEL 06 E8500 Intel Core 2 Duo SEXXX CO0 3 16GHZ 6M 1333 06 FPO Intel Core 2 Duo Processor Specification Update 15 tel Component Identification nformation Component Identification Information The Intel Core 2 duo processor can be identified by the following values Reserved Extended Extended Reserved Processor Family Model Stepping Family Model Type Code Number ID 27 27 20 When EAX is initialized to a value of 1 the CPUID instruction returns the Extended Family Extended Model Type Family Model and Stepping value in the EAX register Note that the EDX processor signature value after reset is equivalent to the processor signature output value in the EAX register NOTES 1 The Extended Family bits 27 20 are used in conjunction with the Family Code specified in bits 11 8 to indicate whether the processor belongs to the Intel386 Intel486 Pentium Pentium Pro Pentium 4 Intel Core or Enhanced Intel Core processor family 2 The Ex
49. mbers for Errata AW58 to AW63 to Feb 11 2009 align with the errata description e Updated Erratum AW1 Mar 11 2009 e Added Erratum AW76 May 13 2009 e Added E7600 processor information June 3 2009 Intel Core 2 Duo Processor Specification Update intel i Preface This document is an update to the specifications contained in the documents listed in the following Affected Documents Related Documents table It is a compilation of device and document errata and specification clarifications and changes and is intended for hardware system manufacturers and for software developers of applications operating system and tools Information types defined in the Nomenclature section of this document are consolidated into this update document and are no longer published in other documents This document may also contain information that has not been previously published Affected Documents Document Title Document Number Intel Core 2 Duo Processor E8000 and E7000 Series Datasheet 219732 006 a Related Documents Document Title Document Location Intel 64 and 1A 32 Architectures Software Developer s Manual Volume 1 Basic Architecture Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2A Instruction Set Reference Manual A M http www intel com produc ts processor manuals index htm Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2B Instruction Set Reference Manual N Z
50. nd LGA 8 9 10 11 12 13 6 MB 3 16 GHz E 1 2 3 4 5 06 7 SLB9K EO 2 x 3MB 1067Ah E8500 1333 MHz 775 land LGA 8 9 10 11 12 13 6 MB 3 33 GHz E 1 2 3 4 5 6 7 SLB9L EO 2 x 3MB 1067Ah E8600 1333 MHz 775 land LGA 8 9 10 11 12 13 NOTES 1 These processors support the 775_VR_CONFIG_06 specifications 2 These parts support Intel 64 3 These parts support Execute Disable Bit Feature 4 These parts support Intel Virtualization Technology Intel VT 5 These parts have Intel Trusted Execution Technology Intel TXT enabled 6 These parts have PROCHOT enabled 7 These parts have THERMTRIP enabled 8 These parts support Thermal Monitor 2 TM2 feature 9 These parts have PECI enabled 10 These parts have Enhanced Intel SpeedStep Technology EIST enabled 11 These parts have Extended HALT State C1E enabled 12 These parts have Extended Stop Grant State C2E enabled 13 These parts have Deeper Sleep State C4E enabled Intel Core 2 Duo Processor Specification Update 17 intel Errata AW1 Problem Implication Workaround Status AW2 Problem Implication Workaround Status 18 EFLAGS Discrepancy on Page Faults after a Translation Change This erratum is regarding the case where paging structures are modified to change a linear address from writable to non writable without software performing an appropriate TLB invalidation When a subsequent access to that address by
51. ngs affected see the Summary Tables of Changes The XRSTOR Instruction May Fail to Cause a General Protection Exception The XFEATURE ENABLED MASK register XCRO bits 63 9 are reserved and must be 0 consequently the XRSTOR instruction should cause a general protection exception if any of the corresponding bits in the XSTATE BV field in the header of the XSAVE XRSTOR area is set to 1 Due to this erratum a logical processor may fail to cause such an exception if one or more of these reserved bits are set to 1 Software may not operate correctly if it relies on the XRSTOR instruction to cause a general protection exception when any of the bits 63 9 in the XSTATE_BV field in the header of the XSAVE XRSTOR area is set to 1 It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes The XSAVE Instruction May Erroneously Modify Reserved Bits in the XSTATE BV Field Bits 63 2 of the HEADER XSTATE BV are reserved and must be 0 Due to this erratum the XSAVE instruction may erroneously modify one or more of these bits If one of bits 63 2 of the XSTATE BV field in the header of the XSAVE XRSTOR area had been 1 and was then cleared by the XSAVE instruction a subsequent execution of XRSTOR may not generate the GP general protection exception that would have occurred in the absence of this erratum Alternatively if one of those bits had been 0 and was then set by
52. ntified For the steppings affected see the Summary Tables of Changes A REP STOS MOVS to a MONITOR MWAIT Address Range May Prevent Triggering of the Monitoring Hardware The MONITOR instruction is used to arm the address monitoring hardware for the subsequent MWAIT instruction The hardware is triggered on subsequent memory store operations to the monitored address range Due to this erratum REP STOS MOVS fast string operations to the monitored address range may prevent the actual triggering store to be propagated to the monitoring hardware A logical processor executing an MWAIT instruction may not immediately continue program execution if a REP STOS MOVS targets the monitored address range Software can avoid this erratum by not using REP STOS MOVS store operations within the monitored address range For the steppings affected see the Summary Tables of Changes Performance Monitoring Event MISALIGN_MEM_REF May Over Count Performance monitoring event MISALIGN_MEM_REF 05H is used to count the number of memory accesses that cross an 8 byte boundary and are blocked until retirement Due to this erratum the performance monitoring event MISALIGN_MEM_REF also counts other memory accesses The performance monitoring event MISALIGN_MEM_REF may over count The extent of the over counting depends on the number of memory accesses retiring while the counter is active None identified For the steppings affected see the Summary Tables of Ch
53. of the STI Set Interrupt Flag instruction are normally serviced immediately after the instruction following the STI An exception to this is if the following instruction triggers a FMF In this situation the interrupt should be serviced before the MF Because of this erratum if following STI an instruction that triggers a MF is executed while STPCLK Enhanced Intel SpeedStep Technology transitions or Thermal Monitor 1 events occur the pending MF may be serviced before higher priority interrupts Software may observe MF being serviced before higher priority interrupts None identified For the steppings affected see the Summary Tables of Changes VERW VERR LSL LAR Instructions May Unexpectedly Update the Last Exception Record LER MSR The LER MSR may be unexpectedly updated if the resultant value of the Zero Flag ZF is zero after executing the following instructions 1 VERR ZF 0 indicates unsuccessful segment read verification 2 VERW ZF 0 indicates unsuccessful segment write verification 3 LAR ZF 0 indicates unsuccessful access rights load 4 LSL ZF 0 indicates unsuccessful segment limit load The value of the LER MSR may be inaccurate if VERW VERR LSL LAR instructions are executed after the occurrence of an exception Software exception handlers that rely on the LER MSR value should read the LER MSR before executing VERW VERR LSL LAR instructions For the steppings affected see the Summary Tables of Changes I
54. ollowing the counter overflow Due to this erratum if the counter overflow occurs after execution of either MOV SS or STI storage of the PEBS record is delayed by one instruction When this erratum occurs software may observe storage of the PEBS record being delayed by one instruction following execution of MOV SS or STI The state information in the PEBS record will also reflect the one instruction delay None identified For the steppings affected see the Summary Tables of Changes Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some Transitions Performance Monitor Event FP_MMX_TRANS_TO_MMX Event CCH Umask 01H counts transitions from x87 Floating Point FP to MMX instructions Due to this erratum if only a small number of MMX instructions including EMMS are executed immediately after the last FP instruction a FP to MMX transition may not be counted The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be lower than expected The degree of undercounting is dependent on the occurrences of the erratum condition while the counter is active Intel has not observed this erratum with any commercially available software Intel Core 2 Duo Processor Specification Update Errata Workaround Status AWS Problem Implication Workaround Status AW10 Problem Implication Workaround Status AW11 Problem Implication Workaround Status intel None ide
55. on Workaround Status AW55 Problem Implication Workaround Status AW56 Problem Implication Workaround 38 14A32_MC1_STATUS MSR bit 60 may not reflect the correct state of the enable bit in the IA32_MC1_CTL MSR at the time of the last update None identified For the steppings affected see the Summary Tables of Changes A VM Exit Due to a Fault While Delivering a Software Interrupt May Save Incorrect Data into the VMCS If a fault occurs during delivery of a software interrupt INTn in virtual 8086 mode when virtual mode extensions are in effect and that fault causes a VM exit incorrect data may be saved into the VMCS Specifically information about the software interrupt may not be reported in the IDT vectoring information field In addition the interruptibility state field may indicate blocking by STI or by MOV SS if such blocking were in effect before execution of the INTn instruction or before execution of the VM entry instruction that injected the software interrupt In general VMM software that follows the guidelines given in the section Handling VM Exits Due to Exceptions of Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Programming Guide should not be affected If the erratum improperly causes indication of blocking by STI or by MOV SS the ability of a VMM to inject an interrupt may be delayed by one instruction VMM software should follow the
56. onditions AW3 Xx X X X No Fix Store to WT Memory Data May be Seen in Wrong Order by Two Subsequent Loads Intel Core 2 Duo Processor Specification Update Summary Tables of Changes intel NO co MO EO RO Plan ERRATA AWA x X X X No Fix Non Temporal Data Store May be Observed in Wrong Program Order AWS X X X X No Fix Page Access Bit May be Set Prior to Signaling a Code Segment Limit Fault Updating Code Page Directory Attributes without TLB FOND 5 s NO PIE Invalidation May Result in Improper Handling of Code PF Storage of PEBS Record Delayed Following Execution of AW7 X X X X No Fix MOV SS or STI AW8 x X x X No Fix Performance Monitoring Event FP MMX TRANS TO MMX May Not Count Some Transitions AWO X X X X No Fix A REP STOS MOVS to a MONITOR MWAIT Address Range May Prevent Triggering of the Monitoring Hardware AW10 x x x x No Fix Performance Monitoring Event MISALIGN_MEM_REF May Over Count AW11 X X X X No Fix The Processor May Report a TS Instead of a GP Fault AW12 X X X X No Fix Code Segment limit violation may occur on 4 Gigabyte limit check AW13 x x x X No Fix A Write to an APIC Register Sometimes May Appear to Have Not Occurred AW14 x x x X No Fix Last Branch Records LBR Updates May be Incorrect after a Task Switch REP MOVS STOS Executing with Fast Strings Enabled and AW15 X X X X No Fix Crossing Page Boundaries
57. one identified Intel does not support the use of cacheable and WC memory type aliasing and WC operations are defined as weakly ordered For the steppings affected see the Summary Tables of Changes VM Exit Caused by a SIPI Results in Zero to be Saved to the Guest RIP Field in the VMCS If a logical processor is in VMX non root operation and in the wait for SIPI state an occurrence of a start up IPI SIPI causes a VM exit Due to this erratum such VM exits always save zero into the RIP field of the guest state area of the virtual machine control structure VMCS instead of the value of RIP before the SIPI was received In the absence of virtualization a SIPI received by a logical processor in the wait for SIPI state results in the logical processor starting execution from the vector sent in the SIPI regardless of the value of RIP before the SIPI was received A virtual machine monitor VMM responding to a SIPI induced VM exit can emulate this behavior because the SIPI vector is saved in the lower 8 bits of the exit qualification field in the VMCS Such a VMM should be unaffected by this erratum A VMM that does not emulate this behavior may need to recover the old value of RIP through alternative means Intel has not observed this erratum with any commercially available software VMM software that may respond to SIPI induced VM exits by resuming the interrupt guest context without emulating the non virtualized SIPI response Intel Core 2
58. or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality O Intel 64 requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel 64 Processor will not operate including 32 bit operation without an Intel 64 enabled BIOS Performance will vary depending on your hardware and software configurations See http www intel com technology intel64 for more information including details on which processors support Intel 64 or consult with your system vendor for more information Intel Virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM and for some uses certain platform software enabled for it Functionality performance or other benefits will vary depending on hardware and software configurations Intel Virtualization Technology enabled BIOS and VMM applications are currently in development F No computer system can provide absolute security under all conditions Intel Trusted Ex
59. pdate the Intel 64 and A 32 Architectures Software Developer s Manual Volume 3A System Programming Guide in the coming months Until that time an application note TLBs Paging Structure Caches and Their Invalidation http www intel com products processor manuals index htm is available which provides more information on the paging structure caches and TLB invalidation In rare instances improper TLB invalidation may result in unpredictable system behavior such as system hangs or incorrect data Developers of operating systems should take this documentation into account when designing TLB invalidation algorithms For the processors affected Intel has provided a recommended update to system and BIOS vendors to incorporate into their BIOS to resolve this issue Intel Core 2 Duo Processor Specification Update Documentation Changes j n te Documentation Changes The Documentation Changes listed in this section apply to the following documents e Intel Core 2 Duo Processor E8000 and E7000 Series Datasheet All Documentation Changes will be incorporated into a future version of the appropriate processor documentation Note Documentation changes for Intel 64 and A 32 Architectures Software Developer s Manual volumes 1 2A 2B 3A and 3B will be posted in a separate document Intel 64 and 1A 32 Architectures Software Developer s Manual Documentation Changes Follow the link below to become familiar with this file http
60. ple fault will occur due to the corrupted stack pointer resulting in a processor shutdown If the MCE is called with a stack switch e g when the CPL Current Privilege Level was changed or when going through an interrupt task gate then the corrupted ESP will be saved on the new stack or in the TSS Task State Segment and will not be used Use an interrupt task gate for the machine check handler For the steppings affected see the Summary Tables of Changes CPUID Reports Architectural Performance Monitoring Version 2 is Supported When Only Version 1 Capabilities are Available Intel Core 2 Duo Processor Specification Update 29 intel Problem Implication Workaround Status AW35 Problem Implication Workaround Status AW36 Problem Implication 30 CPUID leaf OAh reports the architectural performance monitoring version that is available in EAX 7 0 Due to this erratum CPUID reports the supported version as 2 instead of 1 Software will observe an incorrect version number in CPUID OAh EAX 7 0 in comparison to which features are actually supported Software should use the recommended enumeration mechanism described in the Architectural Performance Monitoring section of the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3 System Programming Guide For the steppings affected see the Summary Tables of Changes BO B3 Bits in DR6 For Non Enabled Breakpoints May b
61. s write a zero For the steppings affected see the Summary Tables of Changes Instruction Fetch May Cause a Livelock During Snoops of the L1 Data Cache A livelock may be observed in rare conditions when instruction fetch causes multiple level one data cache snoops Due to this erratum a livelock may occur Intel has not observed this erratum with any commercially available software It is possible for BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes Use of Memory Aliasing with Inconsistent Memory Type may Cause a System Hang or a Machine Check Exception Software that implements memory aliasing by having more than one linear addresses mapped to the same physical page with different cache types may cause the system to hang or to report a machine check exception MCE This would occur if one of the addresses is non cacheable and used in a code segment and the other is a cacheable address If the cacheable address finds its way into the instruction cache and the non cacheable address is fetched in the IFU the processor may invalidate the non cacheable address from the fetch unit Any micro architectural event that causes instruction restart will be expecting this instruction to still be in the fetch unit and lack of it will cause a system hang or an MCE Intel Core 2 Duo Processor Specification Update 31 intel Implication Workaround Status AWAO Probl
62. t in the pipeline combined with some rare internal state self modifying code SMC or cross modifying code may not be detected and or handled An instruction that should be overwritten by another instruction while in the processor pipeline may not be detected modified and could retire without detection Alternatively the instruction may cause a Machine Check Exception Intel has not observed this erratum with any commercially available software It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes Data TLB Eviction Condition in the Middle of a Cacheline Split Load Operation May Cause the Processor to Hang If the TLB translation gets evicted while completing a cacheline split load operation under rare scenarios the processor may hang The cacheline split load operation may not be able to complete normally and the machine may hang and generate Machine Check Exception Intel has not observed this erratum with any commercially available software It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Tables of Changes Update of Read Write R W or User Supervisor U S or Present P Bits without TLB Shootdown May Cause Unexpected Processor Behavior Updating a page table entry by changing R W U S or P bits even when transitioning these bits from O to 1 without keeping the affected linear address
63. t resume execution until the next targeted interrupt event or O S timer tick in the case where the monitored address is written by a locked store which is split across cache lines Do not use locked stores that span cache lines in the monitored address range For the steppings affected see the Summary Tables of Changes Programming the Digital Thermal Sensor DTS Threshold May Cause Unexpected Thermal Interrupts Software can enable DTS thermal interrupts by programming the thermal threshold and setting the respective thermal interrupt enable bit When programming DTS value the previous DTS threshold may be crossed This will generate an unexpected thermal interrupt Software may observe an unexpected thermal interrupt occur after reprogramming the thermal threshold In the ACPI OS implement a workaround by temporarily disabling the DTS threshold interrupt before updating the DTS threshold value For the steppings affected see the Summary Tables of Changes Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue Intel Core 2 Duo Processor Specification Update Errata Problem Implication Workaround Status AW32 Problem Implication Workaround Status AW33 Problem Implication Workaround Status AW34 Software which is written so that multiple agents can modify the same shared unaligned memory location at
64. tended Model bits 19 16 in conjunction with the Model Number specified in bits 7 4 are used to identify the model of the processor within the processor s family 3 The Processor Type specified in bits 13 12 indicates whether the processor is an original OEM processor an OverDrive processor or a dual processor capable of being used in a dual processor system 4 The Family Code corresponds to bits 11 8 of the EDX register after RESET bits 11 8 of the EAX register after the CPUID instruction is executed with a 1 in the EAX register and the generation field of the Device ID register accessible through Boundary Scan 5 The Model Number corresponds to bits 7 4 of the EDX register after RESET bits 7 4 of the EAX register after the CPUID instruction is executed with a 1 in the EAX register and the model field of the Device ID register accessible through Boundary Scan 6 The Stepping ID in bits 3 0 indicates the revision number of that model See Error Reference source not found for the processor stepping ID number in the CPUID information Cache and TLB descriptor parameters are provided in the EAX EBX ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register Refer to the Intel Processor Identification and the CPUID Instruction Application Note AP 485 and the Wolfdale Family Processor Family BIOS Writer s Guide BWG for further information on the CPUID instruction 16 Intel Cor
65. the XSAVE instruction a subsequent execution of XRSTOR may generate a GP that would not have occurred in the absence of this erratum It is possible for the BIOS to contain a partial workaround for this erratum that prevents XSAVE from setting HEADER XSTATE BV reserved bits To ensure compatibility with future processors software should not set any XSTATE BV reserved bits when configuring the header of the XSAVE XRSTOR save area For the steppings affected see the Summary Tables of Changes Store Ordering Violation When Using XSAVE The store operations done as part of the XSAVE instruction may cause a store ordering violation with older store operations The store operations done to save the processor context in the XSAVE instruction flow when XSAVE is used to store only the SSE context may appear to execute before the completion of older store operations Intel Core 2 Duo Processor Specification Update Errata Implication Workaround Status AW74 Problem Implication Workaround Status AW75 Problem Implication Workaround Status Intel Core 2 Execution of the stores in XSAVE when XSAVE is used to store SSE context only may not follow program order and may execute before older stores Intel has not observed this erratum with any commercially available software None identified For the steppings affected see the Summary Tables of Changes Memory Ordering Violation With Stores Loa
66. the upper 32 bits of the From source addresses reported through the BTMs Branch Trace Messages or BTSs Branch Trace Stores may be incorrect The upper 32 bits of the From address debug information reported through BTMs or BTSs may be incorrect during this transition None identified For the steppings affected see the Summary Tables of Changes Address Reported by Machine Check Architecture MCA on Single bit L2 ECC Errors May be Incorrect When correctable Single bit ECC errors occur in the L2 cache the address is logged in the MCA address register MCi ADDR Under some scenarios the address reported may be incorrect Software should not rely on the value reported in MCi ADDR for Single bit L2 ECC errors Intel Core 2 Duo Processor Specification Update 23 intel a Workaround Status AW18 Problem Implication Workaround Status AW19 Problem Implication Workaround Status AW20 Problem Implication Workaround Status 24 None identified For the steppings affected see the Summary Tables of Changes Code Segment Limit Canonical Faults on RSM May be Serviced before Higher Priority Interrupts Exceptions Normally when the processor encounters a Segment Limit or Canonical Fault due to code execution a GP General Protection Exception fault is generated after all higher priority Interrupts and exceptions are serviced Due to this erratum if RSM Resume from System
67. tion Update Errata Workaround Status AW42 Problem Implication Workaround Status AW43 Problem Implication Workaround VM execution control field above that of the TPR shadow while either of those bits is 1 incorrect behavior may result This may lead to VMM software prematurely injecting an interrupt into a guest Intel has not observed this erratum with any commercially available software VMM software raising the value of the TPR threshold VM execution control field should compare it to the TPR shadow If the threshold value is higher software should not perform a VM entry instead it could perform the actions that it would normally take in response to a VM exit with exit reason TPR below threshold For the steppings affected see the Summary Tables of Changes Using Memory Type Aliasing with Cacheable and WC Memory Types May Lead to Memory Ordering Violations Memory type aliasing occurs when a single physical page is mapped to two or more different linear addresses each with different memory types Memory type aliasing with a cacheable memory type and WC write combining may cause the processor to perform incorrect operations leading to memory ordering violations for WC operations Software that uses aliasing between cacheable and WC memory types may observe memory ordering errors within WC memory operations Intel has not observed this erratum with any commercially available software N
68. veloper s Manual Volume 3 System Programming Guide including a General Protection Fault GPF or other unexpected behaviors In the event that unpredictable execution causes a GPF the application executing the unsynchronized XMC operation would be terminated by the operating system In order to avoid this erratum programmers should use the XMC synchronization algorithm as detailed in the Intel Architecture Software Developer s Manual Volume 3 System Programming Guide Section Handling Self and Cross Modifying Code For the steppings affected see the Summary Tables of Changes Duo Processor Specification Update 45 intel a AW76 A Page Fault May Not be Generated When the PS bit is set to 1 ina PML4E or PDPTE Problem On processors supporting Intel 64 architecture the PS bit Page Size bit 7 is reserved in PML4Es and PDPTEs If the translation of the linear address of a memory access encounters a PML4E or a PDPTE with PS set to 1 a page fault should occur Due to this erratum PS of such an entry is ignored and no page fault will occur due to its being set Implication Software may not operate properly if it relies on the processor to deliver page faults when reserved bits are set in paging structure entries Workaround Software should not set bit 7 in any PML4E or PDPTE that has Present Bit Bit 0 set to 1 Status For the steppings affected see the Summary Tables of Changes 8 46 Intel Core 2 Duo
69. when multiple streaming load instructions MOVNTDQA are mixed with non streaming loads that split across cache lines the processor may hang Under the scenario described above the processor may hang Intel has not observed this erratum with any commercially available software It is possible for the BIOS to contain a workaround for this erratum However streaming behavior may be re enabled by setting bit 5 to 1 of the MSR at address 0x21 for software development or testing purposes If this bit is changed then a read modify write should be performed to preserve other bits of this MSR When the streaming behavior is enabled and using streaming load instructions always consume a full cache line worth of data and or avoid mixing them with non streaming memory references If streaming loads are used to read partial cache lines and mixed with non streaming memory references use fences to isolate the streaming load operations from non streaming memory operations For the steppings affected see the Summary Tables of Changes Self Cross Modifying Code May Not be Detected or May Cause a Machine Check Exception Intel Core 2 Duo Processor Specification Update Errata Problem Implication Workaround Status AW47 Problem Implication Workaround Status AWAS Problem Implication Workaround Status AW49 If instructions from at least three different ways in the same instruction cache set exis
70. which this value is smaller than expected is determined by the frequency of the above cases None identified For the steppings affected see the Summary Tables of Changes Returning to Real Mode from SMM with EFLAGS VM Set May Result in Unpredictable System Behavior Returning back from SMM mode into real mode while EFLAGS VM is set in SMRAM may result in unpredictable system behavior If SMM software changes the values of the EFLAGS VM in SMRAM it may result in unpredictable system behavior Intel has not observed this behavior in commercially available software SMM software should not change the value of EFLAGS VM in SMRAM For the steppings affected see the Summary Tables of Changes CMPSB LODSB or SCASB in 64 bit Mode with Count Greater or Equal to 2 May Terminate Early In 64 bit Mode CMPSB LODSB or SCASB executed with a repeat prefix and count greater than or equal to 27 may terminate early Early termination may result in one of the following e The last iteration not being executed e Signaling of a canonical limit fault GP on the last iteration While in 64 bit mode with count greater or equal to 2 repeat string operations CMPSB LODSB or SCASB may terminate without completing the last iteration Intel has not observed this erratum with any commercially available software Do not use repeated string operations with RCX greater than or equal to 2 For the steppings affected see the Summary Tables of Changes
71. with Inconsistent Memory Types may use an Incorrect Data Size or Lead to Memory Ordering Violations AW16 X X X X No Fix Upper 32 bits of From Address Reported through BTMs or BTSs May be Incorrect Address Reported by Machine Check Architecture MCA on AWIT No Fix Single bit L2 ECC Errors May be Incorrect Code Segment Limit Canonical Faults on RSM May be AW18 X X X X No Fix Serviced before Higher Priority Interrupts Exceptions and May Push the Wrong Address Onto the Stack AW19 x x x X No Fix Store Ordering May be Incorrect between WC and WP Memory Types AW20 X X x X No Fix EFLAGS CRO CR4 and the EXF4 Signal May be Incorrect after Shutdown AW21 x X X X No Fix Premature Execution of a Load Operation Prior to Exception Handler Invocation Performance Monitoring Events for Retired Instructions pes x ae PAR COH May Not Be Accurate Returning to Real Mode from SMM with EFLAGS VM Set May AW23 5 eX Result in Unpredictable System Behavior AW24 X X x X No Fix CMPSB LODSB or SCASB in 64 bit Mode with Count Greater or Equal to 2 May Terminate Early Intel Core 2 Duo Processor Specification Update 11 12 Summary Tables of Changes NO co MO EO RO Plan ERRATA AW25 X X X X No Fix Writing the Local Vector Table LVT when an Interrupt is Pending May Cause an Unexpected Interrupt Pending x87 FPU Exceptions MF Following
72. x Status Doc Plan Fix Fixed No Fix Row Shaded 8 Erratum Specification Change or Clarification that applies to this stepping This erratum is fixed in listed stepping or specification change does not apply to listed stepping Document change or update that will be implemented This erratum may be fixed in a future stepping of the product This erratum has been previously fixed There are no plans to fix this erratum This item is either new or modified from the previous version of the document Intel Core 2 Duo Processor Specification Update Summary Tables of Changes j n tel Item Numbering Each Specification Update item is prefixed with a capital letter to distinguish the product The key below details the letters that are used in Intel s microprocessor specification updates P O I Dual Core Intel Xeon processor 7000 sequence Intel Celeron processor Dual Core Intel Xeon processor 2 80 GHz Intel Pentium III processor Intel Pentium processor Extreme Edition and Intel Pentium D processor Dual Core Intel Xeon processor 5000 series 64 bit Intel Xeon processor MP with 1MB L2 cache Mobile Intel Pentium III processor Intel Celeron D processor Mobile Intel Celeron processor Intel Pentium 4 processor Intel Xeon processor MP Intel Xeon processor Mobile Intel Pentium 4 processor supporting Hyper Threading technology on 90 nm process te

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