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Netra T4 AC100/DC100 Service and System Reference Manual

1. T F 1 CA ata CeO CaCO COC re CeO ese i COC CSC CSC COC CSC CAC C ee rar pran mO Koocpecacceacccees BRECE CECE ngge BEREE S C O So E RR P j 2 S 7 g Rococo the g Ig Hoo ji i f f So Cy CD E an E 2 A Ee One CaP Cc 2D PS ee tS ae PEI e E yey Sf gt Je o y e MML H ooo p WANEN TU 9 KDP FIGURE 9 7 LOMlite2 Card 9 14 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 9 5 1 9 532 9 5 3 Preparation Before proceeding to remove the LOMlite2 Card carry out the following Initiate antistatic precautions See Section 5 5 Antistatic Precautions on page 5 5 If the system is running shut it down See Section 5 3 2 Powering Off the System on page 5 4 Remove the AC power cord from the appliance inlet and allow 10s for the standby power to dissipate before proceeding Remove the top acces
2. Non Sun device Sun device 50 pin device N 7 7 A 7 E g J a J 7 foot Oa Moe Eo z Roo i i i Adaptor cable Terminator FIGURE 11 5 Connecting External Mass Storage Devices 11 4 Ethernet Connector gt FIGURE 11 6 RJ45 TPE Socket TABLE 11 5 TPE Connector Pinout Pin Description Pin Description 1 Transmit Data 5 Common Mode Termination 2 Transmit Data 6 Receive Data 3 Receive Data 7 Common Mode Termination 4 Common Mode Termination 8 Common Mode Termination 11 8 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 TPE Cable Type Connectivity The following types of twisted pair Ethernet cable can be connected to the 8 pin TPE connector a For 10BASE T applications shielded twisted pair STP cable a Category 3 STP 3 voice grade a Category 4 STP 4 Category 5 STP 5 data grade m For 100BASE T applications shielded twisted pair category 5 STP 5 data grade cable TABLE 11 6 TPE STP 5 Cable Lengths Cable Type Application s MaxLength Max Length Metric Imperial Shielded twisted pair category 5 STP 5 data 10BASE T 1000m 3281 ft grade Shielded twisted pair category 5 STP 5 data 100BASE T 100m 328 ft grade 11 5 FC AL Connector FIGURE 11 7 FC AL Connector TABLE 11 7 FC AL Connector Pinout Pin Description Pin Description 1 Transmit Data TX_P 5 NC 2 GND 6 Receive Data
3. number of blocks 3629760 08 05 01 17 19 47 vrij SunVTS VTSID 34 disktest VERBOSE cOtO0d0 Chapter 3 SunVTS 3 3 3 1 4 1 3 4 New and Modified Tests and Commands The following commands have been added to this release of SunVTS TABLE 3 1 New SunVTS Commands Command Function testadd Adds a test s resource object files to the SunVTS shared object library contained in the SUNWvtstk package testrm Removes a test s resource object file from the SunVTS shared object library contained in the SUNWvtstk package testinfo Lists all the resource object files from the SunVTS shared object library contained in the SUNWvtstk package vts_cmd Enables direct control of SunVTS from your program or scripts on a remote machine connect Enables a user interface to connect to a SunVTS kernel on any system on a network trace System call tracing that assists in tracing test flows through the system interfaces Record Replay Enables test sequences and forks to be recorded and replayed to improve failure reproducibility Reprobe Searches and recompiles reprobes the system s configuration on demand Note To add a third party test executable binary add the test to opt SUNWvts bin sparcv9 then modify the opt SUNWvts bin sparc9 customtest file Netra T4 AC100 DC100 Service and System Reference Manual August 2001 3 1 5 The commands are shown in the SunVTS GUI menus FIGURE 3 1
4. probe scsi Identifies the devices attached to the FC AL buses probe scsi all Identifies all devices attached to all SCSI and FC AL buses test all Includes all tests probe scsi and probe scsi all The probe scsi diagnostic transmits an inquiry command to internal and external FC AL and SCSI devices connected to the system on board SCSI or FC AL interface If the SCSI device is connected and active the target address unit number device type and manufacturer name are displayed The probe scsi all diagnostic transmits an inquiry command to all devices connected to the system The first identifier listed in the display is the SCSI host adapter address in the system device tree followed by the SCSI device identification data Initiate the probe scsi diagnostic by typing the probe scsi command at the ok prompt and initiate the probe scsi all diagnostic by typing the probe scsi all command at the ok prompt To perform a probe command at the ok prompt ensure that autoboot is set to false then perform a reset all The following code examples identify the probe scsi and the probe scsi all diagnostic output messages CODE EXAMPLE 4 1 probe scsi Diagnostic Output Message ok probe scsi LiD HA Port WWN gt Disk description 1 1 210000203700ca78 EAGATE ST39103FCSUN9 0G01479916021084 3 3 210000203708ad4d EAGATE ST39102FCSUN9 0G09299906F45038 ok v n 4 10 Netra T4 AC100 DC100 Serv
5. 0 Test address line transitions 1 W Cache Init O W Cache Init 1 P Cache RAM 0 P Cache RAM l Test address up O Test address up l Test address down O Test address down 1 Test cell disturbance O0 Test cell disturbance 1 Test data reliability O Test data reliability l Test address line transitions 0 Test address line transitions 1 P Cache TAGS l Test address up 0 P Cache TAGS l Test address down O Test address up 1 Test cell disturbance O0 Test address down l Test data reliability O Test cell disturbance 1 Test address line transitions O Test data reliability E 10 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 CODE EXAMPLE E 1 diag level Variable Set to max 11 of 17 1 P Cache SnoopTags l Test address up O Test address line transitions l Test address down 0 P Cache SnoopTags 1 Test cell disturbance O Test address up l Test data reliability Test address down on Oo a i Test cell disturbance 1 Test address line transitions 0 Test data reliability 1 P Cache Status Data 0 Test address line transitions 1 Test address up 0 P Cache Status Data 1 Test address down O Test address up l Test cell disturbance 0 Test address down l Test data reliability O Test cell disturbance 1 Test address line transitions O Test data reliability 1 P Cache Init 0 Test a
6. 2 Set the diag switch and diag out console configuration variables to true ok setver diag switch true ok setver diag out console true Chapter 2 Power On Self Test 2 3 Alternatively from the shell prompt eeprom diag switch true eeprom diag out console true 3 Set the diag level configuration variable to max or min see Section 2 4 POST Diagnostic Levels on page 2 4 ok setenv diag level value eeprom diag level value or Note The default value is min 23 Running POST To run POST Initiate POST using one of the following methods a Briefly press the power ON STBY switch to power cycle the system b At the LOM prompt type poweroff followed by poweron 2 4 POST Diagnostic Levels Two levels of POST are available maximum max level and minimum min level The system initiates the selected level of POST based on the setting of diag level a configuration variable 2 4 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 2 4 1 2 4 2 The time required to complete POST depends on the CPU configuration and the amount of installed memory The following table lists the approximate time required to complete the POST for single and dual processor systems with varying memory installed for diag level variable settings of max and min TABLE 2 1 POST Completion Times CPU and Memory max setting min setting 2P 4GByte 8 minutes 5 minutes 2P
7. 9 1 9 2 PCI Cards This section describes how to remove and fit a PCI card The PCI cards connector are located on the left hand side of the motherboard at the rear of the chassis PCI slots 1 through 3 numbering from the left viewed from the front accept long 64 bit or short 32 bit cards PCI slot 4 can accept only short PCI cards owing to the placement of the FC AL backplane All slots support 33MHz cards slot 1 also supports 66 MHz cards FIGURE 9 1 PCI Card Slots Netra T4 AC100 DC100 Service and System Reference Manual August 2001 9 1 1 D2 9 1 3 Preparation Before proceeding to remove or fit a PCI card carry out the following Initiate antistatic precautions See Section 5 5 Antistatic Precautions on page 5 5 If the system is running shut it down and remove the power See Section 5 3 2 Powering Off the System on page 5 4 Remove the top access cover See Section 5 6 2 Removing the Top Access Cover on page 5 9 Removing a PCI Card Perform the steps listed in Section 9 1 1 Preparation on page 9 3 Disconnect all external cables connected to the PCI card Disconnect any internal cables connected to the PCI card Remove the fixing screw securing the card to the rear of the chassis Ease the card from its slot Place the card on the antistatic mat If you are not replacing the card fit a blanking plate to the rear panel of the chassi
8. Removing the Front Fascia on page 5 11 2 Identify all volumes or applications using the drive m If the volumes are mirrored or RAID 5 protected you can replace the drive without taking down the volume a Otherwise stop all I O activity on the disk drive using the appropriate commands for the particular application Netra T4 AC100 DC100 Service and System Reference Manual August 2001 8 2 8 1 2 Removing a Disk Drive Hot Swap 1 Carry out the steps listed in Section 8 1 1 Preparing to Remove a Disk Drive Hot Swap on page 8 2 2 Isolate the drive from the operating environment Caution Ensure that no file systems are mounted on the device and back up all data before proceeding Logically remove the drive from the FC AL bus by typing luxadm remove_device dev rdsk c1t1d0s2 The list of devices which will be removed is 1 Device dev rdsk clit1id0s2 Please enter q to Quit or lt Return gt to Continue Stopping dev rdsk cltldos2 Done Offlining dev rdsk ccclltldos2 Done Hit lt Return gt after removing the device s 3 Identify the disk to be remove and the bay in which it is installed 4 Use the World Wide Number WWN or Target ID to identify the disk ls als dev rdsk 2 lrwxrwxrws 1 root root 74 May 10 11 16 dev rdsk c0Ot1d0s0 gt devices pcit8 600000 SUNW glc 4 fp 0 0 ssd w2100002307652252 0 a raw truncated for clarity 2 lrwxrwxrws 1 root r
9. amp CoG lt n O amp i dl Hoo t i i ao e c o c CC c ees S 8 Q Q o s Eaa c CRCECECRO ROC ACCA la 5 cC S59 es acne 2S Con o i f i CDE p ses e s se oe ole fef e Wee ei fe o ML u 0 Tg H 00 0 p FIGURE 1 3 LOMLite2 Status LEDs Chapter 1 System Description 1 9 1 4 3 PSU LEDs The PSU status LEDs are located at the left hand end of the PSU see FIGURE 1 4 1 4 3 1 Netra T4 AC100 System TABLE 1 3 PSU Status LED Functions LED Icon Color Function AC Input OK Green Illuminated when AC is present and above 85 VAC PSOK Tr Green Illuminated when output voltages are within operating range Flashes when PSU is in Standby mode Fail Amber Illuminated when PSU is in a Fault condition Off when PSU is enabled OK Flashes if unit is within 10 C of thermal shutdown or has shutdown De E OCCU TOC We FIGURE 1 4 PSU Status LEDs Netra T4 AC100 System 1 10 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 1 4
10. Removing a Removable Media Module Perform the steps listed in Section 8 3 1 Preparation on page 8 10 as appropriate Loosen the four captive Phillips screws securing the RMM drive bay assembly to the front of the chassis and partially withdraw the drive bay from the chassis Disconnect the SCSI data cable at the motherboard Disconnect the power cable at the motherboard Carefully withdraw the RMM drive bay assembly from the chassis and place it on the antistatic mat Remove the DVD R drive as follows a Release the two screws securing the DVD R drive to the drive bay b Detach the power connector at the rear of the drive bay c Slide the DVD R drive out of the drive bay and place it on the antistatic mat Remove the DAT drive as follows a Detach the power connector at the rear of the drive bay b Release the clips holding the SCSI connector and detach if from the rear of the drive c Release the two screws securing the DAT drive to the drive bay d Slide the DAT drive out of the drive bay and place it on the antistatic mat If you are replacing the drive with a new one note the position of the jumpers on the drive s so that you can set up the new drive identically Chapter 8 Storage Devices 8 11 8 3 3 10 11 12 Installing a Removable Media Module Perform the steps listed in Section 8 3 1 Preparation on page 8 10 as appropriate If you are replac
11. 9 4 1 Preparation Before proceeding to remove the lithium battery carry out the following 1 Initiate antistatic precautions See Section 5 5 Antistatic Precautions on page 5 5 9 12 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 9 4 2 9 4 3 If the system is running shut it down and remove the power See Section 5 3 2 Powering Off the System on page 5 4 Remove the top access cover See Section 5 6 2 Removing the Top Access Cover on page 5 9 Removing the Battery Perform the steps listed in Section 9 4 1 Preparation on page 9 12 as required Locate the battery on the motherboard See FIGURE 9 9 Carefully lift the battery retaining clip with a small screwdriver Carefully slide the battery out of its socket and remove it from the system FIGURE 9 6 Battery Location Installing the Battery Note Install the new battery with the plus side up Hold the battery retaining clip up and slide the battery into its socket Install the CPU shroud cover Refit the top access cover See Section 5 6 3 Fitting the Top Access Cover on page 5 9 Reset the time of day and date Chapter 9 Motherboard and Component Replacement 9 13 9 5 LOMLite2 Card The LOMlite2 card is located in the RSC connector the shorter of the two slots between PCI slots 3 and 4
12. SunVTS Diagnostic Start Testing Stop Testing Thresholds Notify Reset Schedules Suspend Test Execution Resume Advanced Connect to host Option Files Trace Test Reprobe system Performance meter Exit SunVST gt FIGURE 3 1 SunVTS Menu Bar Starting SunVTS You can start SunVTS in one of four modes depending on whether you are executing locally or remotely on a CDE GUI OpenLook GUI or in TTY mode a Torun SunVTS kernel and default GUI on the local system type cd opt SUNWvts bin sunvts a Torun SunVTS kernel and OpenLook GUI on the local system type cd opt SUNWvts bin sunvts 1 Chapter 3 SunVTS 3 5 a Torun SunVTS kernel in TTY mode on the local system type cd opt SUNWvts bin sunvts t m To connect and test a remote system hostname but display the GUI on the local host type cd opt SUNWvts bin sunvts h Note The latest SunVTS features may not be supported by the SunVTS OpenLook GUI 3 2 Sun VTS Tests This section lists the tests available in SunVTS 4 4 Some tests have been modified and new tests have been added to support the Netra T4 hardware platform TABLE 3 2 SunVTS Processor Tests Test Function cputest This new test checks the specific functionality of the SPARC processor data path including m g0 register functionality m Compress Uncompress Compare command Legacy Tests These include m
13. 0 Ecache Functional on 1 Verify no branching O Verify cacheline fill on read miss 1 Testing Branching on fcc3 O0 Verify write allocate on write miss l Verify branching on O Verify cacheline update on write hit l Verify no branching O0 Verify write back 1 Ecache Functional 1 Verify cacheline fill on read miss 1 Verify write allocate on write miss 1 Verify cacheline update on write hit oa 1 Verify write back O Xcall Test 0 Sending Cross Calls to CPU AID 1 1 POST_END OBP 4 2 3 2001 04 23 17 48 Sun Netra T4 Clearing TLBs Done POST Results Cpu 700 0000 000 OOTTE 000 si C 0 f 0 0 oO Sol QQ SO Oe CO Fy oS Hh OO E o2 POST Res o0 oO OO Oo O ye Sc o Sol oO OP Oe IP OO 1 OS oOo Oo S02 gt O Orie OG O rir oO Ef gt O GG e E Oy e E Or OL So D Membase 00 Appendix E Example POST Diagnostic Output E 29 CODE EXAMPLE E 2 MemSize 0000 0000 0010 0000 Init CPU arrays Done Init ES tags Done Setup TLB Done MMUs ON Copy Done PC 0000 07ff 008 4200 PC 0000 0000 0000 4278 Decompressing Done Size 0000 0000 0007 24b0 ttya initialized Start Reason Initialize Machine Configuring the machine OBP 4 2 3 2001 04 23 17 48 Sun Netra T4 Clearing TLBs Done Loading Configuration Membase 0000 0000 0000 0000 MemSize 00
14. 1GByte 4 minutes 6 minutes 1P 2GByte 4 minutes 7 minutes 1P 512MByte 3 minutes 5 minutes The default value for diag level is min diag level Variable Set to max When the diag level variable is set to max POST enables an extended set of diagnostic level tests See TABLE 2 1 for approximate completion times CODE EXAMPLE E 1 in Appendix E provides an example of the POST output from a system with two 750MHz CPUs and 4Gbyte of memory and with the diag level variable set to max diag level Variable Set to min When the diag level variable is set to min POST enables an abbreviated set of diagnostic level tests See TABLE 2 1 for approximate completion times CODE EXAMPLE E 2 in Appendix E provides an example of the POST output from a system with two 750MHz CPUs and 4Gbyte of memory and with the diag level variable set to min Chapter 2 Power On Self Test 2 5 2 4 3 Error Messages CODE EXAMPLE 2 3 shows a sample error message at the console CODE EXAMPLE 2 3 Sample POST Console Error Message Power On Self Test Failed Cause DIMM J0406 or System Board ok CODE EXAMPLE 2 4 shows a sample error message at the serial port CODE EXAMPLE 2 4 Sample POST Serial Port Error Message ERROR TEST Memory Initial area TESTID 2 H W under test MAIN MEMORY Fault address 00000000 00000010 Fault status 00000002 0000004f CE Correctable system data ECC error CPU data bit 6 Memory data bit 146 DIMM conn
15. 30 hardware monitor 0 56 pci 8 700000 ebus 5 i2c 1 30 hardware monitor 0 54 pci 8 700000 ebus 5 i2c 1 30 hardware monitor 0 52 pci 8 700000 ebus 5 i2c 1 30 icexp 0 4c pci 8 700000 ebus 5 i2c 1 30 fan control 0 4e pci 8 700000 ebus 5 i2c 1 30 lomlite2 0 ae pci 8 700000 ebus 5 i2c 1 30 power supply 0 ac pci 8 700000 ebus 5 i2c 1 30 scc reader 0 a6 pci 8 700000 ebus 5 i2c 1 30 fcal backplane 0 a4 pci 8 700000 ebus 5 i2c 1 30 icexp 0 7a pci 8 700000 ebus 5 i2c 1 30 icexp 0 72 pci 8 700000 ebus 5 i2c 1 30 motherboard fru 0 a8 pci 8 700000 ebus 5 i2c 1 30 fan control 0 48 pci 8 700000 ebus 5 i2c 1 30 temperature 0 98 pci 8 700000 ebus 5 i2c 1 30 cpu fru 0 a2 pci 8 700000 ebus 5 i2c 1 30 temperature 0 30 pci 8 700000 ebus 5 i2c 1 30 cpu fru 0 ad pci 8 700000 ebus 5 i2c 1 2e dimm fru l ae pci 8 700000 ebus 5 i2c 1 2e dimm fru l ac pci 8 700000 ebus 5 i2c 1 2e dimm fru l aa pci 8 700000 ebus 5 i2c 1 2e dimm fru l1 a8 pci 8 700000 ebus 5 i2c 1 2e dimm fru l1 a6 pci 8 700000 ebus 5 i2c 1 2e dimm fru l1 a4 pci 8 700000 ebus 5 i2c 1 2e dimm fru l1 a2 pci 8 700000 ebus 5 i2c 1 2e dimm fru l1 a0 ok Netra T4 AC100 DC100 Service and System Reference Manual August 2001 TABLE 4 7 shows the child node names When accessing a child device from the parent node you must identify the child node name PCI device number and PCI function number TABLE 4 7 Child Node Names Description Chil
16. At the OBP ok prompt type ok reset all ok probe scsi all If the DVD ROM drive responds correctly to probe scsi all the message identified in CODE EXAMPLE 4 2 is displayed the system SCSI controller has successfully probed the device This is an indication that the motherboard is operating correctly If the drive does not respond to the SCSI controller probe replace the unresponsive drive 4 4 AN AN A Power Supply Unit Troubleshooting Caution During the power supply voltage measurement checks an operational load must be on the power supply Ensure that the power supply cables remain connected to the motherboard The section describes how to use a digital volt meter DVM to test the power supply under operational load See the figures and tables in this section to identify the J3601 and J3603 power connectors Power off the system and remove the top access panel See Chapter 5 for details Caution Use proper ESD grounding techniques when handling components Wear an antistatic wrist strap and use an ESD protected mat Store ESD sensitive components in antistatic bags before placing them on any surface See Section 5 5 Antistatic Precautions on page 5 5 Caution Hazardous voltages are present To reduce the risk of electrical shock and danger to personal health follow the instructions Check the continuity of the power cables between the PDB and motherboard Ensure that th
17. PCI I O Rack mounting options Front to back cooling AC and DC power supply options Alarms functionality for remote management System configuration card Hot swap disk drives Visual diagnostics Environmental monitoring 1 1 System Features System unit components are housed in a 4RU rack mounting enclosure designed to NEBS Level 3 standards Overall chassis dimension width x depth x height are 445 2mm x 508 1mm x 176 6mm 17 52in x 20 00in x 6 95in Flange mounting kits are available for installing the system in 19 inch 23 inch 24 inch and 600 mm racks see FIGURE 2 1 A slide adaptor kit is also available 4 x 7 a i i 5 B D N KR lt r St A 9 T 0 a re 5 oO a oo te te 19 OQ g a o te A Te oO re y Y Y ESE Y Y Y Y 445 2 le DIMENSION A 19 in FLANGES 23 in FLANGES 24 in FLANGES 600mm FLANGES A 2 o g N ps o Y 5 5 3 DIMENSION A 470 4 re gt FIGURE 1 1 Netra T4 System Dimensions and Mounting Options dimensions in mm 1 2 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 System unit electronics are contained on a single printed circuit board motherboard The motherboard contains the CPU modules memory s
18. Slide adaptor B 1 B 2 B 2 1 B 2 1 1 B 2 1 2 Electrical Specification Netra T4 AC100 System Operating Voltage and Frequency TABLE B 1 AC Power Supply Input Requirements Minimum Maximum Voltage 90 Vims 264 Vims Frequency 47 Hz 63Hz Current Inrush The maximum inrush current is 25 Apeak upon start up or restart after power has been removed for 60s or longer Circuit breakers must not be tripped by an inrush current of 25A lasting 200ms Operating The maximum normal input line current is less than 7 2A at 100 VAC under standard test conditions Power Off Mode The maximum input power of the system in power off or remote off state is less than 30VA B 2 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 B 2 1 3 D22 B 2 2 1 B 2 2 2 Overcurrent Protection The AC outlet socket should be protected by a 15A double pole double throw circuit breaker Netra T4 DC100 System DC Input TABLE 12 1 DC Power Supply Input Requirements Electrical Element Requirement Voltage 48VDC 60VDC Max operating current 12A 48VDC 10A 60VDC Max inrush current 30A 48VDC 24A 60VDC 1 The DC power supply range is 40VDC to 75VDC Source Site Requirements The DC source must be a 48 VDC or 60 VDC nominal centralized DC power system m Electrically isolated from any AC power source m Reliably connected to earth that is the battery room
19. Verify Verify S1 Verify SI Verify S17 A aA O Tick amp A aA O Stick amp a a diag level Variable Set to min 3 of 15 O Verify interrupt occurs for each level 1 Walk 1 0 TICK Compare register O Verify interrupt occurs at the right PIL TICK register Overflow TICK Interrupt 1 Stick amp Stick Compare Reg 1 Walk 1 0 STICK Compare register 1 Verify STICK register is counting Measure CPU Clock AFT pin is high Setup Memory Con IMMU Registers 1 IMMU Registers N rates Testing I 1 TSB 1 Verify interrupt occurs at the right PIL 1 Tick amp Tick Compare Reg 1 Verify TICK register is counting ick Compare Reg 1 Verify TICK register Overflow O Walk 1 0 TICK Compare register 1 Verify TICK Interrupt TICK register is counting Stick Compare Reg 1 Verify STICK register Overflow Walk 1 0 STICK Compare register 1 Verify STICK Interrupt TICK TICK TICK register is counting register Overflow Interrupt 1 Measure CPU Clock troller Testing I TSB Test walking 1 t 1 Test walking 0 t 1 Testing I TLB Tag Access 1 Test walking 1 through the register 1 Test walking 0 through the register 1 hrough the register Test walking 1 through the register hrough the register Test walking 0 through the register Testing I TLB Tag Access Test walking 1 throu
20. a 64bit 66MHz PCI bus Electrostatic discharge A type of local area network that enables real time communication between network devices connected directly together through cables A widely implemented network from which the IEEE 802 3 standard for contention networks was developed Ethernet uses a bus topology configuration and relies on the form of access known as CSMA CD to regulate traffic on the main communication line Network nodes are connected by coaxial cable in either of two varieties or by twisted pair wiring See also 10BASE T and 100BASE T Fiber channel arbitrated loop First in first out A type of programmable read only memory PROM that can be reprogrammed by a voltage pulse See also PROM Field replaceable unit Gigabyte 10 bytes Graphical user interface High speed serial interface Input output An interface from the Boot Bus Controller that enables testing of the ASICs on the motherboard Kilobyte 10 bytes Any node location in a tree structure that is farthest from the primary node Light emitting diode Lights Out Management Megabyte per second Megabit per second Megabyte one million bytes Megahertz Media independent interface Netra T4 AC100 DC100 Service and System Reference Manual August 2001 Network NG DIMM Node ns NVRAM OBP PBM PCI bus PCIO PDB Peripheral assembly PID POR POST PROM PSU QFE RAID RMM A configuration of data processing
21. diag level Variable Set to max 6 of 17 TAG est address up est address down disturbance reliability est address line transitions 1 Test address line transitions TAG 1 4M ITLB TAG est address up 1 est address down 1 est address line transitions 1 0 IMMU Init 1 Test data reliability Test address up Test address down Test cell disturbance rest address line transitions O Mapping done MMU enabled 1 8K ITLB TAG Memory address selection Initial area E Cache E Cache a AN NN RS Test address up Test address down Test address line transitions 1 IMMU Init 1 DMMU Init 1 Mapping done MMU enabled 1 Memory address selection Initial area emory marching Initial area 1 Memory marching Initial area Global Vars Init Quick Verification 1 E Cache Global Vars Init 1 E Cache Quick Verification Ecache an Test cell AGS Test address up 1 Ecache TAGS 1 Test address down 1 Test address up Test address down disturbance 1 Test cell disturbance E 6 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 CODE EXAMPLE E 1 O QO O ett Test address diag level Variable Set to max 7 of 17 Test data reliability l Test data reliability line transitions 1 Test address line transi
22. on page 10 32 10 2 8 Peripherals The following peripherals are supported by the Netra T4 system m Section 10 2 8 1 DVD ROM and DAT Drives on page 10 24 m Section 10 2 8 2 Hard Drives on page 10 24 m Section 10 2 8 3 System Configuration Card Reader on page 10 25 10 2 8 1 DVD ROM and DAT Drives The DVD ROM and back up devices tape drive are interfaced through a SCSI controller The Netra T4 system uses a SCSI host controller on the PCI bus This controller is used only in fast narrow mode Note The DVD ROM drive is factory set to SCSI target ID 6 Refer to the installation documentation for the DVD ROM to change the target ID address 10 2 8 2 Hard Drives The system supports two internal hot swap FC AL hard drives Each hard drive has a single connector configuration A drive bracket is used to mount the drives The following table lists the features of the Netra T4 hard drives TABLE 10 3 Internal Hard Drive Features Form Factor Seek Time read write Dimension Hard Drive Capacity RPM average 1 0 inch 36GBytes 10K 7 5 ms 8 5 ms 2 54 cm 10 24 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 10 2 8 3 10 2 9 10 2 10 System Configuration Card Reader The SCCR is attached to the I2C bus This is a system identity device comprising a card reader and a programmed system configuration card The card has two functions m It contains the system identity param
23. on page 5 9 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 pant Il System Reference CHAPTER 10 Functional Description This chapter provides functional descriptions for the following 10 1 Section 10 2 System Overview on page 10 2 Section 10 3 Power Supply on page 10 36 Section 10 4 Motherboard on page 10 37 Section 10 5 Jumper Descriptions on page 10 40 System This section is organized into the following subsections Section 10 2 System Overview on page 10 2 Section 10 2 1 UltraSPARC III Processor on page 10 3 Section 10 2 2 Main Memory on page 10 6 Section 10 2 3 I O Subsystem on page 10 11 Section 10 2 4 Interrupts on page 10 16 Section 10 2 5 BootBus on page 10 17 Section 10 2 7 PCI Bus on page 10 22 Section 10 2 8 Peripherals on page 10 24 Section 10 2 9 Other Peripheral Assembly Options on page 10 25 Section 10 2 10 USB Ports on page 10 25 Section 10 2 11 Parallel Port on page 10 26 Section 10 2 12 Serial Port on page 10 27 Section 10 2 13 Ethernet on page 10 31 Section 10 2 14 FC AL Subsystem on page 10 32 Section 10 2 15 SCSI on page 10 33 Section 10 2 16 Superl O on page 10 35 10 1 10 2 System Overview The Netra T4 AC100 is available as a single or dual UltraSPARC III processor controlled server system The Netra T4 uses sh
24. 0 Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Acknowledge active LOW Busy active HIGH Paper End active HIGH Select active LOW Auto Line Feed active LOW Error active LOW Initialize Printer prime active LOW Select Input active LOW Ground Ground Ground Ground Netra T4 AC100 DC100 Service and System Reference Manual August 2001 TABLE 11 1 Parallel Connector Pinout Continued Pin Signal Name 1 0 Service 22 GND Ground 23 GND Ground 24 GND Ground 25 GND Ground 11 2 Serial Connectors 1300000000000001 2500000000000014 1300000000000001 2500000000000014 FIGURE 11 3 DB 25 Serial Connectors TABLE 11 2 Serial Connector Pinout RS423 RS232 Pin Function 1 0 Signal Description 1 Not connected 2 TxD O Transmit Data 3 RxD I Receive Data 4 RTS O Ready To Send 5 CTS I Clear To Send 6 DSR I Data Set Ready 7 Gnd Signal Ground 8 DCD I Data Carrier Detect 9 14 Not connected 15 TRxC I Transmit Clock 16 Not connected 17 RTxC I Receive Clock Chapter 11 External I O Connectors 11 3 TABLE 11 2 Serial Connector Pinout RS423 RS232 Continued Pin Function 1 0 Signal Description 18 19 Not connected 20 DTR O Data Terminal Ready 21 23 Not connected 24 TxC O Transmit Clock 25 Not connected Note For information about serial port jumpers on the Netra T4 system main logic board see the Netra T4 System Reference Manual 1
25. 0 0 0 Hit any key to return to the main menu 4 24 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 4 5 4 4 4 5 4 5 4 5 4 6 SUNW qlc 4 The following code example shows the QLC test output CODE EXAMPLE 4 12 SUNW qlc 4 Diagnostic Output Message obdiag gt test 2 Hit the spacebar to interrupt testing Testing pci 8 600000 SUNW qlc 4 OS agg daca ieee es SY aaa teenie E E ia E nate a passed Pass 1 of 1 Errors 0 of 0 Tests Failed 0 Elapsed Time 0 0 0 0 Hit any key to return to the main menu bbc 1 0 The following code example shows the bbc 1 0 output message CODE EXAMPLE 4 13 bbc 1 0 Diagnostic Output Message obdiag gt test 3 Hit the spacebar to interrupt testing Testing pci 8 700000 ebus 5 bbc 1 0 PaE ete cactatg ter a E a ah eden in igite ten sees te passed Pass l1 of 1 Errors 0 of 0 Tests Failed 0 Elapsed Time 0 0 0 0 Hit any key to return to the main menu ebus 5 The following code example shows the ebus output message CODE EXAMPLE 4 14 ebus 5 Diagnostic Output Message obdiag gt test 4 Hit the spacebar to interrupt testing Testing pci 8 700000 ebus 5 EEE TIE E wade E E E E laters Vie E weds cal wegen passed Pass 1 of 1 Errors 0 of 0 Tests Failed 0 Elapsed Time 0 0 0 2 Hit any key to return to the main menu Chapter 4 Troubleshooting 4 25 4 5 4 7 flashprom 0 0 The following code example sh
26. 1 2 Device 3 4 Device fan control ioexp fan control 40 96 MB ioexp ioexp fcal backplane scc reader nvram idprom beep rtc gpio pmc parallel 4 Way SUNW qlc fp disk Not hing t network u scsi disk hing t hing t hing t hing t here sb tape scsi disk tape here here here nere Appendix E Example POST Diagnostic Output E 31 E 32 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 APPENDIX F Updating LOMlite2 Firmware This appendix explains how to update the Lights Out Management firmware 1 Connect a terminal to the LOMlite2 serial port as described in Appendix D of the Netra T4 AC100 DC100 Installation and User s Guide Power up the system and boot to the Unix prompt 2 Change to the var tmp directory This directory should contain the current patch in the example 110208 09 cd var tmp 1s 110208 09 110208 09 tar Note Your version number will probably be different 3 Remove the tar file and the directory and its contents rm 110208 09 tar rm r 110208 09 4 Remove the existing patch patchrm 110208 09 Checking installed patches Executing prebackout script prebackout Starting removing driver prebackout Finished Backing out patch 110208 09 Patch 110208 09 has been backed out 5 Reboot the system 6 Copy the new patch into the var tmp directory Fro
27. 1 or 2 and 3 You can download the quadrants from a standalone utility bootable DVD ROM or from the network The updates are available in binary or UNIX shell formats During a flash PROM update the OBP firmware overwrites the upper half of PROM where POST resides keeping the original OBP unchanged After the new OBP is tested successfully the original OBP is overwritten with the new OBP Finally after the OBP is tested again POST is reloaded into the upper half of PROM OBP Prompt On dual processor systems the OBP prompt includes the CPU number 0 ok Resets When the system is first powered up the configuration is determined using information stored in the motherboard and CPU EEPROMS CPU speed memory configuration and so forth and is saved in the BootBus Controller BBC SRAM This is termed a Configuration Reset Subsequent system power cycles generate a configuration reset A Soft Reset occurs on subsequent system resets which uses the BBC s SRAM configuration information To avoid booting with corrupted configuration information a checksum is performed on the data If the data is found to be corrupt the subsequent reset reverts to a configuration reset Chapter 4 Troubleshooting 4 9 4 5 2 4 5 2 1 New and Modified Commands and Tests The probe and test commands have been modified to include FC AL and USB keyboard and mouse respectively TABLE 4 4 probe and test Commands Command New Features
28. 10 PSU Status LEDs Netra T4 DC100 System 1 11 SunVTS Menu Bar 3 5 Power Supply Connector Jack Location 4 6 Netra T4 System Device Tree 4 14 System Power On STBY Front Panel 5 3 Attaching the Antistatic Wrist Strap to the Rear of the Chassis 5 6 Attaching the Antistatic Wrist Strap to the Front of the Chassis 5 7 Top Access Cover 5 8 Front Fascia and Filters 5 10 Power Supply Unit 6 2 Power Distribution Board 6 4 System Switch and LED Assembly 6 9 Netra T4 System Fans 7 2 PSU Fans Assembly 7 3 CPU Fan 7 6 1 2 xi xii n GURE 7 4 mn GURE 8 1 n GURE 8 2 mn GURE 8 3 n GURE 9 1 mn GURE 9 2 nm GURE 9 3 n GURE 9 4 n GURE 9 5 n GURE 9 6 n GURE 9 7 mn GURE 9 8 mn GURE 9 9 mn GURE 9 10 n GURE 9 11 n GURE 10 1 n GURE 10 2 al GURE 10 3 n GURE 10 4 n GURE 10 5 nm GURE 10 6 al GURE 10 7 mn GURE 10 8 n GURE 10 9 n GURE 10 10 mn GURE 10 11 nm GURE 10 12 n GURE 10 13 Fan Connectors 7 8 FC AL Disk Drive and Drive Bay Assembly 8 2 FC AL Backplane and Drive Bay Assembly 8 7 Removable Media Modules 8 10 PCI Card Slots 9 2 CPU Modules 9 5 Using the Torque Tool 9 8 Memory Modules 9 10 Memory Banks 9 12 Battery Location 9 13 LOMlite2 Card 9 14 System Configuration Card Reader 9 16 Motherboard Layout 9 19 Motherboard Fixing Screws 9 21 Removing the Motherboar
29. 10 42 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 CHAPTER 1 1 External I O Connectors This chapter provides information about the external I O connectors FIGURE 11 1 shows the locations of the Netra T4 system back panel connectors SCCR Parallel Ground USB Wrist Strap Attachment Alarms Port LOMlite2 LEDs on sem iaaa NO O See re Il OC Se Sh g g j EEE e E EE COO Ca v aon S 9200000799999 B l i i wa F i CT Psa ooo CGicss Ss Tc ee ee TTT gt SCSI Ethernet FC AL PCI Slot LOMlite2 Appliance PCI Slot short Serial Inlet long PSU SerialB Serial A LEDs FIGURE 11 1 Back Panel Connectors AC100 Shown 11 1 Parallel Connector 11 2 1300000000000001 2500000000000014 FIGURE 11 2 DB 25 Parallel Connector TABLE 11 1 Parallel Connector Pinout Pin Signal Name vO 1 DATA_STROBE_L 2 DAT 0 3 DAT 1 4 DAT 2 5 DAT 3 6 DAT 4 7 DAT 5 8 DAT 6 9 DAT 7 10 ACK_L 11 BSY 12 PERROR 13 SELECT_L 14 AFXN_L 15 ERROR_L 16 RESET_L 17 IN_L 18 GND 19 GND 20 GND 21 GND Service Data Strobe active LOW Data Bit
30. Cache Test cell D Cache Test cell D Cache a5 1 1 Testing I Cache Micro Tag 1 1 1 1 diag level Variable Set to min 7 of 15 Test address down disturbance Test cell disturbance Test address up 1 1 Test address down 1 Test address up Test address down disturbance Test cell disturbance Snoop Tags Test address up 1 I Cache Snoop Tags 1 Test address down 1 Test address up Test address down disturbance Test cell disturbance Init 1 I Cache Init RAM Test address up 1 D Cache RAM 1 Test address down 1 Test address up Test address down disturbance Test cell disturbance TAGS Test address up 1 D Cache TAGS 1 Test address down 1 Test address up Test address down disturbance Test cell disturbance MicroTags Test address up 1 D Cache MicroTags 1 Test address down Test address up 1 Test address down Appendix E Example POST Diagnostic Output Testing I Cache Micro Tag E 23 CODE EXAMPLE E 2 diag level Variable Set to min 8 of 15 O Test cell disturbance on 1 Test cell disturbance D Cache SnoopTags or eS Test address up 1 D Cache SnoopTags l Test address up Test address down oa oO yw l Test address down O Test cell disturbance 1 Test cell disturbance 0 D Cache Ini
31. D O a CO S O S O DMMU Registers A 1 Verify TICK register is counting O Tick amp Tick Compare Reg a 1 Verify TICK register Overflow O Walk 1 0 TICK Compare register 1 Verify TICK Interrupt Verify TICK register is counting Verify TICK register Overflow Verify TICK Interrupt 1 Stick amp Stick Compare Reg 1 Walk 1 0 STICK Compare register 1 Verify STICK register is counting m O Stick amp Stick Compare Reg 1 Verify STICK register Overflow Walk 1 0 STICK Compare register 1 Verify STICK Interrupt Verify STICK register is counting A Verify STICK register Overflow Verify STICK Interrupt 1 Measure CPU Clock Measure CPU Clock AFT pin is high Setup Memory Controller IMMU Registers 1 IMMU Registers Testing I TSB l Testing I TSB Test walking 1 through the register 1 Test walking 1 through the register ena Test walking 0 through the register l Test walking 0 through the register Testing I TLB Tag Access 1 Testing I TLB Tag Access N Test walking 1 through the register 1 Test walking 1 through the register Test walking 0 through the register 1 Test walking 0 through the register 1 DMMU Registers Testing Primary Context l Testing Primary Context ae Test walking 1 through the register 1 Test walking 1 through the register ew Testing Secondar
32. Devices Bus Length SCSI 2 Fast 8 bits 10 1 8 6 0m SCSI 2 Fast Wide 16 bits 20 1 8 6 0m SCSI 3 Parallel Interface Fast 20 Wide 16 bits 40 1 4 3 0m UltraSCSI WideUltra SCSI 3 Parallel Interface Fast 20 Wide 16 bits 40 5 8 1 5m UltraSCSI WideUltra 1 The maximum number of single ended differential SCSI devices is 16 3 Verify the cable type used to connect external SCSI devices You must use Fast 20 SCSI cable s Ensure that the total SCSI cable length does not exceed the permissible total SCSI bus length SCSI 2 Fast Wide SCSI External Devices If you connect SCSI 2 Fast Wide SCSI 20Mb data transfer rate external devices to a Netra t 1400 1405 system follow these cabling and configuration guidelines as shown in FIGURE 11 5 to ensure proper device addressing and operation a If all external mass storage devices use 68 pin connectors connect all non Sun devices to the Netra T4 system first and follow them with Sun devices Sun devices use auto termination a If external mass storage devices consist of 68 pin Sun devices and 50 pin devices connect the Sun 68 pin devices to the Netra T4 system first and terminate the daisy chain with the 50 pin device and its terminator a The total SCSI bus length for all external SCSI devices is 6 0m 19 7ft including the internal cabling Chapter 11 External I O Connectors 11 7 Non Sun device Sun device Sun device roH Oma EOE o Emm o
33. Hard Disk Drive on page 8 1 m Section 8 2 Fiber Channel Backplane and Drive Bay on page 8 6 m Section 8 3 Removable Media Module on page 8 10 Caution The plug at the end of the AC power cord is the primary means of disconnection for the Netra T4 AC100 system 8 1 FC AL Hard Disk Drive The following procedure is concerned with the physical removal and replacement of a hard disk drive as Anon hot swap device a A hot swap device From an operational point of view whether a disk can be considered to be a hot swap device and can be removed without shutting down Solaris depends on how the disk drives are configured in the operating environment The disk is a hot swap device if m The disk is not a root disk or if both of the following statements are true m The disk is a root disk m The disk is mirrored or RAID 5 protected 8 1 In other words if the disk is a root disk and is not mirrored you must treat it as a non hot swap device O o o Ag GEETE H SESS See eee EEE EEE BEN BE RE RIES a SL EEE IEEE DILLEY S ERR ERRE LER RRT E RER EEE ESSE SEES EPERE EERE PERBERES RERET ECE FC AL Disk Drive and Drive Bay Assembly FIGURE 8 1 isk Drive Hot Swap Preparing to Remove a D 8 1 1 Before proceeding to remove a hard disk drive carry out the following 1 Lower the front fascia See Section 5 7 1
34. J3601 Pin Description D 7 LOM Serial Port Adaptor Pinouts G 1 Netra T4 Serial Port Crossover Adaptor Pinouts G 2 Tables xvii xviii Netra T4 AC100 DC100 Service and System Reference Manual August 2001 CODE EXAMP CODE EXAMP CODE EXAMP CODE EXAMP CODE EXAMP CODE EXAMP CODE EXAMP CODE EXAMP CODE EXAMP CODE EXAMP CODE EXAMP CODE EXAMP CODE EXAMP CODE EXAMP CODE EXAMP CODE EXAMP CODE EXAMP CODE EXAMP CODE EXAMP LE 2 1 LE 2 2 LE 2 3 LE 2 4 LE 4 1 LE 4 2 LE 4 3 LE 4 4 LE 4 5 LE 4 6 LE 4 7 LE 4 8 LE 4 9 LE 4 10 LE 4 11 LE 4 12 LE 4 13 LE 4 14 LE 4 15 Code Samples POST Test Menu 2 2 POST Test Control Flags Menu 2 3 Sample POST Console Error Message 2 6 Sample POST Serial Port Error Message 2 6 probe scsi Diagnostic Output Message 4 10 probe scsi all Output Message 4 11 Test Output Message 4 11 Watch Clock Diagnostic Output Message 4 12 watch net Diagnostic Output Message 4 13 watch net all Diagnostic Output Message 4 13 66MHz PCI Bus Devices 4 15 33MHz PCI Bus Devices 4 15 Typical reset all Screen Output 4 22 obdiag Menu 4 23 SUNW lomv 0 0 Diagnostic Output Message 4 24 SUNW qlc 4 Diagnostic Output Message 4 25 bbc 1 0 Diagnostic Output Message 4 25 ebus 5 Diagnostic Output Message 4 25 flashprom 0 0 Diagnostic Output Message 4 26 xix CODE EXAMPLE 4 16 CODE EXAMPLE 4 17 CODE EXAMPLE 4 18 CODE EXAMPLE 4 19 COD
35. Memory Access DVMA mode See Section 10 2 7 PCI Bus on page 10 22 for details PCI B Leaf Block The term PCI refers to the 33 MHz PCI bus PCI specification revision 2 1 The PCI B leaf is the host controller for the 64 bit wide 33 MHz PCI bus It supports both 5V and 3 3V signalling and 32 bit devices The PCI B leaf supports six master devices The Netra T4 system includes only five devices PCIO 2 three slots and the 876 SCSI controller Peripheral Component IO The Peripheral Component IO PCIO 2 contains a multi function PCI interface and three leaves for each of the supported interfaces Ethernet 10 100 Mbit USB and EBus the 1394 leaf is not used FIGURE 10 8 is a block diagram of the PCIO 2 ASIC Chapter 10 Functional Description 10 13 f PCI Bus Bus Adaptor A 64 bit PCI bus rev 2 1 compliant Configuration 33 MHz Space Double write buffers Multi function Ethernet channel 1394 channel USB channel EBus channel MISC Enet DMA USB DMA EBus DMA 2 DMA Not used 1 DMA 4 DMA channels channel channels JTAG m eet N S e USB Bist GEM Control EBus control 10 100 Not used Hub 5 Mbit sec Mbit sec 12 Mbit sec Ethernet PHY USB Ethernet 10 100 BASE T FIGURE 10 8 PCIO 2 Block Diagram PCI Interface The PCI B interface is 64 bit wide at 33MHz It supports slave for PIO and master for DMA transa
36. O O POO O O O O Oy FIGURE D 3 Power Supply Connector J3603 TABLE D 5 Power Supply Connector J3603 Pin Description Pin Signal Description 1 POWERON_L Power on 2 12 VDC 12 VDC 3 5 VDC Return SENSE 5 VDC Return 4 3 3 VDC Return SENSE 3 3 VDC Return 5 RETURN Return 6 RETURN Return 7 Spare Spare 8 POWER_OK Power OK 9 PS_FAN Fan power 10 5 VDC SENSE 5 VDC Sense 11 3 3 VDC SENSE 3 3 VDC Sense 12 12 VDC 12 VDC 13 12 VDC 12 VDC 14 5 VDC_STBY 5 VDC standby Netra T4 AC100 DC100 Service and System Reference Manual August 2001 14 FIGURE D 4 Power Supply Connector J3601 TABLE D 6 Power Supply Connector J3601 Pin Description Pin Signal Description J 3 3 VDC 3 3 VDC 2 3 3 VDC 3 3 VDC 3 3 3 VDC 3 3 VDC 4 3 3 VDC 3 3 VDC 5 5VDC 5 VDC 6 5 VDC 5 VDC 7 5 VDC 5 VDC 8 RETURN 3 3 VDC 3 3 VDC Return 9 RETURN 3 3VDC 3 3 VDC Return 10 RETURN 3 3 VDC 3 3 VDC Return 11 RETURN 3 3 VDC 3 3 VDC Return 12 RETURN 5VDC 5VDC Return 13 RETURN 5VDC 5VDC Return 14 RETURN 5VDC 5VDC Return Appendix D Motherboard Connectors D 7 D 8 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 APPENDIX E Example POST Diagnostic Outp
37. TX_N 3 Transmit DataTX_N 7 GND 4 NC 8 Receive Data TX_P Chapter 11 External I O Connectors 11 9 11 6 USB Connectors 11 10 Four USB connectors two twin Series A are located between the SCSI port and FC AL port Eue a o l Ee a o l 1 2 3 4 1 2 3 4 oma a 1 2 3 4 1 2 3 4 C A ES FIGURE 11 8 Twin Series A USB Connector TABLE 11 8 USB Connector Pinout Pin Description Pin Description Al USBO_VCC 5VDC C1 USB2_VCC 5VDC A2 Port0Data C2 Port2Data A3 Port0Data C3 Port2Data A4 GND C4 GND B1 USB1_VCC 5VDC D1 USB3_VCC 5VDC B2 Port1Data D2 Port3Data B3 Port1Data D3 Port3Data B4 GND D4 GND Netra T4 AC100 DC100 Service and System Reference Manual August 2001 11 7 Alarms Ports The alarms service port connector male DB 15 and LOM port connector RJ45 are located on the alarms card TABLE 11 9 lists the pinouts for the alarms service port connector 8 000000001 9 COO0000 15 FIGURE 11 9 DB 15 Male Alarms Service Port Connector TABLE 11 9 Alarms Service Port Connector Pinout Pin Signal Name Pin Signal Name 1 Not connected 9 ALARM1_NC 2 Not connected 10 ALARM1_COM 3 Not connected 11 ALARM2_NO 4 Not connected 12 ALARM2_NC 5 SYSTEM_NO 13 ALARM2_COM 6 SYSTEM_NC 14 Not connected 7 SYSTEM_COM 15 Not connected 8 ALARM1_NO Shell CHGND The remote Lights Out Management serial port is located below the alarms port The connector is a shielded RJ45 and TABLE 11 10
38. The systems main memory delivers an entire block of information on external cache in a single memory bus cycle This delivery method provides up to 2 4Gbps of sustainable bandwidth 10 6 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 The main memory is implemented with x144 DIMMs also referred to as NG DIMMs Next Generation Dual Inline Memory Modules The system supports up to eight installed NG DIMMs Note The memory bus is clocked at half the system frequency through a clock connected directly to the CPU module The DIMMs also support a SEEPROM for identifying and configuring subsystem memory The CPU module memory controller performs reads and writes in blocks of 64 bytes On non cacheable reads the extraneous data is dropped On non cacheable write the processor must perform a read modify write The memory space is cached The memory subsystem supports 2 and 4 way logical interleaving The unit of interleaving is a logical bank A group of four DIMMs corresponds to two logical banks for interleaving purposes The interleaving is based on multiples of 64 bytes Main memory interleaving is described in more details in Section 10 2 2 3 Interleaving on page 10 10 Chapter 10 Functional Description 10 7 Addr ADDR LE_L 1 0 DIMM 15 0 Addr 15 0 Addr 15 0 WE 1 0 LE_L 1 0 144 bit data piil ADDR CPMS 10 8 CAS 1 0 Addr 1510 i RASO_L cpu pesu ge R
39. To change the speed of a serial port you must edit the etc remote file as follows Become super user and type cd etc ae su Password cd etc Type vi remote Type tip speed device name Typical speeds are 9600 19200 to 38400 bps The device name is the serial port name for example dev tty a b or dev term a b Press lt Esc gt and type wq to save your file change s and to exit from the vi text editor 123 Recommendations For a modem to host system connection use an RS423 RS232 straight through cable with DB 25 male connectors at both ends 12 2 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 APPENDIX A Illustrated Parts List This appendix lists the authorized replaceable parts for the Netra T4 system unit FIGURE A 1 is an exploded view of the system unit with numerical references that correlate to the replaceable components listed in TABLE A 1 and TABLE A 2 A brief description of each listed component is also given and where appropriate a reference to the section in this manual containing the replacement procedure The part numbers listed in TABLE A 1 and TABLE A 2 were correct at the time of publication of this manual but are subject to change without notice Consult your authorized Sun sales representative or service provider to confirm a part number before ordering the replacement part A 2 FIGURE A 1 Exploded View of t
40. and Sun Graphical User Interface was developed by Sun Microsystems Inc for its users and licensees Sun acknowledges the pioneering efforts of Xerox in researching and developing the concept of visual or graphical user interfaces for the computer industry Sun holds a non exclusive license from Xerox to the Xerox Graphical User Interface which license also covers Sun s licensees who implement OPEN LOOK GUIs and otherwise comply with Sun s written license agreements Federal Acquisitions Commercial Software Government Users Subject to Standard License Terms and Conditions DOCUMENTATION IS PROVIDED AS IS AND ALL EXPRESS OR IMPLIED CONDITIONS REPRESENTATIONS AND WARRANTIES INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT ARE DISCLAIMED EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD TO BE LEGALLY INVALID Copyright 2001 Sun Microsystems Inc 901 San Antonio Road Palo Alto CA 94303 4900 Etats Unis Tous droits r serv s Ce produit ou document est distribu avec des licences qui en restreignent l utilisation la copie la distribution et la d compilation Aucune partie de ce produit ou document ne peut tre reproduite sous aucune forme par quelque moyen que ce soit sans l autorisation pr alable et crite de Sun et de ses bailleurs de licence s il y en a Le logiciel d tenu par des tiers et qui comprend la technologie relative aux polices de caract res est p
41. and reader to overwrite the EEPROM contents with the original motherboard s identification parameters The I2C bus is also used to monitor CPU die temperatures through sensors in each CPU chip and on the processor board The I2C bus monitors the fan speed using LM80s on the PDB and power supply status Chapter 10 Functional Description 10 21 10 2 7 10 2 7 1 The I2C multimaster bus interfaces with the following devices m System configuration card reader SCCR a FC AL backplane m Power distribution board PDB m Lights Out Management board a LED and switch board a Power Supply Unit The I2C bus supports a Lights Out Management LOMlite2 board through the I2C connector to the PDB The LOMlite 2 board is a remote support feature that provides remote monitoring and system administration The LOMlite2 board is powered by a 5V standby supply that enables the board to remain powered after the host has shut down PCI Bus The peripheral component interconnect PCI bus is a 32 bit or 64 bit bus with multiplexed address and data lines The PCI bus provides electrical interconnect between highly integrated peripheral controller components peripheral add on devices and the processor memory system There are two PCI buses in the Netra T4 system m One slot 3 3VDC 64 bit or 32 bit 66MHz or 33MHz bus a Three slot 5 0VDC 64 bit or 32 bit 33 MHz bus Both buses are controlled by the SBC ASIC There are two on board PCI de
42. and system configuration card See Section 9 6 3 Installing the SCCR on page 9 17 Fit any memory modules to be installed See Section 9 3 3 Installing a Memory Module on page 9 11 Reconnect the power interlock cable to J3602 on the motherboard Reconnect the FC AL data cable to J2901 on the motherboard Reconnect the SCSI data cable to J5002 on the motherboard Reconnect the RMM power cable to J3608 on the motherboard Reconnect the power cable to J3603 on the motherboard Reconnect the power cable to J3601 on the motherboard Reconnect the power cable to J3303 on the motherboard Reconnect the power cable to J3302 on the motherboard Refit the CPU module s See Section 9 2 3 Installing a CPU Module on page 9 7 Refit the LOMlite2 card See Section 9 5 3 Installing the LOMlite2 Card on page 9 15 Refit the PCI card s See Section 9 1 3 Installing a PCI Card on page 9 3 Chapter 9 Motherboard and Component Replacement 9 23 9 24 19 20 21 22 Refit the CPU fan assembly See Section 7 2 3 Installing the CPU Fan Assembly on page 7 7 If necessary refit the FC AL drive assembly See Section 8 2 3 Installing the FC AL Backplane and Drive Bay on page 8 9 If necessary refit the RMM drive assembly See Section 8 3 3 Installing a Removable Media Module on page 8 12 Refit the top access cover See Section 5 6 3 Fitting the Top Access Cover
43. coi J0405 ro 20 10404 ro cou J0403 im SCSI port coo 402 i J2202 cou T aio J0400 5002 cpu sloto 13001 J0501 J0601 SCSI ports 33002 J5301 Enet cpu slot 1 0701 J0801 Fca J2902 Battery PER e 2108 SEEPROM T gt __ 118609 2104 33 MHz PCI 4 J2601 2 LOME 213501 33 MHz PCI 3 J2501 J201 33 MHz PCI 2 J2401 33 66 MHz PCI 1 J2301 E FIGURE 4 1 Power Supply Connector Jack Location 4 6 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 TABLE 4 2 J3601 Voltage Pin Table Pin Voltage Pin Voltage 1 OV 8 5V 2 12V 9 n a 3 OV 10 5V 4 OV 11 3 3 V 5 OV 12 12V 6 OV 13 12V 7 n a 14 5V TABLE 4 3 J3603 Voltage Pin Table Pin Voltage Pin Voltage 1 3 3V 8 OV 2 3 3 V 9 OV 3 3 3 V 10 OV 4 3 3 V 11 OV 5 5V 12 OV 6 5V 13 OV 7 5V 14 OV OpenBoot PROM Diagnostics The following sections describe the OpenBoot PROM diagnostics To execute the OpenBoot PROM on board diagnostics the system must be at the ok prompt Section 4 5 1 New Features on page 4 8 Section 4 5 2 New and Modified Commands and Tests on page 4 10 Section 4 5 3 Device Tree on page 4 14 Section 4 5 4 Running the Diagnostics on page 4 18 Chapter 4 Troubleshooting 4 7 4 5 1 New Features This section summarizes the features supported in OpenBoot 4 2 that are not covered in the OpenBoot 3 x Command Reference Manu
44. confirm a part number before you order a replacement part 1 3 Environmental Performance The principal environmental requirements are given in Section B 3 Environmental Specification on page B 4 Chapter 1 System Description 1 5 1 4 LEDs The Netra T4 server has three sets of LEDs that show the status of the system 1 4 1 System LEDs The system LEDs are located behind the front fascia immediately to the right of the ON STBY switch as you face the unit as shown in FIGURE 1 2 Light pipes transmit the Power System Alarm1 Alarm2 and Fault LEDs through the fascia and are visible from the front of the system To view the remaining LEDs you must lower the front fascia vesvsrens Ovca ony gt Goce Ot p Ov OX O 09 FIGURE 1 2 Front Panel System LEDs 1 6 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 The Alarm1 Alarm2 System and Fault LEDs are mirrored on the LOMlite2 card visible from the rear of the system see Section 1 4 2 LOMlite 2 LEDs on page 1 8 TABLE 1 1 LED Power System Alarm1 Alarm2 Input A OK Input B OK Fault Disk0 Active Disk0 OK to Remove Disk0 Fault Icon Legend D SYSTEM ALARM1 ALARM2 DC A DC B Color Green Green Amber Amber Green Green Amber Green Blue Amber Front Panel System LED Functions Function Illuminate
45. connected to the loop through a hub chip The hub supports two internal connectors and the external connector Internal signal detect circuitry automatically detects the presence of a device at the external connector that enables or disables the external port The individual ports can also be bypassed manually by a software probe and programming a GPIO register in the FC AL controller TABLE 10 4 ISP2200A GPIO Bits ISP2200A GPIO Bits Drive Control Input Output Type Default Reset Value lt 0 gt External drive Output 1 lt 1 gt Internal drive 1 Output 1 lt 2 gt Internal drive 2 Output 1 lt 3 gt External port detect Input o 0 means bypass 1 means enable The FC AL host controller ASIC has a 64 bit 66 MHz PCI EPCI interface The controller contains the serializer deserializer SERDES and the transceivers on chip The host controller implements the Fiber Channel protocol through a microcoded engine The memory for the firmware is external and is implemented with synchronous 128kByte SRAM This memory also keeps the context data for outstanding I Os The figure below shows the Netra T4 disk subsystem architecture 10 32 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 10 2 15 EPCI PCI Interface ISP2200A HDMP0451 Connector FIGURE 10 16 FC AL Disk subsystem SCSI The system implements a small computer system interface SCSI for Ultra SCSI 40M
46. it away from the socket The cable is connected to J3603 on the motherboard Disconnect the I2C ribbon cable from J4 on the PDB by opening the retaining lugs at each end of the socket and pulling out the connector The I2C cable is connected to J3604 on System Configuration Card Reader SCCR board Chapter 6 Power Subassemblies 6 5 6 2 3 10 11 12 Disconnect the FC AL drive fan at J16 on the PDB Disconnect the cable at J3302 on the motherboard This cable is connected to J10 on the PDB Disconnect the cable at J3303 on the motherboard This cable is connected to J8 on the PDB Disconnect the power interlock cable at J3602 on the motherboard The power interlock cable connects to J14 on the PDB Disconnect the ON STBY switch and LED cable at J15 on the PDB by opening the retaining lugs at each end of the socket and pulling out the connector Remove the single captive Phillips screw retaining the PDB See FIGURE 6 2 Slide the PDB towards the front of the system and lift it from the chassis Place the PDB on the antistatic mat Installing the PDB Perform the steps as required listed in Section 6 2 1 Preparation on page 6 4 Locate the PDB in the chassis with the fixing screw towards the front of the system and align the cut outs in the metal shielding on the base of the PDB with the three hooks in the base of the chassis Ensure that the PSU connector and the plastic air guide on the PDB a
47. of the unit two persons are required to remove the unit from and replace it in the rack 5 2 Tools To perform the removal and fitting procedures described in Part 1 of this manual you will need the following tools Phillips No 2 screwdriver stubby Phillips No 2 screwdriver 15cm 6in Phillips No 1 screwdriver 10cm 4in 6mm 0 25 in flat blade screwdriver stubby Grounding wrist strap Anti static mat Torque tool supplied with the system and located inside the system chassis 5 3 5 3 1 System ON STBY Switch The Netra T4 system switch is a rocker momentary switch that functions as a standby device only controlling logic circuits that enable power module output Powering On the System Before powering on inspect the supply conductors for mechanical security 5 2 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 5 3 1 1 Netra T4 AC100 System 1 Plug the AC power cord into the appliance inlet on the PSU and into the mains supply 2 Set the front panel ON STBY system switch to the ON position and hold it until the system starts to power up or use the LOMlite2 poweron command or OBP poweron command ON system aarm Qatrarme2 FIGURE 5 1 System Power On STBY Front Pane
48. on page 5 9 Installing a CPU Module Perform the steps listed in Section 9 2 1 Preparation on page 9 6 as required If you have not already done so remove the purple plastic CPU shroud cover by holding the tabs to release them and lifting the cover from the chassis Identify the slot to be used Without touching the heat sink and the connectors on the base of the CPU module insert the CPU module in the CPU shroud until it touches the socket on the motherboard and the module s captive screws are aligned with the screw holes in the CPU shroud Turn both screws by hand clockwise at the same time until they are finger tight Use the torque tool to tighten each screw until the gap in the tool closes See FIGURE 9 3 The torque is now set at 5lbf in Note If you are using an adjustable torque tool tighten the CPU module screws to 5lbf in Caution Do not overtighten or subsequently retighten the screws Refit the shroud cover by sliding it back into place until the locking tags engage Return the torque tool to its storage place in the system chassis Refit the top access cover See Section 5 6 3 Fitting the Top Access Cover on page 5 9 Chapter 9 Motherboard and Component Replacement 9 7 sae AL en XO FIGURE 9 3 Using the Torque Tool Netra T4 AC100 DC100 Service and System Reference Manual August 2001 9 8 9 3 gt gt
49. or they may break 7 Press the top of the fascia forward until the catch on the fascia clicks into place on the system chassis 5 8 5 8 1 Air Filter If required you can replace the black mesh screen located behind the front fascia with the optional foam air filter and metal retainer supplied with the system see FIGURE 5 5 Clean or replace the filter regularly to maintain the airflow through the system Caution To ensure that dust is not sucked into the system when you replace the filter remove the fascia completely from the system before proceeding Removing and Fitting the Mesh Screen Detach the front fascia and place it on a workbench away from the immediate vicinity of the system See Section 5 7 1 Removing the Front Fascia on page 5 11 Press the two catches on the mesh screen and lift that side away from the fascia Carefully disengage the two tabs at the other side from the fascia and lift out the screen Take care that you do not damage the plastic locating lugs when you detach the screen Continue with Step a or Step b as required a Replace with a foam filter and retainer as described in Step 4 through Step 6 in Section 5 8 2 Replacing the Filter on page 5 13 b Continue from the following step to replace the screen 5 12 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 5 8 2 Insert the locating tabs one side of the mesh screen int
50. selection All Banks Safari registers Safari ID reg fc000000 0011a954 1 Map PCI B space 0 Map PCI A space 1 Schizo reg test Schizo reg test 1 PBM B registers PBM A registers 1 Iommu B registers on O Iommu A registers on 1 Streaming Cache B registers Streaming Cache A registers m 1 Mondo Interrupt B registers Mondo Interrupt A registers a 1 Schizo pci B id test 1 PCI B Vendor ID 108e Schizo pci A id test 1 PCI B Device ID 8001 PCI A Vendor ID 108e 1 Schizo mem test PCI A Device ID 8001 l memtst ram data port B on os on os Schizo mem test E 26 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 1 Correctable System ECC Test 1 Uncorrectable System ECC Test 1 Memory address selection All Banks CODE EXAMPLE E 2 diag level Variable Set to min 11 of 15 on a AN Ne A m T0 OG Or OS memtst ram data port A l memtst cam data port B O memtst cam data port A l memtst ram addr port B O memtst ram addr port A l memtst cam addr port B O memtst cam addr port A l memtst pnta port B O memtst pnta port A l memtst lnta port B O memtst Ilnta port A l memtst rnta port B O memtst rnta port A l memtst enta port B O memtst enta port A l memtst ln addr port B O memtst ln addr port A l memtst pg addr port B O memtst pg addr port A l memtst sbuf addr port B O mem
51. tasks concerned with the maintenance and configuration of the system How This Book Is Organized Chapter 1 provides an overview of the key features of the Netra T4 server Chapter 2 describes the Power On Self Test POST diagnostics Chapter 3 contains an overview of the SunVTS Validation Test Suite Chapter 4 describes how to troubleshoot and correct hardware problems Chapter 5 discusses the precautions you should take before working on the system and explains how to gain access to the internal components Chapter 6 describes how to remove and fit the PSU and power subassemblies Chapter 7 describes how to remove and fit the system fans Chapter 8 describes how to remove and fit the system storage devices Chapter 9 describes how to remove and fit the motherboard and the components that interface with it Chapter 10 provides a functional description of the system Chapter 11 provides information about the I O connectors xxi Chapter 12 describes how to connect and set up a modem Appendix A provides an illustrated list of replaceable parts and components Appendix B provides a product specification Appendix C contains a list of tools that are needed to service the system Appendix D provides details of the internal motherboard connectors Appendix E provides an example of a typical POST diagnostic output Appendix F describes how to update LOMlite2 firmware Appendix G describes how to connect to the Netra T4 s
52. 00 0001 0000 0000 Init CPU arrays Done Init E tags Done Setup TLB Done MMUs ON Block Scrubbing Done Copy Done PC 0000 07ff f008 4200 PC 0000 0000 0000 4278 Decompressing Done Size 0000 0000 0007 24b0 ttya initialized Start Reason First start after Power On System Reset SPOR PLL Probing gptwo at 0 0 SUNW UltraSPARC III memory controller Probing gptwo at 1 0 SUNW UltraSPARC III memory controller Probing gptwo at 8 0 pci pci Loading Support Packages kbd translator dimm fru diag level Variable Set to min 14 of 15 750 MHz 5 1 750 MHz 5 1 8 MB 8 MB Loading onboard drivers ebus flashprom bbc power i2c dimm fru dimm fru dimm fru dimm fru dimm fru dimm fru dimm fru i2c cpu fru temperature cpu fru hardware monitor hardware monitor Netra T4 AC100 DC100 Service and System Reference Manual August 2001 CODE EXAMPLE E 2 diag level Variable Set to min 15 of 15 hardware monitor temperatur motherboard fru ioexp power supply lomlite2 lombus SUNW lomc serial lomp lomv Memory Configuration Segment Base SUNW Netra T4 Probing Probing Probing Probing Probing Probing Probing Probing pci pci pci pci pci pci pci pci 8 60 8 60 8 70 8 70 8 70 8 70 8 70 8 70 5 0O OOo O O OO O CF OGO Oh GS OO D O T O OQ OOGO Device Device Device Device Device 4 1 5 6 Device
53. 1 400000 Diagnostic Output Message obdiag gt test 15 Hit the spacebar to interrupt testing Testing pci 8 700000 ebus 5 serial 1 400000 ae aie wares recone IAs aisle cst tes OT passed Pass 1 of 1 Errors 0 of 0 Tests Failed 0 Elapsed Time 0 0 0 1 Hit any key to return to the main menu WSHe5 3 The following code example shows the USB output message CODE EXAMPLE 4 26 usb 5 3 Diagnostic Output Message obdiag gt test 16 Hit the spacebar to interrupt testing Testing pci 8 700000 usb 5 3 EAN E E reece wad tar shin io Nieibar Sr eh oaane terete se odstate uskeuds ot See passed Pass 1 of 1 Errors 0 of 0 Tests Failed 0 Elapsed Time 0 0 0 0 Hit any key to return to the main menu Chapter 4 Troubleshooting 4 29 4 5 4 19 test all The test a11 diagnostic runs all tests in sequence Note You can exclude certain tests using the except command The following code example shows the test a11 output message CODE EXAMPLE 4 27 test all Diagnostic Output Message obdiag gt test all Hit the spacebar to interrupt testing Testing pci 8 700000 ebus 5 lombus 1 3062f8 SUNW lomv 0 0 passed Testing pei 8 600000 SUNW q LECA mae eee este ia eee a deel Sa oe ed passed Testing pere3 4 000 00 ebus 5 bbC C10 a ces t ccs ek dared te aid a eaten Bee passed Testing PCs 00000 ESDUS CD eisa Peace es coder te ace E E EEE wees EA ENEA Beets passed Testing p
54. 1 10 DB 15 Male Alarms Service Port Connector 11 11 RJ45 Lights Out Management Serial Connector 11 12 Exploded View of the Netra T4 System Unit A 2 Smart Card Reader Connector J3604 Pin Assignments D 1 Internal FC AL Connector J2901 D 4 Power Supply Connector J3603 D 6 Power Supply Connector J3601 D 7 Figures xiii xiv Netra T4 AC100 DC100 Service and System Reference Manual August 2001 TABLE 1 1 TABLE 1 2 TABLE 1 3 TABLE 1 4 TABLE 2 1 TABLE 3 1 TABLE 3 2 TABLE 3 3 TABLE 3 4 TABLE 3 5 TABLE 3 6 TABLE 3 7 TABLE 4 1 TABLE 4 2 TABLE 4 3 TABLE 4 4 TABLE 4 5 TABLE 4 6 TABLE 4 7 Tables Front Panel System LED Functions 1 7 LOMlite2 Status LED Functions 1 8 PSU Status LED Functions 1 10 PSU Status LED Functions Netra T4 DC100 1 11 POST Completion Times 2 5 New SunVTS Commands 3 4 SunVTS Processor Tests 3 6 SunVTS Memory Tests 3 7 SunVTS Storage Device Tests 3 7 SunVTS Network Tests 3 7 SunVTS Communications Port Tests 3 7 SunVTS Custom Test 3 8 Internal Drives Identification 4 3 J3601 Voltage Pin Table 4 7 J3603 Voltage Pin Table 4 7 probe andtest Commands 4 10 Selected OpenBoot PROM On Board Diagnostic Tests 4 12 Parent Node Names 4 15 Child Node Names 4 17 XV TABLE 4 8 TABLE 4 9 TABLE 4 10 TABLE 10 1 TABLE 10 2 TABLE 10 3 TABLE 10 4 TABLE 10 5 TABLE 10 6 TABLE 10 7 TABLE 10 8 TABLE 10 9 TABLE 11 1 TABLE 11 2 TABL
55. 1 3 11 4 Ge FIGURE 11 4 68 Pin SCSI Connector TABLE 11 3 68 Pin SCSI Connector Pinout c SCSI Connector 6 amp o0oo0o0000000000000000000000000000000035 T Pin Signal Name Pin Signal Name 1 GND 21 GND 2 GND 22 GND 3 GND 23 GND 4 GND 24 GND 5 GND 25 GND 6 GND 26 GND 7 GND 27 GND 8 GND 28 GND 9 GND 29 GND 10 GND 30 GND 11 GND 31 GND 12 GND 32 GND Netra T4 AC100 DC100 Service and System Reference Manual August 2001 TABLE 11 3 68 Pin SCSI Connector Pinout Continued Pin Signal Name Pin Signal Name 13 GND 33 GND 14 GND 34 GND 15 GND 35 DB lt 12 gt 16 GND 36 DB lt 13 gt 17 TERMPWR 37 DB lt 14 gt 18 TERMPWR 38 DB lt 15 gt 19 Not connected 39 PAR lt 1 gt 20 GND 40 DB lt 0 gt 41 DB lt 1 gt 55 ATN 42 DB lt 2 gt 56 GND 43 DB lt 3 gt 57 BSY 44 DB lt 4 gt 58 ACK 45 DB lt 5 gt 59 RST 46 DB lt 6 gt 60 MSG 47 DB lt 7 gt 61 SEL 48 PAR lt 0 gt 62 CD 49 GND 63 REQ 50 TERM DIS 64 IO 51 TERMPWR 65 DB lt 8 gt 52 TERMPWR 66 DB lt 9 gt 53 Reserved 67 DB lt 10 gt 54 GND 68 DB lt 11 gt Note All signals shown in TABLE 11 3 are active low Chapter 11 External I O Connectors 11 5 11 3 1 11 3 2 11 3 2 1 SCSI Implementation m SCSI 3 Fast 20 UltraSCSI parallel interface m 16 bit SCSI bus m 40Mbps data transfer rate m Support for 16 SCSI addresses a Target 0 to 6 and 8 to F for devices a Target 7 reserved for SCSI hos
56. 1 6c Host ID 80fb216c 0 ok 6 At the ok prompt type obdiag Verify that the OBDiag menu is displayed CODE EXAMPLE 4 10 CODE EXAMPLE 4 10 obdiag Menu or brd Ay a g 1 SUNW lomv 0 0 2 SUNW qlc 4 3 bbc 1 0 4 ebus 5 5 flashprom 0 0 6 gpio 1 300600 7 i2c 1 2e 8 i2c 1 30 9 network 5 1 10 parallel 1 300278 11 pmc 1 300700 12 rtc 1 300070 13 scsi 6 14 scsi 6 1 15 serial 1 400000 16 usb 5 3 Commands test test all except help what printenvs setenv versions exit Chapter 4 Troubleshooting 4 23 The following menu is displayed when the help command is executed TABLE 4 10 obdiag Help Command Description exit Exits obdiag tool help Prints this help information setenv Sets diagnostic configuration variable to new value printenvs Prints values for diagnostic configuration variables versions Prints self tests library and obdiag tool versions test all Tests all devices displayed in the menu test 1 2 5 Tests devices 1 2 and 5 except 2 5 Tests all devices except devices 2 and 5 what 1 2 5 Prints some selected properties for devices 1 2 and 5 4 5 4 3 SUNW lomv 0 0 The following code example shows the lomv test output CODE EXAMPLE 4 11 SUNW lomv 0 0 Diagnostic Output Message obdiag gt test 1 Hit the spacebar to interrupt testing Testing pci 8 700000 ebus 5 lombus 1 3062f8 SUNW lomv 0 0 a ea ace wer ee passed Pass 1 of 1 Errors 0 of 0 Tests Failed 0 Elapsed Time 0
57. 2 2 Removing the FC AL Backplane and Drive Bay on page 8 8 6 Remove the RMM drive assembly See Section 8 3 2 Removing a Removable Media Module on page 8 11 LAZ Removing the PSU Fans Assembly 1 Perform the steps in Section 7 1 1 Preparation on page 7 3 as required 2 Disconnect the fan power cables at J6 and J7 on the PDB 3 Disengage the hooks on the plastic airflow guide from the chassis front panel 4 Lift the plastic airflow guide together with the two fans from the chassis enclosure FASS Installing the PSU Fans Assembly 1 Perform the steps in Section 7 1 1 Preparation on page 7 3 as required 2 Insert the fans in the plastic airflow guide Ensure that the airflow direction arrows are aligned with the arrow on the plastic guide 3 Insert the plastic airflow guide and fans into the enclosure and gently press into place until the plastic hooks on the guide locate in the notches in the chassis front panel 4 Reconnect the fan power cables to J6 and J7 on the PDB Connect the left hand fan Fan 1 to J6 and the right hand fan Fan 2 to J7 5 Refit the RMM drive assembly See Section 8 3 3 Installing a Removable Media Module on page 8 12 6 Refit the FC AL drive assembly See Section 8 2 3 Installing the FC AL Backplane and Drive Bay on page 8 9 7 4 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 7 Refit the top access cover See Section 5
58. 2 5 The following code examples identify the watch net and the watch net all output messages CODE EXAMPLE 4 5 watch net Diagnostic Output Message 0 ok watch net Internal loopback test succeeded Link is up Looking for Ethernet Packets is a Good Packet X is a Bad Packet Type any key WO SCOP esd abe aided whee a ee gees See eS CODE EXAMPLE 4 6 watch net all Diagnostic Output Message 0 ok watch net all pci 8 700000 network 5 1 Internal loopback test succeeded Link is up Looking for Ethernet Packets is a Good Packet X is a Bad Packet Type any key to stop Serial Port Protocol The serial port protocol is now programmed as RS232 or RS423 using setenv rather than by changing a jumper setting To change the serial ports to RS232 type setenv ttya mode 9600 8 n 1 rs232 setenv ttyb mode 9600 8 n 1 rs232 setenv auto boot false reset all To change the serial ports to RS423 type ok setenv ttya mode 9600 8 n 1 rs423 ok setenv ttyb mode 9600 8 n 1 rs423 ok setenv auto boot false ok reset all Chapter 4 Troubleshooting 4 13 4 5 3 Device Tree The device tree for the Netra T4 system is shown in FIGURE 4 2 pci 8 700000 pci 8 600000 L mera ntroller E PCI slot 1 ODIE sd 0 0 Disks st 4 0 st 0 0 Tapes sd 6 0 DVD ROM euses _ network 5 1 ss
59. 3 2 Netra T4 DC100 System TABLE 1 4 PSU Status LED Functions Netra T4 DC100 LED Icon Color Function Fail J Amber Illuminated when PSU is in a Fault condition Off when PSU is not enabled OK Flashes if unit is within 10 C of thermal shutdown or has shutdown PSOK Green Illuminated when output voltages are within operating range Flashes when PSU is in Standby mode Input B OK B Green Illuminated when input voltage from feeder B is above 37V Off when Input B is below 35V Input A OK A Green Illuminated when input voltage from feeder A is above 37V Off when Input A is below 35V Dw e Tere hy e jet Je moog ponon OWONU mommy kael y FIGURE 1 5 PSU Status LEDs Netra T4 DC100 System Chapter 1 System Description 1 11 1 12 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 CHAPTER 2 Power On Self Test This chapter describes how to initiate power on self test POST diagnostics The chapter contains the following topics Section 2 1 POST Overview on page 2 1 Section 2 2 Pre POST Preparation on page 2 3 Section 2 3 Running POST on page 2 4 a a a m Section 2 4 POST Diagnostic Levels on page 2 4 2 1 POST Overview POST is a firmware program that is useful in determining if a portion of the system has failed POST verifies the core functionality
60. 4 14 ortc 1 300070 The following code example shows the rtc 1 300070 output message CODE EXAMPLE 4 22 rtc 1 300070 Diagnostic Output Message obdiag gt test 12 Hit the spacebar to interrupt testing Testing pci 8 700000 ebus 5 rtc 1 300070 PEE E oN E E E EE R AE ota eta passed Pass 1 of 1 Errors 0 of 0 Tests Failed 0 Elapsed Time Hit any key to return to the main menu 4 5 4 15 scsi 6 4 28 The following code example shows the scsi 6 output message CODE EXAMPLE 4 23 scsi 6 Diagnostic Output Message obdiag gt test 13 Hit the spacebar to interrupt testing Testing pci 8 700000 scsi 6 EEE a eds shaker E E E A AE TE E take Walenoer sr passed Pass 1 of 1 Errors 0 of 0 Tests Failed 0 Elapsed Time Hit any key to return to the main menu Netra T4 AC100 DC100 Service and System Reference Manual August 2001 0 0 0 0 0 20 0 85 0 0 0 5 4 5 4 16 4 5 4 17 4 5 4 18 scsi 6 1 The following code example shows the scsi 6 1 output message CODE EXAMPLE 4 24 scsi 6 1 Diagnostic Output Message obdiag gt test 14 Hit the spacebar to interrupt testing Testing pci 8 700000 scsi 6 1 OS aera dace rea gue eats ate eee EAT ot AE E awake E AEA passed Pass l1 of 1 Errors 0 of 0 Tests Failed 0 Elapsed Time 0 0 0 5 Hit any key to return to the main menu serial l1 400000 The following code example shows the serial output message CODE EXAMPLE 4 25 serial
61. 4 AC100 DC100 Service and System Reference Manual August 2001 CODE EXAMPLE E 1 diag level Variable Set to max 5 of 17 4M Test Test on O S sO O Test O Test O Test O Test O Test 4M a rest oa oOo 0O oO est rest Test O O 0 Test 0 Test 0 Test DTLB TAG address up address down 1 4M DTLB TAG cell disturbance 1 Test address up data reliability 1 Test address down address line transitions 1 Test cell disturbance DTLB TAG 1 Test data reliability address up 1 Test address line transitions 1 8K DTLB TAG address down 1 Test address up address line transitions 1 Test address down ITLB RAM address up address down 1 Test address line transitions cell disturbance data reliability 1 4M ITLB RAM address line transitions 1 Test address up ITLB RAM 1 Test address down address up 1 Test cell disturbance address down 1 Test data reliability cell disturbance 1 Test address line transitions 1 8K ITLB RAM data reliability l Test address up l Test address down 1 Test cell disturbance address line transitions l Test data reliability Appendix E Example POST Diagnostic Output E 5 CODE EXAMPLE E 1 0 0 0 0 0 0 0 ea ear oO 4M ITLB DMMU Ini est cell Test data a O 8K ITLB ao on
62. 44 oC CPU1L Sensor package temperature 44 oC WARNING Temperature sensor on UPAO missing WARNING Temperature sensor on UPA1 missing WARNING Smart card reader missing Read parameters from seeproms Size bank MB Number of banks DI 0 2562 DI T2562 DI 2 2562 DI 32562 DI 4 2562 DI 5 2562 DI 6 2562 DI T 2562 Bank 0 is present size 00000000 40000000 Bank 1 is present size 00000000 40000000 Bank 2 is present size 00000000 40000000 Bank 3 is present size 00000000 40000000 Setup CPUs and system frequency CPU O ratio 5 CPU 1 ratio 5 System frequency 150 MHz Load PLL and reset 1 PLL reset PLL reset os 1 SoftInt amp Interrupt O Configure I2C controller 0 0 Configure I2C controller 1 SoftInt amp Interrupt oa Test walking 1 through softint register os Test walking 0 through softint register oa 1 Tick amp Tick Compare Reg Verify interrupt occurs for each level 1 Walk 1 0 TICK Compare register oa O Verify interrupt occurs at the right PIL E 2 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 1 Test walking 1 through softint register 1 Test walking 0 through softint register 1 Verify interrupt occurs for each level 1l Verify interrupt occurs at the right PIL CODE EXAMPLE E 1 diag level Variable Set to max 3 of 17 on ap Ya Gan oD aA m
63. 6 3 Fitting the Top Access Cover on page 5 9 8 Refit the front fascia See Section 5 7 2 Fitting the Front Fascia on page 5 11 hae PERAN CPU Fan Assembly The CPU fan is mounted on the transverse support bar in front of the CPU module housing Preparation Before proceeding to remove the CPU fan assembly carry out the following Initiate antistatic precautions See Section 5 5 Antistatic Precautions on page 5 5 If the system is running shut it down and remove the power See Section 5 3 2 Powering Off the System on page 5 4 Remove the top access cover See Section 5 6 2 Removing the Top Access Cover on page 5 9 Lower the front fascia See Section 5 7 1 Removing the Front Fascia on page 5 11 Remove the RMM drive assembly See Section 8 3 2 Removing a Removable Media Module on page 8 11 Chapter 7 Fan Subassemblies 7 5 FIGURE 7 3 CPU Fan August 2001 Netra T4 AC100 DC100 Service and System Reference Manual 7 6 722 7 2 9 Removing the CPU Fan Assembly Perform the steps in Section 7 2 2 Removing the CPU Fan Assembly on page 7 7 as required Disconnect the fan power cable at J9 on the PDB Using a stubby Phillips screwdriver remove the two captive screws securing the retaining clip on the right hand side of the fan Slide the fan to the right to clear the fan retainer and ease the assembly f
64. 6 USB Connectors 11 10 11 7 Alarms Ports 11 11 11 8 System Configuration Card Reader 11 12 Modem Setup 12 1 12 1 To Set Up the Modem 12 1 12 2 Serial Port Speed Change 12 2 12 3 Recommendations 12 2 Illustrated Parts List A 1 Product Specification B 1 B 1 Physical Specification B 1 B 1 1 Dimensions B 1 B 1 2 Mounting Flanges B 1 B 2 Electrical Specification B 2 B 2 1 Netra T4 AC100 System B 2 B 2 2 Netra T4 DC100 System B 3 B 3 Environmental Specification B 4 B 3 1 Operating and Storage B 4 B 3 2 Acoustic Noise B 5 B 3 3 Earthquake B 5 B 3 4 Electro Magnetic Compatibility B 5 Tool Requirements C 1 Motherboard Connectors D 1 D 1 SCCRConnector D 1 D 2 Internal SCSI Connector D 3 D 3 Internal FC AL Connector D 4 Contents ix D 4 Power Connectors D 5 E Example POST Diagnostic Output E 1 F Updating LOMlite2 Firmware F 1 G Connecting to the Netra T4 Server G 1 G 1 Connecting to the LOM Serial Port G 1 G 2 Connecting to the Serial Ports G 2 x Netra T4 AC100 DC100 Service and System Reference Manual August 2001 GURE 1 1 GURE 1 2 GURE 1 3 GURE 1 4 GURE 1 5 GURE 3 1 GURE 4 1 GURE 4 2 GURE 5 1 GURE 5 2 GURE 5 3 GURE 5 4 GURE 5 5 GURE 6 1 GURE 6 2 GURE 6 3 GURE 7 1 GURE 7 2 GURE 7 3 Figures Netra T4 System Dimensions and Mounting Options dimensions in mm Front Panel System LEDs 1 6 LOMLite2 Status LEDs 1 9 PSU Status LEDs Netra T4 AC100 System 1
65. 600 i2c 1 2e Test Function LOMlite2 Selftest Lomlite registers test FC AL SCSI Enclosure Services SES Subsystem Tests m FC AL ISP2200A PCI configuration space register test FPM FB DMA PBUI and RISC register test Mailbox tests Memory bank tests RISC RAM test FIFO load and unload test m Disk Tests Read Write Restore test Seek test Random seek test Hour glass seek test Built in self test BIST m SES Tests Get supported diagnostic page test Get configuration page test a Get enclosure status page test BBC Self Test m Register test RIO Ebus Self Test PCI configuration space register test Ebus register test DMA register test DMA functional test TCR register test AUX I O register test Flash Self Test m Flash read test m Flash write test manufacturing test only Super I O Self Test m General purpose I O test I2C Self Test m 12C bus test 4 20 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 TABLE 4 9 Netra T4 System Specific OBDiag Self Tests Continued Test Test Function i2c 1 30 network 5 1 parallel 1 300278 pmc 1 300700 rtc 1 300070 scsi 6 scsi 6 1 serial 1 400000 usb 5 3 I2C Self Test m 12C bus test RIO GEM Self Test 10 100 Mbits PCI configuration space register test RIO GEM register test Internal loopback RIO GEM level Internal loopback Lucent 6612 PHY level External loopback requires RJ45 loopback c
66. 66MHz All four PCI slots can accept 33 MHz cards Note Installing a 33 MHz card into a 66 MHz EPCI slot will slow system performance 66 MHz cards are restricted to the slot labelled EPCI 1 The following table lists the mapping of the PCI slots to the two PCI buses and the type of PCI cards supported in each slot TABLE 10 2 PCI Slot to PCI Bus Mapping Connector Slot Width bits Clock Rates DC Voltage VDC Label Conn No PCI Bus Card Type bits MHz Card Type PCI 4 J2601 B 64 32 or 64 33 5 universal PCI 3 J2501 B 64 32 or 64 33 5 universal PCI 2 J2401 B 64 32 or 64 33 5 universal PCI 66 1 J2301 A 64 32 or 64 66 3 3 universal PCI Bus ASICs SCSI Controller The SCSI controller ASIC provides an interface between the 33 MHz PCI bus and the internal and external SCSI buses The dual SCSI bus controller provides separate connections to internal and external devices SCSI channel A is used for internal devices and supports the SCSI fast and narrow mode SCSI channel B is used for external devices and supports the SCSI ultra wide mode Chapter 10 Functional Description 10 23 FC AL Disk Controller The FC AL disk controller ASIC provides an interface between the 64 bit 66 MHz PCI bus the two FC AL hard drives and an external FC AL connector The FC AL controller provides connection to internal and external devices through one channel The FC AL loop supports up to 125 devices See Section 10 2 14 FC AL Subsystem
67. A leaf block PCIB leaf block The following figure depicts the micro architecture of the SBC ASIC Arb Or Data ECC Ctrl Address 10 MHz JTAG JTAG 5 Ctrl Sun Crossbar Interconnect Merge Buffer Interface Halll UPA64S Block Leaf not used DMA FSM PIO FSM Clocks Misc gt 66 MHz v v IChip 64 bit 33 MHz PCI 6 devices 64 bit 66 33 MHz EPCI 2 4 devices FIGURE 10 7 SBC Block Diagram 10 12 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 10 2 3 2 The internal interface between the Sun CrossBar Interconnect interface block and the leaf blocks is fully asynchronous This enables the frequency of Sun CrossBar Interconnect to be tuned according to the limitations of the system There is no relative frequency limitation and the frequency of a leaf can be higher than the Sun CrossBar Interconnect frequency EPCI A Leaf Block The extended PCI EPCI is the 64 bit 66 MHz PCI The PCI A leaf is the host controller for the EPCI It supports 3 3V signalling only The PCI A leaf can support four master devices The Netra T4 system only includes two the EPCI slot and the FC AL disk controller The micro architecture of both PCI leaves is almost identical and the PCI A leaf also supports the logic blocks mentioned above to comply with the Sun4u Sun5 architecture The EPCI high bandwidth pluggable I O interface sustains up to 500Mbps in streaming Direct Virtual
68. AGS Status Data Test address up up Test address down down Test cell disturbance disturbance 1 P Cache SnoopTags Init Test address up FPU Registers 1 O Test walking 1 0 FPU registers 1 1 Test address down Test cell disturbance P Cache Status Data Test address up Test cell disturbance P Cache Init FPU Registers Test walking 1 0 FPU registers L 1 1 1 1 Test address down 1 1 1 1 st register addressing Test walking 1 FSR register Ecache RAM Test address up 1 T st register addressing 1 FSR 1 Test walking 1 FSR register 1 Ecache RAM l Test address up Appendix E Example POST Diagnostic Output E 25 CODE EXAMPLE E 2 Test address down 1 Test address down Test cell disturbance 1 Test cell disturbance Ecache Init 1 Ecache Init Correctable Ecach cc Test 1 Correctable Ecache ECC Test Uncorrectable Ecache ECC Test diag level Variable Set to min 10 of 15 1 Uncorrectable Ecache ECC Test Correctable SW Ecache ECC Test 1 Correctable SW Ecache ECC Test Uncorrectable SW Ecache ECC Test 1 Uncorrectable SW Ecache ECC Test Correctable System ECC Test Uncorrectable System ECC Test Memory address
69. Assembly 7 4 7 1 3 Installing the PSU Fans Assembly 7 4 7 2 CPU Fan Assembly 7 5 7 2 1 Preparation 7 5 7 2 2 Removing the CPU Fan Assembly 7 7 7 2 3 Installing the CPU Fan Assembly 7 7 8 Storage Devices 8 1 8 1 FC AL Hard Disk Drive 8 1 8 1 1 Preparing to Remove a Disk Drive Hot Swap 8 2 8 1 2 Removing a Disk Drive Hot Swap 8 3 8 1 3 Hot Swapping a Disk Drive Installation 8 4 8 1 4 Preparing to Remove an Unmirrored Root Disk 8 5 8 1 5 Removing an Unmirrored Root Disk 8 5 8 1 6 Installing an Unmirrored Root Disk 8 6 8 2 Fiber Channel Backplane and Drive Bay 8 6 8 2 1 Preparation 8 8 8 2 2 Removing the FC AL Backplane and Drive Bay 8 8 8 2 3 Installing the FC AL Backplane and Drive Bay 8 9 8 3 Removable Media Module 8 10 8 3 1 Preparation 8 10 8 3 2 Removing a Removable Media Module 8 11 8 3 3 Installing a Removable Media Module 8 12 9 Motherboard and Component Replacement 9 1 9 1 PCI Cards 9 2 9 1 1 Preparation 9 3 9 1 2 Removing a PCI Card 9 3 vi Netra T4 AC100 DC100 Service and System Reference Manual August 2001 Part II 10 9 2 9 3 9 4 9 5 9 6 9 7 9 1 3 Installing a PCI Card 9 3 Processor Modules 9 4 9 2 1 Preparation 9 6 9 2 2 Removing a CPU Module 9 6 9 2 3 Installing a CPU Module 9 7 Memory Modules 9 9 9 3 1 Preparation 9 10 9 3 2 Removing a Memory Module 9 11 9 3 3 Installing a Memory Module 9 11 Replaceable Battery 9 12 9 4 1 Preparation 9 12 9 4 2 Removing the Battery 9 13 9 4 3 I
70. B 3 4 Temperature Variation Operating 30 C hr maximum Storage 30 C hr maximum Altitude Operating 0 to 3000m Storage 0 to 12000m Acoustic Noise Less than 6 0Bels in tests performed in accordance with ISO 9295 1988 International Standard on Acoustics Measurement of high frequency Noise Emitted by Computer and Business Equipment Earthquake The system conforms to the NEBS requirements for earthquake zone 4 Electro Magnetic Compatibility Immunity Emissions Conforms to GR 1089 CORE and EN55024 1 Conforms to GR 1089 CORE and EN55022 Class A and FCC A Appendix B Product Specification B 5 B 6 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 APPENDIX C Tool Requirements This appendix lists the tools you will require to service the Netra T4 system Phillips No 1 screwdriver 10cm 4in Phillips No 2 screwdriver 15cm 6in Phillips No 2 screwdriver stubby 6mm 0 25in flat blade screwdriver 10cm 4in Antistatic wrist strap Antistatic mat Long nose pliers Digital voltage meter DVM Torque tool calibrated to 5lbf in 3mm square drive Place components sensitive to electrostatic discharge ESD such as system boards disk drives and memory modules on an antistatic mat 1 Located inside the system at the front of the chassis on the left hand side panel C 1 C 2 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 APPENDIX
71. BC boot boot PROM CRC DAT DIMM DMA DRAM DTAG DVD DVM EBus EEPROM 1 A number used by the system software to identify a storage location 2 In networking a unique code that identifies a node to the network Application specific integrated circuit An operation that is not synchronized with the timing of any other part of the system BootBus controller To load the system software into memory and start it running In Sun workstations the boot PROM contains a PROM monitor program a command interpreter used for booting resetting low level configuring and simple testing Cyclic redundancy check Digital audio tape Dual in line memory module A small printed circuit card that contains dynamic random access memory chips Direct memory address Dynamic random access memory Read write dynamic memory in which the data can be read or written in approximately the same amount of time for any memory location Dual tag or data tag Digital video disk Digital voltage meter A slow byte wide bus for low speed devices Electrically erasable programmable read only memory EMI EPCI ESD Ethernet FC AL FIFO flash PROM FRU Gbyte GUI HSI I O JTAG Kbyte Leaf LED LOM MBps Mbps Mbyte MHz MII Electromagnetic interference Electrical characteristic that directly or indirectly contributes to a degradation in performance of an electronic system Extended peripheral component interconnect
72. CPU slot must be fitted with a shroud filler panel in place of a CPU module Caution When you unpack a new CPU module from its packing carton it is important that you observe the following handling precautions to avoid damaging the module 1 When you lift the module from the packing carton in its antistatic bag use both hands to support the module along its short sides 2 After you remove the module from its antistatic bag handle it only by its captive screws Do not touch the connectors on the bottom edge of the module which can be easily bent or damaged by improper handling 3 Do not remove the plastic cover from the connectors until you are ready to install the module 4 Do not grip the module by the heat sinks which can shift if handled improperly 5 Use proper ESD grounding techniques when handling components Wear an antistatic wrist strap and use an ESD protected mat Store ESD sensitive components in antistatic bags before placing them on any surface 9 4 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 FIGURE 9 2 CPU Modules 9 5 Chapter 9 Motherboard and Component Replacement Del O22 Preparation Before proceeding to remove a CPU module carry out the following Initiate antistatic precautions See Section 5 5 Antistatic Precautions on page 5 5 If the system is running shut it down and remove the power See Section 5 3 2 Powering O
73. D Motherboard Connectors This sppendix describes the system motherboard connector signals and pin assignments The appendix contains the following sections Section D 1 SCCR Connector on page D 1 Section D 2 Internal SCSI Connector on page D 3 Section D 3 Internal FC AL Connector on page D 4 a a a m Section D 4 Power Connectors on page D 5 D 1 SCCR Connector The SCCR connector J3604 is located on the motherboard 1 3 5 7 9 O Oo O O Oo Oo 2 4 6 8 10 FIGURE D 1 Smart Card Reader Connector J3604 Pin Assignments D 1 D 2 TABLE D 1 SCCR J3604 Pin Assignments Pin Signal Name Description 1 12 VDC 12VDC power 2 GND Ground 3 GND Ground 4 I2C_SCL I2C bus clock 5 5 VDC 5 VDC power 6 I2C_SDA I2C bus data 7 GND Ground 8 GND Ground 9 Int_L 10 NC No connection Netra T4 AC100 DC100 Service and System Reference Manual August 2001 D 2 Internal SCSI Connector oooooo0o0000000000000000000000000000000000000000000 oooooo0o0000000000000000000000000000000000000000000 49 Internal SCSI Connector J5002 50 TABLE D 2 Internal SCSI Connector J5002 Pin Signal Name 1 19 20 22 24 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 26 32 36 38 40 GND SCSI data bus SCSI_A_PAR lt 0 gt Termpowr_A SCSI_A_ATN_L SCSI_A_BSY_L SCSI_A_ACK_L SCSI_A_RESET_L Appendix D M
74. DC with a maximum of 12 VDC and 12VDC in RS 232 mode RS 423 support is similar except that signaling levels are between 4VDC to 6VDC and 4VDC to 6VDC The line driver switches at 5 3VDC and 5 3 VDC with a maximum of 6V and 6 VDC The preferred signaling protocol is RS 423 The higher voltages of RS 232 makes it more difficult to switch at the higher baud rates The maximum rate for RS 232 is approximately 64Kbaud while the maximum rate for RS 423 is 460 8 Kbaud The system default is set to RS 232 Note The serial port protocol is changed using the OBP not by changing a jumper setting Synchronous Rates The serial synchronous ports operate at any rate from 50Kbaud to 256 Kbaud when the clock is generated from the serial port controller When the clock is generated from an external source the synchronous ports operate at up to 384Kbaud Clock generation is accurate within one percent for any rate that is generated between 50Kbaud and 256 Kbaud Asynchronous Rates The serial asynchronous ports support twenty baud rates that are all exact divisors of the crystal frequency with the exception of 110 which is off by less than one percent Baud rates are 50 75 110 200 300 600 1200 1800 2400 4800 9600 19200 38400 57600 76800 115200 153600 230400 307200 and 460800 Chapter 10 Functional Description 10 29 10 2 12 2 Slew Rate and Cable Length The maximum RS 423 cable length is 30 0m 98 4ft and th
75. E 11 3 TABLE 11 4 TABLE 11 5 TABLE 11 6 TABLE 11 7 TABLE 11 8 TABLE 11 9 TABLE 11 10 TABLE A 1 TABLE A 2 TABLE B 1 TABLE 12 1 TABLE D 1 TABLE D 2 TABLE D 3 OBDiag Configuration Variables 4 19 Netra T4 System Specific OBDiag Self Tests 4 20 obdiag Help 4 24 Valid Memory Configurations 10 9 PCI Slot to PCI Bus Mapping 10 23 Internal Hard Drive Features 10 24 ISP2200A GPIO Bits 10 32 AC Power Supply Output Values 10 36 DC Power Supply Output Values 10 36 Power Supply Control Signal Levels 10 37 Motherboard Component Functions 10 39 Flash PROM Jumper Settings 10 42 Parallel Connector Pinout 11 2 Serial Connector Pinout RS423 RS232 11 3 68 Pin SCSI Connector Pinout 11 4 Determining SCSI Bus Length 11 7 TPE Connector Pinout 11 8 TPE STP 5 Cable Lengths 11 9 FC AL Connector Pinout 11 9 USB Connector Pinout 11 10 Alarms Service Port Connector Pinout 11 11 Lights Out Management Serial Connector Pinout 11 12 Netra T4 Field Replaceable Units A 3 Netra T4 Optional Components A 4 AC Power Supply Input Requirements B 2 DC Power Supply Input Requirements B 3 SCCR J3604 Pin Assignments D 2 Internal SCSI Connector J5002 D 3 Internal FC AL Connector J2901 D 4 xvi Netra T4 AC100 DC100 Service and System Reference Manual August 2001 TABLE D 4 TABLE D 5 TABLE D 6 TABLE G 1 TABLE G 2 Power Connectors D 5 Power Supply Connector J3603 Pin Description D 6 Power Supply Connector
76. E EXAMPLE 4 20 CODE EXAMPLE 4 21 CODE EXAMPLE 4 22 CODE EXAMPLE 4 23 CODE EXAMPLE 4 24 CODE EXAMPLE 4 25 CODE EXAMPLE 4 26 CODE EXAMPLE 4 27 CODE EXAMPLE E 1 gpio 1 300600 Diagnostic Output Message 4 26 i2c 1 2e Diagnostic Output Message with TIP Line Installed 4 26 i2c 1 30 Diagnostic Output Message 4 27 network 5 1 Diagnostic Output Message 4 27 parallel 1 300278 Diagnostic Output Message 4 27 pmc 1 300700 Diagnostic Output Message 4 28 rtc l1 300070 Diagnostic Output Message 4 28 scsi 6 Diagnostic Output Message 4 28 scsi 6 1 Diagnostic Output Message 4 29 serial 1 400000 Diagnostic Output Message 4 29 usb 5 3 Diagnostic Output Message 4 29 test all Diagnostic Output Message 4 30 diag level Variable Set to max E 1 CODE EXAMPLE E 2 diag level Variable Set to min E 17 XX Netra T4 AC100 DC100 Service and System Reference Manual August 2001 Preface This manual supports the Netra T4 AC100 DC100 server and comprises two parts m Part I Service is written for technicians advanced computer system end users with experience in replacing hardware and troubleshooting system administrators and authorized service providers ASPs Only suitably qualified service personnel may carry out tasks described in this manual that involve the removal of the top cover m Part II System Reference is written for OEM engineers system designers and application programmers who have to perform advanced
77. IMMs empty 128MByte 128MByte empty 256MByte 128MByte 256MByte 256MByte empty 512MByte 128MByte 512MByte Interleaving 2 way 2 way 2 way 4 way 2 way 2 way 2 way 2 way 2 way 4 way 2 way 2 way 2 way 2 way Chapter 10 Functional Description 10 9 10 2 2 3 10 2 2 4 TABLE 10 1 Valid Memory Configurations Continued Total Configured Memory Density Even Bank 0 DIMMs Odd Bank 1 DIMMs Interleaving 3 0GByte 512MByte 256MByte 2 way 256MByte 512MByte 2 way 4 0GByte 512Mbyte 512MByte 2 way 4 way 1GByte empty 2 way empty 1GByte 2 way 4 5GByte 1GByte 128MByte 2 way 128MByte 1GByte 2 way 5 0GByte 1GByte 256MByte 2 way 256MByte 1GByte 2 way 6 0GByte 1GByte 512MByte 2 way 512MByte 1GByte 2 way 8 0GByte 1GByte 1GByte 2 way 4 way Interleaving The main memory supports interleaving on 64 byte boundaries The memory system supports from one to four logical banks The DIMMs support two banks For interleaving purposes all banks are treated identically regardless of their physical location Two successive accesses to distinct logical banks located in the same group of DIMMs are processed the same as accesses to logical banks that are in separate groups of DIMMs The memory controller for the Netra T4 system supports 2 way and 4 way interleaving The main memory is accessed only on 64 byte block reads or writes The interleaving is based on a 64 byte addressing and the four low order bits of a block physical
78. M J0202 DIMM J0203 DIMM J0304 DIMM J0305 DIMM J0406 DIMM J0407 DIMM J0501 CPU connector J0601 CPU connector J0701 CPU connector J0801 CPU connector J1801 Not used J2001 Serial ports A B rear panel connector J2103 Jumper PROM R W See Section 10 5 Jumper Descriptions on page 10 40 J2104 Jumper PROM Select See Section 10 5 Jumper Descriptions on page 10 40 J2202 SCSI Parallel rear panel connector J2301 66 MHz PCI 1 connector J2401 33 MHz PCI 2 connector J2501 33 MHz PCI 3 connector J2601 33 MHz PCI 4 connector J2901 FC AL internal connector J2902 FC AL rear panel connector J3001 USB rear panel connector J3002 USB rear panel connector J3202 Not used Chapter 10 Functional Description 10 39 TABLE 10 8 Motherboard Component Functions Continued Designation Function J3203 Not used J3302 Not used J3303 Not used J3501 Server RSC connector J3601 Power supply connector J3602 Combined cable connector J3603 Power supply connector J3604 Smart card reader connector J3605 Not used J3608 Peripheral power cable connector J4301 Not used J4401 Not used J4501 Not used J5002 SCSI connector J5301 Ethernet rear panel connector 10 5 Jumper Descriptions Jumper configurations can be changed from the default settings by setting jumper switches on the motherboard A jumper switch is closed sometimes referred to as shorted with the plastic cap inserted over two pins of the jumper A jumper is open with the pl
79. Motherboard DVD ROM and DAT drives Hard drive Any option card that contains an onboard self test OBDiag performs root cause failure analysis on the referenced devices by testing internal registers confirming subsystem integrity and verifying device functionality On the motherboard OBDiag tests not only the motherboard but also its interfaces PCI SCSI Ethernet Serial Parallel USB I2C FC AL OBDiag Tests Each self test executes independently and returns a zero if it completes successfully or anon zero and an error report if it is unsuccessful Diagnostic configuration variables determine the level of coverage execution flow and the corresponding output These variables are configured using the setenv command TABLE 4 8 OBDiag Configuration Variables Variable Function Possible Values Default Value diag level Determines how the tests are performed min min max diag passes Defines the number of times the self test 1 method s are performed 1 When diag level is set to min OBDiag performs abbreviated tests 2 When diag level is set to max OBDiag performs extended tests 3 Where is the number of times the tests are performed integer Chapter 4 Troubleshooting 4 19 The new tests and their features for the Netra T4 system are summarized in TABLE 4 9 TABLE 4 9 Netra T4 System Specific OBDiag Self Tests Test SUNW lomv 0 0 SUNW qlc 4 bbc 1 0 ebus 5 flashprom 0 0 gpio 0 300
80. N L ETAT ET TOUTES AUTRES CONDITIONS DECLARATIONS ET GARANTIES EXPRESSES OU TACITES SONT FORMELLEMENT EXCLUES DANS LA MESURE AUTORISEE PAR LA LOI APPLICABLE Y COMPRIS NOTAMMENT TOUTE GARANTIE IMPLICITE RELATIVE A LA QUALITE MARCHANDE A L APTITUDE A UNE UTILISATION PARTICULIERE OU A L ABSENCE DE CONTREFA ON Od am Ca Adobe PostScript Part I Contents Service System Description 1 1 1 1 1 2 1 3 1 4 System Features 1 1 System Unit Components 1 5 Environmental Performance 1 5 LEDs 1 6 1 4 1 System LEDs 1 6 1 4 2 LOMlite2LEDs 1 8 1 4 3 PSU LEDs 1 10 Power On Self Test 2 1 2 1 2 2 2 3 2 4 POST Overview 2 1 2 1 1 How to Use POST 2 2 Pre POST Preparation 2 3 Running POST 2 4 POST Diagnostic Levels 2 4 2 4 1 diag level Variable Set to max 2 5 2 4 2 diag level Variable Set tomin 2 5 2 4 3 Error Messages 2 6 Contents iii 3 SunVTS 3 1 3 1 3 2 The Validation Test Suite 3 1 3 1 1 SunVTS Requirements 3 2 3 1 2 SunVTS References 3 2 3 1 3 Installation 3 3 3 1 4 New and Modified Features and Options 3 3 3 1 5 Starting SunVTS 3 5 SunVTS Tests 3 6 3 2 1 Guide to Using SunVTS 4 4 3 8 4 Troubleshooting 4 1 4 1 4 2 4 3 4 4 4 5 4 6 Power On Failure 4 2 System LEDs 4 2 Drive Failure 4 2 Power Supply Unit Troubleshooting 4 4 OpenBoot PROM Diagnostics 4 7 4 5 1 New Features 4 8 4 5 2 New and Modified Commands and Tests 4 10 4 5 3 Device Tree 4 14 4 5 4 Running the Dia
81. SI function number 4 5 4 Running the Diagnostics This section contains the following OpenBootDiag diagnostic information Section 4 5 4 1 OBDiag Tests on page 4 19 Section 4 5 4 2 Starting the OBDiag Menu on page 4 22 Section 4 5 4 3 SUNW lomv 0 0 on page 4 24 Section 4 5 4 4 SUNW qlc 4 on page 4 25 Section 4 5 4 5 bbc 1 0 on page 4 25 Section 4 5 4 6 ebus 5 on page 4 25 Section 4 5 4 7 flashprom 0 0 on page 4 26 Section 4 5 4 8 gpio 1 300600 on page 4 26 Section 4 5 4 9 i2c 1 2e on page 4 26 Section 4 5 4 10 i2c 1 30 on page 4 27 Section 4 5 4 11 network 5 1 on page 4 27 Section 4 5 4 12 parallel 1 300278 on page 4 27 Section 4 5 4 13 pmc 1 300700 on page 4 28 Section 4 5 4 14 ortc 1 300070 on page 4 28 Section 4 5 4 15 scsi 6 on page 4 28 Section 4 5 4 16 scsi 6 1 on page 4 29 Section 4 5 4 17 serial 1 400000 on page 4 29 Section 4 5 4 18 usb 5 3 on page 4 29 Section 4 5 4 19 test all on page 4 30 4 18 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 4 5 4 1 Note Set the diag level variable to min prior to performing these tests This can be done at the ok prompt or within the obdiag menu The OpenBoot diagnostic OBDiag is a menu driven set of diagnostics that reside in flash PROM on the motherboard OBDiag can isolate errors in the following system components
82. TS diagnostic software a SunVTS Test Reference Manual provides details about each individual SunVTS test a SunVTS Programmer s Guide supports the development of custom tests 3 2 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 3 1 3 3 1 4 Installation The SunVTS 4 4 software comprises four installation packages SUNWvts SunVTS kernel user interface and tests SUNWvtsx SunVTS 64 bit package SUNWvtsol SunVTS user interface SUNWvtsmn SunVTS man pages For details of the installation procedure refer to the Netra T4 AC100 DC100 Installation and User s Guide New and Modified Features and Options The following additions have been made to support the Netra T4 system Multiple user interfaces can monitor and run tests concurrently Tests have been included for the new components of the hardware platform Remote features enable you to interface to SunVTS from a remote system A test scheduler enables you to specify groups of tests to be conducted in a predefined order Tests in a group are executed concurrently so that all tests in one group complete before the tests in another group begin group P group beg m Anew SunVTS message format displays the information re ordered and labeled lt timestamp gt lt hostname gt SunVTS VTSID lt vts msgid gt lt modulename gt lt submodulename gt lt insttnum gt lt vts_msgtype gt lt device_pathname gt lt msg_txt gt
83. Tag ID of FCAL FC ALJTag ID Probing Seeprom on DIMMs and CPU modules CPUO Sensor pac CPU1L Sensor pac kage kage 1000a12 temperature 43 oC temperature 22 oC Temperature sensor on UPAO missing Temperature sensor on UPA1 missing Smart card reader missing ead parameters from seeproms Size bank MB Number of banks WARNING WARNING WARNING R DI 025 DI L325 DI 2 25 DI B25 DI 4 25 DI 9225 DI 25 DI TEZI Bank 0 is Bank 1 is Bank 2 is Bank 3 is 62 62 62 62 62 62 62 62 present present present present size 00000000 40000000 size 00000000 40000000 size 00000000 40000000 size 00000000 40000000 Setup CPUs and system frequency CPU 0 ratio CPU 1 ratio System frequency 5 5 150 MHz Load PLL and reset PLL reset on SoftInt os j j 0 Configure I2C 1 0 Configure 1 rest I2C lest 1 PLL rese 1 SoftIn t amp Interrupt controller 0 wal king 1 through softint register controller 1 wal king 0 through softint register amp Interrupt 1 Verify interrupt occurs for each level Test walking 1 through softint register E 18 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 CODE EXAMPLE E 2 OOO aA a Ore Oo e E e E e 3 Test walking 0 through softint register Verify Verify
84. Y interface that provide test configuration and status monitoring The SunVTS interface can run on one system to display the SunVTS test session of another system on the network SunVTS is distributed with each Solaris release It is located on the Sun Computer Systems Supplemental CD SunVTS Requirements Your system must meet the following requirements to run SunVTS a The SunVTS packages must be installed The main package is SUNWvts There are additional supporting packages that differ with the revision of the Solaris operating system that is installed See also Section 3 1 3 Installation on page 3 3 and the corresponding SunVTS documentation a The system must be booted to the multiuser level level 3 a To run SunVTS with a GUI CDE or Open Look that GUI must be installed Otherwise run SunVTS with the TTY mode interface SunVTS References To find out more information about the using SunVTS refer to the SunVTS documentation for the Solaris release that you are running The SunVTS documents are part of the Solaris on Sun Hardware AnswerBook collection This AnswerBook collection is pre installed on the hard disk of new systems It is also distributed on the Software Supplemental CD that is part of each Solaris Media Kit release and is also accessible at http docs sun com The following list describes the contents of each SunVTS document a SunVTS User s Guide describes how to install configure and run the SunV
85. address PA 9 6 determine the bank within a memory segment The stride on which banks are interleaved is 64 bytes no interleaving 128 bytes 2 way interleaving 256 bytes 4 way interleaving In only one configuration is it possible to interleave by four Both groups must be populated with DIMMs of the same size supporting two banks Memory Timing The CPU module memory controller is programmable so that different SDRAM speeds can be accommodated at different system clock frequencies and different processor clock ratios The memory bus timing is controlled by a set of four memory timing control registers 10 10 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 10 2 3 10 2 3 1 Memory Timing Values The timing values for a given configuration depend on the following factors m Speed of the SDRAM The frequency of the SDRAM chip is indicated in the serial ID EEPROM on each DIMM When two groups of four DIMMs are present the SDRAM speed is considered the speed of the slowest SDRAM chip in the group a DIMM implementation The implementation of the DIMM influences the timing parameters in the same way that the traces on the DIMM board define the memory bus topology The DIMM also supports a buffer for the address and control signals The serial ID PROM identifies the DIMM and by default defines a given implementation m System clock frequency Sun CrossBar Interconnect frequency The memory bus clock g
86. address line transitions 1 D Cache Init Test address 1 address 1 1 1 address 1 1 1 diag level Variable Set to max 9 of 17 Test address up MicroTags up Test address down down Test cell disturbance disturbance Test data reliability reliability Test address line transitions line transitions D Cache SnoopTags Test address up SnoopTags up Test address down down Test cell disturbance disturbance Test data reliability reliability Test address line transitions Init 1 W Cache RAM 1 Test address up RAM up Test address down down Test cell disturbance disturbance Test data reliability reliability Test address line transitions line transitions W Cache TAGS Test address up TAGS Test address down Test address up 1 Test cell disturbance Appendix E Example POST Diagnostic Output E 9 CODE EXAMPLE E 1 diag level Variable Set to max 10 of 17 0 Test address down l Test data reliability Test cell disturbance oe Test data reliability 1 Test address line transitions Test address line transitions 1 W Cache SnoopTAGS 0 W Cache SnoopTAGS l Test address up on oO wy O Test address up l Test address down O0 Test address down 1 Test cell disturbance O0 Test cell disturbance 1 Test data reliability O Test data reliability l Test address line transitions
87. ag gt test 8 Hit the spacebar to interrupt testing Testing pci 8 700000 ebus 5 i2c 1 30 OS agg ance rie ate ei Sth aed Toucan ghar seamaster apes tae passed Pass l1 of 1 Errors 0 of 0 Tests Failed 0 Elapsed Time 0 0 0 0 Hit any key to return to the main menu network 5 1 The following code example shows the network 5 1 output message CODE EXAMPLE 4 19 network 5 1 Diagnostic Output Message obdiag gt test 9 Hit the spacebar to interrupt testing Testing pci 8 700000 network 5 1 Hit any key to return to the main menu parallel 1 300278 The following code example shows the parallel port output message CODE EXAMPLE 4 20 parallel 1 300278 Diagnostic Output Message obdiag gt test 10 Hit the spacebar to interrupt testing Testing pci 8 700000 ebus 5 parallel 1 300278 Blea a Meats Cae bale Sateen Wade Bk ha eosin passed Pass 1 of 1 Errors 0 of 0 Tests Failed 0 Elapsed Time 0 0 0 0 Hit any key to return to the main menu Chapter 4 Troubleshooting 4 27 4 5 4 13 pmc 1 300700 The following code example shows the pmc 1 300700 output message CODE EXAMPLE 4 21 pmc 1 300700 Diagnostic Output Message bdiag gt test 11 Hit the spacebar to interrupt testing Testing pci 8 700000 ebus 5 pmc 1 300700 Space S re state nw advenote ss she O Mesto en fo passed Pass 1 of 1 Errors 0 of 0 Tests Failed 0 Elapsed Time Hit any key to return to the main menu 4 5
88. age 0 8VDC 10 4 Motherboard FIGURE 10 18 shows a block diagram of the Netra T4 motherboard TABLE 10 8 describes the functions of the connectors and jumpers Note Unnumbered connectors in FIGURE 10 18 are not used by the Netra T4 system Chapter 10 Functional Description 10 37 i J3603 J3608 J3604 L an J3601 J2001 L H 1 J0407 A 10 J0406 i o 5 1 J0405 0 J0404 1 J0403 J2202 1 J0401 H 0 J0400 ey J5002 j CPU H slot 0 Pek J0501 J0601 SCSI ports J J3002 f J5301 Enet CPU L o slot 1 J0701 J0801 FC AL 3 J2902 z Battery i i 1 J2103 sEEPROM Eii J3602 J2104 33 MHz PCI 4 J2601 O LOMLite 2J3501 33 MHz PCI 2 J2401 33 66 MHz PCI 1 J2301 4 a FIGURE 10 18 System Motherboard Block Diagram 10 38 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 Note In FIGURE 10 18 unnumbered connectors are not used by the Netra T4 system TABLE 10 8 Motherboard Component Functions Designation Function J0100 DIMM J0101 DIM
89. ags turn Reset Me CPU Test Ecache emory Schizo RIO Test Estar Te ECC Test P Tests BIST System F I2C Fan Run POST Return t nu S ests ests ests S st UP only S requency and CPU Ratio Temperature Smart card o OBP Netra T4 AC100 DC100 Service and System Reference Manual August 2001 Selection 2 enables you to change the test control flags CODE EXAMPLE 2 2 CODE EXAMPLE 2 2 POST Test Control Flags Menu 0 Selection 2 0 0 Return 0 af Run all Tests in this Menu 0 2 Change Test Control Flags 0 3 Toggle Trace Flag c 0 4 Toggle Loop a test flag 1 0 5 Toggle Loop on error flag e 0 6 Toggle Print all error flag p 0 7 Display current state of all flags 0 8 Help on Test Flags 0 Selection Note If diag switch false POST is disabled If diag switch true and diag level max POST runs in max mode If diag switch true and diag level min POST runs in min mode To run POST power cycle the system 2 2 Pre POST Preparation 1 Connect a terminal to the LOM serial port on the Netra T4 server to view POST progress and error messages See Section G 1 Connecting to the LOM Serial Port on page G 1 Note By default the input and output device is the LOM serial port To direct POST output to ttya or ttyb set both input device and output device to ttya or ttyb
90. al 10 27 POST configuring to run 2 3 diagnostics E 1 error messages 2 6 example output E 1 maximum level 2 4 messages 2 1 minimum level 2 4 running 2 3 2 4 test control flags 2 3 power connector J3601 4 6 D 7 J3603 4 6 D 6 power distribution board See PDB power on failure 4 2 Power On Self Test See POST power supply unit See PSU power switch 5 2 pre POST preparation 2 3 probe 4 10 probe scsi 4 10 probe scsi all 4 10 processor module See CPU module prompt OBP 4 9 PSU control signals 10 37 installing 4 2 6 3 LEDs 4 2 AC100 1 10 removing 6 2 R removable media modules 8 10 removing battery 9 13 CPU fan 7 7 Index 4 Netra T4 AC100 Service and System Reference Manual August 2001 CPU module 9 6 DAT drive 8 11 disk drive hot swap 8 3 non hot swap 8 5 drive bay 8 8 DVD ROM drive 8 11 FC AL backplane 8 8 LED assembly 6 10 LOMlite2 card 9 15 memory modules 9 11 motherboard 9 20 PCI card 9 3 PDB 6 5 PSU 6 2 PSU fans 7 4 SCCR 9 17 system switch 6 10 reset configuration 4 9 soft 4 9 running POST 2 4 S SCCR installing 9 17 removing 9 17 SCSI 10 33 cable 11 6 configuration 11 6 external cable 10 35 host adapter 10 34 implementation 11 6 SCSI 2 devices 11 7 supported target devices 10 34 SCSI connector 11 4 serial connector 11 3 serial port 10 27 asynchronous rates 10 29 components 10 28 EIA levels 10 29 functions 10 28
91. al part no 806 1377 10 and the OpenBoot 3 x Quick Reference part no 806 2908 10 Universal Serial Bus USB FC AL drive support New device driver support for PCI prober a 2C USB NVRAM FC AL a ERI a Safari Giga Plane Two gptwo support Autoconfiguration Flash PROM 2MByte divided into quadrants Quadrant 0 Sun Blade 1000 OBP Start address 0 Quadrant 1 Sun Fire E280R OBP Netra T4 OBP Start address 512k Quadrant 2 POST shared Start address 1 0M a Quadrant 3 OBDiag shared Start address 1 5M Flash updates replace two quadrants at a time Quadrant 0 and 1 Quadrant 2 and 3 Support for a Stop A a Stop A on ttya a Stop N emulated by lom gt bootmode reset_nvram a Stop F emulated by lom gt bootmode forth a Stop D emulated by lom gt bootmode diag PCI Buses Two PCI buses are implemented that are fully independent in terms of address and data paths channel engines gptwo memory physical address space I O physical address space and configuration space As the device space is not shared between the two PCI buses you must access the specific PCI node to view its properties 4 8 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 Flash PROM The flash PROM is divided into quadrants that are dedicated to Sun Blade 1000 OBP Sun Fire E280R OBP Netra T4 OBP POST and OBDiag respectively A flash update involves two quadrants either 0 and
92. an subassemblies of the Netra T4 system unit as shown in FIGURE 7 1 The chapter contains the following sections m Section 7 1 PSU Fans on page 7 2 m Section 7 2 CPU Fan Assembly on page 7 5 Caution The plug at the end of the AC power cord is the primary means of disconnection for the Netra T4 AC 100 system Caution To isolate the Netra T4 DC100 system open the circuit breakers in both negative supply conductors 7 1 FIGURE 7 1 Netra T4 System Fans 7 1 PSU Fans The two PSU fans are mounted in a plastic airflow guide at the front of the chassis between the FC AL disk drive assembly and the RMM assembly The two fans and the airflow guide form a single FRU 7 2 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 FIGURE 7 2 PSU Fans Assembly Ald Preparation Before proceeding to remove the PSU fans assembly carry out the following 1 Initiate antistatic precautions See Section 5 5 Antistatic Precautions on page 5 5 2 If the system is running shut it down and remove the power See Section 5 3 2 Powering Off the System on page 5 4 Chapter 7 Fan Subassemblies 7 3 3 Lower the front fascia See Section 5 7 1 Removing the Front Fascia on page 5 11 4 Remove the top access cover See Section 5 6 2 Removing the Top Access Cover on page 5 9 5 Remove the FC AL drive assembly See Section 8
93. ared memory multiprocessor architecture with both processors installed on a single motherboard See FIGURE 10 1 Each UltraSPARC III processor has a memory controller installed within the processor When two UltraSPARC II modules are installed on a Netra T4 system only the memory controller installed in CPU slot 0 is enabled The Netra T4 I O subsystem is designed around a system bus controller SBC ASIC which is a bridge between the Sun CrossBar Interconnect address bus and the 33MHz and 66MHz PCI buses The two PCI buses interface with the FC AL controller and any other boards that are installed in the PCI slots A 33MHz PCI bus PCI B supports SCSI controllers that interface with the internal DVD ROM or DAT drives A 66MHz PCI bus PCI A or EPCI for extended PCI bus supports the Fibre Channel Arbitrated Loop FC AL controller that interfaces with the hard disk drives The 33MHz PCI B I O buses support the Peripheral Component I O 2 PCIO 2 ASIC This ASIC is an interface between the 33 MHz PCI bus external universal serial buses USB the 10 100 Mbit Ethernet ports the boot PROM and the EBus Note EBus is a slow byte wide bus for low speed devices such as the serial port controller the SuperI O controller used primarily as a parallel port interface and the boot PROM A BootBus controller BBC ASIC is connected to both UltraSPARC II modules through a shared BootBus The BBC ASIC bridges the BootBus to the EBus to w
94. ascia See Section 5 7 2 Fitting the Front Fascia on page 5 11 8 12 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 CHAPTER 9 oe Motherboard and Component Replacement This chapter describes how to remove and fit the Netra T4 motherboard and the components that interface directly with the motherboard The chapter contains the following sections Section 9 1 PCI Cards on page 9 2 Section 9 2 Processor Modules on page 9 4 Section 9 3 Memory Modules on page 9 9 Section 9 4 Replaceable Battery on page 9 12 Section 9 5 LOMLite2 Card on page 9 14 Section 9 6 System Configuration Card Reader on page 9 16 Section 9 7 Motherboard on page 9 18 Note The only hot swap components in the Netra T4 system are the hard disks All other components including those described in this chapter require the system to be powered down and electrically isolated before they can be removed or fitted Caution Use proper ESD grounding techniques when handling components Wear an antistatic wrist strap and use an ESD protected mat Store ESD sensitive components in antistatic bags before placing them on any surface Caution The plug at the end of the AC power cord is the primary means of disconnection for the Netra T4 AC100 system Caution To isolate the Netra T4 DC100 system open the circuit breakers on both negative supply conductors 9 1
95. astic cap inserted over one or no pin s of the jumper 10 40 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 10 5 1 Closed Open e opo 1 1 l poe OOPS 23 FIGURE 10 19 Selected Jumper Settings Jumper descriptions include brief overviews of flash PROM jumpers and additional system board jumper and connector blocks Jumpers are identified on the system board by J designations Jumper pins are located immediately adjacent to the J designator Pin 1 is marked with an asterisk in any of the positions shown in the figure below J 2 XXX Jumper designation E O o Pins i OO OO FIGURE 10 20 Identifying Jumper Pins Flash PROM Jumpers Flash PROM jumpers J2103 and J2104 are for reprogramming specific code blocks and remote programming of the flash PROM The following figure shows the flash PROM jumper locations Chapter 10 Functional Description 10 41 FC AL connector J4301 Not Used Flash PROM jumpers a olo J2103 a ojo J2104 Ge ee FIGURE 10 21 Flash PROM Jumper Locations TABLE 10 9 Flash PROM Jumper Settings Default Jumper on Jumper Pins 1 2 Select Pins 2 3 Select Pins Signal Controlled J2103 Write protect Write enable 1 2 FLASH PROM PROG ENABLE J2104 Select No select 1 2 XOR LOGIC SET
96. at is read through an analog to digital converter with an I2C interface Chapter 10 Functional Description 10 19 10 2 6 The multimaster I2C bus is used in the Netra T4 system to connect to the SCCR interface The SCCR performs a 3 3VDC to 5VDC voltage translation to interface with the PDB I2C devices The LOMlite2 module connects into the I2C bus at the PDB and is the second I2C multimaster device See also Section 10 2 6 I2C Bus on page 10 20 Clock Synthesizers The BBC ASIC supports another serial interface to access the clock synthesizers Synthesizers allow frequency margining on the system clock After a power on reset the clock frequency for the system is set at a default low frequency 100 MHz The multiplier in the CPU modules also are set at their lower value The POST OpenBoot PROM software determines the optimal system frequency by reading the I2C EEPROMs on the module and the motherboard The POST OpenBoot PROM software programs the new multiplier values in the CPU processors and adjusts the frequency of the synthesizers A subsequent reset will activate the new multiplier values inside the processors Note The Netra T4 system can accommodate two processors running at different speeds I2C Bus The main purposes of the I2C buses are Environmental control Configuration identification Remote system monitoring Remote system management At boot time the I2C bus is used by POST and OBP to identify the cur
97. aution To isolate the Netra T4 DC100 system open the circuit breakers in both negative supply conductors 6 1 6 1 1 1 Power Supply Unit The PSU is located below the motherboard and is accessed from the rear of the system The method of removal is the same for the AC and DC PSUs Preparation Before proceeding to remove the PSU carry out the following Initiate antistatic precautions See Section 5 5 Antistatic Precautions on page 5 5 6 1 2 If the system is running shut it down and power off the system See Section 5 3 2 Powering Off the System on page 5 4 FIGURE 6 1 Power Supply Unit 6 1 2 Removing the PSU 1 Perform the appropriate steps listed in Section 6 1 1 Preparation on page 6 1 2 Remove the power cord from the PSU 3 Release the three captive Phillips screws colored purple located along the top of the PSU that secure it to the system chassis 6 2 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 6 1 3 Ensure that the system chassis cannot move then pull briefly on the PSU handle to detach the PSU from the Power Distribution Board PDB If you are working on a bench you may require an additional person to hold the system chassis steady while you disengage the PSU Using the PSU handle gently withdraw the PSU from the system chassis and place it on an antistatic mat Note Lay the PSU flat on the mat do not stand it on it
98. bps parallel interface bus Ultra SCSI provides the following m Efficient peer to peer I O bus devices a Mechanical electrical and timing specification definition that support transfer rates of 20Mbytes s or 40Mbytes s corresponding to the data path width of an 8 bit or 16 bit bus respectively m Peak bandwidth of 40Mbytes s with implemented 16 bit bus width The internal SCSI bus is terminated at each end One set of terminators is located close to the DVD ROMOM drive connector on the DVD ROM SCSI cable A second set of terminators is located close to the internal SCSI connector The following figure shows the SCSI bus configuration Chapter 10 Functional Description 10 33 10 2 15 1 10 2 15 2 DVD ROM SCSI drive controller UltraSCSI SCSI bus B f External to chassis connector J2202 FIGURE 10 17 Configuration for the SCSI Bus Host Adapter The host adapter is a QLogic PCI SCSI ASIC The host adapter and all target devices comply with the Ultra SCSI single ended drivers and receivers characteristics The electrical characteristics of the output buffers include Vo output low equals OVDC to 0 5VDC with Iu at 48mA signal asserted Von out high equals 2 5VDC to 3 7VDC signal negated tise rising slew rate equals 520mV ns maximum 0 7 VDC to 2 3 VDC tray falling slew rate equals 520mV ns maximum 2 3 VDC to 0 7VDC The Ultra SCSI electrical characteristic
99. cated on the front and rear system panels provide information about the status of the system and many of its subsystems Refer to Section 1 4 LEDs on page 1 6 for a description of their function 4 3 Drive Failure This section provides hard drive DVD ROM and DAT drive failure symptoms and suggested actions 4 2 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 Symptom A hard drive read write or parity error is reported by the operating environment or customer application A DVD ROM or DAT drive read error or parity error is reported by the operating environment or customer application Action Replace the drive indicated by the failure message The operating environment identifies the internal drives as listed in the following table TABLE 4 1 Internal Drives Identification Operating Environment Address Drive Physical Location and Target cltid0s Left hard drive LiD HA 1 clt2d0s Right hard drive LiD HA 2 c0t 6d0s DVD ROM drive target 6 optional c0t5d0s DAT drive target 5 optional Note The symbol in the operating environment address examples is a numeral between 0 and 7 that describes the slice or partition on the drive Symptom The DVD ROM drive fails to respond to commands Action Test the drive response to the probe scsi command as follows Note To bypass POST type setenv diag switch false at the ok prompt Chapter 4 Troubleshooting 4 3
100. ci 8 700000 ebus 5 flashprom 0 0 eee eee eee eee eee passed Testing pci 8 700000 ebus 5 gpio l1 300600 ee eee ee ee ee ee ee eee passed Testing pcie 3700000 ebus 5 1 2CO1 726 crises sce ea ee oie ele eee ee passed Testing pcer s 700000 ebus 5 T2CO1y SO siete caries ean a ee ad ln ae ee passed T sting pcre sS 700000 network 5 E aeea e e bale wk is Ge ei Us passed Testing pci 8 700000 ebus 5 parallel 1 300278 eee ee eee eee eee passed Testing pci 8 700000 ebus 5 pmc 1 300700 iaaea aea eee ee ee eee eee passed Testing pci 8 700000 ebus 5 rtc 1 300070 ee ee a aa ee ee eee passed Testing perves 700000 SCSACG sii eo eterna aed eee Ria e aad aS a Saw Bde passed Testingy peig 7000 00 SCSL C651 fed ae die ented ate ek wera eae aoe ete eta passed Testing pci 8 700000 ebus 5 serial 1 400000 ee ee eee ee ee ee ee eee passed Testing pc1s 00000 WSbG5 3 erana Pha ai oS ete E trae oe ese elaca bie hla teats passed Hit any key to return to the main menu 4 6 OpenBoot Emergency Procedures The following paragraphs describe how to emulate the functions of the Stop commands from the lom gt prompt 4 6 1 Stop A To emulate Stop A type break at the 1om gt prompt 4 30 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 4 6 2 Stop N To emulate Stop N type bootmode reset_nvram at the lom gt prompt 4 6 3 Stop F To emulate Stop F type bootmode forth at the lom gt p
101. ctions on the PCI bus Master transactions use 256 byte burst transfers Note The byte burst rate is programmable and can vary The PCIO 2 is a multi function PCI device as defined by the PCI specification and it supports a separate configuration space for each of the three interfaces See Section 10 2 7 PCI Bus on page 10 22 for details 10 14 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 10 2 3 3 Ethernet Leaf The Ethernet interface supports two DMA channels for full duplex the PCIO 2 Ethernet interfaces through PHY 6612 and COMBO magnetics and RJ45 connector See Section 10 2 13 Ethernet on page 10 31 for details USB Leaf USB Universal Serial Bus is a standard defined for the PC industry that provides connectivity to low cost low bandwidth peripherals USB defines a tree topology through hub devices although logically it behaves as a bus The USB standard defines two data transfer rates 1 5 and 12 Mbit sec USB supports live connect and disconnect of devices hot plugging The PCIO 2 USB channel engine has a single DMA engine with 1 Kbit of internal buffering It serves as the USB host controller and a hub with four ports As a host controller it manages control flow data flow and connections The PCIO 2 USB host controller programming model is Open HCI compatible EBus Leaf EBus is a byte wide I O bus that provides the ability to interface to instruction set architectu
102. d Do not mix CDE and OpenLook environments The files customtest and customtest_OtherDevices are separate files in the 64 bit version of SunVTS They are installed in opt SUNWvts bin spacv9 and not opt SUNWvts bin as is the case for the 32 bit version The environment variable VTS_PM_PATH is used to locate the pix map files when SunVTS is not installed in the default base directory opt The following tests have been renamed spif gt spiftest pmem gt pmemtest vmem gt vmemtest The following tests are not supported in 64 bit mode a cgl4test m isdntest a tcxtest The physical map view displays only one level of the hierarchy To view the complete hierarchy use the logical view 3 8 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 CHAPTER 4 Troubleshooting od This chapter describes how to troubleshoot possible hardware problems and suggests corrective actions This chapter contains the following topics Section 4 1 Power On Failure on page 4 2 Section 4 2 System LEDs on page 4 2 Section 4 3 Drive Failure on page 4 2 Section 4 4 Power Supply Unit Troubleshooting on page 4 4 Section 4 5 OpenBoot PROM Diagnostics on page 4 7 Section 4 6 OpenBoot Emergency Procedures on page 4 30 Caution Regardless of the position of the ON STBY switch when an AC power cord remains connected to the system hazardous volta
103. d w2100002037653317 0 ssd w2100002037653328 0 rtc 1 300070 i dimm 0 a0 dimm 0 a8 LOM console 1 3083f8 nvram 0 e0 scc reader 0 a6 LOM bus 1 3062f8 idprom 0 e0 fcal backplane 0 a4 PMC 1 300700 ioexp 0 74 ioexp 0 7a gpio 1 300600 hardware monitor 0 56 ioexp 0 72 Hh hardware monitor 0 54 motherboard fru 0 a8 hardware monitor 0 52 fan control 0 48 ioexp 0 4c temperature 0 98 fan control 0 4e cpu fru 0 a2 lomlite2 0 ae temperature 0 30 HH HEE power supply 0 ac cpu fru 0 a0 FIGURE 4 2 Netra T4 System Device Tree 4 14 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 The device tree comprises the Parent Node see TABLE 4 6 the Port ID and the PCI Bus Module PBM Control Space Offset within the System Bus Controller SBC address space for the parent node TABLE 4 6 Parent Node Names Description Child New Name Parent Comments SCSI Bus scsi pci 8 700000 Internal SCSI scsi 6 External SCSI scsi 6 1 USB Bus usb pci 8 700000 Ethernet Bus network pci 8 700000 EBus ebus pci 8 700000 FC AL Bus qlc pci 8 600000 The following values apply to the Netra T4 system m Port ID 8 a PBM Control Space Offset a 600000 for 66 MHz PCI bus Bus A a 700000 for 33MHz PCI bu
104. d Node Name Comment Serial Port serial Old name se Parallel Port off Ebus parallel Old name ecpp LOMlite2 Card lom console General Purpose I O Port gpio I2C Bus i2c Real Time Clock rtc BootBus Controller bbc Flash PROM flashprom Motherboard motherboard Temperature Sensor temperature CPU cpu ID PROM off I2C bus idprom NVRAM off I2C bus nvram Memory DIMM off I2C bus dimm The following device ID field values are assigned to the Netra T4 system m Device ID 4 FC AL m Device ID 5 usb ebus eri serial parallel gpio a Device ID 6 Internal and external SCSI Example FC AL Internal Disk Drive Path pci 8 60000 SUNW qlc 4 fp 0 0 ssd w2100002037653317 0 where from left to right pci represent the PCI bus 8 represents the Netra T4 platform 600000 represents 66MHz PCI qlc represents the FC AL controller driver 4 is the FC AL device number Chapter 4 Troubleshooting 4 17 fp is the FC AL port driver HUB 0 0 are the FC AL HUB device number and FC AL HUB function number ssd represents the disk driver wi is the World Wide ID number Example SCSI Internal Disk Drive Path pci 8 7000000 scsi 6 sd l1 0 where from left to right m pci represent the PCI bus m 8 represents the Netra T4 platform m 700000 represents 33MHz PCI m scsi represents the SCSI controller driver m 6 is the SCSI device number m sd represents the SCSI disk driver m 1 0 are the SCSI device number and SC
105. d continuously while power is supplied to the system Off or reset during power up procedures and illuminated when UNIX is running and the Alarms driver is installed This LED is reset by a hardware Watchdog timeout or whenever the user defined Alarm3 is asserted Illuminated whenever the user defined Alarm is asserted Illuminated whenever the user defined Alarm2 is asserted Illuminated when the input voltage from feeder A is above 37V Off when Input A is below 35V Not used by the AC100 Illuminated when the input voltage from feeder B is above 37V Off when Input B is below 35V Not used by the AC100 Driven by the LOMlite2 module under identified system fault conditions Illuminated when Disk0 is active Illuminated in response to a user request when Disk0 can be removed safely without affecting the system operation Illuminated when the system has identified a fault in DiskO Chapter 1 System Description 1 7 TABLE 1 1 Front Panel System LED Functions Continued LED Icon Legend Color Function Disk1 Active D Green Illuminated when Disk1 is active Disk1 OK to C Blue Illuminated in response to a user request Remove v when disk1 can be removed safely without affecting the system operation Disk1 Fault aS Amber Iluminated when the system has identified a fault in Disk1 1 These LEDs are duplicated on the LOMlite2 card face plate see Section 1 4 2 LOMlite 2 LEDs on page 1 8 2 Lower the fr
106. d from the Chassis 9 22 Netra T4 Logical System Diagram 10 3 UltraSPARC III Processor Functional Block Diagram 10 4 I O Logical Diagram 10 5 Memory Subsystem 10 6 Main Memory Functional Block Diagram 10 8 DIMM Mapping 10 9 SBC Block Diagram 10 12 PCIO 2 Block Diagram 10 14 Ebus 10 16 System Interrupt Block Diagram 10 17 Netra T4 Boot Bus 10 18 I2C Bus 10 21 USB and Parallel Port Functional Block Diagram 10 26 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 mn mn mn n n n mn n nm n n n n mn n mn mn mn n Gn mn al n GURE 10 14 GURE 10 15 GURE 10 16 GURE 10 17 GURE 10 18 GURE 10 19 GURE 10 20 GURE 10 21 GURE 11 1 GURE 11 2 GURE 11 3 GURE 11 4 GURE 11 5 GURE 11 6 GURE 11 7 GURE 11 8 GURE 11 9 GURE 11 10 GURE A 1 GURE D 1 GURE D 2 GURE D 3 GURE D 4 Serial Port Functional Block Diagram 10 28 LOMlite2 Serial Port Functionality 10 30 FC AL Disk subsystem 10 33 Configuration for the SCSI Bus 10 34 System Motherboard Block Diagram 10 38 Selected Jumper Settings 10 41 Identifying Jumper Pins 10 41 Flash PROM Jumper Locations 10 42 Back Panel Connectors AC100 Shown 11 1 DB 25 Parallel Connector 11 2 DB 25 Serial Connectors 11 3 68 Pin SCSI Connector 11 4 Connecting External Mass Storage Devices 11 8 RJ45 TPE Socket 11 8 FC AL Connector 11 9 Twin Series AUSB Connector 1
107. d signals The Sun CrossBar Interconnect address and control signals together with the data signals and the switch control signals are routed through the module connectors The Ultra SPARC III processors directly supports the main memory SDRAM The memory controller is on the same die as the processor The address and control signals for the SDRAM chips originate at the CPU chip pins and are routed to the motherboard through the module connectors Note Only the module in slot CPU0 has an active memory controller The SBC I O ASIC chip interface to the Combined Processor Memory Switch CPMS chips on the motherboard is through a private data bus 72 bits wide of which 8 bits are used for ECC see FIGURE 10 3 LOM Console Serial BBC BootBus Data 72 bits Address Control Interrupts hie 7 PCI 33 MHz Serial f EPCI 66 MHz Parallel PROM d External Connector External Connector TTYA TTY B Internal Drive s DVD ROM FIGURE 10 3 I O Logical Diagram The CPUs contain serial EEPROMs for self identification at boot time The SEEPROM is interfaced through the I2C bus and provides the version of the CPU module the size and speed of the external cache the maximum internal f
108. ddress line transitions 1 FPU Registers 0 P Cache Init l Test walking 1 0 FPU registers FPU Registers Test walking 1 0 FPU registers 1 Test register addressing 1 FSR 0 Test register addressing 1 Test walking 1 FSR register FSR Test walking 1 FSR register 1 Ecache RAM 0 Ecache RAM l Test address up Ord oO Test address up l Test address down Test address down oS Appendix E Example POST Diagnostic Output E 12 CODE EXAMPLE E 1 oo 0 a n Safari ID O Test cell Test data 1 Tes dist 1 Tes reli 1 Tes 1 E Ecache Init diag level Variable Set to max 12 of 17 t cell disturbance urbance t data reliability ability t address line transitions Test address line transitions cache Init 1 Correctable Ecache ECC Test Correctable Ecache ECC Test 1 Uncorrectable Ecache ECC Test Uncorrectable Ecache ECC Test 1 Correctable SW Ecache ECC Test Correctable SW Ecache ECC Test 1 Uncorrectable SW Ecache ECC Test Uncorrectable SW Ecache ECC Test 1 Correctable System ECC Test Correctable 1 U Uncorrectabl 1 Memory addre Memory march CLE Safari regis reg Sy
109. degC 3 CPUO die OK 53degC 4 CPU1 enclosure OK 21degC 5 CPU1 die OK 50degC Overheat sensors 1 PSU OK Circuit breakers 1 SCC OK 2 PSU OK F 4 Netra T4 AC100 DC100 Service and System Reference Manual e August 2001 APPENDIX G Connecting to the Netra T4 Server This appendix describes how to connect a terminal and other equipment to the external ports on your Netra T4 server The appendix contains the following sections a Connecting to the LOM Serial Port on page 1 a Connecting to the Serial Ports on page 2 Connecting to the LOM Serial Port The LOM serial port is the default console port To connect a terminal to the LOM serial RJ 45 port you require one of the following TABLE G 1 RJ 45 male to DB 25 male cable wired as shown in TABLE G 1 CAT5 Ethernet cable RJ 45 male to RJ 45 male part no 530 2961 and an RJ 45 female to DB 25 male adaptor part no 530 2889 wired as shown in TABLE G 1 RJ 45 LOM Port Signal LOM Serial Port Adaptor Pinouts DB 25 Terminal 1 a fF WwW N RTS CTS DTR DSR TXD RXD REF GND REF GND 5 6 3 N C or GND N C or GND G 1 TABLEG 1 LOM Serial Port Adaptor Pinouts Continued RJ 45 LOM Port Signal DB 25 Terminal 6 RXD TXD 2 7 DSR DTR 20 8 CTS RTS 4 To communicate with your Netra T4 server connect the cable from serial port A on your terminal to the LOM serial port on the Netra T4 server 1 Power on you
110. devices and software connected together for information exchange Next generation dual inline memory module An addressable point on a network Each node in a Sun network has a different name A node can connect a computing system a terminal or various other peripheral devices to the network Nanosecond 10 seconds Nonvolatile random access memory A type of RAM that retains information when power is removed from the system In Sun systems contains the system hostID number and Ethernet address In Netra T4 systems this information is stored on the system configuration card OpenBoot PROM A routine that tests the network controller diskette drive system memory cache system clock network monitoring and control registers PCI bus module Peripheral component interconnect bus A high performance 32 or 64 bit wide bus with multiplexed address and data lines PCI to EBus Ethernet controller An ASIC that bridges the PCI bus to the EBus enabling communication between the PCI bus and all miscellaneous I O functions as well as the connection to slower on board functions power distribution board Removable media assembly Can include a card reader CD ROM drive DVD ROM drive 4 mm tape drive a diskette drive and any other 3 5 inch device Process ID Power on reset Power on self test A series of tests that verify that system board components are operating properly Initialized at system power on or when the system is r
111. e m sptest tests the serial sync and async ports m ecpptest tests the parallel ports Chapter 3 SunVTS 3 7 TABLE 3 7 SunVTS Custom Test Test Function cpupmtest This new test checks the CPU power management functionality Note Test failures occur if you run nettest and netlbtest simultaneously 32l Guide to Using SunVTS 4 4 The following guidance notes points are included to help you use SunVTS 4 4 The packages SUNWeswsa SUNWsycfd SUNWesnta and SUNWeswgn are no longer required or supplied for physical mapping support The disktest probe does not premount any partitions by default You can set the environment variable BYPASS_FS_PROBE to zero to force all unmounted partitions to premount Premounting will not take place even if you have enabled it if the disktest probe detects the presence of Veritas or Solstice DiskSuite If you run a media subtest on a disk partition in WriteRead mode data corruption can occur if the partition is shared with other programs An option file created when BYPASS_FS_PROBE was set to 0 may not load when BYPASS_FS_PROBE is set to 1 If required create option files for both states of BYPASS_FS_PROBE SunVTS Kerebos SEAM security is now on by default To turn security off edit the security file opt SUNvts bin sunvts to include a in the HOST section This will make all the listed hosts trusted hosts Physical mapping is supported only on systems that support config
112. e Ethernet tap or hub If the Ethernet cable is not correctly attached the external loopback test will fail test all Sequentially tests system configured Tests are sequentially executed in devices containing selftest device tree order viewed with the show devs command watch clock The watch clock diagnostic displays the result as a seconds counter During normal operation the seconds counter repeatedly increments from 0 to 59 Initialize the watch clock diagnostic by typing the watch clock command at the ok prompt The following code example identifies the wat ch clock diagnostic output message CODE EXAMPLE 4 4 Watch Clock Diagnostic Output Message 0 ok watch clock Watching the seconds register of the real time clock chip It should be ticking once a second Type any key to stop 4 watch net and watch net all The watch net and watch net all diagnostics monitor Ethernet packets on the Ethernet interfaces connected to the system Good packets received by the system are indicated by a period Errors such as the framing error and the cyclic redundancy check CRC error are indicated with an X and an associated error description Initiate the watch net diagnostic is by typing the wat ch net command at the ok prompt and initiate the wat ch net all diagnostic by typing the watch net all command at the ok prompt 4 12 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 4 5
113. e module CKES5 01 RAS2_L ee RAS2_L CS 3 0 CKE2 CKE2 i FIGURE 10 5 Main Memory Functional Block Addr 15 0 a lt a lt ee lt ee lt A lt A lt A lt 576 bit data Diagram ADDR DIMM RASO_L CKEO CSO RAS2_L CKE2 CS2 CASO L WEO_L DATA Netra T4 AC100 DC100 Service and System Reference Manual August 2001 Addr 15 0 gt ADDR DIMM RASO _L CKEO CSO RAS2_L CKE2 CS2 CASO L WEO_L DATA Adar 1 5 9 10 2 2 2 A B J2001 dean SCSI port J2202 J3603 J3608 J3604 J3601 J0407 J0406 J0405 J0404 J0403 J0402 J0401 Ol o 4 o o J0400 CPU slot0O J0501 FIGURE 10 6 DIMM Mapping Memory Configuration J5002 J0601 The following table describes the valid memory configurations TABLE 10 1 Valid Memory Configurations Total Configured Memory Density 512MByte 512MByte 1 0GByte 1 0GByte 1 0GByte 1 5GByte 2 0GByte 2 5GByte Even Bank 0 DIMMs 128MByte empty 128MByte 256MByte empty 256MByte 128MByte 256MByte 512MByte empty 512MByte 128MByte Odd Bank 1 D
114. e PSU is correctly located in the chassis and that the fixing screws are fully tightened 4 4 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 Check the PSU LEDs see Section 1 4 3 PSU LEDs on page 1 10 to verify the status of the PSU Check that the power cable connectors are properly seated at the PDB and motherboard Power on the system Using a DVM check the power supply output voltages See FIGURE 4 1 for the power supply connector location on the motherboard Note All power supply connectors being tested must remain connected to the motherboard and PDB a With the negative probe of the DVM placed on a connector ground GND pin position the positive probe on each power pin b Verify voltage and signal availability as listed in the voltage pin tables If any power pin signal is not present with the power supply active and the power cables between the PDB and motherboard properly connected replace the power supply Chapter 4 Troubleshooting 4 5 J3603 J3608 Chal sD Cho eP 7 1 5 1 2 1 J3601 a J3603_P 3608P sos 2001 on JAT tg a J0406 Eo o
115. e and double precision sqrt on 1 Test single and double precision addition 0 Test single and double precision abs Test single and double precision subtraction 0 Test single and double precision conversion Test single and double precision multiplication 0 FPU Move To Registers 1 Test single and double precision division O Moving SP fp value through all fp registers 1 Test single and double precision sqrt O Moving DP fp value through all fp registers 1 Test single and double precision abs 0 FPU Branch 1 Test single and double precision conversion 0 Testing Branching on fcco0 1 FPU Move To Registers 0 Verify branching a 1 Moving SP fp value through all fp registers O0 Verify no branching a 1 Moving DP fp value through all fp registers O0 Testing Branching on fccl 1 FPU Branch O0 Verify branching on 1 Testing Branching on fcc0 E 28 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 CODE EXAMPLE E 2 diag level Variable Set to min 13 of 15 O0 Verify no branching 1 Verify branching 0 Testing Branching on fcc2 on 1 Verify no branching O Verify branching 1 Testing Branching on fccl O Verify no branching on 1 Verify branching O Testing Branching on fcc3 1 Verify no branching O Verify branching 1 Testing Branching on fcc2 O Verify no branching oa 1l Verify branching
116. e antistatic package Locate the socket in which the DIMM is to be fitted Align the DIMM with the socket noting the orientation of the keyways in the DIMM and the tags in the socket Press down firmly on both corners of the DIMM with your thumbs until the connectors are fully seated in the socket and the levers click into place Continue to fit DIMMs until one or both banks are full FIGURE 9 5 Note All the DIMMs in a single bank must be of the same density Chapter 9 Motherboard and Component Replacement 9 11 7 Refit the top access cover See Section 5 6 3 Fitting the Top Access Cover on page 5 9 K J3603 P u3608P J3604 A B r 4 J3601 J2001 L d J0407 J0406 5 J0405 J0404 J0403 J0402 J0401 J0400 SCSI port J2202 oO o 4 o J5002 CPU slot 0 J0501 J0601 FIGURE 9 5 Memory Banks 9 4 Replaceable Battery The system contains a replaceable lithium battery part number 150 2850 Caution Danger of explosion if battery is incorrectly replaced Replace with only with the same or equivalent type recommended by the manufacturer Dispose of used batteries according to the manufacturer s instructions
117. e it home Lock the drive in the bay by pressing on the drive handle until the drive latch closes This action engages the drive with the FC AL backplane connector Refit the front fascia See Section 5 7 2 Fitting the Front Fascia on page 5 11 Press lt Return gt to answer the last line of Step 1 8 4 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 8 1 4 8 1 5 Preparing to Remove an Unmirrored Root Disk Before proceeding to remove a hard disk drive carry out the following Lower the front fascia See Section 5 7 1 Removing the Front Fascia on page 5 11 Initiate antistatic precautions See Section 5 5 Antistatic Precautions on page 5 5 If the system is running shut it down and remove the power See Section 5 3 2 Powering Off the System on page 5 4 Removing an Unmirrored Root Disk Perform the steps listed in Section 8 1 4 Preparing to Remove an Unmirrored Root Disk on page 8 5 Identify the disk to be remove and the bay in which it is installed Use the World Wide Number WWN or Target ID to identify the disk ls als dev rdsk 2 lrwxrwxrws 1 root root 74 May 10 11 16 dev rdsk c0t1d0s0 gt devices pcit8 600000 SUNW glc 4 fp 0 0 ssd w2100002307652252 0 a raw truncated for clarity 2 lrwxrwxrws 1 root root 74 May 10 11 16 dev rdsk cO0t2d0sl1 gt devices pcit8 600000 SUNW glc 4 fp 0 0 ssd
118. e maximum RS 232 cable length is 15 24m 50 0ft The slew rate changes depending on the speed For speeds less than 100Kbaud the slew rate is set at 5VDC ms For rates greater than 100Kbaud the slew rate is increased to 10 ms This enables maximum performance for the greater baud rates and better signal quality at the lesser baud rates lom console Serial Port The LOMlite2 serial port interfaces through an RJ45 connector on the board plate Host Microcontroller Console C ine Driver Serial Receiver LOMlite 2 FIGURE 10 15 LOMlite2 Serial Port Functionality The major features of the LOMlite2 serial port include Single asynchronous port switchable from LOMlite2 to console Single rate 9600 Baud 8 bit No Parity 1 Stop Bit RS232 RS423 compatibility RTS CTS flow control 10 30 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 10 2 13 10 2 13 1 Ethernet The system supports 10 Mbps 10BASE T twisted pair Ethernet and 100 Mbps 100BASE T Twisted pair Ethernet is provided through an 8 pin RJ45 connector The Ethernet circuitry design is based on a Lucent PHY The PHY chip integrates a 100BASE T physical coding sub layer PCS and a complete 1OBASE T module in a single chip The 100BASE X portion of the PHY IC consists of the following functional blocks Transmitter Receiver Clock generation module Clock recovery module The 10BASE T section of the PHY IC consists of the 10 Mbps tran
119. ebooted Programmable Read Only Memory A type of read only memory ROM that allows data to be written into the device with hardware device called a PROM programmer After the PROM has been programmed it is dedicated to that data and cannot be reprogrammed power supply unit Quad fast Ethernet Redundant array of inexpensive disks Removeable media module Glossary 3 SAI SBC SBus SCC SCCR SCSI SERDES SLVM SRAM STP Sun Crossbar Interconnect SunVTS Synchronization TIP TPE TOD TTL UPA UTP VRMS 10BASE T Serial asynchronous interface System bus controller Serial bus System configuration card System configuration card reader Small computer system interface Serializer deserializer Sun Logical Volume Manager Static random access memory Shielded twisted pair A high speed wide data path super computing architecture that allows independent and simultaneous connections between major system components Validation Test Suite a diagnostic application designed to test hardware The action of forcing certain points in the execution sequences of two or more asynchronous processes to coincide in time A connection that enables a remote shell window to be used as a terminal to display test data from a system Twisted pair Ethernet Time of day A timekeeping integrated circuit Transistor transistor logic UltraSPARC port architecture Provides graphics interconnection Unshielded twisted pair Volt
120. ect the strap as shown in or FIGURE 5 3 M Man Foner ou mpe boere emona G lo BL Eeccooacecacecceee ERR CER EREC COE QS C la amp ES x q a las rad amp h g E gi sace S Ro oa c o AR ise As l j a is ARN oS SEEE EECC a aaas S COD CS cee D4 one co i ALm aA D B sAJ oke e Te e o o e M m o a 4 H o0 j O FIGURE 5 2 Attaching the Antistatic Wrist Strap to the Rear of the Chassis 5 6 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 _ a eos es a REE FIGURE 5 3 Attaching the Antistatic Wrist Strap to the Front of the Chassis 5 7 Chapter 5 Before Servicing the System 5 6 Top Access Cover The top access cover is secured by two captive screws located at the rear of the system FIGURE 5 4 Top Access Cover Only the PSU hard disk drives front fascia and air filter can be accessed without removing the top cover If there is sufficient clearance above the unit and it is mounted on slide rails you should be able to car
121. ector J0406 Connector pin 124 CPMS slice 124 SQ OF e SS DE OE e St SS 0 0 0 0 0 0 0 0 0 0 2 6 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 CHAPTER 3 SunVTS This chapter contains an overview of the Sun Validation Test Suite 4 4 SunVTS diagnostic tool You can use SunVTS to validate a system when troubleshooting and during periodic maintenance This chapter contains the following topics Section 3 1 The Validation Test Suite on page 3 1 Section 3 1 1 SunVTS Requirements on page 3 2 Section 3 1 2 SunVTS References on page 3 2 Section 3 1 3 Installation on page 3 3 Section 3 1 4 New and Modified Features and Options on page 3 3 Section 3 2 SunVTS Tests on page 3 6 3 1 The Validation Test Suite SunVTS Version 4 4 is the Sun online Validation Test Suite supplied with the Netra T4 system SunVTS is a comprehensive software diagnostic package that tests and validates hardware by verifying the connectivity and functionality of most hardware controllers devices and platforms SunVTS can be tailored to run on various types of systems ranging from desktops to servers and has many features that you can customize to meet the varying requirements of differing diagnostic situations 3 1 AA SilyZ SunVTS executes multiple diagnostic tests from a graphical user interface GUI or TT
122. em The external sources for reset include the Power Up reset from the power supply the reset buttons on the motherboard the Superl O watchdog timer and fatal error conditions The reset controller also includes registers that a processor uses to generate an external reset to itself or another processor JTAG Controller BBC is the host for the JTAG controller that includes a programmable master tap controller This enables processors to access the JTAG scan rings in the system by simply executing programmed I O operations to the BBC master tap controller registers The processor s can access the internal scan chain of all the ASICs and perform different levels of testing boundary scan internal scan for ATPG RAM tests and BIST if available The JTAG controller enables an external JTAG master to be connected to the motherboard for controlling all scan rings including the processor s scan ring s and the BBC internal scan ring I2C Buses The BBC supports five master I2C buses and a single multi master I2C bus Small I2C serial EEPROMs make it possible to identify pluggable modules that cannot be identified easily through their regular data path The DIMMs include an I2C serial EEPROM that contains information relative to the size and the speed of the DRAM The CPU modules include an I2C EEPROM which indicates the size of the second level cache and the speed of the processor Sensors on the CPU modules provide temperature data th
123. em Reference Manual August 2001 Test single and double precision addition l Verify buffering Test single and double precision subtraction l Verify coalescing Test single and double precision multiplication 1 Pcache Functional Test single and double precision division 1 FPU Functional Test single and double precision sqrt 1 Test single and double precision addition Test single and double precision abs 1 Test single and double precision subtraction Test single and double precision conversion 1 Test single and double precision multiplication O FPU Move To Registers 1 Test single and double precision division O Moving SP fp value through all fp registers 1 Test single and double precision sqrt O Moving DP fp value through all fp registers 1 Test single and double precision abs O FPU Branch 1 Test single and double precision conversion CODE EXAMPLE E 1 diag level Variable Set to max 15 of 17 on os on on os os 10 Testing Branching on fcc0O 1 FPU Move To Registers O Verify branching 1 Moving SP fp value through all fp registers O Verify no branching 1 Moving DP fp value through all fp registers O Testing Branching on feccl 1 FPU Branch O Verify branching 1 Testing Branching on fcc0O O Verify no branching on 1 Verify branching O Testing Branching on fcc2 a 1 Verify no branching O Verify branching 1 Testing Branching on fccl O Verify
124. emove a memory module carry out the following 1 Initiate antistatic precautions See Section 5 5 Antistatic Precautions on page 5 5 2 If the system is running shut it down and remove the power See Section 5 3 2 Powering Off the System on page 5 4 3 Remove the top access cover See Section 5 6 2 Removing the Top Access Cover on page 5 9 9 10 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 9 3 2 9 99 If necessary disconnect the power cable at J3601 on the motherboard to ease access Removing a Memory Module Perform the steps listed in Section 9 3 1 Preparation on page 9 10 Locate the DIMM s to be removed Press down on the lever at each end of the DIMM socket to eject the DIMM from its socket Hold the DIMM by the top corners and put it upwards out of its socket Place the DIMM on an antistatic mat If you are storing the DIMM place it in an antistatic package preferably its original container Continue to remove DIMMs as required or fit replacements See Section 9 3 3 Installing a Memory Module on page 9 11 If necessary reconnect the power cable at J3601 on the motherboard Refit the top access cover See Section 5 6 3 Fitting the Top Access Cover on page 5 9 Installing a Memory Module Perform the steps listed in Section 9 3 1 Preparation on page 9 10 Remove the DIMM from its protectiv
125. enerated by the CPU module is half the system clock frequency The timing parameters are relative to this clock m System implementation The memory subsystem implementation also defines the timing parameters The term implementation refers to the motherboard and all the chips that are part of the memory bus A given implementation of a Netra T4 system defines a set of timing parameters m Processor clock ratio The UltraSPARC III module clock speed is a multiple x4 x5 or x6 of the system clock Timing parameters are defined in terms of processor clocks which means that the processor frequency must be adjusted before programming the memory timing control registers I O Subsystem The I O subsystem is designed around two bridge ASICs system bus controller SBC and PCIO 2 SBC is the bridge between the Sun CrossBar Interconnect bus and the two PCI buses PCIO 2 is the bridge between the 33MHz PCI bus and USB 10 100 Mbit Ethernet and EBus The graphics slot UPA64S is not used on the Netra T4 system SBC ASIC The SBC ASIC supports the full Sun CrossBar Interconnect protocol The CPU module interface to the 288 bit Sun CrossBar Interconnect data bus is through a 144 bit private data bus at 150MHz for a maximum bandwidth of 2 4Gbyte sec Chapter 10 Functional Description 10 11 SBC is composed of a Sun CrossBar Interconnect interface block and two leaf blocks the UPA645 leaf block is not used in the Netra T4 system a PCI
126. erial ports xxii Typographic Conventions Typeface Meaning Examples AaBbCc123 The names of commands files Edit your login file and directories on screen Use 1s a to list all files computer output You have mail AaBbCc123 What you type when su contrasted with on screen Password computer output AaBbCc123 Book titles new words or terms Read Chapter 6 in the User s Guide words to be emphasized Command line variable replace with a real name or value These are called class options You must be superuser to do this To delete a file type rm filename Netra T4 AC100 DC100 Service and System Reference Manual August 2001 Shell and System Prompts Shell Prompt C shell machine_name C shell superuser machine_name Bourne shell and Korn shell S Bourne shell and Korn shell superuser OpenBoot PROM okt LOMlite2 lom gt 1 In dual processor systems the processor number 0 or 1 is included for example 0 ok Related Documentation Application Title Part Number Installation Netra T4 AC100 DC100 Installation and User s Guide 806 7334 11 User Compliance Netra T4 AC100 DC100 Compliance and Safety Manual 806 7335 11 OpenBoot PROM OpenBoot 3 x Command Reference 806 1377 10 OpenBoot PROM Quick Reference 806 2908 10 Accessing Sun Documentation Online A broad selection of Sun system documentation is located at http www sun com products n solutions hardware docs A complete s
127. es See Section 9 2 2 Removing a CPU Module on page 9 6 Ease the RMM drive assembly forward in the chassis access the PDB connectors See Section 8 3 2 Removing a Removable Media Module on page 8 11 Remove the FC AL drive assembly forward in the chassis to access the PDB connectors See Section 8 2 2 Removing the FC AL Backplane and Drive Bay on page 8 8 Remove the SCCR See Section 9 6 2 Removing the SCCR on page 9 17 Removing the Motherboard Perform the steps listed in Section 9 7 1 Preparation on page 9 18 as required Disconnect the power cable at J3302 on the motherboard Disconnect the power cable at J3303 on the motherboard Disconnect the power cable at J3601 on the motherboard Disconnect the power cable at J3603 on the motherboard Disconnect the RMM power cable at J3608 on the motherboard Disconnect the SCSI data cable at J5002 on the motherboard Disconnect the FC AL data cable at J2901 on the motherboard Disconnect the power interlock cable at J3602 on the motherboard Remove the three screws securing the motherboard to the rear chassis panel Move the motherboard towards the front of the unit to disengage the I O sockets from the rear panel of the chassis See FIGURE 9 11 Ensure that you do not damage the EMI shielding surrounding the I O connectors Carefully lift the motherboard from the chassis and place it on the antistatic mat Lift the le
128. et 4 13 watch net all 4 13 POST 2 1 minimum level of POST 2 4 modem cable 12 2 setting up 12 1 switch settings 12 2 motherboard 9 18 installing 9 23 layout 9 19 removing 9 20 system configuration card 9 18 mounting flanges B 1 N node names 4 15 4 17 O OBDiag 4 9 4 18 menu 4 23 self tests 4 20 starting 4 22 tests 4 25 to 4 30 OBP prompt 4 9 Index 3 OBP diagnostics 4 7 4 18 probe scsi 4 10 probe scsi all 4 10 selected tests 4 12 watch clock 4 12 watch net 4 12 watch net all 4 12 OBP parameters diag level 2 1 2 4 diag out console 2 3 diag switch 2 1 2 3 input device 2 3 output device 2 3 ON STBY switch 4 2 5 2 OpenBoot PROM See OBP output device 2 3 overcurrent protection B 3 B 4 P parallel connector 11 2 parallel port 10 26 electrical characteristics 10 27 external cable 10 27 parts list A 1 PCI bus 4 8 10 22 10 23 devices 4 15 slot to PCI bus mapping 10 23 PCI card 9 2 10 22 10 23 installing 9 3 removing 9 3 slots 9 2 universal 10 23 PDB installing 6 6 removing 6 5 peripheral assemblies 10 25 peripherals 10 24 pin configuration J2901 D 4 J3601 D 7 J3603 D 6 J3604 D 1 J5002 D 3 pinout alarms serial port 11 12 alarms service port connector 11 11 Ethernet connector 11 8 FC AL connector 11 9 parallel connector 11 2 SCSI connector 11 4 serial connector 11 3 USB connector 11 10 port parallel 10 26 seri
129. et of Solaris documentation and many other titles are located at http docs sun com Preface xxiii Ordering Sun Documentation Fatbrain com an Internet professional bookstore stocks select product documentation from Sun Microsystems Inc For a list of documents and how to order them visit the Sun Documentation Center on Fatbrain com at http www fatbrain com documentation sun Sun Welcomes Your Comments Sun is interested in improving its documentation and welcomes your comments and suggestions You can email your comments to Sun at docfeedback sun com Please include the part number 806 7336 11 of your document in the subject line of your email xxiv Netra T4 AC100 DC100 Service and System Reference Manual August 2001 PART Service CHAPTER 1 System Description This chapter lists the main features of the Netra T4 AC100 DC100 server and describes the function of the LEDs located on the front and rear panels The chapter contains the following sections m Section 1 1 System Features on page 1 1 m Section 1 2 System Unit Components on page 1 5 m Section 1 3 Environmental Performance on page 1 5 m Section 1 4 LEDs on page 1 6 The Netra T4 server is a single or dual processor device that uses the UltraSPARC III processor High performance processors High performance disk system memory and I O subsystems High performance peripheral component interconnect
130. eters for the server information such as the Ethernet MAC address HostID and other configuration parameters m It replaces the NVRAM for the storage of configuration variables and other non volatile data If a system configuration card is not present in the SCCR the OBP initialization sequence will abort and a fatal error message is displayed If the card is removed while Solaris is running LOMlite2 detects its absence and initiates an orderly shutdown after 60s Other Peripheral Assembly Options The system supports other peripheral assembly options that can be installed in the system These options can include the DVD ROM drive and DAT drive USB Ports Four USB ports enable you to connect USB peripherals Chapter 10 Functional Description 10 25 Parallel port DB 25 USB Peripherals Parallel EMI port filter USB port pore Superl O PCIO 2 ASIC 1 Serial P ort 2 FIGURE 10 13 USB and Parallel Port Functional Block Diagram 10 2 11 Parallel Port The parallel port is managed by the SuperI O component The parallel port is supported by an IEEE 1284 compliant parallel port controller located on the SuperI O ASIC The parallel port controller is a PC industry standard controller that achieves a 2 Mbits sec Mbps data transfer rate The parallel port controller interface supports the ECP protocol as well as the following a Centronics Provides a widely accepted parallel port interface Compat
131. ff the System on page 5 4 Remove the top access cover See Section 5 6 2 Removing the Top Access Cover on page 5 9 Removing a CPU Module Perform the steps listed in Section 9 2 1 Preparation on page 9 6 Remove the purple plastic CPU shroud cover by holding the tabs to release them and lifting the shroud from the chassis Identify the CPU module to be removed Remove the torque tool from its location inside the chassis See FIGURE 9 2 Use the tool to loosen each knurled torque screw counter clockwise through 360 Turn both screws by hand at the same time until the CPU module is released from the slot Without touching the heat sink and the connectors on the base of the CPU module lift the module out of the CPU shroud and place it on the antistatic mat You can use the plastic faceplate as a handle If you are not immediately fitting a new CPU module continue below otherwise continue with Section 9 2 3 Installing a CPU Module on page 9 7 a Refit the CPU shroud cover by sliding it back into place until the locking tags engage Note that slot CPU0 must always contain a CPU module b Fit a blanking panel in the open slot 9 6 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 92 3 10 Return the torque tool to its storage place in the system chassis Refit the top access cover See Section 5 6 3 Fitting the Top Access Cover
132. ft hand side of the motherboard first to ensure that the capacitors located at the right hand side of the board do not foul the SCCR mountings on the chassis side panel 9 20 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 13 Note the settings of the Flash PROM jumpers J2103 and J2104 so that they can be transferred to a new motherboard oO Q Motherboard Screws mS FIGURE 9 10 Motherboard Fixing Screws Chapter 9 Motherboard and Component Replacement 9 21 FIGURE 9 11 Removing the Motherboard from the Chassis Netra T4 AC100 DC100 Service and System Reference Manual August 2001 9 22 9 7 3 10 11 12 13 14 15 16 17 18 Installing the Motherboard Perform the steps listed in Section 9 7 1 Preparation on page 9 18 as required Remove the motherboard from its protective antistatic packaging and place it on the antistatic mat Set the Flash PROM jumpers J2103 and J2104 to the same settings as those on the motherboard being replaced Locate the motherboard in the chassis with the I O sockets to the rear and move it towards the rear until the sockets engage with the cutouts in the rear panel of the chassis Caution Ensure that you do not damage the EMI shielding Secure the board with the screws removed in Step 10 in the previous section Refit the SCCR
133. g the FC AL Backplane and Drive Bay on page 8 8 6 8 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 FIGURE 6 3 System Switch and LED Assembly 6 9 Chapter 6 Power Subassemblies 6 3 2 6 3 3 Removing the System Switch and LED Assembly Perform the steps as required listed in Section 6 3 2 Removing the System Switch and LED Assembly on page 6 10 Gently prise the board from the four retaining spring loaded pins Apply pressure evenly at each pin during removal to ensure that you do not bend the board Disconnect the ribbon cable at J201 on the LED board Place the assembly on an antistatic mat Installing the System Switch and LED Assembly Perform the steps as required listed in Section 6 3 2 Removing the System Switch and LED Assembly on page 6 10 Reconnect the ribbon cable from J15 on the PDB and J0302 on the LOMlite2 board to J201 on the LED board Locate the assembly on the four mounting pins on the inside of the chassis front panel See FIGURE 6 3 Apply pressure evenly at all four pins until the board is securely located on the pins Refit the top access cover See Section 5 6 3 Fitting the Top Access Cover on page 5 9 6 10 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 CHAPTER 7 Fan Subassemblies p gt gt This chapter contains procedures for removing and replacing the two f
134. gage the lugs and lift it off When handling the access cover ensure that you do not damage the EMI shielding gaskets on the underside of the cover Fitting the Top Access Cover 1 Carry out the appropriate steps listed in Section 5 6 1 Preparation on page 5 9 as required 2 With the fixing screws on the access cover towards the rear of the system chassis locate the lugs on the access cover in the slots on the side panels of the system chassis see FIGURE 5 4 3 Slide the access cover forward to engage the lugs Ensure that the rear of the access cover is flush with the rear of the system chassis 4 Tighten the two captive Phillips screws to secure the access cover Chapter 5 Before Servicing the System 5 9 5 7 Front Fascia The detachable front fascia houses the optional air filter and is fastened to the system chassis at the bottom edge by two plastic tethers You need to detach the fascia completely only to change the filter to avoid dust from the filter being sucked back into the system you can carry out all other procedures by lowering the fascia and leaving the tethers attached Filter Retainer Filter Optional RBM ee Mesh Screen Tether FIGURE 5 5 Front Fascia and Filters 5 10 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 5 7 1 5 7 1 1 Del Removing the Front Fascia Caution Exercise care when opening the fascia You must detac
135. ge is always present within the power supply Caution Wear an antistatic wrist strap and use an ESD protected mat when handling components When servicing or removing system unit components use an antistatic wrist strap with a 10mm press stud connection and attach the antistatic wrist strap to the press stud at the rear or front of the chassis before removing the top access cover Caution Owing to the weight of the unit two persons are required to remove the unit from and replace it in the rack 4 1 4 1 Power On Failure This section provides examples of power on failure symptoms and suggested actions Symptom The system does not power up when you press the ON STBY switch Action Ensure that a PSU is installed and properly seated Check that the three PSU fixing screws have been tightened Ensure that the AC power cord is properly connected to the system and to the wall socket Verify that the wall socket is supplying AC power to the system Press the ON STBY switch If the system does not power on the CPU module s may not be properly seated Inspect the CPU module s for proper seating and press the ON STBY switch again If the AC power wall socket is live and the CPU module s are properly seated but the system does not power on the PSU may be defective Check the status of the PSU LEDs and see Section 4 4 Power Supply Unit Troubleshooting on page 4 4 4 2 System LEDs The system LEDs lo
136. gh the register Test walking 0 through the register 0 DMMU Registers Appendix E Example POST Diagnostic Output E 19 CODE EXAMPLE E 2 diag level Variable Set to min 4 of 15 on 1 DMMU Registers Testing Primary Context oa gt yw l1 Testing Primary Context O Test walking 1 through the register 1 Test walking 1 through the Testing Secondary Context on oO 1 Testing Secondary Context 0 Test walking 1 through the register 1 Test walking 1 through the Testing D TSB 1 Testing D TSB 0 Test walking 1 through the register 1 Test walking 1 through the Testing D TLB Tag Access oO yw m oO wy 1 Testing D TLB Tag Access 0 Test walking 1 through the register 1 Test walking 1 through the Testing Virtual Watchpoint a oO wy l Testing Virtual Watchpoint O Test walking 1 through the register 1 Test walking 1 through the Testing Physical Watchpoint oa oO 0 Test walking 1 through the register 1 Test walking 1 through the 0 4M DTLB RAM 1 4M DTLB RAM 0 Test address up a l Test address up O Test address down l Test address down O0 Test cell disturbance 1 Test cell disturbance 0 8K DTLB RAM 1 8K DTLB RAM O Test address up on l Test address up 0 Test address down l Test address down O0 Test cell disturbance 1 Test cell disturbance 4M DTLB TAG ee est address up 1 Testing Phys
137. gnostics 4 18 OpenBoot Emergency Procedures 4 30 4 6 1 Stop A 4 30 4 6 2 Stop N 4 31 4 6 3 Stop F 4 31 4 6 4 Stop D 4 31 5 Before Servicing the System 5 1 5 1 5 2 5 3 Accessibility 5 1 Tools 5 2 System ON STBY Switch 5 2 5 3 1 Powering On the System 5 2 iv Netra T4 AC100 DC100 Service and System Reference Manual August 2001 5 4 5 5 5 6 5 7 5 8 5 3 2 Powering Off the System 5 4 Disconnection and Isolation 5 5 5 4 1 Netra T4 AC100 System 5 5 5 4 2 Netra T4 DC100 System 5 5 Antistatic Precautions 5 5 5 5 1 Attaching the Antistatic Wrist Strap 5 6 Top Access Cover 5 8 5 6 1 Preparation 5 9 5 6 2 Removing the Top Access Cover 5 9 5 6 3 Fitting the Top Access Cover 5 9 Front Fascia 5 10 5 7 1 Removing the Front Fascia 5 11 5 7 2 Fitting the Front Fascia 5 11 Air Filter 5 12 5 8 1 Removing and Fitting the Mesh Screen 5 12 5 8 2 Replacing the Filter 5 13 Power Subassemblies 6 1 6 1 6 2 6 3 Power Supply Unit 6 1 6 1 1 Preparation 6 1 6 1 2 Removing the PSU 6 2 6 1 3 Installing the PSU 6 3 Power Distribution Board 6 4 6 2 1 Preparation 6 4 6 2 2 Removing the PDB 6 5 6 2 3 Installing the PDB 6 6 System Switch and LED Assembly 6 8 6 3 1 Preparation 6 8 6 3 2 Removing the System Switch and LED Assembly 6 10 6 3 3 Installing the System Switch and LED Assembly 6 10 Contents v 7 Fan Subassemblies 7 1 7 1 PSU Fans 7 2 7 1 1 Preparation 7 3 7 1 2 Removing the PSU Fans
138. gt amp Memory Modules This section describes how to remove and fit the dual inline memory modules DIMMs The DIMMs are located in two banks to the right of the CPU modules see FIGURE 9 4 The banks comprise alternate slots designated 0 even slots and 1 odd slots and all four slots in either or both of the banks must be filled Caution Use proper ESD grounding techniques when handling components Wear an antistatic wrist strap and use an ESD protected mat Store ESD sensitive components in antistatic bags before placing them on any surface Caution When you remove and replace a single DIMM an identical replacement is required The replacement DIMM must be inserted into the same socket as the removed DIMM Caution Each DIMM bank must contain at least four DIMMs of equal density for example four 256Mbyte DIMMs to function properly Do not mix DIMM densities within any bank Caution Handle DIMMs only by the edges Do not touch the DIMM components or metal parts Always wear a grounding strap when handling a DIMM Chapter 9 Motherboard and Component Replacement 9 9 The DIMMs keyed for alignment are available in 128 MByte 256 MByte 512 MByte and 1GByte densities and each bank must contain four DIMMs of the same density However the DIMMs in bank 0 need not be the same as those in bank 1 Memory Modules FIGURE 9 4 Memory Modules 9 3 1 Preparation Before proceeding to r
139. h the plastic locating pegs on the bottom edge of the fascia before lowering it Pull the fascia away from the top of the chassis not more than 2 5cm 1lin using the finger hold in the middle of the fascia Lift the fascia forward and off the locating pegs on the bottom edge of the fascia Swing the fascia forward and down so that it hangs on the two plastic tethers Detaching the Fascia Tethers Squeeze together the sides of each plastic tether and pull it from the system chassis Similarly squeeze together the sides of the tether to detach each locating pin in turn from the retainers on the fascia Fitting the Front Fascia Follow Step 1 through Step 5 if you are refitting the tethers to the fascia otherwise start at Step 6 Insert one side of the locating pin on the tether in the retainer on the fascia Squeeze the sides of the tether together to insert the other locating pin Repeat Step 1 and Step 2 for the other tether Insert the other end of one of the tethers in the corresponding slot in system chassis If the tether is a tight fit squeeze the sides of the tether together Repeat Step 4 for the other tether Chapter 5 Before Servicing the System 5 11 6 Swing the fascia up until it is nearly vertical and insert the locating pegs on the bottom of the fascia in the slots on the system chassis Caution Do not swing the fascia forward once you have inserted the locating pegs
140. he backplane Disconnect the power cable to J0101 on the FC AL backplane The cable is connected to J12 on the PDB Disconnect the I2C cable to J0103 on the FC AL backplane This cable is connected to J13 on the PDB Carefully withdraw the assembly from the chassis and place it on the antistatic mat 8 8 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 8 2 2 1 8 2 3 10 11 12 Removing the Backplane With assembly on the antistatic mat release the two Phillips screws securing the backplane to the drive bay Remove the backplane and place it flat on the antistatic mat Installing the FC AL Backplane and Drive Bay Perform the steps listed in Section 8 2 1 Preparation on page 8 8 as required If the backplane was removed from the drive bay in Step 8 above place the backplane and drive bay on the antistatic mat align the fixing holes on the backplane with those on the rear of the drive bay and refit the two screws Align the assembly with the cutout in the front of the chassis located to the left of the CPU fan Slide the assembly partially into the chassis Reconnect the I2C cable from J13 on the PDB to J0103 on the FC AL backplane Reconnect the power cable from J12 on the PDB to J0101 on the FC AL backplane Reconnect the ribbon data cable from J2901 on the motherboard to J0102 on the FC AL backplane and press it home until the side locking l
141. he Netra T4 System Unit Netra T4 AC100 DC100 Service and System Reference Manual August 2001 TABLE A 1 Netra T4 Field Replaceable Units Ref FRU Number Description 1 501 5893 LOMlite2 Module 2 300 1496 AC PSU AC100 3 540 4795 Power Distribution Board PDB 4 501 5965 System Configuration Card Reader SCCR 5 540 5023 Fan Assembly 80mm PSU 6 370 4360 Fan Assembly 127mm CPU 7 501 5915 LED Card and Switch Assembly 8 540 4794 FC AL Backplane 9 501 5938 Motherboard 10 501 5675 Processor 750 MHz 11 501 4489 Memory Module 128MByte 11 501 5401 Memory Module 256MByte 11 501 5030 Memory Module 512MByte 11 501 5031 Memory Module 1GByte 12 540 4525 FC AL Disk Drive 36GByte 13 390 0028 DDS 4 DAT Drive 14 390 0025 DVD Drive Not shown 501 5656 PCI Card 10 100BaseT Fast Wide UltraSCSI Not shown 501 5019 PCI Card 10BaseT FastEthernet Not shown 375 0006 PCI Card Dual Differential SCSI Not shown 370 2728 PCI Card HSI P 2 0 Not shown 375 0100 PCI Card SAI P 3 0 Not shown 501 3028 PCI Card ATM 155MMF P 4 0 Not shown 501 3027 PCI Card ATM 155 UTP P 4 0 Not shown 501 5406 PCI Card Quad Fast Ethernet II Not shown 501 5373 PCI Card Gigabit Ethernet P 2 0 Not shown 501 5901 PCI Card Gigabit Ethernet MMF P 3 0 Not shown 501 5902 PCI Card Gigabit Ethernet UTP P 3 0 Appendix A Illustrated Parts List A 3 A 4 TABLE A 1 Ref Netra T4 Field Rep
142. hich slow I O devices and the boot PROM are attached The BBC ASIC incorporates an inter integrated circuit I2C bus interface and a JTAG master controller The 12C controller is used to identify the processor modules the DIMMs and for environmental control The JTAG master controller is used for boundary testing on the system board ASIC and processor testing 10 2 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 12C BBC E E m E E gt Memory Subsystem E Address E m E E gt BootGroup Safari Addr Contrl Bus 144 bits Private CPU 0 Bus 300MHz Data 288 bits 576 bits _ Sun epssbpe interconnect LJ Private CPU 1 Bus 144 bits Ebus Flash PROM Serial Parallel l lt gento SuperlO 82532 TTYA TTYB 10 2 1 PHY LU6612 Ethernet USB FIGURE 10 1 Netra T4 Logical System Diagram UltraSPARC III Processor Each UltraSPARC III processor CPU module implements the SPARC V 9 architecture with the Visual Instruction Set VIS extension The CPU module also provides new VIS extensions along with prefetch instructions FIGURE 10 2 is a fu
143. ibility Provides an asynchronous byte wide forward host to peripheral channel with data and status lines used according to their original definitions a Nibble mode Provides an asynchronous reverse peripheral to host channel under control of the host Data bytes are transmitted as two sequential four bit nibbles using four peripheral to host status lines 10 26 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 10 2 12 10 2 12 1 Parallel Port Cables The parallel port cable is IEEE 1284 compliant and consists of 18 pairs of signal wires that are double shielded with braid and foil The maximum length of the parallel port cable is 2m 6 6 feet Electrical Characteristics Drivers operate at nominal 5VDC TTL levels The maximum open circuit voltage is 5 5 VDC and the minimum is 0 5VDC A logic high level signal is at least 2 4 VDC at a source current of 0 32mA and a logic low level signal is no more than 0 4VDC at a sink current of 14mA Receivers also operate at nominal 5 VDC TTL levels and can withstand peak voltage transients between 2VDC and 7VDC without damage or improper operation The high level threshold is less than or equal to 2 0 VDC and the low level threshold is at least 0 8 VDC Sink current is less than or equal to 0 32mA at 2 0VDC and source current is less than or equal to 12mA at 0 8VDC Serial Port The Netra T4 server has three serial ports a Two ports ttya and ttyb are i
144. ical Watchpoint register register register register register register E 20 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 CODE EXAMPLE E 2 a CO o a T O 5o 0O Oo Oo Test Test 4M est Test 4M Test lest w us est 8K Test Test Test diag level Variable Set to min 5 of 15 1 4M DTLB TAG address down cell DTLB 1 1 1 Test address up disturbance Test address down TAG Test cell disturbance address up 1 1 8K DTLB TAG Test address up address down 1 Test address down address line transitions ITLB 1 RAM address up address down cell 1 ITLB 1 1 4M ITLB RAM disturbance Test address up RAM Test address down address up 1 Test cell disturbance address down cell 1 1 ITLB 1 8K ITLB RAM disturbance Test address up Test address down TAG address up 1 Test cell disturbance address down cell ITLB 1 disturbance 1 4M ITLB TAG TAG Test address up address up 1 Test address down address down 1 Test cell disturbance address line transitions 1 8K ITLB TAG Appendix E Example POST Diagnostic Output Test address line transitions E 21 CODE EXAMPLE E 2 O IMMU Init l Test address
145. ice and System Reference Manual August 2001 4 5 2 2 CODE EXAMPLE 4 2 probe scsi all Output Message ok probe scsi all pci 8 600000 SUNW glc 4 LiD HA Port WWN Disk description 3 3 210000203708ad4d SEAGATE ST39102FCSUN9 0G09299906F45038 1 1 210000203700ca78 SEAGATE ST39103FCSUN9 0G01479916021084 pci 8 700000 scsi 6 1 Target 0 Unit 0 Disk SEAGATE ST39173W SUN9 0G2815 pci 8 700000 scsi 6 Target 6 Unit 0 Removable Read Only device TOSHIBA DVD ROM SD M12011B08 ok test alias name device path all The test diagnostic combined with a device alias or device path enables a device self test program If a device has no self test program the message No selftest method for device name is displayed To enable the self test program for a device type the test command followed by the device alias or device path name The following code example identifies the test output message TABLE 4 5 lists test alias name selections their descriptions and their required preparation CODE EXAMPLE 4 3 Test Output Message ok test net Testing net Chapter 4 Troubleshooting 4 11 4 5 2 3 4 5 2 4 TABLE 4 5 Selected OpenBoot PROM On Board Diagnostic Tests Type of Test Description Preparation test net Performs internal external loopback An Ethernet cable must be test of the system auto selected attached to the system and to an Ethernet interfac
146. idth requirements of the serial port controller Note Interrupts are generated when the buffer reaches 32 bytes or half full The line drivers and line receivers are compatible with both RS 232 and RS 423 protocols Software control sets the line drivers and line receivers to either RS 232 or RS 423 protocols The line driver slew rate is also programmable For rates over 100 Kbaud the slew rate is set to 1OVDC usec For rates under 100Kbaud the slew rate is set to 5VDC wsec Serial Port Functions Modem connection to the serial port enables access to the Internet Synchronous X 25 modems are used for telecommunications in Europe An ASCII text window is accessible through the serial port on non graphic systems Low speed printers button boxes for CAD CAM applications and devices that function like a mouse 10 28 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 are also accessible through the serial port The additional speed of the serial port can be used to execute communications with a CSU DSU for a partial T1 line to the Internet at 384Kbaud EIA Levels Each serial port supports both RS 232 and RS 423 protocols RS 232 signaling levels are between 3VDC and 15VDC and 3VDC and 15VDC A binary 1 001 is anything greater than 3 VDC and a binary 0 000 is anything less than 3 VDC The signal is undefined in the transition area between 3 VDC and 3 VDC The line driver switches at 10 VDC and 10 V
147. il the two locking lugs at each end of the connector click into place Refit the CPU shroud See Section 9 2 3 Installing a CPU Module on page 9 7 Refit the FC AL disk drive assembly See Section 8 2 3 Installing the FC AL Backplane and Drive Bay on page 8 9 Refit the RMM assembly See Section 8 3 3 Installing a Removable Media Module on page 8 12 Engage the PSU connector with the PDB by performing Step 4 through Step 6 of the PSU fitting procedure See Section 6 1 3 Installing the PSU on page 6 3 Refit the top access cover See Section 5 6 3 Fitting the Top Access Cover on page 5 9 Chapter 6 Power Subassemblies 6 7 6 3 6 3 1 System Switch and LED Assembly The system switch and LEDs are mounted on a card attached to the front of the chassis by four spring loaded pins see FIGURE 6 3 The LEDs are transmitted to the front fascia by light pipes attached to the inside of the front fascia Preparation Before proceeding to remove the system switch and LED assembly carry out the following Initiate antistatic precautions See Section 5 5 Antistatic Precautions on page 5 5 If the system is running shut it down and remove the power See Section 5 3 2 Powering Off the System on page 5 4 Remove the top access cover See Section 5 6 2 Removing the Top Access Cover on page 5 9 Remove the FC AL drive assembly See Section 8 2 2 Removin
148. ing 5 11 mesh screen 5 12 removing 5 11 tethers 5 11 FC AL backplane 8 6 installing 8 9 removing 8 8 FC AL connector 11 9 flash PROM 4 9 jumper settings 10 42 jumpers 9 21 10 41 functional description system 10 1 functional diagram UltraSPARC MI 10 4 l input device 2 3 installing battery 9 13 CPU fan 7 7 CPU module 9 7 DAT drive 8 12 disk drive hot swap 8 4 non hot swap 8 6 drive bay 8 9 DVD ROM drive 8 12 FC AL backplane 8 9 Index 2 Netra T4 AC100 Service and System Reference Manual August 2001 LED assembly 6 10 LOMlite2 card 9 15 memory modules 9 11 motherboard 9 23 PCI card 9 3 PDB 6 6 PSU 6 3 PSU fans 7 4 SCCR 9 17 SunVTS 3 3 system switch 6 10 isolating the system 5 5 J J3601 connector 4 6 J3603 connector 4 6 jumper settings flash PROM 10 42 jumpers 10 41 flash PROM 10 41 identifying 10 41 L LED assembly 6 8 installing 6 10 removing 6 10 LEDs AC PSU 1 10 DC PSU 1 11 disk drive 1 7 LOMlite2 1 8 PSU 4 2 AC100 1 10 system 1 7 4 2 LOMlite2 card installing 9 15 location 9 14 removing 9 15 LEDs 1 8 updating firmware F 1 M main memory system 10 6 mapping PCI slot to PCI bus 10 23 maximum level of POST 2 4 memory banks 9 12 filling 9 9 numbering 9 9 memory modules 9 9 handling 9 9 installing 9 11 removing 9 11 message diagnostic probe scsi 4 10 probe scsi all 4 11 test 411 watch clock 4 12 watch n
149. ing an existing drive ensure the jumper settings match those on the drive you are replacing Otherwise refer to the documentation enclosed with your drive for information about the settings To refit the DVD R drive a Slide the drive partially into the right hand slot in the RMM drive bay assembly b Align the SCSI connector with the port on the DVD R drive and press the drive into the drive bay until the connector is firmly attached c Reconnect the power cable at the rear of the drive d Tighten the two captive Phillips screws to secure the drive in its bay To refit the DAT drive a Slide the drive into the left hand slot in the RMM drive bay b Tighten the two captive Phillips screws to secure the drive in its bay c Attach the SCSI connector at the rear of the drive and lock the retaining clips over the connector d Reconnect the power cable at the rear of the drive Slide the drive bay assembly partially into the chassis Reconnect the SCSI data cable to the drives at the motherboard Reconnect the power cable to the drives at the motherboard Slide the drive bay assembly fully into the chassis until it is flush with the front panel Refit the four Phillips screws to secure the drive bay assembly to the chassis If necessary fit a plastic cover to any unoccupied drive bay Refit the top access cover See Section 5 6 3 Fitting the Top Access Cover on page 5 9 Refit the front f
150. ith the power supply Chapter 10 Functional Description 10 35 10 3 10 3 1 10 3 2 Power Supply AC100 PSU The 500W autosensing AC power supply has a voltage range of 90 Vims to 254 Vims and a frequency range of 47Hz to 63Hz The maximum input current is 9A at 100V The power supply output voltages are listed in TABLE 10 5 The power supply continues to regulate all outputs for 20ms after AC power is removed TABLE 10 5 AC Power Supply Output Values Output Voltage VDC Max Current A Regulation Band V 1 3 3 38 0 3 23 to 3 43 2 5 0 48 0 4 85 to 5 25 3 12 0 10 0 11 40 to 12 60 4 12 0 0 5 12 60 to 11 40 5 5 0_Standby 1 25 4 75 5 25 DC100 PSU The maximum continuous output power rating is 500W for single or dual input supply The maximum continuous rating per output is shown in TABLE 10 6 TABLE 10 6 DC Power Supply Output Values Output Voltage V Current A Regulation Band V 1 3 3 38 0 3 23 to 3 43 2 5 0 48 0 4 85 to 5 25 3 12 10 0 11 40 to 12 60 4 12 0 5 12 60 to 11 65 5 5 0 1 5 4 75 to 5 25 10 36 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 10 3 3 Control Signals All power supply control signals are at signal levels shown in TABLE 10 7 TABLE 10 7 Power Supply Control Signal Levels Parameter Min Max Von high level output voltage 3 4VDC Vor low level output voltage 0 4VDC Vin high level input voltage 2 4VDC Vit low level input volt
151. l 5 3 1 2 Netra T4 DC100 System 1 Insert both DC input connectors 2 Close both DC circuit breakers 3 Momentarily set the front panel ON STBY system switch to the ON position and hold it until the system starts to power up Chapter 5 Before Servicing the System 5 3 5 3 2 5 3 2 1 5 3 2 2 Powering Off the System Caution Before you turn off power to the system back up the files and exit from the operating environment Failure to do so may result in data loss Where necessary notify the users that the system is going down Netra T4 AC100 System Follow step a or b as appropriate a Halt the operating environment Set the ON STBY switch at the front of the system to the STBY D position and hold it until the system shuts down this can take several seconds or use the LOMlite2 poweroff command or OBP power off command b Set the ON STBY switch at the front of the system to the STBY position and release it immediately to initiate a clean shut down followed by a power off Verify that the Power LED is off Disconnect the AC power cord from the rear of the system Caution Regardless of the position of the ON STBY switch when an AC power cord remains connected to the system hazardous voltage could be present within the power supply Netra T4 DC100 System Follow step a or b as appropriate a Halt the operating environment Set the ON STBY switch at the front of the s
152. laceable Units Continued FRU Number Description Not shown Not shown Not shown Not shown Not shown Not shown Not shown Not shown Not Shown Not Shown 501 5426 PCI Card Combined FC AL and Gigabit Ethernet 375 0130 PCI Card SSL Crypto Accelerator 375 3019 PCI Card Single FC Network Adaptor 370 3868 PCI Card Cluster SCI PCI 64 Adaptor 375 0078 PCI Card H W RAID Controller 375 0005 PCI Card Dual Channel SE UltraSCSI 540 4372 Redundant FC 8 Port Switch 560 2631 Cable Kit Power 560 2632 Cable Kit Data 530 3032 Power Cable 1 Also an optional component TABLE A 2 Ref 10 11 11 11 11 12 13 14 Not shown Not shown Not shown Not shown Not shown Not shown Not shown Not shown Netra T4 Optional Components Part Number Description X6990A Processor 750 MHz X7050A 512MByte Memory Expansion 4 x 128 MByte DIMMs X7053A 1GByte Memory Expansion 4 x 256 MByte DIMMs X7051A 2GByte Memory Expansion 4 x 512MByte DIMMS X7052A 4GByte Memory Expansion 4 x 1GByte DIMMS X6724A 36GByte FC AL Disk Drive X6295A DDS 4 DAT Drive X6168A DVD R Drive 10x X1032A PCI Card 10 100BaseT Fast Wide UltraSCSI X1033A PCI Card 10BaseT FastEthernet X6541A PCI Card Dual Differential SCSI X1155A PCI Card HSI P 2 0 X2156A PCI Card SAI P 3 0 X1157A PCI Card ATM 155MMF P 4 0 X1158A PCI Card ATM 155UTP P 4 0 X1034A PCI Card Quad Fast Ethernet Netra T4 AC100 DC100 Service a
153. lign with the cut outs in the chassis then slide the PDB towards the rear of the chassis to engage the hooks Tighten the single captive Phillips screw to secure the PDB to the chassis Reconnect the ON STBY switch and LED cable at J15 on the PDB by inserting the connector in the socket and closing the retaining lugs at each end of the socket Reconnect the power interlock cable from J14 on the PDB to J3602 on the motherboard Reconnect the cable from J8 on the PDB to J3303 on the motherboard Reconnect the cable from J10 on the PDB to J3302 on the motherboard Reconnect the FC AL drive fan to J16 on the PDB 6 6 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 10 11 12 13 14 15 16 17 18 19 Refit the PSU fan assembly See Section 7 1 3 Installing the PSU Fans Assembly on page 7 4 Refit the CPU fan assembly See Section 7 2 3 Installing the CPU Fan Assembly on page 7 7 Reconnect the I2C ribbon cable from J3604 on the SCCR board to J4 on the PDB by inserting the connector in the socket and closing the retaining lugs at each end of the socket Reconnect the small white 14 way power cable from J3603 on the motherboard to J3 on the PDB by inserting the connector until the central locking lug at the back of the connector clicks into place Reconnect the large black 14 way power cable from J3604 on the motherboard to J2 on the PDB by inserting the connector unt
154. lists the connector pinouts Chapter 11 External I O Connectors 11 11 FIGURE 11 10 RJ45 Lights Out Management Serial Connector TABLE 11 10 Lights Out Management Serial Connector Pinout Pin Signal Name Pin Signal Name 1 RTS 5 REF 0V 2 DTR 6 RXD 3 TXD Z DSR 4 REF 0V 8 CTS Shell CHGND 11 8 System Configuration Card Reader The slot for system configuration card is located at the extreme left hand side of the rear panel see FIGURE 11 1 11 12 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 CHAPTER 12 Modem Setup Any modem compatible with CCITT V 24 can be connected to the Netra T4 serial ports Modems can be set up to function in one of three ways a Dial out only m Dial in only m Bidirectional calls 12 1 To Set Up the Modem To set up your modem Become root and type admintool ae su Password admintool Click on Serial Port Manager Select Port a or Port b for your modem connection Click on Edit The Serial Port Manager Modify Service window is displayed Choose the Expert level of detail 12 1 From the Use Template menu choose one of the following a Modem Dial Out only b Modem Dial In only c Modem Bidirectional Click on Apply Set your modem auto answer switch to one of the following a Off Dial Out Only a On Dial In Only a On Bidirectional 12 2 Serial Port Speed Change
155. m the var tmp directory confirm that it contains the file 1102018 lt version gt tar and then run a checksum to confirm that it has been copied correctly cksum 110208 lt version gt tar 123456789 1076224 110208 lt version gt tar Note Your checksum will be different If the checksum is not correct the file is corrupt 7 Extract the files from the patch tar xf var tmp 110208 lt version gt tar 8 Install the new patch patchadd 110208 lt version gt 9 Reboot the system F 2 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 10 To update the LOMlite2 firmware at the Unix prompt type lom G default Note This process takes about five minutes Do not turn off the system while the update is progressing Press Return to redisplay the Unix prompt 11 Enter to change to the LOMlite2 prompt t lom gt 12 Run the ver command to confirm that the firmware has been updated lom gt ver 13 Finally check the functionality by running the env command from the lom gt prompt Appendix F Updating LOMlite2 Firmware F 3 lom gt env LEDs 1 Power ON 2 Fault ON 3 Supply A OFF 4 Supply B OFF 5 PSU ok ON 6 PSU fail OFF Alarms ikea OFF 205 OFF 37 ON PSUS 1 AC OK Fans 1 PSU1 OK speed 88 2 PSU2 OK speed 86 3 CPU OK speed 94 Temperature sensors 1 Ambient OK 21degC 2 CPUO enclosure OK 22
156. memtst pg addr port B O memtst pg addr port A l memtst sbuf addr port B O memtst sbuf addr port A 1 Schizo merg test 0 Schizo merg test l merg_wr 8 byte port B O merg_wr 8 byte port A l merg_wr 4 byte port B O merg_wr 4 byte port A l merg_wr 2 byte port B O merg_wr 2 byte port A l merg_wr 1 byte port B O merg_wr 1 byte port A l merg_blkwr block port B merg_blkwr block port A PCI B space for RIO RIO Config 1 Icache Functional Verify cacheline fill on read miss Appendix E Example POST Diagnostic Output E 13 E 14 CODE EXAMPLE E 1 a AN ANOS OOS E a O Verify O Verify a Verify no Verify oa oa on a O Dcache Functional Verify set associativity Wceache Functional 1 Deache Functional diag level Variable Set to max 14 of 17 allocate on write miss fetch from memory on read miss 1 Verify no allocate on write miss write through on write hit write through fetch on read miss 1 Verify write through on write hit Verify cacheline fill on write miss Verify buffering Verify coalescing Pcache Functional 1 Wceache Functional 0 FPU Functional 1 Verify cacheline fill 1 Verify set associativity 1 Verify cacheline fill on read miss 1 Verify fetch from memory on read miss l Verify write through fetch on read miss on write miss Netra T4 AC100 DC100 Service and Syst
157. moving the Top Access Cover on page 5 9 Remove all memory modules See Section 9 3 2 Removing a Memory Module on page 9 11 Remove the LOMLite 2 alarms card See Section 9 5 2 Removing the LOMlite2 Card on page 9 15 9 18 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 A B J2001 SCSI port J2202 J3001 SCSI ports J3002 J5301 Enet FC AL J2902 J3603 J36087 J3604 J3601 a i J0407 a 0 J0406 r a Ti J0405 0 J0404 1 J0403 To J0402 1 J0401 0 J0400 J5002 CPU slot 0 J0501 J0601 CPU slot 1 opnon0oo J0701 J2104 33 MHz PCI 4 J2601 LOMLite 2J3501 33 MHz PCI 3 J2501 33 MHz PCI 2 J2401 33 66 MHz PCI 1 J2301 FIGURE 9 9 Motherboard Layout J0801 Battery SEEPROM J3602 O J2901 O Chapter 9 Motherboard and Component Replacement 9 19 97 2 10 10 11 12 Remove all PCI cards See Section 9 1 2 Removing a PCI Card on page 9 3 Remove all CPU modul
158. ncorporated in the motherboard a A single serial port lom console is incorporated in the LOMlite2 board ttya and ttyb The motherboard serial ports are synchronous and asynchronous with full modem controls Motherboard serial port functions are controlled by a serial port controller that is electrically connected to the system through the EBus Line drivers and line receivers control the serial port signal levels and provide RS 232 and RS 423 compatibility Each motherboard serial port interfaces through its own DB 25 connector The major features of each motherboard serial port include Two fully functional synchronous and asynchronous serial ports DB 25 connectors Increased baud rate to 384Kbaud synchronous 460 8 Kbaud asynchronous Variable edge rate for greater performance EBus interface The following figure shows a functional block diagram of the serial port Chapter 10 Functional Description 10 27 Li Serial port A ple DB 25 POLA receiver EMI RS 232 423 select filter ees Serial port p gt controller Line __ driver gt Serial port B DB 25 Slew rate select EMI filter lt Line lt _ _ rene receiver FIGURE 10 14 Serial Port Functional Block Diagram Serial Port Components Serial port components include a serial port controller line drivers and receivers The serial port controller contains sixty four byte input and output buffers that are used to reduce the CPU bandw
159. nctional block diagram of the UltraSsPARC III processor DVD ROM Chapter 10 Functional Description 10 3 The CPU is physically mounted on a module that plugs vertically into the system motherboard The module contains the processor and eight external cache SRAMs available either as 4 Mbyte 8 x 4 Mbit SRAMs or as 8 Mbyte 8 x 8 Mbit SRAMs The module also includes a DC to DC converter to limit the current density in the connector at the male female interface and provide better power regulation at the pins of the processor CPU Modules 12C JTAG t BBC Ebus Memory Subsystem lt CPMS CPMS CPMS CPMS m CPMS CPMS 576 bits Sun Crossbar Interconnect Data Bus internal FIGURE 10 2 UltraSPARC III Processor Functional Block Diagram The base CPU module frequency is 750 MHz Note The two UltraSPARC III CPUs need not run at the same frequency Each CPU module plugs vertically into the motherboard through a set of two connectors Each module is equipped with a mechanical insertion extraction mechanism 10 4 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 The processors are interconnected through the Sun CrossBar Interconnect bus but the CPU module s only support the Sun CrossBar Interconnect address and comman
160. nd System Reference Manual August 2001 TABLE A 2 Netra T4 Optional Components Continued Ref Part Number Description Not shown X1141A PCI Card Gigabit Ethernet P 2 0 Not shown X1150A PCI Card Gigabit Ethernet UTP P 3 0 Not shown X1151A PCI Card Gigabit Ethernet MMF P 3 0 Not shown X6799A PCI Card Single FC Network Adaptor Not shown X1133A PCI Card SSL Crypto Accelerator Not shown X2069A PCI Card Combined FC AL and GBE Not shown X1074A PCI Card Cluster SCI PCI 64 Adaptor Not shown X6542A PCI Card H W RAID Controller Not shown X6540A PCI Card Dual Channel SE UltraSCSI Not shown X6746A Redundant FC 8 Port Switch 15 X7006A Filter Pack 10 16 X7007A Front Bezel Appendix A Illustrated Parts List A 5 A 6 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 APPENDIX B Product Specification This appendix defines the physical electrical and environmental requirements for installing the Netra T4 AC100 system The appendix contains the following sections m Section B 1 Physical Specification on page B 1 m Section B 2 Electrical Specification on page B 2 m Section B 3 Environmental Specification on page B 4 B 1 Physical Specification B 1 1 Dimensions Dimension include the front fascia and PSU handle m Width 445 2mm 17 53in a Depth 508 1mm 20 00in a Height 176 6mm 6 95in 4RU B 1 2 Mounting Flanges 19 inch 23 inch 24 inch 600 mm
161. no branching A 1 Verify branching O Testing Branching on fcc3 a 1 Verify no branching O Verify branching 1 Testing Branching on fcc2 O Verify no branching oa 1l Verify branching Ecache Functional a 1 Verify no branching O Verify cacheline fill on read miss 1 Testing Branching on fcc3 O Verify write allocate on write miss l Verify branching O Verify cacheline update on write hit l Verify no branching O Verify write back 1 Ecache Functional 1 Verify cacheline fill on read miss 1 Verify write allocate on write miss 1 Verify cacheline update on write hit 1 Verify write back O Xcall Test 0 Sending Cross Calls to CPU AID 1 1 POST_END OBP 4 2 3 2001 04 23 17 48 Sun Netra T4 Appendix E Example POST Diagnostic Output 15 E 16 CODE EXAMPLE E 1 diag level Variable Set to max 16 of 17 Clearing TLBs Done POST Results Cpu 0 700 0000 0000 0000 0000 Sol 0000 07f 015 06b0 o2 0000 0000 0000 0000 POST Results Cpu 1 200 0000 0000 0000 0000 sol 0000 07f 015 06b0 o2 0000 0000 0000 0000 Membase 0000 0000 0000 0000 MemSize 0000 0000 0010 0000 Init CPU arrays Done Init E tags Done Setup TLB Done MMUs ON Copy Done PC 0000 07ff 008 4200 PC 0000 0000 0000 4278 Decompressing Done Size 0000 0000 0007 24b0 ttya initialized Start Reason Initialize Machine C
162. nstalling the Battery 9 13 LOMLite2 Card 9 14 9 5 1 Preparation 9 15 9 5 2 Removing the LOMlite2 Card 9 15 9 5 3 Installing the LOMlite2 Card 9 15 System Configuration Card Reader 9 16 9 6 1 Preparation 9 16 9 6 2 Removing the SCCR 9 17 9 6 3 Installing the SCCR 9 17 Motherboard 9 18 9 7 1 Preparation 9 18 9 7 2 Removing the Motherboard 9 20 9 7 3 Installing the Motherboard 9 23 System Reference Functional Description 10 1 10 1 System 10 1 10 2 System Overview 10 2 Contents vii 10 2 1 UltraSPARC III Processor 10 3 10 2 2 Main Memory 10 6 10 2 3 I O Subsystem 10 11 10 2 4 Interrupts 10 16 10 2 5 BootBus 10 17 10 2 6 I2C Bus 10 20 10 2 7 PCI Bus 10 22 10 2 8 Peripherals 10 24 10 2 9 Other Peripheral Assembly Options 10 25 10 2 10 USB Ports 10 25 10 2 11 Parallel Port 10 26 10 2 12 Serial Port 10 27 10 2 13 Ethernet 10 31 10 2 14 FC AL Subsystem 10 32 10 2 15 SCSI 10 33 10 2 16 SuperI O 10 35 10 3 Power Supply 10 36 10 3 1 AC100 PSU 10 36 10 3 2 DC100 PSU 10 36 10 3 3 Control Signals 10 37 10 4 Motherboard 10 37 10 5 Jumper Descriptions 10 40 10 5 1 Flash PROM Jumpers 10 41 11 External I O Connectors 11 1 11 1 Parallel Connector 11 2 11 2 Serial Connectors 11 3 11 3 SCSI Connector 11 4 11 3 1 SCSI Implementation 11 6 11 3 2 SCSI Cabling and Configuration 11 6 viii Netra T4 AC100 DC100 Service and System Reference Manual August 2001 12 11 4 Ethernet Connector 11 8 11 5 FC AL Connector 11 9 11
163. o the corresponding slots on the fascia Carefully swing the other side down until the catches on the screen engage with the fascia Re attach the fascia to the system chassis See Section 5 7 2 Fitting the Front Fascia on page 5 11 Replacing the Filter If not already removed detach the front fascia and place it on a workbench away from the immediate vicinity of the system See Section 5 7 1 Removing the Front Fascia on page 5 11 Release the two clips securing the filter retainer and lift it from the fascia Remove the filter and carefully dispose of it Clean the fascia to remove any remaining dust Insert a new filter and secure it with the retainer Re attach the fascia to the system chassis See Section 5 7 2 Fitting the Front Fascia on page 5 11 Chapter 5 Before Servicing the System 5 13 5 14 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 CHAPTER 6 Power Subassemblies gt gt This chapter describes procedures for removing and replacing the power subassemblies of the Netra T4 system unit The chapter contains the following sections m Section 6 1 Power Supply Unit on page 6 1 m Section 6 2 Power Distribution Board on page 6 4 m Section 6 3 System Switch and LED Assembly on page 6 8 Caution The plug at the end of the AC power cord is the primary means of disconnection for the Netra T4 AC100 system C
164. obing pci 8 700000 Device Probing pci 8 700000 Device Probing pci 8 700000 Device Probing pci 8 700000 Device Probing pci 8 700000 Device e 4 1 5 6 1 2 3 4 40 96 MB 4 Way SUNW qlc fp disk Not hing t network u scsi disk hing t hing t hing t hing t here sb tape scsi disk tape here here here nere CODE EXAMPLE E 2 is a typical POST output for a system with two 750 MHz CPUs and 4GByte of memory and with the diag level variable set to min CODE EXAMPLE E 2 0 nn Oo o oo Oo 0 O TDG 2 CO je Configure I2C controller 0 Configure I2C controller 1 POST v4 1 7 01 22 2001 06 55 PM diag level Variable Set to min 1 of 15 1 Transfered from OBP or Unknown source of reset PLL reset I2C Controller Loopback Test Read JTag IDs of all ASICs BBCJTag ID SCSIJTag ID I RIOJTag SchizoJTag ID 1483203b 15060045 chipJTag ID dle203b ID 13e5d03b 1824c06d Appendix E Example POST Diagnostic Output CODE EXAMPLE E 2 CPMSJ1 CPMSJ1 CPMSJ1 CPMSJ1 CPMSJ1 CPMSJ1 ag ag ag ag ag ag diag level Variable Set to min 2 of 15 ID ID ID ID ID ID ae a 1 11 J 1 42903b 142903b 142903b 42903b 142903b 142903b Read J
165. odem 12 2 SCSI 11 6 cable lengths STP 5 11 9 circuit breakers B 3 configuration reset 4 9 connector alarms serial port 11 11 alarms service port 11 11 Ethernet 11 8 FC AL 11 9 J2901 D 4 J3601 4 6 D 7 J3603 4 6 D 6 J3604 D 1 J5002 D 3 parallel 11 2 SCSI 11 4 serial 11 3 USB 11 10 CPU module handling 9 4 installing 4 2 9 7 removing 9 6 slots 9 4 UltraSPARC MI 10 3 D DAT drive installing 8 12 Index 1 removing 8 11 DC power requirements B 3 DC PSU DC output 10 36 LEDs 1 11 device ID fields 4 17 device tree 4 14 diag level 2 1 2 4 4 19 diagnostics OBP 4 7 SunVTS 3 6 to 3 8 watch clock 4 12 diag out console 2 3 diag passes 4 19 diag switch 2 1 2 3 dimensions 1 1 B 1 DIMMS density 9 10 disk drive 8 1 hot swap 8 2 installing 8 4 removing 8 3 identification 4 3 LEDs 1 7 non hot swap installing 8 6 removing 8 5 disk drive failure 4 2 drive bay installing 8 9 removing 8 8 drive bay assembly 8 6 DVD ROM drive failure 4 2 installing 8 12 removing 8 11 E electrical specification B 2 environmental specification B 4 error messages POST 2 6 Ethernet 10 31 external cable 10 32 TPE connectivity 11 9 Ethernet connector 11 8 external cables lengths 11 9 parallel port 10 27 F failure disk drive 4 2 DVD ROM drive 4 2 power on 4 2 fans CPU installing 7 7 removing 7 7 PSU installing 7 4 removing 7 4 fascia 5 10 fitt
166. of the system including the CPU module s motherboard memory and some on board I O devices and generates messages that can be useful in determining the nature of a hardware failure POST can be run even if the system is unable to boot POST detects most system faults and is located in the motherboard OpenBoot PROM POST can be set to run by the OpenBoot program at power up by setting two environment variables the diag switch and the diag level flag which are stored on the System Configuration Card POST diagnostic and error message reports are displayed on a console 2 1 ae 2 2 m diag switch is set to true default is false m diag level is set to min max or menus default is min If diag level is set to min or max POST performs an abbreviated or extended test respectively see Section 2 4 POST Diagnostic Levels on page 2 4 If diag level is set to menus a menu of all the tests executed at power up is displayed CODE EXAMPLE 2 1 CODE EXAMPLE 2 1 How to Use POST POST runs automatically when the system power is applied and following an automatic system reset if both of the following conditions apply POST Test Menu Xcall Test Sending Cross Calls to CPU AID 1 Maa OM ooon eA WNHE OO Hh 10 Selection Re Run all Tests in this Menu Change Test Control Fl
167. onfiguring the machine OBP 4 2 3 2001 04 23 17 48 Sun Netra T4 Clearing TLBs Done Loading Configuration Membase 0000 0000 0000 0000 MemSize 0000 0001 0000 0000 Init CPU arrays Done Init E tags Done Setup TLB Done MMUs ON Block Scrubbing Done Copy Done PC 0000 07ff f008 4200 PC 0000 0000 0000 4278 Decompressing Done Size 0000 0000 0007 24b0 ttya initialized Start Reason First start after Power On System Reset SPOR PLL Probing gptwo at 0 0 SUNW UltraSPARC III 750 MHz 5 1 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 8 MB CODE EXAMPLE E 1 memory controller Probing gptwo at 1 0 SUNW UltraSPARC III memory controller Probing gptwo at 8 0 pci pci Loading Support Packages Loading onboard drivers dimm fru kbd translator ebus flashprom bbc power i2c dimm fru diag level Variable Set to max 17 of 17 750 MHz 5 1 8 MB dimm fru dimm fru dimm fru dimm fru dimm fru dimm fru i2c cpu fru temperatur hardware monitor temperatur mo cpu fru hardware monitor hardware monitor fan control ioexp fan control therboard fru ioexp ioexp iocexp fcal backplane scc reader power supply lomlite2 nvram idprom beep rtc gpio pmc parallel lombus SUNW lomc serial lomp lomv Memory Configuration Segment Base 0 Siz SUNW Netra T4 Probing pci 8 600000 Device Probing pci 8 600000 Device Probing pci 8 700000 Device Pr
168. onnector SuperI O Self Test m ECP and EPPP mode parallel port test requires loopback connector SuperI O Self Test m Advanced power controller Real time clock TOD test SCSI 53C875 Self Test SCSI 53C875 register test SCSI timer test SCSI DMA test SCSI loopback test SCSI wide transfer test SCSI BIST test SCSI 53C875 Self Test SCSI 53C875 register test SCSI timer test SCSI DMA test SCSI loopback test SCSI wide transfer test SCSI BIST test Serial SAB 82532 Self Test m Internal loopback test m External loopback test RIO USB Self Test m PCI configuration space register test m USB HCI register test m Reset test Chapter 4 Troubleshooting 4 21 4 5 4 2 Starting the OBDiag Menu OBDiag is started from the ok prompt and builds a dynamic menu created from the device tree including those devices that have associated self tests To start OBDiag 1 At the ok prompt type ok setenv mfg mode on mfg mode on 2 Then type ok setenv diag switch true diag switch true Q Then type ok setenv auto boot false auto boot fals A Then type ok reset all Verify that the platform resets see the following code example ol CODE EXAMPLE 4 9 Typical reset al1 Screen Output ok reset all Resetting screen not found keyboard not found eyboard not present Using lom console for input and output Start Reason Soft Reset Sy
169. ont fascia to view these LEDs 1 4 2 LOMlite 2 LEDs The LOMlite2 status LEDs which mirror the alarm status and power LEDs on the front panel are located on the rear of the system between the LOMlite2 DB 15 alarms relay port and RJ45 serial port as shown in FIGURE 1 3 TABLE 1 2 LOMlite2 Status LED Functions LED Icon Legend Color Alarm 1 1 Amber Alarm 2 2 Amber Fault 4 Amber System SYS Green Function Illuminated when user defined Alarm 1 is asserted Illuminated when user defined Alarm 2 is asserted Driven by the LOMlite 2 card and illuminated when a system fault condition exists Illuminated when Solaris is running and the LOMlite2 driver is installed Off while the system is powering up Reset by watchdog timeout assertion of user defined Alarm 3 1 8 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 Alarms Service Port C LEDs Serial Port CA Cj orendi System Contgurton Ga O O E il i B B u C qe ERER Rci YLI C C e a RS SOR BOO R ORA amp x Ga Q ic a q g ag Q a a 7 amp
170. oot 74 May 10 11 16 dev rdsk cO0t2d0sl1 gt devices pcit8 600000 SUNW glc 4 fp 0 0 ssd w2100002307653317 0 a raw truncated for clarity m For internal FC AL disks Target ID Number Disk Bay Number m For external FC AL disks Target ID Multipack ID x 8 Drive Bay Number 5 Push the disk drive latch downwards to release the drive handle Chapter 8 Storage Devices 8 3 8 1 3 Using the drive handle ease the drive from the drive bay until you feel the drive connector disengage from the FC AL backplane connector Holding the disk by the handle slide the disk drive out of the bay Support the weight of the drive with your other hand to avoid unnecessary pressure on the drive handle Place the disk drive on an antistatic mat Hot Swapping a Disk Drive Installation Logically add the drive to the FC AL bus by typing luxadm insert_device The list of devices which will be inserted is 1 Device dev rdsk cl1lt2d0s2 Please enter q to Quit or lt Return gt to Continue Stopping dev rdsk cltldos2 Done Offlining dev rdsk ccclltldos2 Done Hit lt Return gt after insertion of the device s If necessary lower the front fascia See Section 5 7 1 Removing the Front Fascia on page 5 11 Align the disk drive with the slot in the drive bay Slide the disk drive into the drive bay until it makes contact with the FC AL backplane connector Do not forc
171. otherboard Connectors TABLE D 2 Internal SCSI Connector J5002 Continued Pin Signal Name 42 SCSI_A_MSG_L 44 SCSI_A_SEL_L 46 SCSI_A_CD_L 48 SCSI_A_REQ_L 50 SCSI_A_IO_L D 3 Internal FC AL Connector 1 Jo O12 O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O 19 0 of 20 FIGURE D 2 Internal FC AL Connector J2901 TABLE D 3 Internal FC AL Connector J2901 Pin Signal Name 1 Dr1_PB1_F_1 2 DR2PB2_F_1 3 4 7 8 11 12 GND 15 16 19 20 D 4 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 TABLE D 3 Internal FC AL Connector J2901 Continued Pin Signal Name 5 T_DR2_PORT2IN_P 6 T_DR2_PORT2IN_N 9 DR2_PORT20UT_P 10 DR2_PORT2OUT_N 13 T_DR1_PORT1IN_P 14 T_DR1_PORT1IN_N 17 DR1_PORT1OUT_P 18 DR1_PORT1OUT_N D 4 Power Connectors The motherboard has seven power connectors The following table lists these power connectors the connector use and the supporting figure and table xx identifies the motherboard connector location TABLE D 4 Power Connectors Connector Use Supporting Figure Supporting Table J3603 Power from power FIGURE D 3 TABLE D 5 supply J3601 Power from power FIGURE D 4 TABLE D 6 supply J3303 Power to CPU fan J3602 Power to combined cable assembly J3608 Power to peripheral power cable assembly Appendix D Motherboard Connectors D 5 D 6 14 7 PO O O O O
172. ows the flashprom output message CODE EXAMPLE 4 15 flashprom 0 0 Diagnostic Output Message obdiag gt test 5 Hit the spacebar to interrupt testing Testing pci 8 700000 ebus 5 flashprom 0 0 Spe OIE re are takereandverotete eke htek Mere antes passed Pass 1 of 1 Errors 0 of 0 Tests Failed 0 Elapsed Time Hit any key to return to the main menu 45 4 8 gpiok1 300600 The following code example shows the gpio output message CODE EXAMPLE 4 16 gpio 1 300600 Diagnostic Output Message obdiag gt test 6 Hit the spacebar to interrupt testing Testing pci 8 700000 ebus 5 gpio l1 300600 EE E cose E EE E EEO R E passed Pass 1 of 1 Errors 0 of 0 Tests Failed 0 Elapsed Time Hit any key to return to the main menu 4 5 4 9 i2c 1 2e 4 26 The following code example shows the i2c1 2e output message 0 20 70 0 0 0 0 CODE EXAMPLE 4 17 i2c 1 2e Diagnostic Output Message with TIP Line Installed obdiag gt test 7 Hit the spacebar to interrupt testing Testing pci 8 700000 ebus 5 i2c 1 2e REEE AEE eaten abel nena at a Menge E passed Pass 1 of 1 Errors 0 of 0 Tests Failed 0 Elapsed Time Hit any key to return to the main menu Netra T4 AC100 DC100 Service and System Reference Manual August 2001 0 0 0 0 4 5 4 10 4 5 4 11 4 5 4 12 TAC 1 30 The following code example shows the i2c1 30 output message CODE EXAMPLE 4 18 i2c 1 30 Diagnostic Output Message obdi
173. p to two removable media drives DVD ROM and DDS 4 DAT Reliability Availability and Serviceability LOMLite 2 automatic system recovery Remote diagnosis via Solaris and LOMLite 2 Hot swap disks Diagnostic LEDs Environmental monitoring Field Replaceable Unit FRU ID support Documentation Installation and User s Guide Service and System Reference Manual this document Compliance and Safety Manual a a m Release Notes Software Support m Lights Out Management 2 0 LOMlite2 m SLVM Sun Logical Volume Manager m SunVTS 4 4 Sun Validation Test Suite m SunMC Sun Management Center m SNMP Sun Netra SNMP Management Agent m SunCluster a SRS SunUP ready 1 4 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 PCI Card Support SunSwift Fast Ethernet Quad Fast Ethernet QFE High Speed Serial Interface HSI Serial Asynchronous Interface SAI ATM 155 Dual Differential SCSI Gigabit Ethernet FC AL FC AL and Gigabit Ethernet combination SSL Crypto Accelerator 1 2 System Unit Components The system unit components are listed by part number in Appendix A Note The part numbers listed in Appendix A were correct when this manual was published but they are subject to change without notice Numerical references illustrated in FIGURE A 1 correlate to the references listed in TABLE A 1 and TABLE A 2 Refer to your authorized Sun sales representative or service provider to
174. positive bus is connected to the grounding electrode m Rated for a minimum of 20 A per feed pair Note The Netra T4 DC100 system must be installed in a restricted access location The IEC EN and UL 60950 define a restricted access location as an area intended for qualified or trained personnel only and having access controlled by a locking mechanism such as a key lock or an access card system Appendix B Product Specification B 3 B 2 2 3 Overcurrent Protection Requirements a Overcurrent protection devices must be provided as part of each host equipment rack a Two 20A single pole fast trip DC rated circuit breakers one per ungrounded supply conductor must be located in the negative supply conductor between the DC power source and the Netra T4 DC100 system m Circuit breakers must not trip when presented with inrush current of 20A lasting 250 ms B 3 Environmental Specification This section defines the principal operating requirements and limitations B 3 1 Operating and Storage Normal Ambient Temperature Operating 5 C to 45 C Storage 40 C to 70 C Normal Ambient Humidity Operating 5 to 85 non condensing subject to a maximum absolute humidity of 0 024 kg water kary air 5 to 90 for a maximum of 96 consequtive hours Storage 10 to 95 subject to a maximum absolute humidity of 0 024 kg water kSary air B 4 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 B 3 2 B 3 3
175. protocol 4 13 slew rate 10 30 speed change 12 2 synchronous rates 10 29 setenv ttya mode 4 13 soft reset 4 9 specification electrical B 2 environmental B 4 Stop command emulation Stop A 4 30 Stop D 4 31 Stop F 4 31 Stop N 4 31 SunVTS description 3 1 GUI menu 3 5 installing 3 3 operation 3 2 references 3 2 requirements 3 2 starting 3 5 tests communication ports 3 7 memory 3 7 network 3 7 processor 3 6 storage device 3 7 Superl O 10 35 switch ON STBY 4 2 system functional description 10 1 LEDs 1 7 4 2 main memory 10 6 system configuration card 2 1 system LED assembly 6 8 system switch 6 8 installing 6 10 removing 6 10 T test 4 10 diagnostic message 4 11 tools 5 2 C 1 torque tool 9 6 9 7 9 8 U UltraSPARC III processor 10 3 function diagram 10 4 Index 5 universal PCI card 10 23 unmirrored root disk 8 5 updating firmware LOMlite2 F 1 USB connector 11 10 Ww watch clock diagnositcs 4 12 watch clock 4 12 watch net 4 12 watch net all 4 12 weight 1 3 wrist strap 5 6 Index 6 Netra T4 AC100 Service and System Reference Manual August 2001
176. r terminal and open a window 2 Connect your Netra T4 server to the mains power supply The lom gt prompt is displayed on the terminal 3 Power on the server by pressing the ON switch until the server starts to power up and wait for the ok prompt to appear on the terminal G 2 Connecting to the Serial Ports You can also use the Netra T4 serial ports A and B ttya and ttyb as a console port You require one of the following m DB 25 male to DB 25 male crossover cable wired as shown in TABLE G 2 a DB 25 male to DBV 25 male straight through cable with a crossover adaptor wired as shown in TABLE G 2 TABLEG 2 Netra T4 Serial Port Crossover Adaptor Pinouts DB 25 Netra T4 Signal DB 25 Terminal 1 1 2 RXD TXD 3 3 TXD RXD 2 4 RTS CTS 5 5 CTS RTS 4 6 DSR DTR 20 7 GND GND 7 G 2 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 TABLEG 2 Netra T4 Serial Port Crossover Adaptor Pinouts Continued DB 25 Netra T4 Signal DB 25 Terminal 8 DCD DTR 20 20 DTR DSR 6 20 DTR DCD 8 You must also configure the Netra T4 serial port as the input and output device and direct the diagnostic output to the console ok setenv diag out console true ok setenv input device ttya ok setenv output device ttya Appendix G Connecting to the Netra T4 Server G 3 G 4 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 Glossary address ASIC Asynchronous B
177. rboard Feed the cable between the large and small power cables to the PDB and reconnect the cable to J4 on the PDB Replace the cable tie removed in Step 3 in the previous section Replace the SCCR cover and tighten the two screws removed in Step 2 of the previous section Refit the CPU fan assembly See Section 7 2 3 Installing the CPU Fan Assembly on page 7 7 Chapter 9 Motherboard and Component Replacement 9 17 7 Refit the smart card in the SCCR 8 Refit the top access cover See Section 5 6 3 Fitting the Top Access Cover on page 5 9 9 7 9 7 1 Motherboard The motherboard component and connector layout is shown in FIGURE 9 9 Caution Use an antistatic mat when working with the motherboard An antistatic mat contains the cushioning needed to protect the underside components to prevent motherboard flexing and to provide antistatic protection Note If you intend to exchange the motherboard and preserve the Ethernet address HostID and other configuration settings you must retain the system configuration card Preparation Before proceeding to remove the motherboard carry out the following Initiate antistatic precautions See Section 5 5 Antistatic Precautions on page 5 5 If the system is running shut it down and remove the power See Section 5 3 2 Powering Off the System on page 5 4 Remove the top access cover See Section 5 6 2 Re
178. re devices In a Netra T4 system there are four devices on this bus the audio module is not used Boot PROM Flash memory OpenBoot PROM OBP prompt Power On Self Test POST a OpenBoot Diagnostics OBDiag m Synchronous serial controller RS 232 RS 423 ports m Superl O chip a Parallel port a TOD clock socketed 3V lithium battery m 12C controller The TOD clock function is implemented by the real time clock inside the Superl O ASIC The nonvolatile RAM is implemented by a I2C serial EEPROM and part of the boot PROM Chapter 10 Functional Description 10 15 10 2 4 The EBus channel engine also supports four DMA controllers with programmable transfer size and chained and unchained mode Only one device supports slave DMA transfers on EBus Superl O for the parallel port single DMA engine BootBus 12 PCI 33 MHz me C JTAGS Ebus Parallel Serial Flash Control SuperlO lt PROM SAB p 82532 TTYA I TTYB Keyboard Mouse FIGURE 10 9 Ebus Interrupts The interrupt model in a Netra T4 system follows the Sun4u Sun5 architecture Interrupts are delivered to the processor s as Mondo vectors The CPU receives interrupt packets that are issued over the Sun CrossBar Interconnect bus The processors can issue interrupts to each other called cross calls They are issued by SBC for I O interr
179. rent configuration POST and OBP access the SEEPROM on each processor board to determine System configuration CPU clock ratio Ecache size Processor module version DIMM sizes SCC contents 10 20 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 BBC 12C Ctl 0 Motherboard SEEPROM AT24C64 DIMMO DIMM1 DIMM2 DIMM3 DIMM4 DIMM5 DIMM6 DIMM7 SEEPROM SEEPROM SEEPROM SEEPROM SEEPROM SEEPROM SEEPROM SEEPROM AT24C64 AT24C64 AT24C64 AT24C64 AT24C64 AT24C64 AT24C64 AT24C64 OI t 2 Spare 7 S are 3 p Spare 4 p P a SE EPROM GPU SEEPROM CRU T24C64 AT24C64 A C6 gt C6 Temperature Temperature LOMlite ensor lt gt ensor lt gt Max1617 Max1617 Master Slave 5 87LPC762 FIGURE 10 12 I2C Bus In addition located on the motherboard is a soldered 12C SEEPROM containing the FRU ID structure POST and OBP also access the SEEPROMs in each of the DIMMs which indicate their density and type This data can be used to configure the active memory controller The Ethernet address and host ID can be transferred to another system in case of motherboard failure by using the system configuration card
180. requency of the processor and other operating parameters Chapter 10 Functional Description 10 5 10 2 2 10 2 2 1 Thermal management relies on high air flow and a large heat sink radiation area to maintain uniform temperature control for the CPU module s The temperature of the CPU module s is monitored to avoid any destructive effect in case of fan failure The CPU die contains a temperature sensing diode that is connected to a temperature controller located off the die This temperature controller performs the analog to digital temperature conversion and is interfaced through the I2C serial bus Main Memory The memory subsystem comprises to memory groups and four logical banks The memory groups are divided into even and odd slots A configuration is valid only if at least the odd or even slots are filled with four DIMMs of the same density Address Bus Even Slots 0 0 0 0 l Address Bus UltraSPARC III CPU 0 Control Bus N Safari Data Bus 144 Data 576 bits I Odd Slots 1 FIGURE 10 4 Memory Subsystem Organization As shown on FIGURE 10 1 direct access to the system main memory is controlled only by one of the two CPU modules in a multiprocessor environment Memory is accessed from UltraSPARC Processor 0 through the Sun CrossBar Interconnect bus The main memory data bus is 576 bits wide which corresponds to an external cache block of 64 bytes
181. rom beneath the transverse support bar Installing the CPU Fan Assembly Perform the steps in Section 7 2 2 Removing the CPU Fan Assembly on page 7 7 as required Orientate the fan so that the arrow on the body is pointing towards the rear of the chassis the fan grill is facing towards the front of the system and the cable exits from the right see FIGURE 7 3 Working from the right slide the fan into position above the PSU fan airflow guide and under the transverse support bar Ensure that the fan body is properly located in the metal retainer on the left hand side Refit the retaining clip and tighten the two captive Phillips screws Reconnect the fan power cable to J9 on the PDB Refit the RMM drive assembly See Section 8 3 3 Installing a Removable Media Module on page 8 12 Refit the top access cover See Section 5 6 3 Fitting the Top Access Cover on page 5 9 Refit the front fascia See Section 5 7 2 Fitting the Front Fascia on page 5 11 Chapter 7 Fan Subassemblies 7 7 aN Y E lanmin M T j LOO o 20 f lj l Ses af FIGURE 7 4 Fan Connectors August 2001 Netra T4 AC100 DC100 Service and System Reference Manual 7 8 CHAPTER 8 Storage Devices This chapter contains procedures for removing and fitting the Netra T4 system storage devices The chapter contains the following sections m Section 8 1 FC AL
182. rompt 4 6 4 Stop D To emulate Stop D diags type bootmode diag at the lom gt prompt Chapter 4 Troubleshooting 4 31 4 32 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 CHAPTER 5 Before Servicing the System This chapter lists the tools you will need to install or remove components describes the function of the system ON STBY switch states the antistatic precautions that must be taken before working on the Netra T4 system describes how to access system unit and describes how to change the air filters The chapter contains the following sections Section 5 1 Accessibility on page 5 1 Section 5 2 Tools on page 5 2 Section 5 3 System ON STBY Switch on page 5 2 Section 5 4 Disconnection and Isolation on page 5 5 Section 5 5 Antistatic Precautions on page 5 5 Section 5 6 Top Access Cover on page 5 8 Section 5 7 Front Fascia on page 5 10 Section 5 8 Air Filter on page 5 12 5 1 Accessibility The following components can be accessed while the system is in the rack PSU Front fascia Air filter Hard drive units 5 1 Access to all other components requires removal of the top cover This is achieved by sliding the unit from the rack if it is mounted on rails and there is sufficient height above the unit to work or removing the unit from the rack and carrying out the procedure on a work bench Caution Owing to the weight
183. rot g par un copyright et licenci par des fournisseurs de Sun Des parties de ce produit pourront tre d riv es des syst mes Berkeley BSD licenci s par l Universit de Californie UNIX est une marque d pos e aux Etats Unis et dans d autres pays et licenci e exclusivement par X Open Company Ltd Sun Sun Microsystems le logo Sun AnswerBook2 docs sun com Netra Netra ft et Solaris sont des marques de fabrique ou des marques d pos es ou marques de service de Sun Microsystems Inc aux Etats Unis et dans d autres pays Toutes les marques SPARC sont utilis es sous licence et sont des marques de fabrique ou des marques d pos es de SPARC International Inc aux Etats Unis et dans d autres pays Les produits portant les marques SPARC sont bas s sur une architecture d velopp e par Sun Microsystems Inc L interface d utilisation graphique OPEN LOOK et Sun a t d velopp e par Sun Microsystems Inc pour ses utilisateurs et licenci s Sun reconna t les efforts de pionniers de Xerox pour la recherche et le d veloppement du concept des interfaces d utilisation visuelle ou graphique pour l industrie de l informatique Sun d tient une licence non exclusive de Xerox sur l interface d utilisation graphique Xerox cette licence couvrant galement les licenci s de Sun qui mettent en place l interface d utilisation graphique OPEN LOOK et qui en outre se conforment aux licences crites de Sun LA DOCUMENTATION EST FOURNIE E
184. ry out servicing with the system in the rack Otherwise you must remove the system from the rack and service it on a bench Caution The unit is heavy and requires two people to remove it from and install it in the rack Note Beryllium copper EMI shielding gaskets are attached to the under surface of the access cover Handle the access cover carefully to avoid damaging the gaskets 5 8 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 5 6 1 5 6 2 5 6 3 Preparation Before proceeding to remove the top access cover carry out the following Initiate antistatic precautions See Section 5 5 Antistatic Precautions on page 5 5 If the system is running shut it down and remove the power See Section 5 3 2 Powering Off the System on page 5 4 Caution Wear an antistatic wrist strap and use an ESD protected mat when handling components When servicing or removing system unit components attach an ESD Strap to the wrist then to the connection point provided on the rear of system and only then remove the power cord from the system unit Following this caution equalizes all electrical potentials with the system unit Removing the Top Access Cover Carry out the appropriate steps listed in Section 5 6 1 Preparation on page 5 9 Release the two captive Phillips screws from the rear of the access cover Push the cover away from the front of the chassis to disen
185. s Bus B CODE EXAMPLE 4 7 shows the result of running the show devs command on the 66 MHz PCI bus and CODE EXAMPLE 4 8 on the 33 MHz PCI bus CODE EXAMPLE 4 7 66MHz PCI Bus Devices ok show devs pci 8 600000 pci 8 600000 SUNW qlc 4 pci 8 600000 SUNW qlc 4 fpe 0 0 pci 8 600000 SUNW qlc 4 fp 0 0 disk ok CODE EXAMPLE 4 8 33MHz PCI Bus Devices ok show devs pci 8 700000 pci 8 700000 scsi 6 1 pci 8 700000 scsi 6 pci 8 700000 usb 5 3 pci 8 700000 network 5 1 pcit 8 700000 ebuse 5 pci 8 700000 scsi 6 1 tape pci 8 700000 scsi 6 1 disk pcit 8 700000 scsit 6 tape pci 8 700000 scsi 6 disk pci 8 700000 ebus 5 serial 1 400000 Chapter 4 Troubleshooting 4 15 CODE EXAMPLE 4 8 33MHz PCI Bus Devices ok show devs pci 8 700000 4 16 pci 8 700000 ebus 5 lom console 1 3083f8 pci 8 700000 ebus 5 lombus 1 3062f8 pci 8 700000 ebus 5 parallel 1 300278 pci 8 700000 ebus 5 pmc 1 300700 pci 8 700000 ebus 5 gpioel 300600 pci 8 700000 ebus 5 rtc 1 300070 pci 8 700000 ebus 5 beep l 32 pci 8 700000 ebus 5 i2c 1 30 pci 8 700000 ebus 5 i2c 1 2e pci 8 700000 ebus 5 power 1 30002e pci 8 700000 ebus 5 bbc 1 0 pci 8 700000 ebus 5 flashprom 0 0 pci 8 700000 ebus 5 lombus 1 3062 8 SUNW lomv 0 0 pci 8 700000 ebus 5 i2c 1 30 nvram 0 e0 pci 8 700000 ebus 5 i2c 1 30 idprom 0 e0 pci 8 700000 ebus 5 i2c 1 30 icexp 0 74 pci 8 700000 ebus 5 i2c 1
186. s and secure it with the fixing screw Refit the top access cover See Section 5 6 3 Fitting the Top Access Cover on page 5 9 Installing a PCI Card Perform the steps listed in Section 9 1 1 Preparation on page 9 3 Locate a vacant PCI slot If your PCI card is a 66Mhz card you must use slot 1 If the slot is protected by a blanking plate remove the fixing screw and the plate Gently push the card into the connector applying even pressure at both ends of the card Chapter 9 Motherboard and Component Replacement 9 3 Secure the plate to the rear panel of the chassis using the fixing screw Connect any internal cables to the PCI card as required Connect any external cables to the PCI card as required Refit the top access cover See Section 5 6 3 Fitting the Top Access Cover on page 5 9 9 2 Processor Modules This section describes how to remove and fit a CPU module The processors and associated circuitry are housed in self contained modules which are inserted into plastic air guides attached to the motherboard There are slots for two processor modules on the Netra T4 motherboard Viewed from the front of the unit CPU0 is located immediately to the left of the memory modules The plastic shroud cover and shroud are also stamped 0 and 1 to further aid identification Note Slot 0 must always contain a CPU module Caution To ensure proper cooling an unused
187. s cover See Section 5 6 2 Removing the Top Access Cover on page 5 9 Removing the LOMlite2 Card Perform the steps listed in Section 9 5 1 Preparation on page 9 15 Locate the LOMlite2 card see FIGURE 9 7 Disconnect all external cables to the LOMlite card Disconnect the I2C cable at J0302 on the LOMlite2 card Remove the screw securing the LOMlite2 I O connector plate to the chassis Pull out the LOMlite2 card and place it on an antistatic mat Note The LOMlite2 card must always be fitted Installing the LOMlite2 Card Perform the steps listed in Section 9 5 1 Preparation on page 9 15 Locate the LOMlite2 slot on the motherboard see FIGURE 9 7 If necessary remove the blanking panel from corresponding aperture on the rear panel of the chassis Insert the LOMlite2 card fully into its slot Secure the LOMlite2 card to the chassis by tightening the plate fixing screw Chapter 9 Motherboard and Component Replacement 9 15 6 Reconnect the I2C ribbon cable to J0302 on the LOMlite2 card 7 Reconnect the external cabling to the I O connectors as required 8 Refit the top access cover See Section 5 6 3 Fitting the Top Access Cover on page 5 9 9 6 System Configuration Card Reader The System Configuration Card Reader SCCR is located at the rear of the chassis on the right hand side panel FIGURE 9 8 System Configuration Card Reader 9 6 1 Prepara
188. s for the host adapter and target device include a Vj input low equals 1 0VDC maximum signal true a Vp input high equals 1 9VDC minimum signal false a I input low current equals 201A when V equals 0 5 VDC a lp input high current equals 20 uA when V equals 2 7VDC a Minimum input hysteresis equals 0 3 VDC Supported Target Devices The SCSI subsystem supports a maximum of three internal devices including the host adapter DVD ROM drive and DAT drive The external SCSI bus supports up to 16 UltraSCSI devices 10 34 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 10 2 15 3 10 2 16 External Cables External Ultra SCSI compliant SCSI cables have an impedance of 900hm 60hm and are required for Ultra SCSI interface The Sun implementation of Ultra SCSI requires that the total SCSI bus length be limited to no more than approximately 6m 20ft with up to twelve Sun compensated devices Owing to the considerably short bus length two Ultra SCSI compliant external cables are supported 800mm 32in and 2m 6 6ft Note Consult your authorized Sun sales representative or service provider to order Ultra SCSI compliant external cables There is also an external SCSI connector on the rear panel for legacy peripheral devices Superl O The Netra T4 system uses a SuperI O ASIC to interface to the parallel port The SuperI O ASIC also m Provides the TOD ID SEEPROM m Interfaces w
189. s front edge Installing the PSU Perform the steps as required listed in Section 6 1 1 Preparation on page 6 1 From the rear of the system locate the PSU in its bay in the base of the system Gently slide the PSU into its bay until it starts to engage the connectors on the PDB Engage the connectors by pushing the PSU firmly into place until the rear plate on the PSU is flush against the rear of the system chassis If you are working on a bench you may require an additional person to hold the system chassis steady while you engage the connectors Tighten the three captive phillips screws colored purple to secure the PSU to the system chassis Reconnect the power connector to the PSU appliance inlet Chapter 6 Power Subassemblies 6 3 Power Distribution Board 6 2 The power distribution board PDB receives power from the PSU and distributes it to the motherboard connectors drive units and system fans LPR CEG er F Wh o O EGEE EE EEEE LEELA 1 amp 3 recente reer y ae ge ye SSS ee GEEKS LEER oN iy o FIGURE 6 2 Power Distribution Board Preparation 6 2 1 Before proceeding to remove a power distribution board PDB carry out the following 1 Initiate antistatic precautions See Section 5 5 Antistatic Precautions on page 5 5 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 6 4 6 2 2 If the s
190. s root mean square An evolution of Ethernet technology that succeeded 10BASE5 and 10BASE2 as the most popular method of physical network implementation A 1OBASE T network has a data transfer rate of 10 megabits per second and uses unshielded twisted pair wiring with RJ 45 modular telephone plugs and sockets Netra T4 AC100 DC100 Service and System Reference Manual August 2001 100BASE T Also known as Fast Ethernet an Ethernet technology that supports a data transfer rate of 100 megabits per second over special grades of twisted pair wiring 100BASE T uses the same protocol as 10BASE T There are three subsets of the 100BASE T technology 100BASE TX defines digital transmission over two pairs of shielded twisted pair wire 1OOBASE T4 defines digital transmission over four pairs of unshielded twisted pair wire 1OOBASE TX defines digital transmission over fiber optic cable Glossary 5 6 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 Index A AC power cord 4 2 AC PSU DC output 10 36 LEDs 1 10 access cover fitting 5 9 removing 5 9 accessing the system 5 1 air filter 5 12 replacing 5 13 alarms serial port connector 11 11 alarms service port connector 11 11 antistatic precautions 5 5 autoboot 4 10 B battery 9 12 disposal 9 12 installing 9 13 removing 9 13 BBC 4 9 BootBus Controller See BBC bus PCI 10 22 10 23 C cable AC power 4 2 external Ethernet 10 32 SCSI 10 35 m
191. sS amp Sun microsystems Netra T4 AC100 DC100 Service and System Reference Manual Sun Microsystems Inc 901 San Antonio Road Palo Alto CA 94303 4900 U S A 650 960 1300 Part No 806 7336 11 August 2001 Revision A Send comments about this document to docfeedback sun com Copyright 2001 Sun Microsystems Inc 901 San Antonio Road Palo Alto CA 94303 4900 U S A All rights reserved This product or document is distributed under licenses restricting its use copying distribution and decompilation No part of this product or document may be reproduced in any form by any means without prior written authorization of Sun and its licensors if any Third party software including font technology is copyrighted and licensed from Sun suppliers Parts of the product may be derived from Berkeley BSD systems licensed from the University of California UNIX is a registered trademark in the U S and other countries exclusively licensed through X Open Company Ltd Sun Sun Microsystems the Sun logo AnswerBook2 docs sun com Netra Netra ft and Solaris are trademarks registered trademarks or service marks of Sun Microsystems Inc in the U S and other countries All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International Inc in the U S and other countries Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems Inc The OPEN LOOK
192. sceiver module with filters The 100BASE X and 10BASE T sections share the following functional characteristics a PCS control m IEEE 802 3u auto negotiation The following sections provide brief descriptions of the following Automatic negotiation Connectors Automatic Negotiation Automatic negotiation controls the cable when a connection is established to a network device It detects the various modes that exist in the linked partner and advertises its own abilities to automatically configure the highest performance mode of inter operation namely 1OBASE T 100BASE TX or 100BASE T4 in half and full duplex modes The Ethernet port supports automatic negotiation At power up an on board transceiver advertises 100BASE TX in half duplex mode which is configured by the automatic negotiation to the highest common denominator based on the linked partner Chapter 10 Functional Description 10 31 10 2 13 2 10 2 14 External Cables The RJ45 Ethernet port supports a Category 5 STP cable for the 100BASE T and a Category 3 4 or 5 STP cable for the 1OBASE T operation Note The maximum cable segment lengths for the 1OOBASE TX and 10BASE TX are 100m 328 ft and 1000m 3282 ft respectively FC AL Subsystem The Netra T4 system supports FC AL Fibre Channel Arbitrated Loop as the interface for internal and external hard drives The physical medium is copper Optical links are not supported The disk drives are
193. ss address cell data diag level Variable Set to max 8 of 17 i reliability 1 Test data reliability 1 Test address line transitions line transitions 1 1 I Cache Snoop Tags Snoop Tags up Test address down Test address up 1 down Test cell disturbance 1 1 disturbance reliability 1 Test data reliability rest address line transitions 1 address line transitions 1 I Cache Init Init 1 D Cache RAM 1 Test address up RAM up Test address down 1 down 1 Test cell disturbance disturbance reliability 1 Test data reliability 1 Test address line transitions line transitions D Cache TAGS Test address up TAGS up rest address down 1 1 1 down 1 Test cell disturbance disturbance reliability 1 Test data reliability Test address line transitions 1 address line transitions 1 D Cache MicroTags Netra T4 AC100 DC100 Service and System Reference Manual August 2001 CODE EXAMPLE E 1 O O O O 0 OD tay 0 0 D Cache Test Test cell Test Test data Test D Cache Test Test cell Test data Test D Cache W Cache Test Test cell Test data Test W Cache 1 address 1 address 1 1 1 address 1 1 Test address 1 address 1 1 1
194. stem ECC Test ncorrectable System ECC Test emory address selection All Banks ECC Test e System ss selection All Banks ing All Banks emory marching All Banks ters c000000 0011a954 1 Map PCI A sp 1 S ap PCI B space ace chizo reg test Schizo reg test 1 PB B registers PBM A registers O Streaming a Cach a a 1 S 1 PCI oa 1 Iommu B registers O Iommu A registers 1 Streaming Cache B registers e A registers 1 Mondo Interrupt B registers O Mondo Interrupt A registers chizo pci B id test B Vendor ID 108e Schizo pci A id test on 1 PCI B Device ID 8001 PCI A Vendor ID 108e Netra T4 AC100 DC100 Service and System Reference Manual August 2001 CODE EXAMPLE E 1 O Map O O RIO a AN ANNO AS 0 diag level Variable Set to max 13 of 17 EBus access Icache Functional 1 Schizo mem test O PCI A Device ID 8001 l memtst ram data port B 0 Schizo mem test O memtst ram data port A l memtst cam data port B O memtst cam data port A l memtst ram addr port B O memtst ram addr port A l memtst cam addr port B O memtst cam addr port A l memtst pnta port B O memtst pnta port A l memtst lnta port B O memtst lnta port A l memtst rnta port B O memtst rnta port A l memtst enta port B O memtst enta port A l memtst ln addr port B O memtst ln addr port A l
195. stem Reset SPOR PLL Probing gptwo at 0 0 SUNW UltraSPARC III 750 MHz 5 1 8 MB memory controller Probing gptwo at 1 0 SUNW UltraSPARC III 750 MHz 5 1 8 MB memory controller Probing gptwo at 8 0 pci pci Loading Support Packages kbd translator Loading onboard drivers ebus flashprom bbc power i2Zc dimm fru dimm fru 4 22 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 CODE EXAMPLE 4 9 Typical reset all Screen Output Continued dimm fru dimm fru dimm fru dimm fru dimm fru dimm fru i2c cpu fru temperature cpu fru hardware monitor hardware monitor hardware monitor temperature fan control fan control motherboard fru ioexp ioexp ioexp fcal backplane scc reader lomlite2 nvram idprom beep rtc gpio pmc parallel lombus SUNW lomc serial lomp lomv emory Configuration Segment Base O Size 2048 MB 4 Way SUNW Netra T4 Probing pci 8 600000 Device 4 SUNW qlce fp disk Probing pci 8 600000 Device 1 Nothing there Probing pci 8 700000 Device 5 network usb Probing pci 8 700000 Device 6 scsi disk tape scsi disk tape Probing pci 8 700000 Device 1 Nothing there Probing pci 8 700000 Device 2 Nothing there Probing pci 8 700000 Device 3 Nothing there Probing pci 8 700000 Device 4 Nothing there Sun Netra T4 2 X UltraSPARC III No Keyboard Copyright 1998 2001 Sun Microsystems Inc All rights reserved OpenBoot 4 2 2048 MB memory installed Serial 16458092 Ethernet address 8 0 20 fb 2
196. systest tests the I O memory and CPU channels m fputest tests the floating point unit m mptest tests two or more processors by having them access a shared memory page 3 6 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 TABLE 3 3 SunVTS Memory Tests Test Function Legacy Tests These include m pmemtest tests the physical memory by targeting parity ECC memory read and addressing problems m vmemtest tests the virtual memory and the swap partitions of the disks TABLE 3 4 SunVTS Storage Device Tests Test Function dvdtest This new test checks the DVD R drive by reading the DVD qlctest This new test checks the ISP2200A FC AL controller The sub tests include m Revision checks m Internal loopback tests m External loopback tests require external loopback cable Legacy Tests These include m cdtest tests the CD ROM drive by reading the CD m tapetest tests tape devices by writing reading and verifying synchronous and asynchronous data blocks TABLE 3 5 SunVTS Network Tests Test netlbtest nettest Function This new test checks the ERI and GEM Ethernet controllers by performing internal and external loopback tests replaces gemtest This system to system legacy test covers all networking devices found in the system TABLE 3 6 SunVTS Communications Port Tests Test usbkbtest Legacy Tests Function This new test covers the keyboard and mouse These includ
197. t 1 D Cache Init W Cache RAM Test address up Test address down Test cell disturbance W Cache TAGS 1 W Cache RAM Test address up a Oy a NEE aa E s ka a O 1 Test address up Test address down oe Test cell disturbance 1 Test address down W Cache SnoopTAGS SO Test address up 1 Test cell disturbance Test address down one Test cell disturbance 1 W Cache TAGS 0 W Cache Init l Test address up 0 P Cache RAM 1 Test address down a oO Test address up 1 Test cell disturbance Test address down 1 W Cache SnoopTAGS l Test address up a oO wy O Test cell disturbance l Test address down 1 Test cell disturbance 0 P Cache TAGS 1 W Cache Init E 24 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 CODE EXAMPLE E 2 Oro O 2 O T 0 FSR O 1 O O 7 ett Test cell P Cache iS Test cell P Cache may Test cell P Cache we 1 Test address 1 Test address down 1 Test address 1 Test address 1 1 diag level Variable Set to min 9 of 15 rest address up 1 P Cache RAM Test address down 1 Test address up disturbance Test address down SnoopTags up Test cell disturbance disturbance 1 P Cache T
198. t Controller Reset BBC Ebus Parallel PHY 7 LU6612 Serial u sn Eo SuperlO Ethernet 82532 USB TTYA i TTYB Keyboard Mouse FIGURE 10 11 Netra T4 Boot Bus BootBus Controller BBC ASIC The BootBus controller provides access to the boot PROM by bridging the Sun CrossBar Interconnect BootGroup signals the BootBus and the EBus The boot PROM connects directly to the EBus The PCIO 2 is also a master on the EBus Full arbitration between the PCIO 2 and the BBC controls access to the EBus The EBus is accessed from the BBC only during the boot sequence that is during the execution of POST and OpenBoot PROM Note When the system is running Solaris software the kernel has no knowledge of the BootBus space Access to the boot PROM through the BBC is optimized for 16 byte master accesses performed by the CPU on the BootBus 10 18 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 BBC is also a slave on the EBus and all its internal registers are accessible through the PCIO 2 Thus software drivers running on Solaris software can access the necessary resources such as the thermal management driver BBC also supports many other functions that are briefly introduced in the following subsections Reset Controller The BBC is the reset controller in the Netra T4 system The controller receives the reset source lines and is responsible for generating the reset signals for the CPU module s and the overall syst
199. t adapter on main logic board Support for up to seven internal SCSI devices including the host adapter a Fast 20 SCSI disk drive target 0 left most drive slot a Fast 20 SCSI disk drive target 1 a Fast 20 SCSI disk drive target 2 Fast 20 SCSI disk drive target 3 right most drive slot Fast 10 SCSI removable media device target 4 Fast 10 SCSI removable media device target 6 m Support for external 8 bit and 16 bit SCSI devices via 68 pin SCSI connector mounted on an adapter board SCSI Cabling and Configuration The SCSI 3 Fast 20 UltraSCSI specification requires that the external SCSI bus length be limited to 3m 10ft for less than five devices internal and external and 1 5m 5ft for five to eight devices When SCSI 3 and SCSI 2 devices are connected to the Netra T4 system SCSI bus the system enables each device to operate at its respective data transfer rate The last external SCSI device in a daisy chain must be terminated internally active termination or with an external terminator according to Forced Perfect Termination FPT technology SCSI Cabling Procedure Count the number of SCSI devices on the system SCSI bus Be sure to count the host adapter as a SCSI device 11 6 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 11 3 2 2 2 Determine the total SCSI bus length TABLE 11 4 Determining SCSI Bus Length Data Transfer Number of SCSI SCSI Implementation Bus Width Rate Mb s
200. the left of the CPU fan and houses the two internal disk drives There are one connector one power connector and one I2C connector to the backplane which is mounted on the rear of the drive bay see FIGURE 8 2 8 6 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 FIGURE 8 2 FC AL Backplane and Drive Bay Assembly 8 7 Chapter 8 Storage Devices 8 2 1 8 2 2 Preparation Before proceeding to remove the FC AL backplane and drive bay assembly carry out the following Initiate antistatic precautions See Section 5 5 Antistatic Precautions on page 5 5 If the system is running shut it down and remove the power See Section 5 3 2 Powering Off the System on page 5 4 Lower the front fascia See Section 5 7 1 Removing the Front Fascia on page 5 11 Remove the top access cover See Section 5 6 2 Removing the Top Access Cover on page 5 9 Removing the FC AL Backplane and Drive Bay Perform the appropriate steps listed in Section 8 2 1 Preparation on page 8 8 Loosen the four captive Phillips screws securing the drive bay to the chassis front panel Disconnect the 20 way ribbon data cable at J0102 on the FC AL backplane by opening the side locking lugs on the socket and withdrawing the connector This cable is connected to J2901 on the motherboard Ease the drive bay assembly forward to access the two lower connectors to t
201. tion Before proceeding to remove a System Configuration Card Reader SCCR carry out the following 1 Initiate antistatic precautions See Section 5 5 Antistatic Precautions on page 5 5 9 16 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 9 6 2 9 6 3 If the system is running shut it down and remove the power See Section 5 3 2 Powering Off the System on page 5 4 Remove the top access cover See Section 5 6 2 Removing the Top Access Cover on page 5 9 Remove the card from the smart card from the SCCR and store it safely Removing the SCCR Perform the steps listed in Section 9 6 1 Preparation on page 9 16 Remove the two slot head screws securing the SCCR cover and remove it Cut the cable tie securing the ribbon cable to the chassis side panel Disconnect the ribbon cable at J3604 on the motherboard and J4 on the PDB Release the two upper captive fixing screws securing the SCCR to the chassis side panel Carefully prise the card off the two lower spring loaded pins Remove the SCCR and place it on the antistatic mat Installing the SCCR Perform the steps listed in Section 9 6 1 Preparation on page 9 16 Locate the SCCR over the two lower spring loaded fixing pins and press the board gently and evenly onto the pins Tighten by hand the two captive upper fixing screws Reconnect the ribbon cable to J3604 on the mothe
202. tions Ecache Address Lin 1 Ecache Address Lin Partial Ecache Init 1 BBC E Star 1 Partial Ecache Init Registers I Cache RAM I Cache RAM ey I Cache ee ae oe Ne BS me ew Test address Test address est address 1 Test address Test address est address Test address Test address l Test address up up l Test address down down l Test cell disturbance est cell disturbance l Test data reliability est data reliability 1 Test address line transitions line transitions I Cache TAGS 1 Testing I Cache Tag TAGS l Test address up Testing I Cache Tag up l Test address down down 1 Test cell disturbance est cell disturbance l Test data reliability est data reliability 1 Test address line transitions line transitions 1 Testing I Cache Micro Tag l Test address up Testing I Cache Micro Tag up l Test address down down 1 Test cell disturbance Test cell disturbance Appendix E Example POST Diagnostic Output E 7 CODE EXAMPLE E 1 pur j est est est est est est est est est est est est E 8 Test data Test address I Cache Test address address cell data O I Cache D Cache Test address address cell data address D Cache Test addre
203. tst sbuf addr port A 1 Schizo merg test Schizo merg test l merg_wr 8 byte port B merg_wr 8 byte port A l merg_wr 4 byte port B merg_wr 4 byte port A Map PCI B space for RIO RIO Config RIO EBus access Icache Functional 1 Icache Functional O Verify cacheline fill on read miss a 1 Verify cacheline fill on read miss Dcache Functional 1 Dcache Functional Verify no allocate on write miss Verify fetch from memory on read miss a 1 Verify no allocate on write miss O Verify write through on write hit a 1 Verify fetch from memory on read miss O Verify write through fetch on read miss 1 Verify write through on write hit Appendix E Example POST Diagnostic Output E 27 CODE EXAMPLE E 2 diag level Variable Set to min 12 of 15 l Verify write through fetch on read miss Verify set associativity Weache Functional Verify cacheline fill on write miss Verify buffering CG Or e SO Verify coalescing a l1 Verify set associativity 0 Pcache Functional 1 Wcache Functional 0 FPU Functional 1 Verify cacheline fill on write miss 0 Test single and double precision addition 1 Verify buffering 0 Test single and double precision subtraction on l Verify coalescing O0 Test single and double precision multiplication 1 Pcache Functional 0 Test single and double precision division 1 FPU Functional O0 Test singl
204. ugs on the socket click into place Slide the assembly completely into the chassis until it is flush with the chassis Tighten the four captive Phillips screws to secure the assembly to the chassis Refit the disk drive s if you have removed them previously Note that the boot disk must be located in drive 0 Refit the top access cover See Section 5 6 3 Fitting the Top Access Cover on page 5 9 Refit the front fascia See Section 5 7 2 Fitting the Front Fascia on page 5 11 Chapter 8 Storage Devices 8 9 8 3 Removable Media Module The optional DVD R and DDS 4 DAT drive Removable Media Modules RMM are housed in their own sub chassis which is located to the right of the CPU fan at the front of the system FIGURE 8 3 Removable Media Modules 8 3 1 Preparation 8 10 The assembly can be removed with the DVD R and DAT drives in place Before proceeding to remove the RMM assembly carry out the following Netra T4 AC100 DC100 Service and System Reference Manual August 2001 8 3 2 Initiate antistatic precautions See Section 5 5 Antistatic Precautions on page 5 5 If the system is running shut it down and remove the power See Section 5 3 2 Powering Off the System on page 5 4 Lower the front fascia See Section 5 7 1 Removing the Front Fascia on page 5 11 Remove the top access cover See Section 5 6 2 Removing the Top Access Cover on page 5 9
205. up O DMMU Init l Test address down O Mapping done MMU enabled l Test address line transitions O Memory address selection Initial area L IMMU Init L DMMU Init l Mapping done MMU enabled 1 Q 1 1 E Cache Global Vars Init E Cache Quick Verification 1 E Cache Global Vars Init IFE Ecache TAGS SO E Cache Quick Verification SO Test address up 1 Ecache TAGS l Test address up Test address down oO wy l Test address down Test cell disturbance oO ww 1 Test cell disturbance O Ecache Address Lin 1 Ecache Address Lin O Partial Ecache Init 1 Partial Ecache Init BBC E Star Registers I Cache RAM 1 I Cache RAM Test address up SO O 1 Test address up Test address down S 1 Test address down O Test cell disturbance 1 Test cell disturbance I Cache TAGS Testing I Cache Tag 1 I Cache TAGS Test address up oe wa o wy l Testing I Cache Tag l Test address up Test address down oO Netra T4 AC100 DC100 Service and System Reference Manual August 2001 diag level Variable Set to min 6 of 15 l Memory address selection Initial area CODE EXAMPLE E 2 oo OD OS OS oO OS Test cell N Test cell I Cache K Test cell I Cache D
206. upts All interrupts that are not cross called are referred to as I O interrupts I O interrupts are issued on separate lines by the various on board devices the PCI cards and UPA cards The interrupts are routed to an interrupt concentrator the I chip that encodes the interrupts and delivers them to the SBC The SBC issues a single Sun CrossBar Interconnect interrupt transaction for each active interrupt FIGURE 10 10 shows the overall interrupt organization in the Netra T4 system 10 16 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 10 2 5 CPU CPU Sun CrossBar Interconnect gt a 7 3 a Ww PCI Slot 0 PCI Slot 1 PCI Slot 2 EPCI Slot 0 FIGURE 10 10 System Interrupt Block Diagram BootBus The CPU modules support an alternate 8 bit bus the BootBus used after a reset to fetch the first instruction they execute The address space of the BootBus corresponds to the boot PROM addressing space as defined by the Sun4u Sun5 architecture The CPU issues its SPARC V9 RED_MODE trap vectors from this address space Chapter 10 Functional Description 10 17 10 2 5 1 FIGURE 10 11 shows how the CPUs access the boot PROM through the BootBus the BBC and EBus BootBus Sun Crossbar Interconnect Boot Group Signals BootBus Request Request BootBus PCI 33 MHz an
207. ut This appendix provides examples of the POST output to serial port A If POST fails to complete compare the last message output with the example The next line in the example may help to identify the cause of the problem CODE EXAMPLE E 1 is a typical POST output for a system with two 750 MHz CPUs and 4GByte of memory and with the diag level variable set to max CODE EXAMPLE E 1 diag level Variable Set to max 1 of 17 OBP 4 2 3 2001 04 23 17 48 Sun Netra T4 Clearing TLBs Done Power On Reset Executing Power On SelfTest 0 O POST v4 1 7 01 22 2001 06 55 PM 1 Transfered from OBP or Unknown source of reset PLL reset Configure I2C controller 0 Configure I2C controller 1 I2C Controller Loopback Test Read JTag IDs of all ASICs BBCJTag ID 1483203b SCSIJTag ID 15060045 I chipJTag ID dle203b RIOJTag ID 13e5d03b SchizoJTag ID 1824c06d CPMSJTag ID 1142903b CPMSJTag ID 1142903b CPMSJTag ID 1142903b CPMSJTag ID 1142903b CPMSJTag ID 1142903b rn ODO O Oo OG O O OCO TO 0 CO O OC O aG O CPMSJTag ID 1142903b E 1 CODE EXAMPLE E 1 diag level Variable Set to max 2 of 17 Oo OO Ore OO Or OOO OOS S kF Or Sas Oa Oy Orr S Oa Or OS a Read JTag ID of FCAL FC ALJTag ID 1000a12f Probing Seeprom on DIMMs and CPU modules CPUO Sensor package temperature
208. vices the SCSI controller and the PCIO 2 ASIC on the 33MHz PCI bus The ISP2200A FC AL disk controller is located on the 64 bit 66 MHz PCI bus PCI Cards PCI cards come in a variety of configurations Not all cards fit or operate in all PCI slots so it is important to know the specifications of your PCI cards and the types of cards supported by each PCI slot in the system Some PCI cards are as short as 174 6mm 6 88in in length called short cards while the maximum length of PCI cards is 311 9mm 12 28in called long cards Slots 0 1 and 2 in the Netra T4 system can accommodate either a long or a short card but slot 3 is restricted by the FC AL drive assembly and can accommodate only a short card Older PCI cards communicate over 32 bit PCI buses while many newer cards communicate over wider 64 bit buses 10 22 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 10 2 7 2 Older PCI cards operate at 5VDC while newer cards are designed to operate at 3 3VDC Cards that require 5VDC will not operate in 3 3 volt slots and 3 3 volt cards will not operate in 5 volt slots Universal PCI cards are designed to operate at either 3 3 VDC or 5VDC so these cards can be inserted into either type of slot The system provides three slots for 5 volt cards and one slot for a 3 3 volt card All four PCI slots accept universal cards Most PCI cards operate at clock speeds of 33MHz while newer EPCI cards operate at
209. w2100002307653317 0 a raw truncated for clarity m For internal FC AL disks Target ID Number Disk Bay Number m For external FC AL disks Target ID Multipack ID x 8 Drive Bay Number 4 Push the disk drive latch downwards to release the drive handle 5 Using the drive handle ease the drive from the drive bay until you feel the drive connector disengage from the FC AL backplane connector Chapter 8 Storage Devices 8 5 8 1 6 Holding the disk by the handle slide the disk drive out of the bay Support the weight of the drive with your other hand to avoid unnecessary pressure on the drive handle Place the disk drive on an antistatic mat Installing an Unmirrored Root Disk Perform the steps listed in Section 8 1 4 Preparing to Remove an Unmirrored Root Disk on page 8 5 as required Align the disk drive with the slot in the drive bay Slide the disk drive into the drive bay until it makes contact with the FC AL backplane connector Do not force it home Lock the drive in the bay by pressing on the drive handle until the drive latch closes This action engages the drive with the FC AL backplane connector Refit the front fascia See Section 5 7 2 Fitting the Front Fascia on page 5 11 Perform a reconfiguration boot by typing 8 2 Fiber Channel Backplane and Drive Bay The FC AL backplane and drive bay assembly is located at the front of the chassis to
210. y Context Appendix E Example POST Diagnostic Output E 3 CODE EXAMPLE E 1 diag level Variable Set to max 4 of 17 l Testing Secondary Context O0 Test walking 1 through the register 1 Test walking 1 through the register Testing D TSB 1 Testing D TSB O Test walking 1 through the register a oO yw 1 Test walking 1 through the register a o yw Testing D TLB Tag Access 1 Testing D TLB Tag Access 0 Test walking 1 through the register 1 Test walking 1 through the register a oO wy Testing Virtual Watchpoint 1 Testing Virtual Watchpoint O Test walking 1 through the register 1 Test walking 1 through the register a oO yw Testing Physical Watchpoint 1 Testing Physical Watchpoint 0 Test walking 1 through the register 1 Test walking 1 through the register 0 4M DTLB RAM 1 4M DTLB RAM O Test address up a l Test address up O Test address down l Test address down O0 Test cell disturbance 1 Test cell disturbance O Test data reliability 1 Test data reliability 0 Test address line transitions l Test address line transitions 0 8K DTLB RAM 1 8K DTLB RAM O Test address up l Test address up 0 Test address down l Test address down O0 Test cell disturbance 1 Test cell disturbance O Test data reliability l Test data reliability 0 Test address line transitions l Test address line transitions E 4 Netra T
211. ystem control application specific integrated circuits ASICs and I O ASICs A fully configured system weighs approximately 27 3kg 601b Operating Environment m Solaris 8 Update 4 01 and Update 7 01 Power m Rack mounting enclosure with one single feed 100 240VAC power supply unit AC100 or one twin feed 48VDC 60VDC power supply unit DC100 Processors m Support for up to two 750MHz UltraSPARC III processor modules each with 8MByte Ecache Memory m Support for up to eight 128MByte 256Mbyte 512MByte or 1GByte Next Generation Dual Inline Memory Module NG DIMMS installed in two groups of four providing from 512MByte to 8GByte of memory IO m Four PCI 2 1 compliant slots one long 64 32 bit 66 33 MHz two long 64 32 bit 33MHz one short 64 32 bit 33 MHz One 10 100BaseT Ethernet connection One Fast Wide SCSI connection Four USB connections two twin Series A ports 12Mb s One external FC AL connection Two internal FC AL connections for hard disks Two RS232 RS423 serial ports One parallel port 1 Up to 312mm long 2 Up to 174 6mm long Chapter 1 System Description 1 3 m One DB 15 LOMlite2 alarms relay port a One RJ45 LOMlite2 alarms serial port System Configuration a 12C system configuration card reader SCCR Storage Up to two FC AL 1 inch hot swap hard disks 36GByte External hardware RAID support through PCI Software RAID support Sun Logical Volume Manager SLVM a a U
212. ystem is running shut it down and power off the system See Section 5 3 2 Powering Off the System on page 5 4 Remove the top access cover See Section 5 6 2 Removing the Top Access Cover on page 5 9 Detach the PSU from the PDB connector by performing Step 2 through Step 4 of the PSU removal procedure Note that it is not necessary to remove the PSU from the system completely See Section 6 1 2 Removing the PSU on page 6 2 Remove the Removable Media Module RMM See Section 8 3 2 Removing a Removable Media Module on page 8 11 Remove the FC AL disk drive assembly See Section 8 2 2 Removing the FC AL Backplane and Drive Bay on page 8 8 Remove the CPU fan assembly See Section 7 2 2 Removing the CPU Fan Assembly on page 7 7 Remove the PSU fans assembly See Section 7 1 2 Removing the PSU Fans Assembly on page 7 4 Remove the CPU shroud cover See Section 9 2 2 Removing a CPU Module on page 9 6 Removing the PDB Perform the steps as required listed in Section 6 2 1 Preparation on page 6 4 Disconnect the large black 14 way power cable at J2 on the PDB by pressing the side locking lugs on the connector and pulling it away from the socket The cable connects to J3604 on the motherboard Disconnect the small white 14 way power cable at J3 on the PDB by pressing the central locking lug at the back of the connector and pulling
213. ystem to the STBY 4 position and hold it until the system shuts down this can take several seconds or use the LOMlite2 poweroff command or OBP power off command b Set the ON STBY switch at the front of the system to the STBY D position and release it immediately to initiate a clean shut down followed by a power off 2 Verify that the Power LED is off 5 4 Netra T4 AC100 DC100 Service and System Reference Manual August 2001 3 Open both DC circuit breakers 4 Detach both DC input connectors 5 4 Disconnection and Isolation 5 4 1 Netra T4 AC100 System The disconnect devices for servicing are defined as m The appliance inlet on the rear of the system m The circuit breakers in the rack in which the system is mounted a The mains plug 5 4 2 Netra T4 DC100 System The disconnect devices for servicing are defined as a The circuit breakers in both negative supply conductors m Both DC input connectors 5 9 Antistatic Precautions Caution Wear an antistatic wrist strap and use an ESD protected mat when handling components When servicing or removing system unit components use an antistatic wrist strap with a 10mm press stud connection and attach the antistatic wrist strap to the press stud at the rear or front of the chassis before removing the top access cover Chapter 5 Before Servicing the System 5 5 5 5 1 Attaching the Antistatic Wrist Strap To attach the antistatic wrist strap to the chassis conn

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