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VisualDSP++® 5.0 Loader and Utilities Manual

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1. Bit Field Description 0 7 LSB of the global header 2 8 15 8 15 of the global header E 16 23 16 23 of the global header 24 31 MSB of the global header 32 39 LSB of the address field of 1st dxe count block no care 40 47 8 15 of the address field of 1st dxe count block no care 48 55 16 23 of the address field of 1st dxe count block no care 3 56 63 MSB of the address field of Ist dxe count block no care E 64 71 LSB 4 of the byte count field of Ist dxe count block z 72 79 8 15 0 of the byte count field of Ist dxe count block 80 87 16 23 0 of the byte count field of 1st dxe count block A 88 95 MSB 0 of the byte count field of Ist dxe count block a 96 103 LSB of the flag word of 1st dxe count block ignore bit set 04 111 MSB of the flag word of 1st dxe count block 12 119 LSB of the first 1st dxe byte count e 20 127 8 15 of the first 1st dxe byte count Be 3 28 135 16 23 of the first Ist dxe byte count 2 36 143 24 31 of the first 1st dxe byte count cae 3 40 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Processors 44 151 LSB of the address field of the 1st data block in Ist dxe 52 159 8 15 of the address field of the 1st data block in Ist dxe _ 160 167 16 23 of the address field of the 1st data block in 1st dxe E 68 175 MSB
2. Silicon Revision 0 0 0 1 0 2 0 3 Width 8 16 8 16 8 16 Flash boot mode NONE NONE NONE NONE ONE NONE PFO 15 PFOH15 PFO 15 PFO 15 PGO 15 PGO 15 PGO 15 PGO 15 PHO 15 PHO 15 PHO 15 PHO 15 SPI boot mode NONE NONE ONE PFO 9 PFO 9 PF15 PF15 PGO 15 PGO 15 PHO 15 PHO 15 SPI slave boot 1 15 NONE ONE mode PF1 15 PF0 10 PFO 10 PF15 PF15 PGO 15 PGO 15 PHO 15 PHO 15 TWI boot mode NONE NONE ONE PFO 15 PFO 15 PGO 15 PGO 15 PHO 15 PHO 15 TWI slave boot NONE NONE ONE mode PFO 15 PFO 15 PGO 15 PGO 15 PHO 15 PHO 15 UART boot 2 15 NONE ONE mode PF2 15 PF2 15 PF2 15 PGO 15 PGO 15 PHO 15 PHO 15 FIFO boot mode NONE PFO PF2 gt 15 PGO 15 PHO 15 1 The ADSP BF534 BF536 BF537 processors always have the RESVECT bit bit 2 in the block header flag word set 3 70 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Processors Table 3 13 pFlag Values for ADSP BF538 BF539 Processors Silicon Revision 0 0 0 3 Width 8 16 Flash boot mode NONE NONE SPI boot mode NONE SPI slave boot mode 1 15 PFI 1L5 1 The ADSP BF538 BF539 processors always have the RESVECT bit bit 2 in the block header flag word set VisualDSP 5 0 Loader and Utilities Manual 3 71 ADSP BF53x BF561 Processor Loader Guide Using VisualDSP Loader After selecting a Loader file ldr as the project output type for your application on the Application Settings
3. 3 64 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Processors Table 3 10 Blackfin Loader Command Line Switch Summary Contd Switch Description MaxZeroFillBlockSize The MaxZeroFillBlockSize switch specifies the maximum block byte count for zero filled blocks The valid values are from 0x0 to OXFFFFFFFO and the default value matches MaxBlockSize MM The MM switch generates make dependencies while producing the output files Mo filename The Mo filename switch writes make dependencies to the named file Use the Mo switch with either M or MM If Mo is not present the default is a lt stdout gt display Mt filename The Mt filename switch specifies the make dependencies target output file Use the Mt switch with either M or MM If Mt is not present the default is the name of the input file with an 1dr exten sion no2kernel The no2kernel switch produces the output file without the boot kernel but uses the boot strap code from the internal boot ROM The boot stream generated by the loader utility is different from the one generated by the boot kernel Applies to the ADSP BF535 processors only noFinalBlock The noFinalBlock switch directs the loader utility not to make a special final block for TWI boot Applies to the ADSP BF537 processors only noFinalTag The noFinalTag switch
4. Currently the loader utility generates single processor loader files for host link and SPI port boot The loader utility supports multiprocessor EPROM boot only The application code must be modified to properly set up multiprocessor booting in host link and SPI port boot modes There are two methods by which a multiprocessor system can be booted e Boot From a Single EPROM e Sequential EPROM Boot Regardless of the method the processors perform the following steps 1 Arbitrate for the bus 2 Upon becoming bus master DMA the 256 word boot stream VisualDSP 5 0 Loader and Utilities Manual 5 21 ADSP 21161 Proc essor Booting 3 Release the bus 4 Execute the loaded instructions Boot From a Single EPROM The loader utility can produce boot loadable files that permit SHARC processors in a multiprocessor system to boot from a single EPROM The BMS signals from each processor may be wire ORed together to drive the EPROM s chip select pin Each processor can boot in turn according to its priority When the last processor has finished booting it must inform the other processors which may be in the idle state that program execu tion can begin if all processors are to begin executing instructions simultaneously When multiple processors boot from a single EPROM the processors can boot identical code or different code from the EPROM If the processors load differing code use a jump table in the loader file based on pro
5. 2 An Init Code Section this section is the initialization code which can be modified by the customer As an example an SDRAM initialization code is supplied The example setups the SDRAM controller as required by certain SDRAM types Different SDRAMs may require different initialization procedure or values 3 A Post Init Section this section restores all the register from the stack Customers should not modify the Pre Init and Post Init Sections The Init Code Section can be modified for a particular application 3 14 VisualDSP 5 0 Loader and Utilities Manual dFinc SEC K pS Eames ES Eee S pes Pais S Setu Loader Splitter for ADSP BF53x BF561 Blac kfin Processors lude lt defBF532 h gt TION program KKKKKKKKKKKKKKKKAKKP CP A THIt SOCETONK KKK KAKA KK KK KKK KKK KK KK P ASTAT Stack Pointer SP is set to the end of P RETS scratchpad memory OxXFFBOOFFC P r7 0 by the on chip boot ROM P p5 0 PIS Oph SPs LEH SPI SSR S133 Pe B03 SP BILSE SPS Bes EH SP c Bos Pali MOS Le aS PS Miele Mes Le sSP a M33 Pale Os be SPd EASE SPa ar hake SPal lay KKKKKKKKKKKKAKKAT QTL Code SOCLI ON KKK KAA KK KAKA KK KK KKK KK KK KKK x x Please insert Initialization code in this section KEKKKKKKKKKKKKKKKKKEKS DRAM Set DEA ARAER ARR RRA AIA IK AR KAKA AK p_SDRAM PO L LOCEBIU_SDR
6. Chapter 7 Loader for TigersHARC Processors Chapter 8 Splitter for SHARC and TigerSHARC Processors Appendix A File Formats Appendix B Utilities VisualDSP 5 0 Loader and Utilities Manual 1 1 Definition of Terms The code examples in this manual have been compiled using VisualDSP 5 0 The examples compiled with another version of VisualDSP may result in build errors or different output although the highlighted algorithms stand and should continue to stand in future releases of VisualDSP Definition of Terms Loader and Loader Utility The term loader refers to a loader utility that is part of the VisualDSP development tools suite The loader utility post processes one or multiple executable dxe files extracts segments that have been declared by the TYPE RAM command in a Linker Description File 1df and generates a loader file 1dr Since the dxe file meets the Executable and Linkable Format ELF standard the loader utility is often called e1floader utility See also Loader Utility Operations on page 1 11 Splitter Utility The splitter utility is part of the VisualDSP development tools suite The splitter utility post processes one or multiple executable dxe files extracts segments that have been declared by the TYPE ROM command a Linker Description File 1df and generates a file consisting of processor instructions opcodes If burned into an EPROM or flash memory
7. DMA channel DMAC6 Ox2Al DMACO 0x2A1 116 TIERO 0x20000 0x8000 IM6 IMEPO 0x1 implied 0x1 implied C6 CEPO 0x100 0x100 ETG EIEPO 0x80 0000 0x40 0000 EM6 EMEPO 0x1 implied 0x1 implied EC6 ECEPO 0x600 0x600 IRQ vector 0x20040 0x8040 Table 4 9 DMA Settings for ADSP 21160 EPROM Booting DMA Setting ADSP 21160 Processor BMS space 8M x 8 bit DMA channel DMAC10 0x4A1 4 8 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2106x 21160 SHARC Processors Table 4 9 DMA Settings for ADSP 21160 EPROM Booting Cont d DMA Setting ADSP 21160 Processor II 0x40000 IM 0x1 implied C10 0x100 EI 0x800000 EM 0x1 implied EC 0x600 IRQ vector 0x40050 After the processor s RESET pin goes inactive on start up a SHARC system configured for EPROM boot undergoes the following boot loading sequence 1 The processor BMS pin becomes the boot EPROM chip select 2 The processor goes into an idle state identical to that caused by the IDLE instruction The program counter PC is set to the processor reset vector address refer to Table 4 2 on page 4 4 The DMA controller reads 8 bit EPROM words packs them into 48 bit instruction words and transfers them into internal memory low to high byte packing order until the 256 words are loaded The DMA parameter registers for appropriate DMA channels are initialized as sh
8. W SUN DSP 5 0 Loader and Utilities Manual Analog Devices Inc One Technology Way Norwood Mass 02062 9106 Revision 2 2 March 2009 Part Number 82 000450 01 ANALOG DEVICES Copynght Information 2009 Analog Devices Inc ALL RIGHTS RESERVED This docu ment may not be reproduced in any form without prior express written consent from Analog Devices Inc Printed in the USA Disclaimer Analog Devices Inc reserves the right to change this product without prior notice Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by impli cation or otherwise under the patent rights of Analog Devices Inc Trademark and Service Mark Notice The Analog Devices logo VisualDSP Blackfin SHARC and Tiger SHARC are registered trademarks of Analog Devices Inc All other brand and product names are trademarks or service marks of their respective owners CONTENTS PREFACE Pitipiee nk This Manual accinieiiicrsscunpeanieiieiedeaceigadtabiaald dailies xiii Darende FN ARP virio pene eeusene ieee xiii Moma aS eaaa SEAR xiv Sats Newin Miis Monal dretrorori ionnan xiv Technical or Customer SUpport cise accel astro ec eaaseeetedesencens Xv Supported VOC ROSES datas cxsidi sient cdenaiaidbiaeti mbni
9. code subroutines that are part of the same VisualDSP project Initcode subroutines invoked by the initcal1 switch are not accompanied by any first boot blocks with the BFLAG_FIRST flag set In the loader file the initcode subroutines translate to boot blocks tagged by the BFLAG_INIT flag When writing an initcode subroutine in C ensure that the code does not rely on libraries or heap support which may not be available in memory by the time the initcode executes An initcode routine is expected to return properly to the boot kernel by an RTS instruction and to meet C language calling conventions see the VisualDSP 5 0 C C Compiler and Library Manual for Blackfin Processors Refer to the initcode examples provided with the VisualDSP installa tion in lt instal _path gt Blackfin ldr init_code Using VisualDSP Loader After selecting a Loader file ldr as the project output type for your Blackfin application on the Application Settings page in the VisualDSP Project Wizard modify the default load settings The Load control in the Project tree control consists of multiple pages When you open the Load Options page also called loader property page view the default load settings for the selected processor As an example Figure 2 1 shows the ADSP BF548 processor s default load settings for PROM boot mode The dialog box options are equivalent to the com mand line switches Refer to ADSP BF51x BF52x BF54x Blackfin Loa
10. elfloader pO dxe bprom fhex 1 060_prom dxe proc ADSP 21060 runs the loader utility with e p0 dxe lIdentifies the executable file to process into a boot load able file The absence of the o switch causes the output file name to default to p0 1dr e bprom Specifies EPROM booting as the boot type for the boot loadable file e fhex Specifies Intel hex 32 format for the boot loadable file 4 26 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2106x 21160 SHARC Processors e 1 060_prom exe Specifies 060_prom exe as the boot kernel file to be used in the boot loadable file e proc ADSP 21060 Identifies the processor model as ADSP 21060 File Searches File searches are important in loader processing The loader utility sup ports relative and absolute directory names default directories and user selected directories for file search paths File searches occur as described on page 1 17 File Extensions Some loader switches take a file name as an optional parameter Table 4 14 lists the expected file types names and extensions Table 4 14 File Extensions Extension File Description dxe Input executable files and boot kernel files The loader utility recognizes overlay memory files ov1 and shared memory files sm but does not expect these files on the command line Place ov1 and sm files in the same directory as the dxe file that refers to them The loader
11. the ADSP BF561 processors Table 3 6 ADSP BF561 Processor Boot Mode Selections Boot Source BMODE 1 0 16 bit external memory bypass boot ROM 00 Eight or 16 bit flash 01 SPI host 10 SPI serial EEPROM 16 bit address range 11 e Execute from 16 bit external memory execution starts from address 0x2000 0000 with 16 bit packing The boot ROM is bypassed in this mode All configuration settings are set for the slowest device possible 3 cycle hold time 15 cycle R W access times 4 cycle setup VisualDSP 5 0 Loader and Utilities Manual 3 35 ADSP BF53x BF561 Proc essor Booting Boot from eight bit 16 bit external flash memory the eight bit 16 bit flash boot routine located in boot ROM memory space is set up using asynchronous memory bank 0 All configura tion settings are set for the slowest device possible 3 cycle hold time 15 cycle R W access times 4 cycle setup Boot from SPI host the ADSP BF561 processor is configured as an SPI slave device and a host is used to boot the processor The host drives the SPI clock and is therefore responsible for the tim ing The baud rate should be equal to or less than one fourth of the ADSP BF561 system clock SCLK Boot from SPI serial EEPROM 16 bit addressable the SPI uses the PF2 output pin to select a single SPI EPROM device submits a read command at address 0x0000 and begins clocking data into the beginning of L1 instruction m
12. 1dr file is stored in a passive memory device and fetched by the processor In SPI master the 1dr file is transmitted to the processor by a host processor configured as an SPI slave In no boot mode the processor fetches and executes instructions directly from the external memory bypassing the boot kernel entirely The loader utility does not produce a file supporting the no boot mode 6 2 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2126x 2136x 2137x 2146x SHARC Processors Software developers who use the loader utility should be familiar with the following operations Power Up Booting Process on page 6 3 Boot Mode Selection on page 6 4 ADSP 2126x 2136x 2137x 2146x Processors Boot Modes on page 6 5 ADSP 2126x 2136x 2137x 2146x Processors Boot Kernels on page 6 19 ADS P 2126x 2136x 2137x 2146x Processors Interrupt Vector Table on page 6 22 ADSP 2126x 2136x 2137x 2146x Processor Boot Streams on page 6 23 Power Up Booting Process The ADSP 2126x ADSP 2136x ADSP 2137x and ADSP 2146x proces sors include a hardware feature that boot loads a small 256 instruction program into the processor s internal memory after power up or after the chip reset These instructions come from a program called a boot kernel When executed the boot kernel facilitates booting of user application code The combination of the boot kernel and application code comprise the boot
13. 4 17 ADSP 21161 processors 5 17 ADSP 2126x 36x 37x processors 6 17 6 23 b prom flash spi spislave VART TWI FIFO loader switch for ADSP BF53x processors 3 60 b prom flash spi spislave UART T W1 FIFO OTP NAND loader switch for ADSP BF51x 52x 54x processors 2 8 bprom host link loader switch for TigerSHARC 7 9 7 10 bprom host link JTAG loader switch for ADSP 2106x 160 processors 4 28 bprom host link spi loader switch for ADSP 21161 processors 5 28 bprom spislave spiflash spimaster spiprom loader switch for ADSP 2126x 36x 37x 46x processors 6 16 6 44 BSEL pin 4 6 BSO bit 4 10 build file formats list of A 4 BUSLCK bit 4 13 4 14 bypass mode See no boot mode byte stacked format files stk 8 4 8 6 8 7 A 12 C caddress loader switch for ADSP 2106x 160 processors 4 28 callback loader switch for Blackfin 2 9 C and C source files 1 8 A 2 CEPO register 4 8 5 8 5 9 5 11 5 12 CLBO register 5 13 5 14 CLKPL bit 6 9 6 11 COFF to ELF file conversion A 5 command line loader for SHARC processors 4 26 5 25 6 42 loader for TigerSHARC processors 7 6 loader splitter for Blackfin processors 2 6 3 58 splitter 8 2 8 5 compilation introduction to 1 8 compressed block headers Blackfin processors 3 12 3 51 SHARC processors 6 37 compressed streams Blackfin processors 3 50 3 54 SHARC processors 6 36 6 39 compression loader switch for Blackfin 3 49 3 61 loader switch for S
14. 6 23 blocks of application code Blackfin processors ADSP BF531 2 3 4 6 7 8 9 processors 3 9 ADSP BF535 processors 3 32 ADSP BF561 processors 3 37 blocks of application code SHARC processors ADSP 2106x 160 processors 4 17 ADSP 21161 processors 5 17 ADSP 2126x 36x 37x processors 6 23 BMODE1 0 pins ADSP BF531 2 3 8 9 processors 3 4 3 16 3 79 2 VisualDSP 5 0 Loader and Utilities Manual BMODE2 0 pins ADSP BF5 1x processors 2 3 ADSP BF534 6 7 processors 3 4 ADSP BF535 processors 3 16 3 21 3 79 BMODE3 0 pins ADSP BF52x 54x processors 2 4 BMS pins ADSP 2106x 160 processors 4 5 4 7 4 10 4 11 4 15 4 23 ADSP 21161 processors 5 4 5 6 5 9 5 13 5 15 5 22 TigerSHARC processors 7 2 7 3 boot sequences introduction to 1 11 ROM See on chip boot ROM sources See boot modes BOOT_CFG1 0 pins 6 4 6 5 6 7 BOOT_CFG2 0 pins 6 5 6 7 boot differences Blackfin processors 3 3 3 8 3 35 3 37 3 38 boot differences SHARC processors 6 11 6 16 boot file formats specifying for Blackfin processors 2 9 2 20 3 62 3 73 specifying for SHARC processors 4 29 5 28 6 45 specifying for TigerSsHARC processors 7 9 boot kernels See also kernels second stage loaders introduction to 1 15 boot loadable files introduction to 1 9 1 10 versus non bootable file 1 15 INDEX boot modes Blackfin processors ADSP BF5 1x processors 2 3 ADSP BF52x 54x processors 2 4 ADSP BF531 2 3 8 9 processors 2 3
15. ADSP BF535 Processor Boot Mode Selections Boot Source BMODE 2 0 Execution Start Address Executes from a 16 bit external memory async 000 0x2000 0000 bank 0 no boot mode bypass on chip boot ROM see on page 3 16 Boots from an eight or 16 bit flash memory 001 0xF000 0000 Boots from an eight bit address SP10 serial EEPROM 010 0xF000 0000 Boots from a 16 bit address SPIO serial EEPROM 011 0xF000 0000 Reserved 111 100 N A 1 The processor jumps to this location after the booting is complete e Execute from 16 bit external memory execution starts from address 0x2000000 with 16 bit packing The boot ROM is bypassed in this mode e Boot from eight bit external flash memory the eight bit flash boot routine located in boot ROM memory space is set up using asynchronous memory bank 0 All configuration settings are set for the slowest device possible 3 cycle hold time 15 cycle R W access times 4 cycle setup VisualDSP 5 0 Loader and Utilities Manual 3 21 ADSP BF53x BF561 Proc essor Booting e Boot from SPI serial EEPROM eight bit addressable the SP 10 uses PF10 output pin to select a single SPI EPROM device submits a read command at address 0x00 and begins clocking data into the beginning of L2 memory An eight bit addressable SPI compatible EPROM must be used e Boot from SPI serial EEPROM 16 bit addressable the SP10 uses PF10 output pin to select a single SPI EPROM
16. Build Files The bytes are ordered left to right most significant to least The termination record has the same format as the header record except for the rightmost field number of records which is all zeros Splitter Output Files in ASCII Format When the Blackfin splitter utility is invoked as a splitter utility its output can be an ASCII format file with the 1dr extension ASCII format files are text representations of ROM memory images that can be post pro cessed by users Data Memory DM Example ext_data TYPE DM ROM START Ox010000 END Ox010003 WIDTH 8 The above DM section results in the following code 00010000 32 bit logical address field 00000004 32 bit logical length field 00020201 32 bit control word 2x address multiply 02 bytes logical width O01 byte physical width 00000000 reserved 0x12 1st data word DM data is 8 bits 0x56 Ox9A OxDE 4th last data word CRC16 optional controlled by the checksum switch A 14 VisualDSP 5 0 Loader and Utilities Manual File Formats Debugger Files Debugger files provide input to the debugger to define support for simula tion or emulation of your program The debugger consumes all the executable file types produced by the linker dxe sm ov1 To simulate IO the debugger also consumes the assembler data file format dat and the loadable file formats 1dr The standard hexadecimal format f
17. However since the former proces sors do not employ a second stage loader their boot streams do not include the second stage loader code and the associated 4 byte header on the top of the kernel code There is also no 4 byte global header VisualDSP 5 0 Loader and Utilities Manual 3 9 ADSP BF53x BF561 Proc essor Booting ADSP BF53 1 BF532 BF533 BF534 BF536 BF537 BF538 BF539 Block Headers and Flags As the loader utility converts the code from an input dxe file into blocks comprising the output loader file each block receives a 10 byte header Figure 3 2 followed by a block body if a non zero block or no block body if a zero block A description of the header structure can be found in Table 3 3 HEADER OF DXE 1 DXE 1 BYTE COUNT BLOCK 1 HEADER 10 BYTE HEADER 4 BYTE ADDRESS BOOT STREAM OF THE BLOCK 1 BODY 18t EXECUTABLE DXE 1 BLOCK 2 HEADER BLOCK 2 BODY 4 BYTE COUNT 2 BYTE FLAG See T SEE FLAG INFORMATION HEADER OF DXE 2 BOOT STREAM OF THE DXE 2 BYTE COUNT 2Nd EXECUTABLE DXE 2 Figure 3 2 ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 Processors Boot Stream Structure Table 3 3 ADSP BF531 BF532 BF533 Block Header Structure Bit Field Description Address 4 byte address at which the block resides in memory 3 10 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Proc essors Table 3 3 ADSP BF53
18. IMPP register 6 6 IMSPI register 6 9 6 11 IMSRX register 5 16 IMx register 4 8 4 9 include file format 7 9 A 8 initcall ADSP BF52x 54x Blackfin loader switch 2 11 init filename loader switch for Blackfin 2 10 2 14 3 11 3 47 3 55 3 62 3 66 initialization external memory 7 10 file inclusion 2 10 2 20 3 62 3 74 initialization blocks ADSP 2126x 36x 37x 46x processors 6 24 6 26 6 27 6 28 6 30 initialization blocks Blackfin processors 2 17 ADSP BF531 2 3 4 6 7 8 9 processors 3 11 3 13 3 48 ADSP BF561 processors 3 43 3 44 3 48 code example 3 14 3 48 initialization calls 2 11 initial word option SHARC processors 6 14 6 15 INIT_L16 blocks 6 27 INIT_L48 blocks 6 26 1 8 VisualDSP 5 0 Loader and Utilities Manual INIT_L64 blocks 6 28 input file formats See source file formats input files executable dxe files 2 7 3 59 4 26 5 25 6 42 7 8 extracting memory sections from 8 5 8 6 in multiprocessor systems 7 6 instruction SRAM Blackfin processors ADSP BF531 2 3 4 6 7 8 9 processors 3 19 ADSP BF535 processors 3 33 ADSP BF561 processors 3 44 3 45 Intel hex 32 file format 2 9 3 62 7 9 A 6 internal boot mode SHARC processors 6 17 internal memory boot loadable file execution 1 10 internal vector tables 4 22 5 21 interrupt vector location 5 9 5 12 interrupt vector tables 4 22 5 21 6 17 6 18 6 22 6 29 6 30 IOP registers 4 12 4 13 IRQ vector 4
19. VisualDSP 5 0 Loader and Utilities Manual 1 15 Boot Steams Boot Streams The loader utility s output 1dr file is essentially the same executable code as in the input dxe file the loader utility simply repackages the exe cutable as shown in Figure 1 2 DXE FILE LDR FILE CODE CODE DATA DATA SYMBOLS DEBUG INFORMATION A DXE FILE INCLUDES AN LDR FILE INCLUDES DSP INSTRUCTIONS CODE AND DATA DSP INSTRUCTIONS CODE AND DATA SYMBOL TABLE AND SECTION INFORMATION RUDIMENTARY FORMATTING TARGET PROCESSOR MEMORY LAYOUT ALL DEBUG INFORMATION HAS DEBUG INFORMATION BEEN REMOVED Figure 1 2 A dxe File Versus an ldr File Processor code and data in a loader file also called a boot stream is split into blocks Each code block is marked with a tag that contains informa tion about the block such as the number of words and destination in the processor s memory Depending on the processor family there can be additional information in the tag Common block types are zero mem ory is filled with 0s nonzero code or data and final code or data Depending on the processor family there can be other block types Refer to the following chapters to learn more about boot streams 1 16 VisualDSP 5 0 Loader and Utilities Manual Introduction File Searches File searches are important in the loader utility operation The loader util ity supports relative and absolute directory names and d
20. already booted subroutine imports the idr file The loader util ity does not insert a boot kernel into the 1dr file a similar subroutine is present already on the processor Instead the loader file begins with the first header of the first block of the boot stream e To omit any interrupt vector table IVT handling In internal boot mode the boot stream is not imported by a boot kernel executing from within the IVT no self modifying FINAL_INIT code which overwrites itself with the IVT is needed Thus the loader utility does not give any special handling to the 256 instructions located in the IVT 0x80000 0x800FF for the ADSP 2126x 0x90000 0x900FF for the ADSP 2136x and 0x8C000 0x8COFF for the ADSP 2146x processors Instead the IVT code or data are handled like any other range of memory VisualDSP 5 0 Loader and Utilities Manual 6 17 ADSP 2126x 2136x 2137x 2146x Proc essor Booting To omit an initial word of 0xa5 When nokerne is selected the loader utility does not place an initial word A5 in the boot stream as required for SPI master booting To replace the FINAL_INIT block with a USER_MESG header The FINAL_INIT block which typically contains the IVT code should not be included in the 1dr file because the contents of the IVT if any is incorporated in the boot stream Instead the loader utility appends one final bock header to terminate the loader file The final block header has a block tag of 0x0
21. dm or 64 8 6 VisualDSP 5 0 Loader and Utilities Manual Splitter for SHARC and TigerSHARC Processors Table 8 2 Splitter Command Line Switches Contd Item Description proc part_number Specifies the processor type to the splitter utility This is a mandatory switch Valid processors are ADSP 21060 ADSP 21061 A ADSP 21160 ADSP 21161 ADSP 21261 ADSP 21262 A ADSP 21363 ADSP 21364 A ADSP 21367 ADSP 21368 A ADSP 21371 ADSP 21375 ADSP TS101 ADSP TS201 A D O O SP 21062 ADSP 21065L SP 21266 ADSP 21267 SP 21365 ADSP 21366 SP 21369 SP TS202 and ADSP TS203 u Byte stacked format files only The be used only in combination with the f utility to use the number in the user flags field of a byte stacked for mat file If the u switch is not used the default value for the number is 0 By default is decimal If is prefixed with 0x the splitter utility inter prets the number as hexadecimal For more information see Splitter Output Files in Byte Stacked Format on page A 12 user flags switch which may b switch directs the splitter VisualDSP 5 0 Loader and Utilities Manual 8 7 Splitter Command Line Table 8 2 Splitter Command Line Switches Contd Item Description si revision none any version The si revision none any switch provides a silicon revisio
22. ing from the three types of SPI slave devices Since SPI is a full duplex protocol the processor is receiving the same amount of bits that it sends as VisualDSP 5 0 Loader and Utilities Manual 6 11 ADSP 2126x 2136x 2137x 2146x Proc essor Booting a read command The read command comprises a full 32 bit word which is what the processor is initialized to send comprised of a 24 bit address with an 8 bit opcode The 32 bit word received while the read command is transmitted is thrown away in hardware and can never be recovered by the user Consequently special measures must be taken to guarantee that the boot stream is identical in all three cases The processor boots in least significant bit first LSB format while most serial memory devices operate in most significant bit first MSB format Therefore it is necessary to program the device in a fashion that is com patible with the required LSB format See Bit Reverse Option for SPI Boot Modes on page 6 13 for details Also because the processor always transmits 32 bits before it begins read ing boot data from the slave device the loader utility must insert extra data into the byte stream in the loader file if using memory devices that do not use the LSB format The loader utility includes an option for creat ing a boot stream compatible with both endian formats and devices requiring 16 bit and 24 bit addresses as well as those requiring no read command at all See
23. loader In VisualDSP 5 0 with the addition of the readal1 switch the loader utility for the ADSP BF51x BF52x BF54x Blackfin proces sors can call the splitter program automatically For more information see readall For TigerSHARC and SHARC processors splitter operations are handled by the splitter program e1 fsp121k exe Loader Utlity Operations Common tasks performed by the loader utility can include Processing the loader option settings or command line switches Formatting the output 1dr file according to user specifications Supported formats are binary ASCII Intel hex 32 and more Valid file formats are described in File Formats on page A 1 Packing the code for a particular data format 8 16 or 32 bit for some processors Adding the code and data from a specified initialization executable file to the loader file if applicable Adding a boot kernel on top of the user code VisualDSP 5 0 Loader and Utilities Manual 1 11 Program Development How e If specified preprogramming the location of the 1dr file in a specified PROM space e Specifying processor IDs for multiple input dxe files for a multiprocessor system if applicable You can run the loader utility from the VisualDSP Integrated Develop ment and Development Environment IDDE when the IDDE is available or from the command line In order to do so in the IDDE open the Project Options dialog box from the Project menu an
24. splitter switch 8 5 on chip boot ROM introduction to 1 14 ADSP BF531 2 3 4 6 7 8 9 processors 1 15 3 3 3 7 3 9 3 11 3 19 3 47 ADSP BF535 processors 3 21 3 23 3 25 ADSP BF561 processors 3 35 3 37 3 43 3 44 3 45 3 47 OTP boot mode ADSP BF5 1x processors 2 3 OTP boot mode ADSP BF52x 54x processors 2 4 output files See also o loader switch generating kernel and application 2 14 3 66 specifying format 1 12 A 5 specifying name 2 14 3 66 7 10 specifying with o switch B 2 specifying word width 3 69 5 29 overlay compression 6 39 overlay memory files ovl 2 7 3 59 7 8 A 5 A 15 P p loader switch for Blackfin 2 14 3 66 loader switch for TigerSHARC 7 10 packing boot data 5 2 7 2 paddress loader switch for SHARC 4 30 5 30 6 47 parallel ports 6 6 parallel serial PROM devices 1 14 pflag PF PG PH loader switch for Blackfin 3 67 3 69 3 70 3 71 3 74 PFx signals 3 67 placement rules of the command line 2 6 3 58 7 6 PMODE register 4 9 4 12 5 7 5 11 pm splitter switch 8 5 PP16 bit 6 6 PPALEPL bit 6 6 PPBHC bit 6 6 VisualDSP 5 0 Loader and Utilities Manual PPBHD bit 6 6 PPCTL register 6 5 6 6 PPDEN bit 6 6 PPDUR bit 6 6 PPEN bit 6 6 PPTRAN bit 6 6 processor IDs 4 23 4 24 5 22 5 23 7 6 7 9 assigning to dxe file 4 29 5 29 6 45 pointing to jump table 4 29 5 29 processor loadable files introduction to 1 13 processor type bits Blackfin
25. switch where e inputfile Name of the executable dxe file to be processed into a single boot loadable or non bootable file An input file name can include the drive and directory For multiprocessor or multi input systems specify multiple input dxe files Put the input file names in the order in which you want the loader utility to process the files Enclose long file names within straight quotes long file name e proc processor Part number of the processor for example proc ADSP BF542 for which the loadable file is built Provide a processor part number for every input dxe if designing multipro cessor systems see Table 2 1 e switch One or more optional switches to process Switches select operations and modes for the loader utility Command line switches may be placed on the command line in any order except the order of input files for a multi input system For a multi input system the loader utility processes the input files in the order presented on the command line 2 6 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF51x BF52x BF54x Blac kfin Proc essors File Searches File searches are important in loader processing The loader utility sup ports relative and absolute directory names default directories and user selected directories for file search paths File searches occur as described on page 1 17 File Extensions Some loader switches take a file
26. the boot format and the boot width for the output kernel file respectively Do not combine the 02 switch with nokernel on the ADSP BF535 processors Combine 02 with 1 filename and or init filename on the ADSP BF531 BF532 BF533 ADSP BF534 BF536 BF537 BF538 BF539 ADSP BF561 processors p The p switch specifies a hex flash PROM output start address for the application code A valid value is between 0x0 and OxFFFFFFFF A specified value must be greater than that specified by kp if both kernel and or initialization and application code are in the same output file a single output file 3 66 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Proc essors Table 3 10 Blackfin Loader Command Line Switch Summary Cont d proc processor Switch Description pFlag The pflag PF PGd PH F switch specifies a 4 bit hex value pFlag PF for a strobe programmable flag or for one of the ports F G or H pFlag PG There is no default value The value is dynamic and varies with pro pFlag PH cessor silicon revision boot mode and width The loader generates warnings for illegal combinations Table 3 11 Table 3 12 and Table 3 11 show the valid values for the pFlag switch Applies to the ADSP BF531 BF532 BF533 BF534 ADSP BF536 BF537 BF538 BF539 and ADSP BF561 processors only The proc processor switch specifies the target
27. 0x2000 0000 Internal SPI memory 010 0x2030 0000 External SPI memory EEPROM or flash 01 0x0000 0000 SPIO host device 100 N A One time programmable OTP memory 10 N A SDRAM memory 110 N A UARTO host 11 N A VisualDSP 5 0 Loader and Utilities Manual 2 3 Table 2 3 ADSP BF52x BF54x Boot Modes ADSP BF51x BF52x BF54x Proc essor Booting Boot Source BMODE 3 0 Start Address Idle no boot 0000 N A Eight or 16 bit external flash memory default mode 000 0x2000 0000 16 bit asynchronous FIFO 0010 0x2030 0000 Eight 16 24 or 32 bit addressable SPI memory 001 0x0000 0000 External SPI host device 0100 N A Serial TWI memory 010 0x0000 0000 TWI host 0110 N A UARTO host on ADSP BF52x processors 011 N A UART1 host on ADSP BF54x processors UART1 host on ADSP BF52x processors 000 N A Reserved on ADSP BF54x processors Reserved 001 N A SDRAM DDR 010 0x0000 0010 OTP memory 011 default page 0x40 Eight or 16 bit NAND flash memory 100 1101 0x0000 0000 16 bit host DMA 110 N A Eight bit host DMA 111 N A VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF51x BF52x BF54x Blac kfin Proc essors ADSP BF51x BF52x BF54x Proc essor Loader Guide The loader utility post processes VisualDSP executable dxe files and generates loader 1dr files A loade
28. 1 12 23 1 Revision 0 1 is distinct from and lower than revision 0 10 The digits to the left of the point specify the chip tapeout number the digits to the right of the point identify the metal mask revision num ber The number to the right of the point cannot exceed decimal 255 e The any value indicates that VisualDSP produces an out put file that can be run at any silicon revision The switch generates either a warning about any potential anomalous conditions or an error if any anomalous conditions occur In the absence of the silicon revision switch the loader utility selects the greatest silicon revision it is aware of if any S In the absence of the switch parameter a valid revision value si revision alone or with an invalid value the loader utility generates an error VisualDSP 5 0 Loader and Utilities Manual 7 11 TigerSHARC Loader Guide Using VisualDSP Interface Load Page After selecting a Loader file as the target type on the Project page in Visu alDSP Project Options dialog box modify the default options on the Load page also called loader property page Click OK to save the selec tions Selecting Build Project from the Project menu generates a loader file For information relative to a specific processor refer to the Visu alDSP online help for that processor VisualDSP invokes the elfloader utility to build the output file Dia log box buttons and fields correspond to
29. 17 VisualDSP 5 0 Loader and Utilities Manual 8 3 Splitter Command Line pm dm 64 0 pm_stuff 0 dm_stuff 0 seg code my_proj dxe Selects program memory pm data memory dm or DATA64 memory 64 as sources in the executable for extraction and placement into the image DATA64 memory does not apply to the ADSP 2106x processors Warning The pm dm or 64 switch does not apply to the ADSP TSxxx processors Because these are the only switches used to identify the memory source the specified sources are PM DM or DATA64 memory sections Because no other content switches appear on these command lines the output file format defaults to a Motorola 32 bit format and the PROM word width of the output defaults to 8 bits for all PROMs Specify names for the output files Use different names so the output of a run does not overwrite the output of a previous run The output names are pm_stuff s_ and dm_stuff s_i The splitter utility adds the s_ file extension to the output files is a number that differenti ates one output file from another Specifies the name of the input dxe file to be processed into non bootable PROM image files Output File Extensions The splitter utility follows the conventions shown in Table 8 1 for output file extensions Table 8 1 Output File Extensions Extension File Description S_ Motorola S record format file The indicates the position 0 least sign
30. 2 19 ADSP BF51x BF52x BF54x Processor Loader Guide Table 2 6 Base Load Page Settings for ADSP BF51x BF52x BF54x Processors Cont d Setting Description Boot format Specifies Intel hex ASCII include or binary format Output width Specifies eight or 16 bits Use default start address Uses the default flash PROM output start address in hex format for the application code Start address Specifies a flash PROM output start address in hex format for the appli cation code Verbose Generates status information as the loader utility processes the files Initialization file Directs the loader utility to include the initialization file init code Output file Names the loader utility s output file Additional options Specifies additional loader switches You can specify additional input files for a multi input system Type the input file names with the paths if the files are not in the current working directory separate any two file names with a space in order for the loader utility to retrieve the files Note The loader utility processes the input files in the order in which the files appear on the command line generated from the property page Using VisualDSP Sec ond Stage Loader If you use a second stage loader select Kernel under Load in the Project Options tree control The page shows the default settings for a loader file that does not include a second
31. 2106x 0x20004 ADSP 21065L and 0x800004 ADSP 21160 in external memory space All DMA control and parameter registers are set to their default initializa tion values The loader utility is not intended to support no boot mode ADSP 2106x 21160 Boot Kemels The boot loading process starts with a transfer of the boot kernel program into the processor memory The boot kernel sets up the processor and loads boot data After the boot kernel finishes initializing the rest of the system the boot kernel loads boot data over itself with a final DMA transfer Boot kernels are loaded at reset into program segment seg_idr which is defined in e 06x_ldr 1df for the ADSP 2106x processors e 065L_idr idf for the ADSP 21065L processors e 160_ldr 1df for the ADSP 21160 processors The files are stored in the lt insta7 _path gt 21k 1dr ADSP 2106x proces sors and 211xx ldr ADSP 21160 processors directories of VisualDSP The default boot kernel files shipped with VisualDSP are listed in Table 4 11 4 16 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2106x 21160 SHARC Processors Table 4 11 ADSP 2106x 21160 Default Boot Kernel Files Processor PROM Booting Link Booting Host Booting ADSP 21060 060_prom asm 060_link asm 060_host asm ADSP 21065L 065L_prom asm N A 065L_host asm ADSP 21160 160_prom asm 160_link asm 160_host asm Once the boot kernel has been loaded successfully into the
32. 8 4 9 IVG15 lowest priority interrupt 3 7 3 12 3 23 3 37 K kb prom flash spi spislave VART TWI FIFO loader switch for Blackfin 3 63 kb prom flash spi spislave uart twilfifo otp na nd loader switch for Blackfin 2 12 kenc dll_ filename loader switch for Blackfin 3 63 Kernel Load page Blackfin processors 2 20 3 76 INDEX kernels ADSP 2106x 160 processors boot sequence 4 3 4 16 default source files 4 17 4 21 loading to processor 4 10 4 13 modifying 4 19 rebuilding 4 22 replacing with application code 4 18 specifying user kernel 4 30 kernels ADSP 21161 processors boot sequence 5 3 default source files 5 16 5 19 modifying 5 18 5 19 rebuilding 5 18 5 19 kernels ADSP 2126x 36x 37x 46x processors boot sequence 6 3 6 19 compression decompression 6 35 6 36 6 40 default source files 6 19 loading to processor 6 8 6 13 modifying 6 20 omitting in output 6 17 rebuilding 6 20 6 21 kernels Blackfin processors See also second stage loader compression decompression 3 50 3 55 graphical user interface 2 20 3 76 omitting in output 3 65 specifying boot mode 2 12 2 19 3 63 3 73 specifying file format 2 12 2 13 3 63 specifying file width 2 20 3 64 3 73 specifying hex address 2 12 3 63 specifying hold time 3 74 specifying kernel and app files 2 22 3 77 specifying user kernel 2 13 3 64 kernels TigerSHARC processors modifying 7 5 omitting in output 7 4 7 10 sou
33. ADSP 21161 Processor Boot Kernels on page 5 16 for more information Refer to the ADSP 21161 SHARC DSP Hardware Reference for detailed information on DMA and system configurations DMA channel differences between the ADSP 21161 and previous SHARC family processors ADSP 2106x account for boot differ ences Even with these differences the ADSP 21161 processors support the same boot capabilities and configuration as the ADSP 2106x processors The processor determines the boot mode at reset from the EB00T LBOOT and BMS pin inputs When EBO0T 0 LBOOT 1 and BMS 1 the processor boots through the link port For information on boot mode selection see Table 5 1 and Table 5 2 on page 5 4 When using any of the power up booting modes address 0x40004 should not contain a valid instruction Because it is not executed during the boot sequence place a NOP or IDLE instruction at this location In link port boot the processor gets boot data from another processor link port or 4 bit wide external device after system power up The external device must provide a clock signal to the link port assigned to link buffer 0 The clock can be any frequency up to the processor clock frequency The clock falling edges strobe the data into the link port The most significant 4 bit nibble of the 48 bit instruction must be down loaded first Table 5 5 shows how the DMA channel 8 parameter registers are initial ized at reset The count register CL
34. ADSP BF534 6 7 processors 3 4 ADSP BF535 processors 3 21 ADSP BF561 processors 3 35 specifying 2 8 2 19 3 60 3 73 boot mode select pins Blackfin processors ADSP BF5 1x processors 2 3 ADSP BF52x 54x processors 2 4 ADSP BF531 2 3 4 6 7 8 9 processors 3 4 ADSP BF535 processors 3 21 boot mode select pins SHARC processors ADSP 21161 processors 5 4 ADSP 2116x 160 processors 4 5 4 6 ADSP 2126x 36x 37x processors 6 4 ADSP 2146x processors 6 5 boot mode select pins TigerSsHARC processors 7 2 7 3 boot modes SHARC processors ADSP 2106x 160 processors 4 2 4 7 ADSP 21161 processors 5 2 5 5 ADSP 2126x 36x 37x 46x processors 6 2 ADSP 2126x 36x 37x processors 6 4 ADSP 2146x processors 6 5 specifying 4 28 5 28 6 4 6 5 6 44 boot process introduction to 1 9 boot sequences Blackfin processors ADSP BF531 2 3 4 6 7 8 9 processors 3 8 ADSP BF535 processors 3 8 3 24 ADSP BF561 processors 3 35 boot sequences SHARC processors ADSP 21161 processors 5 3 ADSP 2116x 160 processors 4 3 ADSP 2126x 36x 37x 46x processors 6 3 bootstraps 1 14 1 15 3 65 7 2 boot streams introduction to 1 14 1 15 1 16 VisualDSP 5 0 Loader and Utilities Manual 1 3 INDEX boot streams Blackfin processors ADSP BF531 2 3 4 6 7 8 9 processors 3 9 3 47 ADSP BF535 processors 3 27 3 28 ADSP BF561 processors 3 37 3 40 3 47 similarities between 3 9 boot streams SHARC processors ADSP 2106x 160 processors
35. BF561 processors In case of an ADSP BF535 processor choose between the default or user sec ond stage loader file The following default second stage loaders are currently available for the ADSP BF535 processors Boot Mode Second Stage Loader File Eight bit flash PROM 535_prom8 dxe 16 bit flash PROM 535_proml6 dxe SPI 535_spi dxe For the ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 BF561 processors no second stage loaders are required hence no default kernel files are provided You can supply your own second stage loader file if so desired steps 3 and 4 5 To produce two output files select the Output kernel in separate file check box This option allows to boot the second stage loader with an initialization code if any from one source and the appli VisualDSP 5 0 Loader and Utilities Manual 3 77 ADSP BF53x BF561 Processor Loader Guide cation code from another source You can specify the kernel output file options such as the Boot Mode source Boot Format and Output Width 6 Select Change hex output kernel code start address to specify the Start address in hex format for the second stage loader code This option allows you to place the second stage loader file at a specific location within the flash PROM 7 Click OK to complete the loader setup Using VisualDSP ROM Splitter Unlike the loader utility the splitter does not format the application data when
36. Block header Bits 0 15 define the type of data block tag Second word Bits 16 47 are the start address of the block Bits 0 15 are the word count for the block Block body Word 1 48 bits if not a zero block Word 2 48 bits Table 4 13 ADSP 2106x 21160 Processor Loader Block Tags Tag Number Block Type Tag Number Block Type 0x0000 final init 0x000A zero pm48 0x0001 zero dml6 0x000B init pm16 0x0002 zero dm32 0x000C init pm32 0x0003 zero dm40 0x000E init pm48 0x0004 init dm16 0x000F zero dm64 ADSP 21160 only 0x0005 init dm32 0x0010 init dm64 ADSP 21160 only 0x0007 zero pm16 0x0011 zero pm64 ADSP 21160 only 0x0008 zero pm32 0x0012 init pm64 ADSP 21160 only 0x0009 zero pm40 The kernel enables the boot port external or link to read the block header After reading information from the block header the kernel places the body of the block in the appropriate place in memory if the block has a block body or initializes in the appropriate place with zero values in the memory if the block is a zero block The final section which is identified by a tag of 0x0 is called the final ini tialization section This section has self modifying code that when executed facilitates a DMA over the kernel replacing it with user applica 4 18 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2106x
37. Boot Stream Table 6 16 Multiprocessor ID Fields Processor ID Number Loader ID Field 0 0x00000001 1 0x00000002 2 0x00000004 3 0x00000008 4 0x00000010 5 0x00000020 6 0x00000040 7 0x00000080 1 amp amp 4 0x00000012 6 amp amp 7 0x000000C0 The multiprocessor tag processor ID and the offset are encapsulated in a multiprocessor header The multiprocessor header includes three 32 bit words the multiprocessor tag the ID 0 7 of the associated processor dxe file in the lowest byte of a word and the offset to the next multipro cessor tag The loader id exe filename switch is used to assign a 6 34 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2126x 2136x 2137x 2146x SHARC Processors processor ID number to an executable file The loader id ref N switch is used to share the same executable file by setting multiple bits in the ID field Figure 6 4 shows the multiprocessor header structure PROCESSOR IDS OFFSET TO NEXT MULITPROCESSOR HEADER Figure 6 4 Multiprocessor Header ADSP 2126x 2136x 2137x 2146x Processors Compression Support The loader utility for the ADSP 2126x 2136x 2137x 2146x processors offers a loader file boot stream compression mechanism known as zLib The zLib compression is supported by a third party dynamic link library zLib1 d11 Additional information about the library can be obtained from the http www zlib
38. CONTENTS LOADER FOR TIGERSHARC PROCESSORS TigerSHARC Processor Boong sesescccscueeniensieeueeiend 7 2 Post Te dauno ane 7 3 TigerS HARC Processor Boot Kernels isscanusirsssanasesarnhussiant 7 4 Boot Kernel Modification ase ssecesacd cients custiseascadensevanccectuameddenss 7 5 Tighe el Loader Gide cc eens 7 5 Using TigerSHARC Loader Command Line aiscesisesrcrssssuenuicnis 7 6 File Searches aairoicetierncieeeeaeie eee 7 8 File Pe aioe 7 8 TigerS HARC Command Line Switches tcc sicercincscoscncsiseranses 7 9 Using VisualDSP Interface Load Page ccccscacecincusstuwsnsnnsnens 7 12 SPLITTER FOR SHARC AND TIGERSHARC PROCESSORS Splitter Command Line ccrinremancninintiukaninin i eaii 8 2 EE EE E E O E E T 8 3 Ratt Pile Entenc iong accede 8 4 Splitter Command Line Switches eis caysnnsisepcecersiicorapecteacsansciies 8 5 ViuelDS Pee Interlace Split Papel ocesannarerininn aa 8 9 FILE FORMATS IE PE orion la eee A 1 DoE a A E E E A 2 Assembly Sonree PSS siioliss tis uerinrtdnatenddiohiinencabimmialolbials A 2 Assembly Initialization Data Files screcsircesnroricranimansu A 2 VisualDSP 5 0 Loader and Utilities Manual xi CONTENTS A Te pect E A E A A 3 Linkar Dacnpaom PAS scissioni A 4 Linker Command Line Files sorisrnnncnonreruinernieita A 4 EE E E A E AE A E A E ATT A 4 Assembler Objeot Piles sccicseicadscouwainsinedeaienmlecsntiaaearcdenss A 5 Library EE aone n A 5 Linker Opie PISS doen r eee A 5 Memor Map FIEF insides A 6 L
39. Documentation Format pdf files for all manuals are provided on the VisualDSP installation CD VisualDSP 5 0 Loader and Utilities Manual xvii CONTENTS Each documentation file type is described as follows File Description chm Help system files and manuals in Microsoft help format htm or Dinkum Abridged C library and FLEXnet License Tools software documenta htm tion Viewing and printing the htm1 files requires a browser such as Internet Explorer 6 0 or higher pdf VisualDSP and processor manuals in PDF format Viewing and printing the pdf files requires a PDF reader such as Adobe Acrobat Reader 4 0 or higher Technical Library CD The technical library CD contains seminar materials product highlights a selection guide and documentation files of processor manuals Visu alDSP software manuals and hardware tools manuals for the following processor families Blackfin SHARC TigerSsHARC ADSP 218x and ADSP 219x To order the technical library CD go to http www analog com proces sors technical_library navigate to the manuals page for your processor click the request CD check mark and fill out the order form Data sheets which can be downloaded from the Analog Devices Web site change rapidly and therefore are not included on the technical library CD Technical manuals change periodically Check the Web site for the latest manual revisions and associated document
40. Finally after booting the second stage loader jumps to the start of L2 memory 0xF000 0000 for application code execution Figure 3 10 ADSP BF535 Processor PROM Flash or SPI Device 2nd Stage Loader Application Code Data Figure 3 10 ADSP BF535 Processors Starting Application Code ADSP BF535 Processor Boot Steams The loader utility generates the boot stream and places the boot stream in the output loader 1dr file The loader utility prepares the boot stream in a way that enables the on chip boot ROM and the second stage loader to load the application code and data to the processor memory correctly Therefore the boot stream contains not only user application code but also header and flag information that is used by the on chip boot ROM and the second stage loader VisualDSP 5 0 Loader and Utilities Manual 3 27 ADSP BF53x BF561 Proc essor Booting The following diagrams illustrate boot streams utilized by the ADSP BF535 processor s boot kernel e Loader Files Without a Second Stage Loader on page 3 28 e Loader Files With a Second Stage Loader on page 3 29 e Global Headers on page 3 31 e Block Headers and Flags on page 3 32 Loader Files Without a Second Stage Loader Figure 3 11 is a graphical representation of an output loader file for eight bit flash PROM boot and eight 16 bit addressable SPI boot with out the second stage loader OUTPUT LDR FILE 4 BYTE HEADER FOR BYTE COU
41. Initial Word Option for SPI Master Boot Modes on page 6 14 for details Figure 6 1 shows the initial 32 bit word sent out from the processor As shown in the figure the processor initiates the SPI master boot process by writing an 8 bit opcode LSB first to the slave device to specify a read operation This read opcode is fixed to 0xC0 0x03 in MSB first format Following that a 24 bit address all zeros is always driven by the proces 6 12 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2126x 2136x 2137x 2146x SHARC Processors sor On the following SPICLK cycle cycle 32 the processor expects the first bit of the first word of the boot stream This transfer continues until the boot kernel has finished loading the user program into the processor SPICLK J Driven by MASTER I taer rr e MASTER OUT SLAVE IN K Cmn A15 88 X AT A0 T mosi SPI SLAVE A E Processor 0x00 X 0x00 oxoo Y 0xA5 ED MASTER IN SLAVE OUT as MISO Slave Processor TX s PILAN i anytime SPICLK driven J 1 gt I PROM i fst KNL MASTER IN SLAVE OUT 1 BYTE MISO i I the FOURTH byte must be 0x45 SFLEROM doesnt i DATA clocked into DSP during this recieves a read cycle MUST be OxAS5 If slave device command and address is an SPI PROM then the FIRST byte must be 0xA5 1 I i Ifthe SPI slave device is a processor 1 1 1 Figure 6 1 SPI Master Mode Booting Us
42. PM or 64 bits for 64 bit memory Example elfspl21k dm r 16 16 8 myfile dxe This command extracts data memory ROM from myfile dxe and creates the following output PROM files e myfile s_0 8 bits wide contains bits 7 0 e myfile s_l1 16 bits wide contains bits 23 8 e myfile s_2 16 bits wide contains bits 39 24 The width of the three output files is 40 bits ram The ram include RAM in PROM switch directs the splitter utility to extract RAM sections from the inputfile The dm pm and 64 switches select the memory The s switch is not influenced by the ram switch f h f sl f s2 f S3 f b The f PROM file format switch directs the splitter utility to gener ate a non bootable PROM image file in the specified format Available selection include e h Intel hex 32 format e s1 Motorola EXORciser format e s s2 Motorola EXORMAX format e s3 Motorola 32 bit format e b byte stacked format If the f switch does not appear on the command line the default format for the PROM file is Motorola 32 bit s3 For information on file formats see Build Files on page A 4 s section_name The s include memory section switch directs the splitter utility to extract the contents of the specified memory section sect jon_name Use the s section_name switch as many times as needed Each instance of the s switch can specify only one sect ion_name Warning Do not use s with pm
43. SRAM data is not booted automatically MEM_DATA_RAM TYPECRAM STARTCOXFF903000 END OXFF907FFF WIDTH 8 Listing 3 7 ROM Segment Definitions LDF File Example PROCESSOR pO OUTPUT COMMAND_LINE_OUTPUT_FILE SECTIONS program_rom 3 80 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Proc essors INPUT_SECT INPUT_SECT TION_ALIGN 4 TIONS OBJECTS rom_code gt MEM_PROGRAM_ROM data_ro INPUT_SECT INPUT_SECT TION _ALIGN 4 TIONS OBJECTS rom_data gt MEM_DATA_ROM data_sram INPUT_SECTION_ALIGN 4 INPUT_SECTIONS OBJECTS ram_data gt MEM_DATA_RAM With the LDF file modified this way the source files can now take advan tage of the newly introduced sections as in Listing 3 8 Listing 3 8 Section Handling Source File Example SECTION rom_code _reset_vector 10 0 T 12 0 13 0 continue with setup and application code es a SECTION rom_data VAR myconst x Oxdeadbeef IR g me SECTION ram_data VAR myvar y n ote that y cannot be initialized automatically VisualDSP 5 0 Loader and Utilities Manual 3 81 ADSP BF53x BF561 Processor Loader Guide 3 82 VisualDSP 5 0 Loader and Utilities Manual 4 LOADER FOR ADSP 2106X 21160 SHARC PROC ESSO RS This chapter explains how the loader utility e floader exe is used to convert e
44. See also global headers header records byte stacked format stk A 13 s record format s_ A 10 hexadecimal format See h_ Intel hex 32 file format hexutil utility B 2 h_ Intel hex 32 file format 7 9 8 4 8 6 A 6 A 12 HoldTime loader switch for Blackfin 3 62 hold time cycles 3 24 3 38 host boot mode introduction to 1 14 host boot mode SHARC processors ADSP 2106x 160 processors 4 2 4 6 4 11 4 13 4 24 ADSP 21161 processors 5 2 5 9 ADSP 2126x 36x 37x 46x processors 6 7 6 10 6 17 host boot mode TigerSsHARC processors 7 2 7 4 7 9 host DMA boot mode ADSP BF52x 54x processors 2 4 hostwidth loader switch for SHARC 5 29 6 15 6 26 6 45 HPM bit 4 12 I ICPP register 6 6 id exe filename loader switch for SHARC 4 24 4 29 5 23 5 29 6 45 loader switch for TigerSHARC 7 6 7 9 id exe N loader switch for SHARC 5 29 IDLE instruction 4 4 4 14 4 19 4 20 5 6 5 10 5 13 5 15 6 22 idle state 3 38 7 3 id ref N loader switch for SHARC 4 29 6 46 ignore blocks Blackfin processors ADSP BF531 2 3 4 6 7 8 9 processors 3 12 ADSP BF561 processors 3 39 IIEPO register 4 8 5 8 5 11 IILBO register 5 14 IPP register 6 6 SPI register 6 9 6 11 IISRX register 5 16 IIVT bit 4 22 5 21 6 22 IIx register 4 8 4 9 4 15 image files See PROM non bootable files IMASK register 4 13 4 14 4 16 IMDYW register 4 14 6 30 IMEP0 register 4 8 5 8 5 11 IMLBO register 5 14
45. Table 5 4 shows how the DMA channel 10 parameter registers are initial ized at reset for host boot The internal count register CEPO is initialized to 0x0100 to transfer 256 words to internal memory The DMAC10 control register is initialized to 0000 0161 The default value sets up external port transfers as follows e DEN 1 external port enabled e MSWF 0 LSB first e PMODE 101 8 bit to 48 bit packing e DTYPE 1 three column data Table 5 4 DMA Channel 10 Parameter Register for Host Boot Parameter Register Initialization Value IIEPO 0x0004 0000 IMEPO Uninitialized increment by 1 is automatic CEPO 0x0100 256 instruction words CPEPO Uninitialized GPEPO Uninitialized EIEPO Uninitialized EMEPO Uninitialized ECEPO Uninitialized At system start up when the processor RESET input goes inactive the fol lowing sequence occurs 1 The processor goes into an idle state identical to that caused by the IDLE instruction The program counter PC is set to address 0x40004 2 The DMA parameter registers for channel 10 are initialized as shown in Table 5 4 VisualDSP 5 0 Loader and Utilities Manual 5 11 ADSP 21161 Proc essor Booting 3 The host uses HBR and CS to arbitrate for the bus 4 The host can write to SYSCON if HBG and READY are returned to change boot width from default 5 The host writes boot information to external port buffer 0
46. The digits to the left of the point specify the chip tapeout number the digits to the right of the point identify the metal mask revision number The number to the right of the point cannot exceed decimal 255 e The any value indicates that VisualDSP produces an output file that can be run at any silicon revision The switch generates either a warning about any potential anoma lous conditions or an error if any anomalous conditions occur S In the absence of the silicon revision switch the loader utility selects the greatest silicon revision it is aware of if any v The v switch directs the loader utility to output verbose loader messages and status information as the loader processes files waits The waits switch specifies the number of wait states for external access Valid inputs are 0 through 15 Default is 15 Wait states apply to the flash PROM boot mode only Applies to the ADSP BF535 processors only 3 68 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Processors Table 3 10 Blackfin Loader Command Line Switch Summary Contd Switch Description width The width switch specifies the loader output file s width in bits Valid values are eight and 16 depending on the boot mode The default value is 16 for FIFO boot mode and ei ght for all other boot modes On the ADSP BF535 processors the switch has no effect on boot ke
47. USER_MESG The header indicates to a subroutine processing the boot stream that this is the end of the stream The header contains two 32 bit data words instead of count and address information unlike the other headers The words can be used to provide version number error checking additional commands return addresses or a number of other messages to the importing subroutine on the processor The two 32 bit values can be set on the command line as argu ments to the nokernel message1 message2 switch The first optional argument is msg_word1 and the second optional argument is msg_word2 where the values are interpreted as 32 bit unsigned numbers If only one argument is issued that argument is msg_word1 It is not possible to specify msg_word2 without specify ing msg_word1 If one or no arguments are issued at the command line the default values for the arguments are 0x00000000 Listing 6 1 shows a sample format for the USER_MESG header Listing 6 1 Internal Booting FINAL_INIT Block Header Format 0x00000000 USER_MESG tag 0x00000000 msg_wordl 1st cmd line parameter 0x00000000 msg_word2 2nd cmd line parameter VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2126x 2136x 2137x 2146x SHARC Processors ADSP 2126x 2136x 2137x 2146x Processors Boot Kemels The boot loading process starts with a transfer of the boot kernel program into the processor memory The boot kernel sets up the pro
48. Using ADSP 2106x 21160 Loader Command Line 00 4 26 A eget eee eee 4 27 NG ccc etcetera 4 27 ADSP 2106x 21160 Loader Command Line Switches 4 28 Using VisualDSP Interface Load Page cersescssssoacrnvenesuieere 4 32 VisualDSP 5 0 Loader and Utilities Manual vii CONTENTS LOADER FOR ADSP 21161 SHARC PROCESSORS AIST 21 161 Processor Booting siacinssaciemiawieeeieuinerieeenes 5 2 Power Up Booting Procesi cnemecsansenennannenmennani 5 3 Boot Mode Selecion wcities enone 5 4 ADSP 21161 Processor Boot Modes circa s esiscassicceveerenseaseccnstunces 5 5 EPROM Boor Mod scarta 5 5 Host Boot Mode secrerotetnrcrinin ieirik aani 5 9 Link Port Boor Mode aacciccettorenioes corres 5 12 SPIL Port Doat Mode nner 5 14 No Boot Mode oroc asnien n S 5 16 ADSP 21161 Processor Boot Kernels sc ccseaceciesonsusecsaxseopersnasnss 5 16 ADSP 21161 Processor Boot Streams srisirorinkarariiravi 5 17 Boot Kernel Modification and Loader Issues 00008 5 18 Rebuilding a Boor Kernel File socrcrissniorinnensimi 5 18 Rebuilding a Boot Kernel Using Command Lines 5 19 Loader Pile Kauss cues en N 5 20 ADSP 21161 Processor Interrupt Vector Table sersroraninisci 5 21 ADSP 21161 Multi Application Multi DXE Management 5 21 Boot From a Siogle EPROM scriorerisinoneninisusneiakai 5 22 Seguenal EPRONT BOOT arcs 5 22 Piocessor 1D Numbers aiseiosn ienn no 5 23 ADSP 21161 Processor Loader Guide cssarcssasrevcreatxarcnarsartevisa
49. Utilities Manual File Formats e Splitter Output Files in Byte Stacked Format on page A 12 e Splitter Output Files in ASCII Format on page A 14 Assembler Object Files Assembler output object files doj are binary object and linkable files ELF Object files contain relocatable code and debugging information for a DSP program s memory segments The linker processes object files into an executable file dxe For information on the object file s ELF for mat see Format References on page A 16 Library Files Library files d1b the output of the archiver are binary object and link able files ELF Library files called archive files in previous software releases contain one or more object files archive elements The linker searches through library files for library members used by the code For information on the ELF format used for executable files refer to Format References on page A 16 The archiver automatically converts legacy input objects from COFF to ELF format Linker Output Files The linker s output files dxe sm ov1 are binary executable files ELF The executable files contain program code and debugging information The linker fully resolves addresses in executable files For information on the ELF format used for executable files see the TIS Com mittee texts cited in Format References on page A 16 The loaders splitter utilities are used to convert executable
50. and BMS pin inputs When EB00T 1 and LB00T 0 the processor boots from an EPROM through the external port and uses BMS as the memory select output For information on boot mode selection see the boot memory select pin descriptions in Table 5 1 and Table 5 2 on page 5 4 When using any of the power up boot modes address 0x40004 should not contain a valid instruction since it is not executed dur ing the booting sequence Place a NOP or IDLE instruction at this location EPROM boot boot space 8M x 8 bit through the external port requires that an 8 bit wide boot EPROM be connected to the processor data bus pins 23 16 DATA23 16 The processor s lowest address pins should be connected to the EPROM address lines The EPROM s chip select should be connected to BMS and its output enable should be connected to RD 5 6 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 21161 SHARC Processors In a multiprocessor system the BMS output is driven by the ADSP 21161 processor bus master only This allows the wired OR of multiple BMS signals for a single common boot EPROM Systems can boot up to six ADSP 21161 processors from a single EPROM using the same code for each processor or differing code for each processor During reset the ACK line is internally pulled high with the equivalent of an internal 20K ohm resistor and is held high with an internal keeper latch It is not necessary to use an external pull up resistor on the
51. and initialization data the 256 words typ ically serve as a loading routine for the application VisualDSP includes loading routines boot kernels which load an entire program through the selected port See ADSP 21161 Processor Boot Kernels on page 5 16 for more information 5 14 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 21161 SHARC Processors Refer to the ADSP 21161 SHARC DSP Hardware Reference for detailed information on DMA and system configurations For information about SPI slave booting refer to EE 177 SHARC SPI Booting located on the Analog Devices processor Web site The processor determines the boot mode at reset from the EB00T LBOOT and BMS pin inputs When EB00T 0 LBOOT 1 and BMS 0 the processor boots through its SPI port For information on the boot mode selection see Table 5 1 and Table 5 2 on page 5 4 When using any of the power up booting modes address 0x40004 should not contain a valid instruction Because it is not executed during the boot sequence place a NOP or IDLE instruction placed at this location For SPI port boot the processor gets boot data after system power up from another processor s SPI port or another SPI compatible device Table 5 6 shows how the DMA channel 8 parameter registers are initial ized at reset The SPI control register SPICTL is configured to 0x0A001F81 upon reset during SPI boot This configuration sets up the SPIRx register for 32 bit ser
52. and performs eight bit DMA A 0x20 byte also assumes 16 bit memory but performs 16 bit DMA e Boot from serial SPI memory EEPROM or flash eight 16 or 24 bit addressable devices are supported as well as AT45DB041 AT45DB081 AT45DB161 AT45DB321 AT45DB642 and AT45DBI1282 DataFlash devices from Atmel The SPI uses the PF10 SPI SSEL1 output pin to select a single SPI EEPROM flash device submits a read command and successive address bytes 0x00 until a valid eight 16 or 24 bit or Atmel addressable device is detected and begins clocking data into the processor e Boot from SPI host device the Blackfin processor operates in SPI slave mode and is configured to receive the bytes of the 1dr file from an SPI host master agent To hold off the host device from transmitting while the boot ROM is busy the Blackfin processor asserts a GPIO pin called host wait HWAIT to signal the host device not to send any more bytes until the flag is deasserted The flag is chosen by the user and this information is transferred to the Black fin processor via bits 10 5 of the FLAG header VisualDSP 5 0 Loader and Utilities Manual 3 5 ADSP BF53x BF561 Proc essor Booting Boot from UART using an autobaud handshake sequence a boot stream formatted program is downloaded by the host The host agent selects a baud rate within the UART s clocking capabili ties When performing the autobaud the UART expects an boot stre
53. bit word at a time Once the last word is written the processor takes over and runs the user code 7 2 VisualDSP 5 0 Loader and Utilities Manual Loader for TigerSHARC Processors e In link port boot mode the processor receives boot data via its link port from another TigerSHARC processor EE 174 ADSP TS1018S TigerSHARC Processor Boot Loader Kernels Operation and EE 200 ADSP TS20x TigerSHARC Processor Boot Loader Kernels Operation provide additional information about the loader These EE notes are available from the Analog Devices Web site at http www analog com processors processors tiger sharc technicalLibrary index html Boot Type Selection To determine the boot mode a TigersHARC processor samples its boot mode select BMS pin While the processor is held in reset the BMS pin is an active input If BMS is sampled low a certain number of clock cycles after reset EPROM flash boot is selected and after RESET goes high BMS becomes an output acting as EPROM chip select If BMS is sampled high after reset the TigerSHARC processor is at an IDLE state waiting for a host or link boot The 100K Ohm internal pull down on BMS may not suffice depending on the line loading Thus an additional external pull down resistor may be necessary for the EPROM boot mode If host or link boot is desired BMS must be high and may be tied directly to the system power bus VisualDSP 5 0 Loader and Utilities Manual 7 3
54. booting is initialized at reset to both internal wait and external acknowledge required The internal keeper latch on the ACK pin initially holds acknowledge high asserted If acknowledge is driven low by another device during an EPROM boot the keeper latch may latch acknowledge low The processor views the deasserted low acknowledge as a hold off from the EPROM In this condition wait states are continually inserted pre venting completion of the EPROM boot When writing a custom boot kernel change the WAIT register early within the boot kernel so UBWM is set to internal wait mode 01 Host Boot Mode The ADSP 2106x 21160 processors accept data from a 8 and 16 bit host microprocessor or other external device through the external port EP80 and pack boot data into 48 bit instructions using an appropriate DMA channel The host is selected when the EB00T and LBOOT inputs are low and BMS is high Configured for host booting the processor enters the slave mode after reset and waits for the host to download the boot program Table 4 10 lists host connections to processors VisualDSP 5 0 Loader and Utilities Manual 4 11 ADSP 2106x 21160 Proc essor Booting Table 4 10 Host Connections to ADSP 2106x 21160 Processors Processor Connection Data Bus Pins ADSP 21060 61 62 Host connected to DATA47 16 or DATA31 16 pins based on HPM bits ADSP 21065L Host connected to DATA31 0 or DATA15 0 or DATA7 0 pins ba
55. boots from a host processor through the processor s external port les YI I O T Boot memory select When boot loading from an EPROM EB00T 1 and LBOOT 0 this pin is an output and serves as the chip select for the EPROM In a multiprocessor system BMS is output by the bus master When host booting or link booting EBOOT 0 BMS is an zmput and must be high 1 Three statable in EPROM boot mode when BMS is an output Table 4 4 ADSP 21060 061 062 and ADSP 21160 Boot Modes EBOOT LBOOT BMS Boot Mode 0 0 0 Input No boot processor executes from external memory 0 0 1 Input Host processor 0 1 0 Input Reserved 0 1 1 Input Link port 1 0 Output EPROM BMS is chip select 1 1 x Input Reserved VisualDSP 5 0 Loader and Utilities Manual 4 5 ADSP 2106x 21160 Proc essor Booting Table 4 5 ADSP 21065L Boot Mode Pins Pin Type Description BMS VO T Boot memory select When BSEL is low BMS is an input pin and selects between host boot mode and no boot mode In no boot mode the processor executes from external memory For no boot mode connect BMS to ground For host boot mode connect BMS to VDD When BSEL is high BMS is an output pin and the processor starts up in EPROM boot mode Connect BMS to the EPROM s chip select BSEL I EPROM boot select Hardwire this signal it is used for system configuration When BSEL is h
56. cannot exceed decimal 255 e The any value indicates that VisualDSP produces an output file that can be run at any silicon revision The switch generates either a warning about any potential anoma lous conditions or an error if any anomalous conditions occur S In the absence of the switch parameter a valid revi sion value si revision alone or with an invalid value the loader utility generates an error Vv Outputs verbose loader messages and status information as the loader utility processes files version Directs the loader utility to show its version information Type elfloader version to display the version of the loader drive Add the proc switch for example elfloader proc ADSP 21262 version to display version information of both loader drive and SHARC loader 6 48 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2126x 2136x 2137x 2146x SHARC Processors Using VisualDSP Interface Load Page After selecting a Loader file as the target type on the Project page in Visu alDSP Project Options dialog box modify the default options on the Load pages also called loader property page Click OK to save the selec tions Selecting Build Project from the Project menu generates a loader file For information relative to a specific processor refer to the Visu alDSP online help for that processor VisualDSP invokes the elfloader utility to build the output file Dia log box
57. chip select for the EPROM In a multiprocessor system BMS is output by the bus master When host booting link booting or SPI booting EBOOT 0 BMS is an input and must be high 1 Three statable in EPROM boot mode when BMS is an output Table 5 2 ADSP 21161 Boot Mode Pin States EBOOT LBOOT BMS Booting Mode 1 0 Output EPROM connects BMS to EPROM chip select 0 0 1 Input Host processor 0 1 1 Input Link port 0 1 0 Input Serial port SPI 0 0 0 Input No boot processor executes from external memory 5 4 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 21161 SHARC Processors ADSP 21161 Proc essor Boot Modes The ADSP 21161 processors support these boot modes EPROM host link and SPI The following section describe each of the modes e EPROM Boot Mode on page 5 5 e Host Boot Mode on page 5 9 e Link Port Boot Mode on page 5 12 e SPI Port Boot Mode on page 5 14 e No Boot Mode on page 5 16 For multiprocessor booting refer to ADSP 21161 Multi Applica tion Multi DXE Management on page 5 21 EPROM Boot Mode EPROM boot via the external port is selected when the E800T input is high and the L800T input is low These settings cause the BMS pin to become an output serving as chip select for the EPROM The DMAC1O control register is initialized for booting packing boot data into 48 bit instructions EPROM boot
58. control to reset and load the file into the memory of a slave processor Non bootable Files Versus Boot loadable Files A non bootable file executes from an external memory of the processor while a boot loadable file is transported into and executes from an internal memory of the processor The boot loadable file is then programmed into an external memory device burned into EPROM within your target sys tem The loader utility outputs loadable files in formats readable by most EPROM burners such as Intel hex 32 and Motorola S formats For advanced usage other file formats and boot modes are supported See File Formats on page A 1 A non bootable EPROM image file executes from an external memory of the processor bypassing the built in boot mechanisms Preparing a non bootable EPROM image is called splitting In most cases except for 1 10 VisualDSP 5 0 Loader and Utilities Manual Introduction Blackfin processors developers working with floating and fixed point processors use the splitter instead of the loader utility to produce a non bootable memory image file A booting sequence of the processor and application program design dic tate the way loader splitter utility is called to consume and transform executable files For Blackfin processors loader and splitter operations are handled by the loader utility program el floader exe The splitter is invoked by a different set of command line switches than the
59. device which connects to the target processor s system bus the processor can directly fetch and execute these instructions See also Splitter Utility Operations on page 1 12 Splitter and loader jobs can be managed either by separate utility pro grams or by the same program see Non bootable Files Versus Boot loadable Files on page 1 10 In the later case the generated output file may contain code instructions and boot streams 1 2 VisualDSP 5 0 Loader and Utilities Manual Introduction Loader File A loader file is generated by the loader utility The file typically has the ldr extension and is often called an LDR file Loader files can meet one of multiple formats Common formats are Intel hex 32 binary or ASCII representation Regardless of the format the loader file describes a boot image which can be seen as the binary version of the loader file See also Non bootable Files Versus Boot loadable Files on page 1 10 Loader Command Line If invoked from a command line prompt the loader and splitter utilities accept numerous control switches to customize the loader file generation Loader Property Page The loader property page is part of the Project Options dialog box of the VisualDSP graphical user interface The property page is a graphical tool that assists in composing the loader utility s command line Boot Mode Most processors support multiple boot modes A boot mode is determined by s
60. files h are ASCII text files that contain macros or other prepro cessor commands which the preprocessor substitutes into source files For information on macros and other preprocessor commands see the VisualDSP 5 0 Assembler and Preprocessor Manual VisualDSP 5 0 Loader and Utilities Manual A 3 Build Files Linker Desc ription Files Linker description files 1df are ASCII text files that contain commands for the linker in the linker scripting language For information on the scripting language see the VisualDSP 5 0 Linker and Utilities Manual Linker Command Line Files Linker command line files txt are ASCII text files that contain command line inputs for the linker For more information on the linker command line see the VisualDSP 5 0 Linker and Utilities Manual Build Files Build files are produced by VisualDSP development tools while build ing a project This section describes the following build file formats e Assembler Object Files on page A 5 e Library Files on page A 5 e Linker Output Files on page A 5 e Memory Map Files on page A 6 e Loader Output Files in Intel Hex 32 Format on page A 6 e Loader Output Files in Include Format on page A 8 e Loader Output Files in Binary Format on page A 9 e Output Files in Motorola S Record Format on page A 10 e Splitter Output Files in Intel Hex 32 Format on page A 12 A 4 VisualDSP 5 0 Loader and
61. files into boot loadable or non bootable files VisualDSP 5 0 Loader and Utilities Manual A 5 Build Files Executable files are converted into a boot loadable file 1dr for the ADI processors using a splitter utility Once an application program is fully debugged it is ready to be converted into a boot loadable file A boot loadable file is transported into and run from a processor s internal memory This file is then programmed burned into an external memory device within your target system A splitter utility generates non bootable PROM image files by processing executable files and producing an output PROM file A non bootable PROM image file executes from processor external memory Memory Map Files The linker can output memory map files xm1 which are ASCII text files that contain memory and symbol information for the executable files The xml file contains a summary of memory defined with the MEMORY com mand in the 1df file and provides a list of the absolute addresses of all symbols Loader Output Files in Intel Hex 32 Format The loader utility can output Intel hex 32 format files 1dr The files support 8 bit wide PROMs and are used with an industry standard PROM programmer to program memory devices One file contains data for the whole series of memory chips to be programmed The following example shows how the Intel hex 32 format appears in the loader s output file Each line in the Intel hex 3
62. files on the command line Place ov1 and sm files in the same directory as the dxe file that refers to them so the loader utility can find them when processing the 1dr file The ovl and sm files can also be placed in the ov1 and sm file output directory spec ified in the 1df file Loader output file VisualDSP 5 0 Loader and Utilities Manual 5 27 ADSP 21161 Processor Loader Guide Loader Command Line Switches Table 5 10 is a summary of the ADSP 21161 loader switches Table 5 10 ADSP 21161 Loader Command Line Switches Switch Description bprom bhost blink bspi Specifies the boot mode The b switch directs the loader utility to prepare a boot loadable file for the specified boot mode The valid modes boot types are PROM host link and SPI If the switch does not appear on the command line the default is bprom To use a custom boot kernel the boot mode selected with the b switch must correspond with the boot kernel selected with the 1 kernelfile switch Otherwise the loader utility automatically selects a default boot kernel based on the selected boot type see ADSP 21161 Processor Boot Kernels on page 5 16 efilename Except shared memory The e switch omits the specified shared memory sm file from the output loader file Use this option to omit the shared parts of the executable file intended to boot a multiprocessor system To omit multiple sm files
63. from flash variable baud rate and other sources 3 6 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Proc essors The following loader topics also are discussed in this chapter e ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 Processor Boot Streams on page 3 9 e ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 Processor Memory Ranges on page 3 19 Refer to the processor s data sheet and hardware reference manual for more information on system configuration peripherals regis ters and operating modes e Blackfin processor data sheets can be found at http www analog com en embedded processing dsp black fin processors data sheets resources index html e Blackfin processor manuals can be found at http www analog com en embedded processing dsp black fin processors manuals resources index html ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 Processor On Chip Boot ROM The on chip boot ROM for the ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 processors does the following 1 Sets up supervisor mode by exiting the RESET interrupt service routine and jumping into the lowest priority interrupt 1VG15 Note that the on chip boot ROM of the ADSP BF534 BF536 and ADSP BF537 processors executes at the Reset priority level does not degrade to the lowest priority interrupt 2 Checks whether the RESET was a software reset and
64. from the command line the loader utility generates the file for the boot kernel in the same boot mode as used to output the user application program kf hex The kf hex asci binary include switch specifies the out kf ascii put file format hex ASCII binary or include for the boot kernel kf binary if you output two files from the loader utility one for the boot ker kf include nel and one for user application code The kf switch must be used in conjunction with the 02 switch If the kf switch is absent from the command line the loader utility generates the file for the boot kernel in the same format as for the user application program kenc dll_filename The kenc d _filename switch specifies the user encryption dynamic library file for the encryption of the data stream from the kernel file If the filename parameter does not appear on the com mand line the encryption algorithm from the default ADI s file is used kp The kp switch specifies a hex flash PROM output start address for the kernel code A valid value is between 0x0 and OxFFFFFFFF The specified value is ignored when no kernel or and initialization code is included in the loader file VisualDSP 5 0 Loader and Utilities Manual 3 63 ADSP BF53x BF561 Processor Loader Guide Table 3 10 Blackfin Loader Command Line Switch Summary Contd Switch Description kWidth The kWidth switch specifies the
65. if so whether to skip the entire sequence and jump to the start of L1 memory OxFFAO 0000 for the ADSP BF533 BF534 BF536 BF537 BF538 and ADSP BF539 processors 0xFFAO 8000 for the VisualDSP 5 0 Loader and Utilities Manual 3 7 ADSP BF53x BF561 Proc essor Booting ADSP BF531 BF532 processors for execution The on chip boot ROM does this by checking the NoBOOT bit bit 4 of the system reset configuration register SYSCR If bit 4 is not set the on chip boot ROM performs the full boot sequence If bit 4 is set the on chip boot ROM bypasses the full boot sequence and jumps to the start of L1 memory 3 The NoB00T bit if bit 4 of the SYSCR register is not set performs the full boot sequence Figure 3 1 ADSP BF531 32 33 34 36 37 39 39 Processor PROM Flash or SPI Device 10 Byte Header for Block 1 Block 1 10 Byte Header for Block 2 Code Blocks e ia 10 Byte Header for Block n Figure 3 1 ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 B F539 Processors Booting Sequence The booting sequence for the ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 pro cessors is different from that for the ADSP BF535 processors The on chip boot ROM for the former processors behaves similarly to the sec ond stage loader of the ADSP BF535 processors see on page 3 23 The boot ROM has the capability to parse address and count information for 3 8 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADS
66. influenced by loader usage For more information on boot kernel operations refer to the comments in the corresponding boot kernel source files and application notes EE 174 ADSP TS101S TigerSHARC Processor Boot Loader Kernels Operation and EE 200 ADSP TS20x TigerSHARC Processor Boot Loader Kernels Opera tion The notes can be found at http www analog com processors processors tigersharc techni calLibrary index html TigerSHARC Loader Guide Loader operations depend on the loader options which control how the loader utility processes executable files You select features such as boot modes boot kernels and output file formats via the loader options These options are specified on the loader utility s command line or via the Load page of the Project Options dialog box in the VisualDSP environment When you open the Load page the default loader settings for the selected processor are already set Option settings on the Load page correspond to switches displayed on the command line These sections describe how to produce a bootable file 1dr e Using TigerSsHARC Loader Command Line on page 7 6 e Using VisualDSP Interface Load Page on page 7 12 VisualDSP 5 0 Loader and Utilities Manual 7 5 TigerSHARC Loader Guide Using TigerSHARC Loader Command Line The TigerSHARC loader utility uses the following command line syntax For a single input file elfloader inputfile proc processor switch For
67. is used to refer to all boot relevant ROM code Boot code typi cally consists of the pre boot routine and the boot kernel Boot Strapping If the boot process consists of multiple steps such as pre loading the boot kernel or managing second stage loaders this is called boot strapping or boot ROM Initialization Code Initialization code or initcode is part of a boot stream for Blackfin proces sors and can be seen as a special boot block While normally all boot blocks of an application are booted in first and control is passed to the application afterward the initialization code executes at boot time It is common that an initialization code is booted and executed before any other boot block This initialization code can customize the target system for optimized boot processing VisualDSP 5 0 Loader and Utilities Manual 1 5 Definition of Terms Global Header Some boot kernels expect a boot stream to be headed by a special informa tion tag The tag is referred to as a global header Callback Routine Some processors can optionally call a user defined routine after a boot block has been loaded and processed This is referred to as a callback rou tine It provides hooks to implement checksum and decompression strategies Slave Boot The term slave boot spawns all boot modes where the target processor functions as a slave This is typically the case when a host device loads data into the target processor s memories The
68. mode uses channel 10 of the IO processor s DMA controller to transfer the instructions to internal mem ory For EPROM booting the processor reads data from an 8 bit external EPROM After the boot process loads 256 words into memory locations 0x40000 through 0x400FF the processor begins to execute instructions Because most processor programs require more than 256 words of instructions and initialization data the 256 words typically serve as a loading routine for the application VisualDSP includes loading routines boot kernels that can load entire programs see ADSP 21161 Processor Boot Kernels on page 5 16 for more information VisualDSP 5 0 Loader and Utilities Manual 5 5 ADSP 21161 Proc essor Booting Refer to the ADSP 21161 SHARC DSP Hardware Reference for detailed information on DMA and system configurations Be aware that DMA channel differences between the ADSP 21161 and previous SHARC processors ADSP 2106x account for boot differences Even with these differences the ADSP 21161 proces sor supports the same boot capability and configuration as the ADSP 2106x processors The DMACx register default values differ because the ADSP 21161 processor has additional parameters and different DMA channel assignments EPROM boot mode uses EPBO DMA channel 10 Similar to the ADSP 2106x processors the ADSP 21161 processor boots from DATA23 16 The processor determines the booting mode at reset from the E8007 LBOOT
69. multiple input files elfloader 7dlexe inputfile dxe id2exe inputfile2 dxe proc pro cessor switch where e inputfile Name of the executable file dxe to be processed into a single boot loadable An input file name can include the drive and directory For multiprocessor or multi input systems specify multiple input dxe files Use the id exe switch where is the ID number from 0 to 7 of the processor Enclose long file names within straight quotes long file name e proc processor Part number of the processor for example ADSP 1S101 for which the loadable file is built e switch One or more optional switches to process Switches select operations and modes for the loader utility Command line switches may be placed on the command line in any order For a multi input system the loader utility processes the input executable files in the ascending order from the id exe switch presented on the command line 7 6 VisualDSP 5 0 Loader and Utilities Manual Loader for TigerSHARC Processors elfloader p0 dxe proc ADSP TS101 bprom fhex 1 Ts101_prom dxe In the above example the command line runs the loader utility with p0 dxe Identifies the executable file to process into a boot load able file Note the absence of the o switch causes the output file name to default to p0 1dr proc ADSP TS101 Specifies ADSP TS101 as the processor type bprom Specifies EPROM booting as
70. name as an optional parameter Table 2 4 lists the expected file types names and extensions Table 2 4 File Extensions Extension File Description dxe Loader input files boot kernel files and initialization files ldr Loader output file kn Loader output files containing kernel code only when two output files are selected In some cases the loader utility expects the overlay input files with the ov1 file extension shared memory input files with the sm extension or both but does not expect those files to appear on a command line or on the Load property page The loader utility finds these files in the directory of the associated dxe files in the current working directory or in the directory specified in the 1df file VisualDSP 5 0 Loader and Utilities Manual 2 7 ADSP BF51x BF52x BF54x Processor Loader Guide ADSP BF51x BF52x BF54x Blackfin Loader Command Line Switc hes A summary of the ADSP BF51x BF52x BF54x Blackfin loader com mand line switches appears in Table 2 5 For a quick on line help on the switches available for a specific processor for example an ADSP BF548 processor use the following command line elfloader proc ADSP BF548 help Table 2 5 ADSP BF51x BF52x BF54x Loader Command Line Switch Summary Switch Description b flash The b prom flash spimaster spislave UART TWImas b prom ter TWIslave FIFO OTP NAND switch directs the loader utility b spim
71. of the address field of the 1st data block in 1st dxe g 76 183 LSB of the byte count of the 1st data block in 1st dxe p E 84 191 8 15 of the byte count of the 1st data block in 1st dxe A 92 199 16 23 of the byte count of the 1st data block in 1st dxe 5 200 207 MSB of the byte count of the 1st data block in 1st dxe 208 215 LSB of the flag word of the 1st block in 1st dxe 216 223 MSB of the flag word of the 1st block in 1st dxe 224 231 Byte 3 of the Ist block of Ist dxe 3 232 239 Byte 2 of the 1st block of 1st dxe E k 240 247 Byte 1 of the 1st block of 1st dxe E 248 255 Byte 0 of the 1st block of 1st dxe P A 256 263 Byte 7 of the 1st block of 1st dxe i And so on 4 VisualDSP 5 0 Loader and Utilities Manual 3 41 ADSP BF53x BF561 Proc essor Booting LSB of the address field of the nth data block in 1st dxe 8 15 of the address field of the nth data block in Ist dxe 16 23 of the address field of the nth data block in Ist dxe MSB of the address field of the nth data block in Ist dxe LSB of the byte count of the nth data block in Ist dxe 8 15 of the byte count of the nth data block in Ist dxe 10 Byte Block Header dxel Block Data Cont d 16 23 of the byte count of the nth data block in Ist dxe MSB of the byte count of the nth data block in Ist dxe LSB of the flag word of the nth block in Ist dxe MSB of the flag word of the nth block in 1st dxe And so on g
72. operation may result if Caution Device damage may result if A Caution identifies conditions or inappropriate usage of the product that could lead to undesirable results or product damage In the online version of this book the word Caution appears instead of this symbol Warning Injury to device users may result if A Warning identifies conditions or inappropriate usage of the product that could lead to conditions that are potentially hazardous for the devices users In the online version of this book the word Warning appears instead of this symbol VisualDSP 5 0 Loader and Utilities Manual xix Notation Conventions XX VisualDSP 5 0 Loader and Utilities Manual 1 INTRODUCTION The majority of this manual describes the loader utility or loader pro gram as well as the process of loading and splitting the final phase of the application development flow Most of this chapter applies to all 8 16 and 32 bit processors Informa tion specific to a particular processor or to a particular processor family is provided in the following chapter Chapter 2 Loader Splitter for ADSP BF51x BF52x BF54x Blackfin Processors Chapter 3 Loader Splitter for ADSP BF53x BF561 Blackfin Processors Chapter 4 Loader for ADSP 2106x 21160 SHARC Processors Chapter 5 Loader for ADSP 21161 SHARC Processors Chapter 6 Loader for ADSP 2126x 2136x 2137x 2146x SHARC Processors
73. processor This is a mandatory switch 5 30 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 21161 SHARC Processors Table 5 10 ADSP 21161 Loader Command Line Switches Cont d Switch Description si revision none any The si revision none any switch provides a silicon revi sion of the specified processor The switch parameter represents a silicon revision of the processor specified by the proc processor switch The parameter takes one of three forms e The none value indicates that the VisualDSP ignores silicon errata e The value indicates one or more decimal digits fol lowed by a point followed by one or two decimal digits Examples of revisions are 0 0 1 12 23 1 Revision 0 1 is distinct from and lower than revision 0 10 The digits to the left of the point specify the chip tape out number the digits to the right of the point identify the metal mask revision number The number to the right of the point cannot exceed decimal 255 e The any value indicates that VisualDSP produces an output file that can be run at any silicon revision The switch generates either a warning about any potential anoma lous conditions or an error if any anomalous conditions occur In the absence of the silicon revision switch the loader utility selects the greatest silicon revision it is aware of if any S In the absence of the switch parameter a valid revi sion value si revis
74. processor via SPI master mode BOOT_CFG1 0 01 SPI slave boot mode is discussed on page 6 8 and SPI master boot modes are discussed on page 6 10 VisualDSP 5 0 Loader and Utilities Manual 6 7 ADSP 2126x 2136x 2137x 2146x Proc essor Booting Both SPI boot modes support booting from 8 16 or 32 bit SPI devices In all SPI boot modes the data word size in the shift register is hardwired to 32 bits Therefore for 8 or 16 bit devices data words are packed into the shift register RXSPI to generate 32 bit words least significant bit LSB first which are then shifted into internal memory For 16 bit SPI devices two words shift into the 32 bit receive shift regis ter RXSR before a DMA transfer to internal memory occurs For 8 bit SPI devices four words shift into the 32 bit receive shift register before a DMA transfer to internal memory occurs When booting the ADSP 2126x 2136x 2137x 2146x processor expects to receive words into the RXSPI register seamlessly This means that bits are received continuously without breaks in the CS link For different SPI host sizes the processor expects to receive instructions and data packed in a least significant word LSW format See the manual for the target SHARC processor peripherals for informa tion on how data is packed into internal memory during SPI booting for SPI devices with widths of 32 16 or 8 bits SPI Slave Boot Mode In SPI slave boot mode the host processor in
75. repeat the switch and its parameter multiple times on the command line For example to omit two files use efileA SM efileB SM In most cases it is not necessary to use the e switch the loader utility processes the sm files efficiently includes a single copy of the code and data from each sm file in a loader file fhex fASCII fbinary finclude fS1 fS2 S3 Specifies the format of the boot loadable file Intel hex 32 ASCII include binary S1 S2 and S3 Motorola S records If the f switch does not appear on the command line the default boot file format is hex for PROM and ASCII for host link or SPL Available formats depend on the boot mode selection b switch e Fora PROM boot select a hex 32 1 2 S3 ASCH or include format e For host or link boot select an ASCII binary or include format e For SPI boot select an ASCH or binary format 5 28 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 21161 SHARC Processors Table 5 10 ADSP 21161 Loader Command Line Switches Cont d Switch Description h Command line help Outputs the list of command line switches or to standard output and exits help Combining the h switch with proc ADSP 21161 for example elfloader proc ADSP 21161 h yields the loader syntax and switches for the ADSP 21161 processors By default the h switch alone provides help for the loader driver hostwidth Sets up
76. reside in the Interrupt Vector Table Ky E Syohegel a yer ane aca ey Spehees Spe eves E E 6 15 cheney a Sveteven Sere Gra Sune layer E E x final_init Reston Bae Setup for IVT instruction patch 18 0x80030 Point to SPI vector to patch from PX Gf R9 0xb16b0000 Load opcode for PM 0 I8 PX into R9 PX pm 0x80002 User instruction destined for 0x80030 is passed in the section header for FINAL_INIT That instr is initialized upon completion of this DMA see comments below using the PX register R11 BSET R11 BY 9 Set IMDW to 1 for inst write K DM SYSCTL R11 Set IMDW to 1 for inst write ph ce tae Setup loop for self modifying instruction 14 0x80004 Point to 0x080004 for self modifying code inserted by the loader at 0x80004 in bootstream af R9 pass R9 R11 R12 Clear AZ copy power on value 6 30 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2126x 2136x 2137x 2146x SHARC Processors of SYSCTL to R11 X DO 0x80004 UNTIL EQ Set bottom of loop address loopstack to 0x80004 and top of loop PC Stack to the address of the next instruction K PCSTK 0x80004 Change top of loop value from the address of this instruction to 0x80004 K FEE ea ASE EE Setup final DMA parameters Ki R1 0x80000 DM IISX R1 Setup DMA to load over ldr y R2 0x180 DM CSX R2 Load internal count E DM IMSX M6 Set to i
77. s An A Byte 1 of the nth block of Ist dxe 42 og 3 Byte 0 of the nth block of Ist dxe m S m Y a gz LSB of the address field of 2nd dxe count block no care 8 15 of the address field of 2nd dxe count block no care N v PA ages pe Ls Sv AT o And so on 3 42 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Proc essors ADSP BF561 Processor Initialization Blocks The initialization block or a second stage loader utility must be used to initialize the SDRAM memory of the ADSP BF561 processor before any instructions or data are loaded into it The initialization blocks are identified by a bit in the flag word of the 10 byte block header When the boot ROM encounters the initialization blocks in the boot stream it loads the blocks and executes them immedi ately The initialization blocks must save and restore registers and return to the boot ROM so the boot ROM can load the rest of the blocks For more details see ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 Block Headers and Flags on page 3 10 Both the initialization block and second stage loader utility can be used to force the boot ROM to load a specific dxe file from the external memory device if the boot ROM stores multiple executable files The initialization block can manipulate the RO or R3 register which the boot ROM uses as the external memory pointers for flash PRO
78. some cases a single application can consist of multiple dxe files Initialization code is a subroutine called at boot time Unlike the ADSP BF53x BF56x processors the ADSP BF51x BF52x BF54x proces sors support initcode written in both assembly and C VisualDSP supports two methods of integrating multiple initcode subroutines The init filename dxe command line switch expects a dxe file The initcode is managed by a separate VisualDSP project If the initcode is written in C language ensure that the dxe file does not include the CRT code because the boot kernel expects a subrou tine The init filename dxe switch can be used multiple times to specify the same file or different files a number of times The loader utility places the code from the initialization files in the order the files appear on the command line All initcodes are inserted after the first regular dxe file The loader utility equips every initcode with a dedicated first boot block which has the BFLAG_FIRST flag set Initcodes however do not feature a final block they are terminated by a boot block VisualDSP 5 0 Loader and Utilities Manual 2 17 ADSP BF51x BF52x BF54x Processor Loader Guide tagged by the BFLAG_INIT flag Therefore in absence of the BFLAG_FINAL flag the boot kernel continues processing of the sub sequent dxe data after finishing execution of the initcode e The initcall sym sym_symbol command line switch relies on init
79. stage loader Unless you develop a second stage loader and use it most of the options on the Kernel page are grayed out Figure 2 2 shows a sample Kernel page with options set for an ADSP BF548 Blackfin processor 2 20 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF51x BF52x BF54x Blac kfin Proc essors Project Options for An ADSP BF548 Based Project fey General Fig Compile C Use boot kernel fey Assemble E unk Boot Mods Boot Format Output Width Load fey Options ee Kernel fs Splitter E Pre build fy Post build 2 Add Startup Code LDF Additional options Figure 2 2 Project Load Kernel Page for ADSP BF548 Processors To create a loader file which includes a second stage loader 1 Select Options under Load to set up base load options see Using VisualDSP Loader on page 2 18 2 Select Kernel under Load to set up the second stage loader options Figure 2 2 3 On the Kernel page select Use boot kernel 4 In Kernel file enter the name of the second stage loader file dxe VisualDSP 5 0 Loader and Utilities Manual 2 21 ADSP BF51x BF52x BF54x Processor Loader Guide 5 To produce two output files select the Output kernel in separate file check box This option allows to boot the second stage loader with an initialization code if any from one source and the appli cation code from another source You can specify the kernel out
80. target 0o imagefile The o output file switch directs the splitter utility to use imagefi le as the name of the splitter output file s If not specified the default name for the splitter output file is inputfile ext where ext depends on the output format norom The norom no ROM in PROM switch directs the splitter utility to ignore ROM memory sections in the input fi e when extracting information for the output image The dm and pm switches select data memory or program memory The operation of the s switch is not influenced by the norom switch pm The pm include program memory switch directs the splitter utility to extract memory sections declared program memory ROM from the input dxe file The pm switch influences the operation of the ram and norom switches adding program memory as the target VisualDSP 5 0 Loader and Utilities Manual 8 5 Splitter Command Line Table 8 2 Splitter Command Line Switches Contd Item Description r F F n The r PROM widths switch specifies the number of PROM files and their width in bits The splitter utility can create PROM files for 8 16 and 32 bit wide PROMs The default width is 8 bits Each parameter specifies the width of one PROM file Place parameters in order from most significant to least significant The sum of the parameters must equal the bit width of the destina tion memory 40 bits for DM 48 bits for
81. target processor can wait pas sively in idle mode or support the host controlled data transfers actively Note that the term host boot usually refers only to boot modes that are based on so called host port interfaces Master Boot The term master boot spawns all boot modes where the target processor functions as master This is typically the case when the target processor reads the boot data from parallel or serial memories Boot Manager A boot manager is a firmware that decides what application has to be booted An application is usually represented by a VisualDSP project and stored in a dxe file The boot manger itself can be managed within an application dxe file or have its own separate dxe file Often the boot manager is executed by so called initialization codes In slave boot scenarios boot management is up to the host device and does not require special VisualDSP support 1 6 VisualDSP 5 0 Loader and Utilities Manual Introduction Multi dxe Boot A loader file may can contain data of multiple application dxe files if the loader utility was invoked by specifying multiple dxe files Either a boot manager decides what application has to be booted exclusively or alternatively one application can terminate and initiate the next applica tion to be booted In some cases a single application can also consist of multiple dxe files Next dxe File Pointer If a loader file contains multiple applications so
82. the ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 and ADSP BF561 processors For further information about the ADSP BF561 processors refer to ADSP BF561 Dual Core Application Management on page 3 44 The ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 and ADSP BF561 loader file structure and the silicon revision of 0 1 and higher allow generation and booting of multiple dxe files into a single processor from external memory As illustrated in Figure 3 20 each exe cutable file is preceded by a 4 byte count header which is the number of bytes within the executable including headers This information can be used to boot a specific dxe file into the processor The 4 byte dxe count block is encapsulated within a 10 byte header to be compatible with the silicon revision 0 0 For more information see ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 Block Headers and Flags on page 3 10 Booting multiple executables can be accomplished by one of the following methods e Use the second stage loader switch l userkernel dxe The option allows you to use your own second stage loader After the second stage loader is booted into internal memory via 3 46 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Proc essors BLOCK 1 10 BYTE HEADER 10 BYTE HEADER FOR COUNT BLOCK 1 4 BYTE COUNT FOR DXE1 BLOCK 2 10 BYTE HEADER BLOCK 2 DXE 1 APPLICATION BLOCK 3
83. the reset vector address refer to Table 4 2 on page 4 4 must not contain a valid instruction because it is not executed during the booting sequence Place a NOP or IDLE instruction at this location If the boot kernel initializes external memory create a custom boot kernel that sets appropriate values in the SYSCON and WAIT register Be aware that the value in the DMA channel register is non zero and IMASK is set to allow DMA channel register interrupts Because the DMA interrupt remains enabled in IMASK this interrupt must be cleared before using the DMA channel again Otherwise unintended interrupts may occur 4 14 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2106x 21160 SHARC Processors A master SHARC processor may boot a slave SHARC processor by writing to its DMACx control register and setting the packing mode PMODE to 00 This allows instructions to be downloaded directly without packing The wait state setting of 6 on the slave processor does not affect the speed of the download since wait states affect bus master operation only Link Port Boot Mode Link port boot is supported on all SHARC processors except the ADSP 21061 and ADSP 21065L processors When link boot the ADSP 2106x 21160 SHARC processors the proces sor receives data from 4 bit link buffer 4 and packs boot data into 48 bit instructions using the appropriate DMA channels DMA channel 6 for the ADSP 2106x processors DMA channel 8 for the ADS
84. the word width for the 1dr file By default the word width for PROM and host is 8 for link is 16 and for SPI is 32 The valid word widths for the various boot modes are e PROM 8 for hex or ASCII format 8 or 16 for include format e host 8 or 16 for ASCII or binary format 16 for include format e link 16 for ASCH binary or include format e SPI 8 16 or 32 for Intel hex 32 or ASCII format jidffexe filename idffref N Specifies the processor ID The idifexe switch directs the loader utility to use the processor ID for the corresponding executable file fi 7 ename when producing a boot loadable file for EPROM boot of a multiprocessor system This switch is used only to produce a boot loadable file that boots multiple proces sors from a single EPROM Valid values for are 1 2 3 4 5 and 6 Do not use this switch for single processor systems For sin gle processor systems use fi ename as a parameter without a switch For more information refer to Processor ID Numbers on page 5 23 Points the processor ID 4 loader jump table entry to the ID M image If the executable file for the processor is identical to the executable of the N processor the switch can be used to set the PROM start address of the processor with ID of to be the same as for the processor with ID of N This effectively reduces the size of the loader file by providing a single copy of an executable to two or more proc
85. this address When using any of the processor s power up boot modes ensure that this address does not contain a critical instruction Because this address is not executed during the booting sequence place a NOP or IDLE in this location The loader utility generates a warning if the vector address 0x40004 does not contain NOP or IDLE When using VisualDSP to create the loader file specify the name of the customized boot kernel executable in the Kernel file box on the Load page of the Project Options dialog box 5 20 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 21161 SHARC Processors ADSP 21161 Processor Interrupt Vector Table If the ADSP 21161 processor is booted from an external source EPROM host link port or SPI the interrupt vector table is located in internal memory If the processor is not booted and executes from external mem ory no boot mode the vector table must be located in external memory The IIVT bit in the SYSCON control register can be used to override the booting mode in determining where the interrupt vector table is located If the processor is not booted no boot mode setting IIVT to 1 selects an internal vector table and setting IIVT to zero selects an external vector table If the processor is booted from an external source any boot mode other than no boot IIVT has no effect The default initialization value of IIVT is zero ADSP 21161 Mult Application Multi DXE Management
86. transforming a dxe file to an 1dr file It emits raw data only Whether data and or instruction segments are processed by the loader or by the splitter utility depends upon the LDF s TYPE command Sections declared with TYPE RAM are consumed by the loader utility and sections declared by TYPE ROM are consumed by the splitter Figure 3 29 shows a sample Load Splitter page with ROM splitter options With the Enable ROM splitter box unchecked only TYPE RAM sections are processed and all TYPE ROM segments are ignored by the loader utility If the box is checked TYPE RAM sections are ignored and TYPE ROM sections are processed by the splitter utility The Mask Address field masks all EPROM address bits above or equal to the number specified For example Mask Address 29 default masks all bits above and including A29 ANDed by Ox1FFF FFFF Thus 0x2000 0000 becomes 0x0000 0000 The valid numbers are integers 0 through 32 but based on your specific input file the value can be within a subset of 0 32 3 78 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Proc essors Project Options for An ADSP BF533 Based Project gt Project a Ft Projec Eh General fig Compile J Enable ROM splitter Eh General E Language Settings Format fy MISRA C re Preprocessor Rh Processor 1 fey Processor 2 Py Profile quided Optimization Ez warning EA Assemble Fag Link EA General E
87. utility takes files with extensions of dxe ovl and sm but expects only those with extension dxe in a command line on the Load page The loader utility finds files with extensions of ovl and sm as it processes the associated dxe file The loader utility searches for ov1 and sm files in the directory holding the dxe files in the directory specified in the 1df file or in the current directory Table 7 2 TigerSHARC File Extensions Extension File Description dxe Loader input files and boot kernel files ldr Loader output file ov Overlay files The loader utility does not expect them on a command line sm Shared memory files The loader utility does not expect them on a command line 7 8 VisualDSP 5 0 Loader and Utilities Manual Loader for TigerSHARC Processors TigerSHARC Command Line Switches A summary of the loader command line switches appears in Table 7 3 Table 7 3 TigerSHARC Loader Command Line Switches Switch Description bprom Prepares a boot loadable file for the specified boot mode Valid boot bhost types include PROM host and link port If the b switch does not blink appear on the command line the default setting is bprom To use a custom kernel the boot type selected with the b switch must corre spond to the boot kernel selected with the 1 switch fhex Prepares a boot loadable file in the specified format Available for fASCII mat selections ar
88. 0 No Zero Fill Figure 3 19 Block Flag Word Bit Assignments ADSP BF535 Processor Memory Ranges Second stage loaders are available for the ADSP BF535 processors in VisualDSP 3 0 and higher They allow booting to e L2 memory 0xF000 0000 e Ll memory v Data bank A SRAM 0xFF80 0000 v Data bank B SRAM 0xFF90 0000 v Instruction SRAM 0xFFAO 0000 v Scratchpad SRAM 0xFFBO 0000 e SDRAM v Bank 0 0x0000 0000 v Bank 1 0x0800 0000 v Bank 2 0x1000 0000 v Bank 3 0x1800 0000 SDRAM must be initialized by user code before any instructions or data are loaded into it VisualDSP 5 0 Loader and Utilities Manual 3 33 ADSP BF53x BF561 Proc essor Booting Second Stage Loader Restrictions Using the second stage loader imposes the following restrictions The bottom of L2 memory must be reserved during booting These locations can be reallocated during runtime The following loca tions pertain to the current second stage loaders v For eight and 16 bit flash PROM booting reserve OxF003 FE00 0xF003 FFFF last 512 bytes v For eight and 16 bit addressable SPI booting reserve 0xF003 FDOO OxF003 FFFF last 768 bytes If segments reside in SDRAM memory configure the SDRAM reg isters accordingly in the second stage loader before booting v Modify a section of code called SDRAM setup in the second stage loader and rebuild the second stage loader Any segments residing in L1 instruction memory OxFFAO 0
89. 000 OxFFAO 3FFF must be eight byte aligned v Declare segments within the 1df file that reside in L1 instruction memory at starting locations that are eight byte aligned for example 0xFFAO 0000 OxFFAO 0008 OxFFAO 0010 and so on v Use the ALIGN 8 directives in the application code The two reasons for these restrictions are e Core writes into L1 instruction memory are not allowed e DMA from an eight bit external memory is not possible since the minimum width of the external bus interface unit EBIU is 16 bits 3 34 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Proc essors Load bytes into L1 instruction memory by using the instruction test com mand and data registers as described in the Memory chapter of the appropriate hardware reference manual These registers transfer eight byte sections of data from external memory to internal L1 instruction memory ADSP BF561 Processor Booting The booting sequence for the ADSP BF561 dual core processors is similar to the ADSP BF531 BF532 BF533 processor boot sequence described on page 3 7 Differences occur because the ADSP BF561 processor has two cores core A and core B After reset core B remains idle but core A executes the on chip boot ROM located at address 0xEF00 0000 The ADSP BF561 Processor On Chip Boot ROM details can be found on page 3 23 Table 3 6 summarizes the boot modes and execution start addresses for
90. 0005 with the only trace as if nothing happened ADSP 2136x 2137x 2146x Multi Application Multi DXE Management Up to eight ADSP 21367 21368 21389 2137x and ADSP 2146x proces sors can be clustered together and supported by the VisualDSP loader utility In PROM boot mode all of the processors can boot from the same PROM The loader utility assigns an input executable dxe file to a pro cessor ID or to a number of processor IDs provided a corresponding loader option is selected on the property page or on the command line The loader utility inserts the ID into the output boot stream using the multiprocessor tag MULTI_PROC see Table 6 12 The loader utility also inserts the offset the 32 bit word count of the boot stream built from the input executable dxe file into the boot stream The MULTI_PROC tag enables the boot kernel to identify each section of the boot stream with the executable dxe file from which that section was built Figure 6 4 shows the multiprocessor boot stream structure The processor ID of the corresponding processor is indicated in a 32 bit word which has the Nth bit set for the dxe file corresponding to ID N Table 6 16 shows all possible ID fields VisualDSP 5 0 Loader and Utilities Manual 6 33 ADSP 2126x 2136x 2137x 2146x Proc essor Booting BOOT KERNEL 1ST dxe BLOCK HEADER 1ST dxe DATA BLOCKS 2ND dxe BLOCK HEADER 2ND dxe DATA BLOCKS Figure 6 3 Multiprocessor
91. 1 BF532 BF533 Block Header Structure Cont d Bit Field Description Count 4 byte number of bytes to boot Flag 2 byte flag containing information about the block the following text describes the flag structure Refer to Figure 3 3 and Table 3 4 for the flag s bit descriptions Table 3 4 Flag Structure Bit Field Description Zero fill block Indicates that the block is for a buffer filled with zeros The body of a zero block is not included within the loader file When the loader utility parses through the dxe file and encounters a large buffer with zeros it creates a zero fill block to reduce the 1dr file size and boot time If this bit is set there is no block body in the block Processor type Indicates the processor either the ADSP BF531 BF532 BF538 or the ADSP BF533 BF534 BF536 BF537 BF539 Once booting is complete the on chip boot ROM jumps to 0xFFAO 0000 on the ADSP BF533 BF536 BF537 BF538 BF539 processor and to OxFFAO 8000 on the ADSP BF531 BF532 processors Initialization Indicates that the block is to be executed before booting The initialization block block indicator allows the on chip boot ROM to execute a number of instruc tions before booting the actual application code When the on chip boot ROM detects an init block it boots the block into internal memory and makes a CALL to it initialization code must have an RTS at the end This option allows the user to run initia
92. 10 BYTE HEADER 10 BYTE HEADER FOR COUNT BLOCK 3 4 BYTE COUNT FOR DXE 2 DXE 2 APPLICATION 10 BYTE HEADER FOR COUNT 4 BYTE COUNT FOR DXE 3 DXE 3 APPLICATION DXE 1 DXE 2 DXE 3 10 BYTE HEADER FOR COUNT 4 BYTE COUNT FOR DXE 4 e Figure 3 20 ADSP BF531 BF32 BF33 BF534 BF536 BF537 BF538 BF539 BF561 Processors Multi Application Booting Streams DXE 4 the on chip boot ROM the loader has full control over the boot process Now the second stage loader can use the dxe byte counts to boot in one or more dxe files from external memory e Use the initialization block switch init filename dxe where filename dxe is the name of the executable file containing the ini tialization code This option allows you to change the external memory pointer and boot a specific dxe file via the on chip boot ROM On the ADSP BF531 and ADSP BF561 processors the ini tialization code is an assembly written subroutine VisualDSP 5 0 Loader and Utilities Manual 3 47 ADSP BF53x BF561 Proc essor Booting A sample initialization code is included in Listing 3 5 The RO and R3 reg isters are used as external memory pointers by the on chip boot ROM The RO register is for flash PROM boot and R3 is for SPI memory boot Within the initialization block code change the value of RO or R3 to point to the external memory location at which the specific application code starts After the processor re
93. 11 SPIDS signal 6 8 SPI EEPROM boot mode Blackfin processors ADSP BF535 processors 3 21 3 24 3 28 3 29 ADSP BF561 processors 3 43 SPIEN bit 6 9 6 10 SPI_FLAGO_O signal 6 10 6 11 SPI flash boot mode ADSP 2126x 2136x 2137x 21469 processors 6 16 SPIFLG register 6 11 SPI host boot mode ADSP 2126x 36x 37x 46x processors 6 17 INDEX SPI master boot modes ADSP 2126x 36x 37x 46x processors 6 7 6 10 6 14 ADSP 2126x 36x 37x processors 6 18 ADSP BF5 1x processors 2 3 ADSP BF52x 54x processors 2 4 ADSP BF531 2 3 8 9 processors 3 4 ADSP BF534 6 7 processors 2 4 3 4 See also SPI flash SPI ROM host processor master boot modes SPI memory slave devices 6 11 SPI PROM boot mode ADSP 2126x 36x 37x 46x processors 6 13 6 14 6 16 SPIRCV bit 6 9 6 11 SPIR x register 5 2 5 14 5 15 SPI slave boot mode ADSP 2126x 2136x 2137x 21469 processors 6 8 SPI slave boot mode ADSP 2126x 36x 37x 46x processors 6 7 6 14 SPI slave boot mode Blackfin processors ADSP BF5 1x processors 2 3 ADSP BF52x 54x processors 2 4 ADSP BF531 2 3 8 9 processors 3 4 ADSP BF534 6 7 processors 3 4 Split page 8 9 splitter introduction to 1 9 1 11 1 12 1 14 as ROM splitter on Blackfin processors 2 19 3 73 command line syntax 8 2 file extensions 8 4 graphical user interface 8 9 list of switches 8 5 output file formats A 10 A 12 A 14 SPORT hex data files A 15 VisualDSP 5 0 Loader and Utilities Manual I 1
94. 2 file contains an extended linear address record a data record or the end of file record 020000040000FA Extended linear address record 0402100000FEO3FOF9 Data record 00000001FF End of file record A 6 VisualDSP 5 0 Loader and Utilities Manual File Formats Extended linear address records are used because data records have a 4 character 16 bit address field but in many cases the required PROM size is greater than or equal to 0xFFFF bytes Extended linear address records specify bits 31 16 for the data records that follow Table A 2 shows an example of an extended linear address record Table A 2 Extended Linear Address Record Example Field Purpose 020000040000FA Example record Start character 02 Byte count always 02 0000 Address always 0000 04 Record type 0000 Offset address FA Checksum Table A 3 shows the organization of a sample data record Table A 3 Data Record Example Field Purpose 0402100000FEO3F0F9 Example record Start character 04 Byte count of this record 0210 Address 00 Record type 00 First data byte FO Last data byte F9 Checksum VisualDSP 5 0 Loader and Utilities Manual A 7 Build Files Table A 4 shows an end of file record Table A 4 End of File Record Example Field Purpose 00000001FF End of file record Start charact
95. 21160 The start addresses and reset vector addresses are summarized in Table 4 2 Table 4 2 ADSP 2106x 21160 Processor Start Addresses Processor Start Address Reset Vector Address ADSP 21060 0x20000 0x20004 ADSP 21061 0x20000 0x20004 ADSP 21062 0x20000 0x20004 ADSP 21065L 0x8000 0x8004 ADSP 21160 0x40000 0x40004 1 The reset vector address must not contain a valid instruction since it is not executed during the booting sequence Place a NOP or IDLE instruction at this location The boot type selection directs the system to prepare the appropriate boot kernel 4 4 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2106x 21160 SHARC Processors Boot Mode Selection The state of various pins selects the processor boot mode For the ADSP 21060 ADSP 21061 ADSP 21062 and ADSP 21160 processors refer to Table 4 3 and Table 4 4 For the ADSP 21065L processors refer to Table 4 5 and Table 4 6 Table 4 3 ADSP 21060 061 062 and ADSP 21160 Boot Mode Pins Pin Type Description EBOOT I EPROM boot When 800T is high the processor boot loads from an 8 bit EPROM through the processor s external port When EBOOT is low the LBOOT and BMS pins determine the booting mode LBOOT Link port boot When LBOOT is high and EBOOT is low the processor boots from another SHARC through the link port When LBOOT is low and EBOOT is low the processor
96. 21160 SHARC Processors tion code that actually belongs in that space at run time The final initialization code also takes care of interrupts and returns the processor registers such as SYSCON and DMAC or LCTL to their default values When the loader utility detects the final initialization tag it reads the next 48 bit word This word indicates the instruction to load into the 48 bit Px register after the boot kernel finishes initializing memory The boot kernel requires that the interrupt external port or link port address depending on the boot mode contains an RTI instruction This RTI is inserted automatically by the loader utility to guarantee that the kernel executes from the reset vector once the DMA that overwrites the kernel is complete A last remnant of the kernel code is left at the reset vector location to replace the RTI with the user s intended code Because of this last kernel remnant user application code should not use the first location of the reset vector This first location should be a NOP or IDLE instruction The kernel automatically completes and the program con troller begins sequencing the user application code at the second location in the processor reset vector space When the boot process is complete the processor automatically executes the user application code The only remaining evidence of the boot kernel is at the first location of the interrupt vector Almost no memory is sacri ficed to the boot co
97. 21161 Specifies ADSP 21161 as the target processor Multiprocessor Systems The following command line elfloader proc ADSP 21161 bprom idlexe Inputl dxe id2exe Input2 dxe runs the loader utility with e proc ADSP 21161 Specifies ADSP 21161 as the target processor e bprom Specifies EPROM booting as the boot type for the boot loadable file e jdlexe Input1 dxe lIdentifies Input1 dxe as the executable file to process into a boot loadable file for a processor with ID of 1 see Processor ID Numbers on page 5 23 e id2exe Input2 dxe lIdentifies Input2 dxe as the executable file to process into a boot loadable file for a processor with ID of 2 see Processor ID Numbers on page 5 23 5 26 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 21161 SHARC Processors File Searches File searches are important in loader processing The loader utility sup ports relative and absolute directory names default directories and user selected directories for file search paths File searches occur as described on page 1 17 File Extensions Some loader switches take a file name as an optional parameter Table 5 9 lists the expected file types names and extensions Table 5 9 File Extensions Extension File Description dxe Executable files and boot kernel files The loader utility recognizes overlay memory files ov1 and shared memory files sm but does not expect these
98. 21161 SHARC processors are detailed in the following sections e ADSP 21161 Processor Booting on page 5 2 Provides general information about various boot modes including information about boot kernels e ADSP 21161 Processor Loader Guide on page 5 24 Provides reference information about the loader utility s graphical user interface command line syntax and switches Refer to EE 177 SHARC SPI Booting EE 199 Link Port Booting on the ADSP 21161 SHARC DSP EE 209 Asynchronous Host Interface on the ADSP 21161 SHARC DSP on the Analog Devices Processor Web site for related information VisualDSP 5 0 Loader and Utilities Manual 5 1 ADSP 21161 Proc essor Booting ADSP 21161 Proc essor Booting The ADSP 21161 processors support five boot modes EPROM host link port SPI port and no boot see Table 5 1 and Table 5 2 on page 5 4 Boot loadable files for these modes pack boot data into words of appropriate widths and use an appropriate DMA channel of the proces sors DMA controller to boot load the words When booting from an EPROM through the external port the ADSP 21161 processor reads boot data from an 8 bit external EPROM When booting from a host processor through the external port the ADSP 21161 processor accepts boot data from 8 or 16 bit host microprocessor When booting through the link port the ADSP 21161 processor receives boot data through the link port as 4 bit wide data in link buffer 4 When boo
99. 2765 is the default The is directly related to the number of cycles the processor locks the bus for boot loading instructing the pro cessor to lock the bus for no more than two times the timeout number of cycles When working with a fast host that cannot tolerate being locked out of the bus use a relatively small timeout value use32bitTagsfor Directs the loader utility to treat the external memory sections as 32 bit ExternalMemory sections as specified in the 1df file and does not pack them into Blocks 48 bit sections before processing This option is useful if the external memory sections are packed by the linker and do not need the loader utility to pack them again VisualDSP 5 0 Loader and Utilities Manual 4 31 ADSP 2106x 21160 Processor Loader Guide Table 4 15 ADSP 2106x 21160 Loader Command Line Switches Switch Description v Outputs verbose loader utility messages and status information as the the utility processes files version Directs the loader utility to show its version information Type elfloader version to display the version of the loader drive Add the proc switch for example elfloader proc ADSP 21062 version to display version infor mation of both loader drive and SHARC loader utility Using VisualDSP Interface Load Page After selecting a Loader file as the target type on the Project page in Visu alDSP Project Options dialog box modify the defaul
100. 3 43 3 45 SDRDIV register 5 18 6 20 second stage loader ADSP BF535 processors 1 15 3 24 3 27 3 32 3 33 3 34 ADSP BF561 processors 3 43 3 44 creating from VisualDSP 2 21 3 77 setting options 2 19 3 73 3 75 source files ADSP BF535 processors 3 77 SENDZ bit 6 9 6 11 sequential EPROM boot 5 22 shared memory Blackfin processors 3 44 3 45 file format sm 2 7 3 44 3 59 7 8 A 5 A 15 in compressed ldr files 6 36 6 39 omitting from loader file 4 28 5 28 shift register See RX registers ShowEncryptionMessage loader switch for Blackfin 3 67 silicon revision setting 2 16 3 68 4 31 5 31 6 48 7 11 8 8 simulators for boot simulation 1 10 single processor systems 4 24 5 23 7 6 7 9 8 2 VisualDSP 5 0 Loader and Utilities Manual si revision none any loader switch for Blackfin 2 16 3 68 loader switch for SHARC 4 31 5 31 6 48 loader switch for TigerSHARC 7 11 splitter switch 8 8 slave processors 1 10 1 14 6 10 s_ Motorola S record files 8 4 A 10 sm shared memory files 2 7 3 59 4 28 5 28 7 8 A 5 A 15 software reset 1 13 3 7 3 23 3 37 source file formats assembly text asm A 2 C C text c cpp cxx A 2 SPIBAUD register 6 11 SPI boot modes SHARC processors ADSP 21161 processors 5 2 5 4 5 14 ADSP 2126x 36x 37x 46x processors 6 7 6 13 6 21 6 29 SPICLK register 6 8 6 10 6 13 6 17 SPICTL register 5 15 6 9 6 11 SPIDMAC register 6 9 6
101. 4 11 4 12 4 13 4 16 4 18 DATA15 0 pios 4 12 DMA ADSP 21161 processors DATA23 16 pins 4 7 5 6 channels See channels by name DMACx DATA31 16 pins 4 12 buffers 5 22 DATA39 32 pins 4 7 channel control registers 5 5 5 6 5 9 5 10 DATA47 16 pins 4 12 5 11 5 16 DATA63 32 pins 4 12 channel interrupts 5 9 5 12 DATA64 memory sections 8 4 8 5 channel parameter registers 5 7 5 9 5 11 DATA7 0 pins 4 7 4 12 5 12 5 13 5 15 5 16 data banks Blackfin processors ionirolles SS 37 3 ADSP BF531 2 3 4 6 7 8 9 processors 3 19 transfers 3 300 S15 S16 3 21 ADSP BF535 processors 3 33 DMA ADSP 2126x 36x 37x 46x processors ADSP BF561 processors 3 45 DataFlash devices 3 4 data packing SHARC processors code example 6 30 parallel port channels 6 6 6 25 parameter registers 6 6 6 8 6 11 6 31 ADSP 2106x 160 processors 4 9 4 10 SPT channels 68 Gell 4 11 4 12 4 15 transfers 6 6 6 8 6 10 6 19 ADSP 21161 processors 5 5 5 9 DMACO channel ADSP 2106x 160 ADSP 2126x 36x 37x 46x processors 6 7 processors 4 3 4 8 4 12 6 26 6 27 DMAC10 channels data streams ADSP 2106x 160 processors 4 2 4 3 4 8 encrypting from application 3 61 4 9 4 12 4 15 encrypting from kernel 3 63 ADSP 21161 processors 5 5 5 6 5 7 5 9 dat data initialization files A 2 5 10 debugger file formats 1 8 A 15 VisualDSP 5 0 Loader and Utilities Manual 1 5 INDEX DMAC6 channel ADSP 2106x 160 process
102. 4 7 lists all PROM to processor connections Table 4 7 PROM Connections to ADSP 2106x 21160 Processors Processor Connection ADSP 21060 61 62 PROM EPROM connects to DATA23 16 pins ADSP 21065L PROM EPROM connects to DATA7 0 pins ADSP 21160 PROM EPROM connects to DATA39 32 pins ADSP 21xxx Address pins of PROM connect to lowest address pins of any pro cessor ADSP 21xxx Chip select connects to the BMS pin ADSP 21060 61 62 65L Output enable connects to the RD pin ADSP 21160 Output enable connects to RDH pin VisualDSP 5 0 Loader and Utilities Manual 4 7 ADSP 2106x 21160 Proc essor Booting During reset the ACK line is pulled high internally with a 2K ohm equivalent resistor and is held high with an internal keeper latch It is not necessary to use an external pull up resistor on the ACK line during booting or at any other time The DMA channel parameter registers are initialized at reset for EPROM booting as shown in Table 4 8 and Table 4 9 The count is initialized to 0x0100 to transfer 256 words to internal memory The external count register ECx which is used when external addresses BMS space are gen erated by the DMA controller is initialized to 0x0600 0x100 words at six bytes per word Table 4 8 DMA Settings for ADSP 2106x EPROM Booting DMA Setting Processor Model ADSP 21060 61 62 ADSP 21065L BMS space 4M x 8 bit 8M x 8 bit
103. 5 INDEX SRAM memory Blackfin processors ADSP BF531 2 3 4 6 7 8 9 processors 3 19 ADSP BF535 processors 3 33 ADSP BF561 processors 3 37 3 45 s section_name splitter switch 8 6 start addresses ADSP 2106x 160 application code 4 4 Blackfin application code 2 14 2 20 3 66 3 74 status information 2 16 2 20 3 68 3 74 stk byte stacked files 8 4 8 6 8 7 A 12 streams See boot streams supervisor mode Blackfin processors ADSP BF531 2 3 4 6 7 8 9 processors 3 7 ADSP BF535 processors 3 23 ADSP BF561 processors 3 37 synchronous boot operations 4 13 SYSCON register SHARC processors ADSP 2106x 160 processors 4 10 4 12 4 13 4 19 4 22 ADSP 21161 processors 5 18 5 21 ADSP 2126x 36x 37x 46x processors 6 20 6 22 SYSCR register Blackfin processors ADSP BF531 2 3 4 6 7 8 9 processors 3 8 ADSP BF561 processors 3 37 3 38 SYSCTL register 6 31 SYSTAT register 4 23 system reset configuration register See SYSCR register T t loader switch for SHARC 4 31 5 31 loader switch for TigerSHARC 7 10 termination records A 11 text files A 4 A 14 TigerSHARC processors boot modes 7 2 7 3 7 9 timeout cycles TigerSHARC processors 7 10 two wire interface TWI boot mode ADSP BF2x 54x processors 2 4 ADSP BF534 6 7 processors 3 4 3 12 txt ASCII text files A 4 U u splitter switch 8 7 UART slave boot mode Blackfin processors 2 3 2 4 3 4 UBWM register 4 11 uncompresse
104. 5 processors only 3 60 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Proc essors Table 3 10 Blackfin Loader Command Line Switch Summary Contd Switch Description compression The compression switch directs the loader utility to compress the boot stream see ADSP BF53 1 BF532 BF533 BF534 BF536 BF537 Processor Compression Support on page 3 49 Either a default or user ini tialization dxe file with decompression code must be provided for compression This switch is for flash PROM boot modes only and does not apply to the ADSP BF535 ADSP BF538 ADSP BF539 or ADSP BF561 processors compressWS The compressWS switch specifies a compression window size in bytes The number is a 2 s exponential value to be used by the com pression engine The valid values are 8 15 bits with the default of 9 bits This switch is for flash PROM boot modes only and does not apply to the ADSP BF535 ADSP BF538 ADSP BF539 or ADSP BF561 processors dmawidth The dmawidth 8 16 switch specifies a DMA width in bits to the loader utility For FIFO boot mode 16 is the only DMA width For other boot modes all DMA widths are valid with the default of eight Does not apply to the ADSP BF535 or ADSP BF561 processors enc dll_filename The enc d11_filename switch encrypts the data stream from the application input dxe file
105. 5DB041B AT45DB081B and AT45DBI161B DataFlash devices Table 3 2 ADSP BF534 BF536 BF537 Processor Boot Modes Boot Source BMODE 2 0 Executes from an external 16 bit memory connected to 000 ASYNC bank 0 no boot mode or bypass on chip boot ROM see on page 3 16 Eight or 16 bit flash PROM 001 Reserved 010 Eight 16 or 24 bit addressable SPI memory in SPI master 011 mode with support for Atmel AT45DB041B AT45DBO081B and AT45DB161B DataFlash devices SPI host in SPI slave mode 100 TWI serial device 101 TWI host 110 UART host 111 3 4 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Processors e Execute from 16 bit external memory execution starts from address 0x2000 0000 with 16 bit packing The boot ROM is bypassed in this mode All configuration settings are set for the slowest device possible 3 cycle hold time 15 cycle R W access times 4 cycle setup e Boot from eight bit or 16 bit external flash memory the eight bit or 16 bit flash boot routine located in boot ROM memory space is set up using asynchronous memory bank 0 All configuration set tings are set for the slowest device possible 3 cycle hold time 15 cycle R W access times 4 cycle setup The boot ROM evalu ates the first byte of the boot stream at address 0x2000 0000 If it is 0x40 eight bit boot is performed A 0x60 byte assumes a 16 bit memory device
106. 600004844521B Header record 10D00043C4034343426142226084C Data record S1 S903000DEF Termination record S1 Table A 5 shows the organization of an example header record Table A 5 Header Record Example Field Purpose 00600004844521B Example record So Start character 06 Byte count of this record 0000 Address of first data byte 484452 Identifies records that follow 1B Checksum Table A 6 shows the organization of an S1 data record A 10 VisualDSP 5 0 Loader and Utilities Manual Table A 6 S1 Data Record Example File Formats Field Purpose 10D00043C4034343426142226084C Example record S1 Record type OD Byte count of this record 0004 Address of the first data byte 3C First data byte 08 Last data byte AC Checksum The S2 data record has the same format except that the start character is s2 and the address field is six characters wide The 3 data record is the same as the S1 data record except that the start character is 3 and the address field is eight characters wide Termination records have an address field that is 16 24 or 32 bits wide whichever matches the format of the preceding records Table A 7 shows the organization of an S1 termination record Table A 7 S1 Termination Record Example Field Purpose S903000DEF Example record s9 Start character 03
107. A channel is automat ically configured for a 256 instruction transfer This transfer boot loads the boot kernel program into the processor memory 2 The boot kernel runs and loads the application executable code and data 3 The boot kernel overwrites itself with the first 256 words of the application at the end of the booting process After that the appli cation executable code starts running The boot mode selection directs the system to prepare the appropriate boot kernel VisualDSP 5 0 Loader and Utilities Manual 5 3 ADSP 21161 Proc essor Booting Boot Mode Selection The state of the LBO00T EBOOT and BMS pins selects the ADSP 21161 pro cessor s boot mode Table 5 1 and Table 5 2 show how the pin states correspond to the modes Table 5 1 ADSP 21161 Boot Mode Pins Pin Type Description EBOOT I EPROM boot when EB00T is high the processor boot loads from an 8 bit EPROM through the processor s external port When EBOOT is low the LBOOT and BMS pins determine booting mode LBOOT Link port boot when LBOOT is high and EBOOT is low the processor boots from another SHARC processor through the processor s link port When LBOOT is low and EBOOT is low the processor boots from a host processor through the processor s external port ies ica I O T Boot memory select when boot loading from EPROM EB00T 1 and LBOOT 0 the pin is an output and serves as the
108. ABBBBCCCC 44445555 44445555 1111 22 BBBBCCCC BBBBCCCC 6666 22 OOOOAAAA OOOOAAAA 5555 11 00000000 00000000 4444 11 CCCC 66 BBBB 66 AAAA 55 0000 55 0000 44 0000 44 CE 6 26 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2126x 2136x 2137x 2146x SHARC Processors Table 6 13 INIT_L48 Block Packing and Zero Padding ASCII Format Original Data Packed into an Even hostwidth Number of 32 bit Words 32 16 8 CC BB INIT_L16 Blocks For 16 bit initialization blocks the number of 16 bit words in the block must be even If an odd number of 16 bit words is in the block then the loader utility adds one additional word all zeros to the end of the block as shown in Table 6 14 The count stored in the header is the actual num ber of 16 bit words The count does not include the padded word Table 6 14 INIT_L16 Block Packing and Zero Padding ASCII Format Original Data Packed into an Even hostwidth Number of 32 bit Words 32 16 8 1122 33441122 33441122 1122 22 3344 00005566 00005566 3344 11 5566 5566 44 0000 33 66 55 00 00 VisualDSP 5 0 Loader and Utilities Manual 6 27 ADSP 2126x 2136x 2137x 2146x Proc essor Booting INIT_L64 Blocks For 64 bit initialization blocks the data is packed as shown in Table 6 15 Table 6 15 INIT_L64 Block Packing ASCII Format O
109. ACK line during booting or at any other time The RBWS and RBAM fields of the WAIT register are initialized to perform asynchronous access and generate seven wait states eight cycles total for the EPROM access in external memory space Note that wait states defined for boot memory are applied to BMS asserted accesses Table 5 3 shows how DMA channel 10 parameter registers are initialized at reset The count register CEPO is initialized to 0x0100 to transfer 256 words to internal memory The external count register ECEP0 used when external addresses BMS space are generated by the DMA controller is ini tialized to 0x0600 0x0100 words at six bytes per word The DMAC10 control register is initialized to 0x00 0561 The default value sets up external port transfers as follows e DEN 1 external port enabled e MSWF 0 LSB first e PMODE 101 8 bit to 48 bit packing Master 1 e DTYPE 1 three column data VisualDSP 5 0 Loader and Utilities Manual 5 7 ADSP 21161 Proc essor Booting Table 5 3 DMA Channel 10 Parameter Registers for EPROM Booting Parameter Register Initialization Value IIEPO 0x40000 IMEPO Uninitialized increment by 1 is automatic CEPO 0x100 256 instruction words CPEPO Uninitialized GPEPO Uninitialized EIEPO 0x800000 EMEPO Uninitialized increment by 1 is automatic ECEPO 0x600 256 words x 6 bytes word The following sequence occurs at syst
110. ADSP 2106x 21160 Loader Command Line Switches Switch Description si revision The si revision none any switch provides a silicon revision dF none any of the specified processor The switch parameter represents a silicon revision of the processor spec ified by the proc processor switch The parameter takes one of three forms The none value indicates that the VisualDSP ignores sili con errata e The value indicates one or more decimal digits followed by a point followed by one or two decimal digits Examples of revisions are 0 0 1 12 23 1 Revision 0 1 is distinct from and lower than revision 0 10 The digits to the left of the point specify the chip tapeout number the digits to the right of the point identify the metal mask revision number The number to the right of the point cannot exceed decimal 255 e The any value indicates that VisualDSP produces an out put file that can be run at any silicon revision The switch generates either a warning about any potential anomalous conditions or an error if any anomalous conditions occur In the absence of the switch parameter a valid revision value si revision alone or with an invalid value the loader utility generates an error tit Host boot only Specifies timeout cycles for example t100 Limits the number of cycles that the processor spends initializing external memory with zeros Valid timeout values range from 3 to 32765 cycles 3
111. ADSP 21367 21368 21369 2137x and ADSP 2146x processors the external PM memory address ranges are 0x200000 0x23FFFF The par allel port automatically packs internal 32 bit words to either 8 bit or 16 bit words for external memory These are the only widths supported The WIDTH command in the linker specifies which packing mode should be used to initialize the external memory WIDTH 8 for 8 bit memory or WIDTH 16 for 16 bit memory The loader utility packs the external memory data from the dxe file according to the linker s WIDTH command The loader utility unpacks the data from the executable file and packs the data again in the loader file if the data is packed in the dxe file due to the packing command in the linker description 1df file Packing and Padding Details For ZERO_INIT sections in a dxe file no data packing or padding in the 1dr file is required because only the header itself is included in the 1dr file However for other section types additional data manipulation is required It is important to note that in a cases the word count placed into the block header in the loader file is the original number of words That is the word count does not include the padded word SPI Port Boot Modes The ADSP 2126x 2136x 2137x 2146x SHARC processor supports boot ing from a host processor via serial peripheral interface slave mode B00T_CFG1 0 00 or BOOT_CFG2 0 000 and booting from an SPI flash SPI PROM or a host
112. BO is initialized to 0x0100 to transfer 256 words to internal memory The LCTL register is overridden during link port boot to allow link buffer 0 to receive 48 bit data VisualDSP 5 0 Loader and Utilities Manual 5 13 ADSP 21161 Proc essor Booting Table 5 5 DMA Channel 8 Parameter Register for Link Port Boot Parameter Register Initialization Value IILBO 0x0004 0000 IMLBO Uninitialized increment by 1 is automatic CLBO 0x0100 256 instruction words CPLBO Uninitialized GPLBO Uninitialized In systems where multiple processors are not connected by the parallel external bus booting can be accomplished from a single source through the link ports To simultaneously boot all the processors make a parallel common connection to link buffer 0 on each of the processors If a daisy chain connection exists between the processors link ports each processor can boot the next processor in turn Link buffer 0 must always be used for booting SPI Port Boot Mode Serial peripheral interface SPI port booting uses DMA channel 8 of the IO processor to transfer instructions to internal memory In this boot mode the processor receives 8 bit wide data in the SPIRx register During the boot process the program loads 256 words into memory loca tions 0x40000 through 0x400FF The processor subsequently begins executing instructions Because most processor programs require more than 256 words of instructions
113. BSO bit set allowing the processor to gain access to the boot EPROM and a third with the 850 bit cleared When BS0 1 the EPROM packing mode bits in the DMACx control register are ignored and 8 to 48 bit packing is forced 8 bit pack ing is available only during EPROM booting or when B50 is set When an external port DMA channel is being used in conjunction with the BSO bit none of the other three channels may be used In this mode BMS is not asserted by a core processor access but only by a DMA transfer This allows the boot kernel to perform other external accesses to non boot memory VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2106x 21160 SHARC Processors The EPROM is automatically selected by the BMS pin after reset and other memory select pins are disabled The processor s DMA controller reads the 8 bit EPROM words packs them into 48 bit instruction words and transfers them to internal memory until 256 words have been loaded The master DMA internal and external count registers Cx and ECx decrement after each EPROM transfer When both counters reach zero DMA trans fer has stopped and RTI returns the program counter to the address where the kernel starts To EPROM boot a single processor system include the executable on the command line without a switch Do not use the id exe switch with ID 0 see ADSP 2106x 21160 Processor ID Num bers on page 4 24 The WAIT register UBWM used for EPROM
114. Byte count of this record 000D Address EF Checksum The S2 termination record has the same format except that the start char acter is S8 and the address field is six characters wide VisualDSP 5 0 Loader and Utilities Manual A 11 Build Files The S3 termination record is the same as the 1 format except the start character is S7 and the address field is eight characters wide For more information see hexutil Hex 32 to S Record File Converter on page B 2 Splitter Output Files in Intel Hex 32 Format The splitter utility can output Intel hex 32 format h_ files These ASCII files support a variety of PROM devices For an example of how the Intel hex 32 format appears for an 8 bit wide PROM see Loader Output Files in Intel Hex 32 Format on page A 6 The splitter utility prepares a set of PROM files Each PROM holds a por tion of each instruction or data This configuration differs from the loader output Splitter Output Files in Byte Stacked Format The splitter utility can output files in byte stacked stk format These files are not intended for PROMs but are ideal for microcontroller data transfers A file in byte stacked format comprises a series of one line headers each followed by a block one or more lines of data The last line in the file is a header that signals the end of the file Lines consist of ASCII text that represents hexadecimal digits Two characters represent one by
115. CONTENTS Technical or Customer Support You can reach Analog Devices Inc Customer Support in the following ways Visit the Embedded Processing and DSP products Web site at http www analog com processors technical_support E mail tools questions to processor tools support analog con E mail processor questions to processor support analog com World wide support processor europe analog com Europe support processor china analog com China support Phone questions to 1 800 ANALOGD Contact your Analog Devices Inc local sales office or authorized distributor Send questions by mail to Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 USA VisualDSP 5 0 Loader and Utilities Manual xv CONTENTS Supported Processors Loader and utility programs of VisualDSP 5 0 supports the following Analog Devices Inc processors e Blackfin ADSP BF xxx e SHARC ADSP 21xxx e TigerSHARC ADSP TSxxx The majority of the information in this manual applies to all processors For a complete list of processors supported by VisualDSP 5 0 refer to the online Help Product Information Product information can be obtained from the Analog Devices Web site VisualDSP online Help system and a technical library CD Analog Devices Web Site The Analog Devices Web site www analog com provides information about a broad range of products analog integrated circuits amplifiers conv
116. Description proc processor The proc processor switch specifies the target processor The processor can be one of the processors listed in Table 2 1 quickboot sec section The quickboot switch takes a sec section no spaces assign ment The switch directs the loader utility to mark blocks within the LDF defined output section name with the BFLAG_QUICKBOOT flag The switch is used to mark blocks to skip on warm boot cycles readall The readal1 switch directs the loader utility to integrate fixed position ROM sections within the loader boot stream The switch calls the splitter utility as a transparent sub process to the loader utility Memory segments declared with the TYPE ROM command in the LDF file are processed by the splitter Segments with the TYPE RAM command emit to the boot stream The valid switch argument is an integer between 0 and 32 where 29 is the default In the resulting loader 1dr file in Intel hex 32 format the ROM based splitter data is merged with the RAM based loader stream The argument is similar to the maskaddr switch which desig nates the upper PROM address bit position for extended address mapping The splitter utility is required to provide the maskaddr parameter to the loader utility to generate a ROM based splitter stream but the required splitter parameter is not available on the loader command line The loader utility solves this requirement by supporting the readal1 sw
117. File Description dxe Executable files and boot kernel files The loader utility recognizes overlay memory files 0v1 and shared memory files sm but does not expect these files on the command line Place ov1 and sm files in the same directory as the dxe file that refers to them The loader utility finds the files when processing the dxe file The ovl and sm files may also be placed in the ov1 and sm file output directory specified in the 1df file Loader output file VisualDSP 5 0 Loader and Utilities Manual 6 43 ADSP 2126x 2136x 2137x 2146x Proc essor Loader Guide Loader Command Line Switches Table 6 18 is a summary of the ADSP 2126x ADSP 2136x ADSP 2137x and ADSP 2146x loader switches Table 6 18 ADSP 2126x 2136x 2137x 2146x Loader Command Line Switches Switch Description bprom Specifies the boot mode The b switch directs the loader utility to bspislave bspi bspimaster bspiprom bspiflash prepare a boot loadable file for the specified boot mode The valid modes boot types are PROM SPI slave SPI master SPI PROM and SPI flash If b does not appear on the command line the default is bprom To use a custom boot kernel the boot type selected with the b switch must correspond with the boot kernel selected with the 1 switch Otherwise the loader utility automatically selects a default boot kernel based on the selected boot type see ADSP 2126x 2136x 2137
118. HARC 6 35 6 39 6 44 Compression Load page Blackfin processors 3 75 compressionOverlay loader switch for SHARC 6 36 6 39 6 44 compression support ADSP 2126x 36x 37x 46x processors 6 35 ADSP BF531 2 3 4 6 7 8 9 processors 3 49 3 75 compression window 3 51 3 56 6 38 6 41 compress WS loader switch for Blackfin 3 56 3 61 loader switch for SHARC 6 41 6 44 conversion utilities B 2 count headers Blackfin processors ADSP BF531 2 3 4 6 7 8 9 processors 3 46 ADSP BF561 processors 3 39 3 43 3 46 CPEPO register 5 8 5 11 CPHASE bit 6 9 6 11 CPLBO register 5 14 1 4 VisualDSP 5 0 Loader and Utilities Manual INDEX CRC32 loader switch for Blackfin 2 8 debugging targets 1 9 CS pin 4 13 5 12 6 8 decompression CSPI register 6 9 6 11 initialization files 3 54 CSRX register 5 16 kernel files 6 40 customer support xv DEN register 5 7 5 11 Cx register 4 8 4 9 4 11 4 15 dlb library files A 5 dm splitter switch 8 5 D DMA ADSP 2106x 160 processors channels See channels by name ODMACx D23 16 bits 4 10 buffers 4 13 D39 32 bits 4 10 channel control registers 4 10 4 12 4 13 D7 0 bits 4 10 4 14 4 15 4 16 data oo channel interrupts 4 13 4 14 4 16 initialization files dat A 2 channel parameter registers 4 8 4 9 4 11 memory dm sections 8 3 8 5 ATX 446 records in Intel hex 32 format A 7 controller 42 48 20 417 transfers See DMA transfers transfers 4 10
119. If you develop an ADSP BF531 BF532 BF533 BF534 BF536 or ADSP BF537 processor based application you can select Compression under Load in the Project Options tree control to set parameters for zLib compression To enable compression select Enable Compression You can select the Compression window size 2 N Retain kernel after boot and Com press Overlays options The dialog box options are equivalent to command line switches See ADSP BF531 BF532 BF533 BF534 BF536 BF537 Processor Compres sion Support on page 3 49 for more information Project Options for An ADSP BF537 Based Project Lp Project a lez Project Eh General j fis Compile zLib Compression Eh General Eh Language Settings Eh MISRA C E Preprocessor fy Processor 1 EA Processor 2 Eh Profile quided Optimization EA Warning Assemble Link Eh General fy LDF Preprocessing C Enable Compression Compression window size 2 N ee of E Elimination fy Processor Load Fs Options Additional options EN conpesson i EA Kernel E Splitter Figure 3 27 Project Load Compression Page for ADSP BF537 Proces sors VisualDSP 5 0 Loader and Utilities Manual 3 75 ADSP BF53x BF561 Processor Loader Guide Using VisualDSP Sec ond Stage Loader for ADSP BF535 Processors If you use a second stage loader select Kernel under Load in the Project Options tree control The page shows the default settings for a loader file that incl
120. Loader Command Line Pa ee esas eRe a oee 2 8 ADSP BF5 1x BF52x BF54x Multi DXE Loader Files 2 17 Using Visul DSP Lae canciones 2 18 Using VisualDSP Second Stage Loader eeceeeeeeeeeeeees 2 20 Using VisualDSP ROM Splitter ss sisicibiiamscissiasasiescnineisiass 2 22 LOADER SPLITTER FOR ADSP BF53X BF561 BLACKFIN iv VisualDSP 5 0 Loader and Utilities Manual CONTENTS PROCESSORS ADSP BF53x BF561 Processor Booting scncacsiceutiemusneienss 3 2 ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF338 BFE539 Processor Booting coccinea 3 3 ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 Processor On Chip Boot ROM ciisuncctenmceae 3 7 ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BE539 Processor Boot Strearns ccsicicsintendedeaas towns sdwdauteaadaawes 3 9 ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF339 Block Headers and Flags ncccnscnsimisisiiis 3 10 ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 Initialization Blocks eeecceeeeeeeeeecceececneeceneeeees 3 13 ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 and ADSP BF535 Processor No Boot Mode 3 16 ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF339 Processor Memory Ranges cesnnmienieseimus 3 19 ADSP BF333 Processor Booting serssaccirsevsoseseniarinnsetonsines 3 21 ADSP BF535 Processor On Chip Boot ROM neses 3 23 ADSP BF535 Processor Second Stage Loader sscseceecese 3 24 ADSP BF535 Processor Boot Streams aernsunvnenrwininvss 3 27 Loa
121. M or SPI memory boot respectively After the processor returns from the execution of the initialization blocks the boot ROM continues to load blocks from the location specified in the RO or R3 register which can be any dxe file in the boot stream This option requires the starting locations of specific executables within exter nal memory The RO or R3 register must point to the 10 byte count header as illustrated in ADSP BF53x and ADSP BF561 Multi Application Multi DXE Management on page 3 46 VisualDSP 5 0 Loader and Utilities Manual 3 43 ADSP BF53x BF561 Proc essor Booting ADSP BF561 Dual Core Application Management A typical ADSP BF561 dual core application is separated into two execut able files one executable file for each core The default linker description 1df file for the ADSP BF561 processor creates two separate executable files p0 dxe and p1 dxe and some shared memory files sm12 sm and sm13 sm By modifying the LDF it is possible to create a dual core application that combines both cores into a single dxe file This is not recommended unless the application is a simple assembly language pro gram which does not link any C run time libraries When using shared memory and or C run time routines on both cores it is best to generate a separate dxe file for each core The loader utility combines the contents of the shared memory files sm12 sm sm13 sm only into the boot stream generated from the dxe fi
122. NT FOR BYTE COUNT N APPLICATION CODE BYTE 0 BYTE 1 BYTE 2 APPLICATION BYTE 3 lt cove N WORDS D7 DO Figure 3 11 Loader File for Eight bit Flash PROM and SPI Boot Without Second Stage Loader 3 28 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Proc essors Figure 3 12 is a graphical representation of an output loader file for 16 bit flash PROM boot without the second stage loader OUTPUT LDR FILE 4 BYTE HEADER FOR BYTE COUNT N BYTE COUNT FOR lt APPLICATION CODE BYTE 0 e e h APPLICATION CODE N WORDS D15 D8 D7 DO Figure 3 12 Loader File for 16 bit Flash PROM Boot Without Sec ond Stage Loader Loader Files With a Second Stage Loader Figure 3 13 is a graphical representation of an output loader file for eight bit flash PROM boot and eight or 16 bit addressable SPI boot with the second stage loader Figure 3 14 is graphical representation of an output loader file for 16 bit flash PROM boot with the second stage loader VisualDSP 5 0 Loader and Utilities Manual 3 29 OUTPUT LDR FILE 4 BYTE HEADER FOR 4 BYTE COUNT FOR BYTE COUNT N 2Nd STAGE LOADER BYTE 0 BYTE 1 BYTE 2 4 2nd STAGE LOADER N BYTES BYTE 0 APPLICATION BYTE 1 CODE iN BLOCKS BYTE 2 D7 DO ADSP BF53x BF561 Proc essor Booting SEE ALSO FIGURE 3 12 SEE ALSO FIGURE 3 14 Figure 3 13 Loader File for Eight bit Flash PROM and SPI B
123. O DM 1T4 M5 R9 PM This instructi tended for that address is instead placed NIT section itiated header and has loaded into PX before executes the RTI at 0x80030 and vectors to the on the PC stack 0x80004 Again the loader has inserted an instruction into the boot stream and has placed it at 0x40005 opcode x39732D802000 on does the 112 M13 R11 following A Restores the power up value of SYSCTL held in R11 B Overwrites The first instruction o this new in C RO RO RO ca This satisfies in FINAL_INIT is achieved wi the processor one final time itself with the instruction PM 0 18 PX f FINAL_INIT places the opcode for struction OxB16B00000000 into R9 uses the AZ the termina DO RESET U thin the las branches to flag to be set tion condition of the loop set up TIL EQ When a loop condition t three instructions of a loop the top of loop address PCSTK 6 32 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2126x 2136x 2137x 2146x SHARC Processors 5 We manually changed this top of loop address 0x80004 and so to conclude the kernel the processor executes the instruction at 0x80004 again 6 There s a new instruction at 0x80004 PM 0 I8 PX This initializes the user intended instruction at 0x80030 the vec tor for the High Priority SPI interrupt At this point the kernel is finished and execution continues at 0x8
124. P BF53x BF561 Blac kfin Proc essors each bootable block This alleviates the need for a second stage loader because a full application can be booted to the various memories with just the on chip boot ROM The loader utility converts the application code dxe into the loadable file by parsing the code and creating a file that consists of different blocks Each block is encapsulated within a 10 byte header which is illustrated in Figure 3 1 and detailed in the following section The headers in turn are read and parsed by the on chip boot ROM during booting The 10 byte header provides all information the on chip boot ROM requires where to boot the block to how many bytes to boot in and what to do with the block ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 Processor Boot Steams The following sections describe the boot stream header and flag frame work for the ADSP BF531 ADSP BF532 ADSP BF533 ADSP BF534 ADSP BF536 ADSP BF537 ADSP BF538 and ADSP BF539 processors e ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 Block Headers and Flags on page 3 10 e ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 Initialization Blocks on page 3 13 The ADSP BF53 1 BF532 BF533 BF534 BF536 BF537 BF538 BF539 processor boot stream is similar to the boot stream that uses a second stage kernel of the ADSP BF535 processors detailed in Loader Files With a Second Stage Loader on page 3 29
125. P 21160 processors Link port mode is selected when the EBOOT is low and LBOOT and BMS are high The external device must provide a clock signal to the link port assigned to link buffer 4 The clock can be any frequency up to a maxi mum of the processor clock frequency The clock falling edges strobe the data into the link port The most significant 4 bit nibble of the 48 bit instruction must be downloaded first The link port acknowledge signal generated by the processor can be ignored during booting since the link port cannot be preempted by another DMA channel Link booting is similar to host booting the parameter registers 11x and Cx for DMA channels are initialized to the same values The DMA channel 6 control register DMAC6 is initialized to 0x00A0 and the DMA channel 10 control register DMAC10 is initialized to 0x100000 This disables external port DMA and selects DTYPE for instruction words The LCTL and LCOM link port control registers are overridden during link boot ing to allow link buffer 4 to receive 48 bit data VisualDSP 5 0 Loader and Utilities Manual 4 15 ADSP 2106x 21160 Proc essor Booting After booting completes the IMASK remains set allowing DMA channel interrupts This interrupt must be cleared before link buffer 4 is again enabled otherwise unintended link interrupts may occur No Boot Mode No boot mode causes the processor to start fetching and executing instructions at address 0x400004 ADSP
126. RC SDRAM Refresh Rate Control Register PO H HI EBIU_SDRRC RO Ox074A Z WCPO RO SSYNC PO L LOCEBIU_SDBCTL SDRAM Memory Bank Control Register PO H HI EBIU_SDBCTL RO Ox0001 Z WCPO RO SSYNC PO L LOCEBIU_SDGCTL SDRAM Memory Global Control Register PO H HI EBIU_SDGCTL RO L 0x998D VisualD SP 5 0 Loader and Utilities Manual 3 15 ADSP BF53x BF561 Proc essor Booting RO H 0x0091 PO RO SSYNC ERKKRKKKKKKKKKKKKKKKEKDOSHK Nit SOCETONK KK KR KKK KKK KKK KK KK KK KK KK L3 SP L2 SP L1 SP LO SP M3 SP M2 SP M1 SP MO SP B3 SP B2 SP Bl SP BO SP 13 SP 12 SP I1 SP 10 SP p5 0 SP r7 0 SP RETS SP ASTAT SP BRK RKKK KK KKK KKK KK KKK KKK KKK KK KK KKK KKK KKK KKK KKK KK KK KKK KKK KKK KK RTS ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 and ADSP BF535 Processor No Boot Mode The hardware settings of BMODE 00 for the ADSP BF531 ADSP BF532 and ADSP BF533 processors or BMODE 000 for the ADSP BF535 proces sors select the no boot option In this mode of operation the on chip boot kernel is bypassed after reset and the processor starts fetching and executing instructions from address 0x2000 0000 in the asynchronous memory bank 0 The processor assumes 16 bit mem
127. SP BF53x BF561 Proc essor Booting A global header s bit assignments for eight and 16 bit addressable SPI boot are illustrated in Figure 3 17 es ee ele Ld Baud rate 0 500 kHz default 1 1 MHz 2 2 MHz Figure 3 17 SPI Boot Global Header Bit Assignments Block Headers and Flags For application code a block is the basic structure of the output 1dr file when the second stage loader is used All application code is grouped into blocks A block always has a header and a body if it is a non zero block A block does not have a body if it is a zero block A block structure is illus trated in Figure 3 18 OUTPUT LDR FILE SIZE OF APPLICATION CODE N1 4 BYTES BYTE COUNT N N1 START ADDRESS OF BLOCK 1 4BYTES z N BYTES 2Nd STAGE LOADER i q BYTE COUNT apytes 8 d OF BLOCK 1 z g ni aii oY SADDRESS macrorstock FOR BLOCK 1 2 BYTES 2 4 BYTES GLOBAL HEADER BODY OF BLOCK 1 SIZE OF APPLICATION CODE N1 E ADDRESS E BLOCK 2 APPLICATION CODE BYTE COUNT OF BLOCK 2 Figure 3 18 An Application Block 3 32 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Proc essors A block header has three words 4 byte clock start address 4 byte block byte count and 2 byte flag word The ADSP BF535 block flag word s bits are illustrated in Figure 3 19 s PE a a Bit 15 1 Last Block 0 Not Last Block Bit 0 1 Zero Fill
128. SP BF548M ADSP BF542M ADSP BF544M ADSP BF547M ADSP BF548M ADSP BF549M There are other boot modes available including idle no boot mode The processor transitions into the boot mode sequence configured by the BMODE pins see Table 2 2 and Table 2 3 The BMODE pins are dedicated mode control pins that is no other functions are performed by the pins The pins can be read through bits in the system configuration register SYSCR 2 2 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF51x BF52x BF54x Blac kfin Proc essors There are two categories of boot modes master and slave In master boot modes the processor actively loads data from parallel or serial memory devices In slave boot modes the processor receives data from parallel or serial memory devices Refer to the processor s data sheet and hardware reference manual for more information on system configuration peripherals regis ters and operating modes e Blackfin processor data sheets can be found at http www analog com en embedded processing dsp black fin processors data sheets resources index html e Blackfin processor manuals can be found at http www analog com en embedded processing dsp black fin processors manuals resources index html Table 2 2 ADSP BF51x Boot Modes Boot Source BMODE 2 0 Start Address Idle no boot 000 N A Eight or 16 bit external flash memory default mode 00
129. SYSCON to change the PMODE and HBW HPW for the ADSP 21065L processors setting The host boot file created by the loader utility requires the host processor to perform the following sequence of actions 1 The host initiates the synchronous booting operation synchronous not valid for the ADSP 21065L processors by asserting the proces sor HBR input pin informing the processor that the default 8 16 bit bus width is used The host may optionally assert the CS chip select input to allow asynchronous transfers 2 After the host receives the HBG signal and ACK for synchronous operation or READY for asynchronous operation from the proces sor the host can start downloading instructions by writing directly to the external port DMA buffer 0 or the host can change the reset initialization conditions of the processor by writing to any of the 10P control registers The host must use data bus pins as shown in Table 4 10 3 The host continues to write 16 bit words 8 bit for the ADSP 21065L to EPB0 until the entire program is boot loaded The host must wait between each host write to external port DMA buffer 0 After the host boot loads the first 256 instructions of the boot kernel the initial DMA transfers stop and the boot kernel 1 Activates external port DMA channel interrupt EP01 stores the DMACx control setting in R2 for later restore clears DMACx for new setting and sets the BUSLCK bit in the MODE2 register to lock out the h
130. Slave Processor Vs a Slave PROM Table 6 9 Initial Word for SPI Master and SPI PROM in ldr File Boot Mode Additional Word hostwidth 32 16 8 SPI master 0xA5000000 45000000 0000 00 A500 00 00 A5 SPI PROM2 OxA5 A5 A5 A5 1 Initial word for SPI master boot type is always 32 bits See Figure 6 1 on page 6 13 for explana tion 2 Initial word for SPI PROM boot type is always 8 bits See Figure 6 1 on page 6 13 for explanation VisualDSP 5 0 Loader and Utilities Manual 6 15 ADSP 2126x 2136x 2137x 2146x Proc essor Booting Table 6 10 Default Settings for PROM and SPI Boot Modes Boot Type Host Output Format Bit Reverse Initial Word Selection Width bprom 8 Intel hex No bspislave 32 ASCII No bspiflash 32 ASCII No bspimaster 32 ASCII No 0x000000a5 bspiprom 8 Intel hex Yes 0xa5 Booting From an SPI Flash For SPI flash devices the format of the boot stream is identical to that used in SPI slave mode with the first byte of the boot stream being the first byte of the kernel This is because SPI flash devices do not drive out data until they receive an 8 bit command and a 24 bit address Booting From an SPI PROM 16 bit address Figure 6 2 shows the initial 32 bit word sent out from the processor from the perspective of the serial PROM device As shown in Figure 6 2 SPI EEPROMs only require an 8 bit opcode and a 16 b
131. The slave DMA internal count register CEP0 decrements after each trans fer When CEPO reaches zero the following wake up sequence occurs 1 The DMA transfers stop 2 The external port DMA channel 10 interrupt EP01 is activated 3 The processor vectors to the EPOI interrupt vector at 0x40050 At this point the processor has completed its boot mode and is executing instructions normally The first instruction at the EP0I interrupt vector location address 0x40050 should be an RTI return from interrupt This process returns execution to the reset routine at location 0x40005 where normal program execution can resume After reaching this point a pro gram can write a different service routine at the EPOI vector location 0x40050 Link Port Boot Mode Link port boot uses DMA channel 8 of the IO processor to transfer instructions to internal memory In this boot mode the processor receives 4 bit wide data in link buffer 0 After the boot process loads 256 words into memory locations 0x40000 through 0x400FF the processor begins to execute instructions Because most processor programs require more than 256 words of instructions and initialization data the 256 words typically serve as a loading routine for the application VisualDSP includes loading routines boot kernels 5 12 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 21161 SHARC Processors that load an entire program through the selected port refer to
132. This instruction is stored in the header for FINAL_INIT as shown in Listing 6 2 e For PROM boot mode the RTI is placed at address 0x80050 for the ADSP 2126x and at 0x90050 for the ADSP 2136x 2137x 2146x processors e For all SPI boot modes the RTI is placed at address 0x80030 for the ADSP 2126x and at 0x90030 for the ADSP 2136x 2137x 2146x processors high priority SPI interrupt 3 Saves an IVT instruction in the FINAL_INIT block header The count and address of a FINAL_INIT block are constant to avoid any redundancy the count and address are not placed into the block header Instead the 32 bit count and address words are used to hold the instruction that overwrites the RTI inserted into the IVT Listing 6 1 illustrates the block header for FINAL_INIT if for example the opcode 0xAABBCCDDEEFF is assumed to be the user intended instruction for the IVT VisualDSP 5 0 Loader and Utilities Manual 6 29 ADSP 2126x 2136x 2137x 2146x Proc essor Booting Listing 6 2 FINAL_INIT Block Header Format 0x00000000 FINAL_INIT tag 0x0 OxEEFF0000 LSBs of instructions ef OxAABBCCDD 4 MSBs of instructions Listing 6 3 FINAL_INIT Section FINAL_INIT The FINAL_INIT subroutine in the boot kernel program sets up a DMA to overwrite itself The code is the very last piece that runs in the kernel it is self modifying code It uses a DMA to overwrite itself initializing the 256 instructions that
133. TigerSHARC Processor Booting TigerSHARC Processor Boot Kemels Upon completion of the DMA in all boot modes the boot loading pro cess continues by downloading the boot kernel into the processor memory The boot kernel sets up and initializes the processor s memory After initializing the rest of the system the boot kernel overwrites itself You can build an 1dr file that includes or does not include a ker nel To build without a kernel use the nokerne command line switch or uncheck the Use boot kernel option on the Kernel page of the Project Options dialog box VisualDSP includes three distinct kernel programs for each Tiger SHARC processor A boot kernel is loaded at reset into a memory segment seg_ldr which is defined in the ADSP TSxxx_Loader 1df file The provided files are located in the lt isntal _path gt TS 1df directory Table 7 1 TigerSHARC Boot Kernel Source Files PROM Boot Kernel Host Boot Kernel Link Port Boot Kernel Ts101_prom asm Ts101_host asm Ts101_link asm Ts201_prom asm Ts201_host asm Ts201_link asm Ts202_prom asm Ts202_host asm Ts202_link asm Ts203_prom asm Ts203_host asm Ts203_link asm 7 4 VisualDSP 5 0 Loader and Utilities Manual Loader for TigerSHARC Processors Boot Kemel Modification For most systems some customization of the boot kernel is required The operation of other tools notably the C C compiler is
134. Use the Additional Options box to enter options that have no dialog box equivalent Option settings on the Load page correspond to switches displayed on the command line For detailed information about the ADSP 2106x 21160 processor loader property page refer to the VisualDSP online help These sections describe how to produce a bootable loader 1dr file e Using ADSP 2106x 21160 Loader Command Line on page 4 26 e Using VisualDSP Interface Load Page on page 4 32 VisualDSP 5 0 Loader and Utilities Manual 4 25 ADSP 2106x 21160 Processor Loader Guide Using ADSP 2106x 21160 Loader Command Line Use the following syntax for the SHARC loader command line elfloader inputfile proc part_number switch switch where e inputfile Name of the executable dxe file to be processed into a single boot loadable file An input file name can include the drive and directory Enclose long file names within straight quotes long file name e proc part_number Part number of the processor for example proc ADSP 21062 for which the loadable file is built The proc switch is mandatory e switch One or more optional switches to process Switches select operations and boot modes for the loader utility A list of all switches and their descriptions appear in Table 4 15 on page 4 28 Command line switches are not case sensitive and placed on the command line in any order The following command line
135. Using Command Lines 6 21 Logder File Te guirrucenenraciir kin N 6 21 VisualDSP 5 0 Loader and Utilities Manual ix CONTENTS ADSP 2126x 2136x 2137x 2146x Processors Interrupt Vector I aaa carter cheese aed oes ee 6 22 ADSP 2126x 2136x 2137x 2146x Processor Boot Streams 6 23 ADSP 2126x 2136x 2137x 2146x Processor Block Tags 6 23 INIT LAS Blocks crocs tee emer ere ee ee 6 26 INIT LG Blocks siscaccscassecciaasvessavessavsanessatvatevarsecseverses 6 27 AT Tule Ble lee anO 6 28 FINAL INIT Blocks acca cccusenetncenccesacunnnssxedmcntusedsbenwnseves 6 28 ADSP 2136x 2137x 2146x Multi Application Multi DXE Manapem nt crosnieri nnie eee 6 33 ADSP 2126x 2136x 2137x 2146x Processors Compression SW DOU wis atanaivins ine aiak ae Aa aa 6 35 Compressed SErEATIS cicaiaidsciisqancdeeaakpuiscinseniaaanaviaaneeians 6 36 Compressed Block Fledder crniecncmccreonennraosris 6 37 Uncompressed SUCOS sprei O 6 38 tveilay Compreso serrrdrsnirink n E EE 6 39 Booting Compressed NORRIE acessem 6 39 Decompression Kernel File cnririntsrunrdninknkiikiiri ates 6 40 ADSP 2126x 2136x 2137x 2146x Processor Loader Guide 6 41 Using ADSP 2126x 2136x 2137x 2146x Loader Command Lit cinema 6 42 File SOc E E E E E E E E E A 6 43 File Extensions sername aia ARAE NNSA 6 43 Loader Command Line Switches ssrssniriaredsnidinsr 6 44 Using VisualDSP Interface Load Page cinccsniinsioiass 6 49 x VisualDSP 5 0 Loader and Utilities Manual
136. Visu alDSP Project Options dialog box modify the default options on the Project Split page also called splitter property page Click OK to save the selections Selecting Build Project from the Project menu invokes the splitter utility to build a non bootable PROM image file Splitter operation relies on splitter options which control the processing of the executable files into output files The page buttons and fields corre spond to the splitter utility s command line switches and parameters see Table 8 2 on page 8 5 Use the Additional Options box to enter options that do not have dialog box equivalents Refer to VisualDSP online Help for details VisualDSP 5 0 Loader and Utilities Manual 8 9 VisualDSP Interface Split Page 8 10 VisualDSP 5 0 Loader and Utilities Manual A FILE FORMATS VisualDSP development tools support many file formats in some cases several for each development tool This appendix describes file formats that are prepared as inputs and produced as outputs The appendix describes three types of files e Source Files on page A 1 e Build Files on page A 4 e Debugger Files on page A 15 Most of the development tools use industry standard file formats These formats are described in Format References on page A 16 Source Files This section describes the following source input file formats e C C Source Files on page A 2 e Assembly Source Files o
137. a warning if the vector address 0x80004 for the ADSP 2126x processors 0x90004 for the ADSP 2136x 2137x 2146x processors does not contain NOP or IDLE When using VisualDSP to create the loader file specify the name of the customized boot kernel executable in the Kernel file box on the Load page of the Project Options dialog box ADSP 2126x 2136x 2137x 2146x Processors Interrupt Vector Table If the ADSP 2126x ADSP 2136x ADSP 2137x or ADSP 2146x proces sor is booted from an external source PROM or SPI boot modes the interrupt vector table is located in internal memory 0x80000 0x800FF for the ADSP 2126x processors 0x90000 0x900FF for the ADSP 2136x 2137x 2146x processors If the processor is not booted and executes from external memory no boot mode the vector table must be located in external memory The IIVT bit in the SYSCTL control register can be used to override the booting mode when determining the location of the interrupt vector table If the processor is not booted no boot mode setting IIVT to 1 selects an internal vector table and setting I1VT 0 selects an external vector table If the processor is booted from an external source any boot mode other than no boot IIVT has no effect The default initialization value of I IVT is zero 6 22 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2126x 2136x 2137x 2146x SHARC Processors ADSP 2126x 2136x 2137x 2146x Proc essor Boot Steams The l
138. able is located If the processor is not booted no boot mode setting IIVT to 1 selects an internal vector table and setting I1VT to 0 selects an external vector table If the processor is booted from an external source any mode other than no boot mode IIVT has no effect The I1VT default initialization value Is 0 4 22 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2106x 21160 SHARC Processors Refer to EE 56 Tips amp Tricks on the ADSP 2106x EPROM and HOST bootloader EE 189 Link Port Tips and Tricks for ADSP 2106x and ADSP 2116x and EE 77 SHARC Link Port Booting on the Analog Devices Web site for more information ADSP 2106x 21160 Mult Application Mult DXE Management Currently the loader utility generates single processor loader files for host and link port boot modes As a result the loader utility supports multipro cessor EPROM boot mode only The application code must be modified for a multiprocessor system boot in host and link port modes The loader utility can produce boot loadable files that permit the ADSP 2106x 21160 SHARC processors in a multiprocessor system to boot from a single EPROM In such a system the BMS signals from each SHARC processor are 0R ed together to drive the chip select pin of the EPROM Each processor boots in turn according to its priority When the last processor finishes booting it must inform the processors to begin program execution Besides taking turns whe
139. address 0x000000DD Third word Tag of data block type The boot kernel examines the tag to determine the type of data or instruc tion being loaded Table 5 8 lists the ADSP 21161N processor block tags Table 5 8 ADSP 21161N Processor Block Tags Tag Number Block Type Tag Number Block Type 0x0000 final init 0x000E init pm48 0x0001 zero dm16 0x000F zero dm64 0x0002 zero dm32 0x0010 init dm64 0x0003 zero dm40 0x0012 init pm64 0x0004 init dml6 0x0013 init pm8 ext 0x0005 init dm32 0x0014 init pm16 ext VisualDSP 5 0 Loader and Utilities Manual 5 17 ADSP 21161 Proc essor Booting Table 5 8 ADSP 21161N Processor Block Tags Contd Tag Number Block Type Tag Number Block Type 0x0007 zero pml6 0x0015 init pm32 ext 0x0008 zero pm32 0x0016 init pm48 ext 0x0009 zero pm40 0x0017 zero pm8 ext Ox000A zero pm48 0x0018 zero pml6 ext 0x000B init pm16 0x0019 zero pm32 ext 0x000C init pm32 0x001A zero pm48 ext 0x0011 zero pm64 Boot Kemel Modification and Loader Issues Some systems require boot kernel customization In addition the opera tion of other tools such as the C C compiler is influenced by whether the loader utility is used If you do not specify a boot kernel file via the Load page of the Project Options dialog box in VisualDSP or via the l kernelfile
140. ader operations specific to the ADSP BF51x BF52x BF54x Blackfin processors are detailed in the following sections e ADSP BF51x BF52x BF54x Processor Booting on page 2 2 Provides general information on various boot modes including information on second stage kernels e ADSP BF51x BF52x BF54x Processor Loader Guide on page 2 5 Provides reference information on the loader utility s com mand line syntax and switches VisualDSP 5 0 Loader and Utilities Manual 2 1 ADSP BF51x BF52x BF54x Proc essor Booting ADSP BF51x BF52x BF54x Proc essor Booting Table 2 1 lists the part numbers that currently comprise the ADSP BF51x BF52x BF54x families of Blackfin processors Future releases of VisualDSP may support additional processors Upon reset an ADSP BF51x BF52x BF54x processor starts fetching and executing instructions from the on chip boot ROM at address 0xEF00 0000 The boot ROM is an on chip read only memory that holds a boot kernel program to load data from an external memory or host device The boot ROM details can be found in the corresponding Blackfin Processor Hardware Reference Table 2 1 ADSP BF51x BF52x BF54x Part Numbers Processor Family Part Numbers ADSP BF518 ADSP BF512 ADSP BF514 ADSP BF516 ADSP BF518 ADSP BF526 ADSP BF522 ADSP BF524 ADSP BF526 ADSP BF527 ADSP BF523 ADSP BF525 ADSP BF527 ADSP BF548 ADSP BF542 ADSP BF544 ADSP BF547 ADSP BF548 ADSP BF549 AD
141. also called loader property page Click OK to save the selections Selecting Build Project from the Project menu generates a loader file For information relative to a specific processor refer to the VisualDSP online help for that processor VisualDSP invokes the elfloader utility to build the output file The Load page buttons and fields correspond to loader command line switches and parameters see Table 5 10 on page 5 28 Use the Additional Options box to enter options that do not have dialog box equivalents 5 32 VisualDSP 5 0 Loader and Utilities Manual 6 LOADER FOR ADSP 2126X 2136X 2137X 2146X SHARC PROCESSORS This chapter explains how the loader utility e floader exe is used to convert executable dxe files into boot loadable files for the ADSP 2126x ADSP 2136x ADSP 2137x and ADSP 2146x SHARC processors Refer to Introduction on page 1 1 for the loader utility overview the introductory material applies to all processor families Refer to Loader for ADSP 2106x 21160 SHARC Processors on page 4 1 for information about the ADSP 21060 ADSP 21061 ADSP 21062 ADSP 21065L and ADSP 21160 processors Refer to Loader for ADSP 21161 SHARC Processors on page 5 1 for information about the ADSP 21161 processors Loader operations specific to the ADSP 2126x 2136x 2137x 2146x SHARC processors are detailed in the following sections e ADSP 2126x 2136x 2137x 2146x Processor Booting Provides
142. am character eight bits data 1 start bit 1 stop bit no parity bit on the RXD pin to determine the bit rate It then replies with an acknowledgement that is composed of 4 bytes 0xBF the value of UART_DLL the value of UART_DLH and 0x00 The host can then download the boot stream When the processor needs to hold off the host it deasserts CTS Therefore the host must monitor this signal Boot from serial TWI memory EEPROM flash the Blackfin processor operates in master mode and selects the TWI slave with the unique ID 0x40 It submits successive read commands to the memory device starting at two byte internal address 0x0000 and begins clocking data into the processor The TWI memory device should comply with Philips I C Bus Specification version 2 1 and have the capability to auto increment its internal address counter such that the contents of the memory device can be read sequentially Boot from TWI host the TWI host agent selects the slave with the unique ID 0x5F The processor replies with an acknowledge ment and the host can then download the boot stream The TWI host agent should comply with Philips I C Bus Specification ver sion 2 1 An IC multiplexer can be used to select one processor at a time when booting multiple processors from a single TWI To augment the boot modes a secondary software loader can be added to provide additional booting mechanisms The secondary loader could pro vide the capability to boot
143. and Using COFF by O Reilly amp Associates Newton MA 1993 Executable and Linkable Format ELF V1 1 from the Portable Formats Specification V1 1 Tools Interface Standards TIS Committee Go to http developer intel com vtune tis htm 1993 Debugging Information Format DWARF V1 1 from the Portable Formats Specification V1 1 UNIX International Inc Go to http developer intel com vtune tis htm 2001 2005 uClinux BFLT Binary Flat Format by Craig Peacock from the beyondlogic org Go to http www beyondlogic org uClinux bflt htm VisualDSP 5 0 Loader and Utilities Manual B UTILITIES The VisualDSP development software includes several utility programs some of which run from a command line only This appendix describes the following utilities e hexutil Hex 32 to S Record File Converter on page B 2 e elf2flt ELF to BFLT File Converter on page B 3 e flrdump BFLT File Dumper on page B 4 Other VisualDSP utilities for example the ELF file dumper are described in the VisualDSP 5 0 Linker and Utilities Manual or online Help VisualDSP 5 0 Loader and Utilities Manual B 1 hexutil Hex 32 to S Record File Converter hexutil Hex 32 to S Record File Converter The hex to S file converter hexutil exe utility transforms a loader 1dr file in Intel hexadecimal 32 bit format to Motorola S record format or produces an unformatted data file Syntax thexutil i
144. anual 2 11 ADSP BF51x BF52x BF54x Processor Loader Guide Table 2 5 ADSP BF51x BF52x BF54x Loader Command Line Switch Summary Contd Switch Description kb flash The kb flash prom spimaster spislave UART TWImas kb prom ter TWIslave FIFO otp nand switch specifies the boot mode kb spimaster flash PROM SPI master SPI slave UART TWI master TWI kb spislave slave or FIFO OTP NAND and SDRAM DDR for the initial kb UART ization code and or boot kernel output file if two output loader kb TWImaster files are selected kb TWIslave kb FIFO The kb switch must be used in conjunction with kb otp the 02 switch kb nand If the kb switch is absent from the command line the loader util ity generates the file for the init and or boot kernel code in the same boot mode as used to output the user application program kf hex The kf hex ascii binary include switch specifies the kf ascii output file format hex ASCII binary include for the initializa kf binary tion and or boot kernel code if two output files from the loader kf include utility are selected one file for the init code and or boot kernel and one file for user application code The kf switch must be used in conjunction with the 02 switch If kf is absent from the command line the loader utility gener ates the file for the initialization and or boot kernel code in the same format as for the user appl
145. anual 3 51 ADSP BF53x BF561 Proc essor Booting dow size specifies to the compression engine a number of bytes taken from the window during the compression The window size is the 2 s exponen tial value As mentioned before the compression decompression mechanism for Blackfin processors utilizes the open source lossless data compression library zLib1 The zLib1 deflate algorithm in turn is a combination of a variation of Huffman coding and LZ77 compression algorithms LZ77 compression works by finding sequences of data that are repeated within a sliding window As expected with a larger sliding window the compression algorithm is able to find more repeating sequences of data resulting in higher compression ratios However technical limitations of the zLib1 decompression algorithm dictate that the window size of the decompressor must be the same as the window size of the compressor For a more detailed technical explanation of the compression decompression implementation on a Blackfin processor refer to the readme txt file in the lt install_path gt Blackfin ldr zlib sre directory of VisualDSP It is not recommended to use memory ranges used by the zlib ker nel The memory ranges used by the kernel such as heap and static data are defined in the LDF file for example in lt install_path gt Blackfin ldr zlib src blkfin_zlib_init ldf of VisualDSP 5 0 In the Blackfin implementation the decompressor is part of the decom pr
146. aster 10 EPROM boot via the parallel port bprom 11 Internal boot not available on all Does not use the loader utility ADSP 2126x processors 6 4 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2126x 2136x 2137x 2146x SHARC Processors Table 6 2 ADSP 2146x Boot Mode Pins BOOT_CFG 2 0 Boot Mode Boot Mode Selection 000 SPI slave bspislave 001 SPI master SPI flash SPI PROM ora bspiflash host processor via SPI master mode bspiprom bspimaster 010 AMI user boot for 8 bit flash memory bprom boot 011 Reserved N A 100 Link port 0 boot blink 101 Reserved N A ADSP 2126x 2136x 2137x 2146x Processors Boot Modes The following sections describe the ADSP 2126x 2136x 2137x 2146x processor boot types e PROM Boot Mode on page 6 5 e SPI Port Boot Modes on page 6 7 e Internal Boot Mode on page 6 17 PROM Boot Mode The ADSP 2126x 2136x 2137x 2146x processors support an 8 bit boot mode through the parallel port This mode is used to boot from external 8 bit wide memory devices The processor is configured for 8 bit boot mode when the BOOT_CFG1 0 pins 10 orB00T_CFG2 0 pins 010 When configured for parallel booting the parallel port transfers occur with the default bit settings for the PPCTL register shown in Table 6 3 VisualDSP 5 0 Loader and Utilities Manual 6 5 ADSP 2126x 2136x 2137x 2146x Proc essor Booting Table 6 3 PPCTL Re
147. aster to prepare a boot loadable file for the specified boot mode Valid b spislave boot modes include flash PROM SPI master SPI slave UART b TWImaster TWI master TWI slave FIFO OTP NAND and b TWIslave SDRAM DDR b UART b FIFO If b does not appear on the command line the default is b OTP b flash b NAND CRC32 polynomial The CRC32 polynomial coefficient switch directs the loader utility to generate CRC32 checksum Use a polynomial coefficient if specified otherwise use default 0xD8018001 This switch inserts an initcode boot block that calls an initializa tion routine residing in the on chip boot ROM The argument field of the boot block provides the used polynomial The loader utility calculates the CRC checksum for all subsequent data blocks and stores the result in the block header s argument field The CRC32 checksum is not performed by the ADSP BF52x boot kernel 2 8 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF51x BF52x BF54x Blac kfin Proc essors Table 2 5 ADSP BF51x BF52x BF54x Loader Command Line Switch Summary Contd Switch Description callback sym symbol Larg const32 The callback switch takes a sym symbol no spaces assign ment The switch directs the loader utility to isolate the named subrou tine into a separate block set the block header s BF LAG_CALLBACK flag and fill in the block header s argument field wi
148. ation errata Notation Conventions Text conventions used in this manual are identified and described as fol lows Additional conventions which apply only to specific chapters may appear throughout this document xviii VisualDSP 5 0 Loader and Utilities Manual CONTENTS Example Description Close command File menu Titles in reference sections indicate the location of an item within the VisualDSP environment s menu system for example the Close com mand appears on the File menu this that Alternative required items in syntax descriptions appear within curly brackets and separated by vertical bars read the example as this or that One or the other is required this that Optional items in syntax descriptions appear within brackets and sepa rated by vertical bars read the example as an optional this or that this Optional item lists in syntax descriptions appear within brackets delim ited by commas and terminated with an ellipse read the example as an optional comma separated list of this SECTION Commands directives keywords and feature names are in text with letter gothic font filename Non keyword placeholders appear in text with italic style format Note For correct operation A Note provides supplementary information on a related topic In the online version of this book the word Note appears instead of this symbol Caution Incorrect device
149. bens 5 24 Using ADSP 21161 Loader Command Line ssssisscecsnsnis 5 25 File Searches sacsrronaniiin an A AS 5 27 viii VisualDSP 5 0 Loader and Utilities Manual CONTENTS File Extensions ccc ssseccsseeccsccccceececsteceaececeececssceeneseeeas 5 27 Loader Command Line Switches lt cc jcisessceseseaccasascasessarssenes 5 28 Using VisualDSP Interface Load Page sccncscssiesssoswwenssvonnse 5 32 LOADER FOR ADSP 2126X 2136X 2137X 2146X SHARC PROCESSORS ADSP 2126x 2136x 2137x 2146x Processor Booting nesese 6 2 Power Up Booting Process aursoriniinedkiniiati iaoiai 6 3 Boot Mode Selection serene ee ee 6 4 ADSP 2126x 2136x 2137x 2146x Processors Boot Modes 6 5 PROM Boot Mod crrsrasairni irad a 6 5 Packing Options for External Memory siscciciareseseanicraccenss 6 7 Packing and Padding Details ssrscrcrcninirisiniatetaneis 6 7 SPI Port Boot Modes gu siciioiciasiatniitiieaudonnaieaeiind 6 7 SPI Sae Boor Mode astern ran nR 6 8 SPI Master Boot Modes sssnniossncsnssiesrenroninness 6 10 Routing Fror an SPL Pie concn aapesnsinns 6 16 Booting From an SPI PROM 16 bit address 1 0 6 16 Booting From an SPI Host Processor sarsivsvernsiasisas 6 17 Ioternal Boot Meade sainarsccatninorniiani iania 6 17 ADSP 2126x 2136x 2137x 2146x Processors Boot Kernels 6 19 Boot Kernel Modification and Loader Issues 0000 6 20 Rebuildmg a Boot Kernel File ass ccsecacssiatcavsssatdasadealsaesasses 6 20 Rebuilding a Boot Kernel
150. bler and Preprocessor Manual Assembly Initialization Data Files Assembly initialization data files dat are text files that contain fixed or floating point data These files provide initialization data for an assembler VAR directive or serve in other tool operations l With and without built in function support a minimal differentiator There are others dialects A 2 VisualDSP 5 0 Loader and Utilities Manual File Formats When a VAR directive uses a dat file for data initialization the assembler reads the data file and initializes the buffer in the output object file doj Data files have one data value per line and may have any number of lines The dat extension is explanatory or mnemonic A directive to Hinclude lt filename gt can take any file name and extension as an argument Fixed point values integers in data files may be signed and they may be decimal hexadecimal octal or binary based values The assembler uses the prefix conventions listed in Table A 1 to distinguish between numeric formats For all numeric bases the assembler uses words of different sizes for data storage The word size varies by the processor family Table A 1 Numeric Formats Convention Description Oxnumber Hexadecimal number H fnumber hifnumber number Decimal number Di tnumber d tnumber B number Binary number bifnumber O number Octal number of number Header Files Header
151. blocks are placed at the top of a loader file They are executed before the rest of the code in the loader file booted into the memory see Figure 3 4 ADSP BF531 32 33 34 36 37 39 39 Processor PROM FLASH OR SPI DEVICE INIT BLOCK HEADER INIT BLOCKS L1 BLOCK HEADER L1 BLOCK SDRAM BLOCK HEADER APP CODE DATA SDRAM BLOCK BLOCK N 10 BYTE HEADER BLOCK N Figure 3 4 ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 Processors Initialization Block Execution Following execution of the initialization blocks the boot process continues with the rest of data blocks until it encounters a final block see Figure 3 5 The initialization code example follows in Listing 3 1 on page 3 14 VisualDSP 5 0 Loader and Utilities Manual 3 13 ADSP BF53x BF561 Proc essor Booting ADSP BF531 32 33 34 36 37 39 39 Processor ARATE enowerash on se DEVICE L1 Momoty Init Block INIT BLOCK HEADER gae Block E INIT BLOCKS L1 BLOCK HEADER L1 BLOCK SDRAM BLOCK HEADER APP CODE DATA SDRAM BLOCK BLOCK N 10 BYTE HEADER BLOCK N SDRAM SDRAM Block Figure 3 5 ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 Processors Booting Application Code Listing 3 1 Initialization Block Code Example This file contains 3 sections 1 A Pre Init Section this section saves off all the processor registers onto the stack
152. boot streams 3 11 proc part_number loader switch for Blackfin 2 15 3 67 loader switch for SHARC 4 30 5 30 6 47 loader switch for TigerSHARC 7 9 7 10 splitter switch 8 7 program counter settings ADSP 2106x 160 processors 4 12 program development flow 1 7 program memory sections splitter 8 3 8 5 Project Options dialog box 1 12 2 5 2 18 2 19 3 57 3 72 3 73 6 20 7 4 7 5 PROM boot mode introduction to 1 14 downloading boot loadable files 1 10 memory devices 6 16 A 6 PROM boot mode ADSP 2126x 36x 37x 46x processors 6 5 6 21 6 29 PROM boot mode TigersHARC processors 7 4 7 9 INDEX PROM flash boot mode Blackfin processors ADSP 535 processors 3 62 ADSP BF531 2 3 4 6 7 8 9 processors 3 4 3 48 ADSP BF535 processors 3 21 3 28 3 29 3 34 ADSP BF561 processors 3 43 3 48 PROM image files creating from command line 8 2 creating from GUI 8 9 ignoring ROM sections 8 5 specifying format 8 6 specifying name 8 5 specifying width 8 6 pull up resistors 5 7 Px register 4 19 6 30 Q quickboot loader switch for Blackfin 2 15 R r splitter switch 8 6 ram splitter switch 8 5 8 6 RBAM bit 5 7 RBWS bit 5 7 RD pin 4 10 5 8 readall loader switch for Blackfin 2 15 references file formats A 16 RESET interrupt service routine 3 7 3 23 3 37 5 12 pin 4 9 5 8 5 11 7 3 VisualDSP 5 0 Loader and Utilities Manual I 13 INDEX reset processor intro
153. buttons and fields correspond to command line switches and parameters see Table 6 18 on page 6 44 Use the Additional Options box to enter options that have no dialog box equivalent VisualDSP 5 0 Loader and Utilities Manual 6 49 ADSP 2126x 2136x 2137x 2146x Proc essor Loader Guide 6 50 VisualDSP 5 0 Loader and Utilities Manual 7 LOADER FOR TIGERSHARC PROC ESSO RS This chapter explains how the loader utility e floader exe is used to convert executable dxe files into boot loadable or non bootable files for the ADSP TSxxx TigerSHARC processors Refer to Introduction on page 1 1 for the loader utility s overview the introductory material applies to all processor families Loader operations specific to the ADSP TSxxx TigerSHARC processors are detailed in the following sections e TigerSHARC Processor Booting on page 7 2 Provides general information on various booting modes including information on boot kernels e TigerSHARC Loader Guide on page 7 5 Provides reference information on the loader utility s com mand line syntax and switches Refer to the processor s data sheet and hardware reference manual for more information on system configuration peripherals registers and operating modes VisualDSP 5 0 Loader and Utilities Manual 7 1 TigerSHARC Processor Booting TigerSHARC Processor Booting At chip reset a TigerSsHARC processor loads bootstraps a 256 instruc tion p
154. c ADSP BF531 for which the loadable file is built Provide a processor part number for every input dxe if designing multipro cessor systems e switch One or more optional switches to process Switches select operations and modes for the loader utility Command line switches may be placed on the command line in any order except the order of input files for a multi input system For a multi input system the loader utility processes the input files in the order presented on the command line 3 58 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Proc essors File Searches File searches are important in loader processing The loader utility sup ports relative and absolute directory names default directories and user selected directories for file search paths File searches occur as described on page 1 17 File Extensions Some loader switches take a file name as an optional parameter Table 3 9 lists the expected file types names and extensions Table 3 9 File Extensions Extension File Description dxe Loader input files boot kernel files and initialization files ldr Loader output file kn Loader output files containing kernel code only when two output files are selected In some cases the loader utility expects the overlay input files with the file extension of ov1 shared memory input files with the extension of sm or both but d
155. cesses executable files You select features such as boot modes boot kernels and output file formats via the loader options These options are specified on the loader utility s command line or via the Load page of the Project Options dialog box in the VisualDSP environment The Load page consists of multiple panes For information specific to the ADSP 2126x 2136x 2137x 2146x processor refer to the VisualDSP online help for that processor When you open the Load page the default loader settings for the selected processor are already set Use the Addi tional Options box to enter options that have no dialog box equivalent Option settings on the Load page correspond to switches displayed on the command line These sections describe how to produce a bootable loader file 1dr e Using ADSP 2126x 2136x 2137x 2146x Loader Command Line on page 6 42 e Using VisualDSP Interface Load Page on page 6 49 VisualDSP 5 0 Loader and Utilities Manual 6 41 ADSP 2126x 2136x 2137x 2146x Proc essor Loader Guide Using ADSP 2126x 2136x 2137x 2146x Loader Command Line Use the following syntax for the SHARC loader command line elfloader inputfile proc processor switch switch where e inputfile Name of the executable file dxe to be processed into a single boot loadable file An input file name can include the drive and directory Enclose long file names within straight quotes long file name e pr
156. cessor ID to select the code for each processor Sequential EPROM Boot Set the EBOOT pin of the processor with ID of 1 high for EPROM boot ing The other processors should be configured for host boot EB00T 0 LBOOT 0 and BMS 1 leaving them in the idle state at startup and allowing the processor with 1D 1 to become bus master and boot itself Connect the BMS pin of processor 1 only to the EPROM s chip select pin When processor 1 has finished booting it can boot the remaining processors by writing to their external port DMA buffer 0 P80 via the multiprocessor memory space 5 22 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 21161 SHARC Processors Processor ID Numbers A single processor system requires only one input dxe file without any prefix and suffix to the input file name for example elfloader proc ADSP 21161 bprom Input dxe A multiprocessor system requires a distinct processor ID number for each input file on the command line A processor ID is provided via the i dftexe fi ename dxe switch where is 1 to 6 In the following example the loader utility processes the input file Input1 dxe for the processor with an ID of 1 and the input file Input2 dxe for the processor with an ID of 2 elfloader proc ADSP 21161 bprom idlexe Inputl dxe id2exe Input2 dxe If the executable for the processor is identical to the executable of the n processor the output loader file contains only one c
157. cessor and loads boot data After the boot kernel finishes initializing the rest of the system the boot kernel loads boot data over itself with a final DMA transfer Table 6 11 lists the ADSP 2126x 2136x 2137x 2146x boot kernels shipped with VisualDSP Table 6 11 ADSP 2126x 2136x 2137x 2146x Default Boot Kernel Files Processor PROM SPI Slave SPI Flash SPI Master Link Port Boot SPI PROM ADSP 2126x 26x_prom dxe 26x_spi dxe N A ADSP 21362 36x_prom dxe 36x_spi dxe N A ADSP 21363 ADSP 21364 ADSP 21365 ADSP 21366 ADSP 21367 369_prom dxe 369_spi dxe N A ADSP 21368 ADSP 21369 ADSP 2137x 375_prom dxe 375_spi dxe N A ADSP 21462 469_prom dxe 469_spi dxe 469_link dxe ADSP 21465 ADSP 21467 ADSP 21469 VisualDSP 5 0 Loader and Utilities Manual 6 19 ADSP 2126x 2136x 2137x 2146x Proc essor Booting At processor reset a boot kernel is loaded into the seg_ldr memory seg ment as defined in the Linker Description File for the default loader kernel that corresponds to the target processor for example 2126x_ldr 1df which is stored in the lt isntal l_path gt ldr VisualDSP directory of the target processor Boot Kemel Modification and Loader Issues Boot kernel customization is required for some systems In addition the operation of other tools such as the C C compiler is influenced by whether the loader utility is used If you do not specify a boot kernel file via t
158. ch for Blackfin 2 13 2 14 3 64 3 65 make files 2 13 2 14 3 64 3 65 map memory map files A 6 maskaddr loader switch for Blackfin 2 13 3 64 masking EPROM address bits 2 13 3 64 master host boot introduction to 1 10 MaxBlockSize loader switch for Blackfin 2 13 3 64 MaxFillBlockSize loader switch for Blackfin 2 13 MaxZeroFillBlockSize loader switch for Blackfin 3 65 memory map files map A 6 memory ranges Blackfin processors ADSP BF531 2 3 4 6 7 8 9 processors 3 19 ADSP BF535 processors 3 33 ADSP BF561 processors 3 45 microcontroller data transfers A 12 MM loader switch for Blackfin 2 14 3 65 MODE register 4 13 MODE2 register 4 13 4 14 INDEX Mo filename loader switch for Blackfin 2 14 3 65 most significant bit first MSB format 6 12 Motorola S record file format 7 9 A 10 MSBF bit 6 9 6 10 MS bit 6 9 6 10 MSWF register 5 7 5 11 Mt filename loader switch for Blackfin 2 14 3 65 Multi 2 17 multiprocessor booting introduction to 1 10 multiprocessor systems Blackfin processors 2 17 3 47 See also dual core systems multiprocessor systems SHARC processors ADSP 2106x 21160 processors 4 23 4 24 ADSP 21161 processors 5 7 5 21 5 22 5 23 ADSP 2136x 37x processors 6 33 multiprocessor systems TigerSsHARC processors 7 6 7 9 N NAND flash boot mode ADSP BF52x 54x processors 2 4 no2kernel loader switch for Blackfin 3 65 no boot mode introductio
159. command line switch the loader utility places a default boot kernel in the loader output file see ADSP 21161 Processor Boot Kernels on page 5 16 based on the specified boot mode Rebuilding a Boot Kernel File If you modify the boot kernel source asm file by inserting correct values for your system you must rebuild the boot kernel dxe before generating the boot loadable 1ar file The boot kernel source file contains default values for the SYSCON register The WAIT SDCTL and SDRDIV initialization code is in the boot kernel file comments 5 18 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 21161 SHARC Processors To Modify a Boot Kernel Source File 1 Copy the applicable boot kernel source file 161_link asm 161_host asm 161_prom asm or 161_spi asm 2 Apply the appropriate initializations of the SYSCON and WAIT registers After modifying the boot kernel source file rebuild the boot kernel dxe file Do this from the VisualDSP IDDE refer to VisualDSP online Help for details or rebuild the boot kernel file from the command line Rebuilding a Boot Kernel Using Command Lines Rebuild a boot kernel using command lines as follows EPROM Boot The default boot kernel source file for EPROM booting is 161_prom asm After copying the default file to my_prom asm and modify ing it to suit your system use the following command lines to rebuild the boot kernel easm2lk proc ADSP 21161 my_pro
160. command line switches and parameters see Table 7 3 on page 7 9 Use the Additional Options box to enter options that have no dialog box equivalent 7 12 VisualDSP 5 0 Loader and Utilities Manual 3 SPLITTER FOR SHARC AND TIGERSHARC PROCESSORS This chapter explains how the splitter utility e1 fsp121k exe is used to convert executable dxe files into non bootable files for the ADSP 21xxx SHARC and ADSP TSxxx TigerSHARC processors Non bootable PROM image files execute from external memory of a processor For Tig erSHARC processors the splitter utility creates a 32 bit image file For SHARC processors the utility creates a 64 48 40 32 bit image file or an image file to match a physical memory size For SHARC processors the splitter utility also properly packs the external memory data or code to match the specified external memory widths if the logical width of the data or code is different from that of the physical memory In most instances developers working with SHARC and TigerSHARC processor use the loader utility instead of the splitter One of the excep tions is a SHARC system that can execute instructions from external memory The non bootable PROM image files are often used with the ADSP 21065L processor systems which have limited internal memory Refer to Introduction on page 1 1 for the splitter utility overview the introductory material applies to both processor families VisualDSP 5 0 Loader and U
161. ction is pre sented as three 16 bit hexadecimal numbers For each 48 bit instruction the data order is lower middle and then upper 16 bits Example lines from an include format file are 0x005c 0x0620 0x0620 0x0045 0x1103 0x1103 Ox00c2 Ox06be Ox06be This example shows how to include this file in a C program const unsigned loader_file include foo ldr bs const unsigned loader_file_count sizeof loader_file sizeof loader_file 0 The loader_file_count reflects the actual number of elements in the array and cannot be used to process the data Loader Output Files in Binary Format The loader utility can output binary format files 1dr to support a vari ety of PROM and microcontroller storage applications VisualDSP 5 0 Loader and Utilities Manual A 9 Build Files Binary format files use less space than the other loader file formats Binary files have the same contents as the corresponding ASCII file but in binary format Output Files in Motorola S Record Format The loader and splitter utilities can output Motorola S record format files s_ which conform to the Intel standard The three file formats sup ported by the loader and PROM splitter utilities differ only in the width of the address field S1 16 bits S2 24 bits or 3 32 bits An S record file begins with a header record and ends with a termination record Between these two records are data records one per line S00
162. d change the project s target type from Executable file to Loader File Loader utility operations depend on the loader options which control how the loader utility processes executable files into boot loadable files letting you select features such as kernels boot modes and output file for mats These options are set on the Load pages of the Project Options dialog box in the IDDE or on the loader command line Option settings on the Load pages correspond to switches typed on the el floader exe command line Splitter Utility Operations Splitter utility operations depend on the splitter options which control how the splitter utility processes executable files into non bootable files e For Blackfin processor the loader utility includes the ROM splitter capabilities invoked through the Project Options dialog box Refer to Using VisualDSP ROM Splitter on page 3 78 Option set tings in the dialog box correspond to switches typed on the elfloader exe command line e For SHARC and TigerSHARC processors change the project s tar get type to Splitter file The splitter options are set via the Project Split page of the Project Options dialog box Refer to Splitter for 1 12 VisualDSP 5 0 Loader and Utilities Manual Introduction SHARC and TigerSHARC Processors on page 8 1 Option set tings in the dialog box correspond to switches typed on the elfsp121k exe command line Boot Modes Once an executable file is f
163. d streams 3 53 6 38 use32bitTagsforExternal Memory Blocks loader switch for SHARC 4 31 utility programs B 1 V VAR directive A 3 vector addresses 4 20 5 20 version loader switch for SHARC 4 32 5 32 6 48 loader switch for TigerSHARC 7 11 splitter switch 8 8 v verbose loader switch for Blackfin 2 16 3 68 loader switch for SHARC 4 32 5 32 6 48 loader switch for TigerSHARC 7 10 W WAIT register 4 9 4 11 4 17 4 19 5 7 5 18 6 20 waits loader switch for Blackfin 3 68 wait states 3 24 3 68 3 73 4 10 4 15 5 7 5 8 width loader switch for Blackfin 2 16 3 64 3 69 WIDTH command 6 7 WL bit 6 9 6 10 1 16 VisualDSP 5 0 Loader and Utilities Manual INDEX word width setting for loader output file 5 29 zero fill blocks SHARC processors 6 45 ADSP 2106x 160 processors 4 18 ADSP 2126x 36x 37x processors 6 25 Z zero padding ADSP 2126x 36x 37x 46x processors 6 26 6 27 zero fill blocks Blackfin processors zeroPadForced loader switch for Blackfin ADSP BF531 2 3 4 6 7 8 9 processors 3 69 3 11 3 65 ADSP BF561 processors 3 39 VisualDSP 5 0 Loader and Utilities Manual I 17
164. de Boot Kemel Modification and Loader Issues Some systems require boot kernel customization The operation of other tools such as the C C compiler is influenced by whether the boot ker nel is used When producing a boot loadable file the loader utility reads a processor executable file and uses information in it to initialize the memory How ever the loader utility cannot determine how the processor SYSCON and WAIT registers are to be configured for external memory loading in the system VisualDSP 5 0 Loader and Utilities Manual 4 19 ADSP 2106x 21160 Proc essor Booting If you modify the boot kernel by inserting values for your system you must rebuild it before generating the boot loadable file The boot kernel contains default values for SYSCON The initialization code can be found in the comments in the boot kernel source file After modifying the boot kernel source file rebuild the boot kernel dxe file Do this from the VisualDSP IDDE refer to VisualDSP online Help for details or rebuild the boot kernel file from the command line When using VisualDSP specify the name of the modified kernel executable in the Kernel file box on the Kernel page of the Project Options dialog box If you modify the boot kernel for EPROM host or link boot modes ensure that the seg_ldr memory segment is defined in the 1df file Refer to the source of the segment in the 1df file located in the lt install_path gt 21k ld
165. der Command Line Switches on page 2 8 for more information about the switches 2 18 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF51x BF52x BF54x Blac kfin Proc essors Project Options for An ADSP BF548 Based Project fey General fis Compile Eh Assemble a Fig Link fs Load ET options Eh Kernel Eh Splitter E Pre build E Post build 2 Add Startup Code LDF Boot Mode Boot Format Flash PROM UART Intel hex O SPI OTwi O ASCII O SPI Slave OFIFO O Include O Binary Use default start address C Verbose Initialization file Output Width Bit 16 bit Output file Additional options Figure 2 1 Project Load Options Page for ADSP BF548 Processors Using the page controls select or modify the load settings Table 2 6 describes each load control and corresponding setting When satisfied with the settings click OK to complete the load setup Table 2 6 Base Load Page Settings for ADSP BF51x BF52x BF54x Processors Setting Description Load Selections for the loader utility The selections are e Options default boot options this section e Kernel specification for a second stage loader see page 2 20 e Splitter specification for the no boot mode see page 2 22 Boot mode Specifies flash PROM SPI SPI slave UART TWI FIFO SDRAM DDR OTP or NAND as a boot source VisualDSP 5 0 Loader and Utilities Manual
166. der Files Without a Second Stage Loader 00 3 28 Loader Files With a Second Stage Loader c eee 3 29 Goba Fen cr cen omer eer eOe er oe ane OPe NOR I eon rere oer 3 31 Block Headers and Flagi i tssectnscdianrcrdsrcaneissvessreantancneas 3 32 ADSP BF535 Processor Memory Ranges sccccscsccouumaun 3 33 Sec ond Srage Loader Restrictions sisiccccissuearscasacorearsceonens 3 34 VisualDSP 5 0 Loader and Utilities Manual v CONTENTS ADSP BF561 Processor Booting secwesreirreisnororurress 3 35 ADSP BF561 Processor On Chip Boot ROM ecen 3 37 ADSP BF561 Processor Boot Streams susssissrironisinosirs 3 37 ADSP BF561 Processor Initialization Blocks ceeeee 3 43 ADSP BF561 Dual Core Application Management 3 44 ADSP BF561 Processor Memory Ranges ccccisrscsosisvvensrtes 3 45 ADSP BF53x and ADSP BF561 Multi Application Multi DXE a ties ncn A E A E gana 3 46 ADSP BF531 BF532 BF533 BF534 BF536 BF537 Processor Compresion CUP PO xamieudinieueieniermiunantn 3 49 Compressed REI sccncaivarsaysicavanesdaansussvennaedanauiameussseercedte 3 50 Compressed Block Headers a occcsecttesnemessuscustiemucmaredoancunss 3 31 Uncompressed Streams eed isececsiacclarce ieee 3 53 Booting Compressed Streams scsisictabiaisemensiriniabianinennion 3 54 Decompression Initialization Files scccnccnniccmerceact 3 54 ADSP BF53x BF561 Processor Loader Guide ciciciccsinessisaxcrstereeni 3 57 Using Blackfin Loader Command Line ssessesarrs
167. device submits a read command at address 0x0000 and begins clocking data into the beginning of L2 memory A 16 bit addressable SPI compatible EPROM must be used A secondary software loader is provided to augment the boot modes The secondary loader provides the capability to boot from PCI 16 bit flash memory fast flash variable baud rates and so on The ADSP BF535 Processor Second Stage Loader is detailed on page 3 24 The following ADSP BF535 topics also are discussed in this chapter e ADSP BF535 Processor Boot Streams on page 3 27 e ADSP BF535 Processor Memory Ranges on page 3 33 Refer to the ADSP BF535 Blackfin Embedded Processor data sheet and the ADSP BF535 Blackfin Processor Hardware Reference man ual for more information on system configuration peripherals registers and operating modes 3 22 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Processors ADSP BF535 Processor On Chip Boot ROM The on chip boot ROM for the ADSP BF535 processor does the follow ing Figure 3 6 ADSP BF535 Processor PROM Flash or SPI Device Figure 3 6 ADSP BF535 Processors On Chip Boot ROM 1 Sets up supervisor mode by exiting the RESET interrupt service rou tine and jumping into the lowest priority interrupt 1VG15 2 Checks whether the RESET is a software reset and if so whether to skip the entire boot sequence and jump to the start of L2 memory 0xF000 0000 f
168. directs the loader utility not to set the final block tag for the first dxe file As a result the boot process continues with code from the second dxe file following the first file Applies to the ADSP BF56x processors only VisualDSP 5 0 Loader and Utilities Manual 3 65 ADSP BF53x BF561 Processor Loader Guide Table 3 10 Blackfin Loader Command Line Switch Summary Contd Switch Description noInitCode The noInitCode switch directs the loader utility not to expect an initialization input file even though an external memory section is present in the input dxe file Applies to the ADSP BF531 BF532 BF533 ADSP BF534 BF536 BF537 BF538 BF539 proces sors only noSecondStageKernel o filename The noSecondStageKernel switch directs the loader utility not to include a default second stage kernel into the loader stream Applies to the ADSP BF56x processors only The o filename switch directs the loader utility to use the speci fied file as the name of the loader utility s output file If the file name is absent the default name is the root name of the input file with an ldr extension 02 The 02 switch produces two output files one for the init block if present and boot kernel and one for user application code To have a different format boot mode or output width from the application code output file use the kb kf kwidth switches to specify the boot mode
169. does when it encounters a compressed stream Finally the loader utility loads the uncompressed boot stream in the conventional way 3 50 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Proc essors The Figure 3 22 illustrates the structure of a compressed block COMPRESSED BLOCK HEADER COMPRESSED STREAM Figure 3 22 Compressed Block Compressed Block Headers A compressed stream always has a header followed by the payload com pressed stream Figure 3 23 shows the structure of a compressed block header 16 BITS 16 BITS PADDED BYTE COUNT SIZE OF USED COMPRESSION OF COMPRESSED STREAM WINDOW 32 BITS TOTAL BYTE COUNT OF THE COMPRESSED STREAM INCLUDING PADDED BYTES 16 BITS COMPRESSED BLOCK FLAG WORD Figure 3 23 Compressed Block Header The first 16 bits of the compressed block header hold the padded byte count of the compressed stream The loader utility always pads the byte count if the resulting compressed stream from the loader compression engine is an odd number The loader utility rounds up the byte count of the compressed stream to be a next higher even number This 16 bit value is either 0x0000 or 0x0001 The second 16 bits of the compressed block header hold the size of the compression window used by the loader compression engine The value range is 8 15 bits with the default value of 9 bits The compression win VisualDSP 5 0 Loader and Utilities M
170. duction to 1 14 1 15 ADSP 2106x 160 processors 4 3 4 8 4 11 4 12 4 16 ADSP 21161 processors 5 3 5 6 5 7 5 9 5 10 5 13 5 15 ADSP 2126x 36x 37x 46x processors 6 3 6 6 6 9 6 10 6 17 6 20 ADSP BF561 processors 3 16 3 35 3 37 3 79 Blackfin processors 2 2 3 2 3 3 3 21 3 25 dual core Blackfin processors 3 35 TigerSHARC processors 7 2 7 3 7 4 vector addresses 4 4 4 9 4 14 5 20 6 21 vector routine 3 18 3 81 5 9 resistors pull up 7 3 restrictions second stage loader 3 34 retainSecondStageKernel loader switch for SHARC 6 47 ROM memory images as ASCII text files A 14 memory sections 8 5 setting splitter options Blackfin processors 2 22 3 78 splitter See splitter romsplitter loader switch for Blackfin 2 13 2 15 3 64 3 67 Rx registers 3 43 3 48 4 13 RXSPI register 6 8 RXSR register 6 8 RXx registers 6 9 S sl Motorola EXORciser file format 7 9 8 6 A 10 s2 Motorola EXORMAX file format 7 9 8 6 A 10 s3 Motorola 32 bit file format 7 9 8 6 A 10 save section loader switch for Blackfin 2 16 scratchpad memory Blackfin processors ADSP BF535 processors 3 33 ADSP BF561 processors 3 45 SDCTL register 5 18 6 20 SDRAM DDR boot mode ADSP BF52x 54x processors 2 4 SDRAM memory ADSP 2106x 160 processors 4 17 SDRAM memory Blackfin processors ADSP BF531 2 3 4 6 7 8 9 processors 3 11 3 15 3 20 ADSP BF535 processors 3 24 3 33 3 34 ADSP BF561 processors
171. e http www beyondlogic org uClinux bflt htm Syntax fltdump switch Lobject_file where object_file is the name of the bfit file whose contents is to be printed Table B 3 shows optional switches used with the f1tdump command B 4 VisualDSP 5 0 Loader and Utilities Manual Table B 3 BFLT File Dumper Command Line Switches Utilities Switch Description D Dumps the file built for the specified processor help Prints the list of the e1fdump switches to stdout V Prints version information o file_name Prints s the output to the specified file VisualDSP 5 0 Loader and Utilities Manual B 5 fitdump BALT File Dumper B 6 VisualDSP 5 0 Loader and Utilities Manual INDEX Numerics 64 splitter switch 8 5 16 to 48 bit word packing 4 12 32 to 16 bit word packing 6 7 32 to 8 bit word packing 6 7 48 to 8 bit word packing 4 9 4 to 48 bit word packing 4 15 8 to 48 bit word packing 4 10 4 11 4 12 5 5 5 9 A ACK pin 4 8 4 11 4 13 5 7 ADDR23 0 address lines 5 8 ADDR31 0 address lines 4 10 address records linear format A 7 ADSP 2106x 160 processors ADSP 21060 061 062 boot modes 4 2 4 5 ADSP 21065L boot modes 4 2 4 6 ADSP 21160 boot modes 4 2 4 5 boot sequence 4 3 direct memory access See DMA DMACx ADSP 21161 processors boot modes 5 2 5 5 boot sequence 5 3 direct memory access See DMA DMACx multiprocessor supp
172. e hex Intel hex 32 s1 s2 s3 Motorola S records fbinary include ASCII and binary Valid formats depend on the b switch fsl boot type selection fs2 e Fora PROM boot type use a hex s1 s2 s3 include f53 binary or ASCII format e For host or link port booting use ASCII or binary formats If the f switch does not appear on the command line the default boot type format is hex for PROM and ASCII for host or link h Invokes the command line help outputs a list of command line or switches to standard output and exits By default the h switch help alone provides help for the loader driver To obtain a help screen for the target TigerSHARC processor add the proc switch to the com mand line For example type el floader proc ADSP TS101 h to obtain help for the ADSP TS101S processor id texe filename Directs the loader utility to use the processor ID number for the cor responding executable file when producing a boot loadable file for a EPROM or host boot multiprocessor system Use this switch only to produce a boot loadable file that boots multi ple processors from a single EPROM Valid are 0 1 2 3 4 5 6 and 7 Warning Do not use this switch for single processor systems For single processor systems use the executable file name as a parameter without a switch VisualDSP 5 0 Loader and Utilities Manual 7 9 TigerSHARC Loader Guide Table 7 3 TigerSHARC Loader Command Line Switche
173. e init filename dxe switch if the applica tion has an external memory section The init code file should contain the code to initialize registers for external memory initial ization o filename The o filename switch directs the loader utility to use the speci fied file as the name of the loader utility s output file If the fi 1e name is absent the default name is the root name of the input file with an 1dr extension 02 The 02 switch directs the loader utility to produce two output files one file for code from the initialization block and or boot kernel and one file for user application code To have a different format boot mode or output width for the application code output file use the kb kf kwidth switches to specify the boot mode the boot format and the boot width for the output kernel file respectively Combine 02 with 1 filename and or init filename dxe p The p switch specifies a hex flash PROM output start address for the application code A valid value is between 0x0 and 0xFFFFFFFF A specified value must be greater than that specified by kp if both kernel and or initialization and application code are in the same output file a single output file 2 14 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF51x BF52x BF54x Blac kfin Proc essors Table 2 5 ADSP BF51x BF52x BF54x Loader Command Line Switch Summary Contd Switch
174. e 6 8 ADSP 2126x 2136x 2137x 2146x Compressed Loader Stream Booting Sequence Decompression Kemel File As stated before a decompression kernel dxe file must be used when building a loader file with compressed streams The decompression kernel file has a built in decompression engine to decompress the compressed streams from the loader file A decompression kernel file can be specified from the loader property page or from the command line via the l userkernel switch VisualDSP includes the default decompression kernel files which the loader utility uses if no other kernel file is specified If building a custom decompression kernel ensure that you use the same decompression function and use the same compression window size for both the kernel and the loader utility 6 40 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2126x 2136x 2137x 2146x SHARC Processors The default decompression kernel files are stored in the lt install_path gt 2126x ldr zlib and 2136x ldr zlib directories of VisualDSP The loader utility uses the window size of 9 bits to perform the compression operation The compression window size can be changed through the loader property page or the compressWS command line switch The valid range for the window size is from 8 to 15 bits ADSP 2126x 2136x 2137x 2146x Processor Loader Guide Loader operations depend on the loader options which control how the loader utility pro
175. e boot kernel sets up the processor and loads boot data After the boot kernel finishes initializing the rest of the system the boot kernel loads boot data over itself with a final DMA transfer Four boot kernels ship with VisualDSP refer to Table 5 7 Table 5 7 ADSP 21161 Default Boot Kernel Files PROM Booting Link Booting Host Booting SPI Booting 161_prom dxe 161_link dxe 161_host dxe 161_spi dxe Boot kernels are loaded at processor reset into the seg_ldr memory seg ment which is defined in the 161_ldr 1df The file is stored in the lt install_path gt 211xx ldr directory of VisualDSP 5 16 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 21161 SHARC Processors ADSP 21161 Processor Boot Steams The loader utility produces the boot stream in blocks and inserts header words at the beginning of data blocks in the loader 1dr file The boot kernel uses header words to properly place data and instruction blocks into processor memory The header format for PROM host and link boot loader files is as follows 0x00000000DDDD OXAAAAAAAALLLL In the above example D is a data block type tag A is a block start address and L is a block word length For single processor systems the data block header has three 32 bit words in SPI boot mode as follows OxLLLLLLLL First word Data word length or data word count of the data block OxAAAAAAAA Second word Data block start
176. e booted into memory After the last block the processor jumps to the start of LI memory for application code execution When it jumps to L1 memory for code execution the processor is still in supervisor mode and in the lowest priority interrupt IVG15 Zero Fill 1 Zero Fill Block 0 No Zero Fill Block Processor Type 1 ADSP BF533 534 536 537 538 539 0 ADSP BF531 BF532 Initialization Block 1 Init Block 0 No Init Block Ignore Block 0 Default Selectable from 0 15 Bits 14 12 11 2 are reserved for future use 1 Ignore Block 0 Do Not Ignore Block Figure 3 3 Flag Bit Assignments for 2 Byte Block Flag Word Note that the ADSP BF534 BF536 BF537 processor can have a special last block if the boot mode is two wire interface TWI The loader utility saves all the data from 0xFF90 3F00 to OxFF90 3FFF and makes the last block with the data The loader utility however creates a regular last 3 12 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Processors block if no data is in that memory range The space of 0xFF90 3F00 to OxFF90 3FFF is saved for the boot ROM to use as a data buffer during a boot process ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 Initialization Blocks The init filename option directs the loader utility to produce the ini tialization blocks from the initialization section s code in the named file The initialization
177. e from 0 through 3 The default value is 3 Applies to the ADSP BF535 processors only init filename dxe The init filename dxe switch directs the loader utility to include the initialization code from the named file The loader util ity places the code from the initialization sections of the specified dxe file in the boot stream The kernel loads the code and then calls it It is the responsibility of the code to save restore state regis ters and then perform an RTS back to the kernel Does not apply to the ADSP BF535 processors 3 62 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Processors Table 3 10 Blackfin Loader Command Line Switch Summary Contd Switch Description kb prom The kb prom flash spi spislave UART TWI FIFO switch kb flash specifies the boot mode PROM flash SPI SPI slave UART TWI kb spi or FIFO for the boot kernel output file if you generate two output kb spislave files from the loader utility one for the boot kernel and another for kb UART user application code kb TWI The spislave UART and TWI parameters are applicable to the kb FIFO ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 and ADSP BF539 processors only The FIFO parameter applies to the ADSP BF534 BF536 BF537 processors of silicon revision 0 4 or newer The kb switch must be used in conjunction with the 02 switch If the kb switch is absent
178. e programs refer to ADSP 21161 Processor Boot Ker nels on page 5 16 for more information Refer to the ADSP 21161 SHARC DSP Hardware Reference for detailed information on DMA and system configurations DMA channel differences between the ADSP 21161 and previous SHARC family processors ADSP 2106x account for boot differ ences Even with these differences the ADSP 21161 processors support the same boot capability and configuration as the ADSP 2106x processors The DMAC10 register default values differ because the ADSP 21161 processor has additional parameters and different DMA channel assignments Host boot mode uses EPBO DMA channel 10 The processor determines the boot mode at reset from the EBO0T LBOOT and BMS pin inputs When EB00T 0 LBOOT 0 and BMS 1 the processor boots from a host through the external port Refer to Table 5 1 and Table 5 2 on page 5 4 for boot mode selection When using any of the power up boot modes address 0x40004 should not contain a valid instruction Because it is not executed during the boot sequence place a NOP or IDLE instruction at this location During reset the processor ACK line is internally pulled high with an equivalent 20K ohm resistor and is held high with an internal keeper latch It is not necessary to use an external pull up resistor on the ACK line during booting or at any other time 5 10 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 21161 SHARC Processors
179. eader Uncompressed Streams Following the compressed streams see Figure 3 21 the loader file includes the uncompressed streams The uncompressed streams include application codes conflicted with the code in the initialization blocks in the processor s memory spaces and a final block The uncompressed stream includes only a final block if there is no conflicted code The final block can have a zero byte count The final block indicates the end of the application to the initialization code VisualDSP 5 0 Loader and Utilities Manual 3 53 ADSP BF53x BF561 Proc essor Booting Booting Compressed Steams The Figure 3 25 shows the booting sequence of a loader file with com pressed streams The loader file is pre stored in the flash memory 1 The boot ROM is pointing to the start of the flash memory The boot ROM reads the initialization code header and boots the ini tialization code 2 The boot ROM jumps to and starts executing the initialization code 3 A The initialization code scans the header for any compressed streams see the compression flag structure in Figure 3 24 The code decompresses the streams to the decompression window in parts and runs the initialization kernel on the decompressed data B The initialization kernel boots the data into various memories just as the boot ROM kernel does 4 The initialization code sets the boot ROM to boot the uncom pressed blocks and the final block FINAL flag is
180. eader just like the other blocks The 10 byte header instructs the boot ROM where in memory to place each block how many bytes to copy and whether the block needs any special processing The block header structure is the same as that of the ADSP BF531 BF532 BF533 processors described in ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 Block Headers and Flags on page 3 10 Each header contains a 4 byte start address for the data block a 4 byte count for the data block and a 2 byte flag word indicating whether the data block is a zero fill block or a final block the last block in the boot stream For the dxe count block the address field is irrelevant since the block is not going to be copied to memory The ignore bit is set in the flag word of this header so the boot loader utility does not try to load the dxe count but skips the count For more details see ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 Block Headers and Flags on page 3 10 Following the dxe count block are the rest of the blocks of the first dxe A bit by bit description of the boot steam is presented in Table 3 8 When learning about the ADSP BF561 boot stream structure keep in mind that the count byte for each dxe is itself a block encapsulated by a block header VisualDSP 5 0 Loader and Utilities Manual 3 39 ADSP BF53x BF561 Proc essor Booting Table 3 8 ADSP BF561 Processor Boot Stream Structure
181. ecified from the loader property page or from the loader command line via the init filename dxe switch VisualDSP includes the default decompression initialization files which the loader utility uses if no other initialization file is specified The default decompression initialization file is stored in the lt install_path gt Blackfin ldr zlib VisualDSP directory The default decompression initialization file is built for the compression window size of 9 bits VisualDSP 5 0 Loader and Utilities Manual 3 55 ADSP BF53x BF561 Proc essor Booting To use a different compression window size build your own decompres sion initialization file For details refer to the readme txt file located in the lt instal _path gt Blackfin ldr zlib src directory The size can be changed through the loader property page or the compressWS com mand line switch The valid range for the window size is 8 15 bits 3 56 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Proc essors ADSP BF53x BF561 Processor Loader Guide Loader utility operations depend on the options which control how the utility processes executable files You select features such as boot modes boot kernels and output file formats via the options The options are specified on the loader utility s command line or via the Load page of the Project Options dialog box in the VisualDSP environment The Load page consists of mult
182. efault directories File searches occur as follows e Specified path If relative or absolute path information is included in a file name the loader utility searches only in that location for the file e Default directory If path information is not included in the file name the loader utility searches for the file in the current working directory e Overlay and shared memory files The loader utility recognizes overlay and shared memory files but does not expect these files on the command line Place the files in the directory that contains the executable file that refers to them or place them in the current working directory The loader utility can locate them when pro cessing the executable file When providing an input or output file name as a loader splitter com mand line parameter use these guidelines e Enclose long file names within straight quotes long file name e Append the appropriate file extension to each file VisualDSP 5 0 Loader and Utilities Manual 1 17 File Searches 1 18 VisualDSP 5 0 Loader and Utilities Manual 2 LOADER SPLITTER FOR ADSP BF51X BF52X BF54X BLAC KFIN PRO C ESSO RS This chapter explains how the loader splitter utility e1f1oader exe is used to convert executable dxe files into boot loadable or non bootable files for the ADSP BF51x ADSP BF52x and ADSP BF54x Blackfin processors Refer to Introduction on page 1 1 for the loader utility overview Lo
183. em start up when the processor RESET input goes inactive l The processor goes into an idle state identical to that caused by the IDLE instruction The program counter PC is set to address 0x40004 The DMA parameter registers for channel 10 are initialized as shown in Table 5 3 The BMS pin becomes the boot EPROM chip select 8 bit master mode DMA transfers from EPROM to the first inter nal memory address on the external port data bus lines 23 16 The external address lines ADDR23 0 start at 0x800000 and incre ment after each access The RD strobe asserts as in a normal memory access with seven wait states eight cycles 5 8 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 21161 SHARC Processors The processor s DMA controller reads the 8 bit EPROM words packs them into 48 bit instruction words and transfers them to internal mem ory until 256 words have been loaded The EPROM is automatically selected by the BMS pin other memory select pins are disabled The master DMA internal and external count registers ECEP0 CEPO dec rement after each EPROM transfer When both counters reach zero the following wake up sequence occurs 1 DMA transfers stop 2 External port DMA channel 10 interrupt EP01 is activated 3 The BMS pin is deactivated and normal external memory selects are activated 4 The processor vectors to the EPOI interrupt vector at 0x40050 At this point the processo
184. emory A 16 bit 24 bit addressable SPI compatible EPROM must be used The following loader topics also are discussed in this chapter ADSP BF561 Processor Boot Streams on page 3 37 ADSP BF561 Processor Initialization Blocks on page 3 43 ADSP BF561 Dual Core Application Management on page 3 44 ADSP BF561 Processor Memory Ranges on page 3 45 Refer to the ADSP BF561 Embedded Symmetric Multiprocessor data sheet and the ADSP BF561 Blackfin Processor Hardware Reference manual for information about the processor s operating modes and states including background information on system reset and booting 3 36 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Processors ADSP BF561 Processor On Chip Boot ROM The boot ROM loads an application program from an external memory device and starts executing that program by jumping to the start of core A s L1 instruction SRAM at address 0xFFAO 0000 Similar to the ADSP BF531 BF532 BF533 processor the ADSP BF561 boot ROM uses the interrupt vectors to stay in supervisor mode The boot ROM code transitions from the RESET interrupt service routine into the lowest priority user interrupt service routine Int 15 and remains in the interrupt service routine The boot ROM then checks whether it has been invoked by a software reset by examining bit 4 of the system reset configuration register SYSCR If bit 4 is not set
185. er 00 Byte count zero for this record 0000 Address of first byte 01 Record type FF Checksum VisualDSP includes a utility program to convert an Intel hexadecimal file to Motorola S record or data file Refer to hexutil Hex 32 to S Record File Converter on page B 2 for details Loader Output Files in Include Format The loader utility can output include format files 1dr These files per mit the inclusion of the loader file in a C program The word width 8 or16 bit of the loader file depends on the specified boot type Similar to Intel hex 32 output the loader output in include format have some basic parts in the following order 1 Initialization code some Blackfin processors 2 Boot kernel some Blackfin SHARC and TigerSsHARC processors 3 User application code A 8 VisualDSP 5 0 Loader and Utilities Manual File Formats 4 Saved user code in conflict with the initialization code some Blackfin processors 5 Saved user code in conflict with the kernel code some Blackfin SHARC and TigerSHARC processors The initialization code is an optional first part for some Blackfin proces sors while the kernel code is the part for some Blackfin SHARC and TigerSHARC processors User application code is followed by the saved user code Files in include format are ASCII text files that consist of 48 bit instructions one per line on SHARC processors Each instru
186. er Initialization Value Comment SPICTL 0x0000 4D22 SPIDMAC 0x0000 0007 Enabled RX initialized on completion IISPI 0x0008 0000 Start of block 0 normal word memory IMSPI 0x0000 0001 32 bit data transfers CSPI 0x0000 0180 VisualDSP 5 0 Loader and Utilities Manual 6 9 ADSP 2126x 2136x 2137x 2146x Proc essor Booting SPI Master Boot Modes In SPI master boot mode the ADSP 2126x 2136x 2137x 2146x proces sor initiates the booting operation by 1 Activating the SPICLK signal and asserting the FLAGO signal on ADSP 2126x and ADSP 21362 21363 21364 21365 21366 or the SPI_FLAGO_0 signal routed by default to the DPI_PB05 pin on the ADSP 21367 21368 21369 2137x and ADSP 2146x to the active low state to enable slave select 2 Writing the read command 0x03 and address 0x00 to the slave device SPI master boot mode is used when the processor is booting from an SPI compatible serial PROM serial flash or slave host processor The specifics of booting from these devices are discussed individually e Booting From an SPI Flash on page 6 16 e Booting From an SPI PROM 16 bit address on page 6 16 e Booting From an SPI Host Processor on page 6 17 On reset the interface starts up in SPI master mode performing a three hundred eighty four 32 bit word DMA transfer SPI master booting uses the default bit settings shown in Table 6 7 Table 6 7 SPI Master Boot Mode Bit Settings Bit Sett
187. erters and digital signal processors To access a complete technical library for each processor family go to http www analog com processors technical_library The manuals selection opens a list of current manuals related to the product as well as a link to the previous revisions of the manuals When locating your manual title note a possible errata check mark next to the title that leads to the current correction report against the manual xvi VisualDSP 5 0 Loader and Utilities Manual CONTENTS Also note MyAnalog com is a free feature of the Analog Devices Web site that allows customization of a Web page to display only the latest infor mation about products you are interested in You can choose to receive weekly e mail notifications containing updates to the Web pages that meet your interests including documentation errata against all manuals MyAn alog com provides access to books application notes data sheets code examples and more Visit MyAnalog com to sign up If you are a registered user just log on Your user name is your e mail address VisualIDSP Online Documentation Online documentation comprises the VisualDSP Help system software tools manuals hardware tools manuals processor manuals Dinkum Abridged C library and FLEXnet License Tools software documenta tion You can search easily across the entire VisualDSP documentation set for any topic of interest For easy printing supplementary Portable
188. es compiled for Blackfin and SHARC architectures The e1f2f1t implements revision 5 flat relocation type For more information see the BFLT relocation structure defined in flat h E1f2f1t does not support ELF files with position independent code and global offset table PIC with GOT E1f2f1t is not capable of compressing text and data segments with gzip tool Syntax elf2flt V r k EE s 1 o file_name elf_input_file where elf_input_file is the name of the dxe file generated by the VisualDSP linker Table B 2 shows optional switches used with the el f2f1t command VisualDSP 5 0 Loader and Utilities Manual B 3 fitdump BFLT File Dumper Table B 2 ELF to BFLT File Converter Command Line Switches Switch Description V Verbose operation r Forces load to RAM k Enables kernel trace on load for debug s Sets application stack size number o file_name Names the output file h Prints the list of the e1f2f1t switches v Prints version information fitdump BFLT File Dumper The BFLT file dumper f1tdump exe utility extracts data from BFLT format executable bfit files and yields text showing the BFLT file s contents The fitdump utility prints the entire contents of the bf1t file in hex In addition the fltdump prints contents of the text section as a list of disas sembled machine instructions For more information on the BFLT file format see uClinux Web sit
189. esser number of tags compared to other SHARC predecessors There is only one initialization tag per width because there is no need to draw dis tinction between pm and dm sections during initialization The same tag is used for 16 bit short word 32 bit normal word and 64 bit long word blocks that contain only zeros The 0x1 tag is used for ZERO_INIT blocks of 16 bit 32 bit and 64 bit words The 0x2 tag is used for ZERO_INIT blocks of 40 bit data and 48 bit instructions For clarity the letter L has been added to the names of the internal block tags L indicates that the associated section header uses the logical word count and Jogical address Previous SHARC boot kernels do not use logi cal values For example the count for a 16 bit block may be the number of 32 bit words rather than the actual number of 16 bit words Only four tags are required to handle an external memory two for each packing mode see Packing Options for External Memory on page 6 7 because parallel port DMA is the only way to access the external memory The external memory can be accessed only via the physical address of the memory This means that each 32 bit word corresponds to either four for 8 bit or two for 16 bit external addresses The EXT appended to the name of the block tag indicates that the address is a physical external address For the ADSP 21367 21368 21369 2137x and ADSP 2146x processors tag INIT_L32 also is used for all external 32 bit bloc
190. ession initialization files see Decompression Initialization Files on page 3 54 These files are built with a default decompressor window size of 9 bits 512 bytes Thus if you choose a non default sliding window size for the compressor by sliding the Compression Window Size slider bar in the Compression tab under Load in the Project Options dialog box then the decompressor must be re built with the newly chosen win dow size For details on re building of the decompressor init project refer to the readme txt file located in the lt install_path gt Black fin ldr zlib srce VisualDSP directory 3 52 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Proc essors While it is true that a larger compression window size results in better compression ratios note that there are counter factors that decrease the overall effective compression ratios with increasing window sizes for Blackfin s implementation of zlib This is because of the limited memory resources on an embedded target such as a Blackfin processor For more information refer to the readme txt file in the lt insta _path gt Black fin ldr zlib src directory of VisualDSP The last 16 bits of the compressed header is the flag word The only valid compression flag assignments are shown in Figure 3 24 Compression Flag Bit 13 0 Not Compression Mode 1 Compression Block Figure 3 24 Flag Word of Compressed Block H
191. essors in a multiprocessor system For more information refer to Processor ID Numbers on page 5 23 VisualDSP 5 0 Loader and Utilities Manual 5 29 ADSP 21161 Processor Loader Guide Table 5 10 ADSP 21161 Loader Command Line Switches Cont d Switch Description kernelfile Directs the loader utility to use the specified kernel file as the boot loading routine in the output boot loadable file The boot kernel selected with this switch must correspond to the boot mode selected with the b switch If the 1 switch does not appear on the command line the loader utility searches for a default boot kernel file Based on the boot mode b switch the loader utility searches in the processor spe cific loader directory for the boot kernel file as described in ADSP 21161 Processor Boot Kernels on page 5 16 o filename Directs the loader utility to use the specified fi ename as the name for the loader output file If not specified the default name is inputfile ldr noZeroBlock paddress The noZeroBlock switch directs the loader utility not to build zero blocks Directs the loader utility to start the boot loadable file at the spec ified address in the EPROM This EPROM address corresponds to 0x8000000 on the ADSP 21161 processor If the p switch does not appear on the command line the loader utility starts the EPROM file at address 0x0 proc ADSP 21161 Specifies the
192. face Load Page on page 5 32 5 24 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 21161 SHARC Processors Using ADSP 21161 Loader Command Line Use the following syntax for the ADSP 21161 loader command line elfloader inputfile proc ADSP 21161 switch switch where e inputfile Name of the executable file dxe to be processed into a single boot loadable file An input file name can include the drive and directory Enclose long file names within straight quotes long file name e proc ADSP 21161 Part number of the processor for which the loadable file is built The proc switch is mandatory e switch One or more optional switches to process Switches select operations and boot modes for the loader utility A list of all switches and their descriptions appear in Table 5 10 on page 5 28 Command line switches are not case sensitive and placed on the command line in any order Single Processor Systems The following command line elfloader Input dxe bSPI proc ADSP 21161 runs the loader utility with e Input dxe Identifies the executable file to process into a boot loadable file for a single processor system Note that the absence of the o switch causes the output file name to default to Input 1dr VisualDSP 5 0 Loader and Utilities Manual 5 25 ADSP 21161 Processor Loader Guide e bSPI Specifies SPI port booting as the boot type for the boot loadable file e proc ADSP
193. file modified this way the source files can now take advan tage of the newly introduced sections as in Listing 3 8 Listing 3 4 Section Handling Source File Example SECTION rom_code _reset_vector 10 0 l 0 12 0 35S 0s continue with setup and application code Pe bse we OE SECTION rom_data VAR myconst x Oxdeadbeef PR os ie cg RO SECTION ram_data VAR myvar y note that y cannot be initialized automatically 3 18 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Processors ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 Processor Memory Ranges The on chip boot ROM on the ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 Blackfin processors allows booting to the following memory ranges e LI memory e ADSP BF531 processor v Data bank A SRAM 0xFF80 4000 0xFF80 7FFF v Instruction SRAM 0xFFAO 8000 OxFFAO BFFF e ADSP BF532 processor v Data bank A SRAM 0xFF80 4000 O0xFF80 7FFF v Data bank B SRAM 0xFF90 4000 OxFF90 7FFF v Instruction SRAM 0xFFAO 8000 OxFFAL 3FFF e ADSP BF533 processor v Data bank A SRAM 0xFF80 0000 O0xFF80 7FFF v Data bank B SRAM 0xFF90 000 OxFF90 7FFF v Instruction SRAM 0xFFAO 0000 OxFFA1 3FFF e ADSP BF534 processor v Data bank A SRAM 0xFF80 0000 0xFF80 7FFF v Data bank B SRAM 0xFF90 0000 0xFF90 7FFF v Instruction SRAM 0xFFAO 0000 0xFFA1 3FFF e ADSP BF536 processo
194. files as well as shared memory and overlay files as inputs to yield a processor loadable file VisualDSP 5 0 includes these loader and splitter utilities e elfloader exe loader utility for Blackfin TigerSHARC and SHARC processors The loader utility for Blackfin processors also acts asa ROM splitter utility when evoked with the corresponding switches e elfspl21k exe ROM splitter utility for TigerSHARC and SHARC processors VisualDSP 5 0 Loader and Utilities Manual 1 9 Program Development How The loader splitter output is either a boot loadable or non bootable file The output is meant to be loaded onto the target There are several ways to use the output e Download the loadable file into the processor s PROM space on an EZ KIT Lite board via the Flash Programmer plug in Refer to VisualDSP Help for information on the Flash Programmer e Use VisualDSP to simulate booting in a simulator session cur rently supported on the ADSP 21060 ADSP 21061 ADSP 21065L ADSP 21160 and ADSP 21161 processors Load the loader file and then reset the processor to debug the booting routines No hardware is required just point to the location of the loader file letting the simulator to do the rest You can step through the boot kernel code as it brings the rest of the code into memory e Store the loader file in an array for a multiprocessor system A mas ter host processor has the array in its memory allowing a full
195. for matted boot stream In this context a boot loadable file differs from a non bootable file in that it stores instruction code in a formatted manner in order to be processed by a boot kernel A non bootable file stores raw instruction code Boot Kemels A boot kernel refers to the resident program in the boot ROM space responsible for booting the processor Alternatively or in absence of the boot ROM the boot kernel can be preloaded from the boot source by a bootstrapping scheme When a reset signal is sent to the processor the processor starts booting from a PROM host device or through a communication port For exam ple an ADSP 2106x 2116x processor brings a 256 word program into internal memory for execution This small program is a boot kernel The boot kernel then brings the rest of the application code into the pro cessor s memory Finally the boot kernel overwrites itself with the final block of application code and jumps to the beginning of the application program Some of the newer Blackfin processors do not require to load a boot ker nel a kernel is already present in the on chip boot ROM It allows the entire application program s body to be booted into the internal and external memories of the processor The boot kernel in the on chip ROM behaves similar to the second stage loader of the ADSP BF535 processors The boot ROM has the capability to parse address and count information for each bootable block
196. formation on the loader utility s com mand line syntax and switches VisualDSP 5 0 Loader and Utilities Manual 3 1 ADSP BF53x BF561 Proc essor Booting ADSP BF53x BF561 Proc essor Booting At power up after a reset the processor transitions into a boot mode sequence configured by the BMODE pins The BMODE pins are dedicated mode control pins that is no other functions are performed by these pins The pins can be read through bits in the system reset configuration register SYSCR An ADSP BF53x or an ADSP BF561 Blackfin processor can be booted from an eight or 16 bit flash PROM memory or from an eight 16 or 24 bit addressable SPI memory The ADSP BF561 processors does not support 24 bit addressable SPI memory boot There is also a no boot option bypass mode in which execution occurs from a 16 bit external memory e ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 Processor Booting description is on page 3 3 e ADSP BF535 Processor Booting description is on page 3 21 e ADSP BF561 Processor Booting description is on page 3 35 Software developers who use the loader utility should be familiar with the the following operations e ADSP BF53x and ADSP BF561 Multi Application Multi DXE Management on page 3 46 e ADSP BF531 BF532 BF533 BF534 BF536 BF537 Processor Compression Support on page 3 49 3 2 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Proc es
197. g commands to rebuild the boot kernel easm21k 21060 my_host asm or easm21k proc ADSP 21060 my_host asm linker T 060_ldr ldf my_host doj Link Port Booting The default boot kernel source file for the ADSP 2106x link port booting is 060_link asm Copy this file to my_link asm and modify it to suit your system Then use the following commands to rebuild the boot kernel easm21k 21060 my_link asm or easm21k proc ADSP 21060 my_link asm linker T 060_ldr ldf my_link doj VisualDSP 5 0 Loader and Utilities Manual 4 21 ADSP 2106x 21160 Proc essor Booting Rebuilding Boot Kernels To rebuild the PROM boot kernel for the ADSP 21065L processors use these commands easm21k 21065L my_prom asm or easm21k proc ADSP 21065L my_prom asm linker T 065L_ldr ldf my_prom doj To rebuild the PROM boot kernel for the ADSP 21160 processors use these commands easm21k 21160 my_prom asm or easm21k proc ADSP 21160 my_prom asm linker T 160_ldr ldf my_prom doj ADSP 2106x 21160 Interrupt Vector Table If an ADSP 2106x 21160 SHARC processor is booted from an external source EPROM host or another SHARC processor the interrupt vec tor table is located in internal memory If however the processor is not booted and executes from external memory the vector table must be located in external memory The I IVT bit of the SYSCON control register can be used to override the boot mode in determining where the interrupt vector t
198. general information about various booting modes includ ing information about boot kernels e ADSP 2126x 2136x 2137x 2146x Processor Loader Guide Provides reference information about the graphical user interface command line syntax and switches VisualDSP 5 0 Loader and Utilities Manual 6 1 ADSP 2126x 2136x 2137x 2146x Proc essor Booting ADSP 2126x 2136x 2137x 2146x Proc essor Booting The ADSP 2126x ADSP 2136x ADSP 2137x and ADSP 2146x proces sors can be booted from an external PROM memory device via the parallel port PROM mode or via the serial peripheral interface SPI slave SPI flash or SPI master mode In no boot mode the processor is booted from the internal ROM only available on some processors In parallel port boot mode the loader output file 1dr is stored in an 8 bit wide parallel PROM device and fetched by the processor On the ADSP 2126x 2136x 2137x 2146x processors whether supporting multiprocessing or not there is no ID lookup table between the kernel and the rest of the application In SPI slave boot mode the loader file is transmitted to the proces sor by a host processor configured as an SPI master There are three cases for the SPI master boot mode SPI master no address SPI PROM 16 bit address and SPI flash 24 bit address The difference between the these modes is the way the slave device sends the first word of the 1dr file In SPI PROM and SPI flash boot modes the
199. gister Settings for PROM Boot Mode Bit Setting PPALEPL 0 ALE is active high PPEN PPDUR 10111 23 core clock cycles per data transfer cycle PPBHC 1 insert a bus hold cycle on every access PP16 0 external data width 8 bits PPDEN 1 use DMA PPTRAN 0 receive read DMA PPBHD 0 buffer hang enabled The parallel port DMA channel is used when downloading the boot kernel information to the processor At reset the DMA parameter registers are initialized to the values listed in Table 6 4 Table 6 4 Parameter Register Settings for PROM Boot Mode Parameter Register Initialization Value Comment PPCTL 0x0000 O16F See Table 6 3 IPP 0 for the ADSP 2126x processors The offset from internal memory 0x10000 for the ADSP 2136x 2146x normal word starting address of processors 0x80000 CPP 0x180 384 The number of 32 bit words that are equivalent to 256 instructions MPP 0x01 EIPP 0x00 ECPP 0x600 The number of bytes in 0x100 48 bit instructions EMPP 0x01 6 6 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2126x 2136x 2137x 2146x SHARC Processors Packing Options for External Memory For the ADSP 2126x processors the external memory address ranges are 0x1000000 0x2FFFFFF For the ADSP 21362 21363 21364 21365 21366 processors the external memory address ranges are 0x1200000 0x1203F FF For the
200. h LDF Preprocessing ER Elimination fs Processor fy Compression Additional options fy Kernel ESen Figure 3 29 Project Splitter Page for ADSP BF533 Processors ADSP BF535 and ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 Proc essor No Boot Mode The hardware settings of BMODE 000 for the ADSP BF535 processors or BMODE 00 for ADSP BF531 ADSP BF532 and ADSP BF533 proces sors select the no boot option In this mode of operation the on chip boot kernel is bypassed after reset and the processor starts fetching and VisualDSP 5 0 Loader and Utilities Manual 3 79 ADSP BF53x BF561 Processor Loader Guide executing instructions from address 0x2000 0000 in the asynchronous memory bank 0 The processor assumes 16 bit memory with valid instruc tions at that location To create a proper ldr file that can be burned into either a parallel flash or EPROM device you must modify the standard LDF file in order for the reset vector to be located accordingly The following code fragments Listing 3 6 and Listing 3 7 illustrate the required modifications in case of an ADSP BF533 processor Listing 3 6 Section Assignment LDF File Example MEMORY Off chip Instruction ROM in Async Bank 0 MEM_PROGRAM_ROM TYPE ROM START Ox20000000 END Ox2009FFFF WIDTH 8 Off chip constant data in Async Bank 0 MEM_DATA_ROM TYPECROM START Ox200A0000 END OX200FFFFF WIDTH 8 On chip
201. he init filename dxe switch directs the loader utility to include the initialization code from the named executable file The loader utility places the code and data from the initialization sec tions at the top of the boot stream The boot kernel loads the code and then calls it It is the code s responsibility to save restore state registers and then perform an RTS back to the kernel Init codes can be written in C language and are compliant to C calling conventions The init filename dxe switch can be used multiple times to specify the same file or different files a number of times The loader utility will place the code from the initialization files in the order the files appear on the command line For more information see ADSP BF5 1x BF52x BF54x Multi DXE Loader Files on page 2 17 2 10 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF51x BF52x BF54x Blac kfin Proc essors Table 2 5 ADSP BF51x BF52x BF54x Loader Command Line Switch Summary Contd Switch Description initcall sym sym_symbol While the init filename dxe switch integrates initialization at at_symbol codes managed by a separate application program the initcal1 stride DstAddrGap switch controls calls to initialization subroutines that are part of count times the same application The initcal1 switch directs the loader utility to dispatch a boot time initialization call to the sym subroutine when the at symbol
202. he Load page of the Project Options dialog box in VisualDSP or via the 1 command line switch the loader utility places a default boot kernel see Table 6 11 in the loader output file based on the specified boot type If you do not want to use any boot kernel file check the No kernel box or specify the nokernel command line switch The loader utility places no boot kernel in the loader output file Rebuilding a Boot Kernel File If you modify the boot kernel source asm file by inserting correct values for your system you must rebuild the boot kernel dxe before generating the boot loadable 1dr file The boot kernel source file contains default values for the SYSCON register The WAIT SDCTL and SDRDIV initialization code are in the boot kernel file comments To Modify a Boot Kernel Source File 1 Copy the applicable boot kernel source file asm 2 Apply the appropriate changes 6 20 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2126x 2136x 2137x 2146x SHARC Processors After modifying the boot kernel source file rebuild the boot kernel dxe file Do this from within the VisualDSP IDDE refer to VisualDSP online Help for details or rebuild a boot kernel file from the command line Rebuilding a Boot Kernel Using Command Lines Rebuild a boot kernel using command lines as follows PROM Booting The default boot kernel source file for PROM booting is 26x_prom asm for the ADSP 2126x processor
203. ial transfers The sPIRx DMA channel 8 parameter registers are configured to DMA in 0x180 32 bit words into internal memory normal word address space start ing at 0x40000 Once the 32 bit DMA transfer completes the data is accessed as 3 column 48 bit instructions The processor executes a 256 word 0x100 boot kernel upon completion of the 32 bit 0x180 word DMA For 16 bit SPI hosts two words are shifted into the 32 bit receive shift register before a DMA transfer to internal memory occurs For 8 bit SPI hosts four words are shifted into the 32 bit receive shift register before a DMA transfer to internal memory occurs VisualDSP 5 0 Loader and Utilities Manual 5 15 ADSP 21161 Proc essor Booting Table 5 6 DMA Channel 8 Parameter Register for SPI Port Boot Parameter Register Initialization Value TISRX 0x0004 0000 IMSRX Uninitialized increment by 1 is automatic CSRX 0x0180 256 instruction words GPSRX Uninitialized No Boot Mode No boot mode causes the processor to start fetching and executing instructions at address 0x200004 in external memory space In no boot mode the processor does not boot load and all DMA control and parameter registers are set to their default initialization values The loader utility does not produce the code for no boot execution ADSP 21161 Processor Boot Kemels The boot loading process starts with a transfer of the boot kernel program into the processor memory Th
204. ication code kp The kp switch specifies a hex flash PROM start address for the initialization and or boot kernel code A valid value is between 0x0 and OxFFFFFFFF The specified value is ignored when neither kernel nor initialization code is included in the loader file 2 12 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF51x BF52x BF54x Blac kfin Proc essors Table 2 5 ADSP BF51x BF52x BF54x Loader Command Line Switch Summary Contd Switch Description kwidth The kwidth 8 16 32 switch specifies an external memory device width in bits for the initialization code and or the boot kernel if two output files from the loader utility are selected If kwidth is absent from the command line the loader utility generates the boot kernel file in the same width as the user applica tion program with the 02 switch The kWidth switch must be used in conjunction 1 userkernel dxe The 1 userkerne dxe switch specifies the user boot kernel file There is no default kernel for the ADSP BF51x BF52x BF54x processors M The M switch generates make dependencies only no output file is generated maskaddr The maskaddr switch masks all EPROM address bits above or equal to For example maskaddr 29 default masks all the bits above and including A29 ANDed by Ox1FFF FFFF For exam ple 0x2000 0000 becomes 0x0000 0000 The valid fs are inte gers 0 through 32 but based on y
205. ificant 1 next to least significant and so on For info about Motorola S record file for mat refer to Output Files in Motorola S Record Format on page A 10 h_ Intel hex 32 format file The indicates the position 0 least significant 1 next to least significant and so on For information about Intel hex 32 file for mat refer to Splitter Output Files in Intel Hex 32 Format on page A 12 stk Byte stacked format file These files are intended for host transfer of data not for PROMs For more information about byte stacked file format format files refer to Splitter Output Files in Byte Stacked Format on page A 12 VisualDSP 5 0 Loader and Utilities Manual Splitter for SHARC and TigerSHARC Processors Splitter Command Line Switches A list of the splitter command line switches appears in Table 8 2 Table 8 2 Splitter Command Line Switches Item Description 64 The 64 include DATA64 memory switch directs the splitter utility to extract all sections declared as 64 bit memory sections from the input dxe file The switch influences the operation of the ram and norom switches adding 64 bit data memory as their target dm The dm include data memory switch directs the splitter utility to extract memory sections declared as data memory ROM from the input dxe file The dm switch influences the operation of the ram and norom switches adding data memory as their
206. igh the processor starts up in EPROM boot mode The processor assumes the EPROM data bus is 8 bits wide Connect BSEL to the processor data bus in LSB alignment When BSEL is low BMS determines the booting mode Connect BSEL to ground 1 Three statable in EPROM boot mode when BMS is an output Table 4 6 ADSP 21065L Boot Modes BSEL BMS Description 0 1 No boot mode The processor executes from external memory at location 0x20004 0 1 Host boot mode The processor defaults to an 8 bit host bus width 1 Output EPROM boot mode The processor assumes an 8 bit EPROM data bus width Connect to the data bus in LSB alignment 4 6 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2106x 21160 SHARC Processors ADSP 2106x 21160 Boot Modes The ADSP 2106x 21160 processors support these boot modes EPROM host and link The following sections describe each of the modes e EPROM Boot Mode on page 4 7 e Host Boot Mode on page 4 11 e Link Port Boot Mode on page 4 15 e No Boot Mode on page 4 16 For multiprocessor booting refer to ADSP 2106x 21160 Multi Applica tion Multi DXE Management on page 4 23 EPROM Boot Mode The ADSP 2106x 21160 processor is configured for EPROM boot through the external port when the 8007 pin is high and the LBOOT pin is low These settings cause the BMS pin to become an output serving as chip select for the EPROM Table
207. ing Comment SPIEN Set 1 SPI enabled MS Set 1 Master device MSBF Cleared 0 LSB first WL 10 32 bit SPI receive shift register word length 6 10 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2126x 2136x 2137x 2146x SHARC Processors Table 6 7 SPI Master Boot Mode Bit Settings Contd Bit Setting Comment DMISO Cleared 0 MISO enabled SENDZ Set 1 Send zeros SPIRCV Set 1 Receive DMA enabled CLKPL Set 1 Active low SPI clock CPHASE Set 1 Toggle SPICLK at the beginning of the first bit The SPI DMA channel is used when downloading the boot kernel infor mation to the processor At reset the DMA parameter registers are initialized to the values listed in Table 6 8 Table 6 8 Parameter Registers Settings for SPI Master Boot Parameter Register Initialization Value Comment SPICTL 0x0000 5D06 SPIBAUD 0x0064 CCLK 400 500 KHz 200 MHz SPIFLG Oxfedl e FLAGO on the ADSP 2126x and ADSP 21362 21363 21364 21365 2136 processors e SPI_FLAGO_O is used as slave select on the ADSP 21367 21368 21369 2137x and ADSP 2146x processors SPIDMAC 0x0000 0007 Enable receive interrupt on completion IISPI 0x0008 0000 Start of block 0 normal word memory IMSPI 0x0000 0001 32 bit data transfers CSPI 0x0000 0180 0x100 instructions 0x180 32 bit words From the perspective of the processor there is no difference between boot
208. ing Various Serial Devices Bit Reverse Option for SPI Boot Modes SPI PROM For the SPI PROM boot type the entirety of the SPI master 1dr file needs the option of bit reversing when loading to SPI PROMs This is because the default setting for the SPICTL register see Table 6 8 on page 6 11 sets the bit order to be LSB first SPI EPROMs are usually MSB first so the 1dr file must be sent in bit reversed order VisualDSP 5 0 Loader and Utilities Manual 6 13 ADSP 2126x 2136x 2137x 2146x Proc essor Booting SPI Master and SPI Slave When loading to other slave devices the SPI master and SPI slave boot types do not need bit reversing necessarily For SPI slave and SPI master boots to non PROM devices the same default exists bit reversed however the host master or slave can simply be configured to transmit LSB first Initial Word Option for SPI Master Boot Modes Before final formatting binary include etc the loader must prepends the word 0xA5 to the beginning of the byte stream During SPI master booting the SPI port discards the first byte read from the SPI SPI PROM For the SPI PROM boot type the word 0xA5 prepended to the stream is one byte in length SPI PROMs receives a 24 bit read com mand before any data is sent to the processor the processor then discards the first byte it receives after this 24 bit opcode is sent totaling one 32 bit word SPI Master For the SPI master boot type the word 0xA5000000 p
209. ink port boot mode TigersHARC processors 7 3 7 9 loadable files See boot loadable files loader operations 1 11 output file formats 1 11 1 16 A 6 A 8 A 9 setting options 2 18 3 72 4 32 5 32 6 49 7 12 8 9 loader file formats ADSP BF535 processors PROM flash boot with kernel 3 30 PROM flash boot without kernel 3 29 PROM flash SPI boot with kernel 3 28 3 30 loader for ADSP 2106x 21160 processors 4 1 loader for ADSP 21161 processors 5 1 loader for ADSP 2126x 36x 37x 469 processors 6 1 loader for ADSP BF51x 52x 54x Blackfin includes splitter 2 1 loader for ADSP BF53x BF561 Blackfin includes splitter 3 1 loader for Blackfin includes splitter command line syntax 2 6 2 8 3 58 3 60 default settings 2 18 3 72 graphical user interface 2 19 3 72 list of switches 2 8 3 60 loader for TigerSsHARC command line syntax 7 6 graphical user interface 7 12 list of switches 7 9 operations 7 1 VisualDSP 5 0 Loader and Utilities Manual loader kernels See boot kernels loader output See output files loader switches See switches by name loading introduction to 1 9 Load page Blackfin processors 2 18 3 72 SHARC processors 4 32 5 32 6 49 TigerSHARC processors 7 12 Load Splitter page Blackfin processors 2 22 3 78 l userkernel loader switch for Blackfin 2 13 3 46 3 64 loader switch for SHARC 4 30 5 30 6 20 6 40 6 46 loader switch for TigerSHARC 7 9 7 10 M M loader swit
210. ion alone or with an invalid value the loader utility generates an error t Host boot type only Specifies timeout cycles The t switch for example t100 limits the number of cycles that the processor spends initializing external memory with zeros Valid values range from 3 to 32765 cycles 32765 is the default value The timeout value is related directly to the number of cycles the processor locks the bus for boot loading instructing the pro cessor to lock the bus for no more than two times the timeout number of cycles When working with a fast host that cannot tol erate being locked out of the bus use a relatively small timeout value VisualDSP 5 0 Loader and Utilities Manual 5 31 ADSP 21161 Processor Loader Guide Table 5 10 ADSP 21161 Loader Command Line Switches Cont d Switch Description y Outputs verbose loader messages and status information as the loader utility processes files version Directs the loader utility to show its version information Type elfloader version to display the version of the loader drive Add the proc switch for example elfloader proc ADSP 21161 version to display version information of both loader drive and SHARC loader Using VisualDSP Interface Load Page After selecting a Loader file as the target type on the Project page in Visu alDSP Project Options dialog box modify the default options on the Load Processor page
211. iple panes When you open the Load page the default loader settings for the selected processor are set already Option settings on the Load page correspond to switches displayed on the command line These sections describe how to produce a bootable or non bootable loader file cc e Using Blackfin Loader Command Line on page 3 58 e Using VisualDSP Loader on page 3 72 Using VisualDSP Compression on page 3 75 e Using VisualDSP Second Stage Loader for ADSP BF535 Pro cessors on page 3 76 e Using VisualDSP ROM Splitter on page 3 78 VisualDSP 5 0 Loader and Utilities Manual 3 57 ADSP BF53x BF561 Processor Loader Guide Using Blackfin Loader Command Line The ADSP BF5xx Blackfin loader utility uses the following command line syntax For a single input file elfloader inputfile proc processor switch For multiple input files elfloader inputfilel inputfile2 proc processor switch where e inputfile Name of the executable dxe file to be processed into a single boot loadable or non bootable file An input file name can include the drive and directory For multiprocessor or multi input systems specify multiple input dxe files Put the input file names in the order in which you want the loader utility to process the files Enclose long file names within straight quotes long file name e proc processor Part number of the processor for example pro
212. is encountered and loaded The stride and count param eters are optional e Ifan optional stride constant 32 bit value is specified the loader utility insets the target program call every stride target address locations e Ifan optional count constant 32 bit value is specified the loader utility insets the target program call count times every stride target address locations apart A count value without a stride value is an error For example the following command line initcall sym _initcode at _othersymbol stride 0x100 count 5 results in function _initcode being called five times the first time just prior to data in __othersymbol being booted Thereaf ter every 256 destination load addresses _initcode is called again until a total of five calls have been made initcal restrictions e initcall target sym_symbo must be a routine entry point end with an RTS It can be written in C language and can rely on the presence of a stack However the routine must not call any libraries not rely on compiler run time environment such as heaps must be self contained e initcall subroutine must be previously loaded and still in memory e initcall subroutine cannot contain any forward refer ences to code not yet loaded e sym symbol address must be less than at_symbol address For more information see ADSP BF51x BF52x BF54x Multi DXE Loader Files on page 2 17 VisualDSP 5 0 Loader and Utilities M
213. ist of 2 7 3 59 ASCII 2 9 3 62 7 9 A 14 binary 2 9 3 62 7 9 build files A 4 byte stacked stk 8 4 8 6 8 7 debugger input files A 15 hexadecimal Intel hex 32 2 9 3 62 7 9 8 4 8 6 include 2 9 3 62 7 9 reference information A 16 s record Motorola 7 9 8 4 8 6 file formatting selecting for output 2 12 3 63 specifying word width 3 69 INDEX file search rules 1 17 final blocks See also last blocks Blackfin processors introduction to 1 15 SHARC processors 4 18 6 18 6 28 FLAG pins ADSP 2106x 160 processors 4 23 flag words Blackfin processors ADSP BF531 2 3 4 6 7 8 9 processors 3 11 ADSP BF535 processors 3 33 ADSP BF561 processors 3 39 3 43 flash memory See also PROM flash boot mode ADSP BF5 1x processors 2 3 ADSP BF52x 54x processors 2 4 devices 1 9 hold time cycle selection 3 62 3 74 FLGO signal 6 10 6 11 fltdump utility B 4 frequency 4 15 5 13 G ghc loader switch for Blackfin 3 62 global header cookies Blackfin processors 3 62 global headers Blackfin processors ADSP BF535 processors 3 31 3 32 ADSP BF561 processors 3 38 GPEP0 register 5 8 5 11 GPLBO register 5 14 GPSRX register 5 16 H h help loader switch for Blackfin 2 9 3 62 loader switch for SHARC 4 29 5 29 6 45 loader switch for TigerSHARC 7 9 HBG pin 4 13 HBR pin 5 12 HBW bits 4 12 VisualDSP 5 0 Loader and Utilities Manual I 7 INDEX header files h A 3
214. it address These devices begin transmitting on clock cycle 24 However because the processor is not expecting data until clock cycle 32 it is necessary for the loader to pad an extra byte to the beginning of the boot stream when programming the PROM In other words the first byte of the boot kernel is the second byte of the boot stream The VisualDSP tools automatically handles this in the loader file generation process for SPI PROM devices 6 16 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2126x 2136x 2137x 2146x SHARC Processors Booting From an SPI Host Processor Typically host processors in SPI slave mode transmit data on every SPICLK cycle This means that the first four bytes that are sent by the host proces sor are part of the first 32 bit word that is thrown away by the processor see Figure 6 1 Therefore it is necessary for the loader to pad an extra four bytes to the beginning of the boot stream when programming the host for example the first byte of the kernel is the fifth byte of the boot stream VisualDSP automatically handles this in the loader file genera tion process Intemal Boot Mode In internal boot mode upon reset the processor starts executing the appli cation stored in the internal boot kernel To facilitate internal booting the nokernel command line switch com mands the loader utility e To omit a boot kernel The nokernel switch denotes that a running on the processor
215. itch romsplitter The romsplitter switch creates a non bootable image only This switch overwrites the b switch and any other switch bounded by the boot mode In the 1df file declare memory segments to be split as type ROM The splitter skips RAM segments resulting in an empty file if all segments are declared as RAM The romsplitter switch supports Intel hex and ASCII formats VisualDSP 5 0 Loader and Utilities Manual 2 15 ADSP BF51x BF52x BF54x Processor Loader Guide Table 2 5 ADSP BF51x BF52x BF54x Loader Command Line Switch Summary Contd Switch Description save sec section The save switch takes a sec section no spaces assignment The switch directs the loader utility to mark blocks within the LDF defined section name with the BFLAG_SAVE flag The switch is used to mark blocks to archive for low power or power fail cycles si revision none any The si revision none any switch provides a silicon revision of the specified processor The switch parameter repre sents a silicon revision of the processor specified by the proc processor switch The parameter takes one of three forms e The value indicates one or more decimal digits fol lowed by a point followed by one or two decimal digits Examples of revisions are 0 0 1 12 23 1 Revision 0 0 is default Revision 0 1 is distinct from and lower than revision 0 10 The digits to the left of the p
216. itiates the booting operation by activating the SPICLK signal and asserting the SPIDS signal to the active low state The 256 word boot kernel is loaded 32 bits at a time via the SPI receive shift register To receive 256 instructions 48 bit words prop erly the SPI DMA initially loads a DMA count of 384 32 bit words which is equivalent to 256 48 bit words The processor s SPIDS pin should not be tied low When in SPI slave mode including booting the SPIDS signal is required to tran sition from high to low SPI slave booting uses the default bit settings shown in Table 6 5 6 8 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2126x 2136x 2137x 2146x SHARC Processors Table 6 5 SPI Slave Boot Bit Settings Bit Setting Comment SPIEN Set 1 SPI enabled MS Cleared 0 Slave device MSBF Cleared 0 LSB first WL 10 32 bit SPI Receive Shift register word length DMISO Set 1 MISO MISO disabled SENDZ Cleared 0 Send last word SPIRCV Set 1 Receive DMA enabled CLKPL Set 1 Active low SPI clock CPHASE Set 1 Toggle SPICLK at the beginning of the first bit The SPI DMA channel is used when downloading the boot kernel infor mation to the processor At reset the DMA parameter registers are initialized to the values listed in Table 6 6 Table 6 6 Parameter Register Settings for SPI Slave Boot Parameter Regist
217. ition a second stage loader must be used to change the wait states or hold time cycles for a flash PROM booting or to change the baud rate for an SPI boot see Blackfin Loader Command Line Switches on page 3 60 for more information on these features Some Second Stage Loader Restrictions are documented on page 3 34 3 24 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Processors When a second stage loader is used for booting the following sequence occurs 1 Upon reset the on chip boot ROM downloads N bytes the second stage loader from external memory to address 0xF000 0000 in L2 memory Figure 3 7 ADSP BF535 Processor PROMFlash or SPI Device Figure 3 7 ADSP BF535 Processors Booting With Second Stage Loader VisualDSP 5 0 Loader and Utilities Manual 3 25 ADSP BF53x BF561 Proc essor Booting 2 The second stage loader copies itself to the bottom of L2 memory ADSP BF535 Processor PROM Flash or SPI Device 0x0 Figure 3 8 ADSP BF535 Processors Copying Second Stage Loader 3 The second stage loader downloads the application code and data into the various memories of the Blackfin processor Figure 3 9 ADSP BF535 Processor PROM Flash or SPI Device Application Figure 3 9 ADSP BF535 Processors Booting Application Code 3 26 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Processors 4
218. its If BMODE 01 or 001 and flash PROM is 16 bit wide the 16 bit option must be selected Wait state Specifies the number of wait states for external access 0 15 The selection is active for the ADSP BF535 processors For the ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 BF561 processors the field is grayed out VisualDSP 5 0 Loader and Utilities Manual 3 73 ADSP BF53x BF561 Processor Loader Guide Table 3 14 Base Load Page Settings for ADSP BF53x BF561 Processors Setting Description Baud rate Specifies a baud rate for SPI booting 500 kHz 1 MHz and 2 MHz The selection is active for the ADSP BF535 processors For the ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 BF561 processors the field is grayed out Hold time Specifies the number of the hold time cycles for flash PROM boot 0 3 The selection is active for the ADSP BF535 processors For the ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 BF561 processors the field is grayed out Programmable flag Same as the pFlag command line switch selects a programmable flag number 0 15 for a strobe or for a port The box is active for the ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 pro cessors Valid values are listed in Table 3 11 through Table 3 13 The NONE option also is available when chosen no pFlag switch appears on the command line Verify the programmable flag setting whenever the processo
219. kfin Proc essors p5 0 SP MAKE SURE NOT TO RESTORE RO for flash PROM Boot R3 for SPI Boot Cr7 20 SP RETS SP ASTAT SP BRK KRKKKKK KKK KKK KK KKK KKK KKK KK KK KK KKK KKK KKK KKK KKK KKK KK KKK KKK KK KK RTS ADSP BF531 BF532 BF533 BF534 BF536 BF537 Proc essor Compression Support The loader utility for the ADSP BF531 BF532 BF533 BF534 BF536 BF537 processors offers a loader file boot stream compression mechanism known as zLib The zLib compression is supported by a third party dynamic link library zLib1l d11 Additional information about the library can be obtained from the http www zlib net Web site The zLibl d11 dynamic link library is included in VisualDSP The library functions perform the boot stream compression and decompression procedures when the appropriate options are selected for the loader utility The initialization executable files with built in decompression mechanism must perform the decompression on a compressed boot stream in a boot process The default initialization executable files with decompression functions are included in VisualDSP The loader compression switch directs the loader utility to perform the boot stream compression from the command line VisualDSP also offers a dedicated loader property page see Figure 3 27 to manage the compression from the IDDE The loader utility takes two steps to compress a boot stream First the utility generate
220. ks The 0x8 tag is for multiprocessor systems exclusively supported on the ADSP 21367 21368 21369 2137x and ADSP 2146x processors The tag indicates that the header is a processor ID header with the ID values and offset values stored in the header A block can have multiple IDs in its block header which makes it possible to boot the block into multiple processors VisualDSP 5 0 Loader and Utilities Manual 6 25 ADSP 2126x 2136x 2137x 2146x Proc essor Booting Two data tags USER_MESG and FINAL_INIT differ from the standard for mat for other SHARC data tags The USER_MESG header is described on page 6 17 and the FINAL_INIT header on page 6 28 INIT_L48 Blocks The INIT_L48 block has one packing and one padding requirements First there must be an even number of 48 bit words in the block If there is an odd number of instructions then the loader utility must append one addi tional 48 bit instruction that is all zeros In all cases the count placed into the header is the original logical number of words That is the count does not include the padded word Once the number of words in the block is even the data in this block is packed according to Table 6 13 Table 6 13 INIT_L48 Block Packing and Zero Padding ASCII Format Original Data Packed into an Even hostwidth Number of 32 bit Words 32 16 8 111122223333 22223333 22223333 3333 33 444455556666 66661111 55551111 2222 33 AAA
221. le for core A p0 dxe By default The boot ROM loads only one single executable before the ROM jumps to the start of core A instruction SRAM 0xFFA0 0000 When two dxe files are loaded a second stage loader is used Or when the noSecondStageKernel switch is called the loader utility combines the two dxe files into one If the he second stage boot loader is used it must start at OxFFAO 0000 The boot ROM loads and executes the second stage loader A default second stage loader is provided for each boot mode and can be customized by the user Unlike the initialization blocks the second stage loader takes full control over the boot process and never returns to the boot ROM The second stage loader can use the dxe byte count blocks to find spe cific dxe files in external memory if a loader file includes the codes and data from a number of dxe files The default second stage loader uses the last 1024 bytes of L2 memory The area must be reserved during booting but can be reallocated at runtime 3 44 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Processors ADSP BF561 Processor Memory Ranges The on chip boot ROM of the ADSP BF561 processor can load a full application to the various memories of both cores Booting is allowed to the following memory ranges The boot ROM clears these memory ranges before booting in a new application e Core A v v v v L1 instruc
222. learing bit 5 in core A s system configuration register Then core B begins execution at address 0xFF60 0000 Multiple dxe files are often combined into a single boot stream see ADSP BF561 Dual Core Application Management on page 3 44 and ADSP BF53x and ADSP BF561 Multi Application Multi DXE Management on page 3 46 Unlike the ADSP BF531 BF532 BF533 processor the ADSP BF561 boot stream begins with a 4 byte global header which contains informa tion about the external memory device A bit by bit description of the global header is presented in Table 3 7 The global header also contains a signature in the upper 4 bits that prevents the boot ROM from reading in a boot stream from a blank device Table 3 7 ADSP BF561 Global Header Structure Bit Field Description 0 1 16 bit flash 0 eight bit flash default is 0 1 4 Number of wait states default is 15 5 Unused bit 6 7 Number of hold time cycles for flash default is 3 8 10 Baud rate for SPI boot 00 500k 01 1M 10 2M 11 27 Reserved for future use 28 31 Signature that indicates valid boot stream 3 38 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Proc essors Following the global header is a dxe count block which contains a 32 bit byte count for the first dxe file in the boot stream Though this block contains only a byte count it is encapsulated by a 10 byte block h
223. lization code such as SDRAM initial ization before the full boot sequence proceeds Figure 3 4 and Figure 3 5 illus trate the process Initialization code can be included within the 1dr file by using the init switch see init filename dxe on page 3 62 See ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 Ini tialization Blocks on page 3 13 for more information VisualDSP 5 0 Loader and Utilities Manual 3 11 ADSP BF53x BF561 Proc essor Booting Table 3 4 Flag Structure Cont d Bit Field Description Ignore block Indicates that the block is not to be booted into memory skips the block and moves on to the next one Currently is not implemented for application code This flag is equivalent to the FIRST flag in boot streams on the ADSP BF51x BF52x BF54x processors Because the IGNORE flag is used for other purposes on the ADSP BF5 1x BF52x BF54x processors the FIRST flag is invented to indicate the first header Last Block 1 Last Block 0 Not Last Block Compressed Block 1 Compressed Block 0 Not Compressed Block Port Number 00 Disabled 01 Port F 10 Port G 11 Port H Programmable Flag BBE BHU a Compressed Indicates that the block contains compressed data The compressed block can block include a number of blocks compressed together to form a single compressed block Last block Indicates that the block is the last block to b
224. lled a boot kernel described on page 1 15 parses the boot stream and initializes memories accordingly The boot kernel runs on the target processor Depending on the architecture the boot kernel may exe cute from on chip boot RAM or may be preloaded from the PROM device into on chip SRAM and execute from there The loader utility generates the boot stream from the linker output an executable file and stores it to file format that can be burned into the PROM Host Boot Mode In this scheme the target processor is a slave to a host system After reset the processor delays program execution until the slave gets signalled by the host system that the boot process has completed Depending on hardware capabilities there are two different methods of host booting In the first case the host system has full control over all target memories The host halts the target while initializing all memories as required In the second case the host communicates by a certain handshake with the boot kernel running on the target processor This kernel may execute from on chip ROM or may be preloaded by the host devices into the processor s SRAM by any bootstrapping scheme 1 14 VisualDSP 5 0 Loader and Utilities Manual Introduction The loader splitter utility generates a file that can be consumed by the host device It depends on the intelligence of the host device and on the target architecture whether the host expects raw application data or a
225. load control and corresponding setting When satisfied with the settings click OK to complete the load setup Table 3 14 Base Load Page Settings for ADSP BF53x BF561 Processors Setting Description Load Selections for the loader utility The options are e Options default boot options this section e Compression specification for zLib compression applies to the ADSP BF531 BF532 BF533 BF534 ADSP BF536 and ADSP BF537 processors see page 3 49 For the ADSP BF535 processor based projects the compression is not available e Kernel specification for a second stage loader Can be used to override the default boot kernel if there is one by default as on the ADSP BF535 processors see page 3 76 e Splitter specification for the no boot mode see page 3 78 If you do not use the boot kernel for the ADSP BF535 processors the Kernel page appears with all kernel option fields grayed out The loader utility does not search for the boot kernel if you boot from the on chip ROM by setting the no2kernel command line switch as described on page 3 65 For the ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 BF561 processors which do not have software boot kernels by default select the boot kernel to use one Boot mode Boot format Output width Specifies flash PROM SPI SPI slave UART TWI or FIFO as a boot source Specifies Intel hex ASCII include or binary format Specifies eight or 16 b
226. loadable 1dr file At power up after the chip reset the booting process includes the follow ing steps l Based on the boot type an appropriate DMA channel is automati cally configured for a 384 word 32 bit transfer or a 256 word 48 bit transfer This transfer boot loads the boot kernel program into the processor memory VisualDSP 5 0 Loader and Utilities Manual 6 3 ADSP 2126x 2136x 2137x 2146x Proc essor Booting 2 The boot kernel runs and loads the application executable code and data 3 The boot kernel overwrites itself with the first 256 48 bit words of the application at the end of the booting process After that the application executable code starts running The boot type selection directs the system to prepare the appropriate boot kernel Boot Mode Selection Unlike earlier SHARC processors ADSP 2126x 2136x 2137x 2146x pro cessors do not have a boot memory select BMS pin On the ADSP 2126x 2136x 2137x 2146x processor the boot type is determined by sampling the state of the BOOT_CFGx pins as described in Table 6 1 and Table 6 2 A description of each boot type follows in ADSP 2126x 2136x 2137x 2146x Processors Boot Modes Table 6 1 ADSP 2126x 2136x 2137x Boot Mode Pins BOOT_CFG 1 0 Boot Mode Boot Mode Selection 00 SPI slave bspislave 01 SPI master SPI flash SPI PROM ora bspiflash host processor via SPI master mode bspiprom bspim
227. loader proc ADSP 21xxx h help where Xxx is 060 061 062 065L or 160 to obtain help for SHARC processors By default the h switch alone provides help for the loader driver jidffexe filename Specifies the processor ID The i d fexe switch directs the loader util ity to use the processor ID for the corresponding executable file filename parameter when producing a boot loadable file for a multi processor system This switch is used to produce a boot loadable file that boots multiple processors from a single EPROM Valid values for are 1 2 3 4 5 and 6 Do not use this switch for single processor systems For single processor systems use fi ename as a parameter without a switch For more infor mation refer to ADSP 2106x 21160 Processor ID Numbers on page 4 24 idffref N Points the processor ID loader jump table entry to the ID M image If the executable file for the JF processor is identical to the executable of the N processor the switch can be used to set the PROM start address of the processor with ID of to be the same as for the processor with ID of N This effectively reduces the size of the loader file by pro viding a single copy of an executable to two or more processors in a multiprocessor system For more information refer to ADSP 2106x 21160 Processor ID Numbers on page 4 24 VisualDSP 5 0 Loader and Utilities Manual 4 29 ADSP 2106x 21160 Proces
228. m asm linker T 161_ldr ldf my_prom doj Host Boot The default boot kernel source file for host booting is 161_host asm After copying the default file to my_host asm and modify ing it to suit your system use the following command lines to rebuild the boot kernel easm21k proc ADSP 21161 my_host asm linker T 161_ldr ldf my_host doj VisualDSP 5 0 Loader and Utilities Manual 5 19 ADSP 21161 Proc essor Booting Link Boot The default boot kernel source file for link booting is 161_link asm After copying the default file to my_link asm and modify ing it to suit your system use the following command lines to rebuild the boot kernel easm21k proc ADSP 21161 my_link asm linker T 161_ldr ldf my_link doj SPI Boot The default boot kernel source file for link booting is 161_SPI asm After copying the default file to my_SP1 asm and modifying it to suit your system use the following command lines to rebuild the boot kernel easm21k proc ADSP 21161 my_SPI asm linker T 161_ldr ldf my_SPI doj Loader File Issues If you modify the boot kernel for the EPROM host SPI or link booting modes ensure that the seg_ldr memory segment is defined in the 1df file Refer to the source of this memory segment in the 1af file located in the 1dr directory of the of the target processor Because the loader utility uses the address of 0x40004 for the first location of the reset vector during the boot load process avoid placing code at
229. me boot stream formats enable them to be organized as a linked list The next dxe pointer NDP is simply a pointer to a location where the next application s boot stream resides Preboot Routine A preboot routine is present in the boot ROM of parts that feature OTP memory on a processor Preboot reads OTP memory and customizes sev eral MMR registers based on factory and user instructions as programmed to OTP memory A preboot routine executes prior to the boot kernel Program Development Flow Figure 1 1 is a simplified view of the application development flow The development flow can be split into three phases 1 Compiling and Assembling 2 Linking 3 Loading Splitting or Both A brief description of each phase follows VisualDSP 5 0 Loader and Utilities Manual 1 7 Program Development How ASSEMBLER AND OR COMPILER LOADER AND OR SPLITTER fi SOURCE FILES TARGET SYSTEM ATT BOOTING UPON RESET EXTERNAL PROCESSOR MEMORY Figure 1 1 Program Development Flow Compiling and Assembling Input source files are compiled and assembled to yield object files Source files are text files containing C C code compiler directives possibly a mixture of assembly code and directives and typically preprocessor com mands The assembler and compiler are documented in the VisualDSP 5 0 Assembler and Preprocessor Manual and VisualDSP 5 0 C C Compiler and Library Manual which are pa
230. mniviciabinaletenanuaneiaaans xvi Produet Tntormatioi srsrintorosineireniniar aeai xvi Anales Derices Web SIE rarnnnenirnia ee xvi VisualDSP Online Documentation sosrersiissnisriirarias xvii Se Library CD arises xviii MNotacon Cohet On cei eee oes xviii INTRODUCTION ari ei of Tomi sacanear a ee 1 2 Program Development FLOW a csc cetrcsansnccecivecccsrdsecaainoretnaca 1 7 Compiling and Assembling csnocirnrsnsnendinneusenniunia 1 8 ETE A ee ee 1 8 Loading SOs OF Boti srrenearserirenenri n eden 1 9 VisualDSP 5 0 Loader and Utilities Manual ill CONTENTS Non bootable Files Versus Boot loadable Files eeseeeees 1 10 Loader Utility Ips prosara 1 11 Splirter Urilicy Operations accede rec avaancenetnandodsacapoenanestad 1 12 Duot Modis a ee 1 13 Wet Mode assisted ntinsniiaalentietiel eget Gheadiai inane eae 1 13 PROM Boot Mode cciieecernanneteioamesrisnieiennees 1 14 Host Doct Made arseenia N 1 14 Beet Be esnean N 1 15 Boor Ne he aria haces ae ie at te cil gained nde stu batdia 1 16 File Searches ae nny ne OR Peo RRP ERODE ENT te nnOT AR 1 17 LOADER SPLITTER FOR ADSP BF51X BF52X BF54X BLACKFIN PROCESSORS ADSP BF51x BF52x BF54x Processor Booting essre 2 2 ADSP BF51x BF52x BF54x Processor Loader Guide 0008 2 5 Using Blackfin Loader Command Line sviesesne 2 6 File eree a 2 7 File Extensions sip scinlancsatediccnciceahradennsenbuascineidnsionesicdinsthedaebiuiennsesied 2 7 ADSP BF51x BF52x BF54x Blackfin
231. n of the specified processor The switch parameter represents a silicon revision of the processor specified by the proc processor switch The parameter takes one of three forms e The none value indicates that the VisualDSP ignores sili con errata e The value indicates one or more decimal digits followed by a point followed by one or two decimal digits Examples of revisions are 0 0 1 12 23 1 Revision 0 1 is distinct from and lower than revision 0 10 The digits to the left of the point specify the chip tapeout number the digits to the right of the point identify the metal mask revision number The number to the right of the point cannot exceed decimal 255 e The any value indicates that VisualDSP produces an out put file that can be run at any silicon revision The switch generates either a warning about any potential anomalous conditions or an error if any anomalous conditions occur In the absence of the silicon revision switch the loader selects the greatest silicon revision it is aware of if any S In the absence of the switch parameter a valid revision value si revision alone or with an invalid value the loader generates an error Directs the splitter utility to show its version information 8 8 VisualDSP 5 0 Loader and Utilities Manual Splitter for SHARC and TigerSHARC Processors VisualDSP Interface Split Page After selecting a Splitter file as the target type on the Project page in
232. n affects more or less the outcome of the data compression Streams in decompression windows of different sizes are in general different and most likely not compatible to each other If you are building a custom decompression kernel ensure the same compression window size is used for both the loader utility and the kernel In general a bigger compression window size leads to a smaller outcome stream How ever the benefit of a big window size is marginal in some cases An outcome of the data compression depends on a number of factors and a compression window size selection is only one of them The other impor tant factor is the coding structure of an input stream A compression window size selection can not cause a much smaller outcome stream if the compression ability of the input stream is low Uncompressed Streams Following the compressed streams the loader utility file includes the uncompressed streams The uncompressed streams include application codes conflicted with the code in the initialization blocks in the proces sor s memory spaces and a final block The uncompressed stream includes 6 38 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2126x 2136x 2137x 2146x SHARC Processors only a final block if there is no conflicted code The final block can have a zero byte count The final block indicates the end of the application to the initialization code Overlay Compression The loader utility compresses
233. n booting EPROM boot of multiple processors is similar to a single processor EPROM boot When booting a multiprocessor system through a single EPROM e Connect all BMS pins to EPROM e Processor with ID of 1 boots first The other processors follow e The EPROM boot kernel accepts multiple dxe files and reads the ID field in SYSTAT to determine which area of EPROM to read e All processors require a software flag or hardware signal FLAG pins to indicate that booting is complete VisualDSP 5 0 Loader and Utilities Manual 4 23 ADSP 2106x 21160 Proc essor Booting When booting a multiprocessor system through an external port e The host can use the host interface e A SHARC processor that is EPROM host or link booted can boot the other processors through the external port host boot mode For multiprocessor EPROM booting select the Multiprocessor check box on the Load page of the Project Options dialog box or specify the idlexe switch on the loader command line These options specify the executable file targeted for a specific processor Do not use the idlexe switch to EPROM boot a single processor whose ID is 0 Instead name the executable file on the command line without a switch For a single processor with 1D 1 use the idlexe switch ADSP 2106x 21160 Processor ID Numbers A single processor system requires only one input dxe file without any prefix and suffix to the input file name for example elfl
234. n page A 2 e Assembly Initialization Data Files on page A 2 e Header Files on page A 3 e Linker Description Files on page A 4 e Linker Command Line Files on page A 4 VisualDSP 5 0 Loader and Utilities Manual A 1 Source Files C C Source Files C C source files are text files c cpp cxx and so on containing C C code compiler directives possibly a mixture of assembly code and directives and typically preprocessor commands Several dialects of C code are supported pure portable ANSI C and at least two subtypes of ANSI C with ADI extensions These extensions include memory type designations for certain data objects and segment directives used by the linker to structure and place executable files The C C compiler run time library as well as a definition of ADI extensions to ANSI C are detailed in the VisualDSP 5 0 C C Compiler and Library Manual for Blackfin Processors Assembly Source Files Assembly source files asm are text files containing assembly instructions assembler directives and optionally preprocessor commands For infor mation on assembly instructions see the Programming Reference manual for your processor The processor s instruction set is supplemented with assembly directives Preprocessor commands control macro processing and conditional assem bly or compilation For information on the assembler and preprocessor see the VisualDSP 5 0 Assem
235. n to 1 10 1 13 See also internal boot mode selecting with romsplitter switch 2 15 3 67 no boot mode Blackfin processors ADSP BF5 1x processors 2 3 ADSP BF52x 54x processors 2 4 ADSP BF531 2 3 4 6 7 8 9 processors 3 4 ADSP BF535 processors 3 21 ADSP BF561 processors 3 37 selecting 2 19 3 16 3 73 3 79 no boot mode SHARC processors ADSP 2106x 160 processors 4 2 4 6 4 16 ADSP 21161 processors 5 2 5 4 5 16 VisualDSP 5 0 Loader and Utilities Manual INDEX nofinalblock loader switch for Blackfin 3 65 nofinaltag loader switch for Blackfin 3 65 noinitcode loader switch for Blackfin 2 14 3 66 nokernel loader switch for ADSP 2126x 36x 37x 46x processors 6 46 loader switch for Blackfin 3 66 loader switch for SHARC 6 17 loader switch for TigerSHARC 7 4 7 10 non bootable files introduction to 1 10 1 15 creating from command line 8 2 creating from IDDE 8 9 ignoring ROM sections 8 5 specifying format 8 6 specifying name 8 5 specifying word width 8 4 8 6 NOP instruction 4 4 4 14 4 19 4 20 5 6 5 10 5 13 5 15 6 22 norom splitter switch 8 5 nosecondstageloader loader switch for Blackfin 3 66 nozeroblock loader switch for SHARC 5 30 6 47 numeric formats A 3 O o2 loader switch for Blackfin 2 12 2 14 3 63 3 66 object files doj A 5 o filename loader switch for Blackfin 2 14 3 66 loader switch for SHARC 4 30 5 30 6 47 loader switch for TigerSHARC 7 10
236. ncrement internal ptr EJ Ae A A A a Si ota Enable SPE interrupt Aea E eet Sec Fei bit clr IRPTL SPIHI Clear any pending SPI interr latch bit set IMASK SPIHI Enable SPI receive interrupt a bit set MODE1 IRPTEN Enable global interrupts AS FLUSH CACHE Remove any kernel instr s from cache Rean eni see Begin final DMA to overwrite this code Ki ustatl dm SPIDMAC bit set ustatl SPIDEN dm SPIDMAC ustatl Begin final DMA transfer Kof Rote ci ete Initiate self modifying sequence Xf JUMP 0x80004 DB Causes 0x80004 to be the return address when this DMA completes and the RTI at 0x80030 is executed Ky IDLE After IDLE patch then start ef IMASK 0 Clear IMASK on way to 0x80004 Ko PX ay VisualDSP 5 0 Loader and Utilities Manual 6 31 ADSP 2126x 2136x 2137x 2146x Proc essor Booting 1 2 3 4 When this final DMA completes the high priority SPI interrupt latched which triggers The IDLE in th IMASK is cleared the following chain of events e delayed branch to completes The PC now 0x80004 due to the JUMP RESET db is pushed on the PC stack and the processor vectors to 0x80030 to service the interrupt Meanwhile the load er anticipating this sequence has auto matically inserted an RTI instruction at 0x80030 The user instruction in in the FINAL_I the DMA was i The processor address stored RO RO R
237. nel 6 DMAC6 for boot ing The ADSP 21160 processors use DMAC8 for link port booting and DMAC10 for the host and EPROM booting When booting from an EPROM through the external port the ADSP 2106x 21160 processor reads boot data from an 8 bit exter nal EPROM When booting from a host processor through the external port the ADSP 2106x 21160 processor accepts boot data from a 8 or 16 bit host microprocessor When booting through the link port the ADSP 2106x 21160 pro cessor receives boot data as 4 bit wide data in link buffer 4 In no boot mode the ADSP 2106x 21160 processor begins exe cuting instructions from external memory Software developers who use the loader utility should be familiar with the following operations Power Up Booting Process on page 4 3 Boot Mode Selection on page 4 5 ADSP 2106x 21160 Boot Modes on page 4 7 ADSP 2106x 21160 Boot Kernels on page 4 16 ADSP 2106x 21160 Interrupt Vector Table on page 4 22 4 2 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2106x 21160 SHARC Processors e ADSP 2106x 21160 Multi Application Multi DXE Manage ment on page 4 23 e ADSP 2106x 21160 Processor ID Numbers on page 4 24 Power Up Booting Process The ADSP 2106x and ADSP 21160 processors include a hardware feature that boot loads a small 256 instruction program into the processors internal memory after power up or after the chip reset These in
238. net Web site The zLib1 dynamic link library is included in VisualDSP The library functions perform the boot stream compression and decompression proce dures when the appropriate options are selected for the loader utility The boot kernel with built in decompression mechanism must perform the decompression on the compressed boot stream in a booting process The default boot kernel with decompression functions are included in VisualDSP The loader compression switch directs the loader utility to perform the boot stream compression from the command line VisualDSP also offers a dedicated loader property page Load Compression to manage the compression from the graphical user interface VisualDSP 5 0 Loader and Utilities Manual 6 35 ADSP 2126x 2136x 2137x 2146x Proc essor Booting The loader utility takes two steps to compress a boot stream First the utility generates the boot stream in the conventional way builds data blocks then applies the compression to the boot stream The decompres sion initialization is the reversed process the loader utility decompresses the compressed stream first then loads code and data into memory seg ments in the conventional way The loader utility compresses the boot stream on the dxe by dxe basis For each input dxe file the utility compresses the code and data together including all code and data from any associated shared memory sm files The loader utility however doe
239. nput_file sl s2 s3 StripHex o file_name where input_file is the name of the 1dr file generated by the VisualDSP splitter utility Table B 1 shows optional switches used with the hexutil command Table B 1 Hex to S Record File Converter Command Line Switches Switch Description sl Specifies Motorola output format S1 s2 Specifies Motorola output format S2 53 Specifies the default output format Motorola S3 That is when no switch appears on the command lines the output file format defaults to 3 StripHex Generates an unformatted data file 0 Names the output file in the absence of the o switch causes the output file name to default to input_file s The Intel hex 32 and Motorola S record file formats are described on page A 6 and on page A 10 respectively B 2 VisualDSP 5 0 Loader and Utilities Manual Utilities elf2fit ELF to BFLT File Converter The ELF to BFLT file converter e1f2f1t exe utility converts a dxe file in Executable and Linkable Format ELF to Binary Flat Format BELT The bf1t file contains three output sections text data and bss Output sections are defined by the ELF file standard The bf1t file can be loaded and executed in an environment running a uClinux operating system For more information on the BFLT file format see uClinux Web site http www beyondlogic org uClinux bflt htm The e1f2f1t currently supports ELF fil
240. oader proc ADSP 21060 bprom Input dxe A multiprocessor system requires a distinct processor ID number for each input file on the command line A processor ID is provided via the i dftexe fi ename dxe switch where is 0 to 6 In the following example the loader utility processes the input file Input1 dxe for the processor with an ID of 1 and the input file Input2 dxe for the processor with an ID of 2 elfloader proc ADSP 21060 bprom idlexe Inputl dxe id2exe Input2 dxe If the executable for the processor is identical to the executable of the n processor the output loader file contains only one copy of the code from the input file elfloader proc ADSP 21060 bprom idlexe Input dxe id2ref 1 4 24 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2106x 21160 SHARC Processors The loader utility points the id 2 exe loader jump table entry to the id 1 exe image effectively reducing the size of the loader file ADSP 2106x 21160 Processor Loader Guide Loader operations depend on the loader options which control how the loader utility processes executable files You select features such as boot modes boot kernels and output file formats via the loader options These options are specified on the loader utility s command line or via the Load page of the Project Options dialog box in the VisualDSP environment When you open the Load page the default loader settings for the selected processor are already set
241. oader Output Files in Intel Hex 32 Format seese A 6 Loader Output Files in Include Format sississsussesevisrcriresess A 8 Loader Output Files in Binary Format srurssrarinkaradnrnesi A 9 Output Files in Motorola S Record Format esesessessrssrsserr A 10 Splitter Output Files in Intel Hex 32 Format ssiccienvscrtvcaciers A 12 Splitter Output Files in Byte Stacked Format s0sscs0 A 12 Splirter Output Files in ASCII Format osc accceaseosdscnscdsyatecensende A 14 i Pe rnr a A AS RR A 15 Format Referentes etasseiniisareciedaaierctsaaciakenninseereiasacianieuaeaieiideniiols A 16 UTILITIES hexutil Hex 32 to S Record File Converter ssessssssssseessssserssssese B 2 elf2iit ELF to BELT File Converter anrsnisriorsniargbunsnniei B 3 Prop BFLT Pils Dumper sosrerasrsrener an B 4 INDEX xii VisualDSP 5 0 Loader and Utilities Manual PREFACE Thank you for purchasing Analog Devices Inc development software for Analog Devices embedded processors Purpose of This Manual The VisualDSP 5 0 Loader and Utilities Manual contains information about the loader splitter program for Analog Devices processors The manual describes the loader splitter operations for these processors and references information about related development software It also provides information about the loader and splitter command line interfaces Intended Audience The primary audience for this manual is a programmer who is familiar with Analog Devices
242. oader utility generates and inserts a header at the beginning of a block of contiguous data and instructions in the loader file The kernel uses headers to properly place blocks into processor memory The archi tecture of the header follows the convention used by other SHARC processors For all of the ADSP 2126x 2136x 2137x 2146x processor boot types the structures of block header are the same The header consists of three 32 bit words the block tag word count and destination address The order of these words is as follows 0x000000TT First word Tag of the data block T 0x0000CCCC Second word Data word length or data word count C of the data block OxAAAAAAAA Third word Start address A of the data block ADSP 2126x 2136x 2137x 2146x Processor Block Tags Table 6 12 details the ADSP 2126x 2136x 2137x 2146x processor block tags Table 6 12 ADSP 2126x 2136x 2137x 2146x Processor Block Tags Tag Count Address Padding 0x0 None FINAL_INIT 0x1 Number of 16 32 Logical short normal None ZERO_LDATA or 64 bit words or long word address 0x2 Number of 48 bit Logical normal word None ZE RO_L482 words address VisualDSP 5 0 Loader and Utilities Manual 6 23 ADSP 2126x 2136x 2137x 2146x Proc essor Booting Table 6 12 ADSP 2126x 2136x 2137x 2146x Processor Block Tags Tag Count Address Padding 0x3 Number
243. oc processor Part number of the processor for example proc ADSP 21262 for which the loadable file is built The proc switch is mandatory e switch One or more optional switches to process Switches select operations and boot modes for the loader utility A list of all switches and their descriptions appear in Table 6 18 on page 6 44 Command line switches are not case sensitive and may be placed on the command line in any order The following command line elfloader Input dxe bSPIflash proc ADSP 21262 runs the loader utility with e Input dxe Identifies the executable file to process into a boot loadable file Note that the absence of the o switch causes the output file name to default to Input 1dr 6 42 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2126x 2136x 2137x 2146x SHARC Processors e bspiflash Specifies SPI flash port booting as the boot type for the boot loadable file e proc ADSP 21262 Specifies ADSP 21262 as the target processor File Searches File searches are important in loader processing The loader utility sup ports relative and absolute directory names default directories and user selected directories for file search paths File searches occur as described on page 1 17 File Extensions Some loader switches take a file name as an optional parameter Table 6 17 lists the expected file types names and extensions Table 6 17 File Extensions Extension
244. oes not expect those files to appear on a command line or on the Load property page The loader utility finds these files in the directory of the associated dxe files in the current working directory or in the directory specified in the 1df file VisualDSP 5 0 Loader and Utilities Manual 3 59 ADSP BF53x BF561 Processor Loader Guide Blackfin Loader Command Line Switches A summary of the Blackfin loader command line switches appears in Table 3 10 Table 3 10 Blackfin Loader Command Line Switch Summary Switch Description b prom The b prom flash spi spislave UART TWI FIFO switch b flash specifies the boot mode and directs the loader utility to prepare a b spi boot loadable file for the specified boot mode Valid boot modes b spislave include PROM flash SPI SPI slave UART TWI and FIFO b UART b TWI SPI slave UART and TWI boot modes are for the b FIFO ADSP BF531 BF532 BF533 BF534 BF536 BF537 and ADSP BF538 BF539 processors FIFO boot mode is for the ADSP BF534 BF536 and ADSP BF537 processors of silicon revision 0 4 or newer only If b does not appear on the command line the default is b flash baudrate The baudrate switch accepts a baud rate for SPI booting only Valid baud rates and corresponding values are e 500K 500 kHz the default value e 1M 1MHz e 2M 2 MHz Boot kernel loading supports an SPI baud rate up to 2 MHz Applies to the ADSP BF53
245. of 16 bit Logical short word If count is odd pad with INIT_L16 words address 16 bit zero word see INIT_L16 Blocks on page 6 27 for details 0x4 Number of 32 bit Logical normal word None INIT_L32 words address 0x5 Number of 48 bit Logical normal word If count is odd pad with INIT_L48 words address 48 bit zero word see INIT_L48 Blocks on page 6 26 for details 0x6 Number of 64 bit Logical long word None see INIT_L64 INIT_L64 words address Blocks on page 6 28 for details 0x7 Number of 32 bit Physical external None ZERO_EXT8 words address 0x8 Number of 32 bit Physical external None ZERO_EXT16 words address 0x9 Number of 32 bit Physical external None INIT_EXT8 words address OxA Number of 32 bit Physical external None INIT_EXT16 words address 0xB Processor IDs Offset to the next pro None MULTI_PROC for bits 0 7 cessor ID in words ADSP 21367 see on page 6 33 for 32 bits ADSP 21368 details ADSP 21369 ADSP 2137x ADSP 2146x 0x0 msg_word1 msg_word2 None see Internal Boot USR_MESG Mode on page 6 17 for more info on msgword 1 The count is the actual number of words and does NOT included padded words added by the loader utility 6 24 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2126x 2136x 2137x 2146x SHARC Processors 2 40 bit data and 48 bit words are treated identically The ADSP 2126x 2136x 2137x 2146x processor uses eleven block tags a l
246. oint specify the chip tapeout number the digits to the right of the point identify the metal mask revision number The number to the right of the point cannot exceed decimal 255 e The none value indicates that the VisualDSP ignores silicon errata e The any value indicates that VisualDSP produces an output file that can be run at any silicon revision The switch generates either a warning about any potential anoma lous conditions or an error if any anomalous conditions occur S In the absence of the silicon revision switch the loader utility selects the default silicon revision it is aware of if any The v switch directs the loader utility to output verbose loader messages and status information as the loader processes files width The width 8 16 32 switch specifies an external memory device width in bits to the loader utility in flash PROM boot mode default is eight For FIFO boot mode the only valid width is 16 For SPI TWI and UART boot modes the only valid width is eight 2 16 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF51x BF52x BF54x Blac kfin Proc essors ADSP BF51x BF52x BF54x Multi DXE Loader Files An ADSP BF5 1x BF52x BF54x loader 1dr file can contain data of multiple application dxe files At boot time the boot kernel boots one application file exclusively or one application file initiates the boot of the next application file In
247. oot With Sec ond Stage Loader OUTPUT LDR FILE 4 BYTE HEADER FOR BYTE COUNT N BYTE 0 BYTE 1 BYTE 2 BYTE 0 BYTE 2 BYTE 4 BYTE COUNT FOR 2nd STAGE LOADER 4 2nd STAGE SEE ALSO LOADER FIGURE 3 12 APPLICATION SEE ALSO CODE FIGURE 3 14 iN BLOCKS D15 D8 D7 DO Figure 3 14 Loader File for 16 bit Flash PROM Boot With Second Stage Loader 3 30 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Proc essors Global Headers Following the second stage loader code and address in a loader file there is a 4 byte global header The header provides the global settings for a booting process see Figure 3 15 OUTPUT LDR FILE BYTE COUNT FOR A PWIES BYTE COUNT N q 2d STAGE LOADER NBYTES 2nd STAGE LOADER L2 MEMORY END ADDRESS 4 BYTES 2 STAGE LOADER lt FROM WHICH 2d STAGE ADDRESS LOADER RUNS ABYTES GLOBAL HEADER lt SEE FIGURES 3 18 AND 3 19 4 BYTES SIZE OF APPLICATION CODE N1 N1 BYTES APPLICATION CODE Figure 3 15 Global Header A global header s bit assignments for eight and 16 bit Flash PROM boot are illustrated in Figure 3 16 EER EE PPE I E EETA LA L Number of hold time cycles 3 default Number of wait states 15 default 1 16 bit Admix 0 8 bit flash PROM 0 default Figure 3 16 Flash PROM Boot Global Header Bit Assignments VisualDSP 5 0 Loader and Utilities Manual 3 31 AD
248. opy of the code from the input file as directed by the command line switch idifref N used in the example elfloader proc ADSP 21161 bprom idlexe Input dxe id2ref 1 where 2 is the processor ID and 1 is another processor ID referenced by processor 2 The loader utility points the id 2 exe loader jump table entry to the id 1 exe image effectively reducing the size of the loader file VisualDSP 5 0 Loader and Utilities Manual 5 23 ADSP 21161 Processor Loader Guide ADSP 21161 Processor Loader Guide Loader operations depend on the loader options which control how the loader utility processes executable files You select features such as boot modes boot kernels and output file formats via the options The options are specified on the loader utility s command line or via the Load page of the Project Options dialog box in the VisualDSP environment The Load page consists of multiple panes For information specific to the ADSP 21161 processor refer to the VisualDSP online help for that processor When you open the Load page the default loader settings for the selected processor are already set Use the Additional Options box to enter options that have no dialog box equivalent Option settings on the Load page correspond to switches displayed on the command line These sections describe how to produce a bootable loader 1dr file e Using ADSP 21161 Loader Command Line on page 5 25 e Using VisualDSP Inter
249. or a SPORT data file is one integer value per line Hexadecimal numbers do not require a 0x prefix A value can have any number of digits but is read into the SPORT register as follows e The hexadecimal number is converted to binary e The number of binary bits read in matches the word size set for the SPORT register and starts reading from the LSB The SPORT register then zero fills bits shorter than the word size or conversely trun cates bits beyond the word size on the MSB end In the following example Table A 9 a SPORT register is set for 20 bit words and the data file contains hexadecimal numbers The simulator converts the hex numbers to binary and then fills truncates to match the SPORT word size The A5A5 is filled and 123456 is truncated Table A 9 SPORT Data File Example Hex Number Binary Number Truncated Filled A5A5A 1010 0101 1010 0101 1010 1010 0101 1010 0101 1010 FFPEL 1111 11 1111 1111 000 1111 1111 1111 1111 0001 A5A5 1010 0101 1010 010 0000 1010 0101 1010 0101 5A5A5 0101 1010 0101 1010 010 0101 1010 0101 1010 0101 ges 0001 0001 0001 0001 000 0001 0001 0001 0001 0001 123456 0001 0010 0011 0100 0101 0110 0010 0011 0100 0101 0110 VisualDSP 5 0 Loader and Utilities Manual A 15 Format References Format References The following texts define industry standard file formats supported by VisualDSP Gircys G R 1988 Understanding
250. or execution The on chip boot ROM does this by checking bit 4 of the system reset configuration register SYSCR If bit 4 is not set the on chip boot ROM performs the full boot sequence If bit 4 is set the on chip boot ROM bypasses the full boot sequence and jumps to 0xF000 0000 VisualDSP 5 0 Loader and Utilities Manual 3 23 ADSP BF53x BF561 Proc essor Booting 3 Finally if bit 4 of the SYSCR register is not set performs the full boot sequence The full boot sequence includes v Checking the boot source either flash PROM or SPI mem ory by reading BMODE2 0 from the SYSCR register v Reading the first four bytes from location 0x0 of the exter nal memory device These four bytes contain the byte count N which specifies the number of bytes to boot in v Booting in N bytes into internal L2 memory starting at loca tion 0xF000 0000 v Jumping to the start of L2 memory for execution The on chip boot ROM boots in N bytes from the external memory These N bytes can define the size of the actual application code or a second stage loader that boots in the application code ADSP BF535 Processor Sec ond Stage Loader The only situation where a second stage loader is unnecessary is when the application code contains only one section starting at the beginning of L2 memory 0xF000 0000 A second stage loader must be used in applications in which multiple seg ments reside in L2 memory or in L1 memory and or SDRAM In add
251. ors 4 2 4 3 4 8 4 9 4 12 4 15 DMACS channels ADSP 2106x 160 processors 4 2 4 3 4 12 4 15 ADSP 21161 processors 5 2 5 12 5 13 5 14 5 15 DMA differences SHARC processors 5 6 5 10 5 13 DMA TigerSHARC processors controller 7 2 register 7 2 transfers 7 2 7 4 dmawidth loader switch for Blackfin 2 9 3 61 DMISO bit 6 9 6 11 doj object files A 5 DTYPE register 4 12 5 7 5 11 dual core architectures See ADSP BF561 processors DWARF 2 debugging information 1 8 dxe executable files 1 16 2 7 3 59 4 27 6 43 7 8 A 5 A 15 E EBOOT pins ADSP 2106x 160 processors 4 5 4 7 4 11 4 15 ADSP 21161 processors 5 4 5 5 5 6 5 9 5 13 5 15 5222 ECEP0 register 4 8 5 7 5 8 5 9 5 11 ECPP register 6 6 ECx register 4 8 4 9 4 11 4 12 e filename loader switch for ADSP 2106x 160 processors 4 28 efilename loader switch for SHARC 5 28 EIEPO register 4 8 5 8 5 11 EIPP register 6 6 Elx register 4 8 4 9 4 12 elf2flt utility B 3 elfloader See loader ELF to BFLT file converter B 3 EMEP register 4 8 5 8 5 11 EMPP register 6 6 EM x register 4 8 4 9 4 12 enc dll_ filename loader switch for Blackfin 3 61 encryption functions 3 61 3 63 3 67 end of file records A 8 EPOI vector 4 13 5 9 5 12 EPBO buffer 4 11 4 12 EPROM boot mode SHARC processors ADSP 2106x 160 processors 4 2 4 5 4 7 4 9 4 11 4 23 4 24 ADSP 21161 processors 5 2 5 4 5 5 multiprocessor
252. ort 5 21 ADSP 2126x 36x 37x 46x processors boot modes 6 2 6 4 6 7 boot sequence 6 3 compression support 6 35 direct memory access See DMA DMACx ADSP 2136x 37x 46x processors multiprocessor support 6 33 ADSP BF5 1x processors boot modes 2 3 multi dxe loader files 2 17 ADSP BF52x 54x processors boot modes 2 4 multi dxe loader files 2 17 ADSP BF531 2 3 4 6 7 8 9 processors ADSP BF534 6 7 only boot modes 3 4 boot modes 3 3 boot sequence 3 8 boot streams 3 9 3 10 compression support 3 49 memory ranges 3 19 multi dxe loader files 3 46 on chip boot ROM 3 3 3 7 3 9 3 19 3 47 ADSP BF535 processors boot modes 3 16 3 21 3 79 boot sequence 3 24 boot streams 3 27 3 28 memory ranges 3 33 on chip boot ROM 3 21 3 23 3 25 second stage loader 3 24 VisualDSP 5 0 Loader and Utilities Manual I 1 INDEX ADSP BF561 processors boot modes 3 35 boot streams 3 37 3 40 dual core architecture 3 35 3 38 memory ranges 3 45 multi dxe loader files 3 46 multiprocessor support 3 44 on chip boot ROM 3 35 3 37 3 43 3 44 3 45 3 47 ALIGN directive 3 34 application loading Blackfin processors ADSP BF531 2 3 4 6 7 8 9 processors 3 9 3 12 3 48 ADSP BF535 processors 3 26 3 27 3 32 ADSP BF561 processors 3 37 3 38 3 44 3 45 3 48 application loading SHARC processors ADSP 2106x 160 processors 4 4 4 17 ADSP 21161 processors 5 3 5 5 5 9 ADSP 2126x 36x 37x 46x proces
253. ory with valid instruc tions at that location To create a proper ldr file that can be burned into either a parallel flash or EPROM device you must modify the standard LDF file in order for the reset vector to be located accordingly The following code fragments Listing 3 6 and Listing 3 7 illustrate the required modifications in case of an ADSP BF533 processor 3 16 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Processors Listing 3 2 Section Assignment LDF File Example MEMORY Off chip Instruction ROM in Async Bank 0 MEM_PROGRAM_ROM TYPE ROM START Ox20000000 END Ox2009FFFF WIDTH 8 Off chip constant data in Async Bank 0 MEM_DATA_ROM TYPE ROM START Ox200A0000 END OX200FFFFF WIDTH 8 On chip SRAM data is not booted automatically MEM_DATA_RAM TYPECRAM START OXFF903000 END OXFF907FFF WIDTH 8 Listing 3 3 ROM Segment Definitions LDF File Example PROCESSOR pO OUTPUT COMMAND_LINE_OUTPUT_FILE SECTIONS program_rom INPUT_SECTION_ALIGN 4 INPUT_SECTIONS OBJECTS rom_code gt MEM_PROGRAM_ROM data_ro INPUT_SECTION_ALIGN 4 INPUT_SECTIONS OBJECTS rom_data gt MEM_DATA_ROM data_sram VisualDSP 5 0 Loader and Utilities Manual 3 17 ADSP BF53x BF561 Proc essor Booting INPUT_SECTION_ALIGN 4 INPUT_SECTIONS OBJECTS ram_data gt MEM_DATA_RAM With the LDF
254. ost 2 Stores the SYSCON register value in R12 for restore 3 Enables interrupts and nesting for DMA transfer sets up the IMASK register to allow DMA interrupts and sets up the MODE1 register to enable interrupts and allow nesting VisualDSP 5 0 Loader and Utilities Manual 4 13 ADSP 2106x 21160 Proc essor Booting 4 Loads the DMA control register with 0x00A1 and sets up its param eters to read the data word by word from external buffer 0 Each word is read into the reset vector address refer to Table 4 2 on page 4 4 for dispatching The data through this buffer has a structure of boot section which could include more than one ini tialization block 5 Clears the BUSLCK bit in the MODE2 register to let the host write in the external buffer 0 right after the appropriate DMA channel is activated For information on the data structure of the boot section and ini tialization see ADSP 2106x 21160 Processor Boot Steams on page 4 17 6 Loads the first 256 words of target the executable file during the final initialization stage and then the kernel overwrites itself The final initialization works the same way as with EPROM booting except that the BUSLCK bit in the MODE2 register is cleared to allow the host to write to the external port buffer The default boot kernel for host booting assumes IMDW is set to 0 during boot loading except during the final initialization stage When using any power up booting mode
255. our specific input file the value can be within a subset of 0 32 The maskaddr switch requires romsplitter and affects the ROM section address only MaxBlockSize The MaxBlockSize switch specifies the maximum block size up to OX7FFFFFFO The value must be a multiple of 4 The default maximum block size is OxFFFO or the value specified by the MaxBlockSize switch MaxFillBlockSize The MaxFillBlockSize switch specifies the maximum fill block size up to OxFFFFFFO The value must be a multiple of two The default fill block size is OxFFFO VisualDSP 5 0 Loader and Utilities Manual 2 13 ADSP BF51x BF52x BF54x Processor Loader Guide Table 2 5 ADSP BF51x BF52x BF54x Loader Command Line Switch Summary Contd Switch Description MM The MM switch generates make dependencies while producing the output files Mo filename The Mo filename switch writes make dependencies to the named file Use the Mo switch with either M or MM If Mo is absent the default is a lt stdout gt display Mt target The Mt target switch specifies the make dependencies target output file Use the Mt switch with either M or MM If Mt is not present the default is the name of the input file with an 1dr extension NoInitCode The NoInitCode switch directs the loader utility not to expect an init code file The loader utility may expect an init code file specified through th
256. own in Table 4 8 and Table 4 9 The external port DMA channel 6 or 10 becomes active following reset it is initialized to set external port DMA enable and selects DTYPE for instruction words The packing mode bits PMODE are ignored and 48 to 8 bit packing is forced with least significant word first The UBWS and UBWM fields of the WAIT register are initialized to gen erate six wait states for the EPROM access in unbanked external memory space VisualDSP 5 0 Loader and Utilities Manual 4 9 ADSP 2106x 21160 Proc essor Booting The processor begins 8 bit DMA transfers from the EPROM to internal memory using the following external port data bus lines 023 16 for the ADSP 21060 61 62 processors 07 0 for the ADSP 21065L processors 039 32 for the ADSP 21160 processors Data transfers begin and increment after each access The external address lines ADDR31 0 start at 0x40 0000 for the ADSP 21060 61 62 processors 0x00 0000 for the ADSP 21065L processors 0x80 0000 for the ADSP 21160 processors The processor RD pin asserts as in a normal memory access with six wait states seven cycles After finishing DMA transfers to load the boot kernel into the pro cessor the BSO bit is cleared in the SYSCON register deactivating the BMS pin and activating normal external memory select The boot kernel uses three copies of SYSCON one that contains the original value of SYSCON a second that contains SYSCON with the
257. page in the VisualDSP Project Wizard modify the default load settings Project Options for An ADSP BF535 Based Project Compile p Eh General es Language Settings Boot Mode Boot Format Output Width fey MISRA C Flash PROM Intel hex Bit fs Preprocessor OSsPI Oascil 16 bit Eh Processor 1 O Include fs Processor 2 O Binary fea Profile guided Optimization EA Warning Wait state Hold time 2 Assemble 0 v 0 v Fb Gener al Use default start address E LDF Preprocessing Cl Verbose Eh Elimination Initialization file fy Processor Load Ee Output file fas Kernel Pes Splitter fey Pre build Additional options E Post build D Add Startup Code LDF Figure 3 26 Project Load Options Page for ADSP BF535 Processors The Load control in the Project tree control consists of multiple pages When you open the Load Options page also called loader property page view the default load settings for the selected processor As an example Figure 3 26 shows the ADSP BF535 processor s default load set tings for PROM booting The dialog box options are equivalent to the command line switches Refer to Blackfin Loader Command Line Switches on page 3 60 for more information about the switches 3 72 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Proc essors Using the page controls select or modify the load settings Table 3 14 describes each
258. pecial input pins that are interrogated when the processor awakes from either a reset or power down state See also Boot Modes on page 1 13 Boot Kernel A boot kernel is software that runs on the target processor It reads data from the boot source and interprets the data as defined in the boot stream format The boot kernel can reside in an on chip boot ROM or in an off chip ROM device Often the kernel has to be pre booted from the boot source before it can be executed In this case the loader utility puts a default kernel to the front of the boot image or allows the user to specify a customized kernel See also Boot Kernels on page 1 15 VisualDSP 5 0 Loader and Utilities Manual 1 3 Definition of Terms Boot ROM A boot ROM is an on chip read only memory that holds the boot kernel and in some cases additional advanced booting routines Second Stage Loader A second stage loader is a special boot kernel that extends the default boot ing mechanisms of the processor It is typically booted by a first stage kernel in a standard boot mode configuration Afterward it executes and boots in the final applications See also Boot Kernels on page 1 15 Boot Source A boot source refers to the interface through which the boot data is loaded as well as to the storage location of a boot image such as a memory or host device Boot Image A boot image that can be seen as the binary version of a loader file Usuall
259. processor The processor can be one of the following ADSP BF531 ADSP BF532 ADSP BF533 ADSP BF534 ADSP BF535 ADSP BF536 ADSP BF537 ADSP BF538 ADSP BF539 ADSP BF561 romsplitter The romsplitter switch creates a non bootable image only This switch overwrites the b switch and any other switch bounded by the boot mode In the 1df file declare memory segments to be split as type ROM The splitter skips RAM segments resulting in an empty file if all seg ments are declared as RAM The romsplitter switch supports hex and ASCII formats ShowEncryptionMessage The ShowEncryptionMessage switch displays a message returned from the encryption function VisualDSP 5 0 Loader and Utilities Manual 3 67 ADSP BF53x BF561 Processor Loader Guide Table 3 10 Blackfin Loader Command Line Switch Summary Contd Switch Description si revision none any The si revision none any switch provides a silicon revi sion of the specified processor The switch parameter represents a silicon revision of the processor specified by the proc processor switch The parameter takes one of three forms e The none value indicates that the VisualDSP ignores silicon errata e The value indicates one or more decimal digits followed by a point followed by one or two decimal digits Exam ples of revisions are 0 0 1 12 23 1 Revision 0 1 is dis tinct from and lower than revision 0 10
260. processor the kernel follows the following sequence 1 Each boot kernel begins with general initializations for the DAG reg isters appropriate interrupts processor ID information and various SDRAM or WAIT state initializations 2 Once the boot kernel has finished the task of initializing the pro cessor the kernel initializes processor memory both internal and external with user application code ADSP 2106x 21160 Processor Boot Steams The structure of a loader file enables the boot kernel to load code and data block by block In the loader file each block of code or data is pre ceded by a block header which describes the block length placement and data or instruction type After the block header the loader utility out puts the block body which includes the actual data or instructions for placement in the processor memory The loader utility however does not output a block body if the actual data or instructions are all zeros in value This type of block called a zero block Table 4 12 describes the block header and block body formats The loader utility identifies the data type in the block header with a 16 bit tag that precedes the block Each type of initialization has a unique tag number The tag numbers and block types are shown in Table 4 13 VisualDSP 5 0 Loader and Utilities Manual 4 17 ADSP 2106x 21160 Proc essor Booting Table 4 12 Boot Block Format First word Bits 16 47 are not used
261. processors The manual assumes the audience has a working knowledge of the appropriate processor architecture and instruc tion set Programmers who are unfamiliar with Analog Devices processors can use this manual but should supplement it with other texts such as hardware reference and programming reference manuals that describe their target architecture VisualDSP 5 0 Loader and Utilities Manual xiii CONTENTS Manual Contents The manual contains Chapter 1 Introduction Chapter 2 Loader Splitter for ADSP BF51x BF52x BF54x Blackfin Processors Chapter 3 Loader Splitter for ADSP BF53x BF561 Blackfin Processors Chapter 4 Loader for ADSP 2106x 21160 SHARC Processors Chapter 5 Loader for ADSP 21161 SHARC Processors Chapter 6 Loader for ADSP 2126x 2136x 2137x 2146x SHARC Processors Chapter 7 Loader for TigersHARC Processors Chapter 8 Splitter for SHARC and TigerS HARC Processors Appendix A File Formats Appendix B Utilities What s New in This Manual This revision of the VisualDSP 5 0 Loader and Utilities Manual docu ments loader and splitter functionality that is new to VisualDSP 5 0 and updates up to update 6 including support for new SHARC processors In addition modifications and corrections based on errata reports against the previous revision of the manual have been made xiv VisualDSP 5 0 Loader and Utilities Manual
262. put file options such as the Boot Mode source Boot Format and Output Width 6 Select Change hex output kernel code start address to specify the Start address in hex format for the second stage loader code This option allows you to place the second stage loader file at a specific location within the flash PROM 7 Click OK to complete the loader utility setup Using VisualDSP ROM Splitter Unlike the loader utility the splitter utility does not format the applica tion data when transforming a dxe file to an 1dr file The splitter utility emits raw data only Whether data and or instruction sections are pro cessed by the loader or by the splitter utility depends upon the LDF s TYPE command Sections declared with TYPE RAM are consumed by the loader utility and sections declared by TYPE ROM are consumed by the splitter Figure 2 3 shows a sample Load Splitter page with ROM splitter options With the Enable ROM splitter box unchecked only TYPE RAM segments are processed and all TYPE ROM sections are ignored by the loader utility If the box is checked TYPE RAM sections are ignored and TYPE ROM seg ments are processed by the splitter utility The Mask Address field masks all EPROM address bits above or equal to the number specified For example Mask Address 29 default masks all bits above and including A29 ANDed by 0x1FFF FFFF Thus 0x2000 0000 becomes 0x0000 0000 The valid numbers are integers 0 thro
263. r v Data bank A SRAM 0xFF80 4000 O0xFF80 7FFF v Data bank B SRAM 0xFF90 4000 0xFF90 7FFF VisualDSP 5 0 Loader and Utilities Manual 3 19 ADSP BF53x BF561 Proc essor Booting v Instruction SRAM 0xFFAO 0000 OxFFAL 3FFF e ADSP BF537 processor v Data bank A SRAM 0xFF80 0000 O0xFF80 7FFF v Data bank B SRAM 0xFF90 0000 OxFF90 7FFF v Instruction SRAM 0xFFAO 0000 OxFFAL 3FFF e ADSP BF538 processor v Data bank A SRAM 0xFF80 4000 O0xFF80 7FFF v Data bank B SRAM 0xFF90 4000 0xFF90 7FFF v Instruction SRAM 0xFFAO 8000 0xFFA1 3FFF e ADSP BF539 processor v Data bank A SRAM 0xFF80 0000 O0xFF80 3FFF v Data bank B SRAM 0xFF90 2000 0xFF90 7FFF v Instruction SRAM 0xFFAO 0000 OxFFAL 3FFF e SDRAM memory v Bank 0 0x0000 0000 0x07FF FFFF Booting to scratchpad memory 0xFFB0 0000 is not supported SDRAM must be initialized by user code before any instructions or data are loaded into it 3 20 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Proc essors ADSP BF535 Processor Booting Upon reset an ADSP BF535 processor jumps to an external 16 bit mem ory for execution if BMODE 000 or to the on chip boot ROM if BMODE 001 010 or 011 The ADSP BF535 Processor On Chip Boot ROM details can be found on page 3 23 Table 3 5 summarizes the boot modes and code execution start addresses for the ADSP BF535 processors Table 3 5
264. r or lt install_path gt 211xx ldr directory of VisualDSP The loader utility generates a warning when vector address 0x20004 for the ADSP 21060 61 62 processors 0x40004 for the ADSP 21160 proces sors or 0x8004 for the ADSP 21065L processors does not contain NOP or IDLE Because the boot kernel uses this address for the first location of the reset vector during the boot load process avoid placing code at this address When using any of the processor s power up boot modes ensure that the address does not contain a critical instruction Because the address is not executed during the booting sequence place a NOP or IDLE instruc tion at this location The boot kernel project can be rebuilt from the VisualDSP IDDE The command line can also be used to rebuild various default boot kernels for the ADSP 2106x 21160 processors 4 20 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2106x 21160 SHARC Processors EPROM Booting The default boot kernel source file for the ADSP 2106x EPROM booting is 060_prom asm Copy this file to my_prom asm and modify it to suit your system Then use the following commands to rebuild the boot kernel easm21k 21060 my_prom asm or easm21k proc ADSP 21060 my_prom asm linker T 060_ldr ldf my_prom doj Host Booting The default boot kernel source file for the ADSP 2106x host booting is 060_host asm Copy this file to my_host asmand modify it to suit your system Then use the followin
265. r silicon revi sion boot mode or width is changed Use default start address Specifies the default flash PROM output start address in hex format for the application code Start address Specifies a flash PROM output start address in hex format for the appli cation code Verbose Generates status information as the loader utility processes the files Initialization file Directs the loader utility to include the initialization file init code Use default decom pression INIT file Directs the loader utility to include the default decompression initializa tion file init code The initialization file selection is active for the ADSP BF531 BF532 BF533 and ADSP BF561 processors For the ADSP BF535 processors the field is grayed out Output file Names the loader utility s output file Additional options Specifies additional loader switches You can specify additional input files for a multi input system Type the input file names with the paths if the files are not in the current working directory separate two file names with a space in order for the loader utility to retrieve the files Note The loader utility processes the input files in the order in which the files appear on the command line generated from the property page 3 74 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Proc essors Using VisualDSP Compression
266. r file can be formatted as binary ASCII or Intel hex style An 1dr file contains the boot stream in a format expected by the on chip boot kernel Loader utility operations depend on the loader options which control how the utility processes executable files You select features such as boot modes boot kernels and output file formats via the options The options are specified on the loader utility s command line or via the Load page of the Project Options dialog box in the VisualDSP environment The Load page consists of multiple panes When you open the Load page the default loader settings for the selected processor are set already Option settings on the Load page correspond to switches displayed on the command line These sections describe how to produce a bootable single and multiple or non bootable loader file e Using Blackfin Loader Command Line on page 2 6 e sing VisualDSP Loader on page 2 18 cc U e Using VisualDSP Second Stage Loader on page 2 20 U cc sing VisualDSP ROM Splitter on page 2 22 VisualDSP 5 0 Loader and Utilities Manual 2 5 ADSP BF51x BF52x BF54x Processor Loader Guide Using Blackfin Loader Command Line The ADSP BF51x BF52x BF54x Blackfin loader utility uses the following command line syntax For a single input file elfloader inputfile proc processor switch For multiple input files elfloader inputfilel inputfile2 proc processor
267. r has completed its boot and is executing instructions normally The first instruction at the EPOI interrupt vector location address 0x40050 should be an RTI return from interrupt This process returns execution to the reset routine at location 0x40005 where normal program execution can resume After reaching this point a pro gram can write a different service routine at the EPOI vector location 0x40050 Host Boot Mode The processor can boot from a host processor through the external port Host booting is selected when the EB00T and LBOOT inputs are low and BMS is high Configured for host booting the processor enters the slave mode after reset and waits for the host to download the boot program The DMAC10 control register is initialized for booting packing boot data into 48 bit instructions Channel 10 of the IO processor s DMA control ler is used to transfer instructions to internal memory Processors accept data from 8 or 16 bit host microprocessor or other external devices VisualDSP 5 0 Loader and Utilities Manual 5 9 ADSP 21161 Proc essor Booting After the boot process loads 256 words into memory locations 0x40000 through 0x400FF the processor begins executing instructions Because most processor programs require more than 256 words of instructions and initialization data the 256 words typically serve as a loading routine for the application VisualDSP includes loading routines boot kernels that can load entir
268. rce files 7 4 specifying user kernel 7 10 VisualDSP 5 0 Loader and Utilities Manual 1 9 INDEX kf hex ascii binary include loader switch for Blackfin 2 12 3 63 knl kernel code files 2 7 3 59 kp loader switch for Blackfin 2 12 2 14 3 63 3 66 kWidth loader switch for Blackfin 2 13 3 64 L L1 memory Blackfin processors ADSP BF531 2 3 4 6 7 8 9 processors 3 7 3 12 3 19 ADSP BF535 processors 3 24 3 33 3 34 ADSP BF561 processors 3 37 3 45 L2 memory Blackfin processors ADSP BF535 processors 3 23 3 24 3 33 3 34 ADSP BF561 processors 3 44 3 45 last blocks Blackfin processors ADSP BF531 2 3 4 6 7 8 9 processors 3 12 3 13 ADSP BF561 processors 3 39 LBOOT pins ADSP 2106x 161 processors 4 5 4 7 4 11 ADSP 21161 processors 5 4 5 5 5 6 5 9 5 13 5 15 LCOM register 4 15 LCTL register 4 15 4 19 5 13 ldr loader output files ASCII format A 4 A 14 binary format A 9 hex 32 format A 6 include format files A 8 naming 2 14 3 66 7 10 specifying host bus width 5 29 6 45 least significant bit first LSB format 6 12 library files dlb A 5 link buffers 4 15 5 12 5 13 linker command line files txt A 4 description file LDF See ldf files memory map files map A 6 output files dxe sm ovl 1 8 A 5 linking introduction to 1 8 link port boot mode SHARC processors ADSP 2106x 160 processors 4 2 4 5 4 15 ADSP 21161 processors 5 2 5 4 5 12 l
269. repended to the stream is 32 bits in length An SPI host configured as a slave begins sending data to the processor while the processor is sending the 24 bit PROM read opcode These 24 bits must be zero filled because the processor discards the first 32 bit word that it receives from the slave The 0xA5 byte is only required for SPI master boot mode Figure 6 2 and Table 6 9 illustrates the first 32 bit word for both the SPI PROM and SPI master cases With bit reversing for SPI master boot mode the 32 bit word is handled according to the host width With bit reversing for SPI PROM boot the 8 bit word is reversed as a byte and prepended see Table 6 10 6 14 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2126x 2136x 2137x 2146x SHARC Processors hic SPI SLAVE READ Cun Xms5 N AT A0 y SPICLK Driven by MASTER MASTER OUT SLAVE IN mosi 1 gt Processor MASTER IN SLAVE OUT Slave Processor Tx s anytime SPICLK driven SPI SLAVE PROM SPI PROM doesnt drive data until it recieves a read command and address 7 X 0x00 oY 0x00 oY oxas 1st KNL y BYTE MISO i MASTER IN SLAVE OUT MISO t 1 i DATA clocked into DSP during this cycle MUST be OxA5 If slave device is an SPI PROM then the FIRST byte must be 0xA5 i Ifthe SPI slave device is a processor the FOURTH byte must be 0x45 I Figure 6 2 SPI Master Boot from a
270. riginal Data Packed into an Even hostwidth Number of 32 bit Words 32 16 8 1111222233334444 33334444 33334444 4444 44 11112222 11112222 3333 44 2222 33 1111 33 22 22 11 alte FINAL_INIT Blocks The final 256 instructions of the 1dr file contain the instructions for the IVT The instructions are initialized by a special self modifying subrou tine in the boot kernel see Listing 6 3 To support the self modifying code the loader utility modifies the FINAL_INIT block as follows 1 Places a multi function instruction at the fifth instruction of the block The loader utility places the instruction RO RO RO DM 14 M5 R9 PM 112 M13 R11 at 0x80004 for the ADSP 2126x processors or 6 28 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2126x 2136x 2137x 2146x SHARC Processors 0x90004 for the ADSP 2136x 2137x 2146x processors The instruction overwrites whatever instruction is at that address The opcode for this instruction is 0x39732D802000 2 Places an RTI instruction in the IVT The loader utility places an RTI instruction opcode 0x0B3E00000000 at the first address in the IVT entry asso ciated with the boot source either PROM or SPI Unlike the multifunction instruction placed at 0x80004 for the ADSP 2126x processors or 0x90004 for the ADSP 2136x 2137x 2146x proces sors which overwrites the data the loader utility preserves the user specified instruction which the RTI replaces
271. rnal memory Valid values range from 3 to 32765 cycles 32765 is the default value The time out value is directly related to the number of cycles the processor locks the bus for boot loading instructing the processor to lock the bus for no more than 2x timeout number of cycles When working with a fast host that cannot tolerate being locked out of the bus use a relatively small timeout value Outputs verbose loader messages and status information as the loader utility processes files VisualDSP 5 0 Loader and Utilities Manual Loader for TigerSHARC Processors Table 7 3 TigerSHARC Loader Command Line Switches Cont d Switch Description version Directs the loader utility to display its version information Type elfloader version to display the version of the loader drive Add the proc switch such asin elfloader proc ADSP TS201 version to display version information for the loader drive and TigerSHARC loader utility si revision The si revision none any switch provides a silicon revision d none any of the specified processor The switch parameter represents a silicon revision of the processor specified by the proc processor switch The parameter takes one of three forms e The none value indicates that the VisualDSP ignores sili con errata e The value indicates one or more decimal digits followed by a point followed by one or two decimal digits Examples of revisions are 0 0
272. rnel code processing The loader utility processes the kernel in eight bit widths regardless of the output width selection e For flash PROM booting the size of the output file depends on the width switch e For FIFO booting the only available width is 16 e For SPI booting the size of the output 1dr file is the same for both width 8 and width 16 The only differ ence is the header information ZeroPadForced The ZeroPadForced switch forces the loader utility to pad each data byte with a zero byte for 16 bit output Use this switch only if your system requires zero padding in a loader file Use this switch with caution arbitrating pad data with zeros can cause the loader file to fail The loader utility performs default zero padding auto matically in general Applies to the ADSP BF531 BF532 BF533 BF534 ADSP BF536 BF537 BF538 BF539 processors only Table 3 11 pFlag Values for ADSP BF531 BF532 BF533 Processors Silicon Revision 0 0 0 2 0 3 0 5 Width 8 16 8 16 Flash boot mode NONE NONE NONE NONE SPI boot mode NONE NONE SPI slave boot mode 1 15 PF1 15 1 The ADSP BF531 BF532 BF533 processors always have the RESVECT bit bit 2 in the block header flag word cleared VisualDSP 5 0 Loader and Utilities Manual 3 69 ADSP BF53x BF561 Processor Loader Guide Table 3 12 pFlag Values for ADSP BF534 BF536 BF537
273. rogram called a boot kernel into the processor s internal memory The boot kernel program may be stored on an external PROM a host pro cessor or another TigerSHARC processor The boot type is selected via the processor s boot mode select BMS pin as described in Boot Type Selection on page 7 3 After the boot kernel loads it executes itself and then loads the rest of the application program and data into the processor The combination of the boot kernel and the application program com prises a boot loadable file TigerSHARC processors support three booting modes EPROM flash host and link The boot loadable files for each of these modes pack the boot data into 32 bit instructions and use a DMA channel of the proces sors DMA controller to boot load the instructions Additionally there are several no boot modes which do not require kernels e In EPROM flash boot mode the loader utility generates a PROM image that contains all project data and loader code The project data is then stored in an 8 bit wide external EPROM After reset the processor performs a special booting scenario reading the EPROM content through the processor s external port and initial izing on chip and off chip memories e In host boot mode the processor accepts boot data from a 32 or 64 bit synchronous microprocessor host The host writes a boot loadable file to the processor s AUTODMA register through the processor s external port one 32
274. rt of the online help Linking Under the direction of the linker description file LDF and linker set tings the linker consumes separately assembled object and library files to yield an executable file If specified the linker also produces the shared memory files and overlay files The linker output dxe files conforms to the ELF standard an industry standard format for executable files The linker also produces map files and other embedded information DWARF 2 used by the debugger 1 8 VisualDSP 5 0 Loader and Utilities Manual Introduction These executable files are not readable by the processor hardware directly They are neither supposed to be burned onto an EPROM or flash memory device Executable files are intended for VisualDSP debugging targets such as the simulator or emulator Refer to the VisualDSP 5 0 Linker and Utilities Manual and online Help for information about linking and debugging Loading Splitting or Both Upon completing the debug cycle the processor hardware needs to run on its own without any debugging tools connected After power up the processor s on chip and off chip memories need to be initialized The pro cess of initializing memories is often referred to as booting Therefore the linker output must be transformed to a format readable by the processor This process is handled by the loader and or splitter utility The loader splitter utility uses the debugged and tested executable
275. s After copying the default file to my_prom asm and modifying it to suit your system use the following command lines to rebuild the boot kernel easm2lk proc ADSP 21262 my_prom asm linker T 2162x_ldr ldf my_prom doj SPI Booting The default boot kernel source file for link booting is 2126x_SPI asm for the ADSP 2126x processors After copying the default file to my_SPI asm and modifying it to suit your system use the following command lines to rebuild the boot kernel easm21k proc ADSP 21262 my_SPI asm linker T 2126x_ldr ldf my_SPI doj Loader File Issues If you modify the boot kernel for the PROM or SPI booting modes ensure that the seg_ldr memory segment is defined in the 1df file Refer to the source of this memory segment in the 1df file located in the 1dr installation directory of the target processor Because the loader utility uses the address of 0x80004 for the ADSP 2126x processors and the address of 0x9004 for the ADSP 2136x 2137x 2146x processors as the first location of the reset vector during the boot load process avoid placing code at the address When using any of the processor s power up booting modes ensure that VisualDSP 5 0 Loader and Utilities Manual 6 21 ADSP 2126x 2136x 2137x 2146x Proc essor Booting the address does not contain a critical instruction because the address is not executed during the booting sequence Place a NOP or IDLE in this loca tion The loader utility generates
276. s Contd Switch Description userkernele Directs the loader utility to use the specified userkerne and to ignore the default boot kernel for the boot loading routine in the output boot loadable file Note The boot kernel file selected with this switch must correspond to the boot type selected with the b switch If 1 does not appear on the command line the loader utility searches for a default boot kernel file in the installation directory see TigerSHARC Processor Boot Kernels on page 7 4 nokernel Supports internal boot mode The nokernel switch directs the loader utility not to include the boot kernel code into the loader 1dr file o filename p Ft Directs the loader utility to use the specified fi 7ename as the name of the loader output file If the fi 7 ename is absent the default name is the name of the input file with an 1dr extension Specifies the EPROM start address hex format for the boot load able file If the p switch does not appear on the command line the loader utility starts the EPROM file at address 0x0 in the EPROM this EPROM address corresponds to address 0x4000000 in a Tiger SHARC processor proc processor Specifies the target processor The processor can be one of the fol lowing ADSP TS101 ADSP TS201 ADSP TS202 or ADSP TS203 t Sets the number of timeout cycles as a maximum number of cycles the processor spends initializing exte
277. s comprised of three 32 bit words The structure of a compressed block header is shows in Figure 6 7 0X00002000 COMPRESSION TAG FLAG OXWBITOPAD WINDOW SIZE PADDED WORD COUNT OXBYTEBYTE COMPRESSED BYTE COUNT Figure 6 7 Compressed Block Header The first 32 bit word of the compressed block header holds the compres sion flag 0x00002000 which indicates that it is a compressed block header VisualDSP 5 0 Loader and Utilities Manual 6 37 ADSP 2126x 2136x 2137x 2146x Proc essor Booting The second 32 bit word of the compressed block header hold the size of the compression window takes the upper 16 bits and padded word count takes the lower 16 bits For the ADSP 2126x 2136x 2137x 2146x pro cessors the loader utility always rounds the byte count of the compressed stream to be a multiple of 4 The loader utility also pads 3 bytes to the compressed stream if the byte count of the compressed stream from the loader compression engine is not a multiple of 4 An actual padded byte count is a value between 0x0000 and 0x0003 The compression window size is 8 15 bits with the default value of 9 bits The compression window size specifies to the compression engine a num ber of bytes taken from the window during the compression The window size is the 2 s exponential value The next 32 bits of the compressed block header holds the value of the compressed stream byte count excluding the byte padded A window size selectio
278. s is a mandatory switch The processor argument is one of the following ADSP 21261 ADSP 21262 ADSP 21266 ADSP 21267 ADSP 21362 ADSP 21363 ADSP 21264 ADSP 21365 ADSP 21366 ADSP 21267 ADSP 21368 ADSP 21369 ADSP 21371 ADSP 21375 ADSP 21462 ADSP 21465 ADSP 21467 ADSP 21469 retainSecondStageKk Directs the loader utility to retain the decompression code in the ernel memory at runtime The retainSecondStageKernel switch must be used with compression VisualDSP 5 0 Loader and Utilities Manual 6 47 ADSP 2126x 2136x 2137x 2146x Proc essor Loader Guide Table 6 18 ADSP 2126x 2136x 2137x 2146x Loader Command Line Switches Cont d Switch Description si revision none any The si revision none any switch provides a silicon revi sion of the specified processor The switch parameter represents a silicon revision of the processor specified by the proc processor switch The parameter takes one of three forms The none value indicates that the VisualDSP ignores sil icon errata The value indicates one or more decimal digits followed by a point followed by one or two decimal digits Exam ples of revisions are 0 0 1 12 23 1 Revision 0 1 is dis tinct from and lower than revision 0 10 The digits to the left of the point specify the chip tapeout number the digits to the right of the point identify the metal mask revi sion number The number to the right of the point
279. s not compress automatically any data from any associated overlay files To compress data and code from the overlay file call the utility with the compressionOverlay switch either from the property page or from the command line Compressed Streams The basic structure of a loader file with compressed streams is shown in Figure 6 5 KERNEL WITH DECOMPRESSION ENGINE 1ST dxe COMPRESSED STREAM 1ST dxe UNCOMPRESSED STREAM 2ND dxe COMPRESSED STREAM 2ND dxe UNCOMPRESSED STREAM Figure 6 5 Loader File with Compressed Streams The kernel code with the decompression engine is on the top of the loader file This section is loaded into the processor first and is executed first when a boot process starts Once the kernel code is executed the rest of 6 36 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2126x 2136x 2137x 2146x SHARC Processors the stream is brought into the processor The kernel code calls the decom pression routine to perform the decompression operation on the stream and then loads the decompressed stream into the processor s memory in the same manner a conventional kernel does when it encounters a com pressed stream Figure 6 6 shows the structure of a compressed boot stream COMPRESSED BLOCK HEADER COMPRESSED STREAM Figure 6 6 Compressed Block Compressed Block Headers A compressed stream always has a header followed by the payload com pressed stream The compressed block header i
280. s only VisualDSP 5 0 Loader and Utilities Manual 6 45 ADSP 2126x 2136x 2137x 2146x Proc essor Loader Guide Table 6 18 ADSP 2126x 2136x 2137x 2146x Loader Command Line Switches Cont d Switch Description idffref N Directs the loader utility to share the boot stream for processor N with processor If the executable file of the processor is identical to the executable of the N processor the switch can be used to set the start address of the processor with ID of to be the same as that of the processor with ID of N This effectively reduces the size of the loader file by providing a single copy of the file to two or more pro cessors in a multiprocessor system This switch applies to the ADSP 21367 21368 21369 2137x and ADSP 2146x processors only userkernel Directs the loader utility to use the specified userkerne and to ignore the default boot kernel for the boot loading routine in the output boot loadable file Note The boot kernel file selected with this switch must correspond to the boot type selected with the b switch If the 1 switch does not appear on the command line the loader utility searches for a default boot kernel file in the installation direc tory see ADSP 2126x 2136x 2137x 2146x Processors Boot Ker nels on page 6 19 For kernels with the decompression engine see Decompression Kernel File on page 6 40 The loader utility does not search for an
281. s the boot stream in the conventional way builds data blocks then applies the compression to the boot stream The decompres VisualDSP 5 0 Loader and Utilities Manual 3 49 ADSP BF53x BF561 Proc essor Booting sion initialization is the reversed process the loader utility decompresses the compressed stream first then loads code and data into memory seg ments in the conventional way The loader utility compresses the boot stream on the dxe by dxe basis For each input dxe file the utility compresses the code and data together including all code and data from any associated overlay ov1 and shared memory sm files Compressed Streams Figure 3 21 illustrates the basic structure of a loader file with compressed streams INITIALIZATION CODE KERNEL WITH DECOMPRESSION ENGINE 15T xe COMPRESSED STREAM 1ST dxe UNCOMPRESSED STREAM 2ND dxe COMPRESSED STREAM 2ND dxe UNCOMPRESSED STREAM Figure 3 21 Loader File with Compressed Streams The initialization code is on the top of the loader file The initialization code is loaded into the processor first and is executed first when a boot process starts Once the initialization code is executed the rest of the stream is brought into the processor The initialization code calls the decompression routine to perform the decompression operation on the stream and then loads the decompressed stream into the processor s mem ory in the same manner a conventional boot kernel
282. s with the encryption algorithms in the dynamic library file d _fi ename If the d _fi ename parame ter does not appear on the command line the encryption algorithm from the default ADI s file is used VisualDSP 5 0 Loader and Utilities Manual 3 61 ADSP BF53x BF561 Processor Loader Guide Table 3 10 Blackfin Loader Command Line Switch Summary Contd Switch Description f hex The f hex ASCII binary include switch specifies the for f ASCII mat of a boot loadable file Intel hex 32 ASCII binary include If f binary the f switch does not appear on the command line the default f include boot mode format is hex for flash PROM and ASCII for SPI SPI slave UART and TWI ghc The ghc switch specifies a 4 bit value global header cookie for bits 31 28 of the global header see Table 3 7 on page 3 38 Applies to the ADSP BF561 processors only h or help The h elp switch invokes the command line help outputs a list of command line switches to standard output and exits By default the h switch alone provides help for the loader driver To obtain a help screen for your target Blackfin processor add the proc switch to the command line For example type elfloader proc ADSP BF535 h to obtain help for the ADSP BF535 processor HoldTime The HoldTime switch allows the loader utility to specify a num ber of hold time cycles for flash PROM boot The valid values ar
283. sed on HBW bits ADSP 21160 Host connected to DATA63 32 or DATA47 31 pins based on HPM bits ADSP 21060 61 62 65L ADSP 21065L host address to 10P registers only ADSP 21160 ADSP 21160 host address to 10P registers and internal memory After reset the processor goes into an idle stage with e PC set to address 0x20004 on the ADSP 21060 61 62 processors e PC set to address 0x8004 on the ADSP 21065L processors e PC set to address 0x40004 on the ADSP 21160 processors The parameter registers for the external port DMA channel 0 6 or 10 are initialized as shown in Table 4 8 and Table 4 9 except that registers EIx EMx and ECx are not initialized and no DMA transfers start The DMA channel control register DMAC6 for the ADSP 21060 61 62 processors DMACO for the ADSP 21065L processors or DMAC10 for the ADSP 21160 processors is initialized which allows external port DMA enable and selects DTYPE for instruction words PMODE for 16 to 48 bit word packing 8 to 48 bit for the ADSP 21065L processors and least significant word first Because the host processor is accessing the EPBO external port buffer the HPM host packing mode bits of the SYSCON register must correspond to the external bus width specified by the PMODE bits of DMACx control register 4 12 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2106x 21160 SHARC Processors For a different packing mode the host must write to DMACx and
284. set in the block header s flag word The boot ROM boots the final payload over writing any areas used by the initialization code Because the final flag is set in the header the boot ROM jumps to EVT1 OxFFAO 0000 for the ADSP BF533 BF534 BF536 BF537 BF538 and ADSP BF539 processors 0xFFAO 8000 for the ADSP BF531 BF532 processors to start application code execution Decompression Initialization Files As stated before a decompression initialization dxe file must be used when building a loader file with compressed streams The decompression initialization dxe file has a built in decompression engine to decompress the compressed streams from the loader file 3 54 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Proc essors FLASH MEMORY BOOT ROM INIT CODE PAYLOAD L1 MEMORY KERNEL AND DECOMPRESSION INITIALIZATION ENGINE KERNEL AND DECOMPRESSION ENGINE DECOMPRESSED STREAM IN PARTS BOOTS INTO VARI OUS MEMORIES THROUGH INIT COMPRESSED E INDON S an IMAGE PAYLOAD BOOT ROM BOOTS FINAL PAYLOAD FINAL PAYLOAD OVER OVERWRITES LOCA WRITING INITIALIATION TION FROM WHICH KERNEL AND INIT CODE EXE DECOMPRESSION WINDOW CUTES IN L1 THEN JUMPS TO EVT1 Figure 3 25 ADSP BF531 BF532 BF533 BF534 BF536 BF537 Com pressed Stream Booting Sequence The decompression initialization file can be sp
285. sncssssesdancaseasaones 3 58 File RS sainn iA ES 3 59 File ESENS ONE seriats NAT 3 59 Blackfin Loader Command Line Switches s sssssssseseesseeee 3 60 Usina Vimal DSPs Loader cscnrocserraeenan e 3 72 Using Visual DSP oe Compression secciecnimnennwenan 3 75 Using VisualDSP Second Stage Loader for ADSP BF535 e E a E ATEA E A O A E 3 76 Using VisuallSP ROM Splitter sorsninniusnerorsraeaniia 3 78 vi VisualDSP 5 0 Loader and Utilities Manual CONTENTS ADSP BF535 and ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 Processor No Boot Mode 3 79 LOADER FOR ADSP 2106X 21160 SHARC PROCESSORS ADSP 2106x 21160 Processor Booting naanwaniinnnnmasnasin 4 2 PowerUp Boouns Proces srren asnan N 4 3 Boot Mode Sey ssssiopsronrinioroan i or 4 5 BISP 2106021 160 Boot Modes spascssssioincieisariaiesanccivieaanaes 4 7 EPROM Boot etree eee 4 7 Host Bone Piste eR 4 11 Link Port Boot Mode Sac cscteceanscnccicasentiecaeesneenonorateesnseceaanens 4 15 No Boor eet eer 4 16 ADSP 2106x 21160 Boot Kernels scsscissinciicecctesvarrirceccannics 4 16 ADSP 2106x 21160 Processor Boot Steams sssssssesseseseeee 4 17 Boot Kernel Modification and Loader Issues 0 ccce08 4 19 ADS 21 06021160 Interrupt Vector Table scsarisrisaissas 4 22 ADSP 2106x 21160 Multi Application Multi DXE Management 4 23 ADSP 2106x 21160 Processor ID Numbers creiensecreseises 4 24 ADSP 2106x 21160 Processor Loader Guide cc c cceesseesecreesees 4 25
286. sor Loader Guide Table 4 15 ADSP 2106x 21160 Loader Command Line Switches Switch Description kernelfile Directs the loader utility to use the specified kernel file as the boot loading routine in the output boot loadable file The boot kernel selected with this switch must correspond to the boot type selected with the b switch If the 1 switch does not appear on the command line the loader searches for a default boot kernel file Based on the boot type b switch the loader utility searches in the processor specific loader direc tory for the boot kernel file as described in ADSP 2106x 21160 Boot Kernels on page 4 16 o filename Directs the loader utility to use the specified fi ename as the name for the loader output file If not specified the default name is input file ldr paddress PROM start address Places the boot loadable file at the specified address in the EPROM If the p switch does not appear on the command line the loader util ity starts the EPROM file at address 0x0 this EPROM address corre sponds to 0x800000 on the ADSP 21060 21061 21062 ADSP 21065L and ADSP 21160 processors proc processor Specifies the processor This a mandatory switch The processor is one of the following ADSP 21060 ADSP 21061 ADSP 21062 ADSP 21065L ADSP 21160 4 30 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2106x 21160 SHARC Processors Table 4 15
287. sors ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 Processor Booting Upon reset an ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 processor jumps to the on chip boot ROM or jumps to 16 bit external memory for execution if BMODE 0 located at 0x2000 0000 The ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 Pro cessor On Chip Boot ROM details can be found on page 3 23 Table 3 1 summarizes the boot modes and execution start addresses for the ADSP BF531 ADSP BF532 ADSP BF533 ADSP BF538 and ADSP BF539 processors Table 3 2 summarizes the boot modes for the ADSP BF534 BF536 BF537 processors which in addition to all of the ADSP BF531 BF532 BF533 processor boot modes also can boot from a TWI serial device a TWI host and a UART host VisualDSP 5 0 Loader and Utilities Manual 3 3 ADSP BF53x BF561 Proc essor Booting Table 3 1 Boot Mode Selections for ADSP BF531 BF532 BF533 BF538 BF539 Processors Boot Source BMODE 1 0 Execution Start Address ADSP BF531 ADSP BF533 ADSP BF532 ADSP BF538 ADSP BF539 Executes from a 16 bit external ASYNC 00 0x2000 0000 0x2000 0000 bank 0 memory no boot mode see on page 3 16 Eight or 16 bit flash PROM 01 OxFFAO 8000 OxFFAO 0000 SPI host in SPI slave mode 10 OxFFAO 8000 OxFFAO 0000 Eight 16 or 24 bit addressable SPI memory 11 OxFFAO 8000 OxFFAO 0000 in SPI master boot mode with support for Atmel AT4
288. sors 6 4 6 17 ADSP 2126x 36x 37x processors 6 30 applications See also blocks of application code loading introduction to 1 15 code start address 2 14 2 20 3 66 3 74 4 4 4 19 5 5 default code start address 2 20 3 74 development flow 1 7 multiple dxe files 2 17 archive files See library files dlb archiver A 5 ASCII file format 2 9 3 62 7 9 A 4 A 14 asm assembly source files 1 8 A 2 assembling introduction to 1 8 assembly directives A 2 initialization data files dat A 2 object files doj A 5 source text files asm 1 8 A 2 asynchronous FIFO boot mode ADSP BF52x 54x processors 2 4 AUTODMA register 7 2 B baudrate loader switch for Blackfin 3 60 baud rate Blackfin processors 3 24 3 38 3 74 BFLAG_CALLBACK block flag 2 9 BFLAG_QUICKBOT block flag 2 15 BFLAG_SAVE block flag 2 16 BELT file dumper B 4 binary flat format bflt B 3 B 4 binary format files Idr 2 9 3 62 7 9 A 9 bit reverse option SHARC processors 6 13 block of application code introduction to 1 16 byte counts Blackfin processors 2 13 3 64 flags See flag words packing See data packing tags 4 18 5 17 6 18 6 23 6 25 block headers Blackfin processors ADSP BF531 2 3 4 6 7 8 9 processors 3 9 3 10 ADSP BF535 processors 3 33 ADSP BF561 processors 3 39 3 43 block headers SHARC processors ADSP 2106x 160 processors 4 17 ADSP 21161 processors 5 17 ADSP 2126x 36x 37x processors 6 18
289. structions come from a program called boot kernel When executed the boot kernel facilitates booting of user application code The combination of the boot kernel and application code comprise the boot loadable 1dr file At power up after the chip reset the booting process includes the follow ing steps 1 Based on the boot type an appropriate DMA channel is automati cally configured for a 256 instruction 48 bit transfer This transfer boot loads the boot kernel program into the processor memory DMA channels used by the various processor models are shown in Table 4 1 Table 4 1 ADSP 2106x 21160 Processor DMA Channels Processor PROM Booting Host Booting Link Booting ADSP 21060 DMAC6 DMAC6 See Table 4 8 DMAC6 See Table 4 8 ADSP 21061 Not supported ADSP 21062 DMAC6 ADSP 21065L DMAC8 DMACO pro DMAC8 DMACO programs Not supported grams DMAC8 see DMAC8 see Table 4 8 Table 4 8 ADSP 21160 DMAC10 See Table 4 9 DMAC10 See Table 4 9 DMAC8 VisualDSP 5 0 Loader and Utilities Manual 4 3 ADSP 2106x 21160 Proc essor Booting 2 The boot kernel runs and loads the application executable code and data 3 The boot kernel overwrites itself with the first 256 words of the application at the end of the booting process After that the appli cation executable code begins to execute from locations 0x20000 ADSP 21060 61 62 0x8000 ADSP 21065L and 0x40000 ADSP
290. systems 5 21 5 22 EPROM flash boot mode TigerSsHARC processors 7 2 7 3 7 10 EPROM flash memory devices 1 13 executable and linkable format ELF executable files dxe 1 2 1 8 1 11 A 5 object files doj A 5 reference information A 16 to binary flat format BFLT converter B 3 external memory boot 1 10 resistors 4 8 7 3 vector tables 4 22 external bus interface unit EBIU 3 34 external memory Blackfin processors ADSP BF531 2 3 4 6 7 8 9 processors 3 3 3 4 3 46 ADSP BF535 processors 3 21 3 24 3 25 3 34 ADSP BF561 processors 3 43 3 46 multiprocessor support 3 46 1 6 VisualDSP 5 0 Loader and Utilities Manual external memory SHARC processors ADSP 2106x 160 processors 4 5 4 6 4 9 4 10 4 14 4 16 4 19 4 22 4 31 ADSP 21161 processors 5 4 5 16 5 21 5 31 ADSP 2126x 36x 37x 46x processors 6 7 6 22 ADSP 2126x 36x 37x processors 6 25 external ports SHARC processors ADSP 2106x 160 processors 4 5 4 7 4 9 4 11 4 13 4 14 4 15 4 19 4 24 ADSP 21161 processors 5 4 5 5 5 6 5 7 5 8 5 9 5 10 5 12 5 22 external ports TigerSHARC processors 7 2 external vector tables 5 21 EZ KIT Lite board targets 1 10 F f h s1 s2 s3 b splitter switch 8 6 f hex ascii binary include loader switch for Blackfin 2 9 3 62 fhex ASCI binary include s1 s2 s3 loader switch for SHARC 4 29 5 28 6 45 fhex ascii binary s1 s2 s3 loader switch for TigerSHARC 7 9 file formats l
291. t options on the Load Processor page also called loader property page Click OK to save the selections Selecting Build Project from the Project menu generates a loader file For information relative to a specific processor refer to the VisualDSP online help for that processor VisualDSP invokes the elfloader utility to build the output file The Load page buttons and fields correspond to loader command line switches and parameters see Table 4 15 on page 4 28 Use the Additional Options box to enter options that do not have dialog box equivalents For the ADSP 21020 processors the only permitted boot mode is JTAG bJTAG is automatically entered in the Additional Options box 4 32 VisualDSP 5 0 Loader and Utilities Manual 5 LOADER FOR ADSP 21161 SHARC PROCESSORS This chapter explains how the loader utility el floader exe is used to convert executable dxe files into boot loadable files for the ADSP 21161 SHARC processors Refer to Introduction on page 1 1 for the loader utility overview the introductory material applies to all processor families Refer to Loader for ADSP 2106x 21160 SHARC Processors on page 4 1 for information about the ADSP 21060 ADSP 21061 ADSP 21062 ADSP 21065L and ADSP 21160 processors Refer to Loader for ADSP 2126x 2136x 2137x 2146x SHARC Processors on page 6 1 for information about the ADSP 2126x and ADSP 2136x processors Loader operations specific to the ADSP
292. te For example F3 represents a byte whose decimal value is 243 Table A 8 shows an example of a header record in byte stacked format In the above example the start address and block length fields are 32 0x20 bits wide The file contains program memory data the MSB is the only flag currently used in the PROM splitter flags field No user flags are A 12 VisualDSP 5 0 Loader and Utilities Manual File Formats Table A 8 Example Header Record in Byte Stacked Format Field Purpose 20008000000000080000001E Example record 20 Width of address and length fields in bits 00 Reserved 80 PROM splitter flags 80 PM 00 DM 00 User defined flags loaded with u switch 00000008 Start address of data block 0000001E Number of bytes that follow set The address of the first location in the block is 0x08 The block con tains 30 1E bytes 5 program memory code words The number of bytes that follow until next header record or termination record must be non Zero A block of data records follows its header record five bytes per line for data memory and six byte per line for program memory or in other phys ical memory width For example Program Memory Section Code or Data 304034343426 142226083C15 Data Memory Section 3040343434 2614222608 DATA64 Memory Section 1122334455667788 99AABBCCDDEEFFOO VisualDSP 5 0 Loader and Utilities Manual A 13
293. ter command line must include one or more of pm dm or 64 or the s switch The 64 switch corresponds to DATA64 memory space TigerS HARC processors do not have pm dm or 64 switches e s section_name The s switch can be used without the pm dm or 64 switch The splitter command line must include one or more of the pm dm and 64 switches or the s switch Most items in the splitter command line are not case sensitive for example pm and PM are interchangeable However the names of memory sections must be identical including case to the names used in the executable Each of the following command lines elfspl21k pm o pm_stuff my_proj dxe proc ADSP21161 elfspl21k dm o dm_stuff my_proj dxe proc ADSP21161 elfspl21k 64 o 64_stuff my_proj dxe proc ADSP21161 elfspl21k s seg code 0 seg code my_proj dxe runs the splitter utility for the ADSP 21161 processor The first command produces a PROM file for program memory The second command pro duces a PROM file for data memory The third command produces a PROM file for DATA64 memory The fourth command produces a PROM file for section seg code The switches on these command lines are as follows File Searches File searches are important in the splitter process The splitter utility sup ports relative and absolute directory names default directories and user selected directories for file search paths File searches occur as described on page 1
294. th the specified constant 32 bit values The switch is used for boot time callbacks The callback is guaranteed to be made prior to the target address of sym symbol The callback cannot be used with CRC32 dmawidth The dmawidth 8 16 32 switch specifies a DMA width in bits for memory boot modes It controls the DMACODE bit field issued to the boot block headers by the width switch For FIFO boot mode 16 is the only DMA width SPI TWI and UART modes use 8 bit DMA f hex The f hex ASCII binary include switch specifies the for f ASCII mat of a boot loadable file Intel hex 32 ASCII binary or f binary include If the f switch does not appear on the command line f include the default file format is hex for flash PROM boot modes and ASCII for other boot modes h or help The help switch invokes the command line help outputs a list of command line switches to standard output and exits By default the h switch alone provides help for the loader driver To obtain a help screen for your target Blackfin processor add the proc switch to the command line For example type elfloader proc ADSP BF542 h to obtain help for the ADSP BF542 processor VisualDSP 5 0 Loader and Utilities Manual 2 9 ADSP BF51x BF52x BF54x Processor Loader Guide Table 2 5 ADSP BF51x BF52x BF54x Loader Command Line Switch Summary Contd Switch Description init filename dxe T
295. the boot ROM presumes that a hard reset has occurred and performs the full boot sequence If bit 4 is set the boot ROM under stands that the user code has invoked a software reset and restarts the user program by jumping to the beginning of core A s L1 memory OxFFAO 0000 bypassing the entire boot sequence When developing an ADSP BF561 processor application you start with compiling and linking your application code into an executable dxe file The debugger loads the dxe file into the processor s memory and executes it With two cores two dxe files can be loaded at once In the real time environment there is no debugger which allows the boot ROM to load the executables into memory ADSP BF561 Processor Boot Streams The loader utility converts the dxe file into a boot stream 1dr file by parsing the executable and creating blocks Each block is encapsulated within a 10 byte header The 1dr file is burned into the external memory device flash memory PROM or EEPROM The boot ROM reads the external memory device parsing the headers and copying the blocks to the VisualDSP 5 0 Loader and Utilities Manual 3 37 ADSP BF53x BF561 Proc essor Booting addresses where they reside during program execution After all the blocks are loaded the boot ROM jumps to address 0xFFAO 0000 to execute the core A program When code is run on both cores the core A program is responsible for releasing core B from the idle state by c
296. the boot type for the boot loadable file fhex Specifies Intel hex 32 format for the boot loadable file 1 TS101_prom exe Specifies the boot kernel file to be used for the boot loadable file elfloader id2exe p0 dxe id3exe pl dxe proc ADSP TS101 bprom fhex 1 Ts101_prom dxe In the above example the command line runs the loader utility with p0 dxe Identifies the executable file for the processor with ID of 2 to process into a boot loadable file Note the absence of the o switch causes the output file name to default to p0 1dr p1l dxe Identifies the executable file for the processor with ID of 3 to process into a boot loadable file proc ADSP TS101 Specifies ADSP TS101 as the processor type bprom Specifies EPROM booting as the boot type for the boot loadable file fhex Specifies Intel hex 32 format for the boot loadable file 1 Ts101_prom exe Specifies the boot kernel file to be used for the boot loadable file VisualDSP 5 0 Loader and Utilities Manual 7 7 TigerSHARC Loader Guide File Searches File searches are important in loader processing The loader utility sup ports relative and absolute directory names default directories and user selected directories for file search paths File searches occur as described on page 1 1 File Extensions Some loader switches take a file name as an optional parameter Table 7 2 lists the expected file types names and extensions The loader
297. the boot type selection b switch e For PROM and SPI PROM boot types select a hex ASCII s1 s2 s3 or include format e For other SPI boot types select an ASCII or binary format h Invokes the command line help outputs a list of command line or switches to standard output and exits help By default the h switch alone provides help for the loader driver To obtain a help screen for the target processor add the proc switch to the command line For example type elfloader proc ADSP 21262 h to obtain help for the ADSP 2126x 2136x and ADSP 2137x processors hostwidth Sets up the word width for the 1dr file By default the word width for PROM and SPI PROM boot modes is 8 for SPI slave SPI flash and SPI master boot modes is 32 The valid word widths are 8 for Intel hex 32 and Motorola S records formats e 8 16 or 32 for ASCII binary and include formats idffexe filename Specifies the processor ID Directs the loader utility to use the pro cessor ID 4 for a corresponding executable file the fi ename parameter when producing a boot loadable file This switch is used to produce a boot loadable file to boot multiple processors Valid values for are 0 1 2 3 4 5 6 and 7 Do not use this switch for single processor systems For single pro cessor systems use fi ename as a parameter without a switch This switch applies to the ADSP 21367 21368 21369 2137x and ADSP 2146x processor
298. the code and data from the executable dxe and shared memory sm files when the compression command line switch is used alone and leaves the code and data from the overlay ov1 files uncompressed The compressionOverlay switch directs the loader utility to compress the code and data from the ov1 files in addition to com pressing the code and data from the dxe and sm files The compressionOverlay switch must be used in conjunction with compression Booting Compressed Steams Figure 6 8 shows the booting sequence of a loader file with compressed streams The loader file is pre stored in the flash memory l 2 A a booting process is initialized by the processor The processor brings the 256 words of the boot kernel from the flash memory to the processor s memory for execution The decompression engine is brought in The compressed stream is brought in then decompressed and loaded into the memory The uncompressed stream is brought and loaded into memory possibly to overwrite the memory spaces taken by the compressed code The final block is brought and loaded into the memory to over write the memory spaces taken by the boot kernel VisualDSP 5 0 Loader and Utilities Manual 6 39 ADSP 2126x 2136x 2137x 2146x Proc essor Booting FLASH MEMORY PROCESSOR BOOT KERNEL 2 MEMORY DECOMPRESSION ENGINE COMPRESSED STREAM UNCOMPRESSED STREAM FINAL BLOCK Figur
299. the proper address even when this switch is absent from the command line e filename Except shared memory The e switch omits the specified shared mem ory sm file from the output loader file Use this option to omit the shared parts of the executable file intended to boot a multiprocessor system To omit multiple sm files repeat the switch and parameter multiple times on the command line For example to omit two files use e fileA sm e fileB sm In most cases it is not necessary to use the e switch the loader utility processes the sm files efficiently includes a single copy of the code and data from each sm file in a loader file 4 28 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2106x 21160 SHARC Processors Table 4 15 ADSP 2106x 21160 Loader Command Line Switches Switch Description fhex Specifies the format of the boot loadable file Intel hex 32 ASCII S1 fASCII S2 S3 binary or include If the f switch does not appear on the fbinary command line the default boot file format is Intel hex 32 for PROM finclude and ASCII for host or link ee Available formats depend on the boot type selection b switch 53 For PROM boot type select a hex ASCII S1 S2 S3 or include format e For host or link boot type select an ASCII binary or include format h Command line help Outputs a list of the command line switches to or standard out and exits Type elf
300. tilities Manual 8 1 Splitter C ommand Line Splitter operations are detailed in the following sections Splitter Command Line on page 8 2 Provides reference information about the splitter utility s com mand line syntax and switches VisualDSP Interface Split Page on page 8 9 Provides reference information about the splitter utility s graphical user interface Splitter Command Line Use the following syntax for the SHARC and TigerSHARC splitter com mand line elfspl21k switch pm amp dm amp 64 amp proc part_number inputfile or elfspl21k switch s section_name inputfile where input file Specifies the name of the executable file dxe to be processed into a non bootable file for a single processor system The name of the input fi e file must appear at the end of the com mand The name can include the drive directory file name and file extension Enclose long file names within straight quotes for example long file name switch One or more optional switches to process Switches select operations for the splitter utility Switches may be used in any order A list of the splitter switches and their descriptions appear in Table 8 2 on page 8 5 8 2 VisualDSP 5 0 Loader and Utilities Manual Splitter for SHARC and TigerSHARC Processors e pm amp dm amp 64 For SHARC processors the amp symbol between the switches indicates AND OR The split
301. ting through the SPI port the ADSP 21161 processor uses DMA channel 8 of the IO processor to transfer instructions to internal memory In this boot mode the processor receives data in the SPIRx register In no boot mode the ADSP 21161 processors begin executing instructions from external memory Software developers who use the loader utility should be familiar with the following operations Power Up Booting Process on page 5 3 Boot Mode Selection on page 5 4 ADSP 21161 Processor Boot Modes on page 5 5 ADSP 21161 Processor Boot Kernels on page 5 16 5 2 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 21161 SHARC Processors e Boot Kernel Modification and Loader Issues on page 5 18 e ADSP 21161 Processor Interrupt Vector Table on page 5 21 e ADSP 21161 Multi Application Multi DXE Management on page 5 21 Power Up Booting Process The ADSP 21161 processors include a hardware feature that boot loads a small 256 instruction program into the processor s internal memory after power up or after the chip reset These instructions come from a program called boot kernel When executed the boot kernel facilitates booting of user application code The combination of the boot kernel and application code comprises the boot loadable 1dr file At power up after the chip reset the booting process includes the follow ing steps 1 Based on the boot mode an appropriate DM
302. tion SRAM 0xFFA0 000 L1 instruction cache SRAM 0xF L1 data bank A SRAM 0xFF80 0 L1 data bank A cache SRAM 0xF L1 data bank B SRAM 0xFF90 0 L1 data bank B cache SRAM 0x L1 instruction SRAM 0xFF60 000 L1 instruction cache SRAM 0xF L1 data bank A SRAM 0xFF40 0 L1 data bank A cache SRAM 0x L1 data bank B SRAM 0xFF50 0 L1 data bank B cache SRAM 0x 0 0 0 OxF F61 0000 00 0x FF40 400 00 0x 0 OxFFAO 3FFF FA1 0000 0xFFA1 3F 000 OxFF80 3FFF F80 4000 OxFF80 7 000 OxFF90 3FFF FF90 4000 OxFF90 7 F6 03FFF 0xFF61 3F FF40 3FFF 0 OxFF40 7 FF50 3FFF FF50 4000 OxFF50 7 e 128K of shared L2 memory FEBO 0000 FEB1 FFFF e Four banks of configurable synchronous DRAM 0x0000 0000 up to Ox1FFF FFFF FF FFF FFF FF FFF FFF S The boot ROM does not support booting to core A scratch mem ory OxFFBO 0000 OxFFBO OFFF and to core B scratch memory OxFF70 0000 0xFF70 OFFF Data that needs to be initialized prior to runtime should not be placed in scratch memory VisualDSP 5 0 Loader and Utilities Manual 3 45 ADSP BF53x BF561 Proc essor Booting ADSP BF53x and ADSP BF561 Mult Application Multi DXE Management This section does not apply to the ADSP BF535 processors This section describes how to generate and boot more than one dxe file for
303. turns from the initialization block code to the on chip boot ROM the on chip boot ROM continues to boot in bytes from the location specified in the RO or R3 register Listing 3 5 Initialization Block Code Example for Multiple dxe Boot include lt defBF532 h gt SECTION program RKKKKKPre Tnit SOCET ON KK RK RK RAK K KKK KKK KK KK KK KKK KKK KKK KK KK KKK SP ASTAT E SP RETS 5P r7 0 SP p5 0 E SP I 103 b SPy SPI r2eh SP 133 SP BO SP B1 SP B2 SP B3 SP MO f SP MIL SP M23 SP M33 P SP LOLASI Li et SP besl SP Ls ERK KRKKKKK KKK KKK KK KKK KKK KKK KK KK KKK KKK KKK KK KKK KKK KK KKK KKK KKK KK KK ERKREKEKT NIC Code SOCETONK KAA KAKKAKK KAKA KKK KK KKK KKK KKK KKK KKK KKK RO H High Address of DXE Location RO for flash PROM boot R3 for SPI boot RO L Low Address of DXE Location RO for flash PROM boot R3 for SPI boot KKK KK KK KK KK KK KK KKK KK KK IK KK KK KK KK KK KK KK RK KK KK KK KKK KK KK IK KK KK KKK XKKKKKPOSt Init SACLE IT ONK KAKA KKK KK KKK KKK KKK KK KKK KKK KKK KK KKK KK L3 SP L2 SP L1 SP LO SP M3 SP M2 SP M1 SP MO SP B3 SP B2 SP Bl SP BO SP 13 SP 12 SP I1 SP 10 SP 3 48 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac
304. udes a second stage loader Unless you develop an application for the ADSP BF535 processor most of the options on the Kernel page are grayed out Figure 3 28 shows a sample Kernel page with options set for an ADSP BF535 Blackfin processor Project Options for An ADSP BF535 Based Project gt Project a lez Project ii aaah Use boot kemel C Output kernel in seperate file fs General fey Language Settings Boot Mode Boot Format Output Width Eh MISRA C fey Preprocessor fs Processor 1 Eh Processor 2 EA Profile guided Optimization Warning Eh Assemble Fig Link E General Use default kernel Eh LDF Preprocessing ER Elimination ER Processor 5 El Load EA Options Eh Additional options E Splitter Eh Pre build v Figure 3 28 Project Load Kernel Page for ADSP BF535 Processors 3 76 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Proc essors To create a loader file which includes a second stage loader 1 Select Options under Load to set up base load options see Using VisualDSP Loader on page 3 72 2 Select Kernel under Load to set up the second stage loader options Figure 3 28 3 On the Kernel page select Use boot kernel 4 In Kernel file enter the name of the second stage loader file dxe The Use default kernel option is available for the ADSP BF535 and grayed out for the ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539
305. ugh 32 based on your specific input file the value can be within a subset of 0 32 2 22 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF51x BF52x BF54x Blac kfin Proc essors Project Options for An ADSP BF548 Based Project py Project Eh General Ris Compile Eh Assemble Fl Link Ae Load ER Options fe Kernel a spitter E Pre build E Post build 2 Add Startup Code LDF e Project l C Enable ROM splitter Format Additional options Figure 2 3 Project Splitter Page for ADSP BF548 Processors VisualDSP 5 0 Loader and Utilities Manual 2 23 ADSP BF51x BF52x BF54x Processor Loader Guide 2 24 VisualDSP 5 0 Loader and Utilities Manual 3 LOADER SPLITTER FOR ADSP BF53X BF561 BLAC KFIN PRO C ESSO RS This chapter explains how the loader splitter utility e1f1oader exe is used to convert executable dxe files into boot loadable or non bootable files for the ADSP BF53x and ADSP BF561 Blackfin processors Refer to Introduction on page 1 1 for the loader utility overview Loader operations specific to the ADSP BF53x and ADSP BF561 Black fin processors are detailed in the following sections e ADSP BF53x BF561 Processor Booting on page 3 2 Provides general information on various boot modes including information on the second stage kernels e ADSP BF53x BF561 Processor Loader Guide on page 3 57 Provides reference in
306. ully debugged the loader utility is ready to convert the executable file into a processor loadable boot loadable file The loadable file can be automatically downloaded booted to the proces sor after power up or after a software reset The way the loader utility creates a boot loadable file depends upon how the loadable file is booted into the processor The boot mode of the processor is determined by sampling one or more of the input flag pins Booting sequences highly processor specific are detailed in the following chapters Analog Devices processors support different boot mechanisms In general the following schemes can be used to provide program instructions to the processors after reset e No Boot Mode e PROM Boot Mode e Host Boot Mode No Boot Mode After reset the processor starts fetching and executing instructions from EPROM flash memory devices directly This scheme does not require any loader mechanism It is up to the user program to initialize volatile memories VisualDSP 5 0 Loader and Utilities Manual 1 13 Boot Modes The splitter utility generates a file that can be burned into the PROM memory PROM Boot Mode After reset the processor starts reading data from a parallel or serial PROM device The PROM stores a formatted boot stream rather than raw instruction code Beside application data the boot stream contains addi tional data such as destination addresses and word counts A small program ca
307. utility finds the files when processing the dxe file The ovl and sm files may also be placed in the ov1 and sm file output directory specified in the 1df file or current working directory Loader output file VisualDSP 5 0 Loader and Utilities Manual 4 27 ADSP 2106x 21160 Processor Loader Guide ADSP 2106x 21160 Loader Command Line Switches Table 4 15 is a summary of the ADSP 2106x and ADSP 21160 loader switches Table 4 15 ADSP 2106x 21160 Loader Command Line Switches Switch Description bprom Specifies the boot mode The b switch directs the loader utility to pre bhos t pare a boot loadable file for the specified boot mode Valid boot modes blink include PROM host and link bJTAG For the ADSP 21020 processors JTAG is the only permitted boot mode If b does not appear on the command line the default is bprom To use a custom boot kernel the boot type selected with the b switch must correspond to the boot kernel selected with the 1 switch Other wise the loader utility automatically selects a default boot kernel based on the selected boot type see ADSP 2106x 21160 Boot Kernels on page 4 16 caddress Custom option This switch directs the loader utility to use the speci fied address Valid addresses are e 20004 and 20040 for the ADSP 2106x processors 8004 and 8040 for the ADSP 21065L processors e 40000 and 40050 for the ADSP 21160 processors The loader utility obtains
308. width of the boot kernel output file when there are two output files one for the boot kernel and one for user application code Valid values are e Eight or 16 for PROM or flash boot kernel e 16 for FIFO boot kernel e Eight for SPI and other boot kernels If this switch is absent from the command line the default file width is e the width parameter for flash PROM boot mode e 16 for FIFO boot mode e Eight when booting from SPI and other boot modes The kWidth switch must be used in conjunction with the 02 switch userkernel dxe The 1 userkerne dxe switch specifies the user boot kernel file The loader utilizes the user specified kernel and ignores the default boot kernel if there is one Currently only the ADSP BF535 processors have default kernels The M switch generates make dependencies only no output file is generated maskaddr The maskaddr switch masks all EPROM address bits above or equal to For example maskaddr 29 default masks all the bits above and including A29 ANDed by Ox1FFF FFFF For example 0x2000 0000 becomes 0x0000 0000 The valid s are integers 0 through 32 but based on your specific input file the value can be within a subset of 0 32 The maskaddr switch requires romsplitter and affects the ROM section address only MaxBlockSize The MaxBlockSize switch specifies the maximum block byte count which must be a multiple of 16
309. x 2146x Processors Boot Kernels on page 6 19 Do not use with the nokerne switch compression Directs the loader utility to compress the application data and code including all data and code from the application associated shared memory files see ADSP 2126x 2136x 2137x 2146x Processors Compression Support on page 6 35 The data and code from the overlay files are not compressed if this switch is used alone see compressionOverlay compressionOverlay Directs the loader utility to compress the application data and code from the associated overlay files see Overlay Compression on page 6 39 This switch must be used with compression compressws The compressWS switch specifies a compression window size in bytes The number is a 2 s exponential value to be used by the com pression engine The valid values are 8 15 with the default of 9 6 44 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2126x 2136x 2137x 2146x SHARC Processors Table 6 18 ADSP 2126x 2136x 2137x 2146x Loader Command Line Switches Cont d Switch Description fhex Specifies the format of a boot loadable file Intel hex 32 ASCII fASCIT binary include If the f switch does not appear on the command fbinary line the default boot file format is a Intel hex 32 for PROM and SPI PROM ASCII for SPI slave SPI 52 flash and SPI master 53 Available formats depend on
310. xecutable dxe files into boot loadable files for the ADSP 21060 ADSP 21061 ADSP 21062 ADSP 21065L and ADSP 21160 SHARC processors Refer to Introduction on page 1 1 for the loader utility overview the introductory material applies to all processor families Refer to Loader for ADSP 21161 SHARC Processors on page 5 1 for information about the ADSP 21161 processors Refer to Loader for ADSP 2126x 2136x 2137x 2146x SHARC Processors on page 6 1 for information about the ADSP 2126x and ADSP 2136x processors Loader operations specific to the ADSP 2106x 21160 SHARC processors are detailed in the following sections e ADSP 2106x 21160 Processor Booting on page 4 2 Provides general information about various booting modes includ ing information about boot kernels e ADSP 2106x 21160 Processor Loader Guide on page 4 25 Provides reference information about the loader utility s graphical user interface command line syntax and switches VisualDSP 5 0 Loader and Utilities Manual 4 1 ADSP 2106x 21160 Proc essor Booting ADSP 2106x 21160 Processor Booting The ADSP 2106x 21160 processors support three boot modes EPROM host link port and no boot see Table 4 3 and Table 4 4 on page 4 5 Boot loadable files for these modes pack boot data into 48 bit instructions and use an appropriate DMA channel of the processor s DMA controller to boot load the instructions The ADSP 2106x processors use DMA chan
311. y it has to be stored into a physical memory that is accessible by either the target processor or its host device Often it is burned into an EPROM or downloaded into a flash memory device using the VisualDSP Flash Pro grammer plug in The boot image is organized in a special manner required by the boot ker nel This format is called a boot stream A boot image can contain one or multiple boot streams Sometimes the boot kernel itself is part of the boot image Boot Stream A boot stream is basically a list of boot blocks It is the data structure that is processed and interpret by the boot kernel The VisualDSP loader util ity generates loader files that contain one or multiple boot streams A boot 1 4 VisualDSP 5 0 Loader and Utilities Manual Introduction stream often represents one application However a linked list of multiple application level boot streams is referred to as a boot stream See also Boot Streams on page 1 16 Boot Host A boot host is a processor or programmable logic that feeds the device con figured in a slave boot mode with a boot image or a boot stream Boot Block Multiple boot blocks form a boot stream These blocks consist of boot data that is preceded by a block header The header instructs the boot kernel how to interpret the payload data In some cases the header may contain special instructions only In such blocks there is likely no payload data present Boot Code Boot code
312. y kernel file if nokernel is selected message2 nokernel messagel Supports internal boot mode The nokernel switch directs the loader utility e Not to include the boot kernel code into the loader 1dr file e Not to perform any special handling for the 256 instructions located in the IVT e To put two 32 bit hex messages in the final block header optional e Not to include the initial word in the loader file For more information see Internal Boot Mode on page 6 17 6 46 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2126x 2136x 2137x 2146x SHARC Processors Table 6 18 ADSP 2126x 2136x 2137x 2146x Loader Command Line Switches Cont d Switch Description o filename Directs the loader utility to use the specified fi 7ename as the name for the loader s output file If the o filename is absent the default name is the root name of the input file with an 1dr extension noZeroBlock The noZeroBlock switch directs the loader utility not to build zero blocks paddress Specifies the PROM start address This EPROM address corresponds to 0x80000 ADSP 2126x processors or to 0x90000 ADSP 2136x 2137x 2146x processors The p switch starts the boot loadable file at the specified address in the EPROM If the p switch does not appear on the command line the loader utility starts the EPROM file at address 0x0 proc processor Specifies the processor Thi

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