2.25MHz Step-Down Converter with Dual LDOs & SVS (Rev. B)
Contents
1. INPUT VOLTAGE 50 40 Ta 85 C TA 25 C lt T 5 30 s 5 O 8 8 20 Ta 40 C 3 Vout 1 8V EN DCDC Vin 10 Mode GND lo 0 mA Measure time 2 s EN_LDOx GND 0 2 5 3 3 5 4 5 5 5 5 V Input Voltage V Figure 9 TPS650001 SHUTDOWN CURRENT INPUT VOLTAGE 20 Ty 85 C Ta 25 C lt a c 9 5 O 10 c 0 o o E Ta 40 C 3 A Vout 1 8V EN_DCDC GND Mode GND lo 0mA Measure time 2 s EN_LDOx GND 0 2 2 5 3 3 5 4 5 5 5 5 V Input Voltage V Figure 11 10 Submit Documentation Feedback Quiescent Current uA Ch1 VINDCDC Ch2 VDCDC I TEXAS INSTRUMENTS www ti com TPS650001 QUIESCENT CURRENT LDOx VS INPUT VOLTAGE EN_DCDC GND lo OMA Measure time 2 s 16 21 26 31 36 41 46 51 56 Vi Input Voltage V Figure 10 LINE TRANSIENT RESPONSE DCDC PFM Mode VINDCDC 3 6 V to 4 2V to 3 6V TA 25 C 500mV div VDCDC 1 8V DCDC Load Current 50mA Mode GND 20mV div t Time 100us div Figure 12 Copyright O 2009 2010 Texas Instruments Incorporated Product Folder Link s TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 1 TEXAS INSTRUME2. VINDCDC ra j _ DISCHG _ EN_DCDC Switch Control LP 1 Roe MODE i FB DCDC LOAD Oscillator H A DC2 OJA Diode o VREF DCDC AGND PGND Figure 21 DCDC Block Diagram and Output Voltage Setting The output voltage of the DCDC converter is set by Equation 1 Roc1 Roca Vococ Veg pcpc X R DC2 Roca Rpc2 DC2 1 Vococ 0 6V x The combined resistance of Roc and Roce should be less than 1 MQ Fixed output voltages and additional current limit options are also possible Please contact Texas Instruments for further information The step down converter has two modes of operation to maximize efficiency at different load conditions At moderate to heavy load currents the device operates in a fixed frequency pulse width modulation PWM mode that results in small output ripple and high efficiency Pulling the MODE pin to a DC high level will result in PWM mode over the entire load range At light load currents the device operates in a pulsed frequency modulation PFM mode to improve efficiency The transition to this mode occurs when the inductor current through the low side FET becomes zero indicating discontinuous conduction PFM mode also results in the output voltage increasing by 1 from its nominally se
3. Vino 0 5V x LDO1_2 2 The combined resistance of R po01_1 and Ri po 2 should be less than 1MQ Oscillator and Spread Spectrum Clock Generation The TPS6500x contains an internal oscillator running at a typical frequency of 2 25MHz This frequency is the fundamental switching frequency of the step down converter when it is running in PWM mode An additional circuit in the oscillator block implements spread spectrum clocking which modulates the main switching frequency when the device is in PWM mode This spread spectrum oscillation reduces the power that may cause EMI When viewed in the frequency domain the SSC spreads out the frequency that may introduce interference while simultaneously reducing the power Since the frequency is continually shifting the amount of time the switcher spends at any single frequency is reduced This reduction in time means that the receiver that may see the interference has less time to integrate the interference Different spin versions of SSC settings are also feasible contact a Texas Instruments sales representative for more information Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Link s TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 TPS65000 TPS65001 TPS650001 oe TPS650003 TPS650006 TPS650061 SLVS810B JUNE 2009 REVISED AUGUST 2010 www ti com SSC On Off Comparison Zoom In of SSC On Off Comparison from 1 5MHz to
4. RUK S PWQFN N20 PLASTIC QUAD FLATPACK NO LEAD NOTES A cow Example Board Layout Stencil Opening Based on a stencil thickness of 0 100mm 0 004inch Note E 7 20x0 4 65 solder coverage on center pad Non Solder Mask Defined Pad Example Via Layout Design Via pattern may vary due to layout constraints Example N Note D F lt Solder Mask Opening NS 1 8 Note F Pad Geometry Note C All around 4211052 D 12 12 All linear dimensions are in millimeters This drawing is subject to change without notice Publication IPC 7351 is recommended for alternate designs This package is designed to be soldered to a thermal pad on the board Refer to Application Note Quad Flat Pack Packages Texas Instruments Literature No SLUA271 and also the Product Data Sheets for specific thermal information via requirements and recommended board layout These documents are available at www ti com http www ti com gt Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release Customers should contact their board assembly site for stencil design recommendations Refer to IPC 7525 for stencil design considerations Customers should contact their board fabrication site for minimum solder mask web tolerances between signal pads WB Texas INSTRUMENTS www ti com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the
5. Changed Figure 1 title From EFFICIENCY DCDC PFM Mode To EFFICIENCY DCDC 600mA PFM Mode 8 Changed Figure 2 title From EFFICIENCY DCDC PFM Mode To EFFICIENCY DCDC 600mA PFM Mode 8 e Added Figure 3 EFFICIENCY DCDC PWM Mode e 8 Added Figure 4 EFFICIENCY DCDC PWM Mode ie 8 Changed the configuration of the PG pin in Figure 30 2200202200200100 0 ee 21 Changed the PG pin connection From VDCDO To Vy in Figure 31 eee eee 21 Changed the configuration of the PG and RST pins in Figure 31 iii 21 Added Figure 32 Typical TPS650001 Application Schematic ener 22 Added Figure 33 Typical TPS650061 Application Schematic nnns 22 Changes from Revision A October 2009 to Revision B Page Inthe Ordering Information Table changed the SVS column From Included To N A for devices TPS650001 AAA 2 Copyright O 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Link s TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 IA TEXAS INSTRUMENTS www ti com PACKAGING INFORMATION PACKAGE OPTION ADDENDUM 11 Apr 2013 Orderable Device Status Package Type Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Op Temp C Top Side Markings Samples 1 Drawing Qty 2 3 4 TPS65000
6. FB_LDO1 FB_LDO2 FB_DCDC 0 3 3 6 V VINDCDC SW PGND 1800 mA Current VINLDO1 2 VLDO1 2 AGND 800 mA at all other pins 1 mA Continuous total power dissipation See dissipation rating table Operating free air temperature Ta 40 85 C Maximum junction temperature Ty 125 C Storage temperature Tsig 65 150 C 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability 2 Submit Documentation Feedback Copyright O 2009 2010 Texas Instruments Incorporated Product Folder Link s TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 I TEXAS INSTRUMENTS www ti com DISSIPATION RATINGS TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 SLVS810B JUNE 2009 REVISED AUGUST 2010 TA lt 25 C TA 70 TA 85 DEVICE PACKAGE Rosa Rose POWER RATING POWER RATING POWER RATING TPS65000 01 1 ET EUR 270 C W 14 C W 370 mW 204 mw 148 mw TPS65000 01 2 48 7 C W 14 C W 2 05 W 1 13 W 821 mW 1 The JEDEC low K 1s board used to derive this data was a 3in x 3in two layer board with 2 ounce copper traces on top of
7. 1 mode 5 1 voltage positioning active R Load regulation PWM mode MODE high 0 5 A tstart Start up time EN_DCDC to start of switching 10 250 us tramp VDCDC ramp up time VDCDC ramp from 10 to 90 250 us Rois ria discharge resistance at EN DCDC low 450 Q 3 The max quiescent current of enabling LDOs is 8uA higher for TPS650001 TPS650003 TPS650006 and TPS650061 4 For VINDCDC VDCDC 1V 5 In PFM Mode the internal reference voltage is typ 1 01 x Vrer 4 Submit Documentation Feedback Copyright O 2009 2010 Texas Instruments Incorporated Product Folder Link s TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 l TEXAS INSTRUMENTS www ti com ELECTRICAL CHARACTERISTICS continued Over full operating ambient temperature range typical values are at T4 25 C Unless otherwise noted specifications apply TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 for condition Viy EN_LDOx EN_DCDC 3 6 V External components L 2 2 uH Cour 10 uF Cy 4 7 uF see the arameter measurement information SLVS810B JUNE 2009 REVISED AUGUST 2010 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOW DROP OUT REGULATORS VI Input voltage for LDOx VINLDOx 1 6 6 V Vo rs voltage LDOx 0 73 VINLDOx Vpo V lo Continuous Pass FET Current 300 mA 2 3V s VINLDOx 340 700 lec Short circuit
8. 150MHz from 1 5MHz to 3 5MHz TA 70 RBW 10 kHz RBW 10 kHz 60 50 dBmV dBmV al i 30 Start 1 5 MHz Stop 150 MHz Start 1 5 MHz Stop 3 5 MHz Figure 25 Figure 26 Figure 25 to Figure 26 shows the advantage of SSC with the frequency spectrum centering on the nominal frequency 2 25MHz The blue spectrum is the result of the spread change As depicted in the figures the harmonic spectrum is attenuated 10dB comparing to the same device without SSC POWER GOOD The open drain PG output is used to indicate the condition of the step down converter and each LDO This is a combined output with the outputs being compared when the appropriate enable signal is high The pin will be pulled low when all enabled outputs are greater than 90 of the target voltage and High Z when an enabled output is less than 90 of its intended value or when all the enable signals are pulled low EN _DCDC O EN_LDO1 EN_LDO2 O VDCDC O VDCDC O VDCDC Target VLDO10 VLDO1 Target VLDO20 Figure 27 Power Good Functionality 16 Submit Documentation Feedback Copyright O 2009 2010 Texas Instruments Incorporated Product Folder Link s TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 MEN
9. and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet PowerPAD is a trademark of Texas Instruments PRODUCTION DATA information is current as of publication date Copyright 2009 2010 Texas Instruments Incorporated Products conform to specifications per the terms of the Texas i Instruments standard warranty Production processing does not necessarily include testing of all parameters I TEXAS INSTRUMENTS TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 SLVS810B JUNE 2009 REVISED AUGUST 2010 www ti com This integrated circuit can be damaged by ESD Texas Instruments recommends that all integrated circuits be handled with appropriate precautions Failure to observe proper handling and installation procedures can cause damage NES ESD damage can range from subtle performance degradation to complete device failure Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications ORDERING INFORMATION Ta PART NUMBER PACKAGE PACKAGE DESIGNATOR OPTIONS SVS SSC ORDERING PACKAGE MARKING TPS65000 QFN 3x3 16 RTE LDO voltages N A Included TPS65000RTE CFO externally adjustable DCDC converters 600mA Vout externally adjustable LDO1 1 8V fixed LDO2 2 8V fixed DCDC Conv
10. change without notice Publication IPC 7351 is recommended for alternate designs This package is designed to be soldered to a thermal pad on the board Refer to Application Note Quad Flat Pack Packages Texas Instruments Literature No SLUA271 and also the Product Data Sheets for specific thermal information via requirements and recommended board layout These documents are available at www ti com http www ti com gt Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release Customers should contact their board assembly site for stencil design recommendations Refer to IPC 7525 for stencil design considerations Customers should contact their board fabrication site for minimum solder mask web tolerances between signal pads WS Texas INSTRUMENTS www ti com MECHANICAL DATA RUK S PWQFN N20 PLASTIC QUAD FLATPACK NO LEAD A 44 PIN 1 INDEX AREA TOP AND BOTTOM 2 THERMA UUU _ SIZE AND_SHAP ON SEPARATE JUT NOTES This drawing is subject to change without notice All linear dimensions are in millimeters Dimensioning and tolerancing per ASME Y14 5M 1994 The package thermal pad must be soldered to the board for thermal and mechanical performance See the additional figure in the Pro
11. issue in this document sold by TI to Customer on an annual basis Addendum Page 2 A TEXAS PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 22 Aug 2012 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS Dimension designed to accommodate the component width Bo Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Y Overall width of the carrier tape Pitch between successive cavity centers i W1 TAPE AND REEL INFORMATION All dimensions are nominal Device Package Package Pins Reel Diameter mm TPS650001RTER 330 0 TPS650001RTET 180 0 TPS650003RTER 330 0 TPS650003RTET 180 0 TPS650006RTER 330 0 TPS650006RTET 180 0 TPS65000RTER 330 0 TPS65000RTET TPS65001RUKR TPS65001RUKT TPS650061RUKR TPS650061RUKT Pack Materials Page 1 A TEXAS PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 22 Aug 2012 TAPE AND REEL BOX DIMENSIONS WTA All dimensions are nominal Device Package Type Package Drawing Pins Length mm Width mm Height mm TPS650001RTER WQFN 367 0 367 0 35 0 TPS650001RTET WQFN 210 0 185 0 35 0 TPS650003RTER WQFN 367 0 367 0 35 0 TPS650003RTET WQFN 210 0 185 0 35 0 TPS650006RTER WQFN 367 0 367 0 35 0 TPS650006RTET WQFN 210 0 185 0 35 0 TPS65000RTER WQFN RTE
12. mainly for automotive use In any case of use of non designated products TI will not be responsible for any failure to meet ISO TS16949 Products Applications Audio www ti com audio Automotive and Transportation www ti com automotive Amplifiers amplifier ti com Communications and Telecom www ti com communications Data Converters DLP Products DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID OMAP Applications Processors Wireless Connectivity dataconverter ti com www dlp com www ti com clocks interface ti com logic ti com microcontroller ti com www ti rfid com www ti com omap Computers and Peripherals Consumer Electronics Energy and Lighting Industrial Medical Security Space Avionics and Defense Video and Imaging TI E2E Community www ti com wirelessconnectivity www ti com computers www ti com consumer apps www ti com energy www ti com industrial www ti com medical www ti com security www ti com space avionics defense www ti com video Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2013 Texas Instruments Incorporated
13. right to make corrections enhancements improvements and other changes to its semiconductor products and services per JESD46 latest issue and to discontinue any product or service per JESD48 latest issue Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All semiconductor products also referred to herein as components are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its components to the specifications applicable at the time of sale in accordance with the warranty in Tl s terms and conditions of sale of semiconductor products Testing and other quality control techniques are used to the extent Tl deems necessary to support this warranty Except where mandated by applicable law testing of all parameters of each component is not necessarily performed Tl assumes no liability for applications assistance or the design of Buyers products Buyers are responsible for their products and applications using TI components To minimize the risks associated with Buyers products and applications Buyers should provide adequate design and operating safeguards Tl does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right relating to any combination machine or process in whic
14. the board 2 The JEDEC high K 2s2p board used to derive this data was a 3in x 3in multilayer board with 1 ounce internal power and ground RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT L1 SW pin inductor 1 5 2 2 3 3 uH Input capacitor at VINDCDC 10 uF Si Input capacitor at VINLDO1 2 2 2 uF Output capacitor for DCDC 10 22 uF Co Output capacitor for LDO1 2 2 2 uF DCDC converter output current 600 mA T DCDC converter output current TPS650061 ONLY 1000 mA LDO1 output current 300 mA LDO2 output current 300 mA Ta Operating ambient temperature 40 85 C ELECTRICAL CHARACTERISTICS Over full operating ambient temperature range typical values are at T4 25 C Unless otherwise noted specifications apply for condition V EN_LDOx EN_DCDC 3 6 V External components L 2 2 uH Cour 10 uF Cin 4 7 uF see the arameter measurement information PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPERATING VOLTAGE Input voltage for VINDCDC of 2 3 6 DCDC converter Vin Input voltage for LDO1 VINLDO1 See 1 6 e V Input voltage for LDO2 VINLDO2 See 1 6 6 Internal undervoltage lockout A threshold Vcc falling 1 72 1 77 1 82 V UVLO Internal undervoltage lockout 160 mV hysteresis SUPPLY CURRENT TPS65000 MODE low EN_DCDC high EN_LDO1 2 low 23 32 lout 0 mA and no switching A Operating quiescent current MODE low EN DCDC l
15. 0 www ti com The RSTSNS pin should be tied to VINDCDC if the reset functionality is not needed from this pin This will cause the reset to activate only when VINDCDC is rising from OV or when VINDCDC has dropped below UVLO The RSTSNS pin should be connected to an external RC network to set the deglitch timing for triggering a reset when VINDCDC is below the UVLO threshold The reset threshold voltage is given by Equation 3 Rsa Rs1 2 3 Vast 0 6V x The RST recovery timing is set by the capacitor on the TRST pin A 2uA current is enabled when the reset condition is met charging the capacitor The TRST voltage is monitored internally and the reset ends when the voltage reaches 0 6V The capacitor value to reset time can be computed with Equation 4 2x 109A 4 The value trsr is the time from the end of condition that activated RST until RST returns to its Hi Z state The TRST pin would be internally discharged to ground when the reset condition is true or after tps 1 Reset Trigger 0 i feet 0 6V x 2uA ltRst 0 0 6V VIRST GND Hi Z RST GND x gt 1 1 1 test test Figure 29 RST Recovery Timing 18 Submit Documentation Feedback Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 PT I UNIS TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 www ti com SLVS810B JUNE 2009 REVISED AUGUST 2010 OUTP
16. 1RTER ACTIVE WQFN RTE 16 3000 Green RoHS CUNIPDAU Level 2 260C 1 YEAR 40 to 85 DAG amp no Sb Br TPS650001RTET ACTIVE WQFN RTE 16 250 Green RoHS CUNIPDAU Level 2 260C 1 YEAR 40 to 85 DAG amp no Sb Br TPS650003RTER ACTIVE WQFN RTE 16 3000 Green RoHS CUNIPDAU Level 2 260C 1 YEAR 40 to 85 DAH amp no Sb Br TPS650003RTET ACTIVE WQFN RTE 16 250 Green RoHS CUNIPDAU Level 2 260C 1 YEAR 40 to 85 DAH amp no Sb Br TPS650006RTER ACTIVE WQFN RTE 16 3000 Green RoHS CUNIPDAU Level 2 260C 1 YEAR 55to 125 DAI amp no Sb Br TPS650006RTET ACTIVE WQFN RTE 16 250 Green RoHS CUNIPDAU Level 2 260C 1 YEAR 40 to 85 DAI umm TPS65000RTER ACTIVE WQFN RTE 16 3000 Green RoHS CUNIPDAU Level 2 260C 1 YEAR 40to 85 CFO um TPS65000RTET ACTIVE WQFN RTE 16 250 Green RoHS CUNIPDAU Level 2 260C 1 YEAR 40 to 85 CFO Nes TPS65001RUKR ACTIVE WQFN RUK 20 3000 Green RoHS CUNIPDAU Level 2 260C 1 YEAR 40 to 85 CFQ Samples amp no Sb Br TPS65001RUKT ACTIVE WQFN RUK 20 250 Green ROHS CUNIPDAU Level 2 260C 1 YEAR 40 to 85 CFQ amp no Sb Br TPS650061RUKR ACTIVE WQFN RUK 20 3000 Green RoHS CUNIPDAU Level 2 260C 1 YEAR 40 to 85 DAJ Samples 8 no Sb Br TPS650061RUKT ACTIVE WQFN RUK 20 250 Green RoHS CUNIPDAU Level 2 260C 1 YEAR 40 to 85 DAJ Samples amp no Sb Br The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device w
17. 3000 367 0 367 0 35 0 TPS65000RTET WQFN RTE 16 250 210 0 185 0 35 0 TPS65001RUKR WQFN RUK 20 3000 367 0 367 0 35 0 TPS65001RUKT WQFN RUK 20 250 210 0 185 0 35 0 TPS650061RUKR WQFN RUK 20 3000 367 0 367 0 35 0 TPS650061RUKT WQFN RUK 20 250 210 0 185 0 35 0 Pack Materials Page 2 MECHANICAL DATA RTE S PWQFN N16 PLASTIC QUAD FLATPACK NO LEAD 285 c Y 2 8 16 7 PN 1 E Li v V 1 ANE e gt gt ee Do EXPOSED THERMAL PAD A 4205254 D 01 NOTES All linear dimensions are in millimeters Dimensioning and tolerancing per ASME Y14 5M 1994 A B This drawing is subject to change without notice C Quad Flatpack No leads QFN package configuration The package thermal pad must be soldered to the board for thermal and mechanical performance See the Product Data Sheet for details regarding the exposed thermal pad dimensions E Falls within JEDEC MO 220 X TEXAS INSTRUMENTS www ti com THERMAL PAD MECHANICAL DATA RTE S PWQFN N16 PLASTIC QUAD FLATPACK NO LEAD THERMAL INFORMATION This package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink The thermal pad must be soldered directly to the printed circuit board PCB After soldering the PCB can be used as a heatsink In addition through the use of t
18. 65000 EN_DCDC sr 2 24H VDCDC o VINDCDC esoko E 3 3V Vin FB DCDC 10pF 10pF lr 15010 ae 470kQ PG NMV O ViN VLDO1 VEDON 470kQ E O 18v FB_LDO1 104F 180k0 LP O A VDCDC o VLDO2 820k0 E 2 8V 10uF 180kQ E A Figure 30 Typical TPS65000 Application Schematic TPS65001 EN DCDC 2 2uH VDCDC Vite d vinpepe 680kQ Y 3 3 T FB_DCDC B 10uF 10uF n MODE P lP lt ie LLL IN 475kQ 1A 470kQ ia RSTSNS PG o PG 0 1nF gt na 47OKQ RST i o jM Ala ww J Ww C TRST VEDO 470kQ O 4 8V 10uF Pa FA 180kQ o EN LDO1 VDCDC Es A EN_LDO2 We VINLDO1 VLDO2 820kQ O 2 8V FB_LDO2 aza T 10uF i VINLDO2 lr 180kQ E AGND E Figure 31 Typical TPS65001 Application Schematic Copyright O 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Link s TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 TPS65000 TPS65001 TPS650001 diri O TPS650003 TPS650006 TPS650061 SLVS810B JUNE 2009 REVISED AUGUST 2010 www ti com TPS650001 2 2uH EN_DCDC SW d v VDCDC uo VINDCDC i 1 2V IN FB_DCDC 7 10uF 10uF MODE P P 470kQ NVV o Vin VLDO1 1 8V FB_LDO1 10uF IE Vin O EN LDO1 7 EN
19. ARACTERISTICS continued LOAD TRANSIENT RESPONSE LDOx lout VINDCDC 3 6V VINLDOx 3 6V TA 25 C Ch1 LDOx Load Current 50mA div LDOx Load Current 15mA to 100mA gt gt VLDOx 1 2V H EN_DCDC GND Ch2 VLDOx 20mV div t Time 200us div Figure 17 PWM to PFM TRANSITION DCDC VINDCDC 3 6V iT 25 C I DCDC Load Current 30mA i VDCDC 1 8V Ch2 VDCDC Ch1 Mode 20mV div 2V div Ch3 SW 2VI div t Time 4us div Figure 19 12 Submit Documentation Feedback Rejection Ratio dB PFM to PWM TRANSITION DCDC VINDCDC 3 6V TA 25 C DCDC Load Current 30mA 1 VDCDC 1 8V Ch1 Mode 2V div Ch2 VDCDC 20mV div 53 ER t Time 4us div Figure 18 POWER SUPPLY REJECTION RATIO LDOx vs FREQUENCY 100 90 80 70 60 50 40 30 20 10 0 i 10 100 1k 10k 100k 1M 10M f Frequency MHz Figure 20 Copyright O 2009 2010 Texas Instruments Incorporated Product Folder Link s TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 PI DENIS TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 www ti com SLVS810B JUNE 2009 REVISED AUGUST 2010 DETAILED DESCRIPTION Step Down Converter The step down converter is intended to allow maximum flexibility in the end equipment The output voltage is user selectable with a resistor network on the output Figure 21 illustrates the necessary connections L
20. D AUGUST 2010 TYPICAL CHARACTERISTICS continued OUTPUT VOLTAGE RIPPLE DCDC PFM Mode OUTPUT VOLTAGE RIPPLE DCDC PWM Mode www ti com Ch1 VDCDC 10mV div Ch1 VDCDC 10mV div Ch2 SW 2V div Ch2 SW 2V div VINDCDC 3 6 V Load DCDC 400mA TA 25 C EN_DCDC high fut EN LDO1 low VINDCDC 3 6 V i Load Current 60mA Ta 25 C i EN DCDC high 20mAdiv EN_LDO1 low EN_LDO2 low VDCDC 1 2 V Ch4 Load Current DCDC 20mAdiv VDCDC 1 2 V EN_LDO2 low Ch3 Load Current DCDC t Time 200ns div Figure 5 Figure 6 STARTUP TIMING DCDC START UP TIMING LDOx x Q A A O 2 az ES VINDCDC 3 6 V ZS lt lt VINLDOx 2 3V ul A t Tat 25 C E 9 VLDOx 1 2 V O a gt gs 5 gt E 82 NS I gt LO z O VINDCDC 3 6 V DE TA 25 C m VDCDC 1 2 V 5 VSI Load LDOx 100mA EN_LDOx OV to 2 3V EN_DCDC low Ch3 SW 20V div Load DCDC 100mA EN DCDC OV to 3 6V Ch3 VLDOx 500mV div EN_LDO1 low EN_LDO2 low t Time 100ns div t Time 100ns div Figure 7 Figure 8 Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link s TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 SLVS810B JUNE 2009 REVISED AUGUST 2010 TYPICAL CHARACTERISTICS continued TPS650001 QUIESCENT CURRENT DCDC PFM Mode
21. IR TEXAS INSTRUMENTS TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 www ti com SLVS810B JUNE 2009 REVISED AUGUST 2010 2 25 MHz Step Down Converter with Dual LDOs and SVS Check for Samples TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 FEATURES Step Down Converters DESCRIPTION Vin Range From 2 3V to 6V The TPS65000 and TPS65001 are single chip Power Spread Spectrum Clock SSC Generation Management ICs for portable applications Both for Reduced EMI devices combine a single step down converter with two low dropout regulators The step down converter 2 25MHz Fixed Frequency Operation enters a low power mode at light load for maximum 600mAor1A TPS650061 Output Current efficiency across the widest possible range of load LDOs currents For da applications the devices can be forced into fixed frequency PWM via a pin The Vin Range From 1 6V to 6V step down converter allows the use of a small Adjustable Output Voltage inductor and capacitors to achieve a small solution Up to 300mA Output Current size The step down converter has Power Good status output that can be used for sequencing The Separate Power Inputs and Enables LDOs are capable of supplying 300mA and can Supply Voltage Supervisor TPS65001 operate with an input voltage range between 1 6V Manual Reset Input for Push Button and 6V allowing them to be supplied from the step down converter or dire
22. NTS www ti com TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 SLVS810B JUNE 2009 REVISED AUGUST 2010 TYPICAL CHARACTERISTICS continued LINE TRANSIENT RESPONSE DCDC PWM Mode i VINDCDC 3 6 V to 4 2V to 3 6V T 25 C Ch1 VINDCDC 500mV div VDCDC 1 8V DCDC Load Current 50mA Mode VINDCDC Ch2 VDCDC 20mV div t Time 100us div Figure 13 LOAD TRANSIENT RESPONSE DCDC PFM Mode VINDCDC 3 6V Tp 25 C VDCDC 1 8V Ch1 VDCDC 50mV div DCDC Load Current 60mA to 540 mA Mode GND 200mA div Ch2 DCDC Load Current t Time 100us div Figure 15 Copyright O 2009 2010 Texas Instruments Incorporated LINE TRANSIENT RESPONSE LDOx tod VINDCDC 6V VINLDOx 1 6 V to 2 3V to 1 6V TA 25 C Ch1 VINLDOx 500mV div Ch2 VLDOx 20mV div VLDOx 1 007V H LDOx Load Current 1mA EN_DCDC GND t Time 100us div Figure 14 LOAD TRANSIENT RESPONSE DCDC PWM Mode VINDCDC 3 6V Ty 25 C VDCDC 1 8V Ch1 VDCDC 50mV div DCDC Load Current 60MA to 540 mA Mode VINDCDC HE Ch2 DCDC Load Current 200mA div t Time 100us div Figure 16 Submit Documentation Feedback 11 Product Folder Link s TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 SLVS810B JUNE 2009 REVISED AUGUST 2010 I TEXAS INSTRUMENTS www ti com TYPICAL CH
23. S TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 www ti com SLVS810B JUNE 2009 REVISED AUGUST 2010 Supply Voltage Supervisor SVS TPS65001 and TPS650061 Only The SVS is made up of 4 inputs and one output The RST pin is an active low high impedance output The MR pin is an active low input suitable for connecting to a push button circuit to allow manual reset generation The RSTSNS pin is an analog input pin used for voltage comparison The TRST pin is connected to an external capacitor allowing the reset timing to be set in the application The VINDCDC pin is the main supply input for the control circuits and the switch mode converter VINDCDC RSTSNS Reset Logic and Timing 0 6V Reference Figure 28 SVS Block Diagram Each input can individually trigger RST to go active Table 1 outlines the paths to activate the reset Table 1 RST Generation Table INPUTS OUTPUTS VINDCDC MR VRSTSNS RST 0 4 lt V lt UVLO X X Low UVLO gt VIHMA 0 6 V Low UVLO gt VIHMA gt 0 6 V High Z gt UVLO lt VILMA X Low Copyright O 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Link s TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 TPS65000 TPS65001 TPS650001 O TPS650003 TPS650006 TPS650061 SLVS810B JUNE 2009 REVISED AUGUST 201
24. UT FILTER DESIGN INDUCTOR AND OUTPUT CAPACITOR Inductor Selection The typical value for the converter inductor is 2 2uH output inductor Larger or smaller inductor values in the range of 1 5uH to 3 3uH can be used to optimize the performance of the device for specific operation conditions The selected inductor has to be rated for its dc resistance and saturation current The dc resistance of the inductance will influence directly the efficiency of the converter Therefore an inductor with lowest dc resistance should be selected for highest efficiency See SLVA157 for more information on inductor selection Equation 5 calculates the maximum inductor current under static load conditions The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 6 This is recommended because during heavy load transient the inductor current will rise above the calculated value V q OUT V Al Vour X N l max louTmax 2 With f Switching Frequency 2 25MHz typical L Inductor Value Al Peak to Peak inductor ripple current li max Maximum Inductor current The highest inductor current will occur at maximum Viy Open core inductors have a soft saturation characteristic and can usually handle higher inductor currents versus a comparable shielded inductor A more conservative approach is to select the inductor current rating just for the maximum switch current of the correspondi
25. _LDO2 VLDO2 e o VLDO2 VINLDO1 2 8V FB_LDO2 10uF VINLDO2 P AGND P Figure 32 Typical TPS650001 Application Schematic TPS650061 EN DCDC SN eM VDCDC ViN S e VINDCDC 475kQ 1 2V FB DCDC 1 10uF 10uF n MODE lr 7 H E 475kQ op gt IN A p 470kQ 100kQ 37982 RSTSNS Vin PG PG IN 0 1pF Ze i uod 232kQ 470kQ ca RST O RST A a ewe T MR VLDO1 LAL Vm p T TRST VLDO1 ha 3 3V ba 100nF FB_LDO1 i VN 4 EN_LDO1 EN_LDO2 1 VLDO2 o VLDO2 VINLDO1 1 8V T FB_LDO2 10uF VINLDO2 le AGND PGND P Figure 33 Typical TPS650061 Application Schematic 22 Submit Documentation Feedback Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 D T Mes TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 www ti com SLVS810B JUNE 2009 REVISED AUGUST 2010 REVISION HISTORY Changes from Original June 2009 to Revision A Page Added device numbers TPA650001 TPS650003 TPS650006 and TPA650061 to the data sheet 1 Changed the PG pin connection From VDCDC To Vy in the application circuit o ooninninninnnnnnnnnnnnnnnnrnr nro ro coconanoss 1 Changed resistor values for VLDO1 and VLDO2 in the application circuit 1 Changed the configuration of the PG and RST pins in the application circuit sse 1 Added Note 2 to the Electrical Characteristics table i 3
26. ctly from the main battery Adjustable moset TAME The step down converter and the LDOs have Adjustable Reset Voltage separate voltage inputs and enables allowing for 3mm x 3mm 16 Pin QFN TPS65000 design and sequencing flexibility 3mm x 3mm 20 Pin QFN TPS65001 The TPS65000 is available in a 16 pin leadless package 3mm x 3mm QFN The TPS65001 extends functionality by adding a Supply Voltage Supervisor SVS The SVS allows APPLICATIONS Point of Load Embedded Processor Power maximum flexibility by having the reset voltage set Cell Phones Smart Phones with two external resistors and the reset time set by PDAs Pocket PCs a small external capacitor In addition an active low Manual Reset input allows the SVS to be connected to a push button for external control The TPS65001 is available in a 20 pin leadless package 3mm x 3mm QFN Portable Media Players SSCG TPS65000 1 Oscillator EN_DCDC VDCDC gt 3 34 LF gt Vin OK 100kQ o PG o RST i Step Down 600mA Supply Voltage Supervisor LDO1 300mA VINLDO1 EN LDO2 LDO2 300mA O VDCDC VINLDO2 Bandgap Reference TPS65000 01 Joint Function Pin TPS65001 Only Function Pin A Please be aware that an important notice concerning availability standard warranty
27. current limit mA VINLDOx 2 3V 210 700 FB LDOx pin current 0 1 uA FB_LDOx voltage Adjustable Voyy mode only 0 5 V VINLDOx 2 3V lour 250mA 370 mV Vpo Dropout Voltage VINLDOx lt 2 3V loyr 175mA 370 mV RS DA VINLDOx 2 3 6V 3 5 3 5 Output Voltage Accuracy 8 lo 1mA to 175mA VINLDOx 1 6V 6V 3 5 3 5 VLDOx 1 2V Load regulation Cra a VIMEDON S SDN 1 5 1 5 Line regulation RET PESO A BR eee 0 5 0 5 PSRR Power Supply Rejection Ratio ai F Vin 2 3V 40 dB tramp VLDOx Ramp Time VLDOx ramp from 10 to 90 200 us Bue dat discharge resistance at EN LDOx low 450 Q Tsp Thermal shutdown Increasing temperature 150 C Thermal shutdown hysteresis Decreasing temperature 30 C SUPPLY VOLTAGE SUPERVISOR Vin Input voltage for RSTSNS pin 0 6 V t mapeaLitc4 MR Deglitch time 1 ms Vin Input high voltage MR pin only 1 2 6 V Vit Input low voltage MR pin only 0 0 4 V likg High input leakage current RST pin 0 01 0 1 uA Vor Output low voltage RST pin only lo 100uA 0 4 V ITRST Reset timer capacitor current 1 6 2 2 2 uA Reset voltage trip voltage Voltage rising Reset time begins 0 58 0 6 0 63 V Reset voltage trip hysteresis Voltage falling RST pulled low 5 6 7 8 Copyright O 2009 2010 Texas Instruments Incorporated Max output voltage VLDOx 3 6V Vpo VINLDOx VLDOx where VINLDOx VLDOx nom 100mV Output voltage specification does not include tolerance of external programming resistors Submit D
28. defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 1 by weight in homogeneous material 9 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature e Multiple Top Side Markings will be inside parentheses Only one Top Side Marking contained in parentheses and separated by a will appear on a device If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top Side Marking for that device Important Information and Disclaimer The information provided on this page represents Tl s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall Tl s liability arising out of such information exceed the total purchase price of the TI part s at
29. duct Data Sheet for details regarding the exposed thermal pad features and dimensions A B C Quad Flatpack No leads QFN package configuration D E F Falls within JEDEC MO 220 3 TEXAS INSTRUMENTS www ti com THERMAL PAD MECHANICAL DATA RUK S PWQFN N20 PLASTIC QUAD FLATPACK NO LEAD THERMAL INFORMATION This package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink The thermal pad must be soldered directly to the printed circuit board PCB After soldering the PCB can be used as a heatsink In addition through the use of thermal vias the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device or alternatively can be attached to a special heatsink structure designed into the PCB This design optimizes the heat transfer from the integrated circuit IC For information on the Quad Flatpack No Lead QFN package and its advantages refer to Application Report QFN SON PCB Attachment Texas Instruments Literature No SLUA271 This document is available at www ti com The exposed thermal pad dimensions for this package are shown in the following illustration PIN 1 INDICATOR Exposed Thermal Pad 1 70t0 10 1 70 0 10 Bottom View Exposed Thermal Pad Dimensions 4209762 E 12 12 NOTE All linear dimensions are in millimeters Ria TEXAS INSTRUMENTS www ti com LAND PATTERN DATA
30. e of 22uF without having large output voltage under and overshoots during heavy load transients Ceramic capacitors having low ESR values result in lowest output voltage ripple and therefore are recommended See the recommended components If ceramic output capacitors are used the capacitor RMS ripple current rating will always meet the application requirements The RMS ripple current is calculated as 1 Vout Vin 1 x Lxf 2x 43 8 At nominal load current the device operates in PWM mode and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor Irmscout Vout X 4 Your VN y 1 Lx f 8 x Cour X f ESR AVour Vour X 9 Where the highest output voltage ripple occurs at the highest input voltage Vi At light load currents the converter operates in Power Save Mode and the output voltage ripple is dependent on the output capacitor value The output voltage ripple is set by the internal comparator delay and the external capacitor The typical output voltage ripple is less than 196 of the nominal output voltage The adjustable output voltage of the DCDC converter is calculated by Equation 1 in the Step Down Converter To keep the external resistor divider network robust against noise an external feed forward capacitor is required for optimum load transient response The value of feed forward capacito
31. erter N A 600MA DCDC VOUT 1 2V fixed LDO1 3 3V fixed LDO2 1 8V fixed DCDC Converter N A 600MA DCDC VOUT 1 5V fixed LDO1 1 8V fixed LDO2 3 3V fixed DCDC Converter N A 600MA DCDC VOUT 1 2V fixed LDO1 3 3V fixed LDO2 1 8V fixed DCDC Converter 1A VOUT externally adjustable TPS65001 QFN 3x3 20 RUK Included Included TPS65001RUK CFQ TPS650001 QFN 3x3 16 RTE Included TPS650001RTE DAG 40 C to 85 TPS650003 QFN 3x3 16 RTE Included TPS650003RTE DAH TPS650006 QFN 3x3 16 RTE Included TPS650006RTE DAI TPS650061 QFN 3x3 20 RUK Included Included TPS650061RUK DAJ 1 TPS650001 TPS650003 and TPS650006 are spin versions of TPS65000 TPS650061 is a spin version of TPS65001 Different DCDC current limits and fixed voltage outputs of the DCDC and LDOs are available Please contact your Texas Instruments sales representative for further information 2 For the most current package and ordering information see the Package Option Addendum at the end of this document or see the TI website at www ti com ABSOLUTE MAXIMUM RATINGS over operating free air temperature range unless otherwise noted MIN MAX UNIT On all pins except AGND PGND EN_DCDC VLDO1 VLDO2 FB_LDO1 FB_LDO2 FB_DCDC pins with Input voltage range respect to AGND V On EN DCDC with respect to AGND 0 3 Vin 0 3 lt 7 Output voltage range On VLDO1 VLDO2
32. esign Each LDO has a separate voltage input and enable signal The input can be tied to the output of the step down converter or the output of another voltage source Each LDO output discharge to ground automatically when EN_LDOx goes low A resistor network is needed to set the output voltage of the LDOs Fixed voltage output versions are also available contact Texas Instruments sales representative for more information The LDOs are general purpose devices that can handle inputs from 6V down to 1 6V making them suitable for direct connection to the battery Figure 24 illustrates the necessary connections for LDO1 The same architecture applies to LDO2 14 Submit Documentation Feedback Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 PI DENIS TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 www ti com SLVS810B JUNE 2009 REVISED AUGUST 2010 VLDO1 VINLDO1 e e ol 0 4 Diode Ripo1_1 EN LDO1 4L el DISCHG LIE LCounon FB_LDO1 bd ZLoaD VREF LD01 di RLop1 2 AGND PGND e la G n Figure 24 LDO Block Diagram and Output Voltage Setting The output voltages of the LDOs are set by Equation 2 Rioor 4 Ripoi 2 Ripo1_2 Vi po1 VeB_LDOo1 X Ru poi 4 Ripo1 2
33. h Tl components or services are used Information published by Tl regarding third party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of significant portions of Tl information in Tl data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Tl is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice Tl is not responsible or liable for any such statements Buyer acknowledges and agrees that it is solely responsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of Tl components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expe
34. hermal vias the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device or alternatively can be attached to a special heatsink structure designed into the PCB This design optimizes the heat transfer from the integrated circuit IC For information on the Quad Flatpack No Lead QFN package and its advantages refer to Application Report QFN SON PCB Attachment Texas Instruments Literature No SLUA271 This document is available at www ti com The exposed thermal pad dimensions for this package are shown in the following illustration PIN 1 INDICATOR Exposed Thermal Pad 1 70 0 10 1 70 0 10 Bottom View Exposed Thermal Pad Dimensions 4206446 3 N 07 13 NOTE A All linear dimensions are in millimeters Ria TEXAS INSTRUMENTS www ti com LAND PATTERN DATA RTE S PWQFN N16 PLASTIC QUAD FLATPACK NO LEAD Note D NOTES A 99M Example Board Layout Example Stencil Design Note E Eee JUU fo O O O 3 0 230 1 3 8 4x0 7 D w 3 75 mr e a Non Solder Mask Defined Pad EN Example Via Layout Design i Via pattern may vary due 68 solder coverage on center pad 3 to layout constraints Example a Note D F N Solder Mask Opening Note F 0 85 Pad Geometry 0 07 Note C All around 4209446 2 H 07 13 All linear dimensions are in millimeters This drawing is subject to
35. ill be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but Tl does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device Eco Plan The planned eco friendly classification Pb Free ROHS Pb Free RoHS Exempt or Green RoHS amp no Sb Br please check http www ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Addendum Page 1 H PACKAGE OPTION ADDENDUM IR TEXAS INSTRUMENTS www ti com 11 Apr 2013 Pb Free RoHS Tl s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 1 by weight in homogeneous materials Where designed to be soldered at high temperatures Tl Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS amp no Sb Br TI
36. l up on MR is required 6 Submit Documentation Feedback Copyright O 2009 2010 Texas Instruments Incorporated Product Folder Link s TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 1 TEXAS INSTRUMENTS TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 www ti com SLVS810B JUNE 2009 REVISED AUGUST 2010 FUNCTIONAL BLOCK DIAGRAM TPS65000 TPS65001 3 x 3 mm QFN Oscillator VINDCDC SW EN_DCDC FB_DCDC MODE PG MR TRST RSTSNS RST VINLDO1 VLDO1 EN_LDO1 FB_LDO1 PGND VINLDO2 VLDO2 EN_LDO2 FB_LDO2 AGND Copyright 2009 2010 Joint Function Pin TPS65001 Only Function Pin Texas Instruments Incorporated Product Folder Link s TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 Submit Documentation Feedback 7 TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 SLVS810B JUNE 2009 REVISED AUGUST 2010 Efficiency 96 Efficiency 96 100 90 80 70 60 50 40 30 20 10 0 0 00001 EFFICIENCY DCDC 1A TPS650061 ONLY PFM Mode EFFICIENCY DCDC 600mA PFM Mode vs I TEXAS INSTRUMENTS www ti com TYPICAL CHARACTERISTICS EFFICIENCY DCDC 600mA PWM Mode OUTPUT CURRENT 6V 2 3V 5V 4 5V Les N lt o 0 0001 0 001 0 01 lo Output Current A Figu
37. ng converter It must be considered that the core material from inductor to inductor differs and will have an impact on the efficiency especially at high switching frequencies Notice that the step down converter has internal loop compensation As the internal loop compensation is designed to work with a certain output filter corner frequency calculated as follows fo L__ withL 2 2uH Cour 104F This leads to the fact the selection of external L C filter has to be coped with the above formula The product of L x Cour should be constant while selecting smaller inductor or increasing output capacitor value See Table 2 and the typical applications for possible inductors Table 2 INDUCTORS INDUCTOR TYPE Inductance uH SUPPLIER Max Dimensions mm MIPS2520D2R2 2 0 FDK 2 5 x 2 0 x 1 0 MIPSA2520D2R2 2 0 FDK 2 5 x 2 0 x 1 2 KSLI 252010AG2R2 2 2 Htachi Metals 2 5 x 2 0 x 1 0 LQM2HPN2R2MJOL 2 2 Murata 2 5 x 2 0 x 1 2 LPS15222 2 2 Coilcraft 3 0 x 3 0 x 1 5 Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Link s TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 TPS65000 TPS65001 TPS650001 A TPS650003 TPS650006 TPS650061 SLVS810B JUNE 2009 REVISED AUGUST 2010 www ti com Output Capacitor Selection The advanced Fast Response voltage mode control scheme of the converter allows the use of small ceramic capacitors with a typical valu
38. ocumentation Feedback Product Folder Link s TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 5 TPS65000 TPS65001 TPS650001 O TPS650003 TPS650006 TPS650061 SLVS810B JUNE 2009 REVISED AUGUST 2010 www ti com PIN ASSIGNMENTS TPS65000 TPS65001 RTE PACKAGE RUK PACKAGE TOP VIEW TOP VIEW 16 15 14 13 20 19 18 17 16 PIN FUNCTIONS 2 1 0 DESCRIPTION NAME TPS65000 TPS65001 VINDCDC 6 8 Input voltage to DCDC converter and all other control blocks EN_DCDC 8 10 I Enable DCDC converter MODE 7 9 l Selects force PWM or PWM PFM automatic transition mode VINLDO1 13 15 Input voltage to LDO1 EN_LDO1 1 3 I Enable LDO1 VINLDO2 16 18 I Input voltage to LDO2 EN_LDO2 2 4 I Enable LDO2 PGND 4 6 Power ground Connected to the PowerPADTM AGND 10 12 Analog ground Star back to PGND as close to the IC as possible PG 3 5 O Open drain active low power good output SW 5 7 O Switch pin connect inductor here FB_DCDC 9 11 I Voltage to DCDC error amplifier VLDO1 12 14 O LDO1 output voltage VLDO2 15 17 O LDO2 output voltage FB_LDO1 11 13 Voltage to LDO1 error amplifier FB_LDO2 14 16 I Voltage to LDO2 error amplifier RSTSNS 19 I Voltage for RST generation RST 20 O Open drain active low reset output MR 1 Active low input to force a reset 1 TRST 2 1 0 Capacitor connection for setting reset time 1 External pul
39. ow i Q EN_LDO1 2 high lour OMA 50 57 lour 0 mA and no switching 2 EN_DCDC high MODE high 4 mA EN_LDO1 2 low loyr OMA Isp Shutdown Current EN_DCDC low EN_LDO1 and EN_LDO2 low 0 16 2 2 uA 1 The design principle allows only VINDCDC to be the highest supply in the system if different voltage input supplies separately to DCDC converter and LDOs meaning VINDCDC gt VINLDO1 VINDCDC gt VINLDO2 2 The max quiescent current of enabling LDOs is 8uA higher for TPS650001 TPS650003 TPS650006 and TPS650061 Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 Submit Documentation Feedback 3 TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 SLVS810B JUNE 2009 REVISED AUGUST 2010 ELECTRICAL CHARACTERISTICS continued Over full operating ambient temperature range typical values are at T4 25 C Unless otherwise noted specifications apply for condition Vy EN LDOx EN DCDC 3 6 V External components L 2 2 uH Cour 10 uF Cy 4 7 uF see the arameter measurement information I TEXAS INSTRUMENTS www ti com PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT TPS65001 MODE low EN_DCDC high EN_LDO1 2 low 24 37 uA lout 0 mA and no switching Operating quiescent cur
40. r should be in the range between 22pF and 33pF provided the equivalent resistance of RDC1 RDC2 in Equation 1 is approximately 300kO Scale change on RDC1 RDC2 would apply a scale change to the feed forward capacitor to keep the RC product a constant Input Capacitor Selection Due to the nature of the DCDC converter having a pulsating input current a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes It is critical to put the input capacitor as close to the VINDCDC pin as close as possible with the clean GND connection provided The same consideration is applied for the output capacitor and the inductor The converters need a ceramic input capacitor of 10uF The input capacitor can be increased without any limit for better input voltage filtering Table 3 Capacitors CAPACITANCE SUPPLIER TYPE 22uF TDK C2012X5R0J226MT Ceramic 22uF Taiyo Yuden JMK212BJ226MG Ceramic 10uF Taiyo Yuden JMK212BJ106M Ceramic 10uF TDK C2012X5R0J106M Ceramic 10uF Murata GRM188R60J106M69D Ceramic 20 Submit Documentation Feedback Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 14 TEXAS INSTRUMENTS TPS65000 TPS65001 3 TPS650001 TPS650003 TPS650006 TPS650061 www ti com SLVS810B JUNE 2009 REVISED AUGUST 2010 APPLICATION CIRCUITS TPS
41. re 1 vs OUTPUT CURRENT 0 1 0 0 00001 Submit Documentation Feedback 0 0001 0 001 0 01 lo Output Current A Figure 3 0 1 Efficiency Efficiency 100 90 Ta 80 vs OUTPUT CURRENT Il 12v LI 25 C 42N 70 60 2 8V 50 40 5 5V 30 20 10 0 0 00001 0 0001 0 001 0 01 0 1 1 lo Output Current A Figure 2 EFFICIENCY DCDC 1A TPS650061 ONLY PWM Mode 100 90 PTA 7 25 C 80 vs OUTPUT CURRENT 70 60 3 6V 5 5V 50 40 30 20 10 0 0 00001 0 0001 0 001 0 01 0 1 1 lo Output Current A Figure 4 Copyright O 2009 2010 Texas Instruments Incorporated Product Folder Link s TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 MENS TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 SLVS810B JUNE 2009 REVISE
42. rent MODE low EN DCDC low Q p 99 EN_LDO1 2 high lour OMA 55 62 pA lour 0 mA and no switching 9 EN_DCDC high MODE high 4 mA EN_LDO1 2 low lour OMA Isp Shutdown Current EN_DCDC low EN_LDO1 and EN_LDO2 low 11 17 uA DIGITAL PINS EN_DCDC EN_LDO1 EN_LDO2 MODE PG MR RST Vin High level input voltage 1 2 V Vit Low level input voltage 0 4 V VoL Low level output voltage PG and RST pins only lo 1004A 0 4 V MODE EN DCDOC EN LDO 1 EN LDO 2 tied to likg Input leakage current GND or VINDCDG 0 01 0 1 uA OSCILLATOR few Oscillator frequency 1 722 2 25 2 847 MHz STEP DOWN CONVERTER POWER SWITCH High side MOSFET on resistance 240 480 Rosfon a VINDCDC Vas 3 6V mQ Low side MOSFET on resistance 185 380 2 3 V lt VINDCDC lt 2 5V 300 lo DC output current mA 2 5 V lt VINDCDC lt 6V 600 la DC output current TPS650061 2 7 V lt VINDCDC lt 6V 1000 mA ONLY liae o MOP ens ese VINDEDE 36V 800 1000 1400 mA Forward current limit PMOS and ILIMF NMOS TPS650061 ONLY 2 7 V lt VINDCDC lt 6V 1200 1500 1680 mA 1 Thermal shutdown Increasing junction temperature 150 o Sp Thermal shutdown hysteresis Decreasing junction temperature 30 STEP DOWN CONVERTER OUTPUT VOLTAGE VDCDC Adjustable output voltage range 0 6 VINDCDC V DCDC FB DCDC pin current 0 1 uA Viet Internal reference voltage 0 594 0 6 0 606 V Output Voltage Accuracy PWM MODE high sus Mode 2 3 lt VINDCDC lt 6V 1 3 Re A VDCDC Output Voltage Accuracy PFM MODE low
43. rtise to create and implement safeguards which anticipate dangerous consequences of failures monitor failures and their consequences lessen the likelihood of failures that might cause harm and take appropriate remedial actions Buyer will fully indemnify Tl and its representatives against any damages arising out of the use of any TI components in safety critical applications In some cases TI components may be promoted specifically to facilitate safety related applications With such components Tl s goal is to help enable customers to design and create their own end product solutions that meet applicable functional safety standards and requirements Nonetheless such components are subject to these terms No TI components are authorized for use in FDA Class III or similar life critical medical equipment unless authorized officers of the parties have executed a special agreement specifically governing such use Only those TI components which TI has specifically designated as military grade or enhanced plastic are designed and intended for use in military aerospace applications or environments Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer s risk and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use TI has specifically designated certain components as meeting ISO TS16949 requirements
44. t value This voltage positioning is intended to minimize the voltage undershoot of a load step from light to heavy loads as when a processor moves from sleep to active modes and the voltage overshoot at load throw off Figure 22 shows the voltage positioning behavior for a light to heavy load step Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Link s TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061 TPS65000 TPS65001 TPS650001 M J 2 7 CENTS TPS650003 TPS650006 TPS650061 SLVS810B JUNE 2009 REVISED AUGUST 2010 www ti com Output voltage Vour nom 1 Light load PFM Mode Vour nom moderate to heavy load PWM Mode p Time Figure 22 PFM Voltage Positioning Pulling the MODE pin to DC ground will result in automatic transition between PFM and PWM modes to maximize efficiency The DCDC converter output automatically discharges to ground through an internal 4500 load when EN_DCDC goes low or when the UVLO condition is met SOFT START The step down converter has an internal soft start circuit that limits the inrush current during start up During soft start the output voltage ramp up is controlled as shown in Figure 23 n I h istat L tramp Figure 23 Soft Start LINEAR REGULATORS The two linear dropout regulators LDOs in the TPS65000 and TPS65001 are designed to provide flexibility in system d
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