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1. 15 11 15 Failure Memory Video Card Video RAM Failure CPU Registers Keyboard Controller Reset Failure Keyboard D ata Keyboard Input Chipset Initialization BIOS ROM Checksum System Timer Test ASIC Register CMOS RAM 1st DMA Controller 2nd Controller Video Vertical Retrace Video Memory Video Adapter First 64K B RAM Interrupt Vectors Initialize Video Video Memory Failure Passed Post OK BIOS ROM Checksum 213 Chapter 4 COMPAQ ont d Beep Code 25 11 25 EURO MYLEX Beep Code 1L 2L 1L 151L 11 25 11 11 3511 11 45 11 11 5511 1L 65 1L 11 75 11 11 85 11 1L 951L 1L 10S 1L 1L 115 1L 1L 12S1L 1L 13 1L 1L 14 1L Beep Code 15 25 11 15 11 25 11 35 3L 214 Failure General Error Video Adapter Failure Start of Test Video Adapter Keyboard Controller Keyboard PIC 0 PICA DMA Page Register RAM Refresh RAM Data Test RAM Parity Check 1st DMA Controller CMOS RAM 2nd Controller CMOS Battery Check CMOS Checksum BIOS ROM Checksum Failure Start of POST Initialization Error System Board Video Adapter EGA VGA Adapter Keyboard Controller BIOS Beep Codes IBM ont d Beep Code Failure Continuous or Repeating Short Power Supply Microid Research The beep codes for the Microid Research S are necessary to distinguish between multiple meanings for the hex codes and for this reason are included
2. 3 71 Monocrome t N N e 26 Cursor Postion 26 Display Cursor Reference 26 Display Hit lt ESC gt Message SeMmoy 51 Memory Read Write Test 51 Base 640K Memory Test 4 A S i 6 4 4 0 4 0 0 0 0 6 6 2 2 1 1 1 N 7 7 7 2 7 7 7 7 7 7 7 2 2 2 N gt 38 BIOS POST Code Listings Hi Evtended Memory CMOS Vai 81 Chenkforsof Hat Re 57 Clear Extended Memory 51 Memory Rat Write Teton IK 51 EuexelMemwyTet 31 Resize Extended Memo 1527 ReenterRed Mode Restore CPU 5 1 8 1 5 7 5 1 5 1 5 1 5 2 8259 Initialization 8 1 8 1 8 1 8 3 8 3 6 181 Keyboard Test Keyboard Reset 81 Sud Key and Ba Te CPT 83 Compare Memory Sze with CMOS 39 EM 3 26 KCMOC CMOS Equipment Chek 26 CMOSSeup Entre 4 Rem dgeChpst 26 Display Power On Message 26 Display Wait and Mouse Check 26 Shadow any Option ROMs 28 6 j 6 4 j 6 6 6 j 6 j Nm 40 Initialize 5 Settings 2 2 2 2 2 2 2 7 7 8 8 1 EM EN EM m EN BIOS POST Code Listings AMI Color Continued Memory Wait States Display Configur
3. MEM ECT 21 2 7 Extended EMOS cited 22 3 0 aa 22 3 1 Programmable Interrupt Controller 22 3 2 PIT Programmable Interval Timer ss 23 20 BIO 23 4 1 Boot Load 23 4 2 BIOS CHECKSUM 23 o tatetar vd aad 24 Table of Contents 24 24 5 2 Protected INL OCG ie 25 5 3 e 25 DURO 26 5 5 ROM Shadow 26 26 DMA is ENT 27 60 MO A POS ON 27 SEIN PEOR Enable 27 send POTS atada 27 6 3 Parallel Mose 27 DIVE O mardi asd 28 FlOppy DIV Bs aaa 28 6 6 Miscellaneous I Diarias 28 VELIS ARI tM Tr OE 28 7 1 Monochrome Display as 28 J2 CA 28 Nide A 29 TAVid RAM 29 RO 29 8 1 Keyboard Conlara dara 29 A A 29 8 3 Keyboard 30 ala TIU 30 DUO ETOT DUSPI a 30 10 0 FR OSI cag
4. 81 initialize Keyboard Controler Bx Detet PI2Mowe 80 24 40 41 2 6 3 1 1 3 2 1 2 2 1 8 1 jali 6 x 24 4 0 66 __ ActivateADMModule j Configures PnP and PCI Devices Initialize D MAC Initialize RTC D ate and Time Test for Total Memory Display Total Mid Post Initialization of Chipset Registers 2 3 6 1 Detect Ports N PU 51 LN w w w 3 51 Adjust for Memory Holes 26 Update CMOS Memory Total Initializes IPL Boot D evices 70 5 1 2 6 E 30 90 90 41 41 22 58 41 Setup Boot 4i Set Boot Processor for POST a Setup Application Processors EM 9 52 BIOS POST Code Listings AMI BIOS 8 Continued Re enable Cache Exit Early CPU Initialization AMI BIOS 8 Boot Block Initialization N ote These codes will appear while updating the BIOS flash Post Code Description Is done NMI Disabled Wakeup Save Power on CPUID in Scratch CMOS D2 D3 D4 D5 D7 DA Additional Chipset Initialization Enable Cache Test Base 512K RAM E1 E8 OEM specific Errors Reserved for Chipset and EC EE System Manufacturers AMI BIOS 8 Boot Block Recovery N ote These codes should only appear if a malfunction occurs while updating the BIOS flash ROM DO 22 D3 D4 D5 CopyBootblocktoRAM D6 D7 D8 2
5. ME 30 CHAPTER 31 BIOS Post Code LISIS parda ad 31 BIO S rra 31 AMIDUS DIO raton mida 33 aiii HR arate 36 BIO S loaded exi bu vultu ld 41 AMI BIOS lin 46 AMI Win Boot Block R COVETY ssssssssssssssesssssssssssssssssssssssessesssssssssessssssssnseess 50 AMLBIOS Bn 51 AMI BIOS 8 Boot Block Initialization se 53 AMI BIOS 8 Boot Block Recovery eren 53 Award BIOS original 54 Table of Contents Award XT Version ta 55 AWA VEFSN 56 O E 57 Award Poe BIOS anat 60 Award Elite Version 4 51 PG 62 Award BIOS Verona aida 64 Award 6 0 Quick PO Sisi 69 Award 6 0 Boot Bloc siria intel 70 COMPAQ er aet QU 71 nadar 76 Pavillion Series 3100 amp 8000 PCs sene 78 EP Vectra BIO Rena aid 84 HE Vet 85 HP Vectra OS 89 IBMAT BIOS tarea cd data 92 IBM dada 95 Fite CASIO BIOS ven RODA 98 Intel 810 Boot Block Recovery sss 98 Intel CA810E Runtime COME in 99 Intel CU S20 BIOS ui 104 Intel CC820 Boot Block Recovery eerte 105 Intel
6. disable successful Adjust memory size depending on relocation shadow 58 Memory size adjusted for relocation shadow Going to clear hit DEL message 59 Hit lt DEL gt message cleared lt WAIT gt message displayed About to start DMA and interrupt controller test E DMA page register test passed To do D MA 1 base register test 62 MA 1 base register test passed To do DMA 2 base gister test MA 2 base register test passed To program 1 and N J MA 1 and 2 programming over To initialize 8259 interrupt controller ck key to issue keyboard reset command 81 eyboard reset error stuck key found To issue keyboard controller interface test command 82 Keyboard controller interface test over To write command byte and init circular buffer 83 Command byte written global data init done To check for lock key xtended sources enabling is in progress eyboard test started Clearing output buffer checking for 84 Lock key checking over To check for memory size mismatch with CMOS 85 Memory size check done To display soft error and check for password or bypass setup 86 Password checked About to do programming before setup 87 Programming before setup complete To uncompress SETUP code and execute CMOS setup 88 etumed from CMOS setup program and screen is cleared bout to do programming after setup 147 3 Intel
7. test over Going to setup timer data area and printer base address A Return after setting timer and printer base addresses G oing to set the RS 232 base address Returned after RS 232 base address Going to do any initialization before coprocessor test Required initialization before coprocessor is over G oing to initialize the coprocessor test Coprocessor initialized G oing to do any initialization after coprocessor test Initialization after coprocessor test is complete G oing to check extended keyboard keyboard ID and num lock Going to display any soft errors Soft error display complete G oing to set keyboard typematic rate Keyboard typematic rate set To program memory wait states Going to enable parity N MI NMI and parity enabled Going to do any initialization required before giving control to optional ROM at E000 Initialization before E000 ROM control over E000 ROM to get control next Retumed from E000 ROM control Going to do any initialization required after E000 optional RO M control 155 gt E 3 Going to display the system configuration Put CGA Int10 module if present in shadow form the runtime SMBIO S image in shadow Copying of code to specific area done oing to give control to Int19 boot loader Intel SE440BX BIOS Uncompressed IN IT Code C heck points Post Code Description 06 Title system hardware 08 chip
8. 4 Initialize PCI bus and devices read ESCD amp allocate resources Check video configuration against CMOS VGA or MDA Initialize all video adapters in system Shadow video BIOS ROM Put processor in big real mode flat mode memory addressing up to 4GB Post display manager initialization video screen error codes now visible Reset and test keyboard first try only warm reset Reset and test keyboard controller both warm and cold reset oO 7 Initialize and register via SMM through APIC bus al NIN ES 9 EN 175 Chapter 3 2 Test extended memory address lines Jump to UserPatch1 E SI NI DI DIO ajo fH gt 1 Ol Sle serial and HD D controller Clear CMOS shutdown Late PO ST core initialization of devices Configure MCD devices Initialize and detect PC compatible PnP ISA devices parallel serial etc Test extended memory 4MB to top of memory 176 BIOS POST Code Listings N Detect amp test for mouse and auxiliary device on keyboard controller Install CD ROM for boot Jump to UserPatch2 Initialize GPNV areas in D MI Search for option RO Ms One long two short beeps on checksum failure of an option ROM Scan for User Flash RO Ms MP Table initialization wa
9. POST code to beuncompresed 08 CMOS checksum calculation to be doneret 08 Any initialization before keyboard to be doneret 0 Keyboard controller 1 free To issue the BAT command to the keyboard controller Any initialization after keyboard controller BAT to be done next Keyboard command byte written Going to issue Pin 23 24 blocking unblocking command 11 Going to check pressing of lt INS gt lt END gt key during poweron 12 To init CMOS if Init CMOS in every boot is set or lt END gt key is pressed Going to disable DMA and interrupt controllers 99 3 Intel CA810E Runtime Code Continued Video display is disabled and port is initialized Chipset init about to begin 8254 timer test about to start About to start memory refresh test Memory refresh line is toggling G oing to check 15 pis On OFF time To read 8042 input port and disable mega key Green PC feature Make 5 cade segment writeable To do any setup before int vector init Interrupt vector initialization to begin To clear password if necessary Any initialization before set video mode to be done Going for monochrome mode and color mode setting Different buses init system static output devices to start if present To give control for any setup required before optional ROM check To look for optional video ROM and give control To give control to do any processing after video ROM ret
10. 1 CO CO CO CO GO CO GO GO CO CO CO CD CO wlw C2 WO CO GO 1 1 gt c C2 ow ER O Co E HE a Co R N ra c Co R Co Nw OS o ol o co C W N R o 0354 81 86 gt 8042 Didn t Accept Write Byte 8042 Failed Generate HPINT on IRQ 12 8042 Failed Generate HPINT on IRQ 11 8042 Failed To Generate HPINT on IRQ 10 8042 Failed To Generate HPINT on IRQ 15 Keyboard is D ead or Not Connected No Result from Keyboard Self Test Cmd Keyboard Self Test Failed BIOS POST Code Listings o 050 EE ox 0700 ma 0705 0706 0707 Mem Cycles too fast In Dynamic Mode 0709 070 tms Fn NE onc NN Hm DNE NE tms DAN rwr DCN P lt Bad DMA Page Register X Reg 0 7 HP HIL Controller Failed Self Test X D ata HP HIL Device Test Failed 51 Lower 640K Failed Read Write Test ForX 0 24 6 gt 0 023 Z gt 0 Bad U13 1357 Y gt 0 Bad U43 Z gt 0 Bad U33 E E N 8 Y gt 0 Bad 022 Z gt 0 Bad 0
11. E w cm 9 LN 9 3 Phoenix Version 4 Release 6 0 Continued HS HI EmeFiPmmg I ForF2 Key Smoke nitialize POST Error Manager nitialize Error Logging 26 26 26 66 4 26 70 27 ETE 41 Initialize Error Display Function Initialize System Error Handler PnPnd Dual CMOS optional 66 _ Initialize Notebook D ocking optional 66 Initialize Notebook D ocking Late Force Check optional Extended Checksum optional Redirect Int 15h to enable remote keyboard Redirect Int 13 to Memory Technologies D evices such as RO M RAM PCMCIA and serial disk 2 0 8 3 8 1 7 0 8 1 2 6 2 6 1 2 6 1 3 1 2 6 1 7 0 2 7 24 2 7 EN 208 BIOS POST Code Listings Phoenix Version 4 Release 6 0 Continued Redirect Int 10h to enable remote serial video Re map I O and memory for PCMCIA __ Initialize digitizer and display message 2 Unknown Interrupt For Boot Block in Flash ROM Phoenix Version 4 0 Release 6 Post Diag Code Sect Description Ei 60 209 3 Phoenix for Boot Block in Flash Continued Boot to Mini DOS Clear Huge Segment Boot to Full DOS Phoenix Medallion BIOS See Award BIOS Version 6 Western Digital BIOS Post Diag Code Sect Description Begin CPU Val
12. N N N E gt Reset PIC 3 2 5 1 Test DRAM Refresh 3 2 5 3 8 2 4 5 3 5 5 5 Test 8742 Keyboard Controller Set ES Segment Register to 4 GB Enable A 20 Line 51 57 5 56 79 Autosize DRAM y 1 1 1 1 1 1 Chapter 3 3 5 2527 4 m 5 36 24 7 2427 E 9 2758 2 2 2 4 N 1 0 6 5 6 3A lt 24 2 7 3D 2427 4 24 27 42 27 51 Initialize Interrupts Initialize BIO S Interrupts 44 2 7 5 1 5 2 7 POST Device Initialization Check ROM Copyright Notice 2 1 Initialize Manager for PCI O ption RO Ms 2 7 7 0 Check Video Config Against CMOS 21 54 Initialize Manager for PCI O ption ROMs 1 2 7 7 0 nitialize all Video Adapters 7 0 Display Quiet Boot Screen c ba 5 5 7 0 Shadow Video BIOS 7 0 Display BIO S Copyright Notice 7 0 Display CPU Type amp Speed 51 52 54 56 58 1417 T 2118 2178 51 54 gt 80 BIOS POST Code Listings 59 5154 5 24 51 Display Press F2 To Enter Setup 5B 2227 5C 1 1 1 5 5 5 2 22 27 22 27 5 5 3178 5 2 2 Display High Address for UMB Recovery Display Error Message N Check for Configuration Errors Test Real Time Clock Test for Key Lock On 24 54 Set Up Hardware Interrupt V ectors 2 3 2 6 Initialize Co Processor if present Detect amp Install External RS232 Ports Configure Non MDC ID
13. POST Probe PCI TECHNICAL MANUAL by A COPYRIGHT O 2005 MICRO 2000 INC ALL RIGHTS RESERVED PRINTED IN USA MICRO 2000 INC 1100 E BROADWAY 375 FLOOR GLENDALE CALIFORNIA 91205 TELEPHONE 818 547 0125 FAX 818 547 0397 www Micro2000 com DOCUMENT VPCI 10 19 2005 TABLE OF CONTENTS INTRODUCTION mariana 7 About a ad d 7 About Post 7 Post Probe Features cnica ana 8 CHAPTER Donna 1 Using The POSTED nai 11 Installing Dear 11 What do all those lights mean eterne 12 o 12 Reset 12 ISA 13 sanana dnd 14 14 Stepping debt b Do Gv DO aba 14 A upon HR ROS ERR 15 The Hex Display aaa 16 More Post Code ReSOUrCES ssssssssesssssssesssssssssssssssesssessessssstsssessssssseessessssessn 167 CHAPTER Ainsa 18 Diagnostic PTOCBCIBS Locas idee 18 18 18 2 0 Motherboard cai 19 Zu Systemi BUS 19 2 2 CPU Central Processing Unit eee 20 2 3 NPU Numerical Processing Unit see 20 2A TD SA T 21 System CIO amer 21 20CMOS
14. ADDRESS 23 GROUND ADDRESS 21 ADDRESS 19 3 3 VDC ADDRESS 17 C BE 2 GROUND INITIATOR READY 3 3 VDC DEVICE SELECT GROUND LOCK PARITY ERROR 3 3 VDC SYSTEM ERROR 3 3 VDC C BE 1 ADDRESS 14 GROUND ADDRESS 12 ADDRESS 10 GROUND ADDRSS 8 ADDRESS 7 3 3 VDC ADDRESS 5 ADDRSS 3 GROUND ADDRSS 1 3 3 VDC ACK 64 BIT 5 VDC 5VDC Appendix A TEST RESET 12 VDC TEST MODE SELECT TEST DATA INPUT 5 VDC INTERRUPT A INTERRUPT C 5 VDC RESERVED 3 3 VDC RESERVED ACCESS KEY ACCESS KEY RESERVED RESET 3 3 VDC GRANT GROUND RESERVED ADDRESS 30 3 3 VDC ADDRESS 28 ADDRESS 26 GROUND ADDRESS 24 INIT DEVICE SELECT 3 3 VDC ADDRESS 22 ADRESS 20 GROUND ADDRESS 18 ADDRESS 16 3 3 VDC CYCLE FRAME GROUND TARGET READY GROUND 5 3 3 SNOOP DONE SNOOP BACKOFF GROUND PAR ADDRESS 15 3 3 VDC ADDRESS 13 ADDRESS 11 GROUND ADDRESS 9 C BE 0 3 3 VDC ADDRESS 6 ADDRESS 4 GROUND ADDRESS 2 ADDRESS 0 3 3 VDC REQUEST 64 BIT 5 VDC 5 VDC SNA 239 Appendix Standard Hardware Interrupts FUNCTION 2222 2 21 0 5 5 6 FLOPPY CONTROLLER PARALLEL PORT LPT1 REAL TIME CLOCK Available appears as IRQ 2 10 Available 11 SCSI 12 ONBOARD MOUSE PORTE 13 MATHCOPROCESSOR PRIMARY 5 SECONDARY IDE Available if not used for standard function 1 240 Appendix Memory All
15. Alternate Display memory R W test passed To look for the alternate display retrace checking Video display checking over D isplay mode set next Display mode set G oing to display power on message Different buses init input IPL general devices to start if present Display different buses initialization error messages New cursor position read and saved To display the Hit lt DEL gt message N gt Eri Data initialized oing to check for memory wrap around at 0 0 and finding the total system test memory Memory wrap around test done Memory size calculation over About to go for writing patterns to test memory E 152 BIOS POST Code Listings Intel D820LP Runtime Continued Pattern to be tested written in extended memory G oing to write patterns in base 640K B memory 48 Patterns written in base memory oing to find out amount of memory below 1M memory 9 Amount of memory below 1M found and verified Going to find out amount of memory above 1M 4B Amount of memory above 1M found and verified Check for soft reset and going to clear memory below 1M for soft reset If power on go to check point 4E 4 Memory below 1M cleared SOFT RESET Going to clear memory above 1M AD Memory above cleared SO FT RESET Going to save the memory size Go to check point 52 display the first 64K B memory size Memory size display started This will be updated during Memory test started NOT S
16. Initialize PCI Bus and Devices Video Initialization Shadow Video BIOS ROM Display Copyright Notice Display CPU Type And Speed 219 Chapter 4 Phoenix 4 0 Continued Beep Code 2 2 1 3 2 2 2 1 2 2 23 2 2 31 2 2 33 2 2 4 1 2 3 1 1 2 3 1 3 2 3 2 1 2 3 23 2 3 31 2 3 3 3 2 3 4 1 2 3 4 3 2 4 1 1 2 4 1 3 2 4 2 1 2 4 2 3 2 4 4 1 2 4 4 3 3 1 1 1 3 1 1 3 3 1 21 3 1 2 3 3 1 3 1 3 1 3 3 3 1 41 3 2 1 1 3 2 1 2 3 2 1 3 3 2 2 1 3 2 2 3 3 2 3 1 220 Failure Keyboard Test Set Key Click Keyboard Enable Unexpected Interrupts T est Display Press F2 To Enter SETUP 512k to 640k RAM Test Expanded Memory Test Extended Memory Address Lines Test User Batch 1 Configure Advanced Cache Registers Extemal CPU Cache Enable Display External Cache Size Display Shadow Message Display Non D isposable Segments Display Error Messages Check for Configuration Errors Real Time Clock Test Check for Keyboard Errors Set Up Hardware Interrupt Vectors NPU Test Disable Onboard I O Ports Detect Install External RS232 Ports Detect Install External Parallel Ports Re Initialize Onboard Ports BIOS Data Area Initialization Extended BIOS Data Area Init Floppy Controller Initialization Hard Disk Controller Initialization Local Bus HD Controller Init User Batch 2 Disable A20 Address Line Clear 4 GB ES Segment Register Search for Option RO Ms BIOS Beep Codes Phoenix 4 0 Continued Beep Code Failure 3 2 33 Sha
17. Probe monitors the voltages bus signals and the computer s Post or Power O n Self Test and shows the results with various LED and 7 segment displays A computer when powering up will go through a series of steps in the BIOS to test the computer s subsystems As it does each step it generates a code for that step called a POST code The code varies according to the manufacturer and version of the BIOS Post Probe reads these codes and if the BIOS fails to get all the way through the tests the code displayed will show where the Power O n Self Test halted There is also a button that allows you to step through the codes one at a time The LED display the code tables for your type of BIOS in Chapter 3 of this manual and the diagnostic procedures in Chapter 2 will allow you to diagnose the failure in many cases to the exact component that 7 Introduction needs to be replaced Together with Micro 2000 s Micro Scope diagnostic software you will have the arsenal to conquer virtually any PC computer problem you may encounter Post Probe Features PCICONNECTOR T SEGMENT DISPLAY OSC LED RESET LED ALE LED STEPPING SWITCH VOLTAGE TEST POINTS 33VDC 5VDC 10 5 VDC 1 3 4 5 6 7 8 9 H2VDC 122VDC CLK LED FRAME SMEMR LED IRDY SMEMW LED TRDY IOW LED DEVSEL IOR LED DIP SWITCH ISACONNECTOR Introduction laa
18. uH Copy main BIO S image to F000 shadow RAM and give control to main BIOS in F000 shadow RAM 123 3 Intel D810E MO Continued Copying of code to specific area done Going to give control to Int19 boot loader Intel D810EMO Boot Block Recovery Code Description Onboard diskette controller if any is initialized Compressed recovery code is uncompressed at F000 0000 in shadow RAM Give control to recovery code at F000 in shadow RAM Initialize interrupt vector tables system timer DMA controller and interrupt controller E8 Initialize extra Intel recovery module Initialize diskette drive EA Try to boot from diskette If reading of boot sector is successful give control to boot sector code EB Boot from diskette failed look for ATAPI 15120 Zip devices EC Try to boot from ATAPI device If reading of boot sector is successful give control to boot sector code EF Boot from diskette and ATAPI device failed G ive two beeps Retry the booting procedure go to checkpoint E9 Intel 0810 Runtime Code U noompressed in F000 Shadow RA M Post Code Description NMI is disabled To check soft reset power on BIOS stack set Going to disable cache if any 06 POST code to be uncompressed CPU init and CPU data area init to be done 08 CMOS checksum calculation to be done next Any initialization before keyboard BAT done next 124 BIOS POST Code Listings Intel D810EMO Ru
19. 5 4 2 6 5 4 7 0 2 5 5 4 3 2 2 6 5 1 3 1 4 0 3 1 4 0 2 6 2 6 2 6 2 6 5 4 3b 72 BIOS POST Code Listings COMPAO General Continued 8 Save RESETWD Value 7 Check RAM Refresh 26 70 Vectorto Option RO Ms Initial 5 5 5 5 5 5 5 2 1 1 1 1 1 1 1 1 6 3 gt 0 0 1 2 1 1 7 T 7 7 7 7 7 26 76 26 51 73 7 7 5 5 5 CN 8 3 5 2 5 5 5 Protected Mode Error during test Display Error Message End of Memory Test N Initialize String D etermine Size to Test 5 2 5 5 Start MEMTEST ES 26 8 10 51 5 5 5 N 5 5 5 5 5 5 1 7 2 2 2 1 7 1 1 1 1 2 2 2 2 1 6 6 8 1 8 1 8 1 1 8 w co CE LAN LN 74 BIOS POST Code Listings COMPAO General Continued OK 8042 Init Mode 5D Start Test Reset Keyboard 2 2 2 9 5 5 5 5 Got Result Check it Start of Fixed Drive Tests Combo Board Not Found Exit 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 6 6 6 7 7 7 7 6 6 5 6 5 6 5 6 5 6 5 6 5 6 5 6 5 6 5 6 5 6 5 6 4 6 4 w LAM 99 5 LA End B1 75 3 e e gt 6 4 6 4 6 4 4 4 4 1 4 1 4 1 1 1 3 1 2 1 2 1 2 5 5 4 4 6 6 2 9 9 9
20. 55 5 5 26 50 5 5 3055 22 52 2 0 0 0 0 0 0 2 2 2 7 0 0 0 0 0 0 0 0 0 0 2 2 w 43 3 AMI Ez Flex BIOS Continued BIOS Data Area Re Checked BIOS Data Area Check Complete 26 50 1 5 5 7 5 7 5 5 wo 5 5 0 di 4 7 7 w ejN 1 0 7 0 Display Power O n Message Check Mouse and Display Wait Message Attempt to Shadow O ption RO Ms 28 65 28 64 64 Initialize Controller 1 3 4 3 2 6 2 6 2 4 2 6 6 1 LN LN LN EN EM EN Dd 44 BIOS POST Code Listings AMI Ez Flex BIOS Continued 2 7 4 0 Check BIO Data Table 2 7 4 0 BIOS Data Table Check Complete 2 6 5 0 Set Memory Size Verify Display Memory Clear All Interrupts 3 5 3 Clear Interrupts Extended K eyboard Check 1 Set Numlock on Keyboard Keyboard Reset 2 2 5 0 Test Cache Memory Size Display Any Soft Errors 3 2 3 5 D o Set Memory Wait States Clear Display 7 6 7 Set Typematic Rate 30 50 3 3 26 70 4 0 4 0 2 0 3 0 0 0 0 0 EM LN LN LN EN 00 D a 45 3 AMI Win BIOS Post Diag Code Sect Description 00 41 Control to nt 19 Boot Loar 0 DA OE OF i i D i iA 20 2 2i 5 26 7 28 BIOS POST Code Listings AMI Win B
21. BIO rra 168 Intel LB440GX LB440GX BIO S 174 Intel NA440BX N440BX BIOS 179 Intel 4 BIO 183 Intel RCMOBX BIOS Continued aaa 184 Intel RC440BX Boot Block Recovery eerte 184 Intel RC440BX Runtime Code 185 Phoenix BIOS Plus Version 10 iaa 190 Phoenix PCI BIOS encanta erit eR TAa cta a RARE 192 Phoenix PCI BIOS UMC 195 Phoenix ISA EISA MCA Version 3 07 198 Phoenix DIOS Version rara 200 Phoenix Version 4 Release 6 0 sra 204 For Boot Block in Flash RO Mini 209 Phoenix Medallion BIO cia 210 Westem Digital BIO S iia rana 210 CHAPTER EET 212 BIOS Beep CIS Os 212 zr LE A PP 212 AA is 213 IR 213 A A E NONAS 213 COMPA Os COM sia 214 214 Micr id Besestt Discos edd icd oho eter 215 MR BIOS L Low Tone H High Tone esee 215 E 216 Phoenix ISA EISA T MON tn S Ein 216 Phoen ote mr FOE NE MEE e om dd 218 O ate 222 CHAPTER 223 POST PIUOCGUUIBS auntiusnnienavnlins 223
22. BIOS POST Code Listings 81 Aboutto Disable B1 3 3 3 3 3 3 3 N 57 DMA Units 1 amp 2 programmed OK 0259 Ov 31 8259 Mask Register Chek OK 31 8259 Mask Register OK 32 _ Check Timer amp Keyboard 32 TimerintemptOK 711 32 About to test Keyboard 32 ERROR Timer Keyboard Intemupt 32 6250 Interrupt Controller Enor 32 8250 Controler Test OK Bi Sat of Keboad Test B1 Keto Ba Tet OK 51 8 1 1 1 1 2 2 8 1 8 1 7 1 2 7 7 7 7 vi 1 1 1 2 2 2 2 2 2 8 1 8 1 35 3 Verify CMOS Battery Power CMOS Battery Verification Done Analyze Test Results for Memory N About to Initialize Timer D ata Check Optional ROM C000 0 Keyboard Sensed to Enable Setup Optional ROM Control OK CMOS Memory Size Update O K Printer Global Data Init OK Calo 19 for bootloader AMI Color 5 1 5 1 7 3 81 6 3 6 2 2 3 40 40 ma Na gt 8 ej Alo 02 Post Diag Code Sect Description 00 Control to Int 19 Boot Loader CPU Test 02 Power On Delay Soft Hard Reset ROM Enable Chipset Initialization 36 BIOS POST Code Listings 26 w DN 37
23. D8MEPEA Runtime Continued Programming after setup complete Going to display power on screen message First screen message displayed lt WAIT gt message displayed PS 2 mouse check and extended BIOS data area allocation to be done Init of different buses optional RO Ms from 800 to start Going to do any init before C800 optional ROM control 97 Anyinit before C800 optional ROM control is over Optional ROM check and control will be done next Optional ROM control is done About to give control to do any required processing after optional RO M retums control and enable external cache Any initialization required after optional RO M test over Going to setup timer data area and printer base address Return after setting timer and printer base addresses oing to set the RS 232 base address Returned after RS 232 base address oing to do any initialization before coprocessor test Required initialization before coprocessor is over G oing to initialize the coprocessor test Coprocessor initialized oing to do any initialization after coprocessor test Initialization after coprocessor test is complete G oing to check extended keyboard keyboard ID and num lock Ol N Going to display any soft errors 3 Soft error display complete G oing to set keyboard typematic rate Keyboard typematic rate set To program memory wait states gt 148 BI
24. H AES dm MM i J 19 POST Probe Physical Layout Introduction Notice The Post Probe card is designed to be used for the short period of time that the computer is performing its Power On Self Test during boot up Leaving the card inserted into the computer for extended periods of time may cause the card to be damaged through overheating and will void the warranty for the Post Probe Chapter 1 Using The POST Probe Installing the Card Y ou will notice that the Post Probe card has two edge connectors One of these is for the ISA or EISA type bus and the other is for the newer PCI bus If your motherboard has slots for both types of bus you should use both The POST codes will be the same but the individual LEDs monitor different signals on each bus If only one bus is available it will be apparent which one to use If neither connector fits in the bus slot you have encountered a third type called the MCA bus MCA stands for Micro Channel Architecture which is a bus standard developed by IBM for their PS 1 and PS 2 systems The Post Probe can also be used in this type of bus by first plugging the ISA connector into an MCA adapter card which 15 available from Micro 2000 To install tum off the computer and open the case Although not required it is usually a good idea to begin by removing all of the adapter cards plugged into the motherboard s bus slots in order to narrow down th
25. Memory Memory refers to storage of information in a way that is readily accessible to other parts of the system This distinguishes it from disk drives CDROM etc These devices also store information but it must be loaded into system memory before it can be used The first megabyte of memory is called conventional memory and was the maximum memory size of the first PCs It is divided into base memory the first 640 kilobytes and the upper memory area between 640k and 1 megabyte abbreviated as UMA Everything above 1 megabyte is called extended memory In some older systems there may be a section of UMA referred to as EMS for Expanded Memory Specification 5 1 RAM Random Access Memory is found on narrow cards modules plugged into the motherboard The chips on theses modules are Dynamic RAM or DRAM chips meaning they must be periodically supplied power on a Refresh line in order to retain their data RAM contents are lost whenever the system power is turned off Each individual chip can store from 64K to 256M bits of data In one common configuration each chip will provide 1 bit of data at a time to the system and 8 chips on the module make up a byte If there is a 9th chip it provides the parity bit Some DRAM chips output 4 or 8 bits at a time and will therefore have only 1 or 2 chips per module plus parity In all cases the quantity and capacity of the chips used determines how many megabytes of memory are contained in th
26. Mode Protected mode allows modem operating systems to run in memory above 1 MB CPUs still have the option to run in Real Mode for backward compatibility and the POST will switch from one to the other this test fails the culprit is usually the CPU chip or the A 20 Line see 5 3 5 3 A 20Line Address lines A 0 through A 19 access the first megabyte of memory Address line A 20 is the first line allowing access to extended memory and must be enabled and disabled as the CPU switches between Real and Protected Mode Because the 286 CPU did not have circuitry to control this the IBM engineers routed A 20 through some unused pins on the 8042 Keyboard Controller chip and it can still be found there 25 Chapter 2 on many systems other systems this function will be found elsewhere on the motherboard Refer to the documentation to find exactly where A failure may be indicated as an A 20 test or as part of the Protected Mode tests 54 ROM Read Only Memory will be found on many adapter cards and on the mother board itself for the BIOS If a POST code just refers to ROM it almost always means adapter card ROM The POST will start at memory address C800 0000 and check in 2K increments for a value of 55AA hex which indicates a device is using that section of ROM The POST will then execute the initialization program for the device starting at the fourth byte of that section If the POST stops during the ROM test you must is
27. Scope Diagnostic software to find out which IRQs are already in use Jumpers on the card will allow you to change to a vacant IRQ and you can then re install the device The table in Appendix A shows the allocated and available IRQs 3 1 Programmable Intenupt Controller PIC The chips that control the interrupt traffic between the CPU and various hardware devices are called Programmable Interrupt Controllers or PICs Each PIC can control eight interrupt lines 22 Diagnostic Procedures designated IRQ 0 through IRQ 7 To achieve the 16 interrupt levels required by all PCs since the 286 the chips are cascaded by connecting the output of a second chip to the IRQ 2 input of the first chip The original 2 is routed to 9 on the second chip Any adapter card that is set to IRQ 2 is actually using IRQ 9 Some PO ST routines will tell you which of the two PIC chips or even which IRQ line is failing but others just indicate a PIC failure 3 2 PIT Programmable Interval Timer This chip controls the timing of CPU interrupt sequences and failure can show up in several places in any POST version On older systems 286 it was also involved in the basic system timing and could be a suspect in benchmarking errors 4 0 BIOS Basic Input Output System These are the hard coded instructions contained in ROM on the motherboard that the computer uses to get started The BIOS executes the POST routine that tests various componen
28. Wrong drive identified 7 Wrong media identified 8 No interrupt from FDC Chapter 3 9 Failed to detect Track 0 A Failed to detect index pulse Y gt 0 Higher Level Error 1 2 Read Sector Error side 0 or 1 3 4 Write Sector Error side 0 or 1 5 6 Format Sector Error side 0 or 1 7 8 Read ID Error Side 0 or 1 Z 1 No ID address mark 2 No data address mark Media is write protected 4 Sector wrong 5 Cylinder wrong 6 Bad cylinder 7 DMA overrun 8 ID CRC error 9 Data CRC error A End of cylinder B Unrecognizable error 51 IBM AT BIOS Post Diag Code Sect Description 92 BIOS POST Code Listings Address Lines 0 15 93 LN LN NN 3 34 3 Initialize Floppy D 41 1 2 1 6 2 2 j 2 2 j j 2 5 1 N C d gt 94 BIOS POST Code Listings IBM PS 2 MCA Post Diag Sect Description 22 CPUFFAA00SS Pattem Tet 12 CPURegsterTest ooo 31 Sjstem Port 94 Enable Chek _ 21 POST Registers Port 102 Enable Chek 21 Port 96 Enable Chek _ 26 Byte OF CMOS NMI Disable 17 CMOS Extended Ports 74 76 Test 57 DMA Test Pons 57 Initialize DMA Chips 51 Refresh Test 81 8042 Buffer Test Port 61 64 81 8042 Intemal Test Port 60 84 8042 Intemal Test 0002 81 8042 Enor ______ 51 se Me
29. control will be done next Optional ROM control is done About to give control to do any required processing after optional retums control and enable external cache Any initialization required after optional ROM test over Going to setup timer data area and printer base address ai 86 87 E 8D 144 3 Intel 815 Runtime Continued 9A Return after setting timer and printer base addresses oing to set the RS 232 base address Returned after RS 232 base address oing to do any initialization before coprocessor test Required initialization before coprocessor is over G oing to initialize the coprocessor test Coprocessor initialized G oing to do any initialization after coprocessor test Initialization after coprocessor test is complete oing to check extended keyboard keyboard ID and num lock N Going to display any soft errors Soft error display complete G oing to set keyboard typematic rate Keyboard typematic rate set To program memory wait states Going to enable parity NMI NMI and parity enabled G oing to do any initialization required before giving control to optional ROM at E000 Initialization before E000 ROM control over E000 ROM to get control next Retumed from E000 ROM control G oing to do any initialization required after E000 optional ROM control Initialization after E000 optional ROM control is over G oing to displ
30. devices etc The bus includes data lines address lines voltages and various other signal lines Those 19 Chapter 2 signal lines which are monitored directly by POST Probe described in the Troubleshooting section of Chapter 1 The bus could also be said to include the bus controller chip and the connectors into which the various adapter cards are plugged The most common bus for most of the PC s history has been the ISA for Industry Standard Architecture and its close cousins the EISA and VESA New systems being sold today nearly always include the faster PCI bus which may be used by itself or in combination with an ISA bus The signal layouts for these various types of buses are shown in Appendix B The USB Universal Serial Bus is external to the motherboard and is not tested during the Post procedure The bus controller chip determines the timing of data transfers controls whether it involves memory or I O and which way the transfer is going A failure of the chip can affect any of these factors The PCI and ISA bus will each have its own controller About the only other problem that occurs with the bus itself is a shorted or open signal line which can cause any number of symptoms depending on which signal is affected When bus defects show up in a system that was previously working the source will most often be found in the edge connectors Remove the adapter cards and inspect the connectors closely for bent pin
31. into DOSTick Timer C0 24 Early Chipset Initialization This and next four codes actually occur at the beginning of POST in order of CF C1 C3 and C5 Test CMOS Red Write Functions Boot Attempt Award 6 0 Quick POST These codes will appear if the Quick Boot option is set in CMOS This option does a shorter version of POST and is recommended for day to day operation but not if there are hardware problems Post Diag Code Sect Description 65 24 Initialize Onboard Devices and Keyboard 6 6 Controller Reset Chipset Registers 8 1 2 2 Check CPUID Initialize Cache and Interrupt 3 0 Vectors 5 0 6 8 0 67 2 Verify 5 and Battery Initialize Keyboard and i BIOS Data Area 66 74 Initialize Video Adapter Test Video RAM 69 30 Initialize 8259 Channel 1 Mask IRQ 9 Quick Memory Test 21 Detect CPU Speed Initialize O nboard Super I O 22 Display PnP Data and Vendor specific text Setup 6 1 Virus Protection 3 Award 6 0 Quick POST Continued GCGF Reeved _ O 1 0 Initialize Mouse and ACPI Subsystem Install 3 0 nterrupt Vectors Display Setup Message Initialize Cache Controller Initialize Floppy Controller and D rives I nitialize N PU Display POST Errors Check Password Write CMOS Values to RAM Enable Parity Initialize O ption ROMs Boot Partition Head Cylinder Values to RAM Final Initialization Set NumLock Status and System Spe
32. is why we ve included a button to allow you to step through the POST see Stepper Switch in Chapter 1 However using the POST code description Appendix A and the information in this chapter and sometimes a little trial and error will nearly always allow you to determine the source of the problem 1 0 Power Supply Power supply voltages are monitored on the system BUS by the POST Probe The voltages supplied are 5V 12V 5V and 12V On machines with a PCI BUS 3 3V 15 also provided on that BUS The LEDs on the POST Probe corresponding to each voltage will light if that voltage is within 10 of its proper value The voltages can also be tested with a voltmeter on the POST Probe measuring between the test point for the voltage you wish to check and the one marked ground 18 Diagnostic Procedures If all of the voltages are 0 the problem is the power supply the main fuse or the supply of 110VAC to the computer check the cord to make sure it s plugged in If one or two of the voltages are bad the cause could be a faulty supply or the voltage line on the bus is either open or shorted Power off and unplug all the adapter cards and I O devices from the motherboard Power up and retest the voltage If it s OK plug things back in one at a time power off when plugging or unplugging of course until the voltage fails That s your culprit If the voltage is still bad with everything unplugged disconnect the power supply from
33. itialize LPT Ports Initialize Math Coprocessor Award Version 3 3 Post Diag Code Description Keyboard Controller 2 On board LSI 2 70 Vido nization _ 79 Video Memory 56 8 1 4 2 24 2 7 3 2 5 1 4 0 7 0 7 0 BIOS POST Code Listings Award Version 3 3 Continued ER N N ER Memory V erifier 20 23 CPU Support Chips 19 1A 1B 1C 1D 1E 1F 4 5 6 7 8 9 A B 0 1 Protected Mode al 5 5 5 6 Shadow RAM Cache controller Floppy Drive Initialization 100 6 54 Award EISA Post Diag Code Sect Description 57 3 i 28 51 21654 26 54 26 54 26 54 26 54 26 54 26 54 26 54 2 4 3 2 8 1 2 2 6 5 1 5 6 2 6 8 1 7 0 7 4 5 7 5 7 5 7 3 2 3 1 3 1 3 1 3 1 3 1 2 7 6 LN LN w RM El 27 58 BIOS POST Code Listings 25 54 25 54 2654 2654 2654 2654 2654 2654 1 Memory Size 256K 1 Memory Test O ver 256K 26 62 25 26 Virus Protection Setup 41 59 5 5 2 7 2 6 5 6 5 4 6 5 6 4 6 2 2 3 2 6 2 0 4 3 2 6 2 4 54 5 5 6 8 1 1 LM LN 3 Award EISA Continued 5 NMI In Protected Disable NMI Chipset D efault Initialization 2 4 4 1 4 1 2 7 26 70 27 55 26 56 27 55 2 i Award PnP BIOS eo 5 N gt La Post Diag Code Sect
34. of INS gt END gt key during power on 12 To Init CMOS if Init CMOS in every boot is set or lt END gt key is pressed G oing to disable DMA and Interrupt controllers 1 Video display is disabled and port B is initialized Chipset init about to begin 8254 timer test about to start About to start memory refresh test A Memory refresh line is toggling Going to check 15 5 ON OFF time 23 To read 8042 input port and disable mega key PC feature Make BIOS code segment writeable To do any setup before Int vector init 25 Interrupt vector initialization to begin To clear password if necessary Any initialization before setting video mode to be done Going for monochrome mode and color mode setting 185 3 Intel RC440BX Runtime Continued 2 Different buses init system static output devices to start if present To give control for any setup required before optional video ROM check To look for optional video ROM and give control To give control to any processing after video ROM returns control f EGA VGA not found then do display memory W test Display memory R W test passed About to look for the retrace checking lee O N Eri I EGA VGA not found Display memory R W test about to begin Display memory R W test and retrace checking failed To do alternate D isplay memory R W test 2 Alternate Display memory R W test passed To look for the altern
35. points Post Code Description NMI is disabled Onboard keyboard controller and real time clock enabled if present Initialization code checksum verification starting Keyboard controller BAT test CPU ID saved and going to 4G B flat mode Initialize chipset start memory refresh amp determine mem size Verify base memory Initialization code to be copied to segment 0 and control to be transferred to segment 0 Control is in segment 0 Used to check if in recovery mode and to verify main BIOS checksum If in recovery mode or BIOS POST Code Listings to main BIOS Find main BIOS module in ROM image if main BIOS checksum is wrong go to checkpoint 0 for recovery Otherwise got o checkpoint D 7 to give control 108 Uncompress the main BIOS module main 5 image to F000 shadow RAM and give control to main BIOS in F000 shadow RAM Intel D815EEA Boot Block Recovery Code Description Onboard diskette controller if any is initialized Compressed recovery code is uncompressed at 000 0000 in shadow RAM Give control to recovery code at F000 in shadow RAM Initialize interrupt vector tables system timer DMA controller and interrupt controller Initialize extra Intel recovery module Initialize diskette drive EA Try to boot from diskette If reading of boot sector is successful give control to boot sector code Boot from diskette failed look for ATAPI LS 120 Zip devices Try to boot fr
36. port selection are given in the Chapter One section covering the DIP switch but more specific information is available for many BIOS versions and is listed below Not all BIOS Post procedures can be monitored by the POST Probe Some systems send POST codes to a printer port at 278h 378h or 3BCh These include some IBM PS2 models and others by Olivetti NCR and amp These ports cannot be detected by the PO ST Probe so no codes will be displayed for these systems There are also systems which do not put out codes at all This was true of the original IBM PC and certain BIO S versions from HP AMI and DTK However the most common practice is to use port 80h which is the default setting for the POST Probe Unless stated otherwise below you can probably assume that Port 80h is the right choice For BIOS versions that do not provide codes to the Post Probe that card s LED indicators can still provide much useful information about what is or is not happening during the POST AMI Uses Port 80h for all versions Award EISA systems use 300h Others use 80h Some versions of Award BIOS have Burn In feature that will repeat the PO ST over and over if a flag for this is set on the motherboard The tip off that this is happening is that the Reset light will blink every few seconds COMPAQ Most systems use Port 84H the rest use 380 Compaq is the only BIOS to use these ports 223 Chapter 5 HP Vectra The various Vec
37. present Put CGA Int10 module if present in shadow E Uncompress SMBIO 5 module and init SMBIOS code and form the runtime SMBIO S image in shadow Going to copy any code to specific area Copying of code to specific area done G oing to give control to Int19 boot loader Intel JN440BX BIOS Uncompressed IN IT Code C heck points Post Code Description 9 0090 SetIN POST Initialize processor registers 0B Enable processor cache Initialize caches to initial PO ST values Initialize I component 168 BIOS POST Code Listings 169 RAM failure on address line xxxx Reinitialize the chipset motherboard only 3 1 Conf nitialize multiprocessor A PIC Enable external and processor caches Setup System Management Mode SMM area N N CN LN 9 170 BIOS POST Code Listings Intel JN 440BX BIOS Continued Display external L2 cache size Display shadow area message gt mitai Reinitialize onboard 1 O ports Configure motherboard configurable devices Inital nitialize BIO S Data Area Initialize hard disk controllers Initialize local bus hard disk controllers Build MPTABLE for multiprocessor boards Disable A20 address line Install CD ROM for boot Clear huge ES segment register Enable non maskable interrupts NMI CN CE w De 171 3 Enter SETUP Eri Clean up all graphics Initialize D MI paramete
38. printer 0213XX SCSI processor 0214 WORM drive SCSI CD ROM drive 0217XX Optical memory Changer multi CD tray or juke box SCSI communications device 234 Chapter 7 The Legacy POST Probe For customers still using original pre PCI Post Probe cards this chapter explains the differences and unique features of the card While the old cards do not monitor the PCI bus they are still functional and powerful tools in a troubleshooting arsenal The Post codes displayed are exactly the same ones listed in this manual and the voltages and other signals monitored on the ISA bus are also the same except that the Memory Read and Memory Write are indicated by the same LED On the other hand the Osc and Clk signals have two LEDs each which light alternately The 3 3V is missing of course since that only occurs on the PCI bus The card works in both ISA and EISA and can also monitor the IBM Micro channel machines by using the same MCA adapter as the new card available from Micro 2000 The Probe One feature unique to the old card is a tri state logic probe which is the source of the probe in the name Post Probe This probe is used to sample the signal outputs on the pins of any CMOS or TTL logic chips The probe feature was discontinued in the new version primarily because of the trend to large scale integration where more and more circuitry is combined into fewer and fewer chips As this trend
39. start memory refresh test Memory refresh line is toggling Going to check 15 ys On OFF time 3 To read 8042 input port and disable mega key reen PC feature Make BIOS cade segment writeable To do any setup before int vector init Interrupt vector initialization to begin To clear password if necessary Any initialization before setting video mode to be done Going for monochrome mode and color mode setting Different buses init system static output devices to start if present 0 give control for any setup required before optional ROM o look for optional video and give control o give control to do any processing after video RO returns control f EGA VGA not found then do display memory R W GA VGA not found Display memory R W test about to egin isplay memory R W test passed About to look for the retrace checking alternate Display memory R W test alternate display retrace checking 7 Display mode set Going to display power on message 8 Different buses init input IPL general devices to start if present 9 Display different buses initialization error messages N es 3g J A New cursor position read and saved To display the Hit lt DEL gt message EN E 145 3 Data initialized Going to check for memory wrap around at 0 0 and finding the total system test memory Memory wrap around test done Memory size ca
40. the motherboard and check the voltages on the power supply connector If everything checks OK the problem is on the motherboard If not it s the power supply 2 0 Motherboard The motherboard holds the central processing unit CPU with its associated timing and control circuitry and the system BUS Also found here are the jumpers that set the system speed and sometimes other variables On the most basic motherboard everything else connects to the motherboard either through adapter cards which plug into the BUS or into a special connector on the motherboard Check the jumpers to make sure they are seated properly and the settings are correct The board itself is seldom a source of failure which usually occurs in the on board circuitry or in one of the devices attached to the motherboard If the problem can be isolated to a particular component it may be possible to replace that component However on modern motherboards the trend has been to combine more and more functions into largescale integrated chips For instance one 82206 chip now combines the two DMA controllers the PITs the PICs and the RTC whereas in older systems these were all separate chips Many of these large scale chips are surface mounted with special and expensive equipment and the only practical option is sometimes to replace the entire board 2 1 System BUS The bus is the pathway on the motherboard over which information travels between the CPU memory O
41. used by the manufacturer to test the chips but are not used during normal POST 30 Chapter 3 BIOS POST Code Listings AMI 2 2 BIOS Post Diag Code Sect Description 03 Register Test Chipset Test BIO S Checksum 0 Page Register OF 8254 Timer 12 Memory Refresh 15 DMA Controllers 18 8237 DMA Initialization 1B 8259 Initialization 1E PIC Chips 21 Memory Refresh 1st Bank 24 Base 64 Address test 27 Base 64 Memory test 2 8742 Keyboard Chip 2D MC146818 RTC CMOS 30 Protected Mode 33 Size Memory 36 Protected Mode 39 Protected Mode Failed 3 CPU Speed Calculation 3F 180 Read 8742 Hardware Switches 31 3 AMI 2 2 BIOS Continued 15 Veny CMOS Configuration 70 Tes amp nilo Video Spin 52 Sart nd Protected Mode Tet N N 81 VerifyLTD Instruction 81 Verify TR Instruction 7 8 8 1 Verify LSL Instruction 81 Verify LAR Instruction 8 1 Verify VERR Instruction 8 Address Line 20 Test 8 1 81 ____ Unexpected Exception Test 52 al N 1 0 1 1 1 1 Start 3rd Protected Mode Test 5 1 5 7 Address Line Test 5 1 System Memory Test xl 2 1 2 3 Eu 55 Shadow MemoryTest 6 Verify Memory Configuration 26 Display Error Messages NIN 80 B0 Detemine Keyboard Type 80 N 23 Math Coprocessor Determi
42. 0BX Boot Block Recovery Code Description Onboard Floppy Controller if any is initialized Compressed recovery code is uncompressed in F000 0000 in Shadow RAM and give control to recovery code in F000 Shadow RAM Initialize interrupt vector tables initialize system timer initialize D MA controller interrupt controller Initialize extra Intel Recovery Module Initialize floppy drive EA Try to boot from floppy If reading of boot sector is successful give control to boot sector code Booting from floppy failed look for ATAPI LS120 Zip devices EC Try to boot from ATAPI If reading of boot sector is successful give control to boot sector code beeps Retry the booting procedure again go to check point E9 Booting from floppy and ATAPI device failed Give two 184 BIOS POST Code Listings Intel RC440BX Runtime Code U noompressed in F000 Shadow RA M Post Code Description N MI is disabled The check soft reset power on BIOS stack set Going to disable cache if any 06 POST code to be uncompressed CPU Init and CPU data area Init to be done 08 CMOS checksum calculation to be done next Any initialization before keyboard BAT to be done 0C KB controller I B free To issue the BAT command to keyboard controller Any initialization after K B controller BAT to be done next Keyboard command byte to be written Going to issue Pin 23 24 blocking unblocking command 11 Going to check pressing
43. 12 9 Y gt 0 Bad 042 Z gt 0 Bad 032 5 1 Lower 640K Failed Marching Ones Test Same parameters as 4X Y 2 61XY 51 RAM Address Line XY Stuck 87 c lt N 3 HP Vectra ES Continued 620 63X Dd 5 E 7400 7500 9 7 001 740 EMI 1 5 1 1 3 1 1 3 1 3 1 e 2 3 un Lower 640K Parity Error Bank X Parity Error Above 1MB Bank X Y Parity Generator Failed To D etect Error Master 8259 Failed R W bits XY Slave 8259 Failed R W Bits XY aster 8259 Failed Interrupt lave 9259 Failed Interrupt Floppy Controller Error X Drive 0 1st Level Error 2 0 Unsuccessful Input from FD 1 Unsuccessful output to FDC 2 Error while executing seek 3 Error during recalibrate 4 Error verifying RAM buffer 5 Error while resetting FD C 6 Wrong drive identified 7 Wrong media identified 8 No interrupt from FDC 9 Failed to detect Track 0 A Failed to detect index pulse Y gt 0 Higher Level Error 1 2 Read Sector Error side 0 or 1 3 4 Write Sector Error side 0 or 1 5 6 Format Sector Error side 0 or 1 7 8 Read ID Error Side 0 or 1 Z 1 No ID address mark 2 No data address mark Media is write protected 4 Sector wrong 5 Cylinder wrong 6 Bad cylinder 7 DMA overrun 8 ID CRC error 9 DataCRC error A End of cylinder B Unrecognizable error No 80287 D etected BIOS POST Code Listings HP Vectra ES Contin
44. 4KB RAM Failure Bit 0 First 64K B RAM Failure Bit 1 12 First 64KB RAM Failure Bit 2 First G4K B RAM Failure Bit 14 First 64K B RAM Failure Bit 4 5 0 First 64KB RAM Failure Bit 5 16 First 64KB RAM Failure Bit 6 First 64K B RAM Failure Bit 7 18 First 64KB RAM Failure Bit 8 First 64K B RAM Failure Bit 9 190 BIOS POST Code Listings Phoenix BIOS Plus Version 1 0 Continued First 64K RAM Failure Bit First 64K B RAM Failure Bit C 26 52 191 5 0 5 0 5 0 5 0 5 0 5 7 5 7 3 1 3 1 3 0 8 1 2 6 2 6 7 4 7 0 7 0 7 3 7 3 7 1 7 2 7 2 3 2 5 3 3 0 5 2 5 0 3 2 2 5 6 2 3C Bo 3 Phoenix BIOS Plus Version 1 0 Continued Parallel Port Test 2 3 0 System Board Select Bad 7 Extended 5 Error Phoenix PCI BIOS 2 Post Diag Code Sect Description 4 10 14 Verify 8742 Keyboard Controller Initialize External Cache 30 32 M 25728 3634 50 Auto Size Exem Cache ic 02 04 0A 0C 0E 16 18 1A 1C 20 22 24 26 2A 2C 2B 4 Verify BIOS ROM Checksum 24 27 _ 24 50 42 32 57 1 50 Test DRAM Refresh 0 0 22 53 50 50 50 22 _ 25 26 2 2 2 5 8 3 5 3 5 8 2 5 5 5 5 2 5 4 7 4 1 0 j 1 2 2 7 1 0 1 2 3 0 0 0 2 0 0 j BIOS POST Code Listings 40 42 44 46 8 2 6 3 0 3 0 42 Check Cop
45. 5 ho B6 BD Do Do DELL BIOS Post Diag Code Sect Description CPU Register Test 76 BIOS POST Code Listings 0D 51 Pariy Bad First AKRAM Bit 0 First 64K RAM Bad 11 Bit 1 First 64K RAM Bad Bit 2 First 64K RAM Bad 13 5 1 Bit 3 First 64K RAM Bad Bit 4 First 64K RAM Bad 15 Bit 5 First 64K RAM Bad Bit 6 First 64K RAM Bad 17 Bit 7 First 64K RAM Bad Bit 8 First 64K RAM Bad 19 5 1 Bit 9 First 64K RAM Bad Bit 10 First 64K RAM Bad 1B Bit 11 First 64K RAM Bad Bit 12 First 64K RAM Bad 1D Bit 13 First 64K RAM Bad Bit 14 First 64K RAM Bad 51 Bit 15 First 64K RAM Bad 77 o e ejo 3 81 Keyboard ContolerTet 26 CMOS Power And Checksum 25 CMOSVdWdin 70 Sereen Initiation Bal 70 SmeR meTethal 13 SmwFoVieoROM 73 SmmVieROM 70 Sereen Ruming Wim ROM 71 Monochrome Monitor Opere 81 2 6 2 6 7 0 7 0 7 3 7 3 7 0 7 0 7 1 7 2 Color 40 Column perable 7 2 Color 80 Column O perable HP Pavillion Series 3100 8 8000 PCs 9 Post Diag Code Sect Description Verify Real Mode 78 BIOS POST Code Listings E oi 24 22 24 Initialize CPU Registers 4 Enable CPU Cache 58 21 24 T 22 51 Restore CPU Ctrl Word During Warm Boot 24 Initialize PCI BUS Mastering D evices B1 12 56 3 1 2 2 24
46. 5 VDC 12 VDC and 12 VDC If a voltage is within a tolerance of 10 to 5 the corresponding LED will be lit There are also six test points one for ground and one for each voltage that allow easy confirmation with a voltmeter Note Theeisno 3 3 V DC ontheISA bus ThePCI bus does not have 5 V DC and some PCI models also are missing the 3 3 V If an LED should be lit and is not the problem could be the power supply the cabling from the power supply or that the voltage line on the bus is being shorted out If none of the LEDs light up check the power supply the main fuse and the AC into the system Reset Line There is one red LED on the board located between two yellow LEDs about 1 inches from the edge opposite the ISA connector This LED will light anytime the system s Reset line is activated This normally happens only once during bootup but you will sometimes see the Post procedure get to a certain point and then reset over and over This usually means a shorted signal on the motherboard 12 Using The POST Probe ISA Signals There are seven yellow LEDs that monitor various signals on the bus With one exception they will monitor one function on the ISA bus and a different function on the PCI bus The ISA functions are listed here first ALE Address Latch Enable This yellow LED next to the Reset LED indicates a signal from the CPU that allows the BIOS to latch addresses such as memory addresses
47. 8 1 Write Command Byte Init Circular Buffer 8 3 Lock K ey Check 2 6 Compare Memory Size with CMO S 2 6 2 6 2 6 2 6 7 0 A 6 4 6 5 6 4 6 j LN LN EM EN 48 BIOS POST Code Listings 54 Optional 2 8 8 5 7 N 13 inicio After NPU Check Extended KB KB ID and Num Tok _ 1 isu Keyboard i Command ECTS 56 Cache Memoy Te 70 Display ay oies i Control to E000 ROM Init Needed After Control to E000 ROM 5 1 1 Copy any Code to 17 ROM Disable Cahe 2 CMOS Shutdown Register Test CMOS Checksum 2 N N 2 5 2 6 Initialize CMOS D ate and Time CB 124 Initialization Before Keyboard Batch 49 1 1 4 4 2 4 4 1 1 2 6 81 Reset Keyboard ID Flag 6 0 A A A 2 6 4 Eu EM EM Bo 3 AMI Win BIOS Continued BAT Command to Keyboard Controller Installation After KB Controller Batch AMI Win Boot Block Recovery Note These codes should only appear if malfunction oours while updating the BIOS flash ROM Post Code Description BIOS POST Code Listings AMI Win Boot Block Recovery Continued Programming D one Restart BIOS AMI BIOS 8 Post Diag Code Sect Description 4i Control to Int 19 Boot Loader 26 VeiyCMOSChdsum 31 PIC and Int Vetor Table 32 initialize Stem Timer 22
48. 9 DA Post Code Description Initialize Floppy DMA and PIC 53 3 Recovery File Not Found Analyze FAT to Locate Recovery File Clusters Award BIOS original XT Read Recovery File Cluster by Cluster Post Diag Code Sect Description 6 2225 CPU RegsterTest Timer Initialization 54 BIOS POST Code Listings 51 TetBaeGik of RAM 31 Semp Init and Temp Sak 31 1 320 Interrupt Mask Register Test 3 1 3 2 Hot Interrupt Test 24 System 5 1 3 1 3 2 24 8 1 2 0 j 7 0 Video Test 6 2 Serial Port D etermination 6 3 Game Port D etermination Copyright Message D isplay 2 5 5 1 65 1 Calculation of CPU Speed 51 Testof System Memory CL 164 65 20 70 62 683 Parallel Port Determination 60 70 N Floppy Drive Test 6 4 6 5 System Initialized Before Boot Call to Int 19 Award XT Version 3 1 cw olmo Sl SB Ol Sl 2 gt Post Diag Code Description 6 24 Initialize 6845 3 5950 7 0 09 70 Initialize the Video 55 3 Award XT Version 3 1 Continued Test First 64K Memory Bank Set Up Interrupt Tables Initialize CO M Ports
49. CC S20 Runtime COGO intacta 106 Intel SE440BX 2 BIO Sora 111 Intel D 810E2CB BIO S s eua orate dro ERE RR 116 Intel D 810E2CB Boot Block Recovery eee 117 Intel D810E2CB Runtime 118 Intel D 810EMO BIO Socia idad 123 Intel D810EMO Boot Block Recovery eere 124 Intel D810EMO Runtime Code eene ttes 124 Intel DBIBBN BIOS a oiv tic eR VERRE 130 Intel D815BN Boot Block Recovery eee 130 Intel D815BN Boot Block Recovery 131 Intel D815BN Runtime Code 131 Intel D815EEA BIO Sos rta dias 136 Intel 815 Boot Block Recovery eee 137 Intel 815 Runtime iaa 137 Intel D 815EPEA BIO naa naaa 143 Intel D815EPEA Boot Block Recovery eee 143 Intel D815EPEA Runtime Code 144 Intel D 820LP BIO 149 4 Table of Contents Intel D 820LP Boot Block Recovery eene 150 Intel SE440BX BIO CO HERREN ER ue 156 Intel SRMOBX etta d repaid 161 Intel SRA40BX Boot Block Recovery seen 162 Intel SRA40BX Boot Block Recovery 163 Intel SR440BX Runtime 202121 02 00 163 Intel IN ABE
50. Description 40 51 TES 26 51 m 24 51 57 2 6 24 2 2 5 7 LN DN 60 BIOS POST Code Listings EN pouce pre 31 54 ramsan 51 Get Sze of Base and Extended 54 Bose and Extended Memory 5 3 3 3 3 5 5 5 8 81 Install PS2 Mouse 2 4 5 6 Try To Tum On Level 2 A Initialize Floppy Controller 6 2 6 3 Initialize Serial amp Parallel Ports N 164 Initialize Hard Drive Controller 51 Se Up Vins Protection B1 Program Num Lock amp Typemalic Speed Unclaimed NMI occured Init all Standard D evices with D efaults Ea 2 6 4 0 Set Flag to allow 5 Setup Utility m Show all Error Messages On Screen Ask For Password if needed 2 6 5 1 Write all CMOS Values currently In BIOS Initialize Math Coprocessor Initialize all ISA ROMs 7 2 1 1 1 4 1 1 1 6 6 1 4 CM 61 3 Award PnP BIOS Continued 5 1 5 6 Auto detect On Board DRAM amp Cache Test First 26K DRAM 40 51 Copy ROM BIOS to E000 FFFF System Booting Award Elite Version 4 51 PG Post Diag Code Description 5 51 SiUplowMemy 09 2258 Baty Cache Inaization 216 Tet CMOSRAM Checksum 70 initialize Video mete 62 BIOS POST Code List
51. E Controllers D etect amp install External Parallel Ports 24 55 20 27 51 81 1 1 27 81 Check for Keyboard Errors 1 1 7 6 7 7 5 8 3 6 Disable On Board Super Ports 5 4 Late POST Device Initialization 6 2 6 4 6 3 6 59 58 EN Lu 62 CE 6 Lu 69 __ Lu 6 1 Lu m 6 pes I E 80 s 82 Lu s 8 8 8 8 3 Determine number of Drives Initialize Hard Disk Controllers nitialize Local BUS HD Controllers 27 impoten Build MPTABLE For Multi processor Boards 2 5 6 5 2 2 6 2 8 7 8 N Search for Option RO Ms Check for Smart Drive Shadow Option Enable Hardware Interrupts D etermine Number of ATA amp SCSI Drives Set Time of Day 24 94 64 55 24 ___ Set Up Power Management 724 64 25 83 9 9 9 9 9 9 9 9 9 70 8 8B 8C 1 2 3 4 5 7 0 2 4 8 2 B4 B5 1 1 2 5 4 4 4 i 4 4 4 5 4 4 4 6 i 0 1 6 6 6 0 A 82 BIOS POST Code Listings 2227 Clear Global Descriptor Table 70 24 nitialize D MI Parameters 2 4 nitialize PnP O ption ROMs 2 6 lear Parity Checkers 2 7 Display Mullet Boot Menu 7 0 Clear Screen O ptional 2 7 Check Virus amp Back Up Reminders 4 1 ry to Boot with Int 19 2 4 nitial
52. IOS Continued Initialize BUS Sys Static Output D ev Setup before O perational Video Check 173 Control to Optional Video ROM 2 NJN w 23 Proc after Optional Video ROM Routine 23 Display Mem Test No RmaeChd 71 XE 7 7 7 7 5 1 7 0 Display Alternate Memory W Test N 3 Virtual Mode Memory Test 2 2 24 Prepare D escriptor Tables Enter Virtual Mode for Memory Test 0 0 0 0 2 7 3 1 Enable Interrupts for Diagnostic Mode Initialize D ata to Check Mem Wrap At 0 0 5 1 5 2 Check Wrap Find Total 1 1 1 1 1 1 5 1 51 47 51 Memory Write Test 640K Base Memory Write Test Determine Memory Above 1 MB 2 6 8 1 Check for Soft Reset clear Mem below 1 MB 3 51 Above IMB Memory Tet 52 Disble GateA20Lme 57 Adjust Message 57 DMAfiBaeRgsmTs 57 DMAfiBaeReirTet N c 31 _ 8259 Controler KebadTe 1 Enable Extended NMI Soues 8 1 Stuck K ey and Batch Test K eyboard Controller Test aa Pe 1 26 Password Soft Error Chek 26 Programming Before Senp 26 Exemite CMOS Sep 26 Programming ARer sep 64 Reset Hard Disk Conroe 65 5 1 5 7 8 1 5 7 5 7 3 1 8 1 8 1 8 1
53. Initialization Initialize POST Memory Manager Clear 512k Base RAM 205 3 Phoenix Version 4 Release 6 0 Continued 70 70 70 81 81 90 0 1 7 0 6 5 7 0 1 7 0 1 1 8 1 i 1 70 Di 81 Display Error Messages 2 Check for Configuration Errors 400 Check for Keyboard Errors LN LN LN LN 206 BIOS POST Code Listings Phoenix Version 4 Release 6 0 Continued 3 1 5 4 Set Up Hardware Interrupt Vectors Initialize NPU if present ine Late POST D evice Initialization Configure non MCD IDE Controllers Disable Onboard Super I O Ports amp IRQs D etect Install External Parallel Ports D etect Install External RS232 Ports Floppy Controller Initialization 2 2 2 5 BIOS Data Area Initialization 3 Enable Non maskable Interrupts 5 Extended BIO S Data Area Init Hard Disk Controller Initialization Test amp Initialize PS2 Mouse 6 6 6 6 SI Rei dpeOnbewO Pu 6 Determine Number of ATA Drives optiona _ 5 6 23 61 60 62 64 63 21 61 20 Motherboard configurable Devices optiona 55 30 55 66 65 64 64 64 27 27 Jump o 7 65 Insta CD ROMforBoot Local Bus HD Controller Init 2 2 2 7 Fix up Multi processor Table 66 Chede for SMART Drive opion 207 3 1 2 4 3 1 1 0 29 0 5 4 4 4 4 9 4 7 4 w
54. Listings Intel CC820 BIOS Continued Control is in segment 0 To check recovery mode and verify main checksum If either it is recovery mode or main BIOS checksum is bad go to check point EO for recovery else go to check point D 7 for giving control to main BIOS Find main BIOS module in ROM image Uncompress the main BIOS module Copy main 5 image to F000 shadow RAM and give control to admin in 2000 shadow Intel CC820 Boot Block Recovery Code Description Onboard floppy controller if any is initialized Compressed recovery code is uncompressed in F000 0000 in shadow RAM and give control to recovery code in F000 shadow RAM Initialize interrupt vector tables initialize system timer initialize controller and interrupt controller Initialize extra Intel Recovery Module Initialize floppy drive Try to boot from floppy Booting from floppy failed look for ATAPI LS120 Zip devices successful give control to boot sector code Booting from floppy failed and ATAPI device failed Give two beeps Retry the booting procedure again go back to check point E9 Try to boot from ATAPI If reading boot sector is 105 3 Intel 820 Runtime Code U noompressed in F000 Shadow RA M Post Code Description 05 POST code to beunoompresal _ 08 CMOS checksum calculation to be done net LB Any aization before keyboard BAT to be done next 0 Keyboard contro
55. O S equipment list 000166 Adapter busy not returning a Ready signal 000115 80386 Protected Mode failure Check 8042 PIT PIC 000167 RTC PIT or Clock enerator 000169 Set Configuration Features 000171 I O adapter battery system board 90 95 Any device 90 95 Set Configuration Features 90 95 IBM Error Messages 000204 Relocated memory run diags again 000205 CMOS 000207 ROM BIOS failure 000210 CPU board 90 95 or memory riser 0021 027 00025 9026 0003 000302 User indicated error from keyboard test 000303 Keyboard or system board error 000304 System board error 900508 00058 0006XX Diskette drive cable or system board Diskette verify failed 227 000305 Keyboard 5V error 000306 System board Aux input 000307 Device L40SX 6 Index stuck high low 000653 4 Read write Read write ams Serial device cable 16550 register failure 228 IBM Error Messages 16550 FIFO error 229 6 Bisync adapter PC video memory 90 95 EGA adapter XT AT LCD display L40SX 0210 DU 002409 Display 002410 System board EST LOS PAY Ins Dn xmi om Alt PC network adapter 230 IBM Error Messages 004640 1 Multiport memory module 004650 Multiport interface cable 005001 L40SX board or LCD assembly 005017 005018 L40SX system board or LCD a
56. OFT RESET About to memory test G oing for sequential and random memory test 5 Memory testing initialization below 1MB complete oing to adjust displayed memory size for relocation shadow 1 Memory size display adjusted due to relocation shadow Memory test above 1MB to follow 2 Memory testing initialization above 1MB complete G oing to save memory size information 3 Memory size information is saved CPU registers are saved Going to enter real mode 54 Shutdown successful CPU in real mode G oing to disable gate A 20 line and disable parity NMI 57 A20 address line parity NMI disable successful A djust memory size depending on relocation shadow 8 Memory size adjusted for relocation shadow G oing to clear hit lt D EL gt message 59 Hit lt DEL gt message cleared lt WATT gt message displayed About to start D MA and interrupt controller test 3 Intel D820LP Runtime Continued D MA page register test passed To do DMA 1 base register test DMA 1 base register test passed To do DMA 2 base register test DMA 2 base register test passed To program DMA 1 and 2 DMA 1 and 2 programming over To initialize 8259 interrupt controller Extended NMI sources enabling is in progress Keyboard test started Clearing output buffer checking for stuck key to issue keyboard reset command Keyboard reset error stuck key found To issue keyboard controller interface test command Keybo
57. OS POST Code Listings Intel 815 Runtime Continued Going to enable parity NMI A7 NMI and parity enabled oing to do any initialization required before giving control to optional ROM at E000 A8 Initialization before E000 ROM control over E000 ROM to get control next A9 Returned from E000 ROM control Going to do any initialization required after E000 optional RO M control A Initialization after E000 optional ROM control is over Going to display the system configuration Put Int13 module runtime image to shadow Generate MP for multiprocessor support if present Put CGA Int10 module if present in shadow E Uncompress SMBIO 5 module and init SMBIOS code and form the runtime SMBIOS image in shadow Going to copy any code to specific area Copying of code to specific area done G oing to give control to Int19 boot loader Intel D820LP BIOS Uncompressed IN IT C ode C he points Post Code Description NMI is disabled Onboard keyboard controller and real time clock enabled if present Initialization code checksum verification starting D1 Keyboard controller BAT test CPU ID saved and going to 4G B flat mode memory size Verify base memory D5 Initialization to be copied to segment 0 and control to be transferred to segment 0 Initialize chipset start memory refresh and determine 149 3 Intel D820LP BIOS Continued Control is in segment 0 Used to check if in reco
58. Port Test 4 4 3 Math Coprocessor Phoenix 4 0 Beep Code Failure 1 1 1 3 Verify Real Mode 1 1 21 Get CPU Type 1 1 23 System Hardware Initialization 1 1 31 Init Chipset with Initial PO ST Values 1 1 3 2 Set Initial PO ST Values in POST Flag 1 1 3 3 CPU Register Initialization 1 1 4 1 Init Cache With Initial POST Values 1 1 43 I O Initialization 1 2 1 1 Power Management Initialization 218 BIOS Beep Codes Phoenix 4 0 Continued Beep Code 1 2 1 2 1 2 1 3 1 2 2 1 1 2 2 3 1 2 31 1 2 3 3 1 2 4 1 1 3 1 1 1 3 1 3 1 3 21 1 3 31 1 3 3 3 1 3 4 1 1 3 4 3 1 4 1 3 1 4 2 4 1 4 31 1 4 3 2 1 4 3 3 1 4 4 1 1 4 4 2 2 1 1 1 2 1 1 3 2 1 2 1 2 1 23 2 1 2 4 2 1 31 2 1 32 2 1 33 2 1 41 2 1 4 3 2 2 1 1 Failure Initial POST Values to Alt Registers User Batch 0 Keyboard Controller Initialization BIOS ROM Checksum 8254 Timer Initialization 8237 DMA Controller Initialization Reset PIC DRAM Refresh Test 8742 Keyboard Controller Test Set ES Segment to Register to 4 GB Auto size DRAM Clear 512k Base RAM 512k Base Address Lines Test 512k Base Memory Test CPU Bus Clock Frequency Test Reinitialize the Chipset Shadow System BIOS Reinitialize the Cache Auto size Cache Configure Advanced Chipset Registers CMOS Values to Alternate Registers Set Initial CPU Speed Interrupt Vectors Initialization BIOS Interrupts Initialization Check ROM Copyright Notice PCI Options RO Ms Initialization Check Video Config Against CMOS
59. SET About to display the first 64K B memory size Memory size display started This will be updated during memory test oing for sequential and random memory test Memory testing initialization below 1MB complete G oing to adjust displayed memory size for relocation shadow Memory size display adjusted due to relocation shadow Memory test above 1MB to follow Memory testing initialization above 1MB complete Going to save memory size information Memory size information is saved CPU registers are saved Going to enter real mode Shutdown successful CPU in real mode Going to disable gate A 20 line and disable parity NMI A20 address line parity NMI disable successful Adjust memory size depending on relocation shadow 165 3 Intel SR440BX Runtime Continued 58 Memory size adjusted for relocation shadow oing to clear hit lt DEL gt message 59 Hit lt DEL gt message cleared lt WAIT gt message displayed About to start D MA and interrupt controller test page register test passed To do DMA 1 base register test 62 DMA 1 base register test passed To do DMA 2 base register test 5 DMA 2 base register test passed To program DMA 1 and 2 DMA 1 and 2 programming over To initialize 8259 interrupt controller 7F Extended NMI sources enabling is in progress K eyboard test started Clearing output buffer checking for stuck key to issue keyboard reset co
60. System Hardware OA x OE 66 i D i i 18 iA ic 20 2 2 26 28 30 22 m 5 3 22 50 21428 Check ROM Copyright Initialize Interrupt V ectors Initialize BIO S Interrupts Verify Video Configuration Initialize PCI O ption ROM Manager i 10 Configure Advanced Cache Registers 2 6 2 4 5 5 0 4 8 1 5 0 0 0 4 7 0 1 7 0 5 0 2 0 0 0 0 0 0 0 5 2 2 3 3 5 2 5 2 3 i 5 5 5 5 5 196 BIOS POST Code Listings Phoenix PCI BIOS UMC Chipset Continued Enable External and CPU Registers Set Up APM Display External Cache Size Display Shadow Message Display Non D isposable Segments Display Error Messages Check for Configuration Messages li 50 Se Up Hardware Vecos 13 Test Coprocessor 55 Tnte Extended BIOS Dala Ara 100 197 Reinitialize Onboard I Ports Initialize BIO S D ata Areas 5 2 5 5 3 EN LN EM EM EN 40 22 21 5 0 5 5 2 2 8 3 0 3 6 2 6 3 9 9 6 5 6 4 6 4 6 4 3 4 4 9 1 0 0 9 A0 2 3 Phoenix PCI BIOS UMC Chipset Continued Check Key Lock 2 43 Error Initializing O ption ROM DC Phoenix ISA EISA MCA Version 3 07 w w w tu gt gt gt gt gt gt gt o m gt 2 gt Post Diag Code Sect Description CPU Regist
61. Table of Contents AM utut itas 223 Awa Osos cansa 223 atra 223 A O 224 A NN 224 PVG CRIN cesta ein II 224 CHAPTER 225 225 CHAPTER 7 235 The Legacy Probe 235 A O 235 Using a 236 APPENDIX A ona 237 2 5 ERI A ERU RR ERR RENS 243 Warranty IRA IA 243 246 NOTES O AE de 247 Introduction About Micro2000 Inc Micro 2000 was formed in September 1990 to supply the PC industry with top quality diagnostics which were virtually non existent at the time for that segment of the industry Since then the company has maintained its position of leadership through outstanding technical support and by staying consistently on the cutting edge throughout the rapid advances in PC technology that continue to occur Whether it is PC diagnostic software or hardware educational materials or network administrative tools you can trust all Micro 2000 products to be state of the art and to be the highest quality products of their kind available anywhere About Post Probe The Post Probe is the tool to quickly diagnose any IBM compatible PC that will not boot up The Post Probe is a printed circuit card that plugs into any vacant bus slot on the computer s motherboard It can be used with the ISA bus EISA or the newer PCI bus The Post
62. This LED should blink periodically during the Post If it does not the main suspects are the CPU the DMA circuit Bus Controller or the Clock Generator This LED has no function on the PCI bus READ This LED will be lit anytime the BIOS tries to read from an O device such as the hard drive floppy keyboard etc If an I O device is failing this will give you a clue whether the fault is with the device or its controller light blinks on or something on the motherboard such as the BIOS the DMA chip light doesn t go on On the backside of the board this LED is labeled DEVS IOR I O WRITE Lights when the BIOS writes to a device and provides the same troubleshooting clues as the I O READ Labeled TRDY IOW MEMORY WRITE BIOS checks RAM by writing to memory and then reading what was written This LED blinks during the write If it doesn t suspect the BIOS or the DMA chip Label is IRDY SMEMW MEMORY READ If MEMORY WRITE blinks but this one doesn t try replacing the RAM Labeled FRAME SMEMR CLOCK CLK This monitors the main system timing signal It should blink rapidly and continuously and may appear to be steady on If not lit check the crystal or the clock generator chip This signal is used on both the ISA and PCI but is not present on the MCA bus in Micro channel systems Chapter 1 OSCILLATOR OSC This crystal was the main system timing in XT machines but now is just used by the video control
63. To check recovery mode and verify main BIOS checksum If either it is recovery mode or main BIOS checksum is bad go to check point 0 for recovery else go to check point D 7 for giving control to main BIOS Find main BIOS module in ROM image Uncompress the main BIO S module Copy main BIO S image to F000 shadow RAM and give control to amin BIOS in F000 shadow RAM Intel SR440BX Boot Block Recovery Code Description Onboard floppy controller if any is initialized Compressed recovery code is uncompressed in F000 0000 in shadow RAM and give control to recovery code in F000 shadow RAM Initialize interrupt vector tables initialize system timer initialize D MA controller and interrupt controller Initialize extra Intel Recovery Module Initialize floppy drive Try to boot from floppy devices Try to boot from ATAPI If reading boot sector is successful give control to boot sector code Booting from floppy failed look for ATAPI LS120 Zip 162 BIOS POST Code Listings Intel SR440BX Boot Block Recovery Continued Booting from floppy failed and ATAPI device failed Give two beeps Retry the booting procedure again go back to check point E9 Intel SR440BX Runtime Code U noompressed in F000 Shadow RA M Post Code Description 05 POST code to heunoompresed 08_ CMOS checksum calculation t be doneret 08 Any milton before keyboard BAT to he done net 0 Keyboard controller 1 fr
64. al POST Values BIOS POST Code Listings za T i Set Initial CPU Speed 0 Check ROM Copyright Notice Keyboard Controller Initialization BIOS ROM Checksum LN 201 3 Configure Advanced Cache Registers LN LN LN 202 BIOS POST Code Listings User Batch 2 Disable A20 Address Line 2 2 2 7 Clear 4 GB ES Segment Register 61 5 5 5 5 6 5 6 4 6 4 2 7 5 3 55 24 2 5 8 3 7 0 8 1 6 6 1 6 3 7 6 7 0 7 1 31 54 26 10 i Ga 65 208 Search for Option RO Ms 2 2 4 2 4 2 2 2 Be a D2 EN LN 96 EM EN EM 52 3 Phoenix BIOS Version 4 0 Continued D4 6 4 6 5 Pending Interrupt Error 27 54 Option ROM Error Initialization 51 27 24 5 1 7 T 4 0 51 2 3 1 21 3 1 Boot Device Initialization 1 Boot Code Read OK Phoenix Version 4 Release 6 0 51 27 24 51 27 54 40 BIOSROMOKTet O 51 24 31 21 31 Post Diag Code Sect Description 06 2454 System Hardware 24 Chipset wih POST Vales 9 247 Set nial POST Valuesin POST Flag B 2255 Enable CPU Cale 204 BIOS POST Code Listings Phoenix Version 4 Release 6 0 Continued 60 Configure Advanced Chipset Registers CMOS Values to Alternate Registers Interrupt Vectors Initialization POST Device
65. an be damaged by voltages higher than 12 VDC or lower than 12 VDC 236 Appendix ISA BUS DIAGRAM PCI BUS DIAGRAM STANDARD INTERRUPTS MEMORY ALLOCATIONS COMMON MOTHERBOARD CHIPS 237 Appendix GROUND B1 VO CHK DRV B2 DATA 7 5 VDC DATA 6 IRQ2 DATA 5 5VDC 5 DATA 4 DRQ2 B6 DATA 3 12VDC B7 DATA 2 OWS B8 DATA 1 412 VDC B9 DATA 0 GROUND 10 VO RDY SMEMW B11 AEN SMEMR 12 ADDR 19 13 ADDR 18 14 ADDR 17 3 15 ADDR 16 DRQ3 16 ADDR 15 LB17 ADDR 14 lt DRQ1 ADDR 13 tr REFRESH B19 ADDR 12 5 CLK B20 ADDR 11 IRQ7 B21 ADDR 10 lt IRQ6 B22 ADDR 9 a IRQ5 B23 ADDR 8 IRQ4 B24 ADDR 7 o B25 ADDR 6 gt DACK2 26 ADDR 5 27 ADDR 4 BALE 28 ADDR 3 lt 5 VDC B29 ADDR 2 0 OSC B30 ADDR 1 GROUND 1 ADDR O 5 16 SBHE VOCS 16 LADDR 23 IRQ10 LADDR 22 IRQ 11 LADDR 21 IRQ 12 LADDR 20 IRQ 15 LADDR 19 IRQ 14 LADDR 18 DACK 0 LADDR 17 5 MEMW 5 8 6 DATA 9 DRQ 6 DATA 10 DACK 7 DATA 11 DRQ7 DATA 12 5 VCD DATA 13 MASTER DATA 14 GROUND DATA 15 238 12 VDC TEST CLOCK GROUND TEST DATA OUTPUT 5 VDC 5 VDC INTERRUPT B INTERRUPT D PRSNT 14 RESERVED 2 ACCESS KEY ACCESS KEY RESERVED GROUND CLOCK GROUND REQUEST 3 3 VDC ADDRESS 31 ADDRESS 29 GROUND ADRESS 27 ADDRESS 25 3 3 VDC C BE 3
66. ard controller interface test over To write command byte and init circular buffer Command byte written global data init done To check for lock key Lock key checking over to check for memory size mismatch with CMOS Memory size check done to display soft error and check for password or bypass setup Password checked About to do programming before setup 87 Programming before setup complete To uncompress SETUP code and execute CMOS setup 88 Returned from CMOS setup program and screen is cleared About to do programming after setup Programming after setup complete G oing to display power on screen message 8B First screen message displayed WAIT message displayed PS 2 mouse check and extended BIOS data area allocation to be done 8C Setup options programming after CMOS setup about to start 8D Going to hard disk controller reset 154 BIOS POST Code Listings Intel D820LP Runtime Continued Hard disk controller reset done Floppy setup to be done next 1 Floppy setup complete Hard disk setup done next 5 Init of different buses optional RO Ms from 800 to start Going to do any init before C800 optional ROM control 97 Any init before C800 optional control is over Optional check and control will be done next Optional ROM control is done About to give control to do any required processing after optional RO M returns control and enable extemal cache Any initialization required after optional
67. at module The cards are either SIMMs Single In line Memory Modules 24 Diagnostic Procedures with 30 or 72 pins or DIMMs Dual In line Memory Modules with 168 pins All of the SIMMs or DIMMs in a bank must be the same Size Most POST routines will first determine the amount of memory present and check to see that the amount found agrees with the switch settings and CMOS values Then they will thoroughly test the first 64K partially test memory above 64K and test the refresh signal which is an intermittent voltage supplied to the RAM chips Some BIOS will also test each data line and address line individually which greatly aids troubleshooting If so this info will be found in Chapter 3 under the POST code listings for that BIOS See Appendix A for memory allocations Memory may be mapped in different ways from one system to the next If the system won t boot up because of memory failure and you don t know the mapping strategy in use the low tech solution is to get one SIMM or DIMM of the same capacity presently used in the system and swap out each module in tum until the problem disappears If the symptoms persist the problem is most likely with the signals coming to the module the address lines data lines voltages or refresh signal There is also memory mapping circuitry on the motherboard which may have failed 5 2 Protected Mode The first PCs only had one megabyte of memory and operated in what is now called Real
68. ate display retrace checking Video display checking over Display mode to be set next Display mode set G oing to display the power on message Different buses init input IPL general devices to start if present 9 Display different buses initialization error messages New cursor position read and saved To display the hit lt DEL gt message To prepare the descriptor tables To enter in virtual mode for memory test To enable interrupts for diagnostic mode To initialize data to check memory wrap around at 0 0 D ata initialized Going to check for memory wrap around at 0 0 and finding the total system memory size Memory wrap around test done Memory size calculation over About to go for writing patterns to teat memory 7 Pattern to be tested written in extended memory G oing to write patterns in base 540K memory R N 2 186 BIOS POST Code Listings Intel RC440BX Runtime Continued Patterns written in base memory Going to find out amount of memory below 1MB memory 49 Amount of memory below 1MB found and verified G oing to find out amount of memory above 1MB Amount of memory above 1MB found and verified Check for soft reset and going to clear memory below 1MB for soft reset Memory below 1MB cleared G oing to clear memory above 1MB Memory above 1MB cleared oing to save the memory size Memory test started A bout to display the first 64K memory size 4F Memor
69. atic output devices to start if present Give control for any setup required before optional ROM check To look for optional video ROM and give control D Give control to do any processing after video RO M retums control 138 ER gt S BIOS POST Code Listings Intel D 815 Runtime Continued If EGA VGA not found then do display memory R W EGA VGA not found Display memory R W test about to begin Display memory R W test passed About to look for the retrace checking alternate Display memory R W test alternate display retrace checking Display mode set Going to display power on message Different buses init input IPL general devices to start if present Display different buses initialization error messages New cursor position read and saved To display the Hit DEL message To prepare the descriptor tables To enter virtual mode for memory test To enable interrupts for diagnostics mode To initialize data to check memory wrap around at 0 0 Data initialized Going to check for memory wrap around at 0 0 and finding the total system test memory Memory wrap around test done Memory size calculation over About to go for writing patterns to test memory 7 Pattern to be tested written in extended memory G oing to write patterns in base 640K B memory Patterns written in base memory G oing to find out amount of memory below 1M memory Amount of memory below 1M fo
70. ation 0 1 19 for bootloader AMI Ez Flex BIOS um Post Diag Code Sect Description 10 81 Keyboard Hard Sot Reet 6 iz 07 81 8042 Keyboard Controle Tet 0 81 8042 Keyboard Controle Tet 19 8i 8042 Keyboard roa 8i 8042 Keyboard Controle Tet 5282 Test 042 Protected Mode CEE 2 1 8 8 8 8 8 8 25 26 41 81 27 26 26 2526 2 0 4 1 4 2 1 1 1 1 1 7 6 6 0 3 AMI Ez Flex BIOS Continued 81 Test 042 Keyboard 81 Keyboard Controller Global Function 71 Monochrome 72 _ Test Video ColorMode CGA 22 Check for EGA VGA 74 _ Test Video Memory ron EGATVGA Tee Adapter ETE 7 7 Test Alternate Video Memory Test Alternate Video Adapter 70 Test Video Mode 1 2 2 2 0 0 0 0 0 0 8 1 8 1 0 7 1 7 2 0 4 7 3 2 4 74 7 0 74 7 0 7 0 42 BIOS POST Code Listings AMI Ez Flex BIOS Continued Test Video Mode Initialize BIOS ROM Area Set Power On Display Cursor Display Power On Message 4 Read Cursor Position Display Cursor Reference N Display Setup Message Protected Mode Tested N Build D escriptor Tables Check for Memory Below 1MB 7 1 1 di 7 5 5 5 2 5 5 5 5 5 10
71. ay the system configuration B Put Int13 module runtime image to shadow form the runtime SMBIO S image in shadow Copying of code to specific area done Going to give control to Int19 boot loader 142 BIOS POST Code Listings Intel D815EPEA BIOS U noompressed IN IT Code C he points Code Description NMI is disabled Onboard keyboard controller and real time clock enabled if present Initialization code checksum verification starting D1 Keyboard controller BAT test CPU ID saved and going to 4G B flat mode D3 Initialize chipset start memory refresh and determine memory size 4 Verify base memory D5 Initialization code to be copied to segment 0 and control to be transferred to segment 0 Control is in segment 0 Used to check if in recovery mode and to verify main BIOS checksum If in recovery mode or if main BIO S checksum is wrong go to checkpoint 0 for recovery Otherwise got o checkpoint D 7 to give control to main BIOS Find main BIOS module in ROM image Uncompress the main BIO S module Copy main BIO S image to F000 shadow RAM and give control to main BIOS in F000 shadow RAM Intel D815EPEA Boot Block Recovery Post Code Description Onboard diskette controller if any is initialized Compressed recovery code is uncompressed at F000 0000 in shadow RAM Give control to recovery code at F000 in shadow RAM Initialize interrupt vector tables system timer D MA controller and
72. cleared lt WAIT gt message displayed About to start D MA and interrupt controller test register test passed To do DMA 1 base register test 62 DMA 1 base register test passed To do DMA 2 base register test 2 base register test passed To program DMA 1 2 DMA 1 and 2 programming over To initialize 8259 interrupt controller Extended NMI sources enabling is in progress K eyboard test started Clearing output buffer checking for stuck key to issue keyboard reset command 140 BIOS POST Code Listings Intel 815 Runtime Continued 81 Keyboard reset error stuck key found To issue keyboard controller interface test command 2 Keyboard controller interface test over To write command byte and init circular buffer Command byte written global data init done To check for lock key 84 Lock key checking over To check for memory size mismatch with CMOS Memory size check done display soft error and check for password or bypass setup code and execute CMOS setup About to do programming after setup Programming after setup complete G oing to display power 0n screen message B First screen message displayed WAIT message displayed PS 2 mouse check and extended BIO S data area allocation to be done C Setup options programming afier CMOS setup about to Sat 97 Any init before C800 optional ROM control is over Optional ROM check and
73. comes down to replacing either the keyboard or the controller chip 8 2 A 20 Line One line of the keyboard controller is often used to control Address line 20 More information on this is available under section 5 2 PROTECTED MODE 29 Chapter 2 8 3 Keyboard Lock For security some systems come with a keyboard lock that prevents the system from accepting keyboard input This is a physical lock turned with a key and usually mounted on the front of the case but sometimes on the keyboard Only a few BIOS versions test this 8 4 Turbo Switch On some systems POST will check this switch usually located on the front of the case next to the Reset switch The switch has no function on 486 or higher CPUs 9 0 Error Display If errors occur during the POST many BIOS versions will attempt to put a message on the monitor screen telling you what failed If the system is functioning well enough for the message to arrive on the screen consider yourself lucky Most of these error messages are self explanatory but IBM PC and PS 2 systems send 6 digit code These codes are listed at the end of the BIOS codes chapter 10 0 Reserved Certain POST codes are marked Reserved or OEM specific The BIOS manufacturer will assign these as requested by their customers and you will need to contact your system vendor or motherboard manufacturer to find out what function has been assigned to a particular reserved code Codes marked Debug are
74. compatible PnP ISA devices serial parallel etc 2 SSS i Clear interrupts from COM port detection C Initialize floppy controller Initialize and detect hard disks Detect and test for Mouse or Auxiliary device on keyboard controller Install CD ROM for boot Jump to UserPatch2 Initialize G PNV areas of D MI Search for option RO Ms One long two short beeps for checksum failure of an option ROM Scan for User flash ROMs MP Table initialization wake up secondary processor and halt it Setup Power Management not used Inital ul S E Enable hardware 2 Initialize DMI tables Log POST errors with POST Error Manager and to SEL in BMC Update VID bits and memory presence to BMC Display any FRB errors watchdog time outs bist or CPU failures Erase F2 prompt A Scan for F2 keystroke C Initialize EMP port if selected Remove CO M2 from BDA of EMP is enabled Enter SETUP EN EN EN 8B EN 182 BIOS POST Code Listings Intel NA440BX N440BX BIOS Continued Clear IN POST flag Tum on secure boot if enabled secure front panel blank video floppy write protect Check for errors POST done prepare to boot O perating System One short beep before boot Display Quiet Boot not used Clear screen Check password optional Clear parity checkers Not used ACPI configuration table configuration in memory and BDA Display Multi Boot m
75. continues it not only becomes less feasible to monitor signals which are now completely inside the chips it is also less practical to replace the chips Many of these large integrated circuits are surface mounted parts which can only be removed and installed with specialized equipment However if you find yourself working on a system that is old enough to have some discrete chips for the various motherboard functions Appendix B has a list of the more common chip designations for these functions 235 Chapter 7 Using The Probe The probe itself is an insulated lead about 2 1 2 feet long with a banana jack on one end and the probe tip on the other To use the probe insert the banana jack into a matching banana plug near one edge of the Post Probe card Insert the card into any vacant ISA slot and turn on the system Now the test tip can be placed on any integrated circuit pin you wish to monitor If you are monitoring signals which transition during the Post it might be better to place the tip on the appropriate pin before turning on the power so that the transition can be observed The results can be seen on one of the three LEDs just above the banana plug labeled HI TRI and LOW HI above 2 6 VDC TRI between 1 5 and 2 6 VDC LOW less than 1 5 VDC Voltages of 5 VDC and 12 VDC are shown by lighting both the HI and LOW indicators at the same time The probe is designed to be used with voltages up to 12 VDC but c
76. control to boot sector code Boot from diskette and ATAPI device failed Give two beeps Retry the booting procedure go to checkpoint E9 117 3 Intel D810E2CB Runtime Code U noompressed in F000 Shadow RA M Post Code Description 05 POST code to heunoompresed 08 CMOS checksum calculation be doneret HB 0 Keyboard controller 1 free To issure the BAT command to the keyboard controller Any initialization after keyboard controller BAT to be done next Keyboard command byte written Going to issue Pin 23 24 blocking unblocking command 11 Going to check pressing of lt INS gt lt END gt key during power on 12 To init CMOS if Init CMOS in every boot is set or lt END gt key is pressed Going to disable DMA and interrupt controllers 1 Video display is disabled and port B is initialized Chipset init about to begin 8254 timer test about to start About to start memory refresh test 1A Memory refresh line is toggling G oing to check 15 ys On OFF time 23 To read 8042 input port and disable mega key G reen PC feature Make BIOS cade segment writeable To do any setup before int vector init 25 Interrupt vector initialization to begin To clear password if necessary Any initialization before setting video mode to be done 118 Any initialization before keyboard BAT done next BIOS POST Code Listings Intel D810E 2CB Runtime Continued 28 Going for monoc
77. d to segment 0 and control to be transferred to segment 0 Control is in segment 0 Used to check if in recovery mode and to verify main BIOS checksum If in recovery mode or if main BIOS checksum is wrong go to checkpoint 0 for recovery Otherwise got o checkpoint D 7 to give control to main BIOS Find main BIO 5 module in ROM image Uncompress the main BIO S module main S image to F000 shadow RAM and give control to main BIOS in F000 shadow RAM 1 D7 p Intel CA810E Boot Block Recovery Code Post Code Description Onboard disk controller if any is initialized Compressed recovery code is uncompressed at F000 0000 in shadow RAM Give control to recovery code at 2000 in shadow Initialize interrupt vector tables system timer DMA controller and interrupt controller BIOS POST Code Listings Intel 810 Runtime Code Continued Initialize extra Intel recovery module Initialize diskette drive Try to boot from diskette If reading of boot sector is successful give control to boot sector code EB Boot from diskette failed look for ATAPI LS 120 Zip devices Try to boot from ATAPI device If reading of boot sector is successful give control to boot sector code EF Boot from diskette and ATAPI device failed Give two beeps Retry the booting procedure go to checkpoint E9 Intel CA810E Runtime Code U noompressed in F000 Shadow RA M Post Code Description
78. dow Option RO Ms 3 2 4 1 Set Up Power Management 3 2 4 3 Hardware Interrupts Enable 3 3 1 1 Set Time Of Day 3 3 1 3 Key Lock Test 3 3 3 1 Erase F2 Prompt 3 3 3 3 Scan For F2 Key Stroke 3 3 4 1 Enter SETUP 3 3 4 3 Clear POST Flag 3 4 1 1 Check for Errors 3 4 1 3 Prepare to Boot O perating System 3 4 2 1 One Beep 3 4 23 Password Check 3 4 31 Clear Global D escriptor Table 3 4 4 1 Clear Parity Checkers 3 4 4 3 Clear Screen 3 4 4 4 Virus Backup Reminder Check 4 1 1 1 Boot with INT 19 4 2 1 1 Interrupt Handler Error 4 2 1 3 Unknown Interrupt Error 4 2 2 1 Pending Interrupt Error 4 2 2 3 Option ROM Error Initialization 4 2 31 Shutdown Error 4 2 33 Extended Block Move 4 2 4 1 Shutdown I O Error 4 3 1 3 Chipset Initialization 4 3 1 4 Refresh Counter Initialization 4 3 2 1 Forced Flash Check 4 3 2 2 HW Status of Check 4 3 2 3 BIOSROM OK Test 4 3 2 4 RAM Test 4 3 3 1 PIC Initialization 4 3 33 Read In Bootstrap Code 4 3 3 4 Vector Initialization 221 4 Phoenix 4 0 Continued Beep Code 4 3 4 1 4 3 4 2 4 3 4 3 QUADTEL Beep Code 15 25 11 25 11 35 222 Failure Boot the Flash Program Boot Device Initialization Boot Code Read OK Failure Start of PO ST CMOS Video Controller Peripheral Controller Chapter 5 POST Procedures Each BIOS version has its own peculiarities These include the testing sequence and also what port is used to output the codes General guidelines for
79. e parity N MI NMI and parity enabled G oing to do any initialization required before giving control to optional ROM at E000 Initialization before 000 ROM control over E000 ROM to get control next Returned from E000 ROM control G oing to do any initialization required after E000 optional RO M control Initialization after E000 optional ROM control is over Going to display the system configuration Put Int13 module runtime image to shadow Generate MP for multiprocessor support if present Put CGA Int10 module if present in shadow Uncompress SMBIO S module and init SMBIOS code and form the runtime SMBIO S image in shadow Going to copy any code to specific area Copying of code to specific area done G oing to give control to Int19 boot loader A A5 Goingto enable parity NMI eee AB Put Int13 module runtime image to shadow _______ Intel CC820 BIOS Uncompressed IN IT C ode C heck points Post Code Description NMI is disabled O nboard K BC RTC enabled if present Init code checksum verification starting Keyboard controller BAT test CPU ID saved and going to 4G B flat mode Do necessary chipset initialization start memory refresh and do memory sizing Verify base memory Init code to be copied to segment 0 and control to be transferred to segment 0 ER A 03 D Ven semen AA 104 BIOS POST Code
80. e source of trouble because one of these cards could be shorting out the bus Now orient the Post Probe card so that the row of LEDs are facing up for PCI or toward the front of the computer for ISA If there is any doubt about the orientation of the card there are arrows adjacent to each of the connectors The arrow for the connector in use should be pointing toward the nearest edge of the motherboard Push the Post Probe gently and evenly into a vacant bus slot When the card bottoms out in the slot check along the top edge of the slot to ensure that the card is straight and even You may need to remove a plate or bracket covering the opening at the back of the computer by taking out the screw at the top of the bracket Once the card is installed remove your hands and any tools from the computer case 11 1 and turn on the power The computer will begin its Power O n Self Test What do all those lights mean The Post Probe has two types of displays to tell you what is happening with signals on the bus One is the 2 digit HEX display which we will cover in a later section The other is a set of red green and yellow LEDs The green LEDs check the voltages and the red LED monitors the Reset line The yellow LEDs each show the status of a different bus signal Voltages The five green LEDs monitor the DC voltages from the power supply Starting from the comer of the card the voltages are 3 3 VDC 5 VDC
81. each Post Code number you will find the manufacturer s description of the test as well as a reference number to a particular section of the Diagnostic Procedures in Chapter 2 If you then go to that section of Chapter 2 you will see a detailed analysis of the hardware being tested in that portion of the Post procedures and suggestions to help you isolate and fix the problem The tables are extensive listing over 65 different BIOS versions from 22 manufacturers However new BIOS versions are being released all the time and several BIOS manufacturers will customize the BIOS for their customers For this reason it is quite possible to encounter a POST code that is not included in the tables On the other hand a corrupted BIOS can also cause illegitimate Post Codes that are not in the table 16 Using The POST Probe If the computer is damaged to the extent that Post cannot begin the card will display a code of AA This will usually require replacement of the BIOS the CPU or the entire motherboard The condition can also occur if an adapter card is shorting out one or more bus signals Certain BIOS codes are marked Reserved or OEM specific The BIOS manufacturer will assign these as requested by their customers and you will need to contact your system vendor or motherboard manufacturer to find out what function has been assigned to a particular reserved code Codes marked Debug are used by the manufacturer to test the chips but are no
82. ector tables system timer DMA controller and interrupt controller Initialize extra Intel recovery module Initialize diskette drive 130 BIOS POST Code Listings Intel D815BN Boot Block Recovery Continued Try to boot from diskette If reading of boot sector is successful give control to boot sector code Boot from diskette failed look for ATAPI LS 120 Zip devices Try to boot from ATAPI device If reading of boot sector is successful give control to boot sector code Boot from diskette and ATA PI device failed Give two beeps Retry the booting procedure go to checkpoint E9 Intel 0815 Runtime Code U noompressed in F000 Shadow RA M Post Code Description NMI is disabled To check soft reset power on BIOS stack set Going to disable cache if any 106 POST code to be uncompressed CPU init and CPU data area init to be done 08 CMOS checksum calculation to be done next 0 Any initialization before keyboard BAT done next Keyboard controller 1 free To issure the BAT command to the keyboard controller Any initialization after keyboard controller BAT to be done next Keyboard command byte written Going to issue Pin 23 24 blocking unblocking command Going to check pressing of INS END gt key during poweron To init CMOS if Init CMOS in every boot is set or lt END gt key is pressed G oing to disable DMA and interrupt controllers 13 Video display is disabled and port B is
83. ed Award 6 0 Boot Block U sed when updating Flash BIOS ROM Code Description Clear Base Memory Initialize Keyboard Controller Initialize Interrupt V ectors Ini Initialize Floppy and nboard Super I 70 BIOS POST Code Listings COMPAQ General Post Diag Code Description 0 22 Flags MSWIDTUN 06 2681 NormalCMOSResetCode 31 09 26 Reset CodeinCMOSBye ________ 08 8182 Vector Vis 4067 With EOI Function 0D 32 20 Initialize blast VD U Controller 71 3 General Continued 7 DMA Controller Page Registers 1 5 8 Test Keyboard Controller 5 25 nitialize Time of D ay nitialize 287 Coprocessor est the Keyboard and 8042 Reset A20 Set Default CPU Speed Test Diskette Subsystem Test Fixed Disk Subsystem Initialize Parallel Printer Perform Search for O ptional RO Ms Test Valid System Configuration Clear Screen Check for Invalid Time and D ate Optional Search Test Timer 2 Write to Diag Byte Clear First 128k Bytes of RAM Load Interrupt Vectors 70 77 Load Interrupt Vectors 00 1F Initialize MEMSIZE and RESETWD Verify CMOS Checksum CMOS Checksum is Not Valid Check Battery Power Check for G ame Adapters 6 2 Check for Serial Ports 6 3 heck for Parallel Printer Ports 54 8 1 nitialize Port and Comm Time outs 8 1 Flush Keyboard Buffer 2 33 2 5 8 2 6 5 6 4 6 3
84. ee issure the command to the keyboard controller Any initialization after keyboard controller BAT to be done next Keyboard command byte written Going to issue Pin 23 24 blocking unblocking command 11 Going to check pressing of INS END gt key during poweron 12 To init CMOS if Init CMOS in every boot is set or lt END gt key is pressed Going to disable DMA and interrupt controllers 1 Video display is disabled and port B is initialized Chipset init about to begin 8254 timer test about to start About to start memory refresh test A Memory refresh line is toggling G oing to check 15 ys On OFF time 23 To read 8042 input port and disable mega key G reen PC feature Make BIO 5 cade segment writeable 1 163 3 Intel SR440BX Runtime Continued 24 To do any setup before int vector init 25 Interrupt vector initialization to begin To clear password if necessary Any initialization before setting video mode to be done Going for monochrome mode and color mode setting Different buses init system static output devices to start if present To give control for any setup required before optional ROM check To look for optional video ROM and give control To give control to do any processing after video returns control f EGA VGA not found then do display memory R W EGA VGA not found Display memory R W test about to begin Display memory R W test passed About to
85. em test memory To enable interrupts for diagnostics mode To initialize data to check memory wrap around at 0 0 126 BIOS POST Code Listings Intel D810EMO Runtime Continued Memory test started NO T SOFT RESET About to display the first 64K B memory size Memory size display started This will be updated during memory test G oing for sequential and random memory test Memory testing initialization below 1MB complete G oing to adjust displayed memory size for relocation shadow Memory size display adjusted due to relocation shadow Memory test above 1MB to follow Memory testing initialization above 1MB complete G oing to save memory size information Memory size information is saved CPU registers are saved Going to enter real mode Shutdown successful CPU in real mode G oing to disable gate A 20 line and disable parity NMI Fri N A20 address line parity NMI disable successful Adjust memory size depending on relocation shadow Memory size adjusted for relocation shadow G oing to clear hit lt DEL gt message Hit lt D EL gt message cleared lt WATT gt message displayed About to start D MA and interrupt controller test page register test passed do DMA 1 base register test DMA 1 base register test passed To do D MA 2 base register test DMA 2 base register test passed To program DMA 1 and 2 DMA 1 and 2 programming over To initia
86. enu if ESC is hit Display system configuration summary if enabled in 5 Get total of hard drives and put in BDA Program ID E hard drives timing PIO modes etc Save total of hard drives SCSI and ATA in BDA Fix up MP Table checksum Check SMART hard drive Prepare to boot OS clean up graphics and PMM areas Try to boot Int19h Return to video mode 3 disable PMM return to real mode disable gate 20 clear system memory reset stack invoke Int19h AE T 86 BD 9 _ Intel RC440BX BIOS U nompressed IN IT Code C he points Post Code Description NMI is Disabled Onboard KBC RTC enabled if present Init code Checksum verification starting Keyboard controller BAT test CPU ID saved going to 4GB flat mode 183 Chapter 3 Intel RC440BX BIOS Continued D3 Do necessary chipset initialization start memory refresh do Memory sizing Verify base memory D5 Init code to be copied to segment 0 and control to be transferred to segment 0 Control is in segment 0 To check recovery mode and verify main BIOS checksum If either it is recovery mode or main BIOS checksum is bad go to check point 0 for recovery else go to check point D7 for giving control to main BIOS Find main BIOS module in ROM image Uncompress the main BIOS module Copy main BIOS image to F000 shadow RAM and give control to main BIOS in F000 shadow RAM Intel RC44
87. er Test CMOS Write Read Test ROM BIOS Checksum PIT Test DMA Initialization BIOS POST Code Listings 57 DMA page Register 51 RAM 51 Fm amp GRRAMTet 51 Fist6ikRAMDaaLne 51 Fist 4k RAM Pasty 51 Address Line Fist RAM Bit 0 First 64K RAM Bad Bit 1 First 64K RAM Bad Bit 2 First 64K RAM Bad Bit 3 First 64K RAM Bad 14 Bit 4 First 64K RAM Bad BitO First 64K RAMBad Bit 1 First 64K RAMBad Bit 2 First 64K RAMBad Bit 3 First 64K RAMBad Bit 4 First 64K RAMBad 16 51 18 Bit 9 First 4K Bit 10 First 64K RAMBad Bit 11 First 64K RAMBad Bit 12 First 4K Bit 13 First 64K RAMBad Bit 14 First 64K RAMBad Bit 15 First 64K RAMBad Bit 9 First 64K Bad 1 Bit 10 First 64K RAM Bad Bit 11 First 64K RAM Bad iC 51 Bit 12 First 64K RAM Bad Bit 13 First 64K RAM Bad Bit 14 First 64K RAM Bad Bit 15 First 64K RAM Bad 199 3 Phoenix ISA EISA MCA Version 3 07 Continued 25 7 70 2 6 Phoenix BIOS Version 4 0 Hm Co co Cw ow wl 5 gt AI AaB 6 two Post Diag Code Sect Description 06 2454 System Hardware Initialization 08 24 Init Chipset with Initi
88. f present in shadow Uncompress SMBIO 5 module and init SMBIOS code and form the runtime SMBIOS image in shadow Going to copy any code to specific area Copying of code to specific area done G oing to give control to Int19 boot loader Eri 129 3 Intel D815BN BIOS Uncompressed IN IT Code C hek points Code Description NMI is disabled O nboard keyboard controller and real time clock enabled if present Initialization code checksum verification starting D1 Keyboard controller BAT test CPU ID saved and going to 4G B flat mode D3 Initialize chipset start memory refresh and determine memory size 4 Verify base memory D Initialization code to be copied to segment 0 and control to be transferred to segment 0 Control is in segment 0 Used to check if in recovery mode and to verify main checksum If in recovery mode or if main BIO S checksum is wrong go to checkpoint E0 for recovery Otherwise got o checkpoint D 7 to give control to main BIOS Find main BIOS module in ROM image Uncompress the main BIO S module Copy main BIOS image to F000 shadow RAM and give control to main BIOS in F000 shadow RAM Intel D815BN Boot Block Recovery Post Code Description Onboard diskette controller if any is initialized Compressed recovery code is uncompressed at 000 0000 in shadow RAM Give control to recovery code at F000 in shadow RAM Initialize interrupt v
89. fore functional However for later portions of the Post these codes can provide additional information that should be useful in pinpointing malfunctioning components IBM Code Description 000100 System or CPU board on 90 95 000101 System Board or PIC failed 000102 ROM BIOS PIT 90 95 CPU board 000103 ROM BIOS 2KB CMOS or PIT CPU board on 90 95 Verify jumper is in position 2 3 000104 8259 PIC Protected Mode failed Check 8259 8042 000105 8253 4 failed or Reset command from 8042 not accepted PIC PIT failure or hot NMI on 90 95 Check memory 8254 8259 000111 I O Parity Error Memory adapter RAM chip 000112 MCA Watchdog timeout Adapter system board 000113 DMA arbitration timeout Check any adapter 60 or 120 MB drive system board 000114 External ROM error 6 000116 80386 16 32 Bit Test failed PIC bus controller 8042 000118 System board memory 000121 Unexpected Interrupt Check adapter boards 000131 Cassette Wrap failure PC DMA compatibility Check drive plugs connectors 000132 4 DMA chips 000152 RTC CMOS chip battery 000160 Adapter ID not recognized 000161 Battery dead or not connected or CMOS Byte 0 incorrect 000162 An adapter or attached hardware is failing 000163 System CMOS options not set 000164 Memory Size Error CMOS bad RAM chip or address line 000165 System options not set or a CMOS setting does not match BI
90. hrome mode and color mode setting Different buses init system static output devices to start if present To give control for any setup required before optional ROM check To look for optional video ROM and give control To give control to do any processing after video ROM returns control If EGA VGA is not found then do display memory R W EGA VGA not found Display memory R W test about to begin Display memory R W test passed Ab out to look for the retrace checking Display memory R W test or retrace checking failed To do alternate Display memory R W test Alternate Display memory R W test passed To look for the alternate display retrace checking Video display checking over Display mode to be set next Display mode set Going to display the power on message Different buses init input IPL general devices to start if present Display different BUS initialization error messages New cursor position read and saved To display the Hit lt DEL gt message To prepare the descriptor tables gt Eri To enter virtual mode for memory test To enable interrupts for diagnostics mode To initialize data to check memory wrap around at 0 0 Data initialized G oing to check for memory wrap around at 0 0 and finding the total system test memory Memory wrap around test done Memory size calculation over About to go for writing patterns to test memory 119 28 3 Intel D810E2CB Runti
91. idation 6 51 Memory Refresh Validation Enor 9 51 Vent Base Memory 9 70 DMA Controller 2 Verified Verify Interrupt Controller 1 210 5 57 BMAColeiVef BIOS POST Code Listings Westem Digital BIOS Continued Lower 640K Mem Fault Mem Fault Above 1MB 211 Chapter 4 BIOS Beep Codes Some manufacturers have their BIOS emit a series of beeps indicating what part of the Post routine failed to pass Each manufacturer has their own approach to this Some use long and short beeps some use low tones and high tones and still others rely just on the number of beeps to convey the information Unlike the hex codes though the beep patterns tend to be consistent for each BIOS manufacturer and do not vary from one BIOS version to the next Although not as definitive as the hex codes these beep codes are still useful when troubleshooting a non booting system particularly when a Post Probe card is not at hand AMI Beep Code Failure 1S RAM Refresh Failure 25 Parity Error 35 RAM Base 64 45 System Timer Failure 5S CPU 65 20 Failure 75 Virtual Mode 85 Video Memory 95 ROM Checksum 105 5 Register 115 Cache Test 1L 3S Memory Test 11 85 Display Test 212 BIOS Beep Codes Award 4 51 Beep Code 1L 11 25 11 35 AST Beep Code 115 125 1L 11 15 11 25 11 35 11 45 11 55 11 65 11 75 11 85
92. in Microid Research s BIOS Code Table in Chapter 3 MR BIOS L Low Tone H High Tone Beep Code Failure LH LLL ROM BIOS Checksum LH HLL DMA Page Register LH LHL Keyboard Controller LH HHL RAM Refresh LH LLH 1st DMA Controller LH HLH 2nd DMA Controller LH LLLL First 64KB Pattern Test LH HLLL First 64KB Parity G enerator LH LHLL First 64K B Parity Check LH HHLL First 64KB Data LH LLHL First 64K B Address LH HLHL First 64K B Block Read LH LHHL First 64K B Block Write LH HHHL PIC 1 LH LLLH PIC 2 LH HLLH PIC 1 Address Failure LH LHLH PIC 2 Address Failure LH HHLH PIC Address Error LH LLHH PIC 1 Stuck Interrupt LH HLHH PIC 2 Stuck Interrupt 215 4 BIOS Continued Beep Code Failure LH LHHH PIT IRQ Failure LH HHHH PIT 1 LH LLLLH PIT 2 LH HLLLH PIT Output Failure LH LHLLH CMOS RAM LH HHLLH RTC Interrupt LH LLHLH Video ROM Checksum LH HLHLH Keyboard Controller LH LHHLH RAM Parity Error LH HHHLH Channel Error LH LLLHH A 20 Timeout Error LH HLLHH A 20 Stuck Disabled LH LHLHH A 20 Stuck Enabled Phillips Phillips beep codes are the binary coded equivalent of the PO ST hexadecimal display with a short beep equal to zero and a long beep equal to one For example an Interrupt Controller failure causes a hex code of 35 Converting each digit to binary gives 0011 0101 and would result in the series of beeps long long short long short long Note that any zeroes on the left are trunca
93. ings Award Elite Version 4 51PG Continued lA 2 2 2 5 24 54 52 63 N F 5 5 2 2 5 Security Check Write CMOS Pre Boot Enable Initialize O ption ROMs 2 5 2 6 Initialize Time Value Detect amp Init Math Coprocessor Mfg POST Loop or D isplay Messages Chipset Initialization 24 56 63 4 1 1 7 6 6 2 6 6 5 6 4 3 0 4 3 6 4 4 1 6 8 1 1 8 1 2 4 4 1 5 2 2 2 2 5 5 5 3 2 2 9 9 LN EN 3 Award Elite Version 4 51 PG Continued Cache Presence Test Award BIOS Version 6 0 Same as Phoenix M edallion BIOS Post Diag Code Sect Description 01 Expand x group codes in RAM at 1000 0 N ote 01 is the 7 step of POST not the 1st It follows C C1 and C5 in that order 02 10 0 Reserved 03 2 0 Initialize Superio Early Init Switch 04 10 0 Reserved 05 2 6 Clear CMOS Error Flag Blank O ut Screen 10 0 Reserved 07 8 1 Clear 8042 Interface Start 8042 Self Test 8 1 Test Super I O Keyboard Controller 10 0 Reserved 0A 6 6 8 0 D etect Keyboard and Mouse Ports 10 0 Reserved 0C 10 0 Reserved 10 0 Reserved OE 5 5 Test Shadowing Capability OF 10 0 Reserved 10 24 Auto D etect for D MI Support 11 10 0 Reserved 12 2 6 Test 5 Memory Set Status 13 10 0 Reserved 2 4 Set Chipset D efault Values BIOS POST Code Listings Award BIOS Version 6 0 Continued Set Early Init Onboard Generator Switch 2 10 0 Detec
94. initialized Chipset init about to begin 8254 timer test about to start 131 3 Intel D815BN Runtime Continued 19 About to start memory refresh test 1A Memory refresh line is toggling 6 oing to check 15 ys On OFF time To read 8042 input port and disable mega key Green PC feature Make BIOS cade segment writeable To do any setup before int vector init Interrupt vector initialization to begin To clear password if necessary Any initialization before setting video mode to be done Going for monochrome mode and color mode setting Different buses init system static output devices to start if present To give control for any setup required before optional ROM check To look for optional video ROM and give control To give control to do any processing after video ROM returns control If EGA VGA not found then do display memory R W Display memory R W test passed About to look for the retrace checking gt EGA VGA not found Display memory W test about to begin Display memory R W test or retrace checking failed To do alternate D isplay memory W test Alternate Display memory R W test passed To look for the alternate display retrace checking Video display checking over Display mode set next Display mode set G oing to display power on message Different buses init input IPL general devices to start if present Display different buses initialization error mes
95. interrupt controller Initialize extra Intel recovery module Initialize diskette drive 143 3 Intel D815E PEA Boot Block Recovery Continued EA Try to boot from diskette If reading of boot sector is successful give control to boot sector code Boot from diskette failed look for ATAPI 1 5120 Zip devices EC Try to boot from ATAPI device If reading of boot sector is successful give control to boot sector code EF Boot from diskette and ATAPI device failed Give two beeps Retry the booting procedure go to checkpoint E9 Intel D815EPEA Runtime Code U noompressed in F000 Shadow RA M Post Code Description 05 POST code to e uncompressed 08 CMOS checksum calculation to be doneret FOB Any initialization before keyboard BAT done next 0 Keyboard controller 1 free To issure the BAT command to the keyboard controller Any initialization after keyboard controller BAT to be done next Keyboard command byte written Going to issue Pin 23 24 blocking unblocking command 1 Going to check pressing of lt INS gt lt END gt key during power on 12 To init if Init CMOS in every boot is set or END gt key is pressed Going to disable DMA and interrupt controllers 13 Video display is disabled and port 15 initialized Chipset init about to begin 144 BIOS POST Code Listings Intel 815 PEA Runtime Continued 4 8254 timer test about to start 9 About to
96. ions of the card that show 0 and 120 FF The self diagnostic mode will put the display into a ontinuous loop which won t stop unless it encounters a card malfunction If this occurs contact technical support Chapter 1 The Hex Display Each brand and version of BIOS has its own Post routine that it goes through on boot up and each has its own set of codes that it puts out for the various parts of the Post Even though all computers are prone to the same types of problems the codes will vary and need to be interpreted Fortunately however all BIOS put out the codes in hexadecimal format These hexadecimal codes are displayed by the 7 segment Hex display There are two digits in the display because most BIOS versions use a 2 digit code There are certain 5 such as the HP Vectra ES RS and 05 that use a 4 digit code so the first two digits are displayed momentarily first followed by the last two digits of the code There is a second hex display on the backside of the Post Probe card It displays the same code but makes it easy to read the codes no matter which way the card is oriented in the computer To find out what a code means you must locate the table for your particular BIOS in Chapter 3 of this volume The tables are in alphabetical order by manufacturer Each table lists the codes for those BIOS in numerical order Once you have found the correct table go to the displayed code within that table Next to
97. isplayed About to start DMA and interrupt controller test DMA page register test passed To do DMA 1 base register test 62 DMA 1 base register test passed To do DMA 2 base register test 65 DMA 2 base register test passed To program DMA 1 and 2 0 al MA 1 and 2 programming over To initialize 8259 interrupt controller Extended NMI sources enabling is in progress Keyboard test started Clearing output buffer checking for stuck key to issue keyboard reset command Keyboard reset error stuck key found To issue keyboard controller interface test command Keyboard controller interface test over To write command byte and init circular buffer ER Lock key checking over to check for memory size mismatch with CMOS Memory size check done to display soft error and check for password or bypass setup Password checked About to do programming before setup Programming before setup complete To uncompress SETUP code and execute CMOS setup Command byte written global data init done To check for lock key E E de 102 BIOS POST Code Listings Intel 810 Runtime Code Continued Retumed from 5 setup program and screen is cleared About to do programming after setup Programming after setup complete G oing to display power on screen message First screen message displayed WAIT message displayed PS 2 mouse check and extended data area allocation
98. ize POST Error Manager 2 4 nitialize Error Logging 2 4 nitialize Error Display Function 2 4 nitialize System Error Handler 2 4 nitialize the Chipset 2 4 nitialize the Bridge 2 2 24 nitialize the Processor 3 2 itialiize System Timer Initialize Multiprocessor Initialize OEM Special Code 5 1 Initialize Memory Type 5 1 Shadow Boot Block 1 System Memory Test 83 B8 gt C0 C1 C2 ES C4 1 2 E4 ES E6 E7 E8 E9 EA EB EC ED EE EF 6 1 2 6 4 2 4 0 2 6 2 4 2 7 2 4 2 7 2 4 5 1 Ea 3 HP Pavillion Series 3100 amp 8000 PCs Continued Initialize Beeper Initialize BO OT HP Vectra BIOS Post Diag Code Sect Description 7 5 5 5 8 81 Keyboard Controller Self Test EF Test Timer 0 Timer 2 57 32 0 2 0 1 2 7 2 0 3 5 Test Subsystem 3 Test Interrupt Controller Test RAM Address Lines w w w 84 BIOS POST Code Listings HP Vectra BIOS Continued Size Extended Memory Real Mode RAM Test HP Vectra ES Post Diag Code Sect Description 12 26 27 81 85 3 HP Vectra ES Continued 1 1 c N c N 2 LA N N ER c N LA CO gt
99. ke up secondary processor and halt it Setup Power Management not used Enable security Enable hardware interrupts 2 Log post errors with PO ST error manager and to SEL in BMC Update VID bits and memory presence to BMC Display and FRB errors watchdog time outs bits or processor failures Erase F2 prompt Scan for F2 keystroke Initialize EMP port if selected Remove CO M2 from BDA if EMP is enabled Enter SETUP ClearIN POST flag gt EM Em 8B EM Chapter 3 Intel LB440GX LB440GX BIOS Continued Tum on secure boot if enabled secure front panel blank video floppy write protect Check for errors POST done prepare to boot O perating System B6 Check password optiona Clear parity checkers Not used BD _ Display Multi Boot menu if ESCishit Save total of hard drives SCSI and ATA in BDA 9j Check SMART harddrive 2 Try to boot with Int19h Return to video mode 3 disable return to real mode disable gate A 20 clears system memory resets stack invokes Int19h DO interupthandreror 11 D6 Initialize option ROM error De Shuidownemor 178 BIOS POST Code Listings Intel NA440BX N440BX BIOS Post Code Description Verify real mode 12 Restore processor control word during warm boot only occurs on warm boot i i OE D 28 2 RAM failure on data bits xxxx of low b
100. lculation over About to go for writing patterns to test memory N Pattern to be tested written in extended memory G oing to write patterns in base 640K B memory Patterns written in base memory G oing to find out amount of memory below 1M memory Amount of memory below 1M found and verified G oing to find out amount of memory above 1M Amount of memory above 1M found and verified Check for soft reset and going to clear memory below 1M for soft reset If power on go to check point 4E Mem below 1M cleared SOFT RESET Going to clear mem above 1M Memory above 1M cleared SOFT RESET Going to save the memory size Go to check point 52 Memory test started NOT SOFT RESET About to display the first 64K B memory size Memory size display started This will be updated during memory test G oing for sequential and random memory test Memory testing initialization below 1MB complete G oing to adjust displayed memory size for relocation shadow Memory size display adjusted due to relocation shadow Memory test above 1MB to follow Memory testing initialization above 1MB complete G oing to save memory size information Memory size information is saved CPU registers are saved Going to enter real mode 146 BIOS POST Code Listings Intel D815E PEA Runtime Continued 54 Shutdown successful CPU in real mode G oing to disable gate A20 line and disable parity N MI 57 A20 address line parity
101. ler for color frequency The signal is not present on the PCI bus On an ISA bus the LED will blink rapidly and may appear steady on If not replace the 14 138 Mhz crystal This LED is located next to the Reset LED PCI Signals CLOCK This is the only signal other than voltages monitored in common with the PCI bus It should blink rapidly or appear steadily on FRAME This signal defines the timing window for data transfer on the bus The LED should blink repeatedly during Post If not the problem is most likely with the PCI chipset particularly the bus controller IRDY Initiator Ready This LED blinks when the bus recognizes a device is ready to transfer data If this function is not working problems will be with the PCI chipset TRDY Target Ready Blinks when the bus recognizes a device is ready to receive data Problems could be with the PCI chipset or with an I O device DEVS Device Select This signal shows that a device has been selected for data transfer If no blinks suspect the bus controller Switches Stepping Switch There are two push button switches located at the edges of the card opposite the connectors Either of these allow you to step through and view the POST codes one at a time in reverse of the sequence in which they were issued Just push one of the buttons to progress to the previous code There are two buttons so that one of them should be easily accessible no matter how the Post Probe card is
102. lize 8259 interrupt controller Extended NMI sources enabling is in progress Keyboard test started Clearing output buffer checking for stuck key to issue keyboard reset command Keyboard reset error stuck key found To issue keyboard controller interface test command 127 3 Intel D810EMO Runtime Continued 82 eyboard controller interface test over write command byte and init circular buffer Command byte written global data init done To check for lock key Lock key checking over To check for memory size mismatch with CMOS Memory size check done To display soft error and check for password or bypass setup Password checked About to do programming before setup gt 87 Programming before setup complete To uncompress SETUP code and execute 5 setup Returned from CMOS setup program and screen is cleared About to do programming after setup Programming after setup complete G oing to display power on screen Message First screen message displayed WAIT message displayed PS 2 mouse check and extended data area allocation to be done Setup options programming after CMOS setup about to start In w Going to do any init before C800 optional ROM control Any init before C800 optional RO M control is over Optional RO M check and control will be done next Optional ROM control is done About to give control to do a
103. ller 1 free To issure the BAT command to the keyboard controller Any initialization after keyboard controller BAT to be done next Keyboard command byte written Going to issue Pin 23 24 blocking unblocking command 11 Going to check pressing of INS END gt key during poweron 12 To init CMOS if Init CMOS in every boot is set or lt END gt key is pressed Going to disable DMA and interrupt controllers 1 Video display is disabled and port B is initialized Chipset init about to begin 8254 timer test about to start About to start memory refresh test 1A Memory refresh line is toggling G oing to check 15 ys On OFF time 23 To read 8042 input port and disable mega key Green PC feature Make BIOS cade segment writeable To do any setup before int vector init 25 Interrupt vector initialization to begin To clear password if necessary Any initialization before setting video mode to be done 106 BIOS POST Code Listings Intel CC820 Runtime Code Continued 28 Going for monochrome mode and color mode setting Different buses init system static output devices to start if present To give control for any setup required before optional ROM check To look for optional video ROM and give control To give control to do any processing after video returns control gt Eri If EGA VGA not found then do display memory R W EGA VGA not found Display memory R W test about to begin Display memor
104. look for the retrace checking Display memory R W test or retrace checking failed To do alternate D isplay memory R W test Alternate D isplay memory R W test passed To look for the alternate display retrace checking Video display checking over Display mode set next Display mode set G oing to display power on message Different buses init input IPL general devices to start if present Display different buses initialization error messages New cursor position read and saved To display the Hit DEL message 164 BIOS POST Code Listings Intel SR440BX Runtime Continued Data initialized oing to check for memory wrap around at 0 0 and finding the total system test memory Memory wrap around test done Memory size calculation over About to go for writing patterns to test memory Pattern to be tested written in extended memory Going to write patterns in base 640K memory Patterns written in base memory G oing to find out amount of memory below 1M memory Amount of memory below 1M found and verified Going to find out amount of memory above 1M Amount of memory above 1M found and verified Check for soft reset and going to clear memory below 1M for soft reset If power on go to check point 4E Memory below 1M cleared SOFT RESET G oing to clear memory above 1M Memory above 1M cleared SOFT RESET Going to save the memory size Go to check point 52 Memory test started NOT SOFT RE
105. me Continued Pattern to be tested written in extended memory G oing to write patterns in base 640K B memory 48 Patterns written in base memory oing to find out amount of memory below 1M memory 9 Amount of memory below 1M found and verified Going to find out amount of memory above 1M memory 4B Amount of memory above 1M found and verified Check for soft reset and going to clear memory below 1M for soft reset If power on go to check point 4E 4 Memory below 1M cleared SOFT RESET G oing to clear memory above 1M AD Memory above 1M deared SOFT RESET Going to save the memory size Go to check point 52 display the first 64K B memory size AF Memory size display started This will be updated during memory test G oing for sequential and random memory Memory test started NOT SOFT RESET About to test 50 Memory testing initialization below 1MB complete G oing to adjust displayed memory size for relocation shadow 51 Memory size display adjusted due to relocation shadow Memory test above 1MB to follow 52 Memory testing initialization above 1MB complete oing to save memory size information 53 Memory size information is saved CPU registers are saved Going to enter real mode 54 Shutdown successful CPU in real mode G oing to disable gate A 20 line and disable parity NMI 57 20 address line parity NMI disable successful Going to adjust memory size depending on relocation shadow 8 Memory size adj
106. me clock enabled if present Initialization code checksum verification starting D1 Keyboard controller BAT test CPU ID saved and going to 4G B flat mode 116 BIOS POST Code Listings Intel D810E2CB BIOS Continued D3 Initialize chipset start memory refresh and determine memory size 4 Verify base memory 5 Initialization code to be copied to segment 0 and control to be transferred to segment 0 Control is in segment 0 Used to check if in recovery mode and to verify main BIOS checksum If in recovery mode or if main BIOS checksum is wrong go to checkpoint 0 for recovery Otherwise got o checkpoint D 7 to give control to main BIOS Find main BIOS module in ROM image Uncompress the main BIO S module Copy main BIOS image to F000 shadow RAM and give control to main BIOS in F000 shadow RAM Intel D810E2CB Boot Block Recovery Code Description Onboard diskette controller if any is initialized Compressed recovery code is uncompressed at F000 0000 in shadow RAM Give control to recovery code at F000 in shadow RAM Initialize interrupt vector tables system timer DMA controller and interrupt controller Initialize extra Intel recovery module Initialize diskette drive EA Try to boot from diskette If reading of boot sector is successful give control to boot sector code Boot from diskette failed look for ATAPI LS120 Zip devices Try to boot from ATAPI device If reading of boot sector is successful give
107. mmand Keyboard reset error stuck key found To issue keyboard controller interface test command Keyboard controller interface test over To write command byte and init circular buffer Command byte written global data init done To check for ock key c N R Lock key checking over To check for memory size mismatch with CMOS Memory size check done To display soft error and check for password or bypass setup Password checked About to do programming before setup Programming before setup complete To uncompress SETUP code and execute CMOS setup Retumed from CMOS setup program and screen is cleared About to do programming after setup Programming after setup complete G oing to display power on screen message First screen message displayed lt WAIT gt message displayed PS 2 mouse check and extended BIOS data area allocation to be done E 03 86 _ 87 166 BIOS POST Code Listings Intel SR440BX Runtime Continued 8C Setup options programming after 5 setup about to start 80 Going to hard disk controller reset Hard disk controller reset done Floppy setup to be done next Floppy setup complete Hard disk setup done next Init of different buses optional RO Ms from C800 to start 96 Going to do any init before C800 optional ROM control 97 Any init before C800 optional ROM control is over Optional ROM check and control will be done next Optional ROM contr
108. mong other things this memory holds the date and time RAM configuration information about the peripheral devices such as their IRQ and DMA assignments disk drive parameters whether the computer will start up in Real or Protected Mode etc The CMOS is usually contained in the RTC chip Any number of hardware or software glitches can corrupt the values stored in CMOS in ways that can prevent bootup The POST will check values stored in CMOS against data it receives from other system components and any mismatch can cause the POST to lock up If you can determine the incorrect value try changing it manually through CMOS Setup and restart the computer before replacing any hardware If the POST continues to fail or CMOS cannot maintain its contents the problem may be the chip but more likely will be the CMOS battery or its connections The battery may be inside the RTC chip or an external lithium battery Some HP systems power the CMOS with a capacitor rather than a battery 2 7 Extended CMOS Newer and more complex systems have more variables such as PnP than can be stored in the normal RTC chip and use a chip which has an additional 2K of CMOS memory This is labeled XCMOS 3 0 Interrupts The most common problem with interrupts during the POST is that two I O devices are set to the same IRQ or interrupt request level Remove the most recently installed adapter card The system will probably boot up and you can then use the Micro
109. mory 5 4 ___ BaseMemoryTest 51 __ Base Memory Eror amp 1 Verify Keyboard Commands 31 Iniiaize PIC Master 00 Initialize PIC Slave 26 CMOSByeODTet 15 CMOSChdsunTet 16 CMOSByteD lt WH 81 Check Sofy Hard Rest 1B 52 Protected Mode Initialization _______ 95 2 2 2 2 2 3 1 2 1 2 1 2 6 2 7 5 7 5 1 8 1 8 1 8 1 8 1 5 1 5 1 5 1 8 1 3 1 3 1 2 6 2 6 2 6 8 1 5 2 9 LN w w HD 3 Display Error 160 PIC Master Slave Test 2 1 6 5 1 1 1 2 1 96 BIOS POST Code Listings IBM PS 2 MCA Continued Exit Protected Mode Test for Loop 140 140 140 CW 26 54 97 IFINI DOD D N D D DO D D OI U 5 99 5 5 2 6 9 4 4 4 2 2 6 8 1 41 64 41 1 4 60 6 La 69 6 6D 3 IBM PS 2 Continued Boot code ROM Basic Intel CA810E BIOS Uncompressed IN IT Code C he points Post Code Description NMI is disabled O nboard keyboard controller and real time clock enabled if present Initialization code checksum verification starting Keyboard controller BAT test CPU ID saved and going to 4G B flat mode Initialize chipset start memory refresh and determine memory size Verify base memory Initialization code to be copie
110. most newer systems it will be part of an integrated 1 O Controller on the motherboard 27 Chapter 2 6 4 Hard Drive The POST will first query the controllers and compare to what the CMOS says should be there It may then do a seek test of each drive to the last cylinder and then to the first The problem may be the drive or the controller but it could also be the CMOS values If you can load a diagnostic disk such as Micro Scope you can better pin point the failure area 6 5 Floppy Drive The BIOS will initialize and test he floppy drive As with the hard drive a failure could be the controller the drive or corrupted CMOS 6 6 Miscellaneous I O Many newer BIOS will test the dedicated mouse port and a few will check for a game port If the mouse port fails make sure the mouse is plugged in and doesn t have the keyboard plugged into that port The game port may fail because no controller is dedicated to that port and you will have to disable or remove the port in order to pass the POST Refer to the system docum entation for instructions 7 0 Video The POST may interrogate the Video Card to see what kind of monitor is installed If the test fails most likely the monitor is not connected or doesn t match CMOS parameters 7 1Monochrome Display The BIO S may separately initialize the monochrome and color control circuitry as a holdover from the days when color monitors were a novelty If the controllers are actually
111. nal ROM check and control will be done next Optional ROM control is done About to give control to do any required processing after optional ROM returns control and enable external cache Any initialization required after optional test over Going to setup timer data area and printer base address 9A Return after setting timer and printer base addresses Going to set the RS 232 base address Retumed after RS 232 base address oing to do any initialization before coprocessor test Required initialization before coprocessor is over G oing to initialize the coprocessor test Coprocessor initialized G oing to do any initialization after coprocessor test 9E Initialization after coprocessor test is complete G oing to check extended keyboard keyboard ID and num lock Going to display any soft errors A3 Soft error display complete G oing to set keyboard typematic rate Keyboard typematic rate set To program memory wait states Going to enable parity N MI 7 NMI and parity enabled Going to do any initialization required before giving control to optional ROM at E000 A8 Initialization before E000 ROM control over E000 ROM to get control next 9 Returned from E000 ROM control Going to do any initialization required after E000 optional RO M control AA Initialization after E000 optional RO M control is over Going to display the system configuration 110 BIOS POST Code Listings D Put CGA module f presen in shado
112. ne Ports Available Determine LPT Ports Available co LN LN LN LN La 32 BIOS POST Code Listings AMI 2 2 BIOS Continued 2 6 4 0 Initialize BIO S D ata Area 6 4 6 5 Fixed Floppy Controller Test AMI Plus BIOS Post Diag Code Sect Description 00 ii Control To inept 06 32 SsemTimerComingOK 8 57 CH2efDd amp ComtTetOK 19 57 CHiofDdaComtTetOKk 08 57 PaiySawCkmd 5732 Refresh Link Togging OK 33 3 AMI Plus BIOS Continued Address Line Test OK 51 __ 64K Base Memory Test OK 5 1 4 0 Interrupt Vectors Initialized CMOS Read Write Test OK 81 8042 Keyboard Controller 26 CMOSChecksum Battery check Monochrome Mode Set OK 7 2 MES Color Mode Set OK Video ROM Search Optional Video ROM Control OK mr a 3 ee 0 EES 70 Video Retrce Check OK ee 70 VieTeOK 70 Video Dipy 152 Vinu Mode Memory Tet N Display Memory Read Write Test OK Processor in Virtual Mode Memory Address Line Test Memory Address Line Test Global Byte set for Video OK Memory Below IMB Calculated Memory Test in Progress Memory Initialization O ver below 1MB Memory Initialization Over above 1MB Display Memory Size Memory Size Computation OK 5 1 5 1 8 1 2 6 2 6 7 1 7 3 7 3 74 74 7 0 7 0 7 0 7 0 1 2 1 1 1 1 1 1 1 1 34
113. nter base address Going to set the RS 232 base address Returned after RS 232 base address oing to do any initialization before coprocessor test Required initialization before coprocessor is over G oing to initialize the coprocessor next Coprocessor initialized G oing to do any initialization after coprocessor test E Initialization after coprocessor test is complete oing to check extended keyboard keyboard ID and num lock Going to display and soft errors Soft error display complete G oing to set keyboard typematic rate co 4 Keyboard typematic rate set To program memory wait states NMI and parity enabled oing to do any initialization required before giving control to optional ROM at E000 Initialization before E000 ROM control over E000 ROM to get control next Returned from E000 ROM control Going to do any initialization required after E000 optional ROM control gt Initialization after E000 optional ROM control is over G oing to display the system configuration B C form the runtime SMBIOS image in shadow 189 Eri Chapter 3 Intel RC440BX Runtime Continued Going to copy any code to specific area to INT19 boot loader m Copying of code to specific area done G oing to give control Phoenix BIOS Plus Version 1 0 Post Diag Code Sect Description 22 26 2 32 57 57 50 50 50 First 64KB Logic Failure 0 50 First64KB Party Emor 10 First 6
114. ntime Continued 0 Keyboard controller I free issure the BAT command to the keyboard controller Any initialization after keyboard controller BAT done next Keyboard command byte written Going to issue Pin 23 24 blocking unblocking command Going to check pressing of lt INS gt lt END gt key during power on To init CMOS if Init CMOS in every boot is set or lt END gt key is pressed Going to disable DMA and interrupt controllers Video display is disabled and port B is initialized Chipset init about to begin 8254 timer test about to start About to start memory refresh test Memory refresh line is toggling G oing to check 15 ys On OFF time To read 8042 input port and disable mega key Green PC feature Make BIOS cade segment writeable To do any setup before int vector init Interrupt vector initialization to begin To clear password if necessary Any initialization before setting video mode to be done Going for monochrome mode and color mode setting Different buses init system static output devices to start if present To give control for any setup required before optional ROM check To look for optional video ROM and give control To give control to do any processing after video ROM returns control If EGA VGA not found then do display memory R W EGA VGA not found Display memory R W test about to begin Eri 125 3 Intel D810EMO Runtime Continued 30 Display mem
115. ny required processing after optional RO M returns control and enable external cache Any initialization required after optional ROM test over Going to setup timer data area and printer base address Return after setting timer and printer base addresses Going to set the RS 232 base address 8D 96 97 128 BIOS POST Code Listings Intel D810EMO Runtime Continued Returned after RS 232 base address oing to do any initialization before coprocessor test Required initialization before coprocessor is over G oing to initialize the coprocessor test Coprocessor initialized G oing to do any initialization after coprocessor test Initialization after coprocessor test is complete G oing to check extended keyboard keyboard ID and num lock Going to display any soft errors Soft error display complete G oing to set keyboard typematic rate Keyboard typematic rate set To program memory wait states Going to enable parity N MI NMI and parity enabled Going to do any initialization required before giving control to optional ROM at E000 Initialization before E000 ROM control over E000 ROM to get control next Returned from E000 ROM control Going to do any initialization required after E000 optional RO M control Initialization after E000 optional ROM control is over Going to display the system configuration Put Int13 module runtime image to shadow G enerate MP for multiprocessor support if present Put CGA Int10 module i
116. ocations 0A0000 OAFFFF 0B0000 OB7FFF 0B8000 0 0000 0C8000 OD FFFF 0E0000 OEFFFF 0 0000 OFSFFF 0F6000 OFD FFF 0FE000 OFFFFF 100000 10FFFF 241 Appendix Common Chips Pentium I IV Pentium Pro MMX K5 K6 Athlon 6x86 DMA CONTROLLER 8237 8254 8042 8742 82288 82C206 PIT mum CONTROLLER meo ss 242 Appendix Warranty Information 243 Limited Hardware Warranty The manufacturer warrants to the original purchaser of this product that the hardware shall be free from defects resulting from faulty manufacture or components for a period of one 1 year from the date of sale Defects covered by this Limited Warranty shall be corrected either by repair or at the manufacturer s election by replacement In the event of replacement the replacement unit shall be warranted for the remainder of the original one 1 year period or thirty days whichever is longer THERE ARE NO ORAL OR WRITTEN WARRANTIES EXPRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO THOSE OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE This Limited Warranty is non transferable and does not apply if the product has been damaged by accident abuse misuse modification misapplication shipping to the manufacturer or service by someone other than the manufacturer The manufacturer does not warrant that this product will meet the purchaser s req
117. ol is done About to give control to do any required processing after optional returns control and enable external cache Any initialization required after optional ROM test over Going to setup timer data area and printer base address 9A Return after setting timer and printer base addresses Going to set the RS 232 base address Returned after RS 232 base address oing to do any initialization before coprocessor test Required initialization before coprocessor is over G oing to initialize the coprocessor test Coprocessor initialized G oing to do any initialization after coprocessor test 9E Initialization after coprocessor test is complete G oing to check extended keyboard keyboard ID and num lock Going to display any soft errors A3 Soft error display complete G oing to set keyboard typematic rate Keyboard typematic rate set To program memory wait states Going to enable parity NMI 7 NMI and parity enabled oing to do any initialization required before giving control to optional ROM at E000 3 Intel SR440BX Runtime Continued A8 Initialization before E000 ROM control over E000 ROM to get control next A9 Returned from E000 ROM control Going to do any initialization required after E000 optional ROM control AA Initialization after E000 optional ROM control is over Going to display the system configuration Put Int13 module runtime image to shadow Generate MP for multiprocessor support if
118. olate which device is causing the problem Starting with the most recently added device remove the adapter cards one at a time until the problem disappears It may be a defective I O device or its adapter card but often is just a problem with the setup of the device Common errors are two devices both trying to use the same section of memory or set to the same IRQ or DMA values 5 5 ROM Shadowing Most systems have the ability to move ROM code into RAM where it can be accessed much faster If this test fails disable ROM shadowing in the CMOS and tum it back on a portion at a time Start by enabling shadowing for the BIOS ROM then Video ROM If the System Setup allows enable shadowing by the other adapter cards one at a time until the culprit is found The cure could be either the card s ROM or the RAM for that memory section As a quick fix you may be able to just leave shadowing disabled for that device 5 6 Cache In 486 and later processors the CPU has internal cache memory for faster access to frequently needed RAM contents This is Level 1 Cache and if it fails the CPU is defective Additional cache is provided by static SRAM chips external to the CPU called Level 2 Cache Some new CPUs have Level 2 cache in CPU and call it Unified 26 Diagnostic Procedures Cache With a Level 2 Cache failure either the SRAM or CPU is defective or the system expects external cache but none is installed 5 7 DMA Direct Memory Acces
119. om ATAPI device If reading of boot sector is successful give control to boot sector code Boot from diskette and ATAPI device failed G ive two beeps Retry the booting procedure go to checkpoint E9 Intel D815EEA Runtime Code U noompressed in F000 Shadow RA M Post Code Description 03 NMI is disabled To check soft reset power on 05 BIOS stack set Going to disable cache if any 137 3 Keyboard controller I free To issure the BAT command to the keyboard controller Any initialization after keyboard controller BAT done next 0 N Eri Keyboard command byte written Going to issue Pin 23 24 blocking unblocking command Going to check pressing of lt INS gt lt END gt key during power on 2 To init CMOS if Init CMOS in every boot is set or END key is pressed G oing to disable D MA and interrupt controllers Video display is disabled and port B is initialized Chipset init about to begin 0254 timer test about to start 9 About to start memory refresh test Memory refresh line is toggling Going to check 15 pis On OFF time To read 8042 input port and disable mega key G reen PC feature Make BIOS cade segment writeable To do any setup before int vector init 5 Interrupt vector initialization to begin To clear password if necessary Any initialization before setting video mode to be done Going for monochrome mode and color mode setting D ifferent buses init system st
120. on shadow Memory test above 1MB to follow Memory testing initialization above 1MB complete G oing to save memory size information Memory size information is saved CPU registers are saved Going to enter real mode 133 3 Intel D 815BN Runtime Continued 54 Shutdown successful CPU in real mode G oing to disable gate A 20 line and disable parity NMI 57 A20 address line parity NMI disable successful Adjust memory size depending on relocation shadow Memory size adjusted for relocation shadow G oing to clear hit lt D EL gt message Hit lt DEL gt message cleared lt WATT gt message displayed About to start DMA and interrupt controller test DMA page register test passed To do DMA 1 base register test 62 DMA 1 base register test passed To do DMA 2 base register test 65 DMA 2 base register test passed To program DMA 1 and 2 DI MA 1 and 2 programming over initialize 8259 interrupt controller Extended NMI sources enabling is in progress Keyboard test started Clearing output buffer checking for stuck key to issue keyboard reset command Keyboard reset error stuck key found To issue keyboard controller interface test command Keyboard controller interface test over To write command byte and init circular buffer Command byte written global data init done To check for lock key R Lock key checking over To check for memory size misma
121. oriented in the machine 14 Using The POST Probe Please note that the button does not actually cause the Post routines to execute rather it shows you the sequence that has already been executed This information is valuable because the Post will not always stop on the section where the error occurred Sometimes it goes to the next step before locking up In other cases the Post issues its code only after successful completion of a particular routine If it doesn t complete the Post will still be showing the code of the previous routine If the BIOS has been corrupted you may even find the Post executing steps out of sequence and the stepper switch is the only way to easily determine exactly what is happening DIP Switch The four position dual inline pin DIP switch on the Post Probe card sets the I O port that the card reads to get its Post codes Most systems output their codes to 1 O Port 80 but there are exceptions as noted in the table Switch 1234 Port 80 1111 Most ISA EISA amp PCI systems default Port 84 0111 Compaq systems Port 90 1101 PS2 models 25 and 30 Port 190 1100 Any BIOS using Port 190 Port 300 1011 A ward systems with EISA bus Port 380 1010 Compaq systems Port 680 1001 MCA systems All Above 1000 When in doubt try this Test 0000 Self diagnostic mode The settings above represent 02O FF and 1 ON This chart is also silk screened onto the back of the Post Probe Be aware there are some early vers
122. ory R W test passed About to look for the retrace checking 1 Display memory R W test or retrace checking failed To do alternate Display memory R W test 32 Alternate Display memory R W test passed To look for the alternate display retrace checking Video display checking over Display mode set next Display mode set Going to display power on message Different buses init input IPL general devices to start if present Display different buses initialization error messages To prepare the descriptor tables To enter virtual mode for memory test Memory wrap around test done Memory size calculation over About to go for writing patterns to test memory 7 Pattern to be tested written in extended memory G oing to write patterns in base 640 memory Patterns written in base memory Going to find out amount of memory below 1M memory Amount of memory below 1M found and verified G oing to find out amount of memory above 1M Amount of memory above 1M found and verified Check for soft reset and going to clear memory below 1M for soft reset If power on go to check point 4E C Memory below 1M cleared SO FT RESET Going to clear memory above 1M Memory above 1M cleared SO FT RESET Going to save the memory size Go to check point 52 New cursor position read and saved To display the Hit DEL message 5 Data initialized Going to check for memory wrap around at 0 0 and finding the total syst
123. ram memory wait states Going to enable parity N MI NMI and parity enabled G oing to do any initialization required before giving control to optional ROM at E000 Initialization before E000 ROM control over E000 ROM to get control next Returned from E000 ROM control Going to do any initialization required after E000 optional ROM control gt gt E 122 BIOS POST Code Listings Going to display the system configuration Put CGA Int10 module if present in shadow form the runtime SMBIOS image in shadow Copying of code to specific area done Going to give control to Int19 boot loader Intel 0810 BIOS U noompressed IN IT C ode C he points Post Code Description NMI is disabled O nboard keyboard controller and real time clock enabled if present Initialization code checksum verification starting D1 Keyboard controller BAT test CPU ID saved and going to 4G B flat mode Initialize chipset start memory refresh amp determine mem size Verify base memory Initialization code to be copied to segment 0 and control to be transferred to segment 0 Control is in segment 0 Used to check if in recovery mode and to verify main checksum If in recovery mode or if main BIOS checksum is wrong go to checkpoint E 0 for recovery Otherwise got o checkpoint D 7 to give control to main BIOS Find main BIOS module in ROM image D8 Uncompress the main BIOS module
124. roller 1 free To issure the BAT command to the keyboard controller Any initialization after keyboard controller BAT to be done next Keyboard command byte written Going to issue Pin 23 24 blocking unblocking command power on To init CMOS if Init CMOS in every boot is set or lt END gt key is pressed G oing to disable DMA and interrupt controllers Video display is disabled and port B is initialized Chipset init about to begin Memory refresh line is toggling oing to check 15 ps On OFF time 23 To read 8042 input port and disable mega key Green PC feature Make BIOS cade segment writeable To do any setup before int vector init 25 Interrupt vector initialization to begin To clear password if necessary Any initialization before setting video mode to be done 151 3 Intel D820LP Runtime Continued 28 Going for monochrome mode and color mode setting Different buses init system static output devices to start if present To give control for any setup required before optional ROM check To look for optional video ROM and give control To give control to do any processing after video returns control If EGA VGA not found then do display memory R W EGA VGA not found Display memory R W test about to begin Display memory R W test passed About to look for the retrace checking Display memory R W test or retrace checking failed To do alternate Display memory R W test
125. rs Initialize PnP Option RO Ms w gt C1 Initialize POST Error Manager PEM Check password optional Clear global descriptor table ional Clear parity checkers EN 172 BIOS POST Code Listings Intel JN 440BX BIOS Continued nitialize error logging Initialize the chipset Initialize the bridge Initialize the processor I nitialize system timer Initialize OEM special code Initialize PIC and DMA Initialize memory type Initialize memory speed Shadow boot block System memory test Initialize interrupt vectors F3 Initialize beeper LN 173 3 Intel LB440GX LB440GX BIOS Post Code Description Verify real mode 12 Restore processor control word during warm boot only occurs on warm boot m i C4 Initialize system Mas in 05 i Initialize caches to inal POST vales D 28 2A Cear 512KB be RAM RAM om addres 7 2E RAM failure on data bits xxxx of low byte of memory bus 1st 4Meg 38 20 29 Post Memory Manager initialization PMM 33 34 0 174 BIOS POST Code Listings Intel LB440GX LB440GX BIOS Continued Enable processor cache Initialize local bus IDE not used anymore but here for Phoenix standard gt c Test 8742 keyboard controller Read processor bus clock frequency amp compute boot processor speed
126. ry above 1M found and verified Check for soft reset and going to clear memory below 1M for soft reset If power on go to check point 4E Memory below 1M cleared SOFT RESET Going to clear memory above 1M Memory above 1M cleared SOFT RESET Going to save the memory size Go to check point 52 Memory test started NOT SOFT RESET About to display the first 64K B memory size Memory size display started This will be updated during memory test Going for sequential amp random memory test Memory testing initialization below 1MB complete Adjust displayed memory size for relocation shadow Memory size display adjusted due to relocation shadow Memory test above 1MB to follow Memory testing initialization above 1MB complete G oing to save memory size information 101 gt gt gt gt gt gt gt gt gt o Ti Eri J O c 3 Intel CA810E Runtime Code Continued 53 Memory size information is saved CPU registers are saved Going to enter real mode 54 Shutdown successful CPU in real mode G oing to disable gate A 20 line and disable parity NMI A20 address line parity NMI disable successful Going to adjust memory size depending on relocation shadow Memory size adjusted for relocation shadow G oing to clear hit lt D EL gt message Hit lt DEL gt message cleared lt WATT gt message d
127. s Allows data transfers to and from memory without monopolizing the CPU All systems since the 286 use two cascaded D MA chips to provide 15 DMA channels or a VLSI chip that combines D MA with the PIT PIC and RTC functions Y ou may get a POST code for DMA but you should also suspect the DMA if RAM fails and can t be fixed by swapping the memory modules 6 0 I O Input Output This covers any devices which send information to and from the motherboard except for the video and keyboard which are covered separately This includes the floppy and hard drives and the serial and parallel ports Most BIOS routines do not test the CD ROM or sound cards 6 11 0 Enable few POSTS will test the ability to enable and disable an integrated I O Controller 6 2 Serial Ports The POST will search for serial ports and then test them An error shows that a port was found and that a problem was detected with it Most systems have serial ports designated 1 CO 2 and the POST may tell you which was being tested It may also refer to an RS232 test Older systems will have serial controllers that can be replaced but most newer systems have a large scale integrated 1 controller surface mounted on the motherboard 6 3 Parallel Ports An error indicates that the POST found a parallel port but it was not functioning properly The problem is usually the I O controller Older systems will have a parallel controller card but on
128. s or minute metal filings Keep in mind that the problem may also be in the bus controller or other chips connected directly to the bus or on one of the adapter cards 2 2 CPU Central Processing Unit The BIOS will try to identify the CPU and will put that ID into the CMOS It will then have the CPU execute a series of instructions to test its functions If you have just installed a new CPU and retained an obsolete BIOS that could be a cause for failure Otherwise the problem is the CPU chip itself which will have to be replaced Fortunately this chip is usually mounted in a socket or a removable housing 2 3 NPU Numerical Processing Unit Also commonly called the Math Coprocessor this chip handles the more complicated mathematical functions which takes some of the 20 Diagnostic Procedures load from the CPU Since the 486 the NPU is incorporated into the CPU In older systems the NPU is a separate chip which is often impossible to remove and replace without special equipment On these systems replacement of the entire motherboard is the most realistic option 2 4 Chipset This diagnostic code refers to the chip or chips on the motherboard associated with the BIOS rather than the video chipset covered under code 7 0 Each BIOS version is designed to work best with a particular chip set The set would include the PIC PIT DMA controllers BIOS ROM CMOS and These are covered separately but if the problem can
129. sages New cursor position read and saved To display the Hit lt DEL gt message 132 BIOS POST Code Listings gt gt gt gt gt gt gt gt gt F2 gt 1 Y 69 Data initialized oing to check for memory wrap around at 0 0 and finding the total system test memory Memory wrap around test done Memory size calculation over About to go for writing patterns to test memory Pattern to be tested written in extended memory oing to write patterns in base 640K B memory Patterns written in base memory G oing to find out amount of memory below 1M memory Amount of memory below 1M found and verified Going to find out amount of memory above 1M Amount of memory above 1M found and verified Check for soft reset and going to clear memory below 1M for soft reset If power on go to check point 4E Memory below 1M cleared SOFT RESET G oing to clear memory above 1M Memory above 1M cleared SOFT RESET Going to save the memory size Go to check point 52 Memory test started NOT SOFT RESET About to display the first 64K B memory size Memory size display started This will be updated during memory test G oing for sequential and random memory test Memory testing initialization below 1MB complete G oing to adjust displayed memory size for relocation shadow Memory size display adjusted due to relocati
130. separate they will be found on the motherboard rather than on a video adapter card 7 2 Color Display See 7 1 Monochrome D isplay 28 Diagnostic Procedures 7 3 Video ROM The POST looks for a value of 55AAh at memory location C000 0000 and will then run the program located at C000 0003 If this test fails it will probably be a faulty video card but it could also be that the video card identified in CMOS does not match the one installed in the system 74 Video RAM The amount of system RAM allotted to video is not enough for today s graphic intensive programs so video adapters will have their own RAM located on the adapter card itself this test fails replace the video card 8 0 Keyboard The POST will see if it can detect the keyboard and will also test the keyboard controller If the keyboard is not detected make sure it is plugged in and then check the connector As a last resort swap out the keyboard which may be defective or may just need a good cleaning 8 1 Keyboard Controller The keyboard controller chip 8042 8742 is located on the motherboard and controls serial data transfers to and from the keyboard often including the reset signal to the CPU The controller uses IRQ 1 for keystroke data coming in from the keyboard and stores the keystrokes in an internal buffer until the interrupt is recognized by the CPU Some PO ST routines run extensive tests of the keyboard functions but any failure still
131. set with inita POST vales S4INPOSRg b Enable CPU cache 156 BIOS POST Code Listings 4 Initialize BIOSintemupls SSS 157 4 3 Setup System Management Mode SMM area Initialize EISA motherboard 8 LN 8 LN 158 BIOS POST Code Listings Fix up multiprocessor table Search for option ROMs w E 9 w 5 LN 159 3 Clean up all graphics Initialize D parameters Check virus and backup reminders Try to boot with Int19h Initialize PnP Option RO Ms Initialize POST Error Manager Clear global descriptor table Clear parity checkers Display Multi Boot menu Initialize error logging Initialize error display function Initialize system error handler w 80 m 160 BIOS POST Code Listings Boot to mini DOS Boot to full DOS Intel SR440BX BIOS Uncompressed IN IT Code C he points N Post Code Description NMI is disabled O nboard KBC RTC enabled if present Init code checksum verification starting 161 3 Intel SR440BX BIOS Continued D1 Keyboard controller BAT test CPU ID saved and going to 4GB flat mode Do necessary chipset initialization start memory refresh and do memory sizing Verify base memory init code to be copied to segment 0 and control to be transferred to segment 0 Control is in segment 0
132. ss G oing to do any initialization before coprocessor test Required initialization before coprocessor is over Going to initialize the coprocessor test Coprocessor initialized G oing to do any initialization after coprocessor test Initialization after coprocessor test is complete G oing to check extended keyboard keyboard ID and num lock Going to display any soft errors Soft error display complete G oing to set keyboard typematic rate Keyboard typematic rate set To program memory wait states gt 8D 96 97 3 Intel D815BN Runtime Continued Going to enable parity NMI NMI and parity enabled Going to do any initialization required before giving control to optional ROM at E000 Initialization before E000 ROM control over E000 ROM to get control next Returned from E000 ROM control Going to do any initialization required after E000 optional RO M control Initialization after E000 optional ROM control is over Going to display the system configuration Put Int13 module runtime image to shadow Generate MP for multiprocessor support if present Put CGA Int10 module if present in shadow Uncompress SMBIO 5 module and init SMBIOS code and form the runtime SMBIO S image in shadow Going to copy any code to specific area Copying of code to specific area done G oing to give control to Int19 boot loader Intel D815EEA BIOS U noompressed IN IT C ode C he
133. ssembly 19 20 23 005030 3 L40SX external display or system board 005037 0085XX Expanded memory expansion adapter X 0086XX Mouse system board 231 6 0089XX IBM music card SCSI adapter w cache any SCSI device system board Oo 010002 Card selected feedback 010007 Multiprotocol adapter or cable TOX 0104 ESDI drive controller cables 010400 Unknown failure 010450 Read write verify failure 51 010452 010153 104555 010458 Fixed disk integrated controller 01059 010460 232 IBM Error Messages 14702 010473 Corrupt data low level drive 010718 010480 ESDI fixed disk cable controller Switches 2 3 5 ON with 70 115 drive 010481 ESDI controller LS Level 2 cache 90 95 or CPU P75 CPU card 90 95 Verify jumper in pos 1 2 20mhz 014952 Plasma display assembly 016540 6157 streaming tape drive or adapter 0166XX Token ring adapter primary system board 0167XX Token ring adapter alt 233 6 018001 Wizard adapter or adapter memory 018029 018031 Wizard adapter cable 019402 8 80286 memory adapter 0200 Image adapter memory 0208XX SCSI device 0210XY SCSI device Y drive Y A 60mb D 160 mb 80 mb 320mb 120 mb 400 mb U Undetermined drive type 0211XX Sequential access SCSI 2 3 tape drive 0212XX SCSI
134. stuck key to issue keyboard reset command Keyboard reset error stuck key found To issue keyboard controller interface test command Keyboard controller interface test over To write command byte and init circular buffer Lock key checking over To check for memory size mismatch with CMOS Memory size check done To display soft error and check for password or bypass setup Password checked About to do programming before setup Command byte written global data init done To check for lock key Programming before setup complete To uncompress SETUP code and execute CMOS setup Returned from CMOS setup program and screen is cleared About to do programming after setup Programming after setup complete G oing to display power on screen Message First screen message displayed WAIT message displayed PS 2 mouse check and extended BIOS data area allocation to be done Setup options programming after CMOS setup about to start Going to hard disk controller reset Hard disk controller reset done Floppy setup to be done next 109 w c Ti N gt N 3 Intel CC820 Runtime Code Continued Floppy setup complete Hard disk setup done next Init of different buses optional RO Ms from 800 to start 96 Going to do any init before C800 optional ROM control 97 Any init before C800 optional ROM control is over Optio
135. t 52 Memory test started NOT SOFT RESET About to display the first 64 memory size Memoyy size display started This is updated during memory test Sequential and random memory test 0 Memory testing initialization below 1MB complete G oing to adjust displayed memory size for relocation shadow 5 Memory size display adjusted due to relocation shadow Memory test above 1MB to follow 52 Memoyy testing initialization above 1 complete G oing to save memory size information 5 Memory size information is saved CPU registers are saved Going to enter real mode 54 Shutdown successful CPU in real mode G oing to disable gate A 20 line and disable parity NMI 57 20 address line parity NMI disable successful Going to adjust memory size depending on relocation shadow 8 Memory size adjusted for relocation shadow oing to clear hit lt D EL gt message 59 Hit DEL message cleared WAIT message displayed About to start D MA and interrupt controller test D MA page reg test passed do DMA 1 base reg test BIOS POST Code Listings Intel CC820 Runtime Code Continued 62 DMA 1 base register test passed To do DMA 2 base register test D MA 2 base register test passed To program DMA 1 and 2 DMA 1 and 2 programming over To initialize 8259 interrupt controller al Extended NMI sources enabling is in progress Keyboard test started Clearing output buffer checking for
136. t CPU Data N N 0 10 0 10 0 3 0 6 10 0 N 10 0 10 0 Initialize HPM Notebook Only E 100 100 100 100 100 22 24 100 100 100 78 100 100 100 100 100 65 E 3 Award BIOS Version 6 0 Continued 100 100 100 100 100 100 100 100 100 Test Channel 2 Bits 00 100 100 10 0 10 0 10 0 10 0 10 0 10 0 100 Initialize CPU and Cache 10 0 Initialize USB m RN ho o a a ER 66 BIOS POST Code Listings Award BIOS Version 6 0 Continued Test Extended Memory 100 106 00 10 0 10 0 N D 5 0 1 N N 100 100 100 106 100 100 100 100 30 50 100 22 50 100 100 00 6 5 Initialize Floppy Controller N N gt N 66 RN oF c N Ea 67 3 Award BIOS Version 6 0 Continued 100 100 100 Test for AWDFLASH EXE 10 0 100 62 63 100 100 N 100 100 100 100 10 N 10 0 1 0 4 3 Enable Power Mgt Check for Password 21 54 100 100 100 100 100 100 100 41 Read Boot Sector for Antivirus Code N TE 100 RN 68 BIOS POST Code Listings Award BIOS Version 6 0 Continued 96 25 Load RTC Date Time
137. t be isolated to a particular function you will be referred to this code If the Chipset Initialization Test fails you will need the specific documentation from the motherboard or manufacturer to isolate the problem or else just replace the motherboard If the failure is the Chipset Wait State you can usually cure it by changing the 5 wait state values for the Read Write Cache Read Cache Write etc Refer to the BIOS documentation 2 5 System Clock There are two aspects of the clock that are tested during the POST First are the crystal oscillators The main crystal generates the timing frequency for the CPU and Bus This signal is also indicated by the CLOCK LED on the POST Probe card There is a second 14 318 crystal which was the original system clock but is now just used by the PIT and video circuits The other part is the Real Time Clock chip which generates the date and time information this chip also usually contains the CMOS memory cells see next section You should be able to tell from the POST code description which is being tested Do not confuse any of these with the operating system clock DOS and Windows both keep track of the date and time but not until the system has successfully booted up 2 6 CMOS This is a section of non volatile memory meaning it holds its contents even when the computer is turned off because of a long life CMOS 21 Chapter 2 battery that provides it power A
138. t used during normal POST More Post Code Resources If you come across a code that is not in the table or a BIOS whose table is not included in Chapter 3 please check the following websites http bioscentral com http www shopctc com BiosHelp Biospostcodes MI htm http pchell com hardware beepcodes shtml http computerhope com beep htm http uktsupport co uk reference biosb htm If you are still unable to find the code please contact the Micro2000 Technical Support department We can help you determine the cause of the missing code and you can help us keep our BIOS listing up to date Chapter 2 Diagnostic Procedures Using The Codes Next to each of the POST Codes in Chapter 3 is a Diagnostic Code which refers to one of the sections of this chapter Here you will find a description of the part of the system that was being tested by that portion of the POST Where applicable there are also suggestions for further isolating the problem Appendix A has part numbers of some of the common motherboard chips for various functions to help you locate the specific component It does not always mean you should replace that particular component Most operations in the system require interaction from several components and each can appear to fail if not given correct data or signals from another part Also the PO ST may not halt on the section with the defect but on the one immediately before or after That
139. tch with CMOS Memory size check done To display soft error and check for password or bypass setup Password checked About to do programming before setup 87 Programming before setup complete To uncompress SETUP code and execute CMOS setup Retumed from CMOS setup program and screen is cleared About to do programming after setup E E 06 co 134 BIOS POST Code Listings Intel D815BN Runtime Continued Programming after setup complete G oing to display power on screen message 8B First screen message displayed WAIT message displayed PS 2 mouse check and extended BIO S data area allocation to be done m options programming after 5 setup about to oing to hard disk controller reset Hard disk controller reset done Floppy setup to be done next Floppy setup complete Hard disk setup done next Init of different buses optional RO Ms from C800 to start Going to do any init before C800 optional ROM control Any init before C800 optional ROM control is over Optional ROM check and control will be done next Optional ROM control is done About to give control to do any required processing after optional returns control and enable external cache Any initialization required after optional test over Going to setup timer data area and printer base address Return after setting timer and printer base addresses Going to set the RS 232 base address Returned after RS 232 base addre
140. ted so the series always starts with a long beep Phoenix ISA EISA Beep Code Failure 1 1 2 CPU Registers Low 1 1 2 System Board 1 1 3 CMOS 216 BIOS Beep Codes Phoenix ISA EISA MCA Continued Beep Code Low 1 1 3 1 1 4 1 2 1 1 2 2 1 2 3 1 3 1 1 3 2 1 3 3 1 3 4 1 4 1 1 4 2 1 4 3 1 4 4 2 1 1 2 1 2 2 1 3 2 1 4 2 2 1 2 2 2 2 2 3 2 2 4 2 3 1 2 3 2 2 3 3 2 3 4 2 4 1 2 4 2 2 4 3 2 4 4 3 1 1 3 1 2 3 1 3 Failure Extended CMO S RAM BIOSROM Checksum PIT Interrupt timer DMA Initialization DMA Page Register RAM Refresh First 64K B RAM First 64K B Data Line First 64K O dd Even Logic Address Line Failure First 64K B Parity Bus Timing Non maskable Interrupt Bit 0 First 64KB Bil Bit2 15215 Bi4 Bit Bito B Bit8 amp Bit9 Bit 10 Bit 11 Bit12 Bit13 Bit14 Bit15 Slave DMA Register Master DMA Register Master Interrupt Mask 217 Chapter 4 Phoenix ISA EISA MCA Continued Beep Code Failure 3 1 4 Slave Interrupt Mask 3 2 2 Interrupt Vector Error 3 2 3 OEM Reserved 3 2 4 Keyboard Controller 3 3 1 CMOS RAM 3 3 2 CMOS Configuration 3 3 3 OEM Reserved 3 3 4 Video Memory 3 4 1 Video Initialization 4 2 1 Timer Tick Failure 4 2 2 Shutdown Test 4 2 3 A 20 Line 4 2 4 Protected Mode Interrupt 4 3 1 RAM Address Failure 4 3 3 PIC 2 Failure 4 3 4 RTC Failure 4 4 1 Serial Port Test 4 4 2 Parallel
141. to be done Setup options programming after 5 setup about to 5 Going to hard disk controller reset Hard disk controller reset done Floppy setup done next Floppy setup complete Hard disk setup next Init of different buses optional RO Ms from 800 to start Going to do any init before C800 optional ROM control Any init before C800 optional ROM control is over Optional check and control will be done next Optional ROM control is done About to give control to do any required processing after optional RO M returns control and enable external cache Any initialization required after optional test over Going to setup timer data area and printer base address Return after setting timer and printer base addresses Going to set the RS 232 base address Returned after RS 232 base address G oing to do any initialization before coprocessor test Required initialization before coprocessor is over G oing to initialize the coprocessor test Coprocessor initialized G oing to do any initialization after coprocessor test Initialization after coprocessor test is complete G oing to check extended keyboard keyboard ID and num lock Going to display any soft errors Soft error display complete G oing to set keyboard typematic rate LAN 5 97 Eri 103 3 Intel 810 Runtime Code Continued Keyboard typematic rate set To program memory wait states Going to enabl
142. tra BIOS versions use a four digit POST code The first two digits will be displayed briefly on the POST Probe followed by the second two digits and then the sequence is repeated The code will also be sent to the monitor if the video circuitry is working If failure occurs during POST the BIOS will emit a 4beep error code regardless of the error IBM PS2 model 20 286 uses Port 190h PS2 model 25 amp 30 use Port 90h MCA systems use 680h The old IBM XT uses Port 60h which cannot be read by the POST Probe AT machines use the standard Port 80h There is also an extensive set of codes which will be sent to the monitor These are different than the bus codes displayed by the POST Probe and are listed in Appendix C Display of these assumes functioning video of course and may also require an IBM reference disk in the floppy A drive Phoenix This BIOS is used by a large number of ystem and motherboard manufacturers who are allowed to modify the BIOS to their own requirements Most of these will use Port 80h for reading the Post Codes Now that Phoenix has acquired A ward we can probably expect future versions of both to share the same standards 224 Chapter 6 IBM Error Messages IBM PC and PS 2 systems will display 6 digit error codes on the monitor screen for problems encountered during the Post If the errors appear at all it indicates that the video has been initialized and that a large portion of the hardware is there
143. ts and parameters of the system and generates the POST codes The BIOS also includes the boot loader see 4 2 4 1Boot Load As its last step the 5 will look for a bootable operating system and turn control of the CPU over to it Most commonly it will look first to the floppy drive and then to the hard drive If a boot load error occurs the BIOS has been unable to complete this function The most likely causes are hardware failure of the drive or a missing boot routine Before making any drastic repairs first remove any floppy diskettes and see if the system boots to the hard drive Then insert a floppy known to contain a boot loader and try booting again If neither works you might suspect a corrupt BIO 5 4 2 BIOS CHECKSUM When all of the data in the BIOS ROM is added up another figure is created called a checksum which will cause the total to roll over to all zeroes The POST does this addition all over again and a quantity other than zero indicates that one or more bits of the ROM code have 23 Chapter 2 changed and therefore the BIOS is corrupted Often corrupted BIOS will not get far enough into the POST to give this indication 4 3 Password A few BIOS versions will check to see if a password is stored in CMOS This is not necessarily a problem because the motherboard will usually have a switch or jumper that allows you to disable the password which you can re enter once the system has booted up 5 0
144. uck key found To issue keyboard controller interface test command Keyboard controller interface test over To write command byte and init circular buffer Command byte written global data init done To check for lock key E R Lock key checking over To check for memory size mismatch with CMOS Memory size check done To display soft error and check for password or bypass setup Password checked About to do programming before setup Programming before setup complete To uncompress SETUP code and execute CMOS setup 8 Returned from CMOS setup program and screen is cleared About to do programming after setup Programming after setup complete G oing to display power on screen message First screen message displayed lt WAIT gt message displayed PS 2 mouse check and extended BIO S data area allocation to be done Goingto do any init before C800 optional control oo co i 86 87 8D 95 96 188 BIOS POST Code Listings Intel RC440BX Runtime Continued 97 Any init before C800 optional ROM control is over Optional ROM check and control will be done next Optional ROM control is done About to give control to do any required processing after optional returns control and enable external cache Any initialization required after optional ROM test over Going to setup timer data area and printer base address 9A Return after setting timer and pri
145. ued A002 80287 Failed Stack Register R W Test 00 No Zero Divide Interrupt from 80287 CXYZ R W Error on Extended RAM in XY Bank CFFF Ext RAM Marching Ones Failure HP Vectra QS amp RS Post Diag Code Sect Description 22 12 42 25 25 26 26 8042 Failed to Accept Reset Command 8042 Failed to Respond To Reset 3 0337 068 0339 08 0338 E UT 0343 Keyboard Clock Line Stuck Low 0344 Keyboard Clock Line Stuck High 0345 0346 0550 0351 0352 0553 0354 7 0503 0505 0700 0701 0702 0703 0704 0707 0708 0709 90 0336 _ 0337 0838 0839 0538 OM 0342 0543 0344 0345 036 0350 0351 0352 053 054 0401 0503 0505 0700 0701 Do 0705 0704 0707 07086 0709 BIOS POST Code Listings HP Vectra OS RS Continued 3010 HP HIL Device Test Failed 5 1 Lower 640K Failed Read Write Test 0246 Y gt 0 Bad 023 Z gt 0 Bad U13 1 3 5 7 gt 0 U43 Z gt 0 Bad 033 E Co ro roa jr2o x S 54 8 gt 0 022 Z gt 0 Bad 012 9 Y gt 0 Bad 042 Z gt 0 Bad 032 Slave 8259 Failed Interrupt 6 5 Floppy Controller Error X Drive 0 1st Level Error 2 0 Unsuccessful Input from FD 1 Unsuccessful output to FDC 2 Error while executing seek 3 Error during recalibrate 4 Error verifying RAM buffer 5 Error while resetting FD C 6
146. uirements it is the purchaser s sole responsibility to determine the suitability of this product for his purposes 244 THE MANUFACTURER S SOLE OBLIGATION AND LIABILITY UNDER THIS WARRANTY IS LIMITED TO THE REPAIR OR REPLACEMENT OF A DEFECTIVE PRODUCT THE MANUFACTURER SHALL NOT IN ANY EVENT BE LIABLE TO THE PURCHASER OR ANY THIRD PARTY FOR ANY INCIDENTAL OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO DAMAGES RESULTING FROM INTERRUPTION OF SERVICE AND LOSS OF BUSINESS OR LIABILITY IN TORT RELATING TO THIS PRODUCT OR RESULTING FROM ITS USE OR POSSESSION 245 Notes 246 Notes 247
147. und and verified G oing to find out amount of memory above 1M B Amount of memory above 1M found and verified Check for soft reset and going to clear memory below 1M for soft reset If power on go to check point 4E N EJ 139 3 Intel 815 Runtime Continued 4 Memory below 1M cleared SOFT RESET Going to clear memory above 1M 4D Memory above 1M cleared SOFT RESET Going to save the memory size Go to check point 52 Memory test started NOT SOFT RESET About to display the first 64K B memory size Memory size display started This is updated during memory test G oing for sequential and random memory test 50 Memory testing initialization below 1MB complete 6 oing to adjust displayed memory size for relocation shadow 51 Memory size display adjusted due to relocation shadow Memory test above 1MB to follow 52 Memory testing initialization above 1MB complete G oing to save memory size information 53 Memory size information is saved CPU registers are saved Going to enter real mode 54 Shutdown successful CPU in real mode Going to disable gate A20 line and disable parity N MI 57 A20 address line parity disable successful Adjust memory size depending on relocation shadow 58 Memory size adjusted for relocation shadow oing to clear hit lt DEL gt message 59 Hit lt DEL gt message
148. urns control f EGA VGA not found then do display memory R W EGA VGA not found Display memory R W test about to begin Display memory R W test passed About to look for the retrace checking Display memory R W test or retrace checking failed To do alternate Display memory R W test Alternate Display memory R W test passed To look for the alternate display retrace checking Video display check over Display mode to be set next Display mode set G oing to display power on message Different buses init input IPL general devices to start if present 100 BIOS POST Code Listings Intel CA810E Runtime Code Continued 39 Display different buses initialization error messages 3A New cursor position read and saved To display the Hit lt DEL gt message To prepare the descriptor tables To enter virtual mode for memory test To enable interrupts for diagnostics mode To initialize data to check memory wrap around at 0 0 Data initialized oing to check for memory wrap around at 0 0 and finding the total system test memory Memory wrap around test done Memory size calculation over About to go for writing patterns to test memory Pattern to be tested written in extended memory G oing to write patterns in base 640K B memory Patterns written in base memory G oing to find out amount of memory below 1M memory Amount of memory below 1M found and verified G oing to find out amount of memory above 1M Amount of memo
149. usted for relocation shadow G oing to clear hit lt DEL gt message 59 Hit DEL message cleared WAIT message displayed About to start D MA and interrupt controller test BIOS POST Code Listings Intel D810E2CB Runtime Continued DMA page register test passed To do DMA 1 base register test DMA 1 base register test passed To do DMA 2 base register test DMA 2 base register test passed To program DMA 1 and 2 DMA 1 and 2 programming over To initialize 8259 interrupt controller Extended NMI sources enabling is in progress Keyboard test started Clearing output buffer checking for stuck key to issue keyboard reset command Keyboard reset error stuck key found To issue keyboard controller interface test command Keyboard controller interface test over To write command byte and init circular buffer Command byte written global data init done To check for lock key Lock key checking over To check for memory size mismatch with CMOS Memory size check done To display soft error and check for password or bypass setup Password checked About to do programming before setup 87 Programming before setup complete To uncompress SETUP code and execute CMOS setup 88 Returned from CMOS setup program and screen is cleared About to do programming after setup Programming after setup complete G oing to display power on screen message 8B First screen message displayed lt WATT gt message displa
150. very mode and to verify main checksum If in recovery mode or if main BIOS checksum is wrong go to checkpoint E0 for recovery Otherwise got o checkpoint D 7 to give control to main BIOS Find main BIOS module in ROM image Uncompress the main BIOS module Copy main BIO S image to F000 shadow and give control to main BIOS in F000 shadow RAM Intel D820LP Boot Block Recovery Post Code Description Onboard diskette controller if any is initialized Compressed recovery code is uncompressed at F000 0000 in shadow RAM Give control to recovery code at F000 in shadow RAM Initialize interrupt vector tables system timer DMA controller and interrupt controller Initialize extra Intel recovery module Initialize diskette drive EA Try to boot from diskette If reading of boot sector is successful give control to boot sector code EB Boot from diskette failed look for ATAPI LS 120 Zip devices EC Try to boot from ATAPI device If reading of boot sector is successful give control to boot sector code EF Boot from diskette and ATAPI device failed Give two beeps Retry the booting procedure go to checkpoint E9 150 BIOS POST Code Listings Intel D820LP Runtime Code U noompressed in F000 Shadow RA M Post Code Description POST code to be uncompressed CMOS checksum callo to be doneret 0B Any initialization before keyboard BAT to be done net 0 Keyboard cont
151. w E Uncompress SMBIOS module and init SMBIOS code and form the runtime SMBIOS image in shadow 1 Going to copy any code to specific area Copying of code to specific area done G oing to give control to Int19 boot loader Intel SE440BX 2 BIOS Uncompressed IN IT C ode C heck points Code Description 06 initialize system hardware 09 chipset with ina POST values 9 Set IN POST ag Enable CPU Initialize the local bus IDE 3 Intel SE 440BX 2 BIOS Continued gt Initialize PO ST dispatch manager Test CMOS RAM 5 Check ROM copyright notice _ 112 Initialize alternate chipset registers LN BIOS POST Code Listings Intel SE 440BX 2 BIOS Continued N gt Set key click if enabled 113 Initialize multiprocessor APIC F6 CE 8 NN 3 Intel SE 440BX 2 BIOS Continued c3 Setup power management 114 w ras LN 9 EN E EN BIOS POST Code Listings Intel SE 440BX 2 BIOS Continued Eri Clear global descriptor table Clean up all graphics Initialize D MI parameters 115 N 3 Intel SE 440BX 2 BIOS Continued gt Initialize boot Boot to mini DOS Boot to full DOS Intel D810E2CB BIOS Uncompressed IN IT Code C he points Post Code Description NMI is disabled O nboard keyboard controller and real ti
152. y R W test passed About to look for the retrace checking Display memory W test or retrace checking failed To do alternate D isplay memory R W test Alternate D isplay memory R W test passed To look for the alternate display retrace checking Video display checking over Display mode set next Display mode set G oing to display power on message Different buses init input IPL general devices to start if present Display different buses initialization error messages New cursor position read and saved To display the Hit DEL message Data initialized oing to check for memory wrap around at 0 0 and finding the total system test memory Memory wrap around test done Memory size calculation over About to go for writing patterns to test memory 107 28 3 Intel CC820 Runtime Code Continued Pattern to be tested written in extended memory Going to write patterns in base 640 memory 48 Patterns written in base memory G oing to find out amount of memory below 1M memory 9 Amount of memory below 1M found and verified Going to find out amount of memory above 1M 4B Amount of memory above 1M found and verified Check for soft reset and going to clear memory below 1M for soft reset If power on go to check point 4E 4 Memory below 1M cleared SOFT RESET G oing to clear memory above 1M AD Memory above 1M cleared SOFT RESET Going to save the memory size Go to check poin
153. y size display started This will be updated during the memory test Going for sequential and random memory test 50 Memory testing initialization below 1MB complete G oing to adjust displayed memory size for reallocation shadow 51 Memory size display adjusted due to reallocation shadow Memory test above 1MB to follow 52 Memory testing initialization above 1MB complete Going to save memory size information 3 Memory size information is saved CPU registers are saved Going to enter real mode 54 Shutdown successful CPU in real mode G oing to disable gate A20 line and disable parity N MI 57 A20 address line parity NMI disable successful oing to adjust memory size depending on reallocation shadow 58 Memory size adjusted for reallocation shadow G oing to clear Hit lt DEL gt message 59 Hit DEL message cleared lt WAIT gt message displayed About to start DMA and interrupt controller test DMA page register test passed To do D 1 base register 62 DMA 1 base register test passed To do DMA 2 base register test 3 Intel RC440BX Runtime Continued 65 DMA 2 base register test passed To program D MA unit 1 and 2 DMA unit 1 and 2 programming over To initialize 8259 interrupt controller Extended NMI sources enabling is in progress Keyboard test started Clearing output buffer checking for stuck key to issue keyboard reset command Keyboard reset error st
154. yed PS 2 mouse check and extended BIO 5 data area allocation to be done 8C Setup options programming after CMOS setup about to start 80 Going to hard disk controller reset 121 3 Intel D810E2CB Runtime Continued Hard disk controller reset done Floppy setup to be done next 1 Floppy setup complete Hard disk setup done next 5 Init of different buses optional RO Ms from 800 to start Going to do any init before C800 optional ROM control 97 Any init before C800 optional RO M control is over Optional check and control will be done next Optional ROM control is done About to give control to do any required processing after optional retums control and enable external cache Any initialization required after optional test over Going to setup timer data area and printer base address Retum after setting timer and printer base addresses Going to set the RS 232 base address Returned after RS 232 base address G oing to do any initialization before coprocessor test Required initialization before coprocessor is over Going to initialize the coprocessor test Coprocessor initialized G oing to do any initialization after coprocessor test Initialization after coprocessor test is complete G oing to check extended keyboard keyboard ID and num lock Going to display any soft errors Soft error display complete G oing to set keyboard typematic rate Keyboard typematic rate set To prog
155. yright Message Checksum 7 0 Check Video Configuration 7 0 7 0 3 0 Initialize Video Adapters CE 40 70 7 0 Display Press F2 to Enter Setup Size and Test Available Memory Base Memory Address Test al 4 80790 193 1 74 76 7 7 50 98 5 50 5 62 8 GE m 53 16 7A 5 0 5 0 5 0 5 0 2 2 2 2 5 5 0 2 5 8 3 3 0 2 3 3 Phoenix PCI BIOS Continued 80 82 Install RS232 Ports 84 Install Parallel Ports 86 88 Initialize Timeout and Reset Flags 8A 2 7 6 6 Initialize Mouse and Ext BIOS Data Area ic 92 9 96 9 9 A0 A2 A4 i A6 i A8 Disable A 20 Line Scan for ROM BIOS Extensions 4 Enable Hardware Interrupts Set Time Of Day AC AE Check for Setup 6 2 6 3 24 64 64 5 3 0 3 0 2 5 8 1 8 1 54 7 0 2 6 2 6 3 4 0 0 7 0 1 0 0 0 Clear 5 Flags Check for POST Errors 4 Set PO ST Complete Flag oO N i c3 B 4 B8 1 C0 D0 D D4 D6 DA 4 N 2 7 5 3 3 80 82 s 86 68 9A C 90 92 94 9698 A0 2 A4 A6 A8 AE BO B2 B4 B6 88 BA BC BE co D0 D2 D4 D6 DA 5 194 BIOS POST Code Listings Phoenix PCI BIOS UMC Chipset Post Diag Code Sect Description 05 217 Initaie
156. yte of memory bus first 4 meg 38 20 29 Post Memory Manager initialization 33 34 Ci 179 3 Initialize Power Management not used in Nightshade Read processor bus clock frequency and compute boot processor speed Initialize and register other CPU via SMM through APIC bus Initialize SMI handler for all processors Wait for secondary processor to execute init SMI handler Exit SMI handler secondary processor executed halt in SMI Initialize PnP bus and devices also read ESCD and allocate resources Check video configuration against CMOS VGA or MDA Initialize all video adapters in system Shadow video BIOS ROM Put CPU in big real mode flat mode memory addressing up to 4GB Post display manager initialization video screen error codes now visible Reset and test keyboard first try only warm reset gt gt LN LN w 180 BIOS POST Code Listings Intel NA440BX N440BX BIOS Continued 2 Reset and test keyboard controller both warm and cold reset Display prompt Press F2 to enter SETUP al CE F6 8 w 88 Initialize BIOS Data Area timeouts for detecting parallel serial and HDD controller Clear CMOS shutdown flag Initialize Extended BIO S D ata Area 1 Late POST core initialization Configure MCD devices 181 gt N 3 Intel NA440BX N440BX BIOS Continued 85 Initialize and detect PC

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