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Zerus Intel Desktop Board D815EEA (Z-D815EEA) Motherboard

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1. Q P Creative Labs ES1373 Digital Controller optional AD1885 audio codec optional AGP universal connector DVO connector Back panel connectors Intel 82815E Graphics and Memory Controller Hub GMCH Processor socket DIMM sockets Power connector Diskette drive connector O NML K K L M N O P Q R S T U OM10041 IDE connectors Serial port B connector Intel 82801BA I O Controller Hub ICH2 SMSC LPC47M102 I O Controller Front panel connectors Intel 82802AB 4 Mbit Firmware Hub FWH Battery Front panel USB connector Speaker PCI bus add in card connectors Communication and Networking Riser CNR connector optional Figure 1 D815EEA Board Components 1 1 4 Block Diagram Product Description Figure 2 is a block diagram of the major functional areas of the D815EEA board Primary Secondary IDE lt ATA 33 66 100 Diagnostic y LEDs USB gt USB Ports 0 and 1 y
2. B31 Signal Name 12V Ground TCK Ground no connect TDO 5 V 5 V INTB INTD no connect PRSNT1 Reserved no connect PRSNT2 Ground Ground Reserved Ground CLK Ground REQ 5 V I O AD31 AD29 Ground AD27 AD25 3 3 V C BE3 AD23 Ground AD21 AD19 3 3 V Pin A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 Signal Name AD16 3 3 V FRAME Ground TRDY Ground STOP 3 3 V Reserved Reserved Ground PAR AD15 3 3 V AD13 AD11 Ground ADO9 Key Key C BEO 3 3 V ADO6 AD04 Ground AD02 ADOO 5 V I O REQ64C 5 V 5 V On PCI bus connector 2 J4D1 this pin is connected to the SMBus clock line On PCI bus connector 2 J4D1 this pin is connected to the SMBus data line Pin Signal Name B32 AD17 B33 C BE2 B34 Ground B35 IRDY B36 3 3 V B37 DEVSEL B38 Ground B39 LOCK B40 PERR B41 3 3V B42 SERR B43 3 3 V B44 C BE1 B45 AD14 B46 Ground B47 AD12 B48 AD10 B49 Ground B50 _ Key B51 Key B52 AD08 B53 AD07 B54 3 3 V B55 AD05 B56 AD03 B57 Ground B58 ADO1 B59 5 V I O B60 ACK64C D I 5V B62 5V These signals in parentheses are optional in the PCI specification and are not currently implemented 65 Intel Desktop B
3. e E ch oom D E F G BERN a 1 1 mooo mooo p EWEN a oon L 1moo00 1 mooo HOO n 1 Oo o OO 0O O O0 0O J l0 11 O O O O O O O O O 0O 20 K J l H OM10044 Item Description Color Reference Designator For more information see A Chassis Fan Fan 2 N A J3F1 Table 28 B CD ROM Legacy style 2 mm White J2F2 Table 29 C ATAPI CD ROM Black J2F1 Table 30 D Auxiliary line in ATAPI style White J2G1 Table 31 E Telephony ATAPI style Green J2G2 Table 32 F Digital video out N A J3H1 Table 33 G Processor fan Fan 3 N A J3M1 Table 34 H Power N A J8K1 Table 35 l Wake on LAN technology N A J6B1 Table 36 J Chassis intrusion N A J7B1 Table 37 K Chassis fan Fan 1 N A J8B1 Table 38 Figure 10 Audio Video Hardware Control and Fan Connectors 59 For information about Intel Desktop Board D815EEA Technical Product Specification Refer to The power connector Section 1 13 2 1 page 43 The functions of the fan connectors Section 1 13 2 2 page 43 Wake on LAN technology Section 1 13 2 3 page 44 Table
4. Power supply fan Provides 12 V DC for a system or chassis fan The fan voltage can be switched control fan 2 on or off depending on the power management state of the computer A tachometer feedback connection is also provided Processor fan fan 3 Provides 12 V DC for a processor fan or active fan heatsink 43 Intel Desktop Board D815EEA Technical Product Specification For information about Refer to The location of the fan connectors Figure 10 page 59 The signal names of the fan connectors Section 2 8 2 2 page 59 1 13 2 3 Wake on LAN Technology A CAUTION 44 For Wake on LAN technology the 5 V standby line for the power supply must be capable of providing adequate 5 V standby current Failure to provide adequate standby current when implementing Wake on LAN technology can damage the power supply Refer to Section 2 11 3 on page 78 for additional information Wake on LAN technology enables remote wakeup of the computer through a network The LAN subsystem PCI bus network adapter monitors network traffic at the Media Independent Interface Upon detecting a Magic Packett frame the LAN subsystem asserts a wakeup signal that powers up the computer Depending on the LAN implementation the D815EEA board supports Wake on LAN technology in the following ways e Through the Wake on LAN technology connector APM only e Through the PCI bus PME signal for PCI 2 2 compliant LAN designs ACPI only e Thro
5. 109 Intel Desktop Board D815EEA Technical Product Specification 4 4 6 Event Log Configuration Submenu 110 To access this menu select Advanced on the menu bar then Event Log Configuration Maintenance Main Advanced Security Power Boot Bag PCI Configuration Boot Configuration Periphera Configuration IDE Configuration Diskette Configuration Event Log Configuration Video Configuration The submenu represented by Table 72 is used to configure the event logging features Table 72 Event Log Configuration Submenu Feature Options Description Event log No options Indicates if there is space available in the event log Event log validity No options Indicates if the contents of the event log are valid View event log Enter Displays the event log Clear all event logs e No default Clears the event log after rebooting e Yes Event Logging e Disabled Enables logging of events e Enabled default Mark events as read Enter Marks all events as read BIOS Setup Program 4 4 7 Video Configuration Submenu To access this menu select Advanced on the menu bar then Video Configuration Maintenance Main Advanced Security Power Boot Bast PCI Configuration Boot Configuration Peripheral Configuration IDE Configuration Diskette Configuration Event Log Configuration Video Configurati
6. 8042 GateA20 cannot be toggled Exception interrupt error Display memory R W error Not used 0 N oO A Q N 0 CMOS Shutdown register test error 1 Invalid BIOS e g POST module not found etc 5 6 Diagnostic LEDs The enhanced diagnostics feature consists of a hardware decoder and four LEDs located between the audio connectors and the serial port connector on the back panel This feature requires no modifications to the chassis other than I O back panel shield or cabling Figure 17 shows the location of the diagnostic LEDs Table 87 lists the diagnostic codes displayed by the LEDs OM10051 Figure 17 Diagnostic LEDs 125 Intel Desktop Board D815EEA Technical Product Specification Table 87 Diagnostic LED Codes Display BIOS Operation Display BIOS Operation QO Amber Power on starting BIOS Amber Undefined O Amber O Amber O Amber O Amber Q Amber Green Green Recovery mode Green Undefined O Amber O Amber
7. Pin OO CO N o a lt WO N Signal Name DCD Data Carrier Detect RXD Receive Data TXD Transmit Data DTR Data Terminal Ready Ground DSR Data Set Ready RTS Request to Send CTS Clear to Send RI Ring Indicator Technical Reference Table 24 MIDI Game Port Connector Pin Signal Name Pin Signal Name 1 5 V fused o 9 5 V fused 2 JOYA 110 JOY6 3 JOYTIMEO 11 JOYTIME2 4 Ground sti 2 MIDI OUT 5 Ground 13 JOYTIME3 6 JOYTIME1 14 JOY7 7 JOY5 15 MIDI IN 8 5 V fused Table 25 Audio Line Out Connector Pin Signal Name Tip Audio left out Ring Audio right out Sleeve Ground Table 26 Audio Line In Connector Pin Signal Name Tip Audio left in Ring Audio right in Sleeve Ground Table 27 Mic In Connector Pin Signal Name Tip Mono in Ring Mic bias voltage Sleeve Ground 57 Intel Desktop Board D815EEA Technical Product Specification 2 8 2 2 8 2 1 lt gt NOTE 58 Internal UO Connectors The internal I O connectors are divided into the following functional groups e Audio video power and hardware control see page 59 ATAPI CD ROM Legacy style 2 mm CD ROM Telephony Auxiliary line in Digital video out Fans 3 Power Chassis intrusion Wake on LAN technology e Add in boards and peripheral interfaces see page 62 CNR communication and networking riser PCI bus 5 AGP Universal IDE 2 Diskette drive Expansion Slots The b
8. Power Boot Exit IDE Drive Configuration The menu represented in Table 76 is used to set the boot features and the boot sequence Table 76 Boot Menu Feature Quiet Boot Intel Rapid BIOS Boot Options e Disabled Enabled default Disabled Enabled default Description Disabled displays normal POST messages Enabled displays OEM graphic instead of POST messages Enables the computer to boot without running certain POST tests Scan User Flash Area After Power Failure Disabled default Enabled Stay Off Last State default Power On Enables the BIOS to scan the flash memory for user binary files that are executed at boot time Specifies the mode of operation if an AC power loss occurs Stay Off keeps the power off until the power button is pressed Last State restores the previous power state before power loss occurred Power On restores power to the computer On Modem Ring Stay Off default Power On In APM mode only specifies how the computer responds to an incoming call on an installed modem when the power is off 2 Boot Device 3 Boot Device 4 Boot Device ARMD FDD Note 1 ARMD HDD Note 2 IDE HDD Note 3 ATAPI CDROM Intel UNDI PXE 2 0 Note 4 Disabled On LAN Stay Off In APM mode only determines how the system responds to a Power On default LAN wake up event On PME Stay Off default In APM mode only determines ho
9. 91 Floppy setup complete Hard disk setup to be done next 95 Init of different buses optional ROMs from C800 to start See Section 5 3 for details of different buses 96 Going to do any init before C800 optional ROM control 97 Any init before C800 optional ROM control is over Optional ROM check and control will be done next 98 Optional ROM control is done About to give control to do any required processing after optional ROM returns control and enable external cache 99 Any initialization required after optional ROM test over Going to setup timer data area and printer base address 9A Return after setting timer and printer base address Going to set the RS 232 base address 9B Returned after RS 232 base address Going to do any initialization before Coprocessor test 9C Required initialization before Coprocessor is over Going to initialize the Coprocessor next 9D Coprocessor initialized Going to do any initialization after Coprocessor test 9E Initialization after Coprocessor test is complete Going to check extended keyboard keyboard ID and num lock A2 Going to display any soft errors A3 Soft error display complete Going to set keyboard typematic rate A4 Keyboard typematic rate set To program memory wait states A5 Going to enable parity NMI A7 NMI and parity enabled Going to do any initialization required before giving control to optional ROM at E000 A8 Initialization before E000 ROM control over
10. Amber O Amber Q Amber Green O Amber Processor cache etc O Amber Undefined oO Green O Green O Amber O Amber Q Amber O Green Green Memory auto size shadow Green Undefined Green etc ei Green Q Amber QO Amber Q Amber Green Amber PCI bus initialization Q Amber Undefined O Amber O Amber J Green Green Q Amber Green Green Video Green Undefined O Amber QO Amber Green Green Amber Green Amber IDE bus initialization QO Amber Undefined Green Green J Green Green Amber O Green Green USB initialization Green Booting operating system Green Green Green Green Q Amber Green Note Undefined states are reserved for future use SCH NOTE After the computer has booted the diagnostic LEDs remain off during normal operation 126
11. kanek kule 57 MiG II GONME GION A yel ae k a den sant H RE RR tiem a KEYE aces eee ne K n ds 57 Chassis Fan Connector J3F1 EE 60 CD ROM Legacy Style Connector GIE 60 ATAPI CD ROM Connector J2 FT EEE E kk Sgr 60 Auxiliary Line In Connector LD ENNEN 60 Telephony Connector J20G2 uE ek kk eR gett KA KK KK YA 60 Digital Video Out Connector JS3 HT iiiiii kk kk kK kK kk 61 Processor Fan Connector GSM eebe kk kk es 61 Power Connector J8K1 E iii kk kek kk K k K k KK KK KAKA KK K 61 Wake on LAN Technology Connector LIP 62 Chassis Intrusion Connector RUE aseene dee abet 62 Chassis Fan Connector A EE 62 CNR Connector 3A1 l n x nl kaliy e Re E e E baie ieee 64 PCI Bus Connectors J4A1 J4B1 J4C1 J4D1 JE 65 Contents AGP Universal Connector EE 66 Diskette Drive Connector J8G3 ENEE 67 PCI IDE Connectors J8G2 Primary and J6G1 Secondary sssssssseeeneeeseerrneeesee 68 Front Panel USB Connector ON EE 70 Serial Port B Connector Eh EE 70 SCSI LED Connector JZAT anne e n K kak Ek hek Ker n h kela kek ae 70 Auxiliary Front Panel Power LED Connector LC 70 Front Panel Connector dS CS cues ods Needs Vacant kk kk kk kK kk kK kk KK 71 States for a Single Colored Power LEID 72 States for a Dual Colored Power LED ANEN 72 BIOS Setup Configuration Jumper Settings U7B1 u 74 Power Usage For Board with Basic Audio and Onboard LA
12. 3 3 V 12 12V 3 Ground 13 Ground 4 5 V 14 PS ON power supply remote on off 5 Ground 15 Ground 6 5 V 16 Ground 7 Ground 17 Ground 8 PWRGD Power Good 18 TP_PWRCONN_18 9 5 V Standby 19 5 V 10 12 V 20 5 V 61 Intel Desktop Board D815EEA Technical Product Specification Table 36 Wake on LAN Technology Connector J6B1 Pin Signal Name 1 5 VSB Ground WOL Table 37 Chassis Intrusion Connector J7B1 Pin Signal Name 1 INTRUDER 2 Ground Table 38 Chassis Fan Connector J8B1 Pin Signal Name FAN1_PWM 12 V FAN1_TACH For information about The power connector The functions of the fan connectors Wake on LAN technology 62 Refer to Section 1 13 2 1 page 43 Section 1 13 2 2 page 43 Section 1 13 2 3 page 44 Technical Reference 2 8 2 3 Add in Board and Peripheral Interface Connectors Figure 11 shows the location of the add in board connector and peripheral connectors Note the following considerations for the PCI bus connectors All of the PCI bus connectors are bus master capable PCI bus connector 2 has SMBus signals routed to it This enables PCI bus add in boards with SMBus support to access sensor data on the board The specific SMBus signals are as follows The SMBus clock line is connected to pin A40 The SMBus data line is connected to pin A41 Item gt CT TO TI II O w B C
13. Notes 1 and 2 128 MB Ss 128 Mbit 16 M X 8 empty 8 128 MB SS 256 Mbit 16 M X 16 empty 4 192 MB DS 128 Mbit 16MX8 8Mx16 12 Notes 1 and 2 192 MB DS 128 64 Mbit 16MX8 8Mx8 16 Notes 1 and 2 256 MB DS 128 Mbit 16MX8 16MX8 16 Notes 1 and 2 256 MB DS 256 Mbit 16MX16 16MX16 8 Notes 1 and 2 256 MB SS 256 Mbit 32 M X 8 empty 8 512 MB DS 256 Mbit 32M X 8 32 M X 8 16 Notes 1 and 2 Notes 1 If the number of SDRAM devices is greater than nine the DIMM will be double sided 2 Front side population back side population indicated for SDRAM density and SDRAM organization A CAUTION To be fully compliant with all applicable Intel SDRAM memory specifications the motherboard should be populated with DIMMs that support the Serial Presence Detect SPD data structure If your memory modules do not support SPD you will see a notification to this effect on the screen at power up The BIOS will attempt to configure the memory controller for normal operation However DIMMs may not function under the determined frequency You can access the PC Serial Presence Detect Specification at http www intel com design pcisets memory 21 Intel Desktop Board D815EEA Technical Product Specification 1 6 Intel 815E Chipset 22 The Intel 815E chipset consists of the following devices e 82815E Graphics and Memory Controller Hub GMCH with Accelerated Hub Architecture AHA bus e 82801BA I O Controller Hub ICH2 with AHA bus e
14. The standby mode can be initiated in the following ways e Time out period specified in the BIOS Setup program e From the operating system such as the Standby menu item in Windows 98 In standby mode the D815EEA board can reduce power consumption by spinning down hard drives and reducing power to or turning off of VESAt DPMS compliant monitors Power management mode can be enabled or disabled in the BIOS Setup program While in standby mode the system retains the ability to respond to external interrupts and service requests such as incoming faxes or network messages Any keyboard or mouse activity brings the system out of standby mode and immediately restores power to the monitor 39 Intel Desktop Board D815EEA Technical Product Specification The BIOS enables APM by default but the operating system must support an APM driver for the power management features to work For example Windows 98 supports the power management features upon detecting that APM is enabled in the BIOS For information about Refer to Enabling or disabling power management in the BIOS Setup program Section 4 6 page 112 The D815EEA board s compliance level with APM Table 3 page 16 1 13 1 2 ACPI 40 ACPI gives the operating system direct control over the power management and Plug and Play functions of a computer The use of ACPI with the D815EEA board requires an operating system that provides full ACPI support ACPI features include e Pl
15. cascade interrupt from slave PIC 3 COM2 Note 4 COM1 Note 5 LPT2 Plug and Play option Audio User available 6 Diskette drive 7 LPT1 Note 8 Real time clock 9 Reserved for ICH system management bus 10 User available 11 User available 12 Onboard mouse port if present else user available 13 Reserved math coprocessor 14 Primary IDE if present else user available 15 Secondary IDE if present else user available Note Default but can be changed to another IRQ PCI Interrupt Routing Map This section describes interrupt sharing and how the interrupt signals are connected between the PCI bus connectors and onboard PCI devices The PCI specification specifies how interrupts can be shared between devices attached to the PCI bus In most cases the small amount of latency added by interrupt sharing does not affect the operation or throughput of the devices In some special cases where maximum performance is needed from a device a PCI device should not share an interrupt with other PCI devices Use the following information to avoid sharing an interrupt with a PCI add in card PCI devices are categorized as follows to specify their interrupt grouping e INTA By default all add in cards that require only one interrupt are in this category For almost all cards that require more than one interrupt the first interrupt on the card is also classified as INTA e INTB Generally the second interrupt on add in cards that req
16. 1 7 1 SU Mell MONG a thee EE a OPN eee EEN 26 1 7 2 Intrared SUpport EE 26 1 7 3 Parallels Gu EE 27 1 7 4 Diskette Drive Controller LE dens omesaeedaciiatedeasaseabeideadendecd lone 27 1 7 5 Keyboard and Mouse Interface E kk e 27 1 8 Graphics Subsystem EEE EEE kk kk ke kK KK KK a KK 28 1 8 1 Integrated Graphics Controller AAA 28 1 8 2 Digital Video Output DVO Connector eect eee eeeeteeeeeeeeeeeeteeeeeeeeeees 30 1 8 3 AGP Universal Connector ccc etic hed Ek cee 31 1 9 e See EE 32 1 9 1 Basic Audio e EE 32 1 9 2 Enhanced PCI Audio Subsystem EE kk kk kk kK 33 19 3 Audio COMMECLO S EE 34 1 10 LAN EE EE 35 1 10 1 Intel 82562ET Platform LAN Connect Device Optional 36 1 10 2 RAR LAN Connector LEDs REENEN 36 1 10 3 LAN Subsystem Gottware ANNE 36 Lk INI ODEON ccs tes cilia did A An std rin k cease Ee GE 36 Hardware Management Subsystem Optional E eke 37 1 12 1 Hardware Monitor Component uk 38 1 12 2 Chassis Intrusion Detect Connector ENEE 38 1 12 3 Fan Control and Monitoring E EEEEE kk kk kk K k ek 38 1 13 Power Management EEE kek kek kk k K k ke kK KK KK KK Kr kk KH 39 1 1 3 1 S flware SUBDOL EEN 39 1 13 2 Hardware Support ste Seton osc eebe eat kK terete eg 42 Intel Desktop Board D815EEA Technical Product Specification 2 Technical Reference vi 2 1 Introd
17. 78 for additional information System integrators should refer to the power usage values listed in Section 2 11 1 on page 77 when selecting a power supply for use with the D815EEA board Measurements account only for current sourced by the D815EEA board while running in idle modes of the started operating systems Additional power required will depend on configurations chosen by the integrator The power supply must comply with the following recommendations found in the indicated sections of the ATX form factor specification e The potential relation between 3 3 VDC and 5 VDC power rails Section 4 2 e The current capability of the 5 VSB line Section 4 2 1 2 e All timing parameters Section 4 2 1 3 e All voltage tolerances Section 4 2 2 For information about _Refer to The ATX form factor specification l Section 1 3 page 16 2 12 Thermal Considerations A 80 CAUTION An ambient temperature that exceeds the board s maximum operating temperature by 5 C to 10 C could cause components to exceed their maximum case temperature and malfunction For information about the maximum operating temperature see the environmental specifications in Section 2 14 Technical Reference Jh CAUTION The processor voltage regulator area item A in Figure 16 can reach a temperature of up to 85 C in an open chassis System integrators should ensure that proper airflow is maintained in the voltage regulator circuit Failure to do s
18. 815E Chipset y Y Y SDRAM Bus S E Pr 82801BA 82802AB Saupe e KN UO Controller Hub wk Firmware Hub Memory Controller Bus ICH2 A EWH EE Hub GMCH DIMM j Banks A A AAA A 3 LPC Bus _ DVO Digital video Diskette Drive Connector output Connector daer l Serial Port A AGP Serial Port B niversal a AP Display Cache ae Ae Parallel Port TE Interface ontroller La Gaz Mouse ie l lt PS 2 Keyboard Hardware gt erm n lll act alte ne eg Zeen Monitor j SMBus i Optional i Optional Analog Codec l gt l PCI Bus x AG Lins CNR l Connector SEI Ster CSMAICD Physical gt w y ya 2 Unit gt Layer lt gt Connector i Interface Interface E Evana nak Ge Ga Raz eo SE ER EG NER SER en KER SESI SEN Wan ae z kab PCI Slot 4 l Optional SE CD ROM PCI Slot 5 la Line In J i SERGE AC 97 gt Audio Digital AC Link Audio Line Out Controller Cod Mic In odece Auxiliary Line In I a Telephony eS AA ent a SD th SS EE a Sh te ai l OM10090 Figure 2 Block Diagram 15 Intel Desktop Board D815EEA Technical Product Specification 1 2 1 3 Online Support Find information about the Intel D815EEA board under Product Info or Customer Support at these World Wide Web sites http www intel com design motherbd htt
19. Advanced on the menu bar then IDE Configuration and then the master or slave to be configured Maintenance Main Advanced Security Power Boot EW PCI Configuration Boot Configuration Peripheral Configuration IDE Configuration Primary IDE Master Primary IDE Slave Secondary IDE Master Secondary IDE Slave Diskette Configuration Event Log Configuration Video Configuration There are four IDE submenus primary master primary slave secondary master and secondary slave Table 70 shows the format of the IDE submenus For brevity only one example is shown Table 70 Primary Secondary IDE Master Slave Submenus Feature Options Description Drive Installed None Displays the type of drive installed Type e None Specifies the IDE configuration mode for IDE devices e User User allows capabilities to be changed e Auto default Auto fills in capabilities from ATA ATAPI device e CD ROM e ATAPI Removable e Other ATAPI e IDE Removable Maximum Capacity None Displays the capacity of the drive LBA Mode Control e Disabled Enables or disables LBA mode control e Enabled default Multi Sector Transfers e Disabled Specifies number of sectors per block for transfers from e 2 Sectors the hard disk drive to memory e 4 Sectors Check the hard disk drive s specifications for optimum setting 8 Sectors 16 Sectors default continued 107 Intel Desktop Board D815EEA Te
20. CMOS in every boot is set or lt END gt key is pressed Going to disable DMA and Interrupt controllers 13 Video display is disabled and port B is initialized Chipset init about to begin 14 8254 timer test about to start 19 About to start memory refresh test 1A Memory Refresh line is toggling Going to check 15 us ON OFF time 23 To read 8042 input port and disable Megakey GreenPC feature Make BIOS code segment writeable 24 To do any setup before Int vector init 25 Interrupt vector initialization to begin To clear password if necessary 27 Any initialization before setting video mode to be done 28 Going for monochrome mode and color mode setting 2A Different buses init system static output devices to start if present See Section 5 3 for details of different buses 2B To give control for any setup required before optional video ROM check 2C To look for optional video ROM and give conirol 2D To give control to do any processing after video ROM returns control 2E If EGA VGA not found then do display memory R W test 2F EGA VGA not found Display memory R W test about to begin 30 Display memory R W test passed About to look for the retrace checking 31 Display memory R W test or retrace checking failed To do alternate Display memory R W test 32 Alternate Display memory R W test passed To look for the alternate display retrace checking 34 Video display checking over Display mode
21. Code Checkpoint EL EEN 119 Runtime Code Uncompressed in F000 Shadow RAM uzm eke 120 Bus Initialization Checkpoints eege tes Rene aPandchernoa tenes kk kk k k k kk kk kk KH 123 Upper Nibble High Byte Functions eee ee ee ee kk kk kk K k KK kk kk KK KK KA 123 Lower Nibble High Byte Functions kee 124 BECP COC CS ege Seege EE 125 Diagnostic LED EE teren ee kek kk kk kk K k ke kk Seege Geh 126 Intel Desktop Board D815EEA Technical Product Specification 1 Product Description What This Chapter Contains nak sch sesch sch sch sech sesch sesch sc ch sesch sch sch A 2 ch 2 OD OO N O Ob G hi A Q N O VIN Me de Ee e dee Ee heen 12 Online SUPP EE 16 Bel EE ee e EE 16 Processorn eebe ain bat tated eebe otha et ae 19 System Memory EE 20 Intel 815E Chipset EE 22 VO C ntroler vm e mm m E E a R 26 Graphics Subsystem EE 28 Audio Subsystem Optional EE Ek kk kk kk KK KK KK KK kK 32 LAN SUBSYSt6 EE 35 CNR Optional aleren naear k ya ke gep kan bene een E 36 Hardware Management Subsystem Optional ke 37 Power Management EE 39 Intel Desktop Board D815EEA Technical Product Specification 1 1 Overview 1 1 1 12 Feature Summary Table 1 summarizes the D815EEA board s major features Table 1 Feature Summary Form Factor Processor Memory Chipset UO Control Video ATX 12 0 inches by 8 2 inches Support
22. D Q e BEE M Hn EN e oooo000000 BII 40 goooooo0o0o000000000000 39 DIHEJ ooooo000000 40 goooooooo0o0o0000000000 39 20 Conoonoodsogoo ss J l H OM10045 Description Reference Designator For more information see Communication and networking riser CNR J3A1 Table 39 PCI bus connector 5 J4A1 Table 40 PCI bus connector A J4B1 Table 40 PCI bus connector 3 J4C1 Table 40 PCI bus connector 2 J4D1 Table 40 PCI bus connector 1 J4E1 Table 40 AGP universal connector J5E1 Table 41 Diskette drive J8G3 Table 42 Primary IDE J8G2 Table 43 Secondary IDE J8G1 Table 43 Figure 11 Add in Board and Peripheral Interface Connectors 63 Intel Desktop Board D815EEA Technical Product Specification Table 39 CNR Connector J3A1 Pin Signal Name Pin Signal Name Al Reserved B1 Reserved A2 Reserved B2 Reserved A3 Ground B3 Reserved A4 Reserved B4 Ground A5 Reserved B5 Reserved A6 Ground B6 Reserved A7 LAN_TXD2 B7 Ground A8 LAN_TXDO A9 Ground B8 LAN_TXD1 B
23. The maintenance menu is displayed The BIOS attempts to recover the BIOS configuration A recovery diskette is required Refer to Section 4 1 page 97 The maintenance menu of the BIOS Setup program Section 4 2 page 98 Section 3 7 page 91 Technical Reference 2 10 Mechanical Considerations 2 10 1 Form Factor The D815EEA board is designed to fit into an ATX form factor chassis Figure 14 illustrates the mechanical form factor for the D815EEA board Dimensions are given in inches millimeters The outer dimensions are 8 20 inches by 12 00 inches 208 20 millimeters by 304 80 millimeters Location of the I O connectors and mounting holes are in compliance with the ATX specification see Section 1 3 3 10 78 74 0 40 10 16 GE 0 00 a i N toca 0 90 22 86 nn ie eee y L m m n C 6 10 154 94 42 J S j 7 80 198 12 0 65 16 51 L 11 35 288 29 0 00 4 90 124 46 11 10 281 94 OM10048 Figure 14 D815EEA Board Dimensions 75 Intel Desktop Board D815EEA Technical Product Specification 2 10 2 I O Shield The back panel I O shield for the D815EE
24. access the computer Detects incoming call similarly for external and internal modems Requires modem interrupt be unmasked for correct operation 1 13 2 6 Wake from USB USB bus activity wakes the computer from an ACPI S1 or S3 state lt gt NOTE Wake from USB requires the use of a USB peripheral that supports Wake from USB 1 13 2 7 Wake from PS 2 Keyboard PS 2 keyboard activity wakes the computer from an ACPI S1 or S3 state 1 13 2 8 PME Wakeup Support When the PME signal on the PCI bus is asserted the computer wakes from an ACPI S1 or S3 state 46 2 Technical Reference What This Chapter Contains 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 IATROCUCTION WEE 47 Memty Map dereer r ee aake ee EEEE eterna dei REEERE 47 eg Oe 48 DMA En 50 PCI Configuration Space Map EE 50 Interrupts ed e aaa ar ant ele deter da EE OAE E OER 51 PCI Interrupt Routing Map mmm See dE Ee AEN kk k K k Ee 51 elle EEN 53 SUE o a yad eege tet OU em ae ite DN sele ar 73 Mechanical Considerations ccccccccccccceeceeeecseeececeeeeeueuseeeuuueeeeueeeuaueeueeeeaueeenaneenenss 75 Electrical COnSiderations 4 4 xax raxa did ya Milk xa l xa kek e AA kane aa n de al Ran iaaa aa Rat 77 Thermal Consideraiions lk ke keka ak ela ka ake kak ka kake kak ka kak kek ka k kk ka 80 SIE ei EE ER KOIANEI EE EE 83 Regulatory Compliance ak egee geed ENEE en 84 2 1 Introduction Section
25. and running the power on self test POST 27 Intel Desktop Board D815EEA Technical Product Specification For information about Refer to The location of the keyboard and mouse connectors Figure 9 page 54 The signal names of the keyboard and mouse connectors Table 18 page 55 1 8 Graphics Subsystem The 815E chipset contains two separate mutually exclusive graphics options Either the integrated graphics controller contained within the 82815E GMCH is used or an add in AGP adapter can be used The GMCH includes an integrated display cache SDRAM controller that supports a Graphics Performance Accelerator GPA card The GPA card is a 32 bit 133 MHz 4 MB SDRAM array for enhanced integrated 2D and 3D graphics performance This interface is multiplexed between the display cache interface and the AGP connector When an AGP card is installed the integrated graphics controller is disabled and the display cache interface is not used For information about Refer to GPA support Section 1 8 3 1 page 31 1 8 1 Integrated Graphics Controller 28 The GMCH features the following e Integrated graphics controller 3 D Hyper pipelined architecture Full 2 D hardware acceleration Motion video acceleration e 3 D graphics visual and texturing enhancement e Display Integrated 24 bit 230 MHz RAMDAC Display Data Channel Standard Version 3 0 Level 2B protocols compliant e Video Hardware motion compensation
26. can be AC power is except when performed disconnected provided by from the battery or external computer source Notes 1 Total system power is dependent on the system configuration including add in boards and peripherals powered by the system chassis power supply 2 Dependent on the standby power consumption of wake up devices used in the system 41 Intel Desktop Board D815EEA Technical Product Specification 1 13 1 2 2 Wake Up Devices and Events Table 10 lists the devices or specific events that can wake the computer from specific states Table 10 Wake Up Devices and Events These devices events can wake up the computer from this state Power switch S1 S3 S5 RTCalam 4 3 5 LAN S1 S3 S5 Note PME S1 S3 S5 Note Modem back panel Serial Port A S1 S3 TIRcommad TSS USB S1 S3 PS 2 keyboard S1 S3 Note For LAN and PME S5 is disabled by default in the BIOS Setup program Setting this option to Power On will enable a wake up event from LAN in the S5 state lt gt NOTE The use of these wake up events from an ACPI state requires an operating system that provides full ACPI support In addition software drivers and peripherals must fully support ACPI wake events 1 13 1 2 3 Plug and Play In addition to power management ACPI provides controls and information so that the operating system can facilitate Plug and Play device enumeration and configuration ACPI is used only
27. ctioM ceiee sc ka en DR Sine N QAR KN k ka KER HON E CA KAK ee cae asta E KE Wer K M cai ed 47 Be Ee EE 47 23 WINN DEE 48 2A DMA Channels js kd siy yine Eege 50 2 5 PCI Configuration Space Map Em kk kk kk edie kK KK KK EEN 50 20 Interrupts ee ee eebe 51 2 7 PCI Interrupt Routing Map EE 51 ZU CON OCOS Eet eebe SEA 53 2 8 1 Back lee Ee 54 2 8 2 Internal I O Ke le 58 2 8 3 External I O Connectors eege Seege 69 249 J mpel BIOOK EE 73 2 10 Mechanical ConsideratliOnS EEE lates eed kk kk KK KK K k KK KK 75 2 40 41 Form Fatores e E A E E E aE e oea 75 7204s 10 2 Jl O ET WER 76 2 11 Electrical Considerations EEN 77 ZAI Power EIER ee S ee AVA ies ote s nd MEVA C N k kn ERA K 77 2 11 2 Add in Board Consideratons kk kek kk kK K 78 2 11 3 Standby Current RequiremenS kk kk kk ke H 78 2 11 4 Fan Connector Current Capability E EEL 79 2 11 5 Power Supply Considerattons ANNE 80 GAEREN ee EE 80 PAD PROMI NNN MMIDMMMMMMIMNMDMMDMMMMMMMMN E EHRa aa eae ne 82 2 14 Environmental srren elya kanya h darik n AR Neh kr KEK ARA Hae h HAA K n L SK REK EES 83 2 15 Regulatory el Ein 84 2 15 1 Safety e EE le 84 215 2 EMG e DE E eo n r lan b y derbirin e kada Lb eyaz bken E 84 2 15 3 Certification AEN le Le GE 85 Overview of BIOS Features Bed e ee en oes ics case a aswswuouo r rrlrlhrlhwz Zz mr mr 87 3 2 BIOS Flash Memory Organization EE 88 3 3 Resourc
28. e System security and manageability logic that enables protection for storing and updating of platform information 25 Intel Desktop Board D815EEA Technical Product Specification 1 7 I O Controller The SMSC LPC47M102 I O Controller provides the following features e Low pin count LPC interface e 3 3 V operation e Two serial ports e One parallel port with Extended Capabilities Port ECP and Enhanced Parallel Port EPP support e Serial IRQ interface compatible with serialized IRQ support for PCI systems e PS 2 style mouse and keyboard interfaces e Interface for one 1 2 MB 1 44 MB or 2 88 MB diskette drive e Intelligent power management including a programmable wake up event interface e PCI power management support e IrDA 1 0 compliant e Fan control Two fan control outputs Two fan tachometer inputs The BIOS Setup program provides configuration options for the I O controller For information about Refer to SMSC LPC47M102 I O controller http www smsc com 1 7 1 Serial Ports The D815EEA board has two serial ports Serial port A is located on the back panel Serial port B is accessible using the connector at location J8E1 The serial ports NS16C550 compatible UARTs support data transfers at speeds up to 115 2 kbits sec with BIOS support The serial ports can be assigned as COM1 3F8h COM2 2F8h COM3 3E8h or COM4 2E8h For information about Refer to The location of the Se
29. e Y appropriate when using a Plug and Play operating system Yes lets the operating system configure Plug and Play devices not required to boot the system This option is available for use during lab testing Reset Config Data es No default No does not clear the PCI PnP configuration data stored in e Yes flash memory on the next boot Yes clears the PCI PnP configuration data stored in flash memory on the next boot Numlock e Off Specifies the power on state of the Numlock feature on the e On default umeric keypad of the keyboard 103 Intel Desktop Board D815EEA Technical Product Specification 4 4 3 Peripheral Configuration Submenu 104 To access this submenu select Advanced on the menu bar then Peripheral Configuration Maintenance Main Advanced Security Power Boot pelts PCI Configuration Boot Configuration Peripheral Configuration IDE Configuration Diskette Configuration Event Log Configuration Video Configuration The submenu represented in Table 68 is used for configuring computer peripherals Table 68 Peripheral Configuration Submenu Feature Options Description Serial port A e Disabled Configures serial port A e Enabled Auto assigns the first free COM port normally COM1 the e Auto default address 3F8h and the interrupt IRQ4 An asterisk displayed next to an address indicates a conflict with another device Base I O address e 3
30. error code beep code information during POST For information about Refer to The location of the onboard speaker Figure 1 page 14 5 5 BIOS Beep Codes 124 Whenever a recoverable error occurs during POST the BIOS displays an error message describing the problem see Table 86 The BIOS also issues a beep code one long tone followed by two short tones during POST if the video configuration fails a faulty video card or no card installed or if an external ROM module does not properly checksum to zero An external ROM module for example a video BIOS can also issue audible errors usually consisting of one long tone followed by a series of short tones For more information on the beep codes issued check the documentation for that external device There are several POST routines that issue a POST terminal error and shut down the system if they fail Before shutting down the system the terminal error handler issues a beep code signifying the test point error writes the error to I O port 80h attempts to initialize the video and writes the error in the upper left corner of the screen using both monochrome and color adapters If POST completes normally the BIOS issues one short beep before passing control to the operating system Error Messages and Beep Codes Table 86 Beep Codes Beep Description Refresh failure Parity cannot be reset First 64 KB memory failure Timer not operational Not used
31. for software MPEG2 decode Software DVD at 30 fps e Integrated graphics memory controller Table 6 lists the refresh frequencies supported by the graphics subsystem Product Description Table 6 Supported Graphics Refresh Frequencies Available Refresh Resolution Color Palette Frequencies Hz Notes 320 x 200 256 colors 70 D 64 K colors 70 D3 16 M colors 70 D 320 x 240 256 colors 70 D 64 K colors 70 D3 16 M colors 70 In 352 x 480 256 colors 70 D 64 K colors 70 D3 16 M colors 70 D 352x576 256 colors 70 In 64 K colors 70 D3 16 M colors 70 D 400 x 300 256 colors 70 D 64 K colors 70 D3 16 Mcolors 70 D 512x384 256 colors 70 ID 64 K colors 70 D3 16 M colors 70 np 640 x 400 256 colors 70 D 64 K colors 70 D3 16 M colors 70 D 640x480 256 colors 60 70 72 75 85 KDO 64 K colors 60 75 85 KD30 64 K colors 70 72 KDO 640 x 480 16 M colors 60 70 72 75 85 KDO 800x600 256 colors 60 70 72 75 85 KDO 64 K colors 60 70 72 75 85 KD30 16 M colors 60 70 72 75 85 KDO 1024 x 768 256 colors 60 70 75 85 KDO 64Kcolors 60 70 75 KD30 64 K colors 85 KD3 16Mcolors 60 70 75 85 KD continued 29 Intel Desktop Board D815EEA Technical Product Specification Table 6 Supported Graphics Refresh Frequencies continued Available Refresh Re
32. of drives that meet this parameter Select a CD ROM drive with a fast initialization rate variations can influence POST times Eliminate unnecessary features such as video company logo displaying screen repaints or mode changes These all add time in the boot process The Plug and Play communication between the video BIOS and the monitor shows time variances Try different monitors Some monitors initialize more quickly thereby enabling the system to boot more quickly Intel Rapid BIOS Boot There are several BIOS settings which if adjusted can reduce the execution time of the POST Set the hard disk drive as the first boot device As a result the POST will not seek a diskette drive saving about one second from the POST time or a CD ROM drive saving about two seconds Make sure that Quiet Boot is disabled to eliminate the logo splash screen This could save several seconds of painting complex graphic images and changing video modes Make sure the Intel Rapid BIOS Boot option in the Boot menu of the BIOS Setup Program is enabled this is typically the default setting This feature bypasses memory count and floppy seek Disable the LAN feature PXE Preboot eXecutable Environment if it will not be used Doing so can reduce up to four seconds of option ROM boot time lt gt NOTE It is possible to optimize the boot process to the point where the system boots so quickly that the Intel Logo Screen or a custom logo splash screen
33. to be set next 37 Display mode set Going to display the power on message 38 Different buses init input IPL general devices to start if present See Section 5 3 for details of different buses 39 Display different buses initialization error messages See Section 5 3 for details of different buses 3A New cursor position read and saved To display the Hit lt DEL gt message continued Error Messages and Beep Codes Table 82 Runtime Code Uncompressed in F000 Shadow RAM continued Code Description of POST Operation 40 To prepare the descriptor tables 42 To enter in virtual mode for memory test 43 To enable interrupts for diagnostics mode 44 To initialize data to check memory wrap around at 0 0 45 Data initialized Going to check for memory wrap around at 0 0 and finding the total system memory size 46 Memory wrap around test done Memory size calculation over About to go for writing patterns to test memory 47 Pattern to be tested written in extended memory Going to write patterns in base 640k memory 48 Patterns written in base memory Going to find out amount of memory below 1M memory 49 Amount of memory below 1M found and verified Going to find out amount of memory above 1M memory 4B Amount of memory above 1M found and verified Check for soft reset and going to clear memory below 1M for soft reset If power on go to check point 4Eh 4C M
34. unique letter C with a tick mark followed by N 232 Located on the component side of the D815EEA board and on the shipping container CE Mark Component side The CE mark should also be on the shipping container 85 Intel Desktop Board D815EEA Technical Product Specification 86 3 Overview of BIOS Features What This Chapter Contains 3 10 fette loi fe EEN 87 BIOS Flash Memory Organization ENEE 88 Re s trce Config lall E 88 System Management BIOS SMBIOS J kk kK kk kk 89 USB Legacy TEE 90 BIOS see ET Nc dee ee dee 90 Recovering BIOS Datta i ci alal nakin a ab eine alaya k ad k Wen ke dak E akla ad k a 91 BOC ODOM EE 92 Fast Booting Systems with Intel Rapid BIOS Boot 92 Set dE TE 94 3 1 Introduction The D815EEA board uses an Intel AMI BIOS which is stored in flash memory and can be updated using a disk based program In addition to the BIOS the flash memory contains the BIOS Setup program POST APM the PCI auto configuration utility and Plug and Play support The D815EEA board supports system BIOS shadowing allowing the BIOS to execute from 64 bit onboard write protected DRAM The BIOS displays a message during POST identifying the type of BIOS and a revision code The initial production BIOS is identified as EA81510A 86A When the D815EEA board jumper is set to configuration mode and the computer is powered up the BIOS compares the CPU version and the microcode version in the BIOS a
35. will not be seen Monitors and hard disk drives with minimum initialization times can also contribute to a boot time that might be so fast that necessary logo screens and POST messages cannot be seen If this should occur it is possible to introduce a programmable delay ranging from 3 to 30 seconds using the Hard Disk Pre Delay feature in the IDE Configuration Submenu of the BIOS Setup Program For information about Refer to IDE Configuration Submenu in the BIOS Setup Program Table 69 page 106 93 Intel Desktop Board D815EEA Technical Product Specification 3 9 3 Operating System 3 9 3 1 Selection The Microsoft Windows Millennium Edition Windows Me operating system has built in capabilities for making PCs boot more quickly For additional information see the following URL http www microsoft com hwdev newpc fast boot htm 3 9 3 2 Optimization To speed operating system availability at boot time limit the number of applications that load into the system tray or the task bar 3 10 BIOS Security Features The BIOS includes security features that restrict access to the BIOS Setup program and who can boot the computer A supervisor password and a user password can be set for the BIOS Setup program and for booting the computer with the following restrictions e The supervisor password gives unrestricted access to view and change all the Setup options in the BIOS Setup program This is the supervisor mode e The user passw
36. 0 00 A 002A 002A 0 0A 0 0A 5 VSB 017A 016A 018A 018A 03A 018A Table 53 lists the power usage for a D815EEA board with the configuration listed above and including the enhanced PCI audio subsystem but no onboard LAN subsystem 77 Intel Desktop Board D815EEA Technical Product Specification Table 53 Power Usage For Board with Enhanced PCI Audio Subsystem and no Onboard LAN subsystem DC Current at Mode AC Power 3 3 V 5 V 12 V 12 V 5 VSB Windows 98 APM full on 43 W 1 80 A 2 81 A 0 18 A 0 00 A 0 09 A Windows 98 APM Suspend 25 W 1 72 A 0 68 A 0 18 A 0 00 A 0 09 A Windows 98 ACPI S0 30 W 1 82 A 0 68 A 0 18 A 0 02 A 0 09 A Windows 98 ACPI S1 25 W 1 73 A 0 68 A 0 18 A 0 02 A 0 09 A Windows 98 ACPI S3 1w 0 0 A 0 0 A 0 0 A 0 0 A 0 23 A Windows 98 ACPI Off low 0 0 A 0 0 A 0 0 A 0 0 A 0 09 A 2 11 2 Add in Board Considerations The D815EEA board is designed to provide 2 A average of 5 V current for each add in board The total 5 V current draw for add in boards in a fully loaded D815EEA board all six expansion slots filled must not exceed 12 A 2 11 3 Standby Current Requirements Jh CAUTION 78 Power supplies used with the board must provide enough standby current to support the Instantly Available ACPI S3 sleep state configuration If the standby current necessary to support multiple wake events fr
37. 00 Shadow RAM Initialize interrupt vector tables initialize system timer initialize DMA controller and interrupt controller En _ Initialize extra Intel Recovery Module E9 Initialize floppy drive EA Try to boot from floppy If reading of boot sector is successful give control to boot sector code ER Booting from floppy failed look for ATAPI LS120 Zip devices EC Try to boot from ATAPI If reading of boot sector is successful give control to boot sector code EE Booting from floppy and ATAPI device failed Give two beeps Retry the booting procedure again go to check point E9 119 Intel Desktop Board D815EEA Technical Product Specification 120 Table 82 Runtime Code Uncompressed in F000 Shadow RAM Code Description of POST Operation 03 NMI is Disabled To check soft reset power on 05 BIOS stack set Going to disable cache if any 06 POST code to be uncompressed 07 CPU init and CPU data area init to be done 08 CMOS checksum calculation to be done next 0B Any initialization before keyboard BAT to be done next 0C KB controller I B free To issue the BAT command to keyboard controller OE Any initialization after KB controller BAT to be done next OF Keyboard command byte to be written 10 Going to issue Pin 23 24 blocking unblocking command 11 Going to check pressing of lt INS gt lt END gt key during power on 12 To init CMOS if Init
38. 2 cache Cache memory may be bad CMOS Battery Low The battery may be losing power Replace the battery soon CMOS Display Type Wrong CMOS Checksum Bad The display type is different than what has been stored in CMOS Check Setup to make sure type is correct The CMOS checksum is incorrect CMOS memory may have been corrupted Run Setup to reset values CMOS Settings Wrong CMOS Date Time Not Set CMOS values are not the same as the last boot These values have either been corrupted or the battery has failed The time and or date values stored in CMOS are invalid Run Setup to set correct values DMA Error Error during read write test of DMA controller FDC Failure Error occurred trying to access diskette drive controller HDC Failure Error occurred trying to access hard disk controller continued 117 Intel Desktop Board D815EEA Technical Product Specification 118 Table 79 BIOS Error Messages continued Error Message Checking NVRAM Update OK Updated Failed Keyboard Error Explanation NVRAM is being checked to see if it is valid NVRAM was invalid and has been updated NVRAM was invalid but was unable to be updated Error in the keyboard connection Make sure keyboard is connected properly KB Interface Error Keyboard interface test failed Memory Size Decreased Memory Size Increased Memory size has decreased since the last boo
39. 24 Ban AD25 A63 AD2 B63 AD3 A31 Ground B31 Ground A64 Vcc3 3 B64 Vcc3 3 A32 AD_STB1 B32 AD_STB1 A65 ADO B65 AD1 Aan C BE3 B33 TAD23 A66 VRREFG_C B66 VREFC_G 66 Table 42 Diskette Drive Connector J8G3 Technical Reference Pin N c a 13 15 17 19 21 23 25 27 29 31 33 Signal Name Ground Ground Key Ground Ground Ground Ground Ground No connect Ground Ground Ground Ground No connect Ground Ground Ground Pin 10 12 14 16 18 20 22 24 26 28 30 32 34 Signal Name DENSEL Reserved FDEDIN FDINDX Index FDMOO Motor Enable A No connect FDDSO Drive Select A No connect FDDIR Stepper Motor Direction FDSTEP Step Pulse FDWD Write Data FDWE Write Enable FDTRKO Track 0 FDWPD Write Protect FDRDATA Read Data FDHEAD Side 1 Select DSKCHG Diskette Change 67 Intel Desktop Board D815EEA Technical Product Specification Table 43 PCI IDE Connectors J8G2 Primary and J6G1 Secondary Pin Signal Name Pin Signal Name 1 Reset IDE 2 Ground 3 Data 7 A Data 8 5 Data 6 6 Daag 7 Data 5 8 Data 10 9 Data 4 10 Data 11 11 Data 3 12 Data 12 13 Data2 14 Data 13 15 Data 1 16 Data 14 17 Data 18 Data 15 19 Ground 20 Key 21 DDRQO DDRQ1 22 Ground 23 WO Write 24 Ground 25 W O Read 26 Ground 27 IOCH
40. 28 Chassis Fan Connector J3F1 Pin Signal Name 1 FAN2_PWM 12 V 3 FAN2_TACH Table 29 CD ROM Legacy Style Connector J2F2 Pin Signal Name CD_Ground CD_IN Left CD_Ground CD_IN Right Signal Name Left audio input from CD ROM CD audio differential ground CD audio differential ground Right audio input from CD ROM Table 31 Auxiliary Line In Connector J2G1 Pin 1 2 3 4 Signal Name Left auxiliary line in Ground Ground Right auxiliary line in Table 32 Telephony Connector J2G2 Pin 1 2 3 4 60 Signal Name Analog audio mono input Ground Ground Analog audio mono output Technical Reference Table 33 Digital Video Out Connector J3H1 Pin Signal Name Pin Signal Name 1 LTVCLKIN 2 5 VDC 3 P_RST_SLOTS 4 LTVCL_3V 5 Ground 6 LTVDA_3V 7 Ground 8 LTVVSYNC 9 Ground 10 LTVHSYNC 11 Ground 12 LTVDATO 13 Ground 14 LTVDAT1 15 Ground 16 LTVDAT2 17 Ground 18 LTVDATS3 19 Ground 20 LTVDAT4 21 Ground 22 LTVDAT5 23 Ground 24 LTVDAT6 25 Ground 26 LTVDAT7 27 Ground 28 LTVDAT8 29 Ground 30 LTVDAT9 31 Ground 32 LTVDAT10 33 Ground 34 LTVDAT11 35 Ground 36 LTVCLKOUTO 37 Ground 38 LTVCLKOUT1 39 Ground 40 LTVBLNK Table 34 Processor Fan Connector J3M1 Pin Signal Name 1 Ground 12 V Ground Table 35 Power Connector J8K1 Pin Signal Name Pin Signal Name 1 3 3 V 11 3 3 V 2
41. 3 Pin Signal In Out Description Pin Signal In Out Description 1 HD PWP Out Harddisk LED pull 2 HDR_BLNK_ Out Front panel green up 330 Q to 5 V GRN LED 3 HDA Out Harddisk active LED 4 HDR_BLNK_ Out Front panel yellow YEL LED 5 GND Ground 6 FPBUT_IN In Power switch 7 FP_RESET In Reset switch 8 GND Ground 9 45V Out IR Power 10 INC 11 IRRX in IrDA serial input 12 GND Ground 13 GND Ground 14 pin removed Not connected 15 IRTX Out IrDA serial output 16 5V Out Power 2 8 3 3 1 Infrared Port Connector Serial port B can be configured to support an IrDA module connected to pins 9 11 13 and 15 For information about Refer to Infrared support Section 1 7 2 page 26 Configuring serial port B for infrared applications Section 4 4 3 page 104 2 8 3 3 2 Reset Switch Connector Pins 5 and 7 can be connected to a momentary SPST type switch that is normally open When the switch is closed the D815EEA board resets and runs the POST 2 8 3 3 3 Hard Drive Activity LED Connector Pins 1 and 3 can be connected to an LED to provide a visual indicator that data is being read from or written to a hard drive For the LED to function properly an IDE drive must be connected to the onboard IDE interface The LED will also show activity for devices connected to the SCSI hard drive activity LED connector Fo
42. 82802AB Firmware Hub FWH The GMCH is a centralized controller for the system bus the memory bus the AGP bus and the Accelerated Hub Architecture interface The ICH2 is a centralized controller for the board s I O paths The FWH provides the nonvolatile storage of the BIOS as well as hardware dependent security features The chipset provides the interfaces shown in Figure 3 4 lt ATA 33 66 100 Network System Bus m USB gt SDRAM Bus e y 815E Chipset e Yy 82815E 82801BA 82802AB Graphios ang gi UO Controller Hub wk Firmware Hub Memory Controller Bus ICH2 FWH Hub GMCH i i A A A Digital video AGP LPC Bus output EES SMBus PCI Bus AC Link v v v v OM10202 Figure 3 Intel 815E Chipset Block Diagram For information about Refer to The Intel 815E chipset Http developer intel com The resources used by the chipset Chapter 2 The chipset s compliance with ACPI APM AC 97 Section 1 3 page 16 1 6 1 Product Description Intel 82815E Graphics and Memory Controller Hub GMCH The GMCH provides the following 1 6 2 An integrated Synchronous DRAM memory controller with autodetection of SDRAM An interface for a single AGP device or a Graphics Performance Accelerator GPA card An interface for a digital video output DVO connector for a flat panel digital CRT or TV out Support for ACPI Rev 1 0 and
43. 9 LAN_RSTSYNC A10 LAN_CLK A11 LAN_RXD1 B10 Ground B11 LAN_RXD2 A12 Reserved B12 LAN_RXDO A13 USB B13 Ground A14 GND B14 Reserved A15 USB B15 5VDUAL A16 12V B16 USB_OC A17 GND B17 Ground A18 3 3VDUAL B18 12V A19 5VD B19 3 3VD A20 Ground B20 Ground A21 EEDI B21 EEDO A22 EECS B22 EECK A23 SMB_A1 B23 Ground A24 SMB_A2 A25 SMB_SDA B24 SMB_AO B25 SMB_SCL A26 AC97_RESET A27 Reserved B26 CDC_DWN_ENAB B27 Ground A28 AC97_SDATA_IN1 A29 AC97_SDATA_INO B28 AC97_SYNC B29 AC97_SDATA_OUT A30 GND For information about The CNR 64 B30 AC97_BITCLK Refer to Section 1 11 page 36 Table 40 PCI Bus Connectors J4A1 J4B1 J4C1 J4D1 J4E1 Technical Reference Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Signal Name Ground TRST 12 V 5 V TMS 5 V TDI 5 V INTA INTC 5 V Reserved 5 V I O Reserved Ground Ground 3 3 V aux RST 5 V I O GNT Ground PME AD30 3 3 V AD28 AD26 Ground AD24 IDSEL 3 3 V AD22 AD20 Ground AD18 Pin Kee B2 B3 B4 B5 pe B7 B8 B9 BIO B11 B12 B13 B14 B15 B16 B17 DER B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30
44. 90 USB Legacy Support USB legacy support enables USB devices such as keyboards mice and hubs to be used even when no operating system USB drivers are in place USB legacy support is used in accessing the BIOS Setup program and installing an operating system that supports USB By default USB legacy support is set to Auto The Auto setting enables USB legacy support if a supported USB device is connected to the USB port This sequence describes how USB legacy support operates in the Auto default mode 1 When you power up the computer USB legacy support is disabled 2 POST begins 3 USB legacy support is temporarily enabled by the BIOS This allows you to use a USB keyboard to enter the BIOS Setup program or the maintenance mode 4 POST completes and disables USB legacy support unless it was set to Enabled or Auto while in the BIOS Setup program 5 The operating system loads While the operating system is loading USB keyboards and mice are not recognized unless USB legacy support was set to Enabled or Auto while in the BIOS Setup program After the operating system loads the USB drivers the USB devices are recognized by the operating system To install an operating system that supports USB enable USB Legacy support or set it to Auto in the BIOS Setup program and follow the operating system s installation instructions Once the operating system is installed and the USB drivers have been configured USB legacy support is no lon
45. 97_desc html El Torito Bootable CD ROM Version 1 0 the Phoenix Web site at format specification January 25 1995 http www ptltd com techs Phoenix Technologies Ltd and specs html IBM Corporation GPA see AIMM IrDAt Serial Infrared Physical Version 1 1 Phone 510 943 6546 Layer Link specification October 17 1995 Fax 510 943 5600 Infrared Data Association E mail irda netcom com LPC Low Pin Count Interface Version 1 0 http www intel com Specification September 29 1997 design chipsets industry Intel Corporation lpc htm PCI PCI Local Bus Version 2 2 http www pcisig com Specification December 18 1998 PCI Special Interest Group PCI Bus Power Version 1 41 http www pcisig com Management Interface December 18 1998 Specification PCI Special Interest Group Plug and Plug and Play BIOS Version 1 0a http www microsoft com Play specification May 5 1994 hwdev respec pnpspecs htm continued 17 Intel Desktop Board D815EEA Technical Product Specification Table 3 Specifications continued Specification Version Revision Date The information is Description Title and Ownership available from SDRAM PC SDRAM Unbuffered Revision 1 0 http www Inte com DIMM Specification February 1998 design chipsets memory Intel Corporation PC SDRAM DIMM Revision 1 5 http www Inte com Specification November 1997 design chipsets memory Intel Corporation PC Serial Prese
46. A board must meet specific dimension and material requirements Systems based on this board need the back panel I O shield to pass certification testing Figure 15 shows the critical dimensions of the chassis dependent I O shield Dimensions are given in inches to a tolerance of 0 02 inches These figures also indicate the position of each cutout Additional design considerations for I O shields relative to chassis requirements are described in the ATX specification See Section 1 3 for information about the ATX specification lt gt NOTE An LC shield compliant with the ATX chassis specification 2 01 is available from Intel I 6 390 Ref 1162 30 0 157 4 00 j 9 787 01 Typ 20 00 0 063 0 61 Refe 6 268 1 60 15 49 159 20 T 0 94 Ref 8 S 3x Dia 0 33 8 38 Go 23 87 SS 4 618 117 30 0 88 22 35 1 0 280 7 10 0 39 Dia 1 89 Ref j9 90 48 00 0 00 0 00 9 450 0 471 E 11 11 55 9 568 T 14 43 i 8x R 02 Min de a 0 171 4 33 0 50 SA a R S 0 321 8 14 SS 8 W 0 471 11 95 S E 0 621 15 76 A 8 Pictorial View OM10343 Figure 15 I O Shield Dimensions 76 2 11 Electrical Considerations 2 11 1 Power Consumption Technical Reference Table 52 and Table 53 list voltage and current measurements for a computer tha
47. APM Rev 1 2 compliant power management Intel 82801BA I O Controller Hub ICH2 The ICH provides the following 1 6 2 1 33 MHz PCI bus interface Support for up to six PCI master devices Low Pin Count LPC interface that supports an LPC compatible I O controller Support for two Master DMA devices Integrated IDE controller that supports Ultra DMA 33 MB sec and ATA 66 100 mode 66 MB sec 100 MB sec Integrated LAN Media Access Controller Universal Serial Bus interface with two USB controllers providing four ports in a UHCI Implementation Power management logic for ACPI Rev 1 0b compliance System Management Bus SMBus clock and data lines also routed to PCI bus connector 2 Real Time Clock with 256 byte battery backed CMOS RAM AC 97 digital link for Audio and telephony codecs including AC 97 2 1 compliance Logic for PCM in PCM out Mic input Modem in and Modem out Separate PCI functions for audio and modem Communications Network Riser CNR interface IDE Interfaces The ICH2 s IDE controller has two independent bus mastering IDE interfaces that can be independently enabled The IDE interfaces support the following modes Programmed I O PIO CPU controls data transfer 8237 style DMA DMA offloads the CPU supporting transfer rates of up to 16 MB sec Ultra DMA DMA protocol on IDE bus supporting host and target throttling and transfer rates of up to 33 MB sec Ultra ATA 66 DMA protocol on I
48. DE bus supporting host and target throttling and transfer rates of up to 66 MB sec ATA 66 protocol is similar to ATA 33 and is device driver compatible ATA 66 uses faster timings and requires a specialized cable to reduce reflections noise and inductive coupling Ultra ATA 100 DMA protocol on IDE bus allows host and target throttling The ICH2 Ultra ATA 100 logic can achieve read transfer rates up to 100 MB sec and write transfer rates up to 88 MB sec The higher quality cable used for ATA 66 DMA support is adequate to reduce reflections noise and inductive coupling for ATA 100 operation 23 Intel Desktop Board D815EEA Technical Product Specification The IDE interfaces also support ATAPI devices such as CD ROM drives and ATA devices using the transfer modes listed in Table 70 on page 107 The BIOS supports logical block addressing LBA and extended cylinder head sector ECHS translation modes The drive reports the transfer rate and translation mode to the BIOS The D815EEA board supports laser servo LS 120 diskette technology through its IDE interfaces The LS 120 drive can be configured as a boot device by setting the BIOS Setup program s Boot menu to one of the following e ARMD FDD ATAPI removable media device floppy disk drive e ARMD HDD ATAPI removable media device hard disk drive For information about Refer to The location of the IDE connectors i Figure 11 page 63 The signal names of the IDE co
49. E000 ROM to get control next A9 Returned from E000 ROM control Going to do any initialization required after E000 optional ROM control AA Initialization after E000 optional ROM control is over Going to display the system configuration AB Put INT13 module runtime image to shadow AC Generate MP for multiprocessor support if present AD Put CGA INT10 module if present in Shadow continued Error Messages and Beep Codes Table 82 Runtime Code Uncompressed in F000 Shadow RAM continued Code Description of POST Operation AE Uncompress SMBIOS module and init SMBIOS code and form the runtime SMBIOS image in shadow B1 Going to copy any code to specific area 00 Copying of code to specific area done Going to give control to INT 19 boot loader Bus Initialization Checkpoints The system BIOS gives control to the different buses at several checkpoints to do various tasks Table 83 describes the bus initialization checkpoints Table 83 Bus Initialization Checkpoints Checkpoint Description 2A Different buses init system static and output devices to start if present 38 Different buses init input IPL and general devices to start if present 39 Display different buses initialization error messages 95 Init of different buses optional ROMs from C800 to start While control is inside the different bus routines additional checkpoints are output to port 80h as WORD t
50. ECP port LPTn base address 400h OCF8 OCFB 4 bytes PCI configuration address register OCF9 1 byte Turbo and reset control register OCFC OCFF 4 bytes PCI configuration data register FFAO FFA7 8 bytes Primary bus master IDE registers FFA8 FFAF D bytes Secondary bus master IDE registers 96 contiguous bytes starting on a 128 byte ICH ACPI TCO divisible boundary 64 contiguous bytes starting on a 64 byte D815EEA board resource divisible boundary 64 contiguous bytes starting on a 64 byte Onboard audio controller divisible boundary 32 contiguous bytes starting on a 32 byte ICH USB divisible boundary 16 contiguous bytes starting on a 16 byte ICH SMBus divisible boundary 4096 contiguous bytes starting on a 4096 byte Intel 82801BA PCI bridge divisible boundary Default but can be changed to another address range Dword access only kkk Byte access only NOTE Some additional I O addresses are not available due to ICH addresses aliassing For information about the ICH addressing refer to Section 1 2 on page 16 49 Intel Desktop Board D815EEA Technical Product Specification 2 4 DMA Channels Table 14 DMA Channels DMA Channel Number Data Width System Resource 0 8 or 16 bits Audio 1 8 or 16 bits Audio parallel port 2 8 or 16 bits Diskette drive 3 8 or 16 bits Parallel port for ECP or EPP audio 4 8 or 16 bits DMA contr
51. F8 default Specifies the base I O address for serial port A if serial port A This feature is present 2F8 is Enabled only when Serial Port A e 3E8 is set to Enabled 2E8 Interrupt e IRQ3 Specifies the interrupt for serial port A if serial port A is This feature is present e IRQ 4 Enabled only when Serial Port A default is set to Enabled Serial port B e Disabled Configures serial port B e Enabled Auto assigns the first free COM port normally COM2 the Auto default address 2F8h and the interrupt IRQ3 An asterisk displayed next to an address indicates a conflict with another device Mode e Normal Specifies the mode for serial port B for normal COM 2 or default infrared applications This option is not available if serial e IrDA SIR A port B has been disabled e ASK_IR Base UO address e 2F8 default Specifies the base I O address for serial port B This feature is present 3Eg only when Serial Port B is set to Enabled 258 continued BIOS Setup Program Table 68 Peripheral Configuration Submenu continued Feature Options Description Interrupt es IRQ3 Specifies the interrupt for Serial port B This feature is present default only when Serial PortB e IRQ4 is set to Enabled Parallel port e Disabled Configures the parallel port e Enabled Auto assigns LPT1 the address 378h and the interrupt IRQ7 e Auto default An asterisk displayed next to an ad
52. GA port Dark blue Table 21 G Parallel port Burgundy Table 22 H Serial port A Teal Table 23 l MIDI Game port Gold Table 24 J Audio line out Lime green Table 25 K Audio line in Light blue Table 26 L Mic in Pink Table 27 Figure 9 Back Panel Connectors 54 lt gt NOTE Technical Reference The back panel audio line out connector is designed to power headphones or amplified speakers only Poor audio quality occurs if passive non amplified speakers are connected to this output Table 18 PS 2 Mouse Keyboard Connectors Pin Signal Name Data Not connected Ground Fused 5 V Clock Not connected Table 19 LAN Connector Signal Name TX TX RX Ground Y 5 Ground RX N 9 gt a A WO DM gt Table 20 USB Connectors Ground Ground Pin Signal Name 5 V fused 2 USBPO USBP1 3 USBP0 USBP1 4 Ground Signal names in brackets are for USB port 1 55 Intel Desktop Board D815EEA Technical Product Specification 56 Table 21 VGA Port Connector Pin Signal Name Pin Signal Name Pin Signal Name 1 Red 6 Ground 11 No connect 2 Green 7 Ground 12 MONID1 3 Blue 8 Ground 13 HSYNC 4 No connect 9 Fused VCC 14 VSYNC 5 Ground 10 Ground 15 MONID2 Table 22 Parallel Port Connector Pin Standard Signal Name ECP Signal Name EPP Signal Name i WRITE WAIT 13 SELECT SELECT 16 INIT RESET Table 23 Serial Port A Connector
53. Intel Desktop Board D815EEA Technical Product Specification a ntel May 2000 Order Number A16964 001 The Intel Desktop Board D815EEA may contain design defects or errors known as errata that may cause the product to deviate from published specifications Current characterized errata are documented in the Intel Desktop Board D815EEA Specification Update Revision History Revision Revision History Date P1 First review draft of the Intel Desktop Board D815EEA Technical Product March 2000 Specification P2 Second review draft of the Intel Desktop Board D815EEA Technical April 2000 Product Specification P3 Third review draft of the Intel Desktop Board D815EEA Technical Product June 2000 Specification 001 First release of the Intel Desktop Board D815EEA Technical Product June 2000 Specification This product specification applies to only standard D815EEA boards with BIOS identifier EA81510A 86A Changes to this specification will be published in the Intel Desktop Board D815EEA Specification Update before being incorporated into a revision of this document Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied
54. J4C1 INTC INTD INTA INB PCI Bus Connector 4 J4B1 INTB NIC INTD INA PCI Bus Connector 5 J4A1 INTA NIR NIC IND sr lt gt NOTE 52 The ICH can connect each PIRQ line internally to one of the IRQ signals 3 4 5 6 7 10 11 12 14 and 15 Typically a device that does not share a PIRQ line will have a unique interrupt However in certain interrupt constrained situations it is possible for two or more of the PIRQ lines to be connected to the same IRQ signal Technical Reference 2 8 Connectors CAUTION Only the back panel connectors of the DSISEEA board have overcurrent protection The D8ISEEA board s internal connectors are not overcurrent protected and should connect only to devices inside the computer s chassis such as fans and internal peripherals Do not use these connectors to power devices external to the computer s chassis A fault in the load presented by the external devices could cause damage to the computer the interconnecting cable and the external devices themselves This section describes the board s connectors This section describes the board s connectors The connectors can be divided into the following groups e Back panel I O connectors see page 54 PS 2 keyboard and mouse LAN USB 2 Parallel port Serial port VGA MIDI game port Audio Line out Line in and Mic in e Internal I O connectors see page 58 Audio ATAPI CD ROM legacy style CD ROM telephony auxili
55. N 77 Power Usage For Board with Enhanced PCI Audio Subsystem and no Onboard LAN sSUubDsysterm ENEE NENNEN EES KK KA KK eg 78 standby Current Requirements stra gedreet Ek kk kek k ke kK KK KAK KK 79 Thermal Considerations for Component LELd Ek kk kk e 82 D815EEA Board Environmental Specifications Ek 83 Sa Ma E EE 84 EMC Regulations issig aae a a E E EE E E E ai 84 Supervisor and User Password Functions ssseesssessseerreeeesserrnnresserttrrrnstrrnnrrnnnnntnne 95 BIOS Setup Program Menu Bar 97 BIOS Setup Program Function Keys tung 98 Maintenance Menu LLL EEE kk kek kk kek KK k KK kk K KK diene KK KAK 98 Extended Configuration SUDMENU iihddE kk kk k k kK kk K K KA 99 Main E EE 100 Advanced E EE 101 PCI Configuration Submenu i kk kk kk k EEN 102 ek een eege eebe kk kk k kk kK KK KAKA 103 Peripheral Configuration Gubmen kuk 104 IDE Configuration Submenu kk kk kk kk kK KK KK KK kK kk 106 Primary Secondary IDE Master Slave Gubmenus Ek 107 Diskette Configuration Submenu EELu kk kk kk kk KK KK K 109 Event Log Configuration Submenu ii Ek kk kk kk KK 110 Video Configuration SUBMENU E 111 Security MOM EE 112 walla TEE 113 eng E EE 114 IDE Drive Configuration SubMenu ANNER ENNEN 115 Ext EIERE 116 BIOS EMOrWICSSACCS Ee 116 Uncompressed INIT Code Checkpooints AAA 119 Boot Block Recovery
56. OS reads the Setup values from flash memory If this memory is corrupted the BIOS reads the custom defaults If no custom defaults are set the BIOS reads the factory defaults Discard Changes Discards changes without exiting Setup The option values present when the computer was turned on are used 116 5 Error Messages and Beep Codes What This Chapter Contains 5 1 BIOS Error Oe GE 117 5 2 Port 80h POST Codes penaa ae deed nt shige ENEE NEE Neue 119 5 3 Bus initialization Checkpoints EE 123 De EE eebe eebe 124 5 5 BIOS BECP COURS vii 4s2 2i5252 5 4521 3 x3 layi das creda ee 124 5 6 Diagnostic E B DJ rhrldrll rrz oaoa r r r_rg _d_ vn 125 5 1 BIOS Error Messages Table 79 lists the error messages and provides a brief description of each Table 79 BIOS Error Messages Error Message Explanation GA20 Error Pri Master HDD Error Pri Slave HDD Error Sec Master HDD Error Sec Slave HDD Error An error occurred with Gate A20 when switching to protected mode during the memory test Could not read sector from corresponding drive Pri Master Drive ATAPI Incompatible Pri Slave Drive ATAPI Incompatible Sec Master Drive ATAPI Incompatible Sec Slave Drive ATAPI Incompatible A Drive Error Cache Memory Bad Corresponding drive in not an ATAPI device Run Setup to make sure device is selected correctly No response from diskette drive An error occurred when testing L
57. OS use A coin cell battery CR2032 powers the real time clock and CMOS memory When the computer is not plugged into a wall socket the battery has an estimated life of three years When the computer is plugged in the standby current from the power supply extends the life of the battery The clock is accurate to 13 minutes year at 25 C with 3 3 VSB applied The time date and CMOS values can be specified in the BIOS Setup program The CMOS values can be returned to their defaults by using the BIOS Setup program gt NOTE If the battery and AC power fail standard defaults not custom defaults will be loaded into CMOS RAM at power on gt NOTE The recommended method of accessing the date in systems with DSIS5EEA boards is indirectly from the Real Time Clock RTC via the BIOS The BIOS on D amp I5EEA boards contains a century checking and maintenance feature This feature checks the two least significant digits of the year stored in the RTC during each BIOS request INT 1Ah to read the date and if less than 80 e 1980 is the first year supported by the PC updates the century byte to 20 This feature enables operating systems and applications using the BIOS date time services to reliably manipulate the year as a four digit value For information about Refer to Proper date access in systems with D815EEA boards Section 1 2 page 16 1 6 3 Intel 82802AB 4 Mbit Firmware Hub FWH The FWH provides the following e System BIOS
58. RDY 28 P ALE Cable Select pull up 29 DDACKO DDACK1 20 Ground 31 TIRQ 14 IRQ 15 32 Reserved 33 DAG Address 1 34 GPIO_DMA66_Detect_Pri GPIO_DMA66_Detect_Sec 35 DAGO Address 0 36 DAG2 Address 2 37 Chip Select 1P Chip Select 1S 38 Chip Select 3P Chip Select 3S 39 Activity Ap Ground Note Signal names in brackets are for the secondary IDE connector 68 Technical Reference 2 8 3 External UO Connectors Figure 12 shows the locations of the external I O connectors GE A B C D E OM10046 Item _Description Reference Designator For more information see A SCSI LED J7A1 Table 46 B Auxiliary front panel power LED J8C2 Table 47 Cc Front panel J8C3 Table 48 D Front panel USB J8C1 Table 44 E Serial port B J8E1 Table 45 Figure 12 External UO Connectors 69 Intel Desktop Board D815EEA Technical Product Specification Table 44 Front Panel USB Connector J8C1 Pin Signal Name Pin Signal Name 4 VREG
59. SMA CD unit interface that supports the following physical layer interface devices 82562ET onboard LAN 82562ET MT 10 100 Mbit sec Ethernet on CNR bus 82562EH 1 Mbit sec HomePNAT on CNR bus e PCI Power Management Supports APM Supports ACPI technology Supports Wake up from suspend state Wake on LANT technology 35 Intel Desktop Board D815EEA Technical Product Specification 1 10 1 Intel 82562ET Platform LAN Connect Device Optional The Intel 82562ET component provides an interface to the back panel RJ 45 connector with integrated LEDs This physical interface may alternately be provided via the CNR connector The Intel 82562ET provides the following functions e Basic 10 100 Ethernet LAN Connectivity e Supports RJ 45 connector with status indicator LEDs e Full driver compatibility e Advanced Power Management support e Programmable transit threshold e Configuration EEPROM that contains the MAC address 1 10 2 RJ 45 LAN Connector LEDs Two LEDs are built into the RJ 45 LAN connector Table 7 describes the LED states when the board is powered up and the LAN subsystem is operating Table 7 LAN Connector LED States LED Color LED State Condition Green Off 10 Mbit sec data rate is selected On 100 Mbit sec date rate is selected Yellow Off LAN link is not established On steady state LAN link is established On brighter and pulsing The computer is communicati
60. WC video memory cache mode Full 32 byte contents of the Write Combining buffer are written to memory as required Cache lookups are not performed Both the video driver and the application must support Write Combining Selects UnCacheable UC video memory cache mode This setting identifies the video memory range as uncacheable by the processor Memory writes are performed in program order Cache lookups are not performed Well suited for applications not supporting Write Combining e UC default SDRAM Auto Configuration e Auto Sets extended memory configuration options to auto or default user defined e User Defined CAS Latency e 3 Selects the number of clock cycles required to address a e 2 column in memory e Auto default SDRAM RAS to CAS es 3 Selects the number of clock cycles between addressing a Delay e 2 row and addressing a column e Auto default SDRAM RAS Precharge e 3 Selects the length of time required before accessing a new e 2 row e Auto default 99 Intel Desktop Board D815EEA Technical Product Specification 4 3 Main Menu To access this menu select Main on the menu bar at the top of the screen Maintenance Main Advanced Security Power Boot Exit Table 64 describes the Main Menu This menu reports processor and memory information and is for configuring the system date and system time Table 64 Main Menu Feature Options Description BIOS Version No o
61. _FPLUSB PWR 3 VREG_FP_USB_PWR 3 ICH_U_P2 4 ICH_U_P3 5 ICH_U_P2 6 ICH_U_P3 7 Ground ati 8 Ground 9 Key no pin 10 ICU_U_OC1_2 Table 45 Serial Port B Connector J8E1 Pin Signal Name Pin Signal Name H4 a2 Serial In SIN2 3 Serial Out SOUT2 4 DTR2 5 Ground 6 DSR2 7 RTS2 8 CTS2 9 RI2 10 Key no pin 2 8 3 1 SCSI Hard Drive Activity LED Connector The SCSI hard drive activity LED connector is a 1 X 2 pin connector that allows add in SCSI controller to use the same LED as the IDE controller This connector can be connected to the LED output of the add in controller card The LED will indicate when data is being read or written using the add in controller Table 46 lists the signal names of the SCSI hard drive activity LED connector Table 46 SCSI LED Connector J7A1 Pin Signal Name SCSI activity 2 Not connected 2 8 3 2 Auxiliary Front Panel Power LED Connector This connector duplicates the signals on pins 2 and 4 of the front panel connector Table 47 Auxiliary Front Panel Power LED Connector J8C2 Pin Signal Name In Out Description 1 HDR_BLNK_GRN Out Front panel green LED 2 No connect 3 HDR_BLNK_YEL Out Front panel yellow LED 70 Technical Reference 2 8 3 3 Front Panel Connector This section describes the functions of the front panel connector Table 48 lists the signal names of the front panel connector Table 48 Front Panel Connector J8C
62. anagement and for CNR board operation 1 12 Hardware Management Subsystem Optional The hardware management features enable the board to be compatible with the Wired for Management WfM specification The board has several hardware management features including the following e Hardware monitoring e Chassis intrusion detect connector e Fan control and monitoring implemented on the SMSC LPC47M102 I O controller For information about Refer to The WfM specification Table 3 page 16 Fan control functions of the SMSC LPC47M102 I O controller Section 1 11 page 36 37 Intel Desktop Board D815EEA Technical Product Specification 1 12 1 Hardware Monitor Component The hardware monitor component provides low cost instrumentation capabilities The features of the component include e Internal ambient temperature sensing e Remote thermal diode sensing for direct monitoring of processor temperature if supported in the processor e Power supply monitoring 12 5 3 3 2 5 3 3 VSB VCCP to detect levels above or below acceptable values e SMBus interface 1 12 2 Chassis Intrusion Detect Connector The board supports a chassis security feature that detects if the chassis cover is removed and sounds an alarm through the onboard speaker For the chassis intrusion circuit to function the chassis power supply must be connected to AC power The security feature uses a mechanical switch on the chassis that attaches to the c
63. ary line input Digital video interface Fans 3 Power Chassis intrusion Wake on LAN technology Add in boards one CNR connector one AGP universal connector and five PCI bus connectors IDE 2 Diskette drive e External I O connectors see page 69 SCSI LED Front panel USB Serial port B Front panel power sleep message waiting LED power switch hard drive activity LED reset switch infrared port and auxiliary front panel LED 53 Intel Desktop Board D815EEA Technical Product Specification 2 8 1 Back Panel Connectors Figure 9 shows the location of the back panel connectors The back panel connectors are color coded in compliance with PC 99 recommendations The figure legend below lists the colors used ORO J K L OM10043 Item Description Color For more information see A PS 2 mouse port Green Table 18 B PS 2 keyboard port Purple Table 18 C LAN Black Table 19 D USB port 0 Black Table 20 E USB port 1 Black Table 20 F V
64. ation on the D815EEA board and X is the instance of the particular part at that general location For example J5J1 is a connector located at 5J It is the first connector in the 5J area GB Gigabyte 1 073 741 824 bytes KB Kilobyte 1024 bytes Kbit Kilobit 1024 bits kbits sec 1000 bits per second MB Megabyte 1 048 576 bytes MB sec Megabytes per second Mbit Megabit 1 048 576 bits Mbit sec Megabits per second xxh An address or data value ending with a lowercase h indicates a hexadecimal value x x V Volts Voltages are DC unless otherwise specified F This symbol is used to indicate third party brands and names that are the property of their respective owners Contents 1 Product Description UNE e EE 12 1 1 1 Soul E K ca pe kanin i karikan REEE AEE AE EEEE HA 12 1 1 2 Manufact ring OpUONS lt s xalk y slan n A hk D R keka H k ae y n a Bi ra wede vee 13 1 1 3 D815EEA Board Layout EE 14 1 1 4 Bl ck Diagrami esie milla kl makina lk lk k kak ELA E UR k 3 karak ka kake kel l k beka k kana Di 15 12 Online SUpport EE 16 1 3 Design SPECICATION 2 Gatintet ont en tetas hs ais eter sate tee ate tea coe 16 TAY dree 19 15 System Memory E 20 156 Intell gI5E Chipset Eed 22 1 6 1 Intel 82815E Graphics and Memory Controller Hub GMCH 23 1 6 2 Intel 82801BA I O Controller Hub ICH2 E e 23 1 6 3 Intel 82802AB 4 Mbit Firmware Hub EW 25 E Ge te EE 26
65. ble 67 is for configuring the IRQ priority of PCI slots individually Table 66 PCI Configuration Submenu Feature Options Description PCI Slot 1 IRQ Priority e Auto default Allows selection of IRQ priority 9 10 11 PCI Slot 2 IRQ Priority e Auto default Allows selection of IRQ priority 9 10 11 PCI Slot 3 IRQ Priority Auto default Allows selection of IRQ priority IRQ Priority selections for 9 PCI slots 3 and 5 are linked Selections made to PCI 10 Slot 3 IRQ Priority are repeated in PCI Slot 5 IRQ Priority 11 PCI Slot 4 IRQ Priority e Auto default Allows selection of IRQ priority 9 10 11 PCI Slot 5 IRQ Priority No options Always set to Auto 102 BIOS Setup Program 4 4 2 Boot Configuration Submenu To access this submenu select Advanced on the menu bar then Boot Configuration Maintenance Main Advanced Security Power Boot Bang PCI Configuration Boot Configuration Peripheral Configuration IDE Configuration Diskette Configuration Event Log Configuration Video Configuration The submenu represented by Table 67 is for setting Plug and Play options resetting configuration data and the power on state of the Numlock key Table 67 Boot Configuration Submenu Feature Options Description No default Specifies if manual configuration is desired No lets the BIOS configure all devices This setting is Plug amp Play O S
66. chnical Product Specification Table 70 Primary Secondary IDE Master Slave Submenus continued Feature PIO Mode Options e Auto default 0 e WOOD Description Specifies the PIO mode Ultra DMA Cable Detected 108 e Disabled default e Mode 0 e Mode 1 e Mode 2 e Mode 3 e Mode A e Mode 5 None Specifies the Ultra DMA mode for the drive Displays the type of cable connected to the IDE interface 40 conductor or 80 conductor for Ultra ATA 66 100 devices BIOS Setup Program 4 4 5 Diskette Configuration Submenu To access this menu select Advanced on the menu bar then Diskette Configuration Maintenance Main Advanced Security Power Boot Bang PCI Configuration Boot Configuration Peripheral Configuration IDE Configuration Diskette Configuration Event Log Configuration Video Configuration The submenu represented by Table 71 is used for configuring the diskette drive Table 71 Diskette Configuration Submenu Feature Options Description Diskette Controller e Disabled Disables or enables the integrated diskette Enabled default controller Floppy A e Not Installed Specifies the capacity and physical size of e 360 KB 514 diskette drive A es 1 2 MB 514 e 720 KB 3V2 e 1 44 1 25 MB 372 default es 2 88 MB 3V2 Diskette Write Protect e Disabled default Disables or enables write protect for the e Enabled diskette drive
67. cification updates Section 1 2 page 16 Intel Celeron processor datasheets and specification updates Section 1 2 page 16 2 13 Reliability 82 The mean time between failures MTBF prediction is calculated using component and subassembly random failure rates The calculation is based on the Bellcore Reliability Prediction Procedure TR NWT 000332 Issue 4 September 1991 The MTBF prediction is used to estimate repair rates and spare parts requirements The Mean Time Between Failures MTBF data is calculated from predicted data at 35 C D815EEA board MTBF 417538 hours Technical Reference 2 14 Environmental Table 56 lists the environmental specifications for the D815EEA board Table 56 D815EEA Board Environmental Specifications Parameter Specification Temperature Non Operating 40 C to 70 C Operating 0 C to 55 C Shock Unpackaged 30 g trapezoidal waveform Velocity change of 170 inches second Packaged Half sine 2 millisecond Product Weight pounds Free Fall inches Velocity Change inches sec lt 20 36 167 21 40 30 152 41 80 24 136 81 100 18 118 Vibration Unpackaged 5 Hz to 20 Hz 0 01 g Hz sloping up to 0 02 g Hz 20 Hz to 500 Hz 0 02 g Hz flat Packaged 10 Hz to 40 Hz 0 015 g Hz flat 40 Hz to 500 Hz 0 015 g Hz sloping down to 0 00015 g Hz 83 Intel Desktop Board D815EEA Technical Produc
68. curity Power Boot Bag PCI Configuration Boot Configuration Peripheral Configuration IDE Configuration Diskette Configuration Event Log Configuration Video Configuration The menu represented in Table 69 is used to configure IDE device options Table 69 IDE Configuration Submenu Feature Options Description IDE Controller e Disabled Specifies the integrated IDE controller e Primary Primary enables only the primary IDE controller Hard Disk Pre Delay Secondary e Both default e Disabled default e 3 Seconds 6 Seconds 9 Seconds e 12 Seconds 15 Seconds e 21 Seconds 30 Seconds Secondary enables only the secondary IDE controller Both enables both IDE controllers Specifies the hard disk drive pre delay Primary IDE Master Primary IDE Slave No options No options Reports type of connected IDE device When selected displays the Primary IDE Master submenu Reports type of connected IDE device When selected displays the Primary IDE Slave submenu Secondary IDE Master Secondary IDE Slave No options No options Reports type of connected IDE device When selected displays the Secondary IDE Master submenu Reports type of connected IDE device When selected displays the Secondary IDE Slave submenu 106 BIOS Setup Program 4 4 4 1 Primary Secondary IDE Master Slave Submenus To access these submenus select
69. cy response 20 Hz to 20 kHz 0 1 dB e ACPI and APM power management compliant Product Description 82801BA Game Port UO Controller Hub aC SU SE 02 ICH2 MIDI Interface gt w CD ROM Analog Devices A d AG 97 Link _ gt AD1885 fe Audoin Analog Cad Mic In nalog LOL wa Modem Audio Line Out OM10226 Figure 4 Block Diagram of Basic Audio Subsystem 1 9 2 Enhanced PCI Audio Subsystem The D815EEA board offers an optional subsystem of AC 97 V 1 03 compliant audio features supported by the Creative Labs ES1373 digital controller with Crystal Semiconductor CS4297 A codec Figure 5 is a block diagram of the enhanced PCI audio subsystem lk CD ROM Analog Codec 4 ele d Crystal Semiconductor t ugio CS4297 A ra en A Modem Audio Line Out gt 82801BA UO Controller Hub i ICH2 AC ji Link ale Game Port gt CNR j e Digital Controller Connector AAG ST Link nes Creative Labs ES1373 MIDI Interface gt OM10227 Figure 5 Block Diagram of Enhanced PCI Audio Subsystem The Creative Labs ES1373 digital controller with the Crystal Semiconductor CS4297 A codec support the following features e Creative Labs ES1373 AC 97 V1 03 Digital Controller PCI 2 1 compliant PCI bus master for PCI audio 64 voice wavetable synthesizer Aureal A3D
70. d Power States Product Description Under ACPI the operating system directs all system and device power state transitions The operating system puts devices in and out of low power states based on user preferences and knowledge of how devices are being used by applications Devices that are not being used can be turned off The operating system uses information from applications and user settings to put the system as a whole into a low power state Table 9 lists the power states supported by the D815EEA board along with the associated system power targets See the ACPI specification for a complete description of the various system and power states Table 9 Power States and Targeted System Power Global States Sleeping States CPU States Device States Targeted System Power Note 1 GO working SO working CO working DO working Full power gt 30 W state state G1 sleeping S1 CPU stopped C1 stop D1 D2 D3 5W lt power lt 30 W state grant device specification specific G1 sleeping S3 Suspend to No power D3 no power Power lt 5 W Note 2 state RAM Context except for wake saved to RAM up logic G2 S5 S5 Soft off No power D3 no power Power lt 5 W Note 2 Context not saved except for wake Cold boot is up logic required G3 No power to the No power D3 no power for No power to the system so mechanical off system wake up logic that service
71. dress indicates a conflict with another device Mode e Output Only Selects the mode for the parallel port Not available if the e Bi directional Parallel port is disabled default Output Only operates in ATt compatible mode e EPP Bi directional operates in PS 2 compatible mode e ECP EPP is Extended Parallel Port mode a high speed bi directional mode ECP is Enhanced Capabilities Port mode a high speed bi directional mode Base I O address 378 default Specifies the base I O address for the parallel port This feature is present 978 only when Parallel Port is set to Enabled Interrupt e IRQ5 Specifies the interrupt for the parallel port This feature is present IRQ 7 only when Parallel Port default is set to Enabled DMA Channel e 1 Specifies the DMA channel This feature is present 3 default only when Parallel Port Mode is set to ECP Audio Device e Disabled Enables or disables the onboard audio subsystem e Enabled default LAN Device e Disabled Enables or disables the LAN device e Enabled default Legacy USB Support e Disabled Enables or disables USB legacy support Enabled See Section 3 5 on page 90 for more information Auto default 105 Intel Desktop Board D815EEA Technical Product Specification 4 4 4 IDE Configuration Submenu To access this submenu select Advanced on the menu bar then IDE Configuration Maintenance Main Advanced Se
72. e Configuration EE 88 3 3 1 PCI AUTO COMTIQUIATION eege Ew kak xake kak anek e ki Re Ra D REKE KAR 88 3 3 2 PCO MDE SUPPO GE 88 3 4 System Management BIOS GMDBIOE kk kk kk kk K k e Ke 89 3 5 SEL EE SUPPOM erer A Or bute binal d bda eba b ba dar kan k Dina ee 90 3 6 ws ee Dee 90 3 6 1 kanguage SUDDO r EE 91 3 6 2 CUSTOM Splash Cr EE 91 3 7 Recovering BIOS RE 91 3 8 Boot OPON S aae a a E R E kiyak a Rad eee tee 92 3 8 1 CD ROM and Network BOO kk kk kk kK kk kK KK KK 92 3 8 2 Booting Without Attached Devices h iiE kk kk kk kk KS 92 Contents 3 9 Fast Booting Systems with Intel Rapid BIOS Boot 92 3 9 1 Peripheral Selection and Configuration cccceceeeeeeeeeeeeeeeteeeeeeeeeeeeeeee 93 3 9 2 Intel Rapid BIOS Boot civic ees iye ik xu mika k la l dae lika ka k kek anak alla e ke a a kak tates 93 3 9 3 Operating System nre d sunda naa n ye di taya ay aaay ak EE 94 3 10 BIOS Security Features vicisis ses seccveiasiesescdea kk KK KK KK KK KK KK KK KA 94 4 BIOS Setup Program Gi Wee ee EE 97 4 2 Maintenance E EE 98 4 2 1 Extended Configuration Gubmen kk kk kek KS 99 4 3 AMA Men EE 100 H ee WE 101 4 4 1 PCI Configuration SubmenU iid kk kek ee 102 4 4 2 Boot Configuration SUBMENU i ele ae kek K k K KH 103 4 4 3 Peripheral Configuration Gubmenu kk e 104 4 4 4 IDE Configuration Gubmen kk 106 4 4 5 Diskette Configuration SubMenu L EE k
73. elerator card installed in the AGP port gt NOTE In earlier documentation the GPA card was referred to as the AGP Inline Memory Module AIMM DVMT technology uses 1 MB of system physical memory for compatibility with legacy applications An example of this would be when using VGA graphics under DOS Once loaded the operating system and graphics drivers allocate the buffers needed for performing graphics functions When the 4 MB GPA card is installed the Z buffer and GDI data are managed directly from this dedicated graphics memory thereby avoiding operating system memory manager calls and improving performance At system BIOS POST the BIOS displays either the amount of physical memory allocated for display cache or the size of the GPA card 4 MB if installed Operating systems such as Windows NTT 4 0 and Windowst 2000 may display the maximum amount of frame buffer memory possible based on the system memory configuration 31 Intel Desktop Board D815EEA Technical Product Specification 1 8 3 3 AGP Add in Card Support AGP is a high performance interface for graphics intensive applications such as 3D applications While based on the PCI Local Bus Specification Rev 2 1 AGP is independent of the PCI bus and is intended for exclusive use with graphical display devices AGP overcomes certain limitations of the PCI bus related to handling large amounts of graphics data with the following features e Pipelined memory read and write op
74. emory below 1M cleared SOFT RESET Going to clear memory above 1M 4D Memory above 1M cleared SOFT RESET Going to save the memory size Go to check point 52h 4E Memory test started NOT SOFT RESET About to display the first 64k memory size 4F Memory size display started This will be updated during memory test Going for sequential and random memory test 50 Memory testing initialization below 1M complete Going to adjust displayed memory size for relocation shadow 51 Memory size display adjusted due to relocation shadow Memory test above 1M to follow 52 Memory testing initialization above 1M complete Going to save memory size information 53 Memory size information is saved CPU registers are saved Going to enter in real mode 54 Shutdown successful CPU in real mode Going to disable gate A20 line and disable parity NMI 57 A20 address line parity NMI disable successful Going to adjust memory size depending on relocation shadow 58 Memory size adjusted for relocation shadow Going to clear Hit lt DEL gt message 59 Hit lt DEL gt message cleared lt WAIT gt message displayed About to start DMA and interrupt controller test 60 DMA page register test passed To do DMA 1 base register test 62 DMA 1 base register test passed To do DMA 2 base register test 65 DMA 2 base register test passed To program DMA unit 1 and 2 66 DMA unit 1 and 2 programming over To initialize 8259 interrupt co
75. erations that hide memory access latency e Demultiplexing of address and data on the bus for nearly 100 percent efficiency For information about Refer to Obtaining the Accelerated Graphics Port Interface Specification Section 1 3 page 16 1 9 Audio Subsystem Optional The D815EEA board offers two separate audio subsystems Both audio subsystems include these features e Split digital analog architecture for improved S N signal to noise ratio gt 85 dB e Power management support for APM 1 2 and ACPI 1 0 driver dependant e 3 D stereo enhancement Both audio subsystems support the following audio connectors e Inputs Three analog line level stereo inputs for connection from line in CD and auxiliary line in Two analog line level inputs for speakerphone One mono microphone input e Outputs Stereo line level output Mono output for speakerphone 1 9 1 Basic Audio Subsystem 32 The basic audio subsystem consists of the following e Intel 82801BA I O Controller Hub OCH e Analog Devices AD1885 analog codec Figure 4 is a block diagram of the basic audio subsystem The basic audio subsystem supports the following features e 94 dB signal to noise ratio sound quality e Playback sample rates up to 48 kHz e 64 voice synthesizer e Software compatible with Windows 98 Gold and SE Windows 2000 and Windows NT 4 0 e Full duplex operation at asynchronous hardware record playback samples rates e Frequen
76. evices Note 375 AGP and PCI 2 2 slots non wake enabled devices Note 20 USB ports Note 517 5 max CNR Note 375 Note Dependent upon system configuration See the note on the following page NOTE AGP and PCI requirements are calculated by totaling the following e One wake enabled device 375 mA e Five non wake enabled devices 20 mA each PS 2 Ports requirements per the IBM PS 2 Port Specification Sept 1991 e Keyboard 275 mA Actual measurements are 220 mA 300 mA depending on the type of keyboard and the operational state of the keyboard s LEDs e Mouse 70 mA USB requirements are calculated by totaling the following e One wake enabled device 500 mA e Three USB non wake enabled devices 2 5 mA each The USB ports are limited to a combined total of 700 mA CNR requirements are calculated as follows One wake enabled device 375 mA e Non wake enabled devices 20 mA 2 11 4 Fan Connector Current Capability The D815EEA board is designed to supply a maximum of 225 mA per fan connector 79 Intel Desktop Board D815EEA Technical Product Specification 2 11 5 Power Supply Considerations A CAUTION The 5 V standby line for the power supply must be capable of providing adequate 5 V standby current Failure to do so can damage the power supply The total amount of standby current required depends on the wake devices supported and manufacturing options Refer to Section 2 11 3 on page
77. for PCI Local Bus Specification Revision 2 2 e Suspend to RAM support e Wake on PS 2 keyboard and USB ports Support for system wake up using an add in network interface card with remote wake up capability For information about The board s compliance level with APM ACPI Plug and Play and SMBIOS Refer to Section 1 3 page 16 Product Description 1 1 2 Manufacturing Options Table 2 describes the D815EEA board s manufacturing options Table 2 Manufacturing Options Audio LAN Hardware Monitor Subsystem Communication and Networking Riser CNR Two separate Audio Codec 97 AC 97 compatible audio subsystem options e A basic audio subsystem that includes the ICH2 component and an Analog Devices AD1885 analog codec or e An enhanced audio subsystem that includes a Creative Labs ES1373 AC oi digital controller and a Crystal Semiconductor CS4297 stereo audio codec Intel 82562ET 10 100 Mbit sec Platform LAN Connect PLC device e Voltage sense to detect out of range values e Chassis intrusion detect connector e Two fan sense inputs used to monitor fan activity One CNR connector slot shared with PCI bus connector 5 13 Intel Desktop Board D815EEA Technical Product Specification 1 1 3 D815EEA Board Layout Figure 1 shows the location of the major components on the D815EEA board mm DO DW gt GI o A B CD
78. for either an Intel Pentium III processor in a Flip Chip Pin Grid Array FC PGA package or an Intel Celeron processor in an FCPGA package or a PPGA package e Three 168 pin SDRAM Dual Inline Memory Module DIMM sockets e Support for up to 512 MB system memory Single or double sided DIMMs supported Intel 815E Chipset consisting of e Intel 82815E Graphics and Memory Controller Hub GMCH e Intel 82801BA I O Controller Hub ICH2 e Intel 82802AB 4 Mbit Firmware Hub FWH SMSC LPC47M102 LPC bus HO controller e Intel 82815E integrated graphics support e AGP universal connector supporting 1X 2X and 4X AGP cards or a Graphics Performance Accelerator GPA e Digital video output DVO connector Peripheral Interfaces e Four Universal Serial Bus USB ports e Two serial ports e One parallel port e Two IDE interfaces with Ultra DMA ATA 66 100 support e One diskette drive interface e MIDI game port e PS 2t keyboard and mouse ports Expansion Capabilities e Five PCI bus add in card connectors SMBus routed to PCI bus connector 2 e One AGP universal connector BIOS Diagnostic LEDs Instantly Available PC Wake on LANT Technology Connector Intel AMI BIOS resident in the Intel 82802AB 4 Mbit FWH e Support for Advanced Power Management APM Advanced Configuration and Power Interface ACPI Plug and Play and SMBIOS Four dual color LEDs on back panel e Support
79. ge a Supervisor Password Supervisor or Supervisor or and user set options limited number Enter Password user user of options Note If no password is set any user can change all Setup options For information about Refer to Setting user and supervisor passwords Section 4 5 page 112 95 Intel Desktop Board D815EEA Technical Product Specification 96 4 BIOS Setup Program What This Chapter Contains Ce W lle dee e Le e WEE 97 42 Maintenances Me nw tests a Dak aig east ect ak Kak lan eel eas et a es eC 98 sti Maln Melik 4x2332 cathe cen adie Nate dee oe ade eti K Wae Ee 100 AA Advanced Men 101 E E EE 112 SG Power MON DN Do A ea ra r r r raXrrWararr N 113 4T 5 e Tol iw jv lela EE 114 NN DN len DY DD rrr ge 116 4 1 Introduction The BIOS Setup program can be used to view and change the BIOS settings for the computer The BIOS Setup program is accessed by pressing the lt F2 gt key after the Power On Self Test POST memory test begins and before the operating system boot begins The menu bar is shown below Maintenance Main Advanced Security Power Boot Exit Table 60 lists the BIOS Setup program menu features Table 60 BIOS Setup Program Menu Bar Maintenance Main Advanced Security Power Boot Exit Clears Allocates Configures Sets Configures Selects boot Saves or passwords and resources for advanced passwords power options and discards BIS credentials
80. ger used USB Legacy support can be left enabled or set to Auto in the BIOS Setup program if needed NOTE USB legacy support is for keyboards mice and hubs only Other USB devices are not supported BIOS Updates A new version of the BIOS can be updated from a 1 44 MB diskette from a legacy diskette drive or an LS 120 diskette drive or a CD ROM using the Intel Flash Memory Update Utility that is available from Intel This utility supports the following BIOS maintenance functions e Updating the flash BIOS from a file on a diskette or a CD ROM e Changing the language section of the BIOS e Verifying that the updated BIOS matches the target system to prevent accidentally installing an incompatible BIOS e Updating the BIOS boot block e Inserting a user logo Updating the flash BIOS from a file automatically updates both the BIOS boot block and the main BIOS This process is fault tolerant to prevent boot block corruption The BIOS boot block may also be updated separately if selected in the update menu BIOS upgrades and the Intel Flash Memory Update Utility are available from Intel through the Intel World Wide Web site Overview of BIOS Features lt gt NOTE Please review the instructions distributed with the upgrade utility before attempting a BIOS update For information about Refer to The Intel World Wide Web site Section 1 2 page 16 3 6 1 Language Support The BIOS Setup program and help messages are supported in five
81. guration No options If Used is displayed User Defined has been selected in Extended Configuration under the Maintenance Menu PCI Configuration No options Configures individual PCI slot s IRQ priority When selected displays the PCI Configuration submenu Boot Settings No options Configures Plug and Play and the Numlock key and resets Configuration configuration data When selected displays the Boot Configuration submenu Peripheral Configuration No options Configures peripheral ports and devices When selected displays the Peripheral Configuration submenu IDE Configuration Specifies type of connected IDE device Diskette Configuration No options When selected displays the Diskette Configuration submenu Event Log Configuration No options Configures Event Logging When selected displays the Event Log Configuration submenu Video Configuration No options Configures video features When selected displays the Video Configuration submenu 101 Intel Desktop Board D815EEA Technical Product Specification 4 4 1 PCI Configuration Submenu To access this submenu select Advanced on the menu bar then PCI Configuration Maintenance Main Advanced Security Power Boot Bag PCI Configuration Boot Configuration Periphera Configuration IDE Configuration Diskette Configuration Event Log Configuration Video Configuration The submenu represented by Ta
82. hardware features and security management power supply changes to and enables components available features features controls Setup extended through the program configuration chipset options mode lt gt NOTE In this chapter all examples of the BIOS Setup Program menu bar include the maintenance menu however the maintenance menu is displayed only when the board is in configuration mode Section 2 9 on page 73 tells how to put the board in configuration mode 97 Intel Desktop Board D815EEA Technical Product Specification Table 61 lists the function keys available for menu screens Table 61 BIOS Setup Program Function Keys BIOS Setup Program Function Key Description lt gt 0f lt gt gt Selects a different menu screen Moves the cursor left or right lt T gt or lt gt Selects an item Moves the cursor up or down lt Tab gt Selects a field Not implemented lt Enter gt Executes command or selects the submenu lt F9 gt Load the default configuration values for the current menu lt F10 gt Save the current values and exits the BIOS Setup program lt Esc gt Exits the menu 4 2 Maintenance Menu To access this menu select Maintenance on the menu bar at the top of the screen Maintenance Main Advanced Security Power Boot Er Extended Configuration The menu shown in Table 62 is for clearing Setup passwords and enabling extended configuration mode Setup only displays this menu in configura
83. hassis intrusion detect connector The mechanical switch is closed for normal computer operation For information about Refer to The location of the chassis intrusion detect connector Figure 10 page 59 The signal names of the chassis intrusion detect connector Table 37 page 62 1 12 3 Fan Control and Monitoring 38 The SMSC LPC47M102 I O controller provides two fan control outputs and two fan tachometer inputs Monitoring and control can be implemented using third party software For information about Refer to The functions of the fan connectors Section 1 13 2 2 page 43 The location of the fan connectors Figure 10 page 59 The signal names of the fan connectors Section 2 8 2 2 page 59 Product Description 1 13 Power Management Power management is implemented at several levels including e Software support Advanced Power Management APM Advanced Configuration and Power Interface ACPI e Hardware support Power connector Fan connectors Wake on LAN technology Instantly Available technology Resume on Ring Wake from USB Wake on Keyboard Wake on PME 1 13 1 Software Support The software support for power management includes e APM e ACPI If the D815EEA board is used with an ACPI aware operating system the BIOS can provide ACPI support Otherwise it defaults to APM support 1 13 1 1 APM APM makes it possible for the computer to enter an energy saving standby mode
84. ics of Information Technology Equipment International VCCI Class B ITE Implementation Regulations for Voluntary Control of Radio Interference by Data Processing Equipment and Electronic Office Machines Japan EN55022 1994 Class B Limits and methods of measurement of Radio Interference Characteristics of Information Technology Equipment Europe EN50082 1 1992 Generic Immunity Standard currently compliance is determined via testing to IEC 801 2 3 and 4 Europe ICES 003 1997 Interference Causing Equipment Standard Digital Apparatus Class B Including CRC c 1374 Canada AS NZ 3548 Australian Communications Authority ACA Standard for Electromagnetic Compatibility Technical Reference 2 15 3 Certification Markings This printed circuit assembly has the following markings related to product certification UL Joint Recognition Mark Consists of small c followed by a stylized backward UR and followed by a small US Component side Manufacturer s recognition mark Consists of a unique UL recognized manufacturer s logo along with a flammability rating 94V 0 Solder side UL File Number for D815EEA boards E139761 Component side PB Part Number Intel bare circuit board part number Solder side PBA10641 001 Battery Side Up marking located on the component side of the D815EEA board in close proximity to the battery holder FCC Logo Declaration Solder side ACA C Tick mark Consists of a
85. ing TMDS transmitter to enable platform support for DVI compliant digital displays or with a discrete TV encoder for TV Out functionality For information about Refer to The location of the DVO connector Figure 10 page 59 The signal names of the DVO connector Table 33 page 61 30 Product Description 1 8 3 AGP Universal Connector The AGP universal connector supports either e Graphics Performance Accelerator GPA cards with 133 MHz SDRAM display cache e AGP add in cards with either 3 3 V or 1 5 V I O For information about Refer to The location of the AGP universal connector Figure 11 page 63 The signal names of the AGP universal connector Table 41 page 66 1 8 3 1 Graphics Performance Accelerator GPA Support The Intel 815E GMCH display cache is a single channel 32 bit wide SDRAM interface The 4 MB display cache resides on a GPA card that plugs into the AGP connector The BIOS detects a GPA card if present in the AGP port and initializes it as display cache memory When a GPA card is initialized the BIOS allocates 1 MB of system memory to support the internal display device operation 1 8 3 2 Dynamic Video Memory Technology DVMT DVMT enables enhanced graphics and memory performance through Direct AGP and highly efficient memory utilization DVMT ensures the most efficient use of all available memory for maximum 2D 3D graphic performance DVMT is implemented on the D815EEA board with a GPA Graphics Performance Acc
86. k ke H 109 4 4 6 Event Log Configuration Submenu kk kk e 110 4 4 7 Video Configuration Gubmen kk kk kk kk 111 EI E EE 112 4 6 Power Men nereh a a eege 113 Be Boot N eene eege EE 114 4 7 1 IDE Drive Configuration SubmenuU kk kk 115 Ze San Se YR A U N DD sli sain eebe Ach tigi ee thane eat yas 116 5 Error Messages and Beep Codes 5 1 BIOS Error d e GE 116 5 2 Port 80h RE 119 5 3 Bus Initialization Checkpoints EE 123 54 Speaker crc d ey n e lee denen cael eve idoiucn Gates note neat einen Se 124 5 5 BIOS Beep G de Siriara ekr hated E cane Ke NABINE dee anoles uae 124 5 6 DI gnOSHC LEDS EE 125 Figures 1 D815EEA Board Components EEE EEE aioe DEEN DANCE 14 Dol e TEE 15 3 Intel 815E Chipset Block Diagram ENEE 22 4 Block Diagram of Basic Audio Subsystem LLE EE kk k kek 33 5 Block Diagram of Enhanced PCI Audio Subsystem eee 33 6 ICH2 and CNR Signal Interface LL E eee 37 7 Using the Wake on LAN Technology Connector sssssessesssserrreessseernnresserrrrrnnerrrnne 44 8 Location of Standby Power Indicator LED A 45 9 Back Panel Connectors eeseeaseege egen ENEE Ee e gege EEN hee 54 10 Audio Video Hardware Control and Fan Connectors M E 59 11 Add in Board and Peripheral Interface CGonnechors 63 EE ue EN Ree 69 13 Location of the Jumper Block E 73 vii Intel Desktop Board D815EEA Technical Product Specificati
87. languages US English German Italian French and Spanish The default language is US English which is present unless another language is selected in the BIOS Setup program 3 6 2 Custom Splash Screen During POST an Intel splash screen is displayed by default This splash screen can be replaced with a custom splash screen A utility is available from Intel to assist with creating a custom splash screen The custom splash screen can be programmed into the flash memory using the BIOS upgrade utility Information about this capability is available on the Intel Support World Wide Web site See Section 1 2 for more information about this site 3 7 Recovering BIOS Data Some types of failure can destroy the BIOS For example the data can be lost if a power outage occurs while the BIOS is being updated in flash memory The BIOS can be recovered from a diskette using the BIOS recovery mode When recovering the BIOS be aware of the following e Because of the small amount of code available in the non erasable boot block area there is no video support You can only monitor this procedure by listening to the speaker or looking at the diskette drive LED e The recovery process may take several minutes larger BIOS flash memory devices require more time e Two beeps and the end of activity in the diskette drive indicate successful BIOS recovery e A series of continuous beeps indicates a failed BIOS recovery To create a BIOS recovery diskette a bo
88. mes of the legacy style 2 mm connector Table 39 page 60 34 Product Description 1 9 3 2 ATAPI CD ROM Audio Connector A 1 x 4 pin ATAPI style connector connects an internal ATAPI CD ROM drive to the audio mixer For information about Refer to The location of the ATAPI CD ROM connector Figure 10 page 59 The signal names of the ATAPI CD ROM connector Table 30 page 60 1 9 3 3 Telephony Connector A 1 x 4 pin ATAPI style connector connects the monoaural audio signals of an internal telephony device to the audio subsystem A monaural audio in and audio out signal interface is necessary for telephony applications such as speakerphones fax modems and answering machines For information about Refer to The location of the telephony connector Figure 10 page 59 The signal names of the telephony connector Table 32 page 60 1 9 3 4 Auxiliary Line In Connector A 1 x 4 pin ATAPI style connector connects the left and right channel signals of an internal audio device to the audio subsystem For information about Refer to The location of the auxiliary line in connector Figure 10 page 59 The signal names of the auxiliary line in connector Table 31 page 60 1 10 LAN Subsystem The Network Interface Controller subsystem consists of the ICH2 with integrated LAN Media Access Controller and a physical layer interface device Feature of the LAN subsystem include e PCI Bus Master Interface e CSMA CD Protocol Engine e Serial C
89. n card with a remote boot ROM installed For information about Refer to The El Torito specification Section 1 3 page 16 3 8 2 Booting Without Attached Devices For use in embedded applications the BIOS has been designed so that after passing the POST the operating system loader is invoked even if the following devices are not present e Video adapter e Keyboard e Mouse 3 9 Fast Booting Systems with Intel Rapid BIOS Boot 92 There are three factors that affect system boot speed e Selecting and configuring peripherals properly e Using an optimized BIOS such as the Intel Rapid BIOS e Selecting a compatible operating system The BIOS is not configured by default to boot at the fastest possible speed Empirical measurements have shown that some Intel Desktop boards when optimized as described above can complete POST Power On Self Test in six seconds or less and boot to an active Microsoft Windows Millennium Me operating system in 21 seconds Overview of BIOS Features In addition to the appliance like speed that benefits end users fast booting systems can also increase an OEMs manufacturing line throughput 3 9 1 Peripheral Selection and Configuration The following techniques will help speed system boot 3 9 2 Choose a hard drive with parameters such as power up to data ready less than eight seconds to minimize hard drive startup delays The Western Digital Caviar AA or BA series are examples
90. nce Revision 1 2A http www intel com Detect SPD December 1997 design pcisets memory Specification Intel Corporation SMBIOS System Management Version 2 3 http developer intel com BIOS August 12 1998 ial wfm design smbios Award Software International Inc Dell Computer Corporation Hewlett Packard Company Intel Corporation International Business Machines Corporation Phoenix Technologies Limited American Megatrends Inc and SystemSoft Corporation UHCI Universal Host Controller Version 1 1 http www usb org Interface Design Guide March 1996 developers Intel Corporation USB Universal Serial Bus Version 1 1 http www usb org Specification September 23 1998 developers Compag Computer Corporation Intel Corporation Microsoft Corporation and NEC WfM Wired for Management Version 2 0 http developer intel com 18 Baseline December 18 1998 Intel Corporation ial WfM wfmspecs htm Product Description 1 4 Processor Jh CAUTION The D8I5EEA board supports processors that have an 18 2 A maximum current draw with a 1 65 to 2 0 V core voltage Using a processor not in compliance with the above guidelines can damage the processor the D8ISEEA board and the power supply See the processor s data sheet for voltage and current usage requirements The D815EEA board supports a single Pentium lll or Celeron processor The system bus speed is automatically selected The D815EEA board supports the proce
91. nd reports if the two match For information about Refer to The D815EEA board s compliance level with APM and Plug and Play Section 1 3 page 16 87 Intel Desktop Board D815EEA Technical Product Specification 3 2 BIOS Flash Memory Organization The Intel 82802AB Firmware Hub FWH includes a 4 Mbit 512 KB symmetrical flash memory device Internally the device is grouped into eight 64 KB blocks that are individually erasable lockable and unlockable 3 3 Resource Configuration 3 3 1 PCI Autoconfiguration The BIOS can automatically configure PCI devices PCI devices may be onboard or add in cards Autoconfiguration lets a user insert or remove PCI cards without having to configure the system When a user turns on the system after adding a PCI card the BIOS automatically configures interrupts the I O space and other system resources Any interrupts set to Available in Setup are considered to be available for use by the add in card PCI interrupts are distributed to available ISA interrupts that have not been assigned to system resources The assignment of PCI interrupts to ISA IRQs is non deterministic PCI devices can share an interrupt but an ISA device cannot share an interrupt allocated to PCI or to another ISA device Autoconfiguration information is stored in ESCD format For information about the versions of PCI and Plug and Play supported by the BIOS see Section 1 3 3 3 2 PCI IDE Support 88 If you selec
92. ng with another computer on the LAN 1 10 3 LAN Subsystem Software LAN software and drivers are available from Intel s World Wide Web site For information about Refer to Obtaining LAN software and drivers Section 1 2 page 16 1 11 CNR Optional The CNR connector supports the audio modem USB and LAN interfaces of the Intel 815E chipset Figure 6 shows the signal interface between the riser and the ICH2 36 Product Description AC 97 Interface 5 R 9 Communication and Intel 82801BA l LAN Interfaces z Networking Riser I O Controller Hub j SMBus l 8 ICH2 x Up to two AC 97 codecs lt USB gt Z and one LAN device Power OM10412 Figure 6 ICH2 and CNR Signal Interface lt gt NOTE The USB interface from the ICH2 to the CNR is not supported on this board The interfaces supported by the CNR connector include but are not limited to the following e AC 97 interface supports audio and or modem functions on the CNR board e LAN interfaces provides one of two LAN interfaces for networking functions Interfaces include an eight pin interface for use with Platform LAN Connection PLC based devices and a 17 pin interface for Media Independent Interface MII based devices commonly referred to as a PHY e SMBus interface provides Plug and Play functionality for the CNR board The CNR connector includes power signals required for power m
93. nnectors Table 43 page 68 BIOS Setup program s Boot menu Table 76 page 114 1 6 2 2 USB 24 The ICH2 contains two separate USB controllers The D815EEA board has four USB ports one USB peripheral can be connected to each port For more than four USB devices an external hub can be connected to any of the ports Two of the USB ports are implemented with stacked back panel connectors the other two are accessible via the front panel USB connector at location J8C1 The D815EEA board fully supports UHCI and uses UHCI compatible software drivers NOTE Computer systems that have an unshielded cable attached to a USB port may not meet FCC Class B requirements even if no device or a low speed USB device is attached to the cable Use Shielded cable that meets the requirements for full speed devices For information about Refer to The location of the USB connectors on the back panel Figure 9 page 54 The signal names of the back panel USB connectors Table 20 page 55 The location of the front panel USB connector l Figure 12 page 69 The signal names of the front panel USB connector Table 44 page 70 The USB specification and UHCI Section 1 3 page 16 Product Description 1 6 2 3 Real Time Clock CMOS SRAM and Battery The real time clock provides a time of day clock and a multicentury calendar with alarm features The real time clock supports 256 bytes of battery backed CMOS SRAM in two banks that are reserved for BI
94. ns to its last known wake state Table 10 on page 42 lists the devices and events that can wake the computer from the S3 state The D815EEA board supports the PCI Bus Power Management Interface Specification For information on the versions of this specification see Section 1 3 Add in boards that also support this specification can participate in power management and can be used to wake the computer The use of Instantly Available technology requires operating system support and PCI 2 2 compliant add in cards and drivers The standby power indicator LED shows that power is still present at the DIMM and PCI bus connectors even when the computer appears to be off Figure 8 shows the location of the standby power indicator LED OM10042 Figure 8 Location of Standby Power Indicator LED 45 Intel Desktop Board D815EEA Technical Product Specification 1 13 2 5 Resume on Ring The operation of Resume on Ring can be summarized as follows Resumes operation from either the APM sleep mode or the ACPI S1 state Requires only one call to
95. ntroller 7F Extended NMI sources enabling is in progress 80 Keyboard test started Clearing output buffer checking for stuck key to issue keyboard reset command 81 Keyboard reset error stuck key found To issue keyboard controller interface test command 82 Keyboard controller interface test over To write command byte and init circular buffer 83 Command byte written global data init done To check for lock key continued 121 Intel Desktop Board D815EEA Technical Product Specification 122 Table 82 Runtime Code Uncompressed in F000 Shadow RAM continued Code Description of POST Operation 84 Lock key checking over To check for memory size mismatch with CMOS 85 Memory size check done To display soft error and check for password or bypass setup 86 Password checked About to do programming before setup 87 Programming before setup complete To uncompress SETUP code and execute CMOS setup 88 Returned from CMOS setup program and screen is cleared About to do programming after setup 89 Programming after setup complete Going to display power on screen message 8B First screen message displayed lt WAIT gt message displayed PS 2 Mouse check and extended BIOS data area allocation to be done 8C Setup options programming after CMOS setup about to start 8D Going for hard disk controller reset 8F Hard disk controller reset done Floppy setup to be done next
96. o identify the routines under execution In these WORD checkpoints the low byte of the checkpoint is the system BIOS checkpoint from which the control is passed to the different bus routines The high byte of the checkpoint is the indication of which routine is being executed in the different buses Table 84 describes the upper nibble of the high byte and indicates the function that is being executed Table 84 Upper Nibble High Byte Functions Value Description func 0 disable all devices on the bus concerned func 1 static devices init on the bus concerned func 2 output device init on the bus concerned func 3 input device init on the bus concerned func 4 IPL device init on the bus concerned func 5 general device init on the bus concerned func 6 error reporting for the bus concerned func 7 add on ROM init for all buses N oa A oO N 123 Intel Desktop Board D815EEA Technical Product Specification Table 85 describes the lower nibble of the high byte and indicates the bus on which the routines are being executed Table 85 Lower Nibble High Byte Functions Value Description Generic DIM Device Initialization Manager On board System devices ISA devices EISA devices ISA PnP devices PCI devices on A Ww N 5 4 Speaker A 47 Q inductive speaker is mounted on the D815EEA board The speaker provides audible
97. o may result in damage to the voltage regulator circuit Figure 16 shows the locations of the localized high temperature zones OM10049 Processor voltage regulator area Processor Intel 82815E GMCH Intel 82801BA ICH2 Creative Labs ES1373 digital controller m 0 O U gt Figure 16 Localized High Temperature Zones 81 Intel Desktop Board D815EEA Technical Product Specification Table 55 provides maximum case temperatures for D815EEA board components that are sensitive to thermal changes Case temperatures could be affected by the operating temperature current load or operating frequency Maximum case temperatures are important when considering proper airflow to cool the D815EEA board Table 55 Thermal Considerations for Components Component Maximum Case Temperature Intel Pentium III processor For processor case temperature see processor Intel Celeron processor datasheets and processor specification updates Intel 82815E GMCH 116 C under bias Intel 82801BA ICH2 109 C under bias Creative Labs ES1373 70 C For information about _Refer to Intel Pentium III processor datasheets and spe
98. oard D815EEA Technical Product Specification Table 41 AGP Universal Connector J5E1 Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name Ai Laun No Connect A34 Vcc3 3 B34 Vcc3 3 A3 TYPEDET B2 Vec A35 AD22 B35 AD21 A3 Reseved B3 ver A36 AD20 B36 AD19 A4 NoConnectt B4 No Connect A37 Ground B37 Ground A5 Ground B5 Ground A38 AD18 B38 AD17 Ae TINTA S B6 INTB A39 AD16 B39 C BE2 A7 RST Je CLK A40 Vcc3 3 B40 Vcc3 3 A8 GNT1 B8 REQ A41 FRAME B41 IRDY A9 Vcc3 3 B9 Vcc3 3 A42 Reserved B42 3 3 V aux Ain sm Bin ISTO A43 Ground B43 Ground A11 Reserved B11 ST2 A44 Reserved B44 Reserved A12 PIPE B12 RBF A45 Vcc3 3 B45 Vcc3 3 A13 Ground B43 Ground A46 TRDY B46 DEVSEL A14 WBF B14 No Gonnect A47 STOP B47 Vcc3 3 A15 SBAT B15 SBAO A48 PME B48 PERR A16 ven Big Vec9 3 A49 Ground B49 Ground A17 Spa B17 SBA2 A50 PAR B50 SERR A18 SBSTB B18 SB STB A51 AD15 B51 C BE1 A19 Ground B19 Ground A52 Vcc3 3 B52 Vcc3 3 Aan SBA5 B20 SBA4 A53 AD13 B53 AD14 A21 Spa B21 SBA6 A54 AD11 B54 AD12 A22 Key B22 Key A55 Ground B55 Ground A23 Key B23 Key A56 AD9 B56 AD10 A24 Key B24 33 3 V aux A57 C BE0 B57 AD8 A25 Key B25_ Key A58 Vcc3 3 B58 Vcc3 3 A26 1 AD30 B26 TAD31 A59 AD_STBO B59 AD_STBO A27 TAD28 J B27 AD29 A60 AD6 B60 AD7 A28 ven B28 Vcc9 3 A61 Ground B61 Ground A29 TAD26 JB29 AD 27 A62 AD4 B62 AD5 Aan TAD
99. oard has the following expansion slots One Accelerated Graphics Port ATX Expansion slot 6 A 4X AGP retention mechanism can be installed during board manufacturing at OEM request Five PCI Local Bus slots compliant with PCI rev 2 2 specification The SMBus is routed to PCI bus connector 2 only ATX Expansion slot 4 PCI add in cards with SMBus support can access sensor data and other information residing on the desktop board One CNR optional shared with PCI bus connector 5 ATX Expansion slot 1 This document references back panel slot numbering with respect to processor location on the desktop board The AGP slot is identified as AGP and is not numbered PCI slots are identified as PCI slot x starting with the slot closest to the processor The CNR slot shares a PCI slot number The ATX MicroATX specifications identify expansion slot locations with respect to the far edge of a full sized ATX chassis The ATX specification and the board s silkscreen are opposite and could cause confusion The ATX numbering convention is made without respect to slot type PCI vs AGP but refers to an actual slot location on a chassis Figure 11 on page 63 illustrates the board s PCI slot numbering Technical Reference 2 8 2 2 Audio Video Power and Hardware Control Connectors Figure 10 shows the location of the audio video power and hardware control connectors
100. oller 5 16 bits Open 6 16 bits Open 7 16 bits Open 2 5 PCI Configuration Space Map Table 15 PCI Configuration Space Map Bus Device Function Number hex Number hex Number hex Description 00 00 00 Memory controller of Intel 82815E component 00 01 00 PCI to AGP bridge 00 02 00 Intel 82815E GMCH graphics memory controller hub 00 1E 00 Hub link to PCI bridge 00 1F Intel 82801BA ICH2 PCI to LPC bridge 00 HEF 01 IDE controller 00 1F 02 USB 00 1F 03 SMBus controller 00 1F 04 USB 00 1F 05 AC 97 audio controller optional 00 1F 06 AC 97 modem controller optional 01 Note 00 00 Add in AGP adapter card 01 02 Note 07 00 Creative Labs ES1373 digital controller 01 02 Note 08 00 LAN controller optional 01 02 Note 09 00 PCI bus connector 1 J4E1 01 02 Note 0A 00 PCI bus connector 2 J4D1 01 02 Note 0B 00 PCI bus connector 3 J4C1 01 02 Note oC 00 PCI bus connector 4 J4B1 01 02 Note OD 00 PCI bus connector 5 J4A1 Note If an add in AGP card is installed it occupies PCI Bus 01 and the other devices occupy PCI Bus 02 If no add in AGP card is installed these PCI devices occupy PCI Bus 01 50 2 6 2 7 Technical Reference Interrupts Table 16 Interrupts IRQ System Resource NMI I O channel check 0 Reserved interval timer 1 Reserved keyboard buffer full 2 Reserved
101. om the PCI and or USB buses exceeds power supply capacity the board may lose register settings stored in memory and may not awaken properly To estimate the standby current required for a specific system configuration the standby current requirements of all installed components must be combined Refer to Table 54 and follow these steps 1 List the board s standby current requirement 767 mA 2 List the PS 2 ports standby current requirement see note below 3 List from the AGP and PCI 2 2 slots wake enabled devices row the total number of wake enabled devices installed and multiply by the standby current requirement 4 List from the AGP and PCI 2 2 slots non wake enabled devices row the total number of wake enabled devices installed and multiply by the standby current requirement 5 List all additional wake enabled devices and non wake enabled devices standby current requirements as applicable 6 Add all the listed standby current totals from steps 1 through 5 to determine the total estimated standby current power supply requirement Technical Reference Table 54 Standby Current Requirements Instantly Available Current Support Standby Current Requirements Description Requirements mA Minimum Total for the board 767 Optional Onboard LAN optional 95 WOL header connected to wake enabled PCI LAN card 525 PS 2 ports Note 345 AGP and PCI 2 2 slots wake enabled d
102. on Tables viii 14 15 16 D815EEA Board BR en EE EE 75 Or Shiela DIMENSIONS emeni iia a ide k ra kine ke d ra hi s ue e kan kiry ad 76 Localized High Temperature Zones AE 81 IWER EE 125 Feature and E 12 Manufacturing Klee 13 ae een EE 16 Supported Bee 19 Supported Memory Configurations E Ek kk ek kk k kK KK KK nnn 21 Supported Graphics Refresh Frequencies e 29 LAN Connector LED States gege Seege ENNEN ENER 36 Effects of Pressing the Power Switch L Ek eg de 40 Power States and Targeted System Power 41 Wake Up Devices and Events M E GAEREN KK KK KAK KK kK 42 Fan Connector DESEMDUONS EE 43 System Memory MAp i kk kk kk Sree cee ae ea AK KK eee 47 PVN E EE 48 DIMA eu 50 PCI Configuration Space Map E e Seege ENEE EE Ee k KK KK KA 50 Interrupts EE 51 PCI Interrupt Routing Mar eege Seege EE Ra KK kK kK KK KK KH 52 PS 2 Mouse Keyboard ConnectOrS E id kk kk kk k kk kk KK KK KK 55 LAIN GOMMOCION RNN Derg g_rr pg 55 USB C onnectOrS E Eu eh EE EE KK KK KK KK kK 55 VGA ee Ree 56 Parallel Port Connector sass 45k yi2d ezz ar Ra Sir ERA Ey y yeda H ZA en ees 56 serial Port Gonn6 lO seras SCHEER KAN karke buk ka r kk Kak SAB NA dn K k KAK bee 56 MIDI Game Port Connector ege gue ee eegene KK KK KA 57 Audio Line Out Connector ENEE 57 Audio Line ln Conn GO eege kx2 k lr almak alla kar ikakan aka ls eka s r kawa bal dae k
103. on The submenu represented in Table 73 is for configuring the video features Table 73 Video Configuration Submenu Options Description Feature Primary Video Adapter AGP default Selects primary video adapter to be used during e PCI boot 111 Intel Desktop Board D815EEA Technical Product Specification 4 5 Security Menu 112 To access this menu select Security from the menu bar at the top of the screen Maintenance Main Advanced Security Power Boot eg The menu represented by Table 74 is for setting passwords and security features Table 74 Security Menu If no password entered previously Feature Options Description Supervisor Password Is Reports if there is a supervisor password set User Password Is Reports if there is a user password set Set Supervisor Password Password can be up to seven Specifies the supervisor password alphanumeric characters Set User Password Password can be up to seven Specifies the user password alphanumeric characters Clear User Password Yes default Clears the user password Note 1 e No User Access Level e Limited Sets BIOS Setup Utility access rights for user Note 2 e No Access level e View Only e Full default Unattended Start e Enabled Enabled allows system to complete the boot Note 1 Disabled default process without a password The keyboard remains locked until a password is entered A password is required to boot f
104. ord gives restricted access to view and change Setup options in the BIOS Setup program This is the user mode e If only the supervisor password is set pressing the lt Enter gt key at the password prompt of the BIOS Setup program allows the user restricted access to Setup e If both the supervisor and user passwords are set users can enter either the supervisor password or the user password to access Setup Users have access to Setup respective to which password is entered e Setting the user password restricts who can boot the computer The password prompt will be displayed before the computer is booted If only the supervisor password is set the computer boots without asking for a password If both passwords are set the user can enter either password to boot the computer 94 Overview of BIOS Features Table 59 shows the effects of setting the supervisor password and user password This table is for reference only and is not displayed on the screen Table 59 Supervisor and User Password Functions Supervisor Password to Password Password Set Mode User Mode Setup Options Enter Setup During Boot Neither Can change all Can change all None None None options Note options Note Supervisor Can change all Can change a Supervisor Password Supervisor None only options limited number of options User only N A Can change all Enter Password User User options Clear User Password Supervisor Can change all Can chan
105. otable diskette must be created and the BIOS update files copied to it BIOS upgrades and the Intel Flash Memory Upgrade utility are available from Intel Customer Support through the Intel World Wide Web site lt gt NOTE If the computer is configured to boot from an LS 120 diskette in the Setup program s Removable Devices submenu the BIOS recovery diskette must be a standard 1 44 MB diskette not a 120 MB diskette 91 Intel Desktop Board D815EEA Technical Product Specification For information about Refer to The BIOS recovery mode jumper settings Table 51 page 12 The Boot menu in the BIOS Setup program Section 4 7 page 114 Contacting Intel customer support Section 1 2 page 16 3 8 Boot Options In the BIOS Setup program the user can choose to boot from a diskette drive hard drives CD ROM or the network The default setting is for the diskette drive to be the first boot device the hard drive second and the ATAPI CD ROM third The fourth device is disabled 3 8 1 CD ROM and Network Boot Booting from CD ROM is supported in compliance to the El Torito bootable CD ROM format specification Under the Boot menu in the BIOS Setup program ATAPI CD ROM is listed as a boot device Boot devices are defined in priority order If the CD ROM is selected as the boot device it must be the first device with bootable media The network can be selected as a boot device This selection allows booting from a network add i
106. ovides full ACPI support 1 13 2 1 Power Connector When used with an ATX compliant power supply that supports remote power on off the D815EEA board can turn off the system power through software control To enable soft off control in software advanced power management must be enabled in the BIOS Setup program and in the operating system When the system BIOS receives the correct APM command from the operating system the BIOS turns off power to the computer With soft off enabled if power to the computer is interrupted by a power outage or a disconnected power cord when power resumes the computer returns to the power state it was in before power was interrupted on or off The computer s response can be set using the After Power Failure feature in the BIOS Setup program s Boot menu For information about Refer to The location of the power connector Figure 10 page 59 The signal names of the power connector Table 35 page 61 The BIOS Setup program s Boot menu Table 76 page 114 The ATX specification Section 1 3 page 16 1 13 2 2 Fan Connectors The D815EEA board has three fan connectors The functions of these connectors are described in Table 11 Table 11 Fan Connector Descriptions Connector Function System fan fan 1 Provides 12 V DC for a system or chassis fan The fan voltage can be switched on or off depending on the power management state of the computer A tachometer feedback connection is also provided
107. p support intel com support motherboards desktop Find Processor Data Sheets or information about Proper Date Access in Systems with Intel Motherboards at these World Wide Web sites http www intel com design litcentr http support intel com support year2000 Find information about the ICH addressing at this World Wide Web site http developer intel com design chipsets datashts Design Specifications Table 3 lists the specifications applicable to the D815EEA board Table 3 Specifications Reference Specification Version Revision Date The information is Name Title and Ownership available from AC 97 Audio Codec 97 Version 2 1 ftp download intel com May 1998 pc supp platform ac97 Intel Corporation ACPI Advanced Configuration Version 1 0b http www teleport com acpi and Power Interface February 1 1999 Specification Intel Corporation Microsoft Corporation and Toshiba Corporation AGP Accelerated Graphics Port Version 2 0 the Accelerated Graphics Interface Specification May 4 1998 Implementers Forum at Intel Corporation http www agpforum org AIMM AGP Inline Memory Module Version 0 9 http developer intel com for Graphics March 2000 technology memory aimm Performance Intel Corporation index htm Accelerator Intel document order number cards 298177 003 AMI BIOS American Megatrends AMIBIOS 99 http Awww amibios com or BIOS Specification 1999 htt
108. p Awww ami com download American Megatrends Inc amibios99 pdf APM Advanced Power Version 1 2 http www microsoft com Management BIOS February 1996 hwdev busbios amp_12 htm Interface Specification Intel Corporation Microsoft Corporation continued Product Description Compaq Computer Corp Phoenix Technologies Ltd and Intel Corporation Table 3 Specifications continued Specification Version Revision Date and The information is Description Title Ownership available from ATA 3 Information Technology Version 6 ATA Anonymous FTP Site AT Attachment 3 October 1995 ftp www dt wdc com ata Interface ASC X3T10 Technical ata 3 X3T10 2008D Committee ATAPI Information Technology Version 18 T13 Anonymous FTP Site AT Attachment with August 19 1998 ftp fission dt wdc com Packet Interface Contact T13 Chair x3t13 project Extensions Seagate Technology d1153r18 pdf T13 1153D ATX ATX Specification Version 2 01 http developer intel com February 1997 design motherbd atx htm Intel Corporation CNR Communication and Version 1 0 http developer intel com Network Riser CNR February 7 2000 technology cnr index htm Specification Intel Corporation EPP Enhanced Parallel Port Version 1 7 http standards ieee org IEEE std 1284 1 1997 1997 reading ieee std_public Institute of Electrical and description busarch Electronic Engineers 1284 1 19
109. ptions Displays the version of the BIOS Processor Type No options Displays processor type Processor Speed No options Displays processor speed System Bus No options Displays the system bus frequency Frequency Cache RAM No options Displays the size of second level cache and whether it is ECC capable Total Memory No options Displays the total amount of RAM Memory Bank 0 No options Displays the amount and type of RAM in the memory Memory Bank 1 banks Memory Bank 2 Language e English default Selects the current default language used by the BIOS e Espanol e Deutsch Processor Serial e Disabled default Enables and disables the processor serial number Number e Enabled Present only when a Pentium III processor is installed System Time Hour minute and Specifies the current time second System Date Day of week Specifies the current date Month day year 100 BIOS Setup Program 4 4 Advanced Menu To access this menu select Advanced on the menu bar at the top of the screen Maintenance Main Advanced Security Power Boot E l PCI Configuration Boot Configuration Peripheral Configuration IDE Configuration Diskette Configuration Event Log Configuration Video Configuration Table 65 describes the Advanced Menu This menu is used for setting advanced features that are available through the chipset Table 65 Advanced Menu Feature Options Description Extended Confi
110. r information about Refer to The SCSI hard drive activity LED connector Section 2 8 3 1 page 70 2 8 3 3 4 Power Sleep Message Waiting LED Connector Pins 2 and 4 can be connected to a single or dual colored LED Table 49 shows the possible states for a single colored LED Table 50 shows the possible states for a dual colored LED 71 Intel Desktop Board D815EEA Technical Product Specification Table 49 States for a Single Colored Power LED LED State Description Off Power off sleeping Steady Green Running Blinking Green Running message waiting Table 50 States for a Dual Colored Power LED LED State Description Off Steady Green Power off Running Blinking Green Running message waiting Steady Yellow Sleeping Blinking Yellow Sleeping message waiting lt gt NOTE To use the message waiting function ACPI must be enabled in the operating system and a message capturing application must be invoked 2 8 3 3 5 Power Switch Connector Pins 6 and 8 can be connected to a front panel momentary contact power switch The switch must pull the SW ONS pin to ground for at least 50 ms to signal the power supply to switch on or off The time requirement is due to internal debounce circuitry on the D815EEA board At least two seconds must pass before the power supply will recognize another on off signal 72 Technical Reference 2 9 Jumper Block Jh CAUTION Do not move any jumpers with the power on Always tu
111. rallel port connector Table 22 page 56 1 7 4 Diskette Drive Controller The I O controller supports one diskette drive that is compatible with the 82077 diskette drive controller and supports both PC AT and PS 2 modes For information about Refer to The location of the diskette drive connector Figure 11 page 63 The signal names of the diskette drive connector Table 42 page 67 The supported diskette drive capacities and sizes Table 71 page 109 1 7 5 Keyboard and Mouse Interface PS 2 keyboard and mouse connectors are located on the back panel The 5 V lines to these connectors are protected with a PolySwitcht circuit that like a self healing fuse reestablishes the connection after an overcurrent condition is removed lt gt NOTE The keyboard is supported in the bottom PS 2 connector and the mouse is supported in the top PS 2 connector Power to the computer should be turned off before a keyboard or mouse is connected or disconnected The keyboard controller contains the AMI keyboard and mouse controller code provides the keyboard and mouse control functions and supports password protection for power on reset A power on reset password can be specified in the BIOS Setup program The keyboard controller also supports the hot key sequence lt Ctrl gt lt Alt gt lt Del gt for a software reset operating system dependent This key sequence resets the computer s software by jumping to the beginning of the BIOS code
112. rial port A connector Figure 9 page 54 The signal names of the Serial port A connector Table 23 page 56 The location of the Serial port B connector Figure 12 page 69 The signal names of the Serial port B connector Table 45 page 70 1 7 2 Infrared Support 26 The front panel connector includes four pins that support Hewlett Packard HSDL 1000 compatible infrared IR transmitters and receivers In the BIOS Setup program Serial port B can be directed to a connected IR device The IR connection can be used to transfer files to or from portable devices like laptops PDAs and printers The Infrared Data Association IrDA specification supports data transfers of 115 2 kbits sec at a distance of 1 meter Product Description For information about Refer to The location of the front panel connector Figure 12 page 69 The signal names of the front panel connector Table 48 page 71 Configuring serial port B for infrared applications Section 4 4 3 page 104 The IrDA specification Section 1 3 page 16 1 7 3 Parallel Port The connector for the multimode bidirectional parallel port is a 25 pin D Sub connector located on the back panel In the BIOS Setup program the parallel port can be configured for the following e Output only PC ATt compatible mode e Bi directional PS 2 compatible e EPP e ECP For information about Refer to The location of the parallel port connector Figure 9 page 54 The signal names of the pa
113. rive 3 4 System Management BIOS SMBIOS SMBIOS is a Desktop Management Interface DMI compliant method for managing computers in a managed network The main component of SMBIOS is the management information format MIF database which contains information about the computing system and its components Using SMBIOS a system administrator can obtain the system types capabilities operational status and installation dates for system components The MIF database defines the data and provides the method for accessing this information The BIOS enables applications such as Intel LANDesk Client Manager to use SMBIOS The BIOS stores and reports the following SMBIOS information e BIOS data such as the BIOS revision level e Fixed system data such as peripherals serial numbers and asset tags e Resource data such as memory size cache size and processor speed e Dynamic data such as event detection and error logging Non Plug and Play operating systems such as Windows NT require an additional interface for obtaining the SMBIOS information The BIOS supports an SMBIOS table interface for such operating systems Using this support an SMBIOS service level application running on a non Plug and Play operating system can obtain the SMBIOS information For information about Refer to The D815EEA board s compliance level with SMBIOS Section 1 3 page 16 89 Intel Desktop Board D815EEA Technical Product Specification 3 5 3 6
114. rn off the power and unplug the power cord from the computer before changing a jumper setting Otherwise the board could be damaged Figure 13 shows the location of the jumper block This 3 pin jumper block determines the BIOS Setup program s mode Table 51 describes the jumper settings for the three modes normal configure and recovery When the jumper is set to configuration mode and the computer is powered up the BIOS compares the CPU version and the microcode version in the BIOS and reports if the two match L OM10047 Figure 13 Location of the Jumper Block 73 Intel Desktop Board D815EEA Technical Product Specification 74 Table 51 BIOS Setup Configuration Jumper Settings J7B1 Configure 3 2 H 1 Recovery e None x Function Mode Jumper Setting Normal zF 3 O For information about How to access the BIOS Setup program BIOS recovery 1 2 P Configuration The BIOS uses current configuration information and passwords for booting After the POST runs Setup runs automatically
115. roduct and available manufacturing options Intended Audience The TPS is intended to provide detailed technical information about the D815EEA board and its components to the vendors system integrators and other engineers and technicians who need this level of information It is specifically not intended for general audiences What This Document Contains Chapter Description A description of the hardware used on the D815EEA board A map of the resources of the board The features supported by the BIOS Setup program The contents of the BIOS Setup program s menus and submenus nan BW N A A description of the BIOS error messages beep codes POST codes and diagnostic LEDs Typographical Conventions This section contains information about the conventions used in this specification Not all of these symbols and abbreviations appear in all specifications of this type Notes Cautions and Warnings lt gt NOTE Notes call attention to important information A CAUTION Cautions are included to help you avoid damaging hardware or losing data A WARNING Warnings indicate conditions which if not observed can cause personal injury Intel Desktop Board D815EEA Technical Product Specification Other Common Notation Used after a signal name to identify an active low signal such as USBPO NxnX When used in the description of a component N indicates component type xn are the relative coordinates of its loc
116. rom a diskette Notes 1 2 This feature appears only if a user password has been set This feature appears only if both a user password and a supervisor password have been set BIOS Setup Program 4 6 Power Menu To access this menu select Power from the menu bar at the top of the screen Maintenance Main Advanced Security Power Boot E l The menu represented in Table 75 is for setting the power management features Table 75 Power Menu Feature Options Description Power Management e Disabled Enables or disables the BIOS power management Enabled default feature Inactivity Timer Off Specifies the amount of time before the computer e 1 Minute enters standby mode e 5 Minutes e 10 Minutes 20 Minutes default e 30 Minutes e 60 Minutes e 120 Minutes Hard Drive e Disabled Enables power management for hard disks during Enabled default standby modes ACPI Suspend State S1 State default Specifies the ACPI suspend state e S3 State Video Repost e Disabled default Allows the video BIOS to be initialized coming out of e Enabled the S3 state Some video controllers require this option to be enabled This feature is present only if the ACPI suspend state is set to S3 113 Intel Desktop Board D815EEA Technical Product Specification 4 7 Boot Menu To access this menu select Boot from the menu bar at the top of the screen 114 Maintenance Main Advanced Security
117. ry note the following Non SPD DIMMs will always revert to a 100 MHz with 3 3 3 timing SDRAM bus Mixing Non SPD DIMMs with SPD DIMMs will always revert to a 100 MHz with 3 3 3 timing SDRAM bus The BIOS will not initialize installed memory above 512 MB At boot the BIOS displays a message indicating that any installed memory above 512 MB has not been initialized Mixed memory speed configurations 133 and 100 MHz will default to 100 MHz 133 MHz SDRAM operation requires a 133 MHz system bus frequency processor The board should be populated with no more than four rows of 133 MHz SDRAM two double sided or one double sided plus two single sided DIMMs 100 MHz SDRAM may be populated with six rows of SDRAM three double sided DIMMs NOTE If more than four rows of 133 MHz SDRAM are populated the BIOS will initialize installed memory up to 512 MB at 100 MHz Product Description Table 5 Supported Memory Configurations DIMM Number of SDRAM SDRAM Organization Number of Capacity Sides Density Front side Back side SDRAM devices 32 MB DS 16 Mbit 2MX8 2MX8 16 Note 1 32 MB SS 64 Mbit 4 M X 16 empty 4 48 MB DS 64 16 Mbit 4MX16 2MX8 12 Notes 1 and 2 64 MB DS 64 Mbit 4MX16 4MX16 8 64 MB SS 64 Mbit 8 M X 8 empty 8 64 MB SS 128 Mbit 8 M X 16 empty 4 96 MB DS 64 Mbit 8MX8 4Mx16 12 Notes 1 and 2 96 MB DS 128 64 Mbit 8MX16 4Mx16 8 Notes 1 and 2 128 MB DS 64 Mbit 8MX8 8MX8 16 Note 1 128 MB DS 128 Mbit 8MX16 8MX 16 8
118. s 2 2 2 6 contain several standalone tables Table 12 describes the system memory map Table 13 shows the I O map Table 14 lists the DMA channels Table 15 defines the PCI configuration space map and Table 16 describes the interrupts The remaining sections in this chapter are introduced by text found with their respective section headings 2 2 Memory Map Table 12 System Memory Map Address Range decimal Address Range hex Size Description 1024 K 524288 K 100000 1FFFFFFF 511 MB Extended memory 960 K 1024 K F0000 FFFFF 64 KB Runtime BIOS 896 K 960 K E0000 EFFFF 64 KB Reserved 800 K 896 K C8000 DFFFF 96 KB Available high DOS memory open to the PCI bus 640 K 800 K A0000 C7FFF 160 KB Video memory and BIOS 639 K 640 K 9FCOO 9FFFF 1 KB Extended BIOS data movable by memory manager software 512 K 639 K 80000 9FBFF 127 KB Extended conventional memory 0 K 512 K 00000 7FFFF 512K Conventional memory 47 Intel Desktop Board D815EEA Technical Product Specification 2 3 I O Map Table 13 I O Map Address hex Size Description 16 bytes DMA controller 0000 OOOF 0020 0021 2 bytes Programmable Interrupt Control PIC 0040 0043 4 bytes System timer 0060 1 byte Keyboard controller byte reset IRQ 0061 1 byte System speaker 0064 E byte Keyboard controller CMD STAT byte 0070 0071 2 bytes Sys
119. s the boot order for the other drives to change automatically to accommodate your selection Table 77 IDE Drive Configuration Submenu Feature Options Description Primary Master IDE 1 IDE default Allows you to select the order in which the Primary 1 through 4 Master IDE drive boots Primary Slave IDE 2 IDE default Allows you to select the order in which the Primary 1 through 4 Slave IDE drive boots Secondary Master IDE 3 IDE default Allows you to select the order in which the 1 through 4 Secondary Master IDE drive boots Secondary Slave IDE 4 IDE default Allows you to select the order in which the 1 through 4 Secondary Slave IDE drive boots 115 Intel Desktop Board D815EEA Technical Product Specification 4 8 Exit Menu To access this menu select Exit from the menu bar at the top of the screen Maintenance Main Advanced Security Power Boot Exit The menu represented in Table 78 is for exiting the BIOS Setup program saving changes and loading and saving defaults Table 78 Exit Menu Feature Description Exit Saving Changes Exits and saves the changes in CMOS SRAM Exit Discarding Changes Exits without saving any changes made in the BIOS Setup program Load Setup Defaults Loads the factory default values for all the Setup options Load Custom Defaults Loads the custom defaults for Setup options Save Custom Defaults Saves the current values as custom defaults Normally the BI
120. solution Color Palette Frequencies Hz Notes 1152 x 864 256 colors 60 70 72 75 KDO 256 colors 85 KD 64 K colors 60 70 KD30 64 K colors 72 75 85 KD3 16 M colors 60 KDO 16 M colors 75 85 KD 1280 x 768 256 colors 60 reduced blanking KDOF 64 K colors 60 reduced blanking KD3F 16 M colors 60 reduced blanking KDF 1280x1024 256 colors 60 KDO 256 colors 70 72 75 85 KD 64 K colors 60 70 72 75 85 KD3 16 M colors 60 70 75 85 KD 1600x1200 256 colors 60 70 72 75 KD Notes K Desktop D DirectDraw 3 Direct3D and OpenGL O Overlay F Digital Display Device only A mode will be supported on both analog CRTs and digital display devices the KD30 flags above apply to both types of displays unless indicated otherwise For information about Refer to Obtaining graphics software and utilities Section 1 2 page 16 1 8 2 Digital Video Output DVO Connector The board routes the Intel 82815E GMCH DVO port to an onboard 40 pin DVO connector The DVO connector can be cabled to a DVI or TV out card to enable digital displays or TV out functionality The Digital Visual Interface DVI specification provides a high speed digital connection for visual data types when using the integrated graphics controller This interface is active only when the integrated graphics controller is enabled The DVI interface allows interfacing with a discrete Transmission Minimized Differential Signal
121. ssors listed in Table 4 Table 4 Supported Processors Type Designation System Bus Frequency L2 Cache Size Pentium III processor in 533EB 600EB 667 733 133 MHz 256 KB an FC PGA package 800EB 866 and 933 500E 550E 600E 650 700 100 MHz 256 KB 750 800 and 850 Celeron processor in an 533A 566 and 600 66 MHz 128 KB FC PGA package Celeron processor in a 500 and 533 66 MHz 128 KB PPGA package All supported onboard memory can be cached up to the cachability limit of the processor See the processor s data sheet for cachability limits For information about Refer to Processor support Section 1 2 page 16 Processor data sheets Section 1 2 page 16 Intel Desktop Board D815EEA Technical Product Specification 1 5 System Memory 20 The D815EEA board has three DIMM sockets and supports the following memory features 3 3 V only 168 pin SDRAM DIMMs with gold plated contacts Unbuffered single or double sided DIMMs Maximum system memory 512 MB minimum system memory 32 MB 133 MHz SDRAM or 100 MHz SDRAM Serial Presence Detect SPD and non SPD memory Non ECC and ECC DIMMs ECC DIMMs will operate in non ECC mode only Suspend to RAM Table 5 lists the supported DIMM configurations In the second column of Table 5 DS refers to double sided memory modules containing two rows of SDRAM SS refers to single sided memory modules containing one row of SDRAM When installing memo
122. t If no memory was removed then memory may be bad Memory size has increased since the last boot If no memory was added there may be a problem with the system Memory Size Changed No Boot Device Available Off Board Parity Error Memory size has changed since the last boot If no memory was added or removed then memory may be bad System did not find a device to boot A parity error occurred on an off board card This error is followed by an address On Board Parity Error Parity Error A parity error occurred in onboard memory This error is followed by an address A parity error occurred in onboard memory at an unknown address NVRAM CMOS PASSWORD cleared by Jumper lt CTRL_N gt Pressed NVRAM CMOS and passwords have been cleared The system should be powered down and the jumper removed CMOS is ignored and NVRAM is cleared User must enter Setup Error Messages and Beep Codes 5 2 Port 80h POST Codes During the POST the BIOS generates diagnostic progress codes POST codes to I O port 80h If the POST fails execution stops and the last POST code generated is left at port 80h This code is useful for determining the point where an error occurred Displaying the POST codes requires an add in card often called a POST card PCI not ISA The POST card can decode the port and display the contents on a medium such as a seven segment display The tables below offer descriptions of
123. t API Sound Blaster Prot Roland MPU 401 MIDI and joystick compatible Ensoniq 3D positional audio and Microsoft DirectSoundt 3D support 33 Intel Desktop Board D815EEA Technical Product Specification e Crystal Semiconductor CS4297 A Stereo Audio Codec 20 bit stereo digital to analog and 18 bit stereo analog to digital converters High performance 18 bit stereo full duplex audio codec with up to 48 kHz sampling rate Connects to the ES1373 digital controller using a five wire digital interface For information about Refer to Obtaining audio software and utilities Section 1 2 page 16 1 9 3 Audio Connectors The audio connectors include the following e CD ROM legacy style 2 mm connector e ATAPI style connectors CD ROM Telephony Auxiliary line in e Back panel audio connectors MIDI Game Port Line out Linein Micin For information about Refer to The back panel audio connectors Section 2 8 1 page 54 A CAUTION The pins on both the legacy style 2 mm and the ATAPI CD ROM connectors are wired to the same inputs on the audio mixer Do not attach CD ROM drives to both connectors Otherwise the board could be damaged 1 9 3 1 CD ROM Legacy style 2 mm Audio Connector A 1 x 4 pin legacy style 2 mm connector connects an internal CD ROM drive to the audio mixer For information about Refer to The location of the legacy style 2 mm connector Figure 10 page 59 The signal na
124. t Auto in the BIOS Setup program the BIOS automatically sets up the two PCI IDE connectors with independent I O channel support The IDE interface supports hard drives up to Ultra ATA 66 100 and recognizes any ATAPI devices including CD ROM drives tape drives and Ultra DMA drives see Section 1 3 for the supported version of ATAPI The BIOS determines the capabilities of each drive and configures them to optimize capacity and performance To take advantage of the high capacities typically available today hard drives are automatically configured for Logical Block Addressing LBA and to PIO Mode 3 or 4 depending on the capability of the drive You can override the auto configuration options by specifying manual configuration in the BIOS Setup program To use Ultra ATA 66 100 features the following items are required e An Ultra ATA 66 100 peripheral device e An Ultra ATA 66 100 compatible cable e Ultra ATA 66 100 operating system device drivers NOTE Ultra ATA 66 100 compatible cables are backward compatible with drives using slower IDE transfer protocols If an Ultra ATA 66 100 disk drive and a disk drive using any other IDE transfer protocol are attached to the same cable the maximum transfer rate between the drives is 33 MB sec Overview of BIOS Features lt gt NOTE Do not connect an ATA device as a slave on the same IDE cable as an ATAPI master device For example do not connect an ATA hard drive as a slave to an ATAPI CD ROM d
125. t Specification 2 15 Regulatory Compliance This section describes the D815EEA board s compliance with safety and EMC regulations 2 15 1 Safety Regulations Table 57 lists the safety regulations the D815EEA board complies with when it is correctly installed in a compatible host system Table 57 Safety Regulations Regulation Title UL 1950 CSA950 3 edition Bi National Standard for Safety of Information Technology Equipment Dated 07 28 95 including Electrical Business Equipment USA and Canada EN 60950 2 Edition 1992 with The Standard for Safety of Information Technology Equipment including Amendments 1 2 3 and 4 Electrical Business Equipment European Community IEC 950 2 edition 1991 with The Standard for Safety of Information Technology Equipment including Amendments 1 2 3 and 4 Electrical Business Equipment International EMKO TSE 74 SEC 207 94 Summary of Nordic deviations to EN 60950 Norway Sweden Denmark and Finland 2 15 2 EMC Regulations 84 Table 58 lists the EMC regulations with which the D815EEA board complies when it is correctly installed in a compatible host system Table 58 EMC Regulations Regulation Title FCC Class B Title 47 of the Code of Federal Regulations Parts 2 and 15 Subpart B pertaining to unintentional radiators USA CISPR 22 2 Edition 1993 Limits and methods of measurement of Radio Interference Class B Characterist
126. t contains the D815EEA board and the following 667 MHz Intel Pentium lll processor with a 512 KB cache e 128 MB SDRAM e 3 5 inch diskette drive e 1 6 GB ATA 33 IDE hard disk drive e 24X IDE CD ROM drive This information is provided only as a guide for calculating approximate power usage with additional resources added Values for the Windows 98 desktop mode are measured at 640 x 480 x 256 colors and 60 Hz refresh rate AC watts are measured with the computer is connected to a typical 200 W power supply at nominal input voltage and frequency with a true RMS wattmeter at the line input gt NOTE Actual system power consumption depends upon system configuration The power supply should comply with the recommendations found in the ATX Form Factor Specification document see Table 3 on page 16 for specification information Table 52 lists the power usage for a D815EEA board with the configuration listed above and including the basic audio subsystem and the onboard LAN subsystem Table 52 Mode Windows 98 APM full on Windows 98 APM Suspend Windows 98 ACPI SO Windows 98 ACPI S1 Windows 98 ACPI S3 Windows 98 ACPI Off AC Power Sw 35 W 29W 24W 1W 0 W Power Usage For Board with Basic Audio and Onboard LAN DC Current at 3 3 V 196A 492A n 1477A 0 0A 0 0A 5 V 230A 0 58 A 0 59 A 0 59 A 0 0A 0 0A 12 V 040A ona O11A om 0 0A 0 0A BE 0 00 A
127. tem CMOS Real Time Clock 0072 0073 2 bytes System CMOS 0080 008F 16 bytes DMA controller 0092 E byte Fast A20 and PIC OOAO 00A1 2 bytes PIC 00B2 00B3 2 bytes APM control 00CO OODF 32 bytes DMA OOFO 1 byte Numeric data processor 0170 0177 8 bytes Secondary IDE channel _01FO 01F7 D bytes Primary IDE channel One of these ranges Can vary from 1 byte Audio game port 0200 0207 to 8 bytes 0208 020F 0210 0217 0218 021F One of these ranges Audio Sound Blaster Pro compatible 0220 022F 16 bytes 0240 024F 16 bytes 0228 022F 8 bytes LPT3 0278 027F 8 bytes LPT2 02E8 02EF D bytes COM4 video 8514A 02F8 02FF 8 bytes COM2 One of these ranges D bytes MPU 401 MIDI 0320 0327 0330 0337 0340 0347 0350 0357 0376 1 byte Secondary IDE channel command port 0377 bits 6 0 7 bits Secondary IDE channel status port 0378 037F 8 bytes LPT1 0388 038B 6 bytes AdLibt FM synthesizer 03B0 03BB 12 bytes Intel 82815E GMCH 03C0 03DF 32 bytes Intel 82815E GMCH 03E8 O3EF 8 bytes COM3 48 continued Technical Reference Table 13 UO Map continued Address hex Size Description 03F0 03F5 6 bytes Diskette channel 1 03F6 1 byte Primary IDE channel command port _03F8 03FF 8 bytes COM1 04D0 04D1 2 bytes Edge level triggered PIC One of these ranges 8 bytes Windows Sound System 0530 0537 OE80 0E87 OF40 OF 47 LPTn 400 8 bytes
128. the POST codes generated by the BIOS Table 80 defines the Uncompressed INIT Code Checkpoints Table 81 describes the Boot Block Recovery Code Checkpoints and Table 82 lists the Runtime Code Uncompressed in FO00 Shadow RAM Some codes are repeated in the tables because that code applies to more than one operation Table 80 Uncompressed INIT Code Checkpoints Code Description of POST Operation DO NMI is Disabled Onboard KBC RTC enabled if present Init code Checksum verification starting D1 Keyboard controller BAT test CPU ID saved and going to 4 GB flat mode D3 Do necessary chipset initialization start memory refresh and do memory sizing D4 Verify base memory D5 Init code to be copied to segment 0 and control to be transferred to segment 0 D6 Control is in segment 0 To check recovery mode and verify main BIOS checksum If either it is recovery mode or main BIOS checksum is bad go to check point EO for recovery else go to check point D7 for giving control to main BIOS D7 Find Main BIOS module in ROM image D8 Uncompress the main BIOS module D9 Copy main BIOS image to F000 shadow RAM and give control to main BIOS in F000 shadow RAM Table 81 Boot Block Recovery Code Checkpoints Code Description of POST Operation E0 Onboard Floppy Controller if any is initialized Compressed recovery code is uncompressed in FO00 0000 in Shadow RAM and give control to recovery code in F0
129. tion mode See Section 2 9 on page 73 for configuration mode setting information Table 62 Maintenance Menu Feature Options Description Clear All Passwords No options Clears the user and administrative passwords Clear BIS Credentials No options Clears the Wired for Management Boot Integrity Service BIS credentials Extended e Default default Invokes the Extended Configuration submenu Configuration e User Defined CPU Information No options Displays CPU Information CPU Microcode No options Displays CPU s Microcode Update Revision Update Revision CPU Stepping No options Displays CPU s Stepping Signature Signature 98 BIOS Setup Program 4 2 1 Extended Configuration Submenu To access this submenu select Maintenance on the menu bar then Extended Configuration Maintenance Main Advanced Security Power Boot Exit Extended Configuration The submenu represented by Table 63 is for setting video memory cache mode This submenu becomes available when User Defined is selected under Extended Configuration Table 63 Extended Configuration Submenu Feature Options Description Extended Configuration e Default User Defined allows setting memory control and video default memory cache mode If selected here will also display in e User Defined the Advanced Menu as Extended Menu Used Video Memory Cache Mode e USWC Selects Uncacheable Speculative Write Combining US
130. to enumerate and configure D815EEA board devices that do not have other hardware standards for enumeration and configuration PCI devices on the D815EEA board for example are not enumerated by ACPI 1 13 2 Hardware Support A CAUTION If the Wake on LAN and Instantly Available technology features are used ensure that the power supply provides adequate 5 V standby current Failure to do so can damage the power supply The total amount of standby current required depends on the wake devices supported and manufacturing options Refer to Section 2 11 3 on page 78 for additional information The board provides several hardware features that support power management including e Power connector e Fan connectors e Wake on LAN technology e Instantly Available technology e Resume on Ring e Wake from USB e Wake from PS 2 keyboard e PME wakeup support 42 Product Description Wake on LAN technology and Instantly Available technology require power from the 5 V standby line The sections discussing these features describe the incremental standby power requirements for each Resume on Ring enables telephony devices to access the computer when it is in a power managed state The method used depends on the type of telephony device external or internal and the power management mode being used APM or ACPI lt gt NOTE The use of Resume on Ring and Wake from USB technologies from an ACPI state requires an operating system that pr
131. ug and Play including bus and device enumeration and APM support normally contained in the BIOS e Power management control of individual devices add in boards some add in boards may require an ACPI aware driver video displays and hard disk drives e Methods for achieving less than 30 watt system operation in the power on standby sleeping state e A Soft off feature that enables the operating system to power off the computer e Support for multiple wake up events see Table 10 on page 42 e Support for a front panel power and sleep mode switch Table 8 lists the system states based on how long the power switch is pressed depending on how ACPI is configured with an ACPI aware operating system Table 8 Effects of Pressing the Power Switch and the power switch is If the system is in this state pressed for the system enters this state Off ACPI G2 G5 Soft off Less than four seconds Power on ee ACPI GO working state On ACPI GO working state Less than four seconds Soft off Standby Kees ACPI G1 sleeping state On ACPI GO working state More than four seconds Fail safe power off Sleep ACPI G1 sleeping Less than four seconds Wake up state Tv NA ACPI GO working state Sleep ACPI G1 sleeping More than four seconds Power off state e TA ACPI G2 G5 Soft off For information about Refer to The D815EEA board s compliance level with ACPI Section 1 3 page 16 1 13 1 2 1 System States an
132. ugh the onboard LAN subsystem when enabled in Setup ACPI only The Wake on LAN technology connector can be used with PCI bus network adapters that have a remote wake up connector as shown in Figure 7 Network adapters that are PCI 2 2 compliant assert the wakeup signal through the PCI bus signal PME pin A19 on the PCI bus connectors Network Interface Remote Card Wake up connector technology PCI Slot connector Desktop Board OM09129 Figure 7 Using the Wake on LAN Technology Connector For information about Refer to The location of the Wake on LAN technology connector Figure 10 page 59 The signal names of the Wake on LAN technology connector Table 36 page 62 Product Description 1 13 2 4 Instantly Available Technology A CAUTION For Instantly Available technology the 5 V standby line for the power supply must be capable of providing adequate 5 V standby current Failure to provide adequate standby current when implementing Instantly Available technology can damage the power supply Refer to Section 2 11 3 on page 78 for additional information Instantly Available technology enables the D815EEA board to enter the ACPI S3 Suspend to RAM sleep state While in the S3 sleep state the computer will appear to be off the power supply is off the fans are off and the front panel LED is amber if dual color or off if single color When signaled by a wake up device or event the system quickly retur
133. uire two or more interrupts is classified as INTB This is not an absolute requirement e INTC and INTD Generally a third interrupt on add in cards is classified as INTC and a fourth interrupt is classified as INTD 51 Intel Desktop Board D815EEA Technical Product Specification The ICH2 has eight programmable interrupt request PIRQ input signals All PCI interrupt sources either onboard or from a PCI add in card connect to one of these PIRQ signals Some PCI interrupt sources are electrically tied together on the D815EEA board and therefore share the same interrupt Table 17 shows an example of how the PIRQ signals are routed on the D815EEA board For example using Table 17 as a reference assume an add in card using INTA is plugged into PCI bus connector 4 In PCI bus connector 4 INTA is connected to PIRQB which is already connected to the SMBus The add in card in PCI bus connector 4 now shares interrupts with these onboard interrupt sources Table 17 PCI Interrupt Routing Map ICH PIRQ Signal Name PCI Interrupt Source PIROF PIRQG PIRQH PIRQB_ Other GMCH I KIpRNIITINIB ONTA TO PIRQA ICH2USBcontroler TINTD to PIRQD SMBus controller INTB ICH2 USB controller INTC to PIRQC ICH2Audio Modem TEW NIR CHSLAN U INTA to PIRQE Creative Labs ES1373 digital controller INTA PCI BusConnector1 J4E1 INTA INTB J INTC Wm PCI Bus Connector 2 J4D1 Wm INTA INB NC PCI Bus Connector 3
134. w the system responds to a Power On PCI power management event On ACPI S5 Stay Off default IN ACPI mode only determines the action of the system when Power On a LAN wake up event occurs 1 Boot Device Floppy Specifies the boot sequence from the available devices To specify boot sequence 1 Select the boot device with lt T gt or lt gt 2 Press lt Enter gt to set the selection as the intended boot device The operating system assigns a drive letter to each boot device in the order listed Changing the order of the devices changes the drive lettering The default settings for the first through fifth boot devices are respectively Floppy e IDE HDD e ATAPI CDROM e Intel UNDI PXE 2 0 e Disabled continued BIOS Setup Program Table 76 Boot Menu continued Feature Options Description IDE Drive Configuration No Options Configures IDE drives When selected displays the IDE Drive Configuration submenu Notes 1 ARMD FDD ATAPI removable device floppy disk drive 2 ARMD HDD ATAPI removable device hard disk drive 3 HDD Hard Disk Drive 4 This boot device is available only when the onboard LAN subsystem is present 4 7 1 IDE Drive Configuration Submenu Maintenance Main Advanced Security Power Boot Exit IDE Drive Configuration The submenu represented in Table 77 is used to set the order in which the IDE drives boot Changing the boot order of a given drive cause
135. warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice The Intel Desktop Board D815EEA may contain design defects or errors known as errata that may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained from Intel Corporation P O Box 5937 Denver CO 80217 9808 or call in North America 1 800 548 4725 Europe 44 0 1793 431 155 France 44 0 1793 421 777 Germany 44 0 1793 421 333 other Countries 708 296 9333 t Third party brands and names are the property of their respective owners Copyright 2000 Intel Corporation All rights reserved Preface This Technical Product Specification TPS specifies the board layout components connectors power and environmental requirements and the BIOS for the Intel Desktop Board D815EEA It describes the standard p

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