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Toshiba TMP92CM22FG Computer Hardware User Manual

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1. Undefined M Function Stores lower 2 bits of AD AD conversion conversion result data storage flag 1 Conversion result stored AD Conversion Result Register 3 High cessum qms ADREGSH ee GENE 12A7H Read Write After reset Undefined Stores upper 8 bits of AD conversion result result ADREGxH ADREGxL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Bits 5 to 1 are always read as 1 is the AD conversion data storage lt ADRxRF gt When the AD conversion result is stored the flag is set to 1 When either of the registers ADREGxH ADREGxL is read the flag is cleared to 0 Figure 3 11 5 Register for AD Converter 92CM22 203 2007 02 16 TOSHIBA TMP92CM22 AD Conversion Result Register 4 Low M Stsmbo aowi Aterreser Undefined _ PP Function Stores lower 2 bits of AD AD conversion conversion result data storage flag 1 Conversion result stored AD Conversion Result Register 4 High pom ees el eom ADREG4H 248 000 S Undefined Stores upper 8 bits of AD conversion result AD Conversion Result Register 5 Low Posee qs
2. anari meres Undefined P 0 Function Stores lower 2 bits of AD AD conversion conversion result data storage flag 1 Conversion result stored AD Conversion Result Register 7 High pr redu em iir eei ADREG7H Undefined Stores upper 8 bits of AD conversion result result ADREGxL 4 3 2 1 Bits 5 to 1 are always read as 1 e BitO is the AD conversion data storage flag lt ADRxRF gt When the AD conversion result is stored the flag is set to 1 When either of the registers ADREGxH ADREGxL is read the flag is cleared to 0 Figure 3 11 7 Register for AD Converter 92CM22 205 2007 02 16 TOSHIBA TMP92CM22 3 11 2 Description of Operation 1 2 Analog reference voltage A high level analog reference voltage is applied to the VREFH pin a low level analog reference voltage 1s applied to the VREFL pin To perform AD conversion the reference voltage the difference between VREFH and VREFL is divided by 1024 using string resistance The result of the division is then compared with the analog input voltage To turn off the switch between VREFH and VREFL program a 0 to ADMOD1 lt VREFON gt in AD mode control register 1 To start AD conversion in the OFF state first write a 1
3. 8 ese ome Ater reset unden Function Stores lower 2 bits of AD AD conversion conversion result data storage flag 1 Conversion result stored AD Conversion Result Register 1 High E deme seq sr e d ADREGIH Undefined Stores upper 8 bits of AD conversion result Channel x ADREGxH ADREGxL 7 6 5 4 3 2 7 6 5 4 3 2 1 O0 e Bits 5to 1 are always read as 1 is the AD conversion data storage lt ADRxRF gt When the AD conversion result is stored the flag is set to 1 When either of the registers ADREGxH ADREGxL is read the flag is cleared to 0 Figure 3 11 4 Register for AD Converter 92CM22 202 2007 02 16 TOSHIBA TMP92CM22 AD Conversion Result Register 2 Low gt x 7 5 2 1 _ EL os Lp a Ater reset unaenea 12 4 Function Stores lower 2 bits of AD AD conversion conversion result data storage flag 1 Conversion result stored AD Conversion Result Register 2 High perspi c pes rmx 502 ADREG2H St ee 12 5 Read Write After reset Undefined Stores upper 8 bits of AD conversion result AD Conversion Result Register 3 Low posee
4. UE ur we mee fel BE NTSBEO c e Always write 0 1 INTSBEO Interrupt request level 92CM22 235 2007 02 16 TOSHIBA TMP92CM22 Interrupt control 2 2 Symbol Addess 7 6 5 4 3 2 1 0 INTPO MESS 9 9 0 write 5 1 INTPO Interrupt request level INTAD INTO INTO amp INTEOAD AD R f ow oR Oow S yS enable ce e m INTTC1 0 INTTCO TTG H RW RN enable INTTC2 amp INTETC23 INTTC3 R R W R R W enable Ore OO 45 5 enable EORR ES P E P d INTTC7 DMA7 INTTC6 DMA6 INTTC6 ITC7C ITC7M2 ITC7M1 ITC7MO ITC6C ITC6M2 ITC6M1 ITC6MO INTETC67 al Wero RW INTTC4 8 RW INTTC7 enable paces cat rwn Tuv ET 3 ee SIO interrupt Prohibit O INTRX1 mode RMW do control 1 INTRX1 1 INTRXO level level mode Interrupt 00 6 P Prohibit S n mode RMW O Rising O Rising O
5. Ld TAO1RUN lt TA1RUN gt Bit7 to 2 Up counter Bit Bito 0 1 2 40 1 2 10 1 2 10 Comparator timing Comparator output Match detect 1 Up counter clear Ww 1 1 1 j l TA1OUT 1 1 1 2 fc 40 MHz lt gt Figure 3 7 10 Square Wave Output Timing Chart 50 duty 92CM22 112 2007 02 16 TOSHIBA TMP92CM22 Making 1 count up on the match signal from the TMRAO comparator Select 8 bit timer mode and set the comparator output from TMRAO to be the input clock to TMRA1 Comparator o Match output forTMRAO TMRAO t 4 when TA1REG 2 Match output for TMRA1 Figure 3 7 11 TMRA1 Count up on Signal from TMRAO 2 16 bit timer mode 16 bit interval timer is configured by pairing the two 8 bit timers TMRAO and 1 To make 16 bit interval timer in which TMRAO and 1 are cascaded together set lt 01 1 0 gt to 01 In 16 bit timer mode the overflow output from TMRAO is used as the input clock for TMRAI regardless of the value set in TAOIMOD lt TAO1CLK1 0 gt Table 3 7 3 shows the relationship between the timer Interrupt cycle and the input clock selection set the timer interrupt interval set the lower eight bits in timer register TAOREG and the upper eight bits in 1 Be sure to set TAOREG
6. Write waits Read waits 001 0 waits 001 0 waits 101 2 waits 101 2 waits 111 4 waits 111 4 waits Others Reserved Others Reserved BEXOM BEXOMO BEXBUS BEXBUSO pel 07 o 00 ROM SRAM 01 Reserved 10 Reserved 11 Reserved 010 1 wait 110 3 waits 011 WAIT pin 010 1 wait 110 3 waits 011 WAIT pin 0 1 Data bus width 00 8 bits 01 16 bits 10 Reserved 11 Reserved PGE OPWR OPWRO PR PRO 212 _____ 0 1 Wait number on page 00 1 state n 1 1 1 mode 01 2 states n 2 2 2 mode 10 3 states n 3 3 3 mode 11 Reserved uci cocci 0 Compare enable 1 Compare disable GE zum Set start address A23 to A16 R W 0 Compare enable 1 Compare disable Set start address A23 to A16 SS 0 Compare enable 1 Compare disable Eu Set start address A23 to A16 Preces EIE ee 0 Compare enable 1 Compare disable po sec Set start address A23 to A16 Byte number in a page 00 64 bytes 01 32 bytes 10 16 bytes 11 8 bytes page access ne 92CM22 239 2007 02 16 TOSHIBA TMP92CM22 b Clock gear System SY
7. o ee ped wa Write waits Read waits 001 0 waits 001 0 waits 101 2 waits 101 2 waits 111 4 waits 111 4 waits Others Reserved Others Reserved B3E B3REC B30M1 B30M0 838051 B3BUSO 507 119 o te Oe Oe CS select 0 No insert 00 ROM SRAM Data bus width 0 Disable write 0 dummy 101 Reserved 00 8 bits 1 Enable cycle 10 Reserved 01 16 bits Default 11 Reserved 10 Reserved 1 Insert 11 Reserved dummy cycle CS select 0 Disable write 0 1 Enable 010 1 wait 110 3 waits 011 WAIT pin 010 1 wait 110 3 waits 011 WAIT pin 010 1 wait 110 3 waits 011 WAIT pin 010 1 wait 110 3 waits 011 WAIT pin 92CM22 238 2007 02 16 TOSHIBA TMP92CM22 Memory controller 2 2 Sms Adress 7 6 T2 T Block EX MEMC control register low PMEMCR Block EX MEMC control register high Page ROM control register Memory mask register 0 Memory start address register 0 Memory mask register 1 Memory start address register 1 Memory mask register 2 Memory start address register 2 Memory mask register 3 Memory start address register 3 0158H Prohibit RMW 0159H Prohibit RMW BEXWWI BEXWWO BEXWR2 BEXWRT BEXWRO Sa ee el psu c
8. DMAG start vector DMA7 DMA7V start 107H vector C ovans owarva pes DMAT start vector 92CM22 46 2007 02 16 TOSHIBA TMP92CM22 6 Specification of a micro DMA burst Specifying the micro DMA burst function causes micro DMA transfer once started to continue until the value in the transfer counter register reaches 0 Setting any of the bits in the register DMAB which correspond to a micro DMA channel as shown below to 1 specifies that any micro DMA transfer on that channel will be a burst transfer Ares 7 9 5 1 DMA request on burst mode DMAB DMA burst 108H t 92CM22 47 2007 02 16 TOSHIBA TMP92CM22 7 Notes The instruction execution unit and the bus interface unit in this CPU operate independently Therefore if immediately before an interrupt is generated the CPU fetches an instruction which clears the corresponding interrupt request flag Note the CPU may execute this instruction in between accepting the interrupt and reading the interrupt vector In this case the CPU will read the default vector 0004H and jump to interrupt vector address FFFF04H avoid this an instruction which clears an interrupt request flag should always be placed after a DI instruction And in the case of setting an interrupt enable again by EI in
9. wueruo seconv DAVE 028 mal o Function Always Select WUP time for Select HALT mode lt DRVE gt 1 Pin write 0 oscillator 00 Reserved Select state 00 Reserved 01 STOP mode using control 01 2 Input frequency 10 IDLE1 mode mode 10 2 Input frequency 11 IDLE2 mode IDLE1 216 1 IDLE1 11 2 frequency mode Note The unassigned register SYSCRO bit6 3 SYSCRO lt bit1 0 gt SYSCR1 lt bit7 4 gt and SYSCR2 lt bit6 gt are RD as undefined value Figure 3 3 3 SFR for System Clock 92CM22 14 2007 02 16 TOSHIBA TMP92CM22 poe sor PLLCR Bitsymbo PLLON FCSEL_ ee _ Note Logic of PLLCR lt LWUPFGs is different DFM of 900 L1 Figure 3 3 4 SFR for PLL EI After reset ES E D Function Protect fc oscillator 0 OFF external driver ability 1 ON 1 Normal 0 Weak 1 Bit symbol 10E4H Read Write After reset Switching the protect ON OFF by write to following 1st KEY 2nd KEY Function 1st KEY EMCCR1 EMCCR2
10. 9 ss INTRX1 WADE f Nm aw rR DR RN Oe ao ET NI ERR ER TI INT5 4 INT4 amp d wn INTTB11 1 INTTB10 1 INTTB10 amp enable pT BON _____ meor Ey XU enable n 4 595 ese dd INTSBEO _ LISBEOC 5 0 2 ISBEOM 5 mec VAR DAP nd enable P peg alee INTPO pr a S O po f Poc move Pom 2 IE A Note Always write 0 92CM22 40 2007 02 16 TOSHIBA TMP92CM22 Sys me Wes 7 1 9 1 5 3 INTAD INTO pi INTEOAD INTETCO1 INTETC23 45 67 INTWDT enable INTTCO amp INTTC1 enable R R R W R W Ze a _ INTTC2 amp enable R jue qure INTTC4 amp NTTCS e INTTC6 amp ius enable ES REESE ECRIRE x NER S INTWD mdr OW ees oz co c enable 2 Interrupt request flag Disables interrupt request Sets interrupt
11. n Undefined P EE nr BU reed eee Iumemap se ERE Undefined ADRTO Undefined 92CM22 249 2007 02 16 TOSHIBA TMP92CM22 11 Watchdog timer Name assess 7 e 5 L5 wore wore lt lt R W een WDT mode 1300H WDT Select detecting time Always 1 Internally Always control 00 2 540 write 0 15 write 0 out 1 Enable 01 2 to the 10 2 fjo reset pin 11 22 register WDT 1301H control Prohibit register RMW WwW WDT disable code 4E WDT clear code 92CM22 250 2007 02 16 TOSHIBA TMP92CM22 6 Port Section Equivalent Circuit Diagram m Reading the circuit diagram Basically the gate symbols written are the same as those used for the standard CMOS logic IC 74H CXX series The dedicated signal is described below STOP This signal becomes active 1 when the halt mode setting register 1s set to the STOP mode and the CPU executes the HALT instruction When the drive enable bit lt DRVE gt is set to 1 however STOP remains at 0 The input protection resistance ranges from several tens of ohms to several hundreds of ohms m Data bus DO t
12. P5CR control Prohibit register HM 0 1 0 Input 1 Output P5FC function Prohibit register RMW 9 MES a e P6CR control Prohibit leder RM e So EHE P6FC function Prohibit register RMW Pot LIUM register RMW M Input 1 Output eme ene eme eme enr EET P7FC Port 7 function Prohibit register Port 2 4 2 2 4 E Port Port 1 WAIT 1 R W 1 CLKOUT 1 Don t set 1 WRLU 1 1 RD Peir Paor Pons P8FC control Prohibit register RMW 92CM22 233 2007 02 16 TOSHIBA port 3 3 Name ees 7 fie S LT scel E control Prohibit register RMW Port 9 0027H P9FC function Prohibit register RMW Port 9 0025H ODE Prohibit register RMW poo 0 Port SI 1 SCL output Note Parone e ete drain drain BEL em LT 1 0 Input 0 Input ___ PC F EAE ce 0 Port 0 Port 0 Port 0 Port E Port 1 INT3 1 INT2 1 INTO 1 INT1 1 TAOIN TBOOUTO TA1OUT
13. Refer to port 1 function setting Port 1 Function Register scu Weer dr ied uestem D osi dE ge Bitsymbel eee ree con Bead We T reel er ose After reset M c 7 o nass Function Refer to port 1 function setting Port 1 Function setting Note 1 Read modify write instruction is prohibited for registers Note 2 P1XC shows X bit of P1CR register Note 3 It is set to Port or Data bus by AM pin setting oa 015 to 08 Figure 3 5 2 Register for Port 1 92CM22 53 2007 02 16 TOSHIBA 3 5 2 TMP92CM22 Port 4 P40 to P47 Port 4 is an 8 bit general purpose I O port Bits can be individually set as either inputs or outputs by control register and function register PAFC In addition to functioning as a general purpose I O port port 4 can also function as a address bus to After released reset device set Port 4 to pins of follow function by combination of AM1 and AMO pins Function Setting after Reset Domtwethsseting Address bus A0 to A7 Address bus 0 to A7 Don t use this setting Reset Direction control on bit basis Internal address bu 0 to A7 5 Selector gt A Output buffer P4CR write Function control on bit basis Output latch lt q lt
14. terese 1T 3 T 1 141 M1V lt 21 8 gt Enables or masks comparison of the addresses M1V21 to M1V8 are corresponding to addresses A21 to A8 The bits of M1V15 to M1V9 are corresponding to address A15 to A9 by 1 bit If 0 is set the comparison between the value of the address bus and the start address is enabled If 1 is set the comparison is masked MAMRn 210 2 FE i E o e qois dado sek a lt 22 15 gt Enables or masks comparison of the addresses MnV22 to MnV15 are corresponding to addresses A22 to A15 If 0 is set the comparison between the value of the address bus and the start address is enabled If 1 is set the comparison is masked After a reset MASRO to MASR3 and MAMRO to are set to BOCSH lt BOE gt B1CSH B1E and lt gt are reset to 0 This disables the CSO CS1 and CS3 areas However 2 lt 2 gt is reset to 0 2 5 lt 2 gt to 1 and CS2 is enabled 000000H to FFFFFFH Also the bus width and the number of waits specified in BEXCSH L are used for accessing address except the specified CSO to CS3 area 92CM22 94 2007 02 16 TOSHIBA TMP92CM22 2 Page ROM control register PMEMCR The page ROM control register sets page ROM accessing ROM page accessing is executed only in block address area 2 PMEMCR A ee PRO
15. Output Write Strobe signal for writing data to pins DO to D7 Output Port 72 Output port WRLU Output Write Strobe signal for writing data to pins D8 to D15 e Output Port 74 Output Port 75 Output port Sara Read write This port is 1 when read and dummy cycle This port is 0 when write cycle Ee een WAIT Input Wait Pin used to request bus wait to CPU cso Output Chip select 0 Outputs 0 when address is within specified address area csi Output Chip select 1 Outputs 0 when address is within specified address area 682 Output Chip select 2 Outputs 0 when address is within specified address area CS3 Output Chip select 3 Outputs 0 when address is within specified address area SCK Serial bus interface clock I O data at SIO mode P91 Port 91 port 50 1 Output Serial bus interface send data at SIO mode SDA Serial bus interface send receive data at mode Open drain output mode by programmable Port 92 port Serial bus interface receive data SIO mode Serial bus interface clock I O data at mode Open drain output mode by programmable Port to A2 7 Input port with pull up resistor 92CM22 5 2007 02 16 TOSHIBA TMP92CM22 Table 2 2 2 Pin Names and Functions 2 2 Pin Names Functions Port I O port Timer input 8 bit timer AO input PC1 Port C1 I O port INT1
16. Read modify Function Software timing Up counter TMRBO source clock write ite 0 ite 0 capture 00 Disable control 00 Reserved instruction is control 01 Reserved 0 Clear 01 T1 prohibited 0 Software 10 Reserved disable 10 4 11 TA10UTJ 1 Clear 11 1 1 Undefined d PA enable Clear BEES counter 0 UCO Enable clearing on match with TBORG1H L Capture interrupt timing Capture control 01 11 B UE to at rising edge of TA1OUT Capture to TBOCP1H L at falling edge of TATOUT Software capture Capture value of up counter to TBOCPOH L Undefined Figure 3 8 4 Register for TMRB 92CM22 128 2007 02 16 TOSHIBA TMP92CM22 TMRB1 Mode Register gt x 7 6 5 4 2 TBIMOD 1192H EXE NINE NEN Read modity Function TB1FF1 Inversion trigger Software Capture timing Up counter TMRB1 source clock write 0 Trigger disable capture 00 Disable control 00 TB1INO pin input instruction is 1 Trigger enable INT4 is rising edge 0 Clear 01 T1 prohibited invert when 01 TB1NO f TB1IN1 7 disable 10 4 UCi2is UC12 CPR INT4 is falling edge t Clear loaded into matches 1 Undefined 1 TB1INO enable TB1CP1H L with INT4 is falling edge TB1RG1H L TAITRGT TA1TRG INT4 is rising edge 11 716
17. and VREFL VREFON String resistance VREFL AMOand AMI Input data Input m NMI NMI Input Schmitt 92CM22 254 2007 02 16 TOSHIBA TMP92CM22 7 Points to Note and Restrictions 1 Notation 1 The notation for built in I O registers is as follows register symbol Bit symbol Example TAO1RUN TAORUN denotes bit TAORUN of register TA01RUN 2 Read modify write instructions RMW An instruction in that the CPU reads data from memory and writes the data to the same memory location by using one instruction Example 1 SET 3 TAO1RUN Set bit3 of TAO1TRUN Example 2 INC 1 100H Increment the data at 100H e Examples of read modify write instructions on the TLCS 900 Exchange instruction EX mem R Arithmetic operations ADD mem R ADC mem R SUB mem R SBC mem R INC 3 mem DEC 3 mem Logic operations AND mem R OR mem R XOR mem R Bit manipulation operations STCF 3 A mem RES 3 mem SET 3 mem CHG 3 mem TSET 3 mem Rotate and shift operations RLC mem RRC mem RL mem RR mem SLA mem SRA mem SLL mem SRL mem RLD mem RRD mem 3 fOSCH fc fFPH fSys and one state The clock frequency that is inputted from X1 and X2 is called The clock that is selected by PLLCR lt FCSEL gt register is called fc The clock that selected by SYSCR1 lt SYSCK gt is called f
18. ze eee rsmbo c Ater resot Undefined So Function Stores lower 2 bits of AD AD conversion conversion result data storage flag 1 Conversion result stored AD Conversion Result Register 5 High cur use cu ie rs ADREGSH PASE gt gt ee Undefined Stores upper 8 bits of AD conversion result result ADREGxH ADREGxL 7 6 5 4 3 2 7 6 5 4 3 2 1 0 0 Bits 5 to 1 are always read as 1 e BitO is the AD conversion data storage flag lt ADRxRF gt When the AD conversion result is stored the flag is set to 1 When either of the registers ADREGxH ADREGxL is read the flag is cleared to 0 Figure 3 11 6 Register for AD Converter 92CM22 204 2007 02 16 TOSHIBA TMP92CM22 AD Conversion Result Register 6 Low __ 4 2 1 0 teachi R _ a Function Stores lower 2 bits of AD AD conversion conversion result data storage flag 1 Conversion result stored AD Conversion Result Register 6 High gt x 7 6 15 4 J 2 1 0 C2ADH ReadWrte Undefined Stores upper 8 bits of AD conversion result AD Conversion Result Register 7 Low
19. Pez Pre Pro Pra Pr Pro ReadWrite O After reset Data from external port Output latch register is set to 1 Port F Control PFCR 00 rue e pare eem Merrest o o o o 0 Input 1 Output Port F Function a ee ee RedWrte d W con Function 0 Port i 0 Port 1 SCLK1 1 SCLKO output output PFFC 003FH Port function setting Fs Imputpot Output port 1 TXD1 TXD1 Open drain En EE Inputpor Ouputpor 1 TXDO TXDO Open drain Note 1 Read modify write instruction is prohibited for the registers PFCR and PFFC Note 2 PF1 RXDO and PF4 RXD1 pins do not have a register changing PORT FUNCTION For example when it is used as an input port the input signal is inputted to SIO as the serial receive data Note 3 and PF3 pins not have a register PFODE for open drain setting Please conduct the open drain Setting according to above setting Figure 3 5 29 Register for Port F 92CM22 76 2007 02 16 TOSHIBA TMP92CM22 3 5 12 Port G PGO to PG7 Port is 8 bit input port and can also be used as the analog input pins for the internal AD converter PG3 can also be used as ADTRG pin for the AD converter Port G PGO to PG7 ANO to AN7 Convertion resu
20. in succession write EMCCR Bit symbol 2nd KEY 1 2 in succession write 10 5 Read Write After reset Function Note In case restarting the oscillator in the stop oscillation state e g Restart the oscillator in STOP mode set EMCCRO DRVOSCH DRVOSOL 1 Figure 3 3 5 SFR for Noise 92CM22 15 2007 02 16 TOSHIBA 3 3 3 TMP92CM22 System Clock Controller The system clock controller generates the system clock signal 55 for the CPU core and internal I O It is used as input that fc outputted from high frequency oscillation circuit and PLL Clock doubler SYSCR1 lt GEAR2 0 gt SYSCR1 lt GEAR2 0 gt sets the high frequency clock gear to either 1 2 4 8 or 16 fc fc 2 4 fc 8 or fc 16 These functions can reduce the power consumption of the equipment in which the device is installed Single clock mode is set by resetting initialized to lt GEAR2 0 gt 100 This setting will cause the system clock to be set to fc 32 fc 16x1 2 For example fsys is set to 1 25 MHz when 40MHz oscillator is connected to the X1 and X2 pins 1 Clock gear controller fFPH is set according to the contents of the clock gear select register SYSCR1 lt GEAR2 0 gt to either fc fc 2 fc 4 fc 8 or fc 16 Using the clock gear to select lower value of fFPH reduces power consumption Example Changing to a high frequency gear SYSCR1 EQU 10E1H
21. Port 4 P40 to P47 to A7 Internal data bus When these ports are used as general purpose port each bit can be set individually for input or output However each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port All of general purpose ports except for port that used as address bus are operated as output port Please be careful when using this setting Figure 3 5 3 Port 4 92CM22 54 2007 02 16 TOSHIBA TMP92CM22 Port 4 Register Es ER pas Port 4 Control Register 0012H Read Write p 19 qo p 9 oe 9 0 Input 1 Output Note2 Port 4 Function Register pec gos Dg T Tops PAFC E ae ee a ipo oup odes pop iin 0 Port 1 Address bus to A7 Note1 Read modify write instruction is prohibited for registers PACR and P4FC Note2 When these ports are used as general purpose port each bit can be set individually for input or output However each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port All of general purpose I O ports except for port that used as address bus are operated as output port Please be
22. Selector A Figure 3 5 25 Port F PFO and 92CM22 73 2007 02 16 TOSHIBA TMP92CM22 2 Ports PF1 and 4 RXDO and XD1 In addition to function as I O port port PF1 and PF4 can also function as RXD input pin of serial channel Direction control on bit basis S Output latch S EC E Selector PF1 RXDO 4 RXD1 Internal data bus PF read A RXDO RXD1 Figure 3 5 26 Port F PF and PF4 92CM22 74 2007 02 16 TOSHIBA TMP92CM22 3 Port 50 SCLKO and port CTS1 SCLK1 In addition to function as I O port port PF2 and PF5 can also function as CTS input pin of serial channel or SCLK I O pin Reset Direction control on bit basis Function control on bit basis S Output latch SCLKO SCLK1 PF write output Internal data bus 5 SCLKO CTSO PF5 SCLK1 CTS1 Selector B S Selector A Figure 3 5 27 Port F PF2 and PF5 PF read CTSO CTS1 SCLKO SCLK1 input 4 Port PF6 and port PF7 These ports are general purpose I O port Reset R Direction control on bit basis S Output latch PF read Internal data bus PF6 to S B Selector A Figure 3 5 28 Port F PF6 and PF7 92CM22 75 2007 02 16 TOSHIBA TMP92CM22 Port F Register e xq ipe
23. Internal data bus Port 7 P70 Output buffer P71 WRLL P72 WRLU P73 P74 CLKOUT P75 R W Selector RD CLKOUT Note P73 is fixed to Figure 3 5 9 Port 7 P70 to P75 92CM22 60 2007 02 16 TOSHIBA TMP92CM22 Reset Direction control on bit basis Internal data bus Port P7 P76 WAIT Output buffer Figure 3 5 10 Port 7 P76 Port 7 Register Read Write P76 P75 P74 P73 P72 P71 P70 After reset Data from 1 1 1 1 1 1 external port Note Note Output latch register is cleared to 0 Port 7 Control Register xe Jor iru pron sere en e ce n Function O7 Input 1 Output Port 7 Function PFG Bit symbol 76 P75F P74F P73F P72F P71F P70F 001FH After reset 3 9 Ir cer Function 0 Port Port SEE Port gt Port Port mm Port 1 WAIT 1 1 CLKOUT 1 Don tset 1 WRLU 1 WRLL 1 RD Note Read modify write instruction is prohibited for registers P7CR and P7FC Figure 3 5 11 Register for Port 7 92CM22 61 2007 02 16 TOSHIBA TMP92CM22 3 5 6 Port 8 P80 to P83 Port 8 is 4 bit output port Resetting sets output latch of P82 to 0 and set output latches of P80 P81 and P83 to 1 In addition to functioning as a output port port 8 can also function as a output chip se
24. SCLKO output lt SCLKS gt 0 rising mode ed Internal clock SCLKO output iS timinig lt SCLKS gt 1 falling mode 1 1 1 1 1 X XC ITXOC INTTXO interrupt 2 request Figure 3 9 19 Transmission Operation in Interface Mode SCLKO output mode In SCLK input mode 8 bit data is output from the TXDO pin when the SCLKO input becomes active after the data has been written to the transmission buffer by the CPU When all data is outputted INTESO lt ITXOC gt will be set to generate INTTXO interrupt SCLKO input lt SCLKS gt 0 f rising mode SCLKO input JE P SCLKS 1 falling mode TXDO X su X BU 1 1 1 1 1 1 deus MEM INTTXO interrupt request 7 Figure 3 9 20 Transmission Operation in I O Interface Mode SCLKO input mode 92CM22 162 2007 02 16 TOSHIBA TMP92CM22 2 Receiving In SCLK output mode the synchronous clock is outputted from SCLKO pin and the data is shifted to receiving buffer 1 This starts when the receive interrupt flag INTESO IRXOC is cleared by reading the received data When 8 bit data are received the data will be transferred to receiving buffer 2 SCOBUF according to the timing shown below and INTESO IRXOC will be set to generate INTRXO interrupt
25. The baud rate generator can be to 1 in UART mode only when 16 16 division function is not used Do not use in I O interface mode Note2 Set BR1CR BR1ADDE to 1 after setting 1 to 15 to BR1ADD lt BR1K3 0 gt when 16 K 16 division function is used Writes to unused bits in the BR1ADD register do not affect operation and undefined data is read from these unused bits Figure 3 9 12 Baud Rate Generater Control for SIO1 BR1CR and BR1ADD 92CM22 159 2007 02 16 TOSHIBA TMP92CM22 7 6 5 4 3 2 1 0 SCOBUF 1200H 7 6 5 4 3 2 1 0 Note Prohibit read modify write for SCOBUF Figure 3 9 13 Serial Transmission Receiving Buffer Register for SIOO and SCOBUF peer e arces 1250 02058 Reaawete mw eee Function IDLE2 Duplex 0 Stop 0 Half 1 Run 1 Full Figure 3 9 14 Serial Mode Control Regsiter for SIO and SCOMOD1 7 6 5 4 3 2 1 0 SC1BUF 1208H 7 6 5 4 3 2 1 0 Note Prohibit read modify write for SC1BUF Figure 3 9 15 Serial Transmission Receiving Buffer Register for SIO1 and SC1BUF posee cur qase JL we 9 _ Es eal Function IDLE2 Duplex 0 Stop 0 Half 1 Run 1 Full Figure 3 9 16 Serial M
26. 5 a 2 5 KSA E o o o o a 8 a 5 lt a 2007 02 16 92CM22 86 TMP92CM22 External read write bus cycle 0 waits at WAIT pin input mode TOSHIBA External read write bus cycle n waits WAIT pin input mode TW i T2 i i 1 1 X 1 1 1 1 i i Output ac we oce eI qa T 4 4 4O f lt 2 etes ES us s aut EW n 9 gt oc gt EW 9 oc 8 8 A 3 A A oz 5 o IE 5 9 2 a AN 2 a 2007 02 16 Sampling 92CM22 87 Sampling TMP92CM22 TOSHIBA 5 waits Example of WAIT input cycle WAIT CLKOUT 20 MHz 2007 02 16 92CM22 88 TOSHIBA TMP92CM22 6 Connecting external memory Figure 3 6 1 shows an example of how to connect external memory to the 92 22 This example connects ROM and SRAM in 16 bit width TMP92CM22 16 bit SRAM Figure 3 6 1 Example of External Memory By resetting TMP92CM22 function as output port Output latch of P82 CS2 is cleared to 0 and output L Output latch of P80 CS0 P81 CS1 and P83 CS3 are set to 1 and output When set port 8 from
27. gt to 0 92CM22 209 2007 02 16 TOSHIBA Example TMP92CM22 1 Convert the analog input voltage on pin and write the result to memory address 0800H using the AD interrupt INTAD processing routine Setting of main routine 7 6 INTEOAD lt X 1 ADMOD1 lt 1 1 ADMODO lt X X O0 EN E Interrupt routine processing example WA ADREG3 WA 226 0800H lt WA Enable INTAD and set it to interrupt level 4 Set pin to the analog input channel Start conversion in channel fixed single conversion mode Read value of ADREG3L ADREG3H to general purpose register WA 16 bits Shift contents read into WA six times to right and zero fill upper bits Write contents of WA to memory address 0800H 2 Converts repeatedly the analog input voltages on the three pins ANO 1 and AN2 using channel scan repeat conversion mode INTEOAD lt X ADMOD1 lt 1 10 ADMODO lt X X 0 ooo X Don t No change 92CM22 210 Disable INTAD Set pins ANO to to be the analog input channels Start conversion in channel scan repeat conversion mode 2007 02 16 TOSHIBA TMP92CM22 3 12 Watchdog Timer Runaway detection timer The TMP92CM22 contains a watchdog timer of runaway detecting The watchdog timer WDT is used to return the CPU to the normal state when it detects that the CPU has started to malfunction Runaway due to causes
28. start cec vector Po MAS startvector 0000 O FES R W 0106H DMA6 start vector eee o o0 o o0 o o o DMA7VS 7 4 7 2 DMA7V1 7 Hl RW s E ae PMA startvector O OSS O R W 0108H burst start vector 1 DMA request on burst mode DIBSH DREQ7 DREQ6 DREQ5 DREQ4 DREQ3 DREQ2 DREQ1 DREQO DMA R W Prohibit dcdit a J 1 request software 92CM22 237 2007 02 16 TOSHIBA TMP92CM22 4 Memory controller 1 2 Name 7 1 Block 0 MEMC control register low Block 0 MEMCT control register high Block 1 MEMC control register low Block 1 MEMC control register high Block 2 MEMC control register low Block 2 MEMC control register high Block 3 MEMC control register low Block 3 MEMC control register high 0140H Prohibit RMW 0141H Prohibit RMW 0144H Prohibit RMW 0145H Prohibit RMW 0148H Prohibit RMW 0149H Prohibit RMW 014CH Prohibit RMW 014DH Prohibit RMW Boww2 Bowwo BowWR2 1 BOWRO 0 1 0 gt N 0 1i 0 Write waits Read waits 001 0 waits 001 0 waits 101 2 waits 101 2 waits 111 4 waits 111 4 waits Others R
29. 001 and read the data The TMP92CM22 generates a clock pulse for 1 bit data transfer Since the master device is a receiver the SDA line on the bus remains high The transmitter receives the high signal as an ACK signal The receiver indicates to the transmitter that the data transfer 18 completed After the one data bit has been received and an interrupt request has been generated the TMP92CM22 generates a stop condition See section 3 10 6 4 and terminates data transfer 9 1 2 3 4 5 6 7 8 1 After clear lt gt to 0 reading receiving data After set 001 to lt BC2 0 gt reading receiving data Output of master Output of slave Figure 3 10 16 Termination of Data Transfer Master receiver mode 92 22 186 2007 02 16 TOSHIBA TMP92CM22 2 If MST 0 Slave mode In the slave mode the 92 22 operates either in normal slave mode or in slave mode after losing arbitration In the slave mode an INTSBEO interrupt request generate when the TMP92CM22 receives a slave address or a GENERAL CALL from the master device or when a GENERAL CALL is received and data transfer is completed or after matching received address In the master mode the TMP92CM22 operates in a slave mode if it losing arbitration INTSBEO interrupt request is generated when a word data transfer terminates after losing arbitration When an INTSBEO interrupt request is generated the PIN is cleared to 0 an
30. 3 10 6 Data Transfer in Bus Mode 1 Device initialization In first set the SBIOBR1 lt P4EN gt SBIOCR1 lt ACK SCK2 0 gt Set SBIOBR1 lt P4EN gt to 1 and clear bits 7 to 5 and in the SBIOCR1 to 0 Next set a slave address lt SA6 0 gt and the ALS lt ALS gt 0 when an addressing format to the I2COAR And write 000 to SBIOCR2 lt MST BB 1 to PIN 10 to lt SBIM1 0 gt and 00 to lt SWRST1 0 gt Set initialization status to slave receiver mode by this setting 2 Start condition and slave address generation 1 Master mode In the master mode the start condition and the slave address are generated as follows In first check a bus free status when SBIOSR lt BB gt 0 Set the SBIOCR1 lt ACK gt to 1 Acknowledge mode and specify a slave address and a direction bit to be transmitted to the SBIODBR When SBIOSR lt BB gt 0 the start condition are generated by writing 1111 to SBIOCR2 lt MST TRX BB PIN gt Subsequently to the start condition nine clocks are output from the SCL pin While eight clocks are output the slave address and the direction bit which are set to the SBIODBR At the 9th clock the SDA line is released and the acknowledge signal is received from the slave device An INTSBE interrupt request generate at the falling edge of the 9th clock The lt PIN gt is cleared to 0 In the master mode the SCL pin is
31. 5 2 invalid gt DOtoDsihold o o fn 6 RD rising gt o o o AC condition e Output High 0 7 Vcc Low 0 3 Vcc C 50 pF Input High 0 9 Vcc Low 0 1 Vcc 2 Page ROM read cycle 3 2 2 2 mode CLKOUT to A23 52 DO to 031 92CM22 222 2007 02 16 TOSHIBA TMP92CM22 4 3 AD Conversion Characteristics Analog reference voltage v io conver supe gd As Analog input voltage ____________ input voltage IAvN Analog current for analog reference voltage IREF lt VREFON gt 1 Analog current for analog reference voltage 3 9 9 0 02 5 0 UA lt gt 0 Total error T 1 0 4 0 LSB Include quantize error of 0 5 LSB 4 4 Event Counter TAOIN and TB11IN1 5 5 fsys Variable 20 MHz 125 kHz Parameter Symbol fc 40 MHz fc 4 MHz Clock cyce 8895100 1 500 _ jJ 600 Low level clock width 4X 40 240 2 ___ High level oock width __ 1240 32040 Note Symbol x in the above table means the period of clock it s same period of the system clock for CPU core The period of fsys depends on the clock gear setting or changing high speed oscillator low speed oscillator and so on 92CM22 223 2007 02 16 TOSHIBA TMP92CM22 4 5 Serial Ch
32. Input clock 00 TB1INO pin input 16 Clear up counter UC12 Clear disable Clear by matching with TBI RG1H L Capture interrupt timing Capture control INT4 control 00 Capture disable Generate INT4 Capture to TB1CPOH L at rising edge by TB1INO Capture to TB1CP1H L at rising edge of TB1IN1 8119 Capture to TB1CPOH L at rising edge of TB1INO Generate INT4 Capture to TB1CP1H L at falling edge of TB1IN1 by TB1INO __ __ Capture to TB1CPOH L at rising edge of TA1OUT Generate INT4 Capture to TB1CP1H L at falling edge of TA1OUT by TB1INO rising ET Software capture Capture value of up counter to TB1CPOH L Undefined Figure 3 8 5 Register for TMRB 92CM22 129 2007 02 16 TOSHIBA TMP92CM22 TMRBO Flip flop Control Register see yw erso TBOFFCO 1183H eme 3 o Read modify Function Always write 11 TBOFFO inversion trigger control write 0 Trigger disable 00 Invert instruction is 1 Trigger enable 01 Set prohibited Invert when Invert when Invert when Invert when 10 Clear the UC10 the UC10 the UC10 the UC10 11 Don t care value is value is matches match with loaded into loaded into with TBORGOH L TBOCP1H L TBOCPOH L TBORG1H L Always re
33. Set the up counter UC12 in free running mode with the internal input clock input the external trigger pulse from TB1INO pin and load the value of up counter into capture register TBICPOH L at the rise edge of external trigger pulse When the interrupt INT4 is generated at the rise edge of external trigger pulse set the value c plus a delay time d to TBIRGOH L d and set the above set value d plus a one shot width p to TBIRGIH L c d p And set 11 to timer flip flop control register TBIFFCR TBIEITI TB1EOT1 gt Set to trigger enable for be inverted timer flip flop TB1FFO by UC12 matching with TBIRGOH L and with TB1RG1H L When interrupt INTTB11 occurs this inversion will be disabled after one shot pulse is output The c d and p correspond to c d and p in Figure 3 8 12 Set the counter in free running mode Count clock Prescaler output ___ __ ____ 1 pin input External trigger pulse Load into capture register 1 TB1CPOH L and generate INT4 Match with TB1RGOH L Generate INTTB11 Inversion i enable Set it to disables that i Inversion inversion caused enable ading into Match with TB1RG1H L Timer ouput pin TB1OUTO 1 1 1 i Delay time Pulse width d Figure 3 8 12 One shot Pulse Output with delay 92CM22 136 2007 02 16 TOS
34. to SBIOCR2 lt SWRST1 0 gt reset signal is inputted to serial bus interface circuit and circuit is initialized All command registers except SBIOCR2 lt SBIM1 0 gt and status flag except SBIOCR2 lt SBIM1 0 gt are initialized to value of just after reset SBIOCRI lt SWRMON gt is set to 1 automatically when completed initialization of serial bus interface 15 Serial bus interface data buffer register SBIODBR The received data can be read and transmission data can be written by reading or writing SBIODBR In the master mode after the slave address and the direction bit are set in this register the start condition is generated 16 PC bus address register I2COAR I2COAR lt SA6 0 gt is used to set the slave address when the TMP92CM22 functions as a slave device The slave address outputted from the master device is recognized by setting the I2COAR lt ALS gt to 0 And the data format becomes the addressing format When set ALS to 1 the slave address is not recognized the data format becomes the free data format 17 Baud rate register SBIOBR1 Write 1 to baud rate circuit control register SBIOBR1 lt P4EN gt before using I C bus 18 Setting register for IDLE2 mode operation SBIOBRO SBIOBRO lt I2SBIO gt is the register setting operation stop during IDLE2 mode Therefore setting lt 125 10 gt is necessary before the HALT instruction is executed 92CM22 183 2007 02 16 TOSHIBA TMP92CM22
35. 00 Invert 01 Set TASFF control for inversion 10 Clear inversion 11 Don t care 0 Disable 0 TMRA2 1 Enable Operation mode 00 8 bit timer mode 01 16 bit timer mode 10 8 bit PPG mode 11 8 bit PWM mode PWM cycle 00 Reserved 01 29 10 27 11 28 110DH Prohibit RMW 92CM22 241 2007 02 16 TOSHIBA 7 16 bit timer 1 2 Sms 7 6 5 _ T2 Timer BO RUN register TBORUN Timer BO mode register TBOMOD Timer BO flip flop control register TBOFFCR 16 bit timer register 0 low TBORGOL 16 bit timer register 0 high TBORGOH 16 bit timer register 1 low TBORG1L 16 bit timer register 1 high TBORG1H Capture register 0 low TBOCPOL Capture register 0 high Capture register 1 low TBOCPOH TBOCP1L Capture register 1 high TBOCP1H 1182H Prohibit RMW 1183H Prohibit RMW 1188H Prohibit RMW 1189H Prohibit RMW 118AH Prohibit RMW 118BH Prohibit RMW TMP92CM22 5 TEORDE CERT EET TBOPRUN RW F w TE TN GRE Rc IN NT EE ti buffer 0 Stop prescaler UC10 1 Run Count up 0 Disable 1 Operate __ TBOCLE TBOCLKI 1 Enable R W Capture timing 00 Disable 01 Reserved 10 Reserved 11 TATOUT f TA1OUT Timer BO source clock 00 Reserved 01 671 10 4 11
36. Bit symbol Read Write After reset OPGE Enable bit 0 No ROM page mode accessing Default 1 ROM page mode accessing OPWR 1 0 Specifies the number of waits 00 1 state n 1 1 1 mode n gt 2 Default 01 2 states n 2 2 2 mode n gt 3 10 3 states n 3 3 3 mode n gt 4 11 Reserved Note the number of waits to the control register BnCSL in each block address area PR 1 0 ROM page size 00 64 bytes 01 32 bytes 10 16 bytes Default 11 8 bytes 92CM22 95 2007 02 16 TOSHIBA TMP92CM22 Table 3 6 1 BOCSL AO 0140H N WT o 0 1 o0 1 J 0 BOCSH Bitsymbol BE BoREC 0 1 BOBUSO 0 o Noe o Nt o o J 0 MAMRO Qu adde Bl are MSARO 0143H t BICSL B1ww2 B1WWO BIWR2 BIWRi BIWRO 0144H ReadWrite WT Aterrset OT o o j BICSH Bitsymbol BfREC Biomi B1OMO BiBUSi BIBUSO 0145H Readwrte ERES ECT NIST TONNES TN DERE ERN 1 0146H R W MSAR1 0147H Read Write R W Atterreset ai A i B2CSL _
37. Port F5 I O port it Serial 1 clock I O CTS1 Serial data send enable 1 Clear to send PF toPF7 2 10 JjJPotF toFzVOpot o O PGO to PG7 Port GO to G7 idit port ANO to AN7 Analog input 0 to 7 Pin used to input to AD converter AD trigger Pin used to request AD converter start Share with PG3 Eur ESTHER Non Maskable interrupt request pin Operation mode AMO 1 2 Input Fixed to AM1 0 AMO 1 External 16 bit bus start 8 16 bit dynamic sizing Fixed to AM1 1 AMO 0 External 8 bit bus start 8 16 bit dynamic sizing Dans VO Hewfewenyosbtoremedenpn ResET 1 Input Reset Initialize TMP92CM22 Schmitt input with pull up resistor VREFH 1 Pin for reference voltage input to AD converter H S VREFL 1 for reference voltage input to AD converter 9 ie a ass 3 _______3 ________ Power supply pin Al Vee pins shoud be connected wih he power _______ DVSS 4 GND pins 0 V 5 DVSS pins should be connected with GND 0 V _ 92CM22 6 2007 02 16 TOSHIBA 3 Operation TMP92CM22 This section describes the basic components functions and operation of the TMP92CM22 3 1 CPU The 92 22 incorporates a high performance 32 bit CPU The TLCS 900 H1 CPU For a description of this CPU s operation please refer to the section of this data
38. Setting of the divide value 000 5 001 6 010 7 011 8 100 9 101 10 110 11 111 Reserved sios SIOM SCK2 SCK SCKO revo qp sn moe repe Prohibit RMW SIO mode Transfer Transfer 0 Stop 1 Start 1 Abort Transfer mode 0 Continue 00 8 bit transmit 10 8 bit transmit receive 11 8 bit receive SBIO buffer register SBIODBR Prohibit RMW buso address register 2 Prohibit RMW Setting slave address Serial bus interface status register SBIOSR when read mode Prohibit RMW Start stop condition request monitor 0 Request 1 Cancel Setting of the divide value 000 4 001 5 010 6 011 7 100 8 101 9 110 10 111 External clock SCKO R Receiving W Transmission Undefined Address recognition 0 Enable 1 Disable GENERAL CALL detection monitor 0 Undetect 1 Detect received bit monitor 0 0 1 1 detection monitor 0 1 Detect detection monitor 0 Undetect 1 Detect Serial bus interface Software reset Serial bus interface control SBIOCR2 operating mode selection 00 Port mode generation generate write 10 and 01 then an internal reset signal is when write register2 Serial bus interface status register SBIOSR when read SIO mode Prohibit Serial bus interface contro
39. TB1INO INT5 PD1 m PGO 2 pe ON The buffer is always turned A current flows 1 Port having a pull up pull down resistor the input buffer if the input pin is not driven 2 AIN input does not cause a current to flow through the OFF The buffer is always turned off No applicable Note Condition A B are as follows SYSCR2 register setting HALT mode lt DRVE gt lt SELDRV gt IDLE1 STOP Co RR 1 oT Condition B Condition B 92CM22 27 2007 02 16 TOSHIBA TMP92CM22 Table 3 3 6 Output Buffer State Table Output Buffer State When the CPU is In HALT In HALT mode IDLE1 STOP Operating mode IDLE2 Condition A Note Condition B Note During Reset Used as Used as Used as Used as Function Function Function Function Output Function Name When When When When Pin external read P60 P67 A16 A23 OFF eed puce OFF ea el p 5 E eae En ON OFF ON S OFF 70 wr ON The buffer is always turned When the bus is released however output buffers for some pins are turned off OFF The buffer is always turned off No applicable Note Condition A B are as follows SYSCR2
40. 0 Watchdog timer Port 6 8 bit timer Timer A1 8 bit timer Timer A2 8 bit timer Timer 32 Kbyte RAM 16 bit timer Timer BO 16 bit timer Timer B1 Figure 1 1 TMP92CM22 Block Diagram 92CM22 3 TMP92CM22 DVCC 3 DVSS 4 X1 X2 RESET AMO AM1 NMI PC3 INTO DO to D7 P10 to P17 D8 to 015 P40 to P47 to A7 P50 to P57 A8 to A15 P60 to P67 A16 to A23 to PA2 PA7 2007 02 16 TOSHIBA TMP92CM22 2 Assignment and Functions The assignment of input output pins for the TMP92CM22FG their names and functions are as follows 2 1 Pin Assignment Figure 2 1 1 shows the pin assignment of the TMP92CM22FG P75 R W L LL P71 WRLL P76 WAIT P83 CS3 P82 CS2 P81 C81 85 10 Dvss4 80 50 AVSS IrI PA1 PD2 TB10UTO PD1 TB11N1 INT5 PDO TB1INO INT4 IIl P92 SI SCL 90 P91 SO SDA 95 PD3 TB10UT1 P90 SCK P74 CLKOUT 100 80 P73 P72 WRLU P70 RD P67 A23 VREFL OU VREFH PGO ANO PG1 AN1 OC PG2 AN2 PG3 AN3 ADTRG O PG4 AN4 015 PG5 AN5 PG6 AN6 CO PG7 AN7 LLL PCO TAOIN PC1 TA1OUT INT1 PC5 TA3OUT INT2 OC PC6 TBOOUTO INT3 OL PFO TXDO PF1 RXDO PF2 SCLKO CTso OC PF3 TXD1 OO PF4 RXD1 PF5 SCLK1 CTS1
41. 9T16 Software capture control 0 Software capture 1 Undefined Up counter control 0 Clear disable 1 Clear enable __ TBOCIT TBOCOT TB0E1T1 TBOEOT TBOFFC TBOFFCO W R W write 0 Control 00 Invert 01 Set 10 Clear 11 Don t care Always read as 11 Always write 11 TBOFFO inversion trigger 0 Trigger disable 1 Trigger enable Invert when Invert when Invert when the UC10 matches with matches with TBORG1H L TBORGOH L Invert when the UC10 value is loaded in to TBOCPOH L Undefined Undefined Undefined Undefined Undefined Undefined Undefined E ee Undefined 92CM22 242 2007 02 16 TOSHIBA TMP92CM22 16 bit timer 2 2 Name 7 6 5 T5 _ RE w 1 o o0 0 Mn k Double IDLE2 Timer B1 TB1RUN RUN 1190H register Timer B1 mode register TB1MOD Timer B1 flip flop control register TB1FFCR 16 bit timer register 0 low TB1RGOL 16 bit timer register 0 high TB1RGOH 16 bit timer register 1 low TB1RG4L 16 bit timer register 1 high TB1RG1H Capture register 0 low T
42. By resetting these port pins become general purpose input port None I O pin is reset to input pin When use built in function process all function by software 92CM22 51 2007 02 16 TOSHIBA 3 5 1 TMP92CM22 Port 1 P10 to P17 1 is an 8 bit general purpose I O port Bits can be individually set as either inputs or outputs by control register P1CR and function register P1FC In addition to functioning as a general purpose I O port port1 can also function as data bus 08 to D15 After released reset device set port1 to pins of follow function by combination of 1 and AMO pins Function Setting after Reset o o Dontusthisseting 1 Detbus DBtoDi5 mupot PlOtoPiZ 1 jJ Don tuse this setting Reset Direction control on bit basis Function control on byte batch External access Data write D8 to D15 Output buffer 2 gt a T S Output latch Port 1 Selector gt P10 to P17 P1 write D8 to D15 te P1 Read access Data read Figure 3 5 1 Port 1 92CM22 52 2007 02 16 TOSHIBA TMP92CM22 Port 1 Register pp wie Tm After reset Data from external port Output latch register is clear to O Port 1 Control Register B qp usi 0006H o
43. H83 Hv3 49151 Bumes uelis YING eDe wouxoe peel 1dnueju peal 4 4 1 1 jdnuejul peal 10199 1 ZOLLNI 9OLLNI SO LLNI VO LLNI O LLNI COLLNI OOLLNI ELNI OLNI GMLNI 1 0 Jejunoo NIN Figure 3 4 3 Block Diagram of Interrupt Controller 2007 02 16 92CM22 39 TOSHIBA TMP92CM22 1 Interrupt priority setting registers Sms ae 7 6 5 INT2 INT1 a 222 1422 74 UE EEG MEME INT3 po me ivo enable eo 1 2 INTTAO amp enable e enable CAN R INTTBO1 TMRBO INTTBOO TMRBO INTTBOO amp INTTBO1 ITBO1C 01 2 ITBO1M1 ITBO1MO ITBOOC 00 2 00 1 ITBOOMO a INTTBOO RBS INTTBOO pres soon enable EE ERR 1 amp enable DONNER siis velar
44. Load into TB1CP1H L INTTA2 INTTAS Figure 3 8 14 Frequency Measurement For example if the value for the level 1 width of of the 8 bit timer is set to 0 5 s and difference between the values in TB1CPOH L and is 100 the frequency is 100 0 5 s 200 Hz 92CM22 138 2007 02 16 TOSHIBA Count clock TMP92CM22 Pulse width measurement This mode allows measuring the high level width of an external pulse While keeping the 16 bit timer event counter counting Free running with the prescaler output clock input external pulse is input through the TB1INO pin Then the capture function is used to load the UC12 values into and TBICP1H L at the rising edge and falling edge of the external trigger pulse respectively The interrupt INT4 occurs at the falling edge of TB1INO The pulse width is obtained from the difference between the values of TB1CPOH L and TB1CP1H L and the internal clock cycle For example if the prescaler output clock is 0 8 us and the difference between and TB1CP1H L is 100 the pulse width will be 100 x 0 8 80 Additionally the pulse width that is over the UC12 maximum count time specified by the clock source can be measured by changing software Prescaler output clock Lulu 1 pin input External pulse Load into TBOCPOH L Load into TBOCP1H L INT4 Note Figure 3 8 15 Pulse Width Measu
45. Since there is a possibility of abnormal writing reading of the data if two memories with different bus width are put in consecutive addresses do not execute an access to placed on both memories with one command 92CM22 82 2007 02 16 TOSHIBA TMP92CM22 Data Size Start Data Width in CPU CPU Data Bit Address Memory Side Bit Address D i b7 to 60 b7 to bO b15 to b8 b15 to b8 b7 to bO b15 to b8 b23 to b16 b31 to b24 b7 to b0 b23 to b16 b7 to 60 b15 to b8 b23 to b16 b31 to b24 b15 to b8 b31 to b24 b7 to bO B15 to b8 b23 to b16 b31 to b24 b7 to 60 b23 to b16 b7 to bO b15 to b8 b23 to b16 b31 to b24 b15 to 08 b31 to b24 During a read data input to the bus ignored At write the bus is at high impedance and the write strobe signal remains inactive 92CM22 83 2007 02 16 TOSHIBA TMP92CM22 4 Wait control The external bus cycle completes a wait of two states at least 100 ns at fsys 20 MHz Setting the lt BnWW2 0 gt and lt BnWR2 0 gt of BnCSL specifies the number of waits in the read cycle and the write cycle BnWW is set with the same method as BnWR BnWW BnWR Bit BnCSL Register BnWW2 BnWH 1 BnWWO Function BnWW1 BnWRO dm T 2 states 0 waits access fixed mode __ _1 _ 3 states 1 wait access fixed mode Default o _1___ states 2 waits access fixed mode _ 5 states 3 waits access fixe
46. Symb Aes 7 6 1 5 3 1 2 L3 TAOREG Undefined 1 1103H Undefined TA2REG Undefined TASREG Undefined Note Read modify write instruction is prohibited for above registers Figure 3 7 9 Register for TMRA 92CM22 110 2007 02 16 TOSHIBA TMP92CM22 3 7 4 Operation in Each Mode 1 8 bit timer mode Both TMRAO and 1 can be used independently as 8 bit interval timers When set function and count data TMRAO and 1 should be stopped 1 Generating interrupts at a fixed interval using TMRA1 To generate interrupts at constant intervals using TMRA1 INTTA1 first stop 1 then set the operation mode input clock and a cycle to TAO1MOD and TAIREG register respectively Then enable the interrupt INTTA1 and start TMRA1 counting Example To generate an INTTA1 interrupt every 40 us at fc 40 MHz set each register as follows MSB LSB 7 6 5 4 3 2 TAO1RUN XXX 0 Stop 1 and clear it to 0 TAO1MOD 0 0 X X 1 Select 8 bit timer mode and select 1 16 fc s at 40MH2 as the input clock TA1REG 0 11 0010 0 Set 40 us 1 100 64H to TAREG INTETAO1 X 1 0 Enable INTTA1 and set it to Level 5 TAO1RUN X X X 11 Start TMRA1 counting X Don tcare change Select the input clock refers to Table 3 7 3 Table 3 7 3 Selecting Interrupt Interval and the Input Clock Using 8 Bit Timer Input clock In
47. received slave address 1s the same as the value set at the I2COAR or when a GENERAL CALL is received 8 bit data are 0 after a start condition Although SBIOCR2 lt PIN gt can be set to 1 by the program the PIN is not clear it to 0 when it is programmed 0 Serial bus interface operation mode selection SBIOCR2 lt SBIM1 0 gt is used to specify the serial bus interface operation mode Set SBIOCR2 lt SBIM1 0 gt to 10 when the device is to be used in I C bus mode after confirming pin condition of serial bus interface to Switch a mode to port after confirming a bus 1s free 10 Arbitration lost detection monitor Since more than one master device can exist simultaneously on the bus in I C bus mode a bus arbitration procedure has been implemented in order to guarantee the integrity of transferred data Data the SDA line is used for bus arbitration The following shows an example of a bus arbitration procedure when two master devices exist simultaneously on the bus Master A and master B output the same data until point After master A outputs and master the SDA line of the bus is wire AND and the SDA line is pulled down to the low level by master A When the SCL line of the bus is pulled up at point b the slave device reads the data on the SDA line that is data in master data transmitted from master B becomes invalid The state in master is cal
48. up counter the comparator match detect signal goes Active If the value set in the timer register is the signal goes active when the up counter overflows The TAOREG are double buffer structure each of which makes a pair with register buffer The setting of the bit lt gt determines whether TAOREG s double buffer structure is enabled or disabled It is disabled if lt TAORDE gt 0 and enabled if lt TAORDE gt 1 When the double buffer is enabled is transferred from the register buffer to timer register when a 2 overflow occurs in PWM mode or at the start of the PPG cycle in PPG mode Hence the double buffer cannot be used in timer mode A reset initializes lt TAORDE gt to 0 disabling the double buffer To use the double buffer write data to the timer register set gt to 1 and write the following data to the register buffer Figure 3 7 3 show the configuration of TAOREG Timer register TAOREG Shift trigger Register buffer 0 Match detecting PPG cycle PWM 2 overflow Selector TA01RUN lt TAORDE gt Write to TAOREG Internal data bus Figure 3 7 3 Timer Register AO TAOREG Note The same memory address is allocated to the timer register and the register buffer When lt TAORDE gt 0 the same value is written to the register buffer and the timer register when lt TAORDE gt 1 only the register b
49. 02 16 TOSHIBA TMP92CM22 3 10 7 Clocked synchronous 8 bit SIO Mode Control The following registers are used to control and monitor the operation status when the serial bus interface SBI is being operated in clocked synchronous 8 bit SIO mode Serial Bus Interface 0 Control Register 1 Us ee sos some sow som sce sc meaw oo o 9 0 o SBIOCR1 1240H Read Function Transfer Continue Transfer mode select Serial clock selection and reset monitor modity write start abort 00 Transmit mode 0 Stop transfer 01 Reserved 1 Start 0 Continue 10 Transmit receive mode prohibited transfer 11 Receive mode 1 Abort transfer Serial clock selection lt SCK2 0 gt at write 1 25 MHz 625 kHz 313 kHz System clock fsys 156 kHz fsys 20 MHz SCL output to SCK pin 78 1 kHz fscl 1598 uz 39 1 kHz 2 19 5 kHz External clock Indicate transfer start stop so Start Note Set the transfer mode and the serial clock after setting lt SIOS gt to 0 and lt SIOINH gt to 1 Serial Bus Interface 0 Data Buffer Register ees pues qm ab E es SBIODBR Read Write R Receiver W Transfer ead modify write After reset Undefined instruction is prohibited Figure 3 10 20 Register
50. 2915 snq 19 1 319 91 11400 16 91 lt 0 1 gt eujeju lt gt 1915169 01 19 319 91 0140 16 91 yN 0191 Jejunoo 19 91 71 lt 0 LNdO0d1 gt LLO QOWOSL 10 99 9S 319081 QONN0 amp g8 L lt 1 gt 0 02 lt 10 90891 gt 71 0 90 91 0 1945621 9119 71 145 1 lt 0 gt 1 snq euJeju LNOLWL Woy 0 16 Figure 3 8 1 Block Diagram of TMRBO 2007 02 16 92CM22 121 TMP92CM22 TOSHIBA sng jeuelu euJelu 1945162 lt 309191 gt 195109 LaL VHODSY JeisiDeJ 19 91 JeisiDeJ 19 91 2149 LLNOLEL indino dojj ditj LOaLLNI 008 LLNI 0 2 151 jndino 2140 10 91 yN 16 91 lt 0 DX TO LG L gt COWLaL on oy 1eyunoo dn
51. 5 states If DMACn 0 then INTTC 010 zz Source address INC mode DMADn lt DMASn DMACn lt 1 5 states If DMACn 0 then INTTC 011 zz Source address DEC mode DMADn lt DMASn DMACn lt DMAOn 1 5 states If DMACn 0 then INTTC 100 zz Source address INC mode DMADn lt DMASn DMACn lt 1 6 states If DMACn 0 then INTTC 101 zz Source address DEC mode DMADn lt DMASn DMACn lt 1 6 states If DMACn 0 then INTTC 110 77 Destination address fixed mode DMADn DMASn DMACn lt DMACn 1 5 states If DMACn 0 then INTTC 111 00 Counter mode DMASn lt DMASn 1 DMACn lt 1 5 states If DMACn 0 then INTTC 27 00 1 byte transfer 01 2 2 byte transfer 10 4 byte transfer 11 Reserved Note 1 The execution state number shows number of best case 1 state memory access 1 state 50 ns at internal 20 MHz Note 2 n shows micro DMA channel number 0 to 7 92CM22 37 2007 02 16 TOSHIBA 3 4 3 TMP92CM22 Interrupt Controller Operation The block diagram in Figure 3 4 3 shows the interrupt circuits The left hand side of the diagram shows the interrupt controller circuit The right hand side shows the CPU interrupt request signal circuit and the halt release circuit For each of the 33 interrupts channels there is an interrupt request flag Consisting of a flip flop an interrupt priority setting register and a micro DMA sta
52. 6 PF7 OL P66 A22 P65 A21 10 P64 A20 DVCC3 II P63 A19 P62 A18 P61 A17 70 P60 A16 CIL P57 A15 P56 A14 P55 A13 P54 A12 P53 A11 P52 A10 P51 A9 IL P50 A8 P47 A7 P46 A6 P45 A5 44 4 11 P43 A3 P42 A2 P41 A1 P40 A0 92 22 100 NM OL DVCC1 LLL DVSS3 o 10 10 e e iD LI LI L1 LI OU LI LI LI LL LL Li LL LLL LLL KGXSESHEASSSASSRSSSZSELS ZS 052 298 522252252 gt gt gt r ooaoaaaga Figure 2 1 1 Pin Assignment Diagram 100 Pin QFP 92CM22 4 2007 02 16 TOSHIBA TMP92CM22 2 2 Pin Names and Functions The following tables show the names and functions of the input output pins Table 2 2 1 Pin Names and Functions 1 2 of Pins 00007 10 Data Lower Data bus DO to 07 P10 to P17 Port 1 I O port that allows I O to be selected the bit level when used to the external 8 bit bus D8 to D15 Data Data bus 08 to 015 P40 to P47 Port 4 I O port AO to A7 Output Address Address bus 0 to A7 P50 to P57 Port 5 I O port 8 10 15 Address Address bus 8 to A15 P60 to P67 Port 6 I O port A16 to A23 Address Address bus A16 to A23 Output Port 70 Output port Output Read Strobe signal for reading external memory
53. 92CM22 256 2007 02 16 TMP92CM22 TOSHIBA Package Dimensions 8 P LQFP100 144 0 50F Unit mm 0 22 0 05 1604302 2007 02 16 92CM22 257 TOSHIBA TMP92CM22 92CM22 258 2007 02 16
54. Function Setting after Reset Donttuse this setting 1 Address bus A16 to A23 EE EE Address bus A16 to A23 Don t use this setting Reset Direction control i on bit basis Internal address bu A16 to A23 5 Selector gt A Output buffer P6CR write Function control on bit basis Output latch lt a a Port 6 P60 to P67 A16 to A23 Internal data bus When these ports are used as general purpose port each bit can be set individually for input or output However each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port All of general purpose I O ports except for port that used as address bus are operated as output port Please be careful when using this setting Figure 3 5 7 Port 6 92CM22 58 2007 02 16 TOSHIBA TMP92CM22 Port 6 EU 0018H Ef Data from external port Output latch register is cleared to 0 Port 6 Control P6CR orar 0 Input 1 Output 2 Port 6 Function E 0 Port 1 Address bus A16 to A23 Note1 Read modify
55. I O registers and their specifications Table 3 5 1 Port Function U with pull up resistor Port Pis Names Number Direction Direction Pin Names for Built In Names of Pins Setting Unit Function Pi0toPi7 8 o Bt X D8toDi5 Pot4 P40toP47 8 w Pots P50tops 8 v 45 Porte 600 67 8 v Bt 16 3 O Port 7 Pt Pn 1 wre P72 1 _ P74 1 75 121 Oupt Pots 90 050 ___ 1 Pee tt 1 S38 Port 9 EE 0 SPA P92 VO Port A o e ___ 1 meu Up A2 input 1 UU Fxd Pote PCO 1 10 B ST TAIN o JUNTISTATOUT _ ___ vo B 11 10 Bt SINT Pce 1 10 Bt INT3 TBOOUTO PotD PD 1 Bt Pi 1 10 O 1 vwo B _ Po 1 10 psp Oe _______ 5 Pero cap 1 ee B Pa o oo S w 11 10 Bi SCLKO cso O S _____ Pr
56. Input Interrupt request pin 1 Interrupt request pin with programmable level rising edge falling edge TA1OUT Timer output 8 bit timer AO or timer A1 output Port C3 I O port Interrupt request pin 0 Interrupt request with programmable level rising edge falling edge Port C5 I O port INT2 Interrupt request pin 2 Interrupt request pin with programmable level rising edge falling edge TASOUT Timer output 8 bit timer A2 or timer A3 output PC6 Port C6 I O port Interrupt request 3 Interrupt request with programmable level rising edge falling edge TBOOUTO Timer output 16 bit timer BO output PDO Port DO I O port INT4 Interrupt request pin 4 Interrupt request pin with programmable rising edge falling edge TB1INO Timer input 16 bit timer B1 input 0 PD1 Port D1 I O port INT5 Interrupt request pin 5 Interrupt request pin with programmable rising edge falling edge TB1IN1 Timer input 16 bit timer B1 input 1 EL 1 0 0 Output Timer output 16 bit timer B1 output 0 D3 I O port Output Timer output 16 bit timer B1 output 1 ion Output Serial send data 0 Open drain output mode by programmable RXDO Input Serial receive data 0 PF2 yo Port F2 I O port SCLKO d yo Serial 0 clock I O me om Serial data send enable 0 Clear to send Port port EIE NE Serial send data 1 Open drain output mode by programmable Pon F4 VO port __________
57. Note AN7 ANO gt gt AN2 gt AN3 gt gt gt AN6 gt AN7 IDLE2 control Stopped In operation 1 Control of application of reference voltage to AD converter 0 OFF ON Before starting conversion before writing 1 to lt 5 gt set the VREFON bit AD Mode Control Register 2 to 1 qnom pr dere qr omm E mecs Bimbo Sp Pe oaa So After reset e e Function AD conversion trigger start control 0 Disable 1 Enable AD conversion start control by external trigger ADTRG input 0 Dsabed Note As pin AN3 also functions as the ADTRG input pin do not set lt ADCH2 0 gt 011 100 101 110 111 when using ADTRG with lt ADTRGEs gt set to 1 Figure 3 11 3 Register for AD Converter 92CM22 201 2007 02 16 TOSHIBA TMP92CM22 AD Conversion Result Register 0 Low qp oe p rac apmEGoL Stsmbo ADROT RP Aterreser Undefined Function Stores lower 2 bits of AD AD conversion conversion result data storage flag 1 Conversion result stored AD Conversion Result Register 0 High pow ses segs ADREGOH OR S Undefined Stores upper 8 bits AD conversion result AD Conversion Result Register 1 Low own m
58. address and direction bit Acknowledge signal Figure 3 10 9 Generation of Start Condition and Slave Address When programmed 0 to SBIOCR2 lt BB gt and 111 to lt MST PIN in during SBIOSR lt BB gt is 1 start a sequence of stop condition output Do not modify the contents of lt MST BB and PIN until a stop condition is generated on a bus 1 SCL line 5 25 42 SDAline 0 0 ne 1 Stop condition Figure 3 10 10 Generation of Stop Condition The state of the bus can be ascertained by reading the contents of SBIOSR BB SBIOSR lt BB3 gt will be set to 1 Bus busy status if a start condition has been detected on the bus and will be cleared to 0 if a stop condition has been detected Bus free status 92 22 180 2007 02 16 TOSHIBA SCL Line 8 9 TMP92CM22 Interrupt service requests and interrupt cancellation When a serial bus interface interrupt request 0 INTSBEO occurs the SBIOSR2 PIN is cleared to 0 During the time that the SBIOSR2 lt PIN gt is 0 the SCL line is pulled down to the low level The PIN is cleared to 0 when end of transmission or receiving 1 word of data And when writing data to SBIODBR or reading data from SBIODBR PIN is set to The time from PIN being set to 1 until the SCL line is released takes tL OW In the address recognition mode lt ALS gt 0 PIN is cleared to 0 when the
59. and external interrupt pin INTO to INT3 These settings operate by programming 1 to the corresponding bit of PCCR and Resetting resets the PCCR and PCFC to 0 and sets all bits to input port 1 PCO TAOIN In addition to function as I O port port PCO can also function as input pin TAOIN of timer channel 0 Reset i Direction control on bit basis Function control on bit basis S Output latch lt lt Internal data bus 1 PCO TAOIN 5 Selector A TAOIN Note Can not read the output latch data when output mode Figure 3 5 18 Port C PCO 92CM22 66 2007 02 16 TOSHIBA TMP92CM22 2 PC1 INT1 TA10UT PC5 INT2 PC6 TBOOUTO In addition to function as I O port port PC1 PC5 and PC6 can also function as external interrupt input pin INT1 to INT3 and output pin of timer channel TA1OUT and TBOOUTO Reset Direction control on bit basis Function control on bit basis S Output latch PC write TA1OUT TBOOUTO B y S Selector p B W S B Selector A Select rising falling lt I2EDGE IBEDGE gt Note Can not read the output latch data when output mode TATOUT 5 2 PC6 INT3 TBOOUTO Internal data bus PC read A Selector S B IIMC2 H LE I2LE IS
60. book which describes the TLCS 900 H1 CPU The following sub sections describe functions peculiar to the CPU used in TMP92CM22 these functions are not covered in the section devoted to the TLCS 900 H1 CPU 3 1 1 Outline TLCS 900 H1 CPU is high speed and high performance CPU based on TLCS 900 L1 CPU TLCS 900 H1 CPU has expanded 32 bit internal and external data bus to process instructions more quickly Outline of TLCS 900 H1 CPU are as follows Width of CPU address bus Width of CPU data bus Internal operating frequency Minimum bus cycle Function of data bus sizing Internal RAM Internal I O External device Minimum instruction execution cycle Conditional jump Instruction queue buffer Instruction set CPU mode Micro DMA Table 3 1 1 Outline of CPU 24 bits 20 MHz 1 clock access 50 ns at 20 MHz 32 bits 8 bits 2 clock access can insert some waits 1 clock 50 ns at 20 MHz 2 clocks 100 ns at 20 MHz 12 bytes Compatible with TLCS 900 900 L 900 H 900 L1 and 900 H2 instruction codes However NORMAL MAX MIN and LDX instructions is deleted Only maximum mode 8 channels 92CM22 7 2007 02 16 TOSHIBA TMP92CM22 3 1 2 Reset Operation When resetting the TMP92CM22 microcontroller ensure that the power supply voltage is within the operating voltage range and that the internal high frequency oscillator has stabilized Then hold the RESET input to low for at l
61. c STOP mode When STOP mode is selected all internal circuits stop including the internal oscillator pin status in STOP mode depends on the settings in the SYSCR2 lt SELDRV DRVE gt register Table 3 3 5 Table 3 3 6 shows the state of these pins in STOP mode After STOP mode has been released system clock output starts when the warm up time has elapsed in order to allow oscillation to stabilize Warm up time set by SYSCR2 lt WUPTM1 0 gt register See the sample warm up times in Table 3 3 4 Figure 3 3 8 illustrates the timing for release of the STOP mode halt state by an interrupt Warm up time D DO to 15 baa 4 4 4 4 45 EN I Interrupt of releasing halt gt Figure 3 3 8 Timing Chart for STOP Mode Halt State Released by Interrupt Table 3 3 4 Sample Warm up Times after Rrelease of STOP Mode atfoscH 10 MHz SYSCR2 lt WUPTM1 0 gt 01 2 10 2 11 2 92CM22 26 2007 02 16 TOSHIBA TMP92CM22 Table 3 3 5 Input Buffer State Table Input Buffer State In HALT mode IDLE1 STOP Input Buffer State Input Buffer State Input Condition A Note Condition B Note When When When When Used as Used as Used as Used as function function function function P10 P17 D8 D15 external OFF read 2 2 2 m INT4
62. due to a delay in the read signal Such an unintended read cycle may cause a trouble as in the case of a in Figure 3 6 3 20 MHz Address 0 MJ L Memory 1 chip select 2 chip select Figure 3 6 3 Read Signal Delay Read Cycle Example When using an externally connected flash EEPROM which users JEDEC standard commands note that the toggle bit may not be read out correctly If the read signal in the cycle immediately preceding the access to the flash EEPROM does not go high in time as shown in Figure 3 6 4 an unintended read cycle like the one shown in b may occur Toggle bit Memor 1 CLKOUT A NS N 1 address KK 1 Flash EEPROM chip select __ Aa X 7 Read 1 1 1 1 Toggle bit N b Figure 3 6 4 Flash EEPROM Toggle Bit Read Cycle When the toggle bit reverse with this unexpected read cycle TMP92CM22 always reads same value of the toggle bit and cannot read the toggle bit correctly To avoid this phenomenon the data polling control recommended 92CM22 97 2007 02 16 TOSHIBA TMP92CM22 2 The cautions at the time of the functional change of a CSn A chip select signal output has the case of a combination terminal with a general purpose port function In this case an output latch register and a function control register are initialized by the reset action and an object terminal is initialize
63. for maskable interrupts Level 6 regardless of the priority level of the interrupt source Because the micro DMA function is implemented through the CPU when the CPU 1s placed in a stand by state by a Halt instruction the requirements of the micro DMA will be ignored pending Micro DMA is supports 8 channels and can be transferred continuously by specifying the micro DMA burst function as below 1 Micro DMA operation When an interrupt request is generated by an interrupt source specified by the micro DMA start vector register the micro DMA triggers a micro DMA request to the CPU at interrupt priority level 6 and starts processing the request The eight micro DMA channels allow micro DMA processing to be set for up to eight types of interrupt at once When micro DMA is accepted the interrupt request flip flop assigned to that channel is cleared Data in one byte two byte or four byte blocks is automatically transferred at once from the transfer source address to the transfer destination address set in the control register and the transfer counter is decremented by 1 If the value of the counter after it has been decremented is not 0 DMA processing ends with no change in the value of the micro DMA start vector register If the value of the decremented counter is 0 a micro DMA transfer end interrupt INTTCO to INTTC7 is sent from the CPU to the interrupt controller In addition the micro DMA start vector register is cleared to 0 th
64. for the SIO Mode 92CM22 190 2007 02 16 TOSHIBA TMP92CM22 Serial Bus Interface 0 Control Register 2 o7 6 5 4 2 1 0 49H Read Function Serial bus interface Note 2 Note 2 5 operation mode selection modify write 00 Port mode instruction is 01 SIO mode prohibited 10 bus mode 11 Reserved Note 1 Set the SBIOCR1 lt BC2 0 gt to 000 before switching Serial bus interface operation mode selection to a clocked synchronous 8 bit SIO mode 00 Port mode Serial bus interface output disabled Note 2 Please always write 00 to SBICR2 lt 1 0 gt Clocked synchronous 8 bit SIO mode bus mode Reserved Serial Bus Interface 0 Status Register peri aaa eq nd per Rama L Hr De poop a eee eee Function Serial Shift transfer operation operation status status monitor monitor Serial transfer operating status monitor Shift operation status monitor 0 Transferterminated O Shiftoperationterminated Serial Bus Interface 0 Baud Rate 0 SBIOBRO eg c ee pce e ee Hoag 4 uu Ed instruction is write 0 prohibited Note mode cannot operate in IDEL2 mode Serial Bus Interface 0 Ba
65. generates the basic clock for transmitting and receiving data In I O interface mode In SCLK output mode with the setting SCOCR lt IOC gt 0 the basic clock is generated by dividing the output of the baud rate generator by 2 as described previously In SCLK input mode with the setting SCOCR lt IOC gt 1 the rising edge or falling edge will be detected according to the setting of the SCOCR lt SCLKS gt register to generate the basic clock In UART mode The SCOMODO SCI 0 setting determines whether the baud rate generator clocks the internal system clock the trigger output signal from TMRAO or the external clock SCLKO pin is used to generate the basic clock SIOCLK 4 Receiving counter The receiving counter is a 4 bit binary counter used in UART mode that counts up the pulses of the SIOCLK clock It takes 16 SIOCLK pulses to receive 1 bit of data each data bit is sampled three times on the 7th 8th and 9th clock cycles The value of the data bit is determined from these three samples using the majority rule For example if the data bit is sampled respectively as 1 0 and 1 on 7th 8th and 9th clock cycles the received data bit is taken to be 1 data bit sampled as 0 0 and 1 are taken to be 0 b Receiving control In I O interface mode In SCLK output mode with the setting SCOCR lt IOC gt 0 the RXDO pin is sampled on the rising or falling edge of the shift clock which is output on the SCLK
66. is written to the register buffer immediately before an overflow occurs by a match between the timer register value and the up counter value the timer flip flop may output an unexpected value For this reason make sure that in PWM mode new data is written to the register buffer by six cycles x 6 before the next overflow occurs by using an overflow interrupt When using PPG mode make sure that new data is written to the register buffer by six cycles before the next cycle compare match occurs by using a cycle compare match interrupt Example when using PWM mode Match between TAOREG and up counter 2 overflow interrupt INTTAO TA1OUT tPWM PWM cycle 1 i Desired PWM cycle i change point Write new data to the register buffer before the next overflow occurs by using an overflow interrupt 92CM22 104 2007 02 16 TOSHIBA TMP92CM22 3 7 3 SFRs TMRAO1 Run a 9 LIE Function TMRAO1 buffer prescaler e puma 0 Disable 1 Operate UC1 UCO 1 Enable 0 Stop and clear 1 Run Count up TAOREG double buffer control Count operation pene stop and sear Note The values of bits 4 to 6 of TAO1RUN are undefined when read TMRA23 Run Register TA23RUN E TA2RDE 2 23 TA23PRUN TASRUN TA2RUN ia ee Peres Qf m o _ Function Double IDLE2 TMRA23 UP buf
67. oscillator Murata Manufacturing Co Ltd Following table shows circuit parameter recommended Oscillation Item of Oscillator Parameter of Elements Running Condition ype IC Frequenc quency Old numter E Tc lt MHz SMD CSTCG20M0V51 RO 6 New New and old is same 20 000 product No CSCTW20M0X51 RO 5 CSTCW2000MX01 CSTCW36M0X51 RO 6 30 000 CSTCW3600MX01 40 000 2 pin CSACWA0MOX51 RO SMD CSACW4000MX01 Note 1 of C1 and C2 are built in condenser type CSTCR4M00G55 RO New and old is same 4 000 product No Lond CSTLS4M00G56 BO 47 CSTS0400MG06 CSTCR6MO00G55 RO 39 New and old is same 6 000 product No CSTLS6M00G56 BO 47 47 CSTS0600MG06 CSTCE10M0G55 RO New and old is same TMP92CM22FG 40 000 product No 3 0t0 3 6 40 to 85 CSTLS10M0G53 BO 15 CSTS1000MG03 Note 2 The product numbers and specifications of the resonators by Murata Manufacturing Co Ltd are subject to change For up to date information please refer to the following URL http Awww murata co jp 92CM22 227 2007 02 16 5 TOSHIBA TMP92CM22 Table of Special Function Registers SFRs The SFRs include the I O ports and peripheral control registers allocated to the 8 Kbytes address space from 000000H to 001FFFH 1 I O port 2 Interrupt controller 3 DMA controller 4 Memory controller 5 Clock gear PLL 6 8 bit timer 7 16 bit timer 8 UART SIO
68. priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt request 92CM22 41 2007 02 16 TOSHIBA TMP92CM22 2 Externalinterrupt control swo Name Adress 7 6 lt lt sence ence ence ence oe numee pec es 00F6H INT3EDGE INT2EDGE INTTEDGE INTOEDGE INTO NMI Prohibit 0 Rising 10 Rising 10 Rising 0 Rising 0 Edge 0 Falling RMW high high high high 1 Level edge 1 Falling 1 Falling 1 Falling 1 Falling 1 Falling low low low low and rising edges Interrupt input mode control me me me mas Prohibit _ ee control2 level L level Rising Falling IXEDGE Note 1 Disable INTO to INT3 before changing INTO to 3 pins mode from level to edge Detect edge Setting example for case of INTO DI LD LD INTCLR OAH NOP NOP NOP X Don t care No change Change from level to edge Clear interrupt request flag Wait El execution Note 2 See electrical characteristics in section 4 for external interrupt input pulse width Note 3 When release halt by INTO to INT interrupt of level mode in interrupt request enable keep setting lev
69. processing Acc lt SCOCR AND 00011100 Check for error if Acc 0 ERROR Acc lt SCOBUF Read receiving data X Don t care No change 92 22 165 2007 02 16 TOSHIBA TMP92CM22 4 Mode 3 9 bit UART mode 9 bit UART mode is selected by setting SCOMODO lt SM1 0 gt to 11 In this mode parity bit cannot be added In the case of transmission MSB 9th bit is programmed to SCOMODO lt TB8 gt In the case of receiving it is stored in SCOCR lt RB8 gt When the buffer is written and read the MSB is read or written first before the rest of the SCOBUF data Wakeup function In 9 bit UART mode the wakeup function for slave controllers 18 enabled by setting SCOMODO0 lt WU gt to 1 The interrupt INTRXO occurs only when lt 8 gt 1 TXD RXD TXD RXD TXD RXD TXD RXD Master Slave 1 Slave 2 Slave 3 Note The TXD pin of each slave controller must be in open drain output mode Figure 3 9 23 Serial Link Using Wakeup Function 92 22 166 2007 02 16 TOSHIBA TMP92CM22 Protocol 1 Select 9 bit UART mode on the master and slave controllers 2 Set the SCOMODO WUP bit on each slave controller to 1 to enable data receiving 3 The master controller transmits one frame data including the 8 bit select code for the slave controllers The MSB Bit8 lt TB8 gt is set to 1 Nsa 5 X 6X 7 5 Select code of slave controller 1 4 Each
70. pulled down to the low level while lt PIN gt is 0 When an interrupt request is generated lt TRX gt is changed according to the direction bit only when an acknowledge signal is returned from the slave device 2 Slave mode In the slave mode the start condition and the slave address are received After the start condition is received from the master device while eight clocks are output from the SCL pin the slave address and the direction bit that are output from the master device are received When a GENERAL CALL or the same address as the slave address set in I2COAR is received the SDA line is pulled down to the low level at the 9th clock and the acknowledge signal is output An INTSBE interrupt request is generated on the falling edge of the 9th clock The PIN is cleared to 0 In slave mode the SCL line is pulled down to the low level while the lt PIN gt 0 92CM22 184 2007 02 16 TOSHIBA TMP92CM22 SCL line SDA line e signal from a Start condition Slave address Direction bit slave device lt PIN gt INTSBEO interrupt ____ L Output of master Output of slave Figure 3 10 13 Start Condition and Slave Address Generation 3 1 word data transfer Check the lt MST gt by the INTSBEO interrupt process after the 1 word data transfer is completed and determine whether the mode is a master or slave 1 If MST 1 Master mode Check
71. request is generated to request that the received data be read The data is then read from the SBIODBR by the interrupt service program When the internal clock is used the serial clock will stop and the automatic wait function will be in effect until the received data 15 read from the SBIODBR When the external clock is used since shift operation is synchronized with an external clock pulse the received data should be read from the SBIODBR before the next serial clock pulse is input If the received data is not read further data to be received is canceled The maximum transfer speed when an external clock is used is determined by the delay time between the time when an interrupt request 15 generated and the time when the received data is read Receiving of data ends when the lt SIOS gt is cleared to 0 by the INTSBEO interrupt service program or when the lt SIOINH gt is set to 1 If lt SIOS gt is cleared to 0 received data is transferred to the SBIODBR in complete blocks The received mode ends when the transfer is completed In order to confirm whether data is being received properly by the program the SBIOSR lt SIOF gt to be sensed The lt SIOF gt is cleared to 0 when receiving is completed When it is confirmed that receiving has been completed the last data is read When the lt SIOINH gt is set to 1 data receiving stops The lt SIOF gt is cleared to 0 The received data becomes invalid the
72. ui 0 mam 0 0 vui 1 Output 1 Output 1 Output 1 Output pec now PotD 0037H function Prohibit register RMW 0 Port Port Port 0 1 TB1OUT1 1 TB1OUTO 1 TBOIN1 1 TBOINO INT5 input INT4 input Port 003EH PF7C PF6C PF5C PF4C PF3C PF2C 1 or control Prohibit egets ARM 0 gp 0 Input 1 Output 7 00 0 pesca aea gt if PC6C PC5C WAY AE WIL Port C 0032H control Prohibit register RMW og 9 c Ji Port C 0033H function Prohibit register RMW Port D 0036H control Prohibit register RMW Z p EA a a 1 a e penes a oe DE Port F 003FH function Prohibit register RMW Always Always 0 Port tS Port Port write 0 write 0 1 SCLK1 1 TXD1 1 SCLKO 1 TXDO output output Note When using SI and SCK input function set P9FC lt P92F P90F gt to 0 Function setting 92CM22 234 2007 02 16 TOSHIBA TMP92CM22 2 Interrupt control 1 2 Name assess 7 6 INT2 INT1 A enable INTE12 0 0 0 0 0 0 0 0 1 INT2 Interrupt request level 1 INT Interrupt req
73. via the timer output pins TBOOUTO which is shared with PC6 Timer output should be specified using the port C function register 92CM22 126 2007 02 16 TOSHIBA TMP92CM22 3 8 3 SFRs TMRBO Run Register TEOPRUN freon un fraw RW Pw w faterreset Function Double Always IDLE2 TMRBO Up counter buffer write 0 0 Stop Prescaler UC10 0 Disable 1 Operate 0 Stop and clear 1 Enable 1 Run Count Count operation Stop and clear Note The values of bits 1 4 and 5 of TBORUN are undefined when read 1 Run Register 7 6 5 4 2 1 j 0 Brsmbo fraw mw Function Double TMRB1 Up counter buffer Prescaler UC12 0 Disable 0 Stop and clear 1 Enable 1 Run Count Count operation Stop and clear Note The values of bits 1 4 and 5 of TB1RUN are undefined when read Figure 3 8 3 Register for TMRB 92CM22 127 2007 02 16 TOSHIBA TMP92CM22 TMRBO Mode Register LE x 9 TBOMOD Bitsymb TBOCPM TBOCPMO TBOCLE TBOCLK TBOCLKO 1822 Readwrite __ RW w After reset cuis gu ee
74. write instruction is prohibited for registers PECR and P6FC Note2 When these ports are used as general purpose l O port each bit can be set individually for input or output However each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port All of general purpose I O ports except for port that used as address bus are operated as output port Please be careful when using this setting Figure 3 5 8 Register for Port 6 92CM22 59 2007 02 16 TOSHIBA 3 5 5 TMP92CM22 Port 7 P70 to P76 Port 7 is a 7 bit general purpose I O port P70 to P75 are used for output only Bits can be individually set as either inputs or outputs by control register P7CR and function register P7FC In addition to functioning as a general purpose I O port P70 to P73 pins can also function as output pin of read write strobe signals to connect with an external memory P74 pin can also function as CLKOUT output pin when outputted internal clock 76 pin can also function as wait input After reset P71 to P75 pins are set to output port mode and P76 pin is set to input port mode P70 pin set port 1 to pins of follow function by combination of AM1 and AMO pins Function Setting after Reset 17252174053 Dont use this setting 1 CPUcontolpin 25 1 CPUcontolpin 25 Don t use this setting Reset E Function control on bit basis Output latch RS P7 read
75. 0 Disable 0 TMRAO 1 Enable T IMBAI Inversion signal for timer flip flop 1 TA1FF Don t care except in 8 bit timer mode inversion by _ control for inversion Disable inversion TFF1 control 00 Invert Set TATFF to 1 Note values of bits 4 to 7 of TA1FFCR are undefined when read 10 Glear TA1FF to 0 H Figure 3 7 7 Register for TMRA 92CM22 108 2007 02 16 TOSHIBA TASFFCR Bit symbol 110DH Read modify write instruction is prohibited Note pum TMRAS Flip Flop Control Register gp eeu po LI o S w S porc peel eism cg pes The values of bits 4 to 7 of TA3FFCR are undefined when read Figure 3 7 8 Register for TMRA 92CM22 109 00 Invert TA3FF 01 Set TA3FF to 1 inversion 10 Clear TA3FF to 0 inversion select 11 Don t care 0 Disable 0 TMRA2 TMP92CM22 TASFFCO TASFFCIE TA3FFCIS R W 1 Enable 1 TMRA3 Inverse signal for timer flip flop 3 TA3FF Don t care except in 8 bit timer mode 0 Invert TMRA2 Invert TMRA3 TASFF control for inversion Disable inversion Enable inversion TASFF control 00 Invert TA3FF Set to 1 Clear to 0 2007 02 16 TOSHIBA TMP92CM22 Timer Register TAOREG to
76. 119 9 co wWgdoral 119 donta 1 10 99 8S lt 2191 1 gt 1 lt NNY LaL gt NNY LaL 0 02 15091 rt OLNO LEL 044091 EI lt 04218 1 gt GOW EL VHIEdOLEL VHOdO dL 491 1 9 0 4 5 9116 1 lt 181 gt Woy SLNI V LNI 1dnuejul 01 Figure 3 8 2 Block Diagram of TMRB1 2007 02 16 92CM22 122 TOSHIBA TMP92CM22 3 8 2 Operation 1 Prescaler The 5 bit prescaler generates the source clock for TMRBO The prescaler clock 0 is a divided clock Divided by 8 from selected clock by the register SYSCR1 lt GEAR1 0 gt of clock gear This prescaler can be started or stopped using TBORUN lt TBOPRUN gt Counting starts when TBOPRUN is set to 1 the prescaler is cleared to zero and stops operation when TBOPRUN is cleared to 0 Table 3 8 2 show prescaler output clock resolution Table 3 8 2 Prescaler Output Clock Resolution Clock gear Timer counter input clock selection TMRB prescaler SYSCR1 TBOMOD lt TBOCLK1 0 gt fc 16 fc 64 fc 256 fc 32 fc 128 fc 512 fc 64 fc 256 fc 1024 fc 128 fc 512 fc 2048 100 1 16 fc 256 1024 fc 4096 2 Up counter UC10 UC10 is a 16 bit binary counter that counts up according to inpu
77. 2 Function control signal Output port lt 1 signal 7 A23 to AO n n 2 92CM22 98 2007 02 16 TOSHIBA TMP92CM22 3 7 8 Bit Timers TMRA The TMP92CM22 features 4 built in 8 bit timers These timers are paired into four modules 1 and TMRA23 Each module consists of two channels and can operate in any of the following four operating modes e 8 bit interval timer mode e 16 bit interval timer mode e 8 16 programmable square wave pulse generation output mode PPG Variable duty cycle with variable period e amp bit pulse width modulation output mode PWM Variable duty cycle with constant period Figure 3 7 1 and Figure 3 7 2 show block diagrams for 1 and TMRA23 Each channel consists of an 8 bit up counter 8 bit comparator and an 8 bit timer register In addition a timer flip flop and a prescaler are provided for each pair of channels The operation mode and timer flip flops are controlled by five controls SFR Special function registers Each of the two modules TMRAO1 and TMRA23 can be operated independently modules operate in the same manner hence only the operation of TMRAOI is explained here The contents of this chapter are as follows 3 7 1 Block diagrams 3 1 2 Operation of Each Circuit 3 7 8 SFRs 3 7 4 Operation in Each Mode 1 8 bit timer mode 2 16 bit timer mode 3 8 bit PPG Programmable pulse generation output mode 4 8 bit
78. 2 4 8 bit PWM Pulse width modulation output mode This mode is only valid for TMRAO In this mode a PWM pulse with the maximum resolution of 8 bits can be output When TMRAO is used the PWM pulse is output on the TA1OUT pin which is also used PC1 can also be used as 8 bit timer The timer output is inverted when up counter matches the value set in the timer register TAOREG or when 2 counter overflow occurs n 6 7 or 8 as specified by 1 lt 1 00 gt The up counter is cleared when 2 counter overflow occurs The following conditions must be satisfied before this PWM mode can be used Value set in TAOREG Value of set for 2 counter overflow Value set in TAOREG z 0 Match with TAOREG and UCO 2 overflow Interrupt INTTAO TA1OUT tPWM PWM cycle Figure 3 7 16 8 Bit Output Wave Form Figure 3 7 17 shows a block diagram representing this mode TAO1RUN TAORUN TATOUT TAOIN 1 TA1FFCR 474 Selector lt gt 16 Inversion 01 lt 1 0 gt lt PWM01 00 gt INTTAO Selector TAOREG WR Register buffer TA01RUN lt TAORDE gt Internal data bus Figure 3 7 17 Block Diagram of 8 Bit PWM Output Mode 92CM22 117 2007 02 16 TOSHIBA TMP92CM22 In this mode the value of the register buffer will be shifted into TAOREG if 2 overflow is detected when the TAOREG doubl
79. 2 output SDA Port 9 P SI input SCL Open drain X Don t care When these ports are used as general purpose l O port each bit can be set individually for input or output However each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port All of general purpose ports except for port that used as address bus are operated as output port Please be careful when using this setting Port 7 P70 to P75 Output port x None RD output WRLL output CLKOUT output P80 P81 P82 P83 91 92 o c 92 22 50 2007 02 16 TOSHIBA Table 3 5 3 Port Setting List 2 2 TMP92CM22 input Pins Spdcitication Register Setting Value PortA PAO PA1 Input port Port D Port F Port G Inptpot ___________ port Po o gt 1 313 pe Po 1 p remna 9 0 eo Pa UNE e eR LM E monem mora LN o emm am Er PGO to PG7 Input port _ ANO to AN7 input x None None Pes ADTRG mut ADTRG input X Don t care
80. 22 9 Transmission buffer The transmission buffer SCOBUF shifts out and sends the transmission data written from the CPU form the least significant bit in order When all the bits are shifted out the transmission buffer becomes empty and generates an INTTXO interrupt 10 Parity control circuit When SCOCR lt PE gt in the serial channel control register is set to 1 it is possible to transmit and receive data with parity However parity can be added only in 7 bit UART mode 8 bit UART mode SCOCR lt EVEN gt field in the serial channel control register allows either even or odd parity to be selected In the case of transmission parity is automatically generated when data is written to the transmission buffer SCOBUF The data is transmitted after the parity bit has been stored in SCOBUF lt TB7 gt in 7 bit UART mode or in SCOMODO lt TB8 gt in 8 bit UART mode SCOCR lt PE gt and SCOCR lt EVEN gt must be set before the transmission data is written to the transmission buffer In the case of receiving data is shifted into receiving buffer 1 and the parity is added after the data has been transferred to receiving buffer 2 SCOBUF and then compared with SCOBUF lt RB7 gt in 7 bit UART mode with SCOCR lt RB8 amp gt in 8 bit UART mode If they are not equal a parity error is generated and the SCOCR PERR flag is set 11 Error flags Three error flags are provided to increase the reliability of data reception 1
81. 22 145 2007 02 16 TOSHIBA TMP92CM22 2 Baud rate generator The baud rate generator 13 a circuit that generates transmission and receiving clocks that determine the transfer rate of the serial channels The input clock to the baud rate generator 2 8 or 2 is generated by the 6 bit prescaler which is shared by the timers One of these input clocks is selected using the lt 0 gt field in the baud rate generator control register The baud rate generator includes a frequency divider which divides the frequency by 1 or N 16 K 16 to 16 values determining the transfer rate The transfer rate is determined by the settings of BROCR lt BROADDE BROS3 0 gt and BROADD lt BROK3 0 gt In UART mode 1 When BROCR lt BROADDE gt 0 The settings BROADD lt BROK3 0 gt are ignored The baud rate generator divides the selected prescaler clock by 1 2 3 16 which is set in BROCR BRO0S3 0 2 When BROCR lt BROADDE gt 1 The 16 K 16 division function is enabled The baud rate generator divides the selected prescaler clock by 16 K 16 using the value of N 2 3 15 set in BROCR BR0S3 0 and the value of K 1 2 3 15 set in BROADD lt BROK3 0 gt Note If N 1andN 16 the 16 16 division function is disabled Clear BROCR BROADDE register to 0 In T O interface mode The N 16 K 16 division function is not ava
82. 3 3 1 System Clock Block Diagram The clock frequency input from the X1 and X2 pins is called fosc and the clock frequency selected by SYSCR1 lt GEAR2 0 gt is called the clock The system clock is defined as the divided 2 clocks of and one cycle of fsys is defined to as one state 92CM22 12 2007 02 16 TOSHIBA TMP92CM22 3 3 1 Block Diagram of System Clock SYSCR2 lt WUPTM1 0 gt PLLCR lt PLUPFG gt Warm up timer for high frequency oscillator lockup for PLL timer fPLL foscH 4 1 High frequency 2 oscillator PLLCR lt FCSEL gt to and TMRBO to TMRB1 TT 5100 and SIO1 ADC B Interrupt controller port SBI PE Figure 3 3 2 Block Diagram of Dual Clock and System Clock 92CM22 13 2007 02 16 TOSHIBA TMP92CM22 3 8 2 SFRs pede i us tie SYSGRO i symbol ces op RAN om a w ipee el ree n ln 0 Su Function Always Always write 1 write 0 sysort GEARS i RNA Function Always Select gear value of high write 0 frequency oscillator 000 High frequency oscillator 001 High frequency oscillator 2 010 High frequency oscillator 4 011 High frequency oscillator 8 100 High frequency oscillator 16 101 110 Reserved 111 sysore
83. 5 Register Eres TIERE EU C T ver me e rm un m T Port 5 Control Register GENE SET SECURUS ERI 0016H Merreset o 0 Input 1 Output Note2 Port 5 Function Register ser 0 Qo Redde S o Fiere 1 0 1 Address bus A8 to 15 Note1 Read modify write instruction is prohibited for registers PSCR and P5FC Note2 When these ports are used as general purpose port each bit can be set individually for input or output However each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port of general purpose ports except for port that used as address bus are operated as output port Please be careful when using this setting Figure 3 5 6 Register for Port 5 92CM22 57 2007 02 16 TOSHIBA 3 5 4 TMP92CM22 Port 6 P60 to P67 Port 6 is an 8 bit general purpose I O port Bits can be individually set as either inputs or outputs by control register P6CR and function register P6FC In addition to functioning as a general purpose I O port port 6 can also function as an address bus A16 to A23 After released reset device set port 6 to pins of follow function by combination of AMI and AMO pins
84. 6 32 Ti x2 4 8 16 32 1024 fc 4096 fc 16384 fc 2048 fc 8192 fc 32768 fc 4096 fc 16384 fc 65536 xB 5 Mode settings Table 3 7 5 shows the SFR settings for each mode Table 3 7 5 Timer Mode Setting Registers Register Name TA01MOD TA1FFCR lt Bit symbol gt lt TA01M1 0 gt lt PWMO01 00 gt lt TA1CLK1 0 gt lt 1 0 gt lt 1 5 gt L r timer Timer F F Function Timer mode PWM cycle Hipper timer 005 AUN 5 input clock input clock inversion select 0 Lower timer Lower timer match External output 8 bit timer x 2 channels 9 1 116 256 T1 4 6116 00 01 10 11 00 01 10 11 1 timer output External 16 bit timer mode T1 4 00 01 10 External 8 bit PWM x 1 channel T1 4 716 8 bit PPG x 1 channel T1 4 00 01 10 edo DO 00 01 10 11 8 bit timer x 1 channel 11 ghe pese Output disable 01 10 11 Don t care 92CM22 119 2007 02 16 TOSHIBA TMP92CM22 3 8 16 Bit Timer Event Counters TMRB The TMP92CM22 contains 2 channels 16 bit timer event counter TMRB which have the following operation modes e 16 bit interval timer mode e 16 bit event counter mode e 16 bit programmable square wave pulse generation output mode PPG Variable duty cycle with variable period Can be used following operation modes by capture function e Frequency measurement mode e Pulse width measur
85. 8 bit timer Name ess 7 5 5 TMRAO1 RUN register TAO1RUN TAOREG register 0 TA1REG register 1 TMRAO1 mode register 01 TMRA1 flip flop control register TA1FFCR TMRA23 RUN register TA23RUN 8 bit timer register 2 TA2REG 8 bit timer register 3 TASREG TMRA23 mode register TA23MOD TMRA3 flip flop control register TA3FFCR 8 bit timer 8 bit timer _ 2 i 0 2 01 TAO1PRUN TA1RUN TAORUN prescaler UC1 UCO 1 Run Count up Undefined ccc 0 Disable 1 Enable 1102H Prohibit RMW 1103H Prohibit RMW Undefined R W ARAARA Operation mode PWM cycle Source clock for TMRA1 Source clock 00 8 bit timer mode 00 Reserved 00 TAOTRG 00 TAOIN pin 01 16 bit timer mode 01 2 01 971 01 1 10 8 bit PPG mode 10 27 10 16 10 674 11 PWM mode 11 2 11 61256 11 6716 TATFFIE TATFFIS RW 00 Invert TA1FF 01 Set TA1FF 10 Clear TA1FF 11 Don t care 1105H Prohibit RMW 0 Disable 1 Operate 0 Stop and clear 1 Run Count up 110AH Prohibit RMW 110BH Prohibit W RMW Undefined R W Undefined Source clock for Source clock for TMRA2 00 TA2TRG 00 Reserved 01 oT1 01 oT1 10 oT16 10 4 11 256 11 oT16 TA3FFCO o0 o
86. 9 bus SIO 10 10 bit ADC 11 WDT Table layout oe tect Bit symbol Rewi pian we gt Initial value after reset i1 i1 E gt Remarks Note Prohibit RMW in the table means that you cannot use RMW instructions on these register Example When setting bitO only of the register PxCR the instruction SET 0 PxCR cannot be used The LD Transfer instruction must be used to write all eight bits Read Write R W Both read and write are possible R Only read is possible W Only write 1s possible W Both read and write are possible when this bit is read as 1 Prohibit RMW Read modify write instructions are prohibited The EX ADD ADC BUS SBC INC DEC AND OR XOR STCF RES SET CHG TSET RLC RRC RL RR SLA SRA SLL SRL RLD and RRD instruction are read modify write instructions R W Read modify write is prohibited when controlling the pull up resistor 92CM22 228 2007 02 16 TOSHIBA TMP92CM22 Table 5 1 Register Address 1 I O port Note Do not access un named addresses 92CM22 229 2007 02 16 TOSHIBA TMP92CM22 2 Interrupt controller 3 controller INTE12 INTE45 INTEOAD DMAOV INTE3 INTETB1 INTETCO1 DMA1V INTETBO1 INTETC23 DMA2V INTESBO INTETC45 DMA3V INTETAO1 INTETC67 DMA4V INTETA23 SIMC DMA5V DMA6V INTWDT DMA7V INTETBO INTCLR DMAB DMAR INTETBOO 2 Reserved INTESO INTES1 INTEPO 4 Memory con
87. AN1 AN2 AN3 AN4 AN5 AN6 111 7 2 AN4 AN5 AN6 AN7 AD mode ADMOD2 control i external register 2 trigger start control 0 Disable 1 Enable AD result ADREGOL register 12 Dec sec eee ee eiu AD result ADREGOH register o high Undefined AD resul A sj 0 _ pem a a C y ADREGtH register 1 high Undefined AD result ADR21 ADR20 ADRERF FSS Undefined se Toup eap VI o SES poreo ga A ADREGAH register2 high Undefined AD result ADR30 1 ADRSRF ADBEGSL ree p oup cS 1 E Urdefined 0 AD result eee register high Undefined 92CM22 248 2007 02 16 TOSHIBA TMP92CM22 AD converter 2 2 Symbol Name 7 _5 ADREG4L ADREG4H ADREGSL ADREG5H ADREG6L ADREG6H ADREG7L ADREG7H AD result register 4 low AD result register 4 high AD result register 5 Low AD result register 5 high AD result register 6 low AD result register 6 high AD result register 7 low AD result register 7 high PP P AT Undefined
88. B1CPOL Capture register 0 high TB1CPOH Capture register 1 low TB1CP1L Capture register 1 high TB1CP1H Always buffer 0 Disable 1 Enable write 0 0 Stop 1 Operate TMRB1 UP counter prescaler UC12 0 Stop and clear 1 Run Count up R W R W TB1FF1 inversion trigger 0 Disable trigger 1 Enable trigger 1192H Prohibit RMW Control TB1FF1 1193H 100 Invert Capture timing 00 Disable 01 TB1NO 7 TB1IN1 7 10 TB11NO 7 TB11NO 4 11 TATOUT 1 1 0 Software capture 1 Undefined TBOFFO inversion trigger 0 Disable trigger Up counter Timer B1 source clock control 00 TB1INO pin input 0 Clear 01 1 disable 110 4 1 Clear 11 9T16 enable Control TB1FFO 00 Invert Prohibit RMW 01 Set 10 Clear 11 Don t care 1 Enable trigger Invert when the UC12 Invert when the UC12 Invert when the UC12 01 Set 10 Clear 11 Don t care Always read as 11 1198H Prohibit RMW 1199H Prohibit RMW 119AH Prohibit RMW 119BH Prohibit RMW value matches the value is loaded in to TB1CPOH L Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 92CM22 243 value Always read as 11 matches the 2007 02 16 TOSHIBA TMP92CM22 8 UART Serial channel 1 2 Name e 7 1 3 Serial channel 0 buffer register
89. BA TMP92CM22 4 Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector as given in Table 3 4 1 to the register INTCLR For example to clear the interrupt flag INTO perform the following register operation after execution of the DI instruction INTCLR lt OAH Clears interrupt request flag INTO Symbol Name Address 7 6 5 4 3 2 j t1 C crave __ Interrupt F8H INTCLR clear Prohibit control RMW Interrupt clear b Micro DMA start vector registers This register assigns micro DMA processing to which interrupt source The interrupt source with a micro DMA start vector that matches the vector set in this register 1s assigned as the micro DMA start source When the micro transfer counter value reaches 0 the micro transfer end interrupt corresponding to the channel is sent to the interrupt controller the micro start vector register is cleared and the micro DMA start source for the channel is cleared Therefore to continue micro DMA processing set the micro DMA start vector register again during the processing of the micro DMA transfer end interrupt If the same vector is set in the micro DMA start vector registers of more than one channel the channel with the lowest number has a higher priority Accordingly if the same vector is set in the micro DMA start vector regi
90. DT disable code Instruction 4 clear code is prohibited WDT disable clear control Disable code Figure 3 12 5 Watchdog Timer Control Register 92CM22 214 2007 02 16 TOSHIBA TMP92CM22 4 Electrical Characteristics 4 1 X Absolute Maximum Ratings Power supply voege ve 05040 COS Ven 05 ion f 2 1 K current 0 w Output Tota w mw J Note The absolute maximum ratings are rated values that must be exceeded during operation even for an instant Any one of the ratings must not be exceeded If any absolute maximum rating is exceeded the device may break down or its performance may be degraded causing it to catch fire or explode resulting in injury to the user Thus when designing products that include this device ensure that no absolute maximum rating value will ever be exceeded Solderability of lead free products Test Test condition Note parameter Solderability 1 Use of Sn 37Pb solder Bath Pass Solder bath temperature 230 C Dipping time 5 seconds solderability rate until forming gt 95 The number of times one Use of R type flux 2 Use of Sn 3 0Ag 0 5Cu solder bath Solder bath temperature 245 C Dipping time 5 seconds The number of times one Use of R type flux use of lead free 92CM22 215 2007 02 16 TOSHIBA TMP92CM22 DC Charac
91. EAT gt After the current conversion has been completed the repeat conversion mode terminates and lt gt is cleared to 0 Switching to a halt state IDLE2 mode with ADMOD1 lt I2AD gt cleared to 0 IDLE1 mode or STOP mode immediately stops operation of the AD converter even when AD conversion is still in progress In repeat conversion modes e g in cases c and d when the halt is released conversion restarts from the beginning In single conversion modes e g in cases a and b conversion does not restart when the halt is released The converter remains stopped Table 3 11 2 shows the relationship between the AD conversion modes and interrupt requests Table 3 11 2 Relationship between the AD Conversion Modes and Interrupt Requests AD Mode Interrupt Request ADMODO Generation Channel fixed single After completion of X conversion mode conversion Channel scan single After completion of scan X 1 conversion mode conversion Channel fixed repeat Every conversion o 1 conversion mode Every forth conversion Channel scan repeat After completion of every X 1 1 conversion mode scan conversion X Don t care 92CM22 208 2007 02 16 TOSHIBA TMP92CM22 5 AD conversion time 84 states 8 4 us at fsys 20 MHz are required for the AD conversion of one channel 6 Storing and reading the results of AD conversion The AD conversion data upper and lower registers ADREGOH L to ADREG7H L stor
92. HIBA TMP92CM22 Example To output a 2 ms one shot pulse with 3 ms delay to the external trigger pulse via the TB11NO pin Clock state Clock gear 1 1 fc Set free running LL Count using 1 TBIMOD XX 10 1 0 0 1 Cr Load into TB1 CPOH L by rising edge of TB1INO pin input lt X X000010 zm lt gt Clear TB1FFO to 0 Disable inversion of TB1FFO Setting in Main PDCR XXX X 1 PD to f i he TB1 TO pin PDFC LX Ow XX cer t X Set to function as the OUTO pin INTE45 X X10 0 E le INT4 Di le INTTB10 and INTTB11 INTET lt nabe PROP ei TB1RUN 0 0 1 X1 Start TMRBO Setting in INT4 TB1RGOH L lt TB1CPOH L ms 9T1 TB1RG1H L lt TB1RGOH L 2 ms 9T1 1 lt X X 1 1 CE e Enable inversion of TB1FFO when match with TB1RGOG L or TB1RG1GIL INTETB1 lt lt X100X Set INTTB11 to enable Setting in INTTB11 TBIFFCR lt X X 0 0 T Disable inversion of TB1FFO when match with TB1RGOH L or TB1RG1H L INTETB1 000 Disable 11 X Don t care No change When delay time is unnecessary invert timer flip flop TB1FFO when up counter value is loaded into capture register TB1CPOH L and set the TB1CPOH L value plus the one shot pulse width p to TBORG1H L when the interrupt INT4 occurs The TB1FFO inversion should be enable when the up counter UC12 value matches and disabled when gene
93. INTO interrupt rising edge 8206H LD INTEOAD 06H Sets INTO interrupt level to 6 8209H El 5 Sets CPU interrupt level to 5 820BH LD SYSCR2 28H Sets HALT mode to IDLE1 mode 820EH HALT 1 Halts CPU 1 INTO interrupt routine 1 INTO 1 1 820 LD XX XX 92CM22 24 2007 02 16 TOSHIBA TMP92CM22 3 Operation a IDLE2 mode In IDLE2 mode only specific internal I O operations as designated by the IDLE2 setting register can take place Instruction execution by the CPU stops Figure 3 3 6 illustrates an example of the timing for clearance of the IDLE2 mode halt state by an interrupt to A23 00 to 015 Interrupt of releasing halt Figure 3 3 6 Timing Chart for IDLE2 Mode Halt State Released by Interrupt b IDLE1 mode In IDLE1 mode only the internal oscillator operates The system clock stops And pin state in IDLE1 mode depend on setting SYSCR2 SELDRV DRVE gt register Table 3 3 5 Table 3 3 6 shows pin state in IDLE1 mode In the halt state the interrupt request is sampled asynchronously with the system clock however clearance of the halt state e g restart of operation is synchronous with it Figure 3 3 7 shows the timing for release of the IDLE1 mode halt state by an interrupt X1 AO to A23 00 to D15 Interrupt of releasing halt Figure 3 3 7 Timing Chart for IDLE1 Mode Halt State Released by Interrupt 92CM22 25 2007 02 16 TOSHIBA TMP92CM22
94. INTSBEO interrupt request SCL SDA PIN INTSBEO interrupt request TMP92CM22 When the lt TRX gt is 0 Receiver mode When the next transmitted data is other than 8 bits set lt BC2 0 gt lt ACK gt and read the received data from SBIODBR to release the SCL line Data which is read immediately after a slave address is sent is undefined After the data is read lt PIN gt becomes 1 Serial clock pulse for transferring new 1 word of data is defined SCL and outputs L level from SDA pin with acknowledge timing An INTSBE interrupt request then generates and the lt PIN gt becomes 0 Then the TMP92CM22 pulls down the SCL pin to the low level The TMP92CM22 outputs a clock pulse for 1 word of data transfer and the acknowledge signal each time that received data is read from SBIODBR 1 2 3 4 5 6 7 8 9 mz Read receiving data 222222072506 5 05 0 03 DA Di DO X ACK XNew D7 Acknowledge signal to a transmitter Output of master Output of slave Figure 3 10 15 Example of when lt BC2 0 gt 000 lt ACK gt 1 Receiver mode In order to terminate the transmission of data to a transmitter clear lt gt to 0 before reading data which 18 1 word before the last data to be received The last data word does not generate a clock pulse as the acknowledge signal After the data has been transmitted and an interrupt request has been generated set lt BC2 0 gt to
95. IT pin input mode Others Reserved BEXCSH gt Read Write o o 0 00 SRAM ROM Default 01 Reserved 10 Reserved 11 Reserved BEXBUS 1 0 00 8 bits Default 01 16 bits 10 Reserved 11 Reserved 92CM22 93 2007 02 16 TOSHIBA TMP92CM22 1 Block address area specification register A start address and range in the block address are specified by the memory start address register MSARn and the memory address mask register MAMRn The memory start address register sets all start address similarly regardless of the block address areas The bit to be set by the memory address mask register is depended on the block address area MSARn 010 MnS lt 23 16 gt Sets a start address Sets the start address of the block address areas The bit is corresponding to the address A23 to A16 MAMRO a aR ECCE E UE ERE E DS EI 0 lt 20 8 gt Enables or masks comparison of the addresses 20 to MOV8 are corresponding to addresses A20 to A8 The bit of 14 to MOVO9 is corresponding to address 14 to A9 by 1 bit If 0 is set the comparison between the value of the address bus and the start address is enabled If 1 is set the comparison is masked MAMR1 a
96. LD SYSCR1 XXXX0100B Changes system clock fsys to fc 32 X Don t care High speed clock gear changing To change the clock gear write the register value to the SYSCR1 lt GEAR2 0 gt register It is necessary the warm up time until changing after writing the register value There is the possibility that the instruction next to the clock gear changing instruction is executed by the clock gear before changing To execute the instruction next to the clock gear switching instruction by the clock gear after changing input the dummy instruction as follows Instruction to execute the write cycle Example SYSCR1 EQU 10E1H LD SYSCR1 XXXX0001B Changes fsys to fc 4 LD DUMMY 00H Dummy instruction Instruction to be executed after clock gear has changed 92CM22 16 2007 02 16 TOSHIBA lt LWUPFG gt TMP92CM22 During lockup After lockup 3 3 4 Clock Doubler PLL PLL outputs the fPLL clock signal which is four times as fast as fOSCH A reset initializes PLL to stop status setting to PLLCR register is needed before use Like an oscillator this circuit requires time to stabilize This is called the lockup time Note 1 Input frequency limitation for PLL The limitation of input frequency High frequency oscillation for PLL is the following foscH 4 to 10 MHz Vcc 3 0 V to 3 6 V Note 2 PLLCR lt LWUPFG gt The logic of PLLCR LUPFG is different from 900 L1 s DFM Be careful to judge an end of lockup time The fol
97. LE gt Figure 3 5 19 Port C PC1 PC5 and PC6 92CM22 67 2007 02 16 TOSHIBA TMP92CM22 3 INTO In addition to function port port can also function as external interrupt pin INTO Reset Direction control on bit basis Function control on bit basis PCFC write S Output latch PC read Internal data bus INTO Selector Select level edge and Select rising falling IIMC IOLE lOEDGE gt S B A Figure 3 5 20 Port C 92CM22 68 2007 02 16 TOSHIBA TMP92CM22 Port C Register qwe oris wes o a Data external Data from Data from external port Note external port Note port Note Note Output latch register is set to 1 Port C Control Register poor roso pose Pore 52 Reaawrte ___ ws wp mersa 0 0 0 0 Function 0 Input 1 Output 0 Input 0 Input 1 Output 1 Output Port C Function Register Fae De p cm pow peer paw Mert 9 9 9 Function 0 Port 0 Port 0 Port 0 Port 1 INT3 1 INT2 1 1 1 1 TAOIN TBOOUTO TA3OUT TA1OUT I
98. NT1 TA1OUT setting om e Input port Output port TA1OUT PCFC 0033H INT2 TA3OUT Setting ea ot Output por INT2 TBOOUTO setting xm e t 0 Inputport Output port INT3 TBOOUTO Note 1 Read modify write instruction is prohibited for the registers PCCR and PCFC Note 2 PCO TAOIN pins do not have a register changing PORT FUNCTION For example when it is used as an input port the input signal is inputted to 8 bit timer as the input 0 Note 3 Can not read the output latch data when PC1 PC5 and PC6 are output mode Figure 3 5 21 Register for Port C 92CM22 69 2007 02 16 TOSHIBA 3 5 10 TMP92CM22 Port D PDO to PD3 Port D is 4 bit general purpose I O port Each bit can be set individually for input or output Resetting sets port D to input port In addition to functioning as a general purpose I O port port D can also function as an input pin INT4 and INT5 output pin TBOIN TB10UT TB3OUT and TB10UT1 These settings operate by programming 1 to the corresponding bit of PDCR and PDFC Resetting resets the PDCR and PDFC to 0 and sets all bits to input port 1 PDO INT4 TB1INO PD1 INT5 TB1IN1 In addition to function as I O port port PDO and PD1 can also function as external interrupt input pins INT4 INT5 timer channel input pins TB1INO and TBIIN1 Reset Direction cont
99. O pin according to the SCOCR lt SCLKS gt setting In SCLK input mode with the setting SCOCR lt IOC gt 1 the RXDO pin is sampled on the rising or falling edge of the SCLK input according to the SCOCR lt SCLKS gt setting In UART mode The receiving control block has a circuit that detects a start bit using the majority rule Received bits are sampled three times when two or more out of three samples are 0 the bit is recognized as the start bit and the receiving Operation commences The values of the data bits that are received are also determined using the majority rule 92CM22 149 2007 02 16 TOSHIBA 6 7 TMP92CM22 The receiving buffers To prevent overrun errors the receiving buffers are arranged in a double buffer structure Received data is stored one bit at a time in receiving buffer 1 which is a shift register When 7 or 8 bits of data have been stored in receiving buffer 1 the stored data is transferred to receiving buffer 2 SCOBUE this causes an INTRXO interrupt to be generated The CPU only reads receiving buffer 2 SCOBUF Even before the CPU reads receiving buffer 2 SCOBUF the received data can be stored in receiving buffer 1 However unless receiving buffer 2 SCOBUF is read before all bits of the next data are received by receiving buffer 1 an overrun error occurs If an overrun error occurs the contents of receiving buffer 1 will be lost although the contents of receiving buffer 2 and SC
100. OCR RBS8 will be preserved SCOCR lt RB8 gt is used to store either the parity bit added in 8 bit UART mode or the most significant bit MSB in 9 bit UART mode In 9 bit UART mode the wake up function for the slave controller is enabled by setting SCOMODO WU to 1 in this mode INTRXO interrupts occur only when the value of SCOCR lt RB8 gt is 1 Transmission counter The transmission counter 13 4 bit binary counter that is used in UART mode and which like the receiving counter counts the SIOCLK clock pulses a TXDCLK pulse is generated every 16 SIOCLK clock pulses 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 TXDCLK 8 Figure 3 9 4 Generation of Transmission Clock Transmission controller InI O interface mode In SCLK output mode with the setting SCOCR lt IOC gt 0 the data in the transmission buffer is output one bit at a time to the TXDO pin on the rising or falling edge of the shift clock which 18 output on the SCLKO pin according to the SCOCR lt SCLKS gt setting In SCLK input mode with the setting SCOCR lt IOC gt 1 the data in the transmission buffer is output one bit at a time on the TXDO pin on the rising or falling edge of the SCLKO input according to the SCOCR lt SCLKS gt setting In UART mode When transmission data sent from the CPU is written to the transmission buffer transmission starts on the rising edge of the next TXDCLK generating a transmission shift cloc
101. OS gt to 0 read the last data and then change the transfer mode 92CM22 197 2007 02 16 TOSHIBA TMP92CM22 Clear lt SIOS gt lt SIOS gt SO pin SI pin co ei ee Aes Ao Ae __ Ado di Ads Aaa Ado Ado Ac INTSBEO eg interrupt SBIODBR Write transmission data a Write transmission data b Read receiving data d lt SIOF gt lt SEF gt SCK pin Output Read receiving data c Figure 3 10 28 Transmission Receiving Mode when an external clock is used SCK pin lt SIOF gt SO Bit6 Bit7 in last transmitted word 1 tsopH 4 15 6 s Min Figure 3 10 29 Transmission Data Hold Time at End of Transmission Receiving Transmission receiving mode 92CM22 198 2007 02 16 TOSHIBA TMP92CM22 3 11 Analog Digital Converter The TMP92CM22 incorporates a 10 bit successive approximation type analog digital converter AD converter with 8 channel analog input Figure 3 11 1 is a block diagram of the AD converter The 8 channel analog input pins ANO to AN7 are shared with the input only port so they can be used as input port Note When IDLE2 IDLE1 or STOP mode is selected as to reduce the power with some timings the system may enter a standby mode even though the internal comparator is still enabled Therefore be sure to check that AD converter operations are halted before a HALT instruction is executed Internal data bus Inter
102. OUT1 PDFC lt PD3F gt PDCR lt PD3C gt PDFC 0037H Note 1 Read modify write instruction is prohibited for the registers PDFC and PDCR Note 2 Can not read the output latch data when PDO and PD1 are output mode Figure 3 5 24 Register for Port D 92CM22 72 2007 02 16 TOSHIBA TMP92CM22 3 5 11 Port to PF7 Port F is 8 bit general purpose I O port Each bit can be set individually for input or output Resetting resets the PFCR and PFFC to 0 and sets all bits to input port And all bits of output latch register to 1 In addition to functioning as a general purpose I O port port F can also function as I O function of serial channel 0 and 1 These settings operate by writing 1 to the corresponding bit of PFFC Resetting resets the PDCR and PDFC to 0 and sets all bits to input port 1 Port and PF3 TXDO TXD1 In addition to function as I O port port PFO and can also function as TXD output pin of serial channel Thus output buffer feature a programmable open drain function and setting enable by PFFC PFOF gt and PFCR lt PFOC PF3C register Reset Direction control on bit basis E Function control on bit basis S Output latch TXDO TXD1 PF write Internal data bus PFO 0 TXD1 Selector Open drain enable lt PFOF 1 0 PF3F 1 PF3C 0 gt S
103. Overrun error lt OERR gt If all the bits of the next data item have been received in receiving buffer 1 while valid data still remains stored in receiving buffer 2 SCOBUF an overrun error is generated The below is a recommended flow when the overrun error is generated INTRX interrupt routine 1 Read receiving buffer 2 Read error flag 3 if lt OERR gt 1 then 4 Set to disable receiving Program 0 to SCOMODO lt RXE gt 5 Wait to terminate current frame 6 Read receiving buffer 7 Read error flag 8 Set to enable receiving Program 1 to SCOMODO RXE 9 Request to transmit again 10 Other 92 22 152 2007 02 16 TOSHIBA TMP92CM22 2 Parity error lt gt The parity generated for the data shifted into receiving buffer 2 SCOBUF is compared with the parity bit received via the RXD pin If they are not equal a parity error is generated 3 Framing error lt gt The stop bit for the received data is sampled three times around the center If the majority of the samples are 0 a framing error is generated 12 Timing generation 1 In UART mode Receiving 8 Bits Parity 8 Bits 7 Bits Parity 7 Bits Interrupt generation Center of last bit Center of last bit Center of stop bit timing Bit8 Parity bit Framing error Center of stop bit Center of stop bit Center of stop bit generation timing Parity error Center of last bit ater n f 4 generation timing Pari
104. P92CM22 UART Serial channel 2 2 Se channel 1 buffer register Serial channel 1 control register Serial SC1MODO channel 1 mode 0 register Serial channel 1 BR1CR baud rate control register Serial BRIADD 1 setting register Serial SC1MOD1 channel 1 mode 1 register uw Receiving yw Undefined RBs EVEN PE OERR PERR FERR SCLKS ioc a RW RW 3 Undefined Receive 0 0 Disable Overrun Parity Framing rate i 2 1 Enable generator 1 SCLK1 TB8 RXE SM1 SMO SC1 SCO Transmis 0 i 00 I O interface 00 Timer TAOREG sion data 0 Disable 01 7 bit UART mode 01 Baud rate bits 1 Enable 10 8 bit UART mode generator 11 9 bit UART mode 10 Internal clock fio enable 11 External clock SCLK1 input Sets frequency divisor K divided by N 16 K 16 1 Operate 0 Half duplex 1 Full duplex 92CM22 245 2007 02 16 TOSHIBA 9 bus Serial channel 1 2 TMP92CM22 7 Te 1240H Prohibit RMW Number of transfer bits mode 000 8 001 1 010 2 011 3 SBIO 100 4 101 5 110 6 control register 1 SBIOCR1 sce eco ack W sce soki 111 7 0 Disable 1 Enable
105. PWM Pulse width modulation output mode 5 Mode settings Table 3 7 1 Registers and Pins for Each Module iris Timer 01 Timer A23 Specification TAOIN Input pin for external clock Shared with PCO External pin Output pin for timer TA1OUT TASOUT flip flop Shared with PC1 Shared with PC5 TAOREG 1102H TA2REG 110AH ET 1103H TA3REG 110BH Timer flip flop control register 1105H 110DH 92CM22 99 2007 02 16 TMP92CM22 TOSHIBA Block Diagrams 3 7 1 1NOLYL LVLLNI 9ul0vl OV LLNI JejsiDoJ 10 9 140 16 8 Lon Jejunoo dn 119 8 lt 1 lt 3040 1 gt 0 NNY O3Hu0vL JeisiDoJ 16 8 049 16 8 yore lt 00 LOWMd gt GOW LOV L lt 0 14120 1 gt lt 0 LMTIOLVL gt GOWLOVL GQONLOV L uc Jejunoo dn 8 NIOV L 210019 indui 1 Jopejes lt NNYOVL gt NNY LOVL Jopejes 9110 1 lt 0 1 gt 01 1219 vo ee 94 8 v 2 Je eosaJg TMRAO 1 Block Diagr
106. REG each time TAIREG matches UCO Use of the double buffer facilitates the handling of low duty waves when duty is varied Match with TAOREG ee DE and U CO Up counter Up counter Q2 Match withTA1REG Shift into register buffer TAOREG Value of compare Register buffer Write TAOREG Register buffer Figure 3 7 15 Operation of Register Buffer 92CM22 115 2007 02 16 TOSHIBA TAO1RUN 01 TAOREG TA1REG TA1FFCR TMP92CM22 Example To generate 1 4 duty 62 5 kHz pulses at fc 40 MHz 166 Calculate the value that should be in the timer register To obtain a frequency of 62 5 kHz the pulse cycle t should be t 1 62 5 kHz 16 us 16 fc s at fc 40MHz 16 us 16 fc s 40 Therefore set TA1REG to 40 28H The duty is to be set to 1 4 t x 1 4 2 16 us x 1 4 2 4 us 4 us 16 fc s 10 Therefore set TAOREG 10 0AH 76 5 4 8 2 0 X X X 0 0 0 Stop TMRAO and and clear it to 0 1 0 X X X X 0 1 Set the 8 bit PPG mode and select 1 as input clock 0 0001 0 1 O0 Write OAH 0 0 1 01 00 0 Write 28H lt X X X X0 1 1 X Set TA1FF and set inversion to enable Writing 10 provides negative logic pulse lt X X X 1 ex X PM Set PC1 to TA1OUT pin TAO1RUN X X X 1 1 1 Start TMRAO and counting X Don tcare change 92CM22 116 2007 02 16 TOSHIBA TMP92CM2
107. RX gt Accessed to SBIODBR or SBIOCR2 Figure 3 10 12 Example of when TMP92CM22 is a Master Device D7A D7B D6A D6B 11 Slave address match detection monitor SBIOSR lt AAS gt operates following in during slave mode In address recognition mode e g when I2COAR ALS 0 when received GENERAL CALL or same slave address with value set to I2COAR SBIOSR lt AAS gt is set to 1 When ALS 1 SBIOSR lt AAS gt is set to 1 after the first word of data has been received SBIOSR lt AAS gt is cleared to 0 when data is written to SBIODBR or read from SBIODBR 12 GENERAL CALL detection monitor SBIOSR lt ADO gt operates following in during slave mode when received GENERAL CALL all 8 bit data is 0 after start condition SBIOSR lt ADO gt is set to 1 And SBIOSR ADO is cleared to 0 when a start condition or stop condition on the bus is detected 13 Last received bit monitor The value on the SDA line detected on the rising edge of the SCL line is stored in the SBIOSR lt LRB gt In the acknowledge mode immediately after an INTSBEO interrupt request has been generated an acknowledge signal is read by reading the contents of the SBIOSR lt LRB gt 92CM22 182 2007 02 16 TOSHIBA TMP92CM22 14 Software reset function The software reset function is used to initialize the SBI circuit when SBI is rocked by external noises etc When write first 10 next 01
108. Rising 0 Rising 0 Falling control high high high high 1 Falling 1 Falling 1 Falling 1 Falling 1 Falling INTWD INTWDT enable of INTCLR clear Prohibit ee control RMW Dr interrupt vector nterrupt ree c s n _ 2 input Prohibit pee poems 0 o0 0 Mn mode RMW INT2 INT1 control 0 Edge 0 Edge 0 Edge 1 Level 1 Level 1 Level 92CM22 236 2007 02 16 TOSHIBA 3 Em Name adress 7 6 5 4 3 2 1 j DMAOVS DMAOV4 DMAOV2 DMAOV1 DMAOVO 1 o0 o0 0 o0 o0 0 I start vector omava start vector DMA1 start vector pz m 6 start vector T o 7 DMA2Vs DMA2V4 DMA2V3 DMA2V2 DMA2V1 DMA2VO e es RW n m o o0 o o0 o0 o start vector DMA2 start vector Pate te s R W 0103H DMA3 start vector Paes ea oe p Te DMAG start vector DOT 0104H 4 start vector e 4 start vector 7 5 DMASV4 DMASV3 DMASV2 DMASVO
109. SCOBUF Serial channel 0 control register Serial channel 0 mode 0 register Serial channel 0 BROCR baud rate control register Serial BROADD Ehannel 0 K setting register Serial SCOMOD1 channel 0 mode 1 register IrDA SIRCR control register HU R Receiving W Transmission Undefined R R Claroaferreadng RW Undefined 0 0 0 0 0 Receive Parity Party 1 O SCLKOT 0 Baud t data 0 Odd 0 Disable Overrun Parity Framing 1 SCLKO E 1 Enable 1 SCLKO pin input Transmis 0 00 1 O interface mode 00 Timer TAOREG sion data 01 7 bit UART mode 01 Baud rate bit8 i 10 8 bit UART mode generator 1 CTS 1 Receive 1 Enable 11 9 UART mode 10 Internal clock fio 11 External clock SCLKO input _ Bross BROS BROS Broso R W RB7 RB6 RBS RB4 RB3 RB2 RBI RBO 1200H TB7 TB6 TB5 TB4 TB3 TB2 TBI TBO Sets frequency divisor K divided by N 16 K 16 00 D Select Receive Transmit Select receive pulse width transmit data 0 Disable 0 Disable Set effective pulse width for equal or more pulse 0 H pulse 1 Enable 1 Enable than 2x x Value 1 100 ns width 1 L pulse Can be set 1 to 14 0 3 16 1 116 0 15 92CM22 244 2007 02 16 TOSHIBA TM
110. SCRO clock control 0 Always ite 1 write 0 2 GEAR _ Select gear value of high frequency write 0 fc System 000 fc SYSCR1 clock 001 2 control 1 010 fc 4 011 fc 8 100 fc 16 101 Reserved 110 Reserved 111 Reserved cen stis ome p mw inesse 27 0r e s rw p qw ege Warm up timer HALT mode DRVE state System 00 Reserved 00 Reserved mode control in SYSCR2 clock 01 28 frequency 01 STOP mode select STOP control 2 10 2 input frequency 10 IDLE1 mode 0 STOP a ge 11 2 input frequency 11 IDLE2 mode 1 IDLE1 1 Remains peel pee 00 before repo d eu 1 External fc oscillator w Ss ae 0 PLL off fc select PLL 1 PLL 0 OSCH warm up 1 PLL x4 flag 0 Don t end warm up 1 End warm up Se poe EMC o EMCCRO control Protect register 0 flag 0 OFF 1 clock driver ability 1 NORMAL 0 WEAK M W EMC EMORI Switching the protect ON OFF by write to following 1st KEY 2nd KEY 1st KEY EMCCR1 2 in succession write EMC 2nd KEY EMCCR1 EMCCR2 in succession write EMCCR2 control 10E5H 92CM22 240 2007 02 16 TOSHIBA TMP92CM22 6
111. SR register Note 2 Switch a mode to port mode after confirming that the bus is free Switch a mode between bus mode and clocked synchronous 8 bit SIO mode after confirming that input signals via port are high level Figure 3 10 4 Register for Bus Mode 92CM22 175 2007 02 16 TOSHIBA TMP92CM22 Serial Bus Interface Status Register eed gos S iosR UM v 0 0 0 Read Function Master Transmitter bus INTSBEO Arbitration Slave address GENERAL Last modify write slave receiver status interrupt lost match CALL received bit instruction is status status monitor request detection detection detection monitor prohibited selection selection monitor i monitor monitor 0 0 monitor monitor 0 Undetected 0 Undetected 1 1 1 Detected 1 Detected 1 Detected Last received bit monitor Last received bit was 0 1 Last received bit was 1 GENERAL CALL detection monitor Undetected GENERAL CALL detected 1 Slave address match detection monitor Undetected Slave address match or GENERAL CALL detected Arbitration lost detection monitor 1 Arbitration lost INTSBEO interrupt request monitor Interrupt requested Interrupt released bus status monitor Free Transmitter receiver status monitor Receiver Transmitter Master slave status monito
112. ST 1 clear micro DMA start vector Interrupt vector V read Interrupt request F F clear Micro DMA processing PC FFFFOOH V Interrupt process program RETI instruction POP SR POP PC INTNEST lt INTNEST 1 Figure 3 4 1 Interrupt and Micro DMA Processing Sequence 92CM22 30 2007 02 16 TOSHIBA 3 4 1 TMP92CM22 General purpose Interrupt Processing When the CPU accepts an interrupt it usually performs the following sequence of operations That is also the same as TLCS 900 L TLCS 900 H and TLCS 900 L1 1 The CPU reads the interrupt vector from the interrupt controller If the same level interrupts occur simultaneously the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt request The default priority is already fixed for each interrupt The smaller vector value has the higher priority level 2 The CPU pushes the value of program counter PC and status register SR onto the stack area indicated by XSP 3 The CPU sets the value which is the priority level of the accepted interrupt plus 1 G 1 to the interrupt mask register lt IFF2 0 gt However if the priority level of the accepted interrupt is 7 the register s value is set to 7 4 The CPU increases the interrupt nesting counter INTNEST by 1 1 5 The CPU jumps to the address indicated by the data at address Interrupt vector and s
113. TOSHIBA TOSHIBA Original CMOS 32 Bit Microcontroller TLCS 900 H1 Series TMP92CM22FG TOSHIBA CORPORATION Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs Before use this LSI refer the section Points of Note and Restrictions TOSHIBA TMP92CM22 CMOS 32 Bit Microcontrollers TMP92CM22FG 1 Outline and Device Characteristics 92 22 is high speed advanced 32 bit microcontroller developed for controlling equipment which processes mass data TMP92CM22FG is a microcontroller which has a high performance CPU 900 H1 CPU and various built in I Os TMP92CM22F is housed in a 100 pin flat package Device characteristics are as follows 1 CPU 32 bit CPU 900 H1 CPU Compatible with TLCS 900 900 L 900 L1 900 H and 900 H2 s instruction code 16 Mbytes of linear address space e General purpose register and register banks e Micro 8 channels 250 ns 4 bytes at fsys 20 MHz best case 2 Minimum instruction execution time 50 ns at fsys 20 MHz 3 Internal memory e Internal RAM 32 Kbytes 32 bit 1 clock access programmable Internal ROM None RESTRICTIONS ON PRODUCT USE 070208EBP e The information contained herein is subject to change without notice 021023 D TOSHIBA is continually working to improve the quality and reliability of its products Nevertheless semiconductor devices in general can malfunction or fail due to their inh
114. TRX gt to 1 for operating the TMP92CM22 as a transmitter Clear the lt TRX gt to 0 for operation as a receiver In slave mode when transfer data in addressing format when received slave address is same value with setting value to I2COAR or GENERAL CALL is received All 8 bit data are 0 after start condition the lt TRX gt is set to 1 by the hardware if the direction bit R W sent from the master device is 1 and lt TRX gt is cleared to 0 by the hardware if the bit is 0 In the master mode after an acknowledge signal is returned from the slave device the lt TRX gt is cleared to 0 by the hardware if a transmitted direction bit is 1 and is set to 1 by the hardware if it is 0 When an acknowledge signal is not returned the current condition 1s maintained The lt TRX gt is cleared to 0 by the hardware after a stop condition on the bus is detected or arbitration is lost 7 Start stop condition generation When programmed 1111 to SBIOCR2 MST BB PIN in during SBIOSR BB 1 0 slave address and direction bit which are set to SBIODBR and start condition are output on a bus it is necessary to set transmitted data to the data buffer register SBIODBR and set 1 to lt gt beforehand 1 SCLline 1 1 2 3 4 5 6 7 8 9 1 1 INE SDAine A6 X A5 X s X A X o X RW 1 zm moms Start condition Ep Slave
115. The outputting for the first SCLKO starts by setting SCOMOD0 lt RXE gt to 1 IRXOC INTRXO interrupt request SCLKO output lt SCLKS gt 0 f rising mode i SCLKO output RN pd qe qeu lt SCLKS gt 1 falling mode i Cas OC Figure 3 9 21 Receiving Operation in Interface Mode output mode In SCLK input mode the data is shifted to receiving buffer 1 when the SCLK input becomes active after the receive interrupt flag INTESO lt IRXOC gt is cleared by reading the received data When 8 bit data is received the data will be shifted to receiving buffer 2 SCOBUF according to the timing shown below and 50 lt gt will be set again to be generate INTRXO interrupt SCLKO input SCLKS 0 7 rising mode SCLKO input 0 c lt SCLKS gt 1 falling mode RXD1 LL X X Bib X X ___ IRXOC i INTRXO interrupt request Figure 3 9 22 Receiving Operation in Interface Mode input mode Note If receiving set to the receive enable state SCOMODO RXE 1 in both SCLK input mode and output mode 92CM22 163 2007 02 16 TOSHIBA TMP92CM22 3 Transmission and receiving Full duplex mode When the full duplex mode is used set the level of receive interrupt to 0 and set enable the interrupt level 1 to 6 to the tr
116. a S O P5 1 10 Fee B O per7 J e 4qd 3 PotG Peo 1 PG 11 ipt Pe 1 1 ipt Fxd 2 11 ipt Fxed ADTRG 1 nw 1 11 ipt Fxd 5 Pes 11 ipt 6 Pez i nw Fea When these ports are used as general purpose I O port bit can be set individually for input or output However each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port All of general purpose ports except for port that used as address bus are operated as output port Please be careful when using this setting 92CM22 49 2007 02 16 TOSHIBA TMP92CM22 Table 3 5 2 Port Setting List 1 2 T Register Setting Value Ports Input Pins Specification PnODE Port 1 P10 to P17 Input port Output port None P40 to P47 Input port x 0 1 Output por AO to A7 output x x Port 5 P50 to P57 Input port Output port to A15 output 0 6 P60 to P67 Input port x A16 to A23 output o c 2 5 Input port Output port WAIT Input P90 to P92 Input port Output port SCK input SCK output Port 8 P80 to P83 Output port CS0 output P82 CS
117. ad as 11 Timer flip flop TBOFFO control Invert Set to 1 Set to 0 Don t care 10 1 Inverted when the UC10 value matches the value in TBORGOH L Disable inversion 1 Enable inversion Inverted when the UC10 value matches the value in TBORG1H L Disable inversion 1 Inverted when the UC10 value is loaded into TBOCPOH L Disable inversion Enable inversion 1 Inverted when the UC10 value is loaded into TBOCP1H L Enable inversion Disable inversion 1 Enable inversion Figure 3 8 6 Register for TMRB 92CM22 130 2007 02 16 TOSHIBA TMP92CM22 TMRB 1 Flip flop Control Register 7 9 4 s 32 4 TBIFFCR 99M w ____ DN UPS D P E Read modity Function TB1FF1 control TB1FFO inversion trigger TB1FFO control write 00 Invert 0 Trigger disable 00 Invert instruction is 01 Set 1 Trigger enable 01 Set prohibited 10 Clear Invert when Invert when Invertwhen Invertwhen 10 Clear 11 Don t care the UC12 the UC12 the UC12 the UC12 11 Don t care value is value is matches with match with loaded into loaded into TB1RGOH L TB1CP1H L TB1CPOH L Always read as 11 Always read as 11 Timer flip flop TB1 TB1FFO control Inverted when the UC12 value matches value in TB1RGOH L Disable inversion Enable inv
118. am Figure 3 7 1 2007 02 16 92CM22 100 TMP92CM22 TOSHIBA L EVLLNI Oulevl eV LLNI n d no VHINL sng 1 5 Jow 119 8 649 19481691 16 8 yore snq lt 1 gt 1915 JejsiDoJ 10 8 289 19 8 lt 0 1 2 gt QONNE2V L lt 0 14126 1 gt lt 0 DX TOEV L QOINE V L Jejunoo 6 8 9393581 1012995 lt gt 1 zon Jejunoo dn 19 8 1 1010925 lt 1 gt 91 vio lt 1 gt 01 0010 yeajo uny cis ese ge vo ze 91 Figure 3 7 2 TMRA23 Block Diagram 2007 02 16 92CM22 101 TOSHIBA TMP92CM22 3 7 2 Operation of Each Circuit 1 Prescaler A 9 bit prescaler generates the input clock to TMRAOI The prescaler s operation can be controlled using TAOIRUN TAOPRUN in the timer control register Setting lt TAOPRUN gt to 1 starts the count setting lt gt to 0 clears prescaler to 0 and stops operation Table 3 7 2 shows the various prescaler output clock resolutions Tab
119. annel Timing interface mode Note Symbol X in the following table means the period of clock fsys it s same period of the system clock for CPU core The period of fsys depends on the clock gear setting or changing high speed oscillator low speed oscillator and so on 1 SCLK input mode fsys fsys Variable 20 MHz 125 kHz Parameter Symbol fc 40 MHz fc 4 MHz cuc EI SCLK period tscy Output data gt SCLK rising falling tscv 2 4X 110 9 31890 Lo _ Valid data input gt rising falling SCLK rinsing falling edge The rising edge is used in SCLK rising mode The falling edge is used in SCLK falling mode Note Value of fsys 20 MHz 125 kHz is value if tscy 16X 2 SCLK output mode fsys fsvs Variable 20 MHz 125 kHz Parameter Symbol fc 40 MHz fc 4 MHz pao Pen fo SCLK SCLK tscy 1X rising falling Valid data input CNN er 80 409 4 65528 Valid data input rising falling 1X 180 8180 92 22 224 2007 02 16 TMP92CM22 TOSHIBA tscy SCLK j Output mode input rising mode SCLK Input falling mode Output data TXD Input data RXD 4 6 Interrupt Capture Symbol X in the following table means the period of clock it s same period of the system Note clock for CPU
120. ansfer interrupts In the transfer interrupt program the receiving operation should be done like the below example before setting the next transfer data Example Channel 0 SCLK output Baud rate 9600 bps fc 4 9152 MHz Main routine 765432 1 INTESO 0001000 PFCR 10 1 SCOMODO 0000000 SCOMOD1 1100000 SCOCR 0000000 BROCR 0001100 SCOMODO 0010000 SCOBUF dos ches Cab ck Transmission interrupt routine Acc SCOBUF SCOBUF X Don t care No change Clock state Clock gear 1 1 Set transmission interrupt level to 1 and disable receiving interrupt level to 0 Set to PFO TXDO PF1 RXDO and SCLKO Set to interface mode Set to full duplex mode Output SCLK select rising edge Set to 9600 bps Set receive to enable Set transmission data Read receiving data Set transmission data 92 22 164 2007 02 16 TOSHIBA TMP92CM22 2 Mode 1 7 bit UART mode 7 bit UART mode is selected by setting serial channel mode register SCOMODO SM 1 0 to 01 In this mode a parity bit can be added Use of a parity bit 18 enabled or disabled by the setting of the serial channel control register SCOCR lt PE gt bit whether even parity or odd parity will be used is determined by the SCOCR EVEN setting when SCOCR lt PE gt is set to 1 Enabled Example When transmitting data of the following format the control registers should
121. ared to 0 Zx pre pm ers pre en 1 P70 Data from external port Output latch register is cleared 0 92 91 R W Data from external port Output latch register is set to 1 PA2 PA1 Ue 79 N VW Data from external port Data from external port o a v Q ie Data from external port Data from external Output latch port Output latch register is register is set to 1 set to 1 Data from external port Output latch register is set to 1 PD2 PD1 im Data from external port Output latch register is set to 1 an CONNU LUE NU EE CER ERR R W Data from external port Output latch register is set to 1 Data from external port V 92CM22 232 2007 02 16 TOSHIBA TMP92CM22 I O port 2 3 Symbol Name Ades 7 9 8 4 SEE DN P1CR control Prohibit register oo o 0 Input 1 Output EOD Port 1 function Prohibit ELI register RMW 1 Data bus D8 to 015 ue Ww PACR ntrol ibi Vh A A T 0 Input 1 Output pm Ww P4FC function Prohibit register RMW 0 Port 1 Address bus A0 to A7
122. be set as described below This explanation applies to channel 0 Star Bto X 1 X 2 X 3 X 5 Xm Stop Transfer direction Transfer speed 2400 bps at fc 39 3216 MHz Clock state Clock gear 1 1 fc 76543210 PFCR lt 1 1 Set PFO to as TXDO pin SCOMOD X0 10 1 Set to 7 bit UART mode SCOCR lt X11 XXX00 Add even parity BROCR 00101000 Set to 2400 bps INTESO 1100 INTTXO interrupt to enable to level 4 SCOBUF lt Set transmission data X Don t care No change 3 Mode 2 8 bit UART mode 8 bit UART mode is selected by setting SCOMODO SM1 0 to 10 In this mode a parity bit can be added Use of a parity bit is enabled or disabled by the setting of SCOCR lt PE gt whether even parity odd parity will be used is determined by the SCOCR lt EVEN gt setting when SCOCR lt PE gt is set to 1 Enabled Example When receiving data of the following format the control registers should be set as described below lt Transfer direction Transfer speed 9600 bps at fc 39 3216 MHz Clock state Clock gear 1 1 fc Main routine 76543210 PFCR 0 Set PF1 RXDO to input pin SCOMOD 0 1 X10 0 1 Set to 8 bit UART mode set receives to enable SCOCR X01 XXX00 Add odd parity BROCR 000110 0 0 Set to 9600 bps INTESO 1100 INTTXO interrupt to enable to level 4 Interrupt routine
123. bus interface SBI in the I2C bus mode Serial Bus Interface Control Register 1 NUMEN SBIOCR1 SCKO we Aerest m mos Read Function Select number of transferred bits Acknowledge Internal serial clock selection and modify write Note 1 mode software reset monitor instruction is parois Note 2 prohibited generate 1 Generate Internal serial clock selection lt SCK2 0 gt at write 000 n 5 Note4 001 n 6 kHz Note4 010 n 7 kHz Note4 System clock fsys 011 8 75 8 2 fsys 20 MHz output to 100 n 9 38 5 kHz SCL pin SYS 101 n 10 19 4 kHz Frequency Hz 110 n 1 9 73 kHz 252 111 Reserved Reserved Software reset state monitor lt SWRMON gt at read During software reset 1 Initial data Acknowledge mode selection Not generate clock pulse for acknowledge signal Generate clock for acknowledge signal Select number of bits transferred lt 2 0 gt Number of Data length Number of Data length clock pulses 8 8 1 1 2 2 3 3 4 4 5 5 6 6 7 7 Note 1 the lt 2 0 gt to 000 before switching to a clocked synchronous 8 bit SIO mode Note 2 For the frequency of the SCL line clock see section 3 10 5 3 Serial clock Note 3 Initial data of SCKO is 0 SWRMON is 1 Note 4 This bus c
124. c wait function will be initiated if new data is not loaded to the data buffer register after the specified 8 bit data is transmitted When new transmission data is written the automatic wait function 1s canceled When the external clock is used data should be written to the SBIODBR before new data is shifted The transfer speed 1s determined by the maximum delay time between the time when an interrupt request 13 generated and the time when data 1s written to the SBIODBR by the interrupt service program When the transmit is started after the SBIOSR lt SIOF gt goes 1 output from the SO pin holds final bit of the last data until falling edge of the SCK For stopping data transmission when the lt SIOS gt is cleared to 0 by the INTSBEO interrupt service program or when the SIOINH is set to 1 When the lt SIOS gt is cleared to 0 the transmitted mode ends when all data is output In order to confirm whether data is being transmitted properly by the program the lt SIOF gt to be sensed The SBIOSR SIOF is cleared to 0 when transmission has been completed When the SIOINH is set to 1 transmitting datat stops The lt SIOF gt turns 0 When the external clock is used it is also necessary to clear lt SIOS gt to 0 before new data is shifted otherwise dummy data is transmitted and operation ends 92CM22 194 2007 02 16 TOSHIBA TMP92CM22 Clear lt SIOS gt i ci l
125. careful when using this setting Figure 3 5 4 Register for Port 4 92CM22 55 2007 02 16 TOSHIBA 3 5 3 Port 5 P50 to P57 TMP92CM22 Port 5 is an 8 bit general purpose I O Bits can be individually set as either inputs or outputs by control register and function register P5FC In addition to functioning as a general purpose I O port port 5 can also function as an address bus A8 to A15 After released reset device set port 5 to pins of follow function by combination of AMI and AMO pins Function Setting after Reset Dontuse this setting Address bus A8 to A15 Address bus to A15 Don t use this setting Reset Direction control i on bit basis E Function control on bit basis Output latch lt E LI Internal address bu A8 to A15 5 Selector gt A Output buffer Internal data bus Port 5 P50 to P57 A8 to A15 When these ports are used as general purpose port each bit be set individually for input or output However each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port All of general purpose I O ports except for port that used as address bus are operated as output port Please be careful when using this setting Figure 3 5 5 Port 5 92CM22 56 2007 02 16 TOSHIBA TMP92CM22 Port
126. core The period of fsys depends on the clock gear setting or changing high speed oscillator low speed oscillator and so on 1 and INTO to INT3 interrupts fsys fsys Variable 20 MHz 125 kHz Symbol fc 40 MHz fc 4 MHz Unit Tem 240 sao 20 2 INT4 to INT5 interrupts NTBL tINTBH INT4 to INT5 Low Level Pulse Width INT4 to INT5 High Level Pulse Width 20 MHz 20 MHz Unit ee 40 MHz 31858 40 MHz 2007 02 16 92CM22 225 TOSHIBA TMP92CM22 4 7 Recommended Oscillation Circuit 92 22 is evaluated by below oscillator vender When selecting external parts make use of this information Note 1 Total loads value of oscillation is sum of external or internal loads C1 and C2 and floating loads of actual assemble board There is a possibility of miss operating using C1 and C2 values in below table When designing board it should design minimum length pattern around oscillator And we recommend that oscillator evaluation try on your actual using board Note 2 When use function of reduced drivability for high frequency oscillator must be used at foscH 4 to 10 MHz 1 Example of oscillation connection circuit X1 X2 Rd pen Figure 4 7 1 High frequency Oscillator 92CM22 226 2007 02 16 TOSHIBA TMP92CM22 2 TMP92CM22 recommended ceramic
127. ction e Mode 1 7 bit UART mode No parity Parity statXBiioX 1X 2 5 6 Mode 2 8 bit UART mode No parity Nsan BOX 1X 2X 3X 4 5X 6X7 2 3 4 5 Parity sin Si 1 2 7 Vary Stop Mode 3 9 51 UART mode 1X 2X 3X 4X5 X 6X7 Wakeup StatXBitoX 1 X 2 X 4X 5X5 X7 If bit8 1 denoted address Select code If bit8 0 denoted data Figure 3 9 1 Data Format 92 22 142 2007 02 16 TOSHIBA 3 9 1 Block Diagram Prescaler 214 163264 T2 8 9132 Serial clock generation circuit BROCR lt BROCK1 0 gt 5 5 o 9 8 a a BROCR lt BROADDE gt Baud rate generater fio SCLKO input Shared with PF2 SCLKO output interface mode Shared with PF2 RXDO Shared with PF1 TAOTRG from TMRAO Selector SCOMODO lt SC1 0 gt Selector Serial channel interrupt control SCOCR lt OERR gt lt PERR gt lt FERR gt Internal data bus TMP92CM22 SIOCLK Selector SCOMODO lt SM1 0 gt I O interface mode Interrupt INTRXO INTTXO Transmission counter UART only 16 Transsmission control CTSO Shared with PF2 SCOMODO lt CTSE gt TXDO Shared with PFO Figure 3 9 2 Block Diagram of 100 92CM22 143 2007 02 16 TOSHIBA TMP92CM22 Prescaler 0 214 1632164 12 T8 9132 Serial clock generation cir
128. cuit BR1CR lt BR1CK1 0 gt BR1CR BRTADD TAOTRG lt 153 0 gt lt BR1K3 0 gt from TMRAO 5 5 5 5 2 9 SIOCLK o Ko 5 o o Se lt BR1ADDE gt fi Baud rate generater lt 5 1 0 gt SC1MODO lt SM1 0 gt 5 SCLK1 input amp VO interface mode Shared with PF5 SCLK1 output m interface mode Interrupt request Shared INTRX1 with PF5 INTTX4 Receive control Transmission Serial channel counter UART only 16 interrupt control UART only 16 Transmission 2 control CTS1 Shared with PF5 SC1MODO lt CTSE gt RXD1 L Shared with TXD1 Shared SC1CR with PF3 lt OERR gt lt gt lt gt Figure 3 9 3 Block Diagram of 5101 92CM22 144 2007 02 16 TOSHIBA TMP92CM22 3 9 2 Operation of Each Circuit 1 Prescaler There is a 6 bit prescaler for generating a clock to SIOO The clock selected using SYSCR1 lt GEAR2 0 gt is divided by 8 and input to the prescaler as The prescaler can be run only case of selecting the baud rate generator as the serial transfer clock Table 3 9 2 shows prescaler clock resolution into the baud rate generator Table 3 9 2 Prescaler Clock Resolution to Baud Rate Generator Clock Gear Clock Resolution SYSCR1 BROCR lt BROCK1 0 gt GEAR2 0 4 The serial interface baud rate generator selects between 4 clock inputs 2 oT8 and 82 among the prescaler outputs 92CM
129. d Halt Release Operation Interrupt Enable Interrupt Disable Status of Received Interrupt p Interrupt level gt Interrupt mask Interrupt level Interrupt mask HALT Mode IDLE1 STOP IDLE1 STOP INTWDT INTO to 3 Note1 INT4 to 5 INTTAO to 3 INTTBOO 01 10 11 OO O1 INTRXO to 1 TXO to 1 INTAD INTSBEO Initialize LSI Interrupt X X X X X X 9 9 D lt 5 8 8 After release the HALT mode CPU starts interrupt processing After release the HALT mode CPU resumes executing starting from instruction following the HALT instruction Interrupt don t process It can not be used to release the HALT mode The priority level Interrupt request level of non maskable interrupts is fixed to 7 the highest priority level There is not this combination type v Release the HALT mode is executed after passing the warm up time Note 1 When the HALT mode is released by INTO to INT3 interrupts of the level mode in the interrupt enabled status hold this level until starting interrupt processing Changing level before holding level interrupt processing is correctly started Note 2 When use external interrupt INT4 to INT5 are used during IDLE2 mode set 16 bit timer RUN register TB1 RUN lt I2TB1 gt to 1 Example release HALT mode An INTO interrupt release the halt state when the device is in IDLE1 mode Address 8203H LD 00H Selects
130. d by the port output 1 or 0 by it Internal External Internal External Functional change Although an object terminal is changed from a port to a chip select signal output by setting up a function control register PnFC register the short pulse for several ns may be outputted to the changing timing Although it does not become especially a problem when using the usual memory it may become a problem when using a special memory XX is a function register address When an output port is initialized by 0 A port is set as Internal address bus Function control signal Pxx o A23 to Output pulse tAD3 The measure by software The countermeasures in S W for avoiding this phenomenon are explained Since CS signal decodes the address of the access area and is generated an unnecessary pulse is outputted by access to the object CS area immediately after setting it as a CSn function Then if internal area 15 accessed also immediately after setting a port as CS function an unnecessary pulse will not output 1 Prohibition of use of an NMI function 2 The banon interruption under functional change DI command 3 Adummy command is added in order to carry out continuous internal access 4 Access to a functional change register is corresponded by 16 bit command LDW command A port is set aSCSn Dummy access Internal address bus __ XX 2 n
131. d mode 6 states 4 waits access fixed mode __ 1 OOO i Waits number fixed mode The bus cycle is completed with the set states The number of states 13 selected from 2 states 0 waits to 6 states 4 waits i WAIT pin input mode This mode samples the WAIT input pins It continuously samples the WAIT pin state and inserts a wait if the pin is active The bus cycle is minimum 2 states The bus cycle is completed when wait signal is non active High level at 2 states The bus cycle extends if the wait signal is active at 2 states and more If a lot of connected pertain ROM and etc Much data output floating time tDF each other s data bus output recovery time is trouble However by setting BnREC of control register BnCSH can to insert dummy cycle of 1 state just before first bus cycle of starting access another block address BnREC Bit BnCSH register No dummy cycle is inserted Default Dummy cycle is inserted 92CM22 84 2007 02 16 TOSHIBA e When not inserting a dummy 0 waits mf ff When inserting a dummy cycle 0 waits Dummy CLKOUT eo J se 92 22 85 TMP92CM22 2007 02 16 TMP92CM22 TOSHIBA b Bus access timing External read write bus cycle 0 waits CLKOUT 20 MHz gt 5 o Address External read write bus cycle 1 wait CLKOUT 20 MHz 5 a em
132. d the SCL pin is pulled down to the low level Either reading writing from to the SBIODBR or setting the PIN to 1 will release the SCL pin after taking time Check the SBIOSR AL TRX lt AAS gt and lt ADO gt and implements processes according to conditions listed in the next table Table 3 10 1 in the Slave Mode The TMP92CM22 detects arbitration lost Set the number of bits of single word to when transmitting a slave address and lt 2 0 gt and write the transmit data to receives a slave address for which the SBIODBR value of the direction bit sent from another master is 1 In salve receiver mode the TMP92CM22 receives a slave address for which the value of the direction bit sent from the master is 1 In salve transmitter mode transmission Check the LRB If LRB is set to 1 data of single word is terminated Set PIN to 1 reset 0 to lt gt and release the bus for the receiver no request next data If LRB was cleared to 0 set bit number of single word to lt BC2 0 gt and write the transmit data to SBIODBR for the receiver requests next data The TMP92CM22 detects arbitration lost Read the SBIODBR for setting the PIN when transmitting a slave address and to 1 Reading dummy data or set the receives a slave address or GENERAL PIN to 1 CALL for which the value of the direction bit sent from another maste
133. disabled when lt TBORDE gt 0 and enabled when lt TBORDE gt 1 When the double buffer 18 enabled data 1s transferred from the register buffer to the timer register when the values in the up counter UC10 and the timer register TBORG1H L match After a reset TBORGOH L and TBORG1H L are undefined If the 16 bit timer is to be used after a reset data should be written to 16 beforehand On a reset lt gt is initialized to 0 disabling the double buffer To use the double buffer write data to the timer register set lt TBORDE gt to 1 then write data to the register buffer as shown below TBORGOH L and the register buffer both have the same memory addresses 001188H and 001189H allocated to them If lt gt 0 the value is written to both the timer register and the register buffer If lt gt 1 the value 18 written to the register buffer only The addresses of the timer registers are as follows TMRBO 1 TBORGOH L TBORG1H L Upper 8 bits Lower 8 bits Upper 8 bits Lower 8 bits i 1189H 1188H 118BH 118AH 1 1 O es E aa ek eh ee 1 1 TB1RGOH L TB1RG1H L Upper 8 bits Lower 8 bits Upper 8 bits Lower 8 bits 1199H 1198H 119BH 119AH 1 1 1 The timer registers are write only reg
134. e buffer is enabled Use of the double buffer facilitates the handling of low duty ratio waves Match with TAOREG Up counter Q Up counter 2 overflow Shift from TAOREG Register buffer TAOREG Value of compare Register buffer Write to TAOREG Figure 3 7 18 Operation of Register Buffer Example To output the following PWM waves on the TA1OUT pin at fc 40 MHz To achieve a 51 2 us PWM cycle by setting 1 16 at fc 40 MHz 51 2 us 16 fc s 128 2 Therefore n should be set to 7 Since the low level period is 36 0 us when 1 16 fc s set the following value for TAOREG 36 0 us 16 fc s 90 MSB LSB 7 6 54 83 2 TAO1RUN X XX 0 Stop TMRAO and clear it to 0 TAOIMOD 4 1 1 1 0 01 Select 8 bit PWM mode cycle 27 and select 1 as the input clock TAOREG 0 1 0 1 1 0 1 0 Write 5AH TA1FFCR X X X X 10 1 Clear TA1FF to 0 set inversion to enable PCCR lt X X X 1 PC1 to TA1OUT pin PCFC X Set PC1 to OUT pin TAO1RUN XXX 14 1 Start TMRAO counting Don t care No change 92CM22 118 2007 02 16 TOSHIBA TMP92CM22 Table 3 7 4 Relationship of PWM Cycle and 2 Counter PWM cycle Clockgear System clock TAxxMOD lt PWMx1 0 gt SYSCRI1 SYSCRO 2 x64 2 x128 2 x256 lt GEAR2 0 gt TAxxMOD lt TAXCLK1 0 gt TAxxMOD TAxCLK1 0 TAxxMOD TAxCLK1 0 1 2 9 4 8 eT16 x32 1 2 4 8 9 1
135. e next micro DMA operation is disabled and micro DMA processing terminates If micro requests are set simultaneously for more than one channel priority 18 not based on the interrupt priority level but on the channel number the lower the channel number the higher the priority channel 0 thus has the highest priority and channel 7 the lowest If an interrupt request is triggered for the interrupt source in use during the interval between the time at which the micro DMA start vector is cleared and the next setting general purpose interrupt processing is performed at the interrupt level set Therefore if the interrupt is only being used to initiate micro DMA and not as a general purpose interrupt the interrupt level should first be set to 0 i e interrupt requests should be disabled If micro DMA and general purpose interrupts are being used together as described above the level of the interrupt which 18 being used to initiate micro processing should first be set to a lower value than all the other interrupt levels Note In this case edge triggered interrupts are the only kinds of general interrupts which can be accepted Note If the priority level of micro DMA is set higher than that of other interrupts CPU operates as follows In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between checking Interrupt specified by micro DMA start vector in theFigure 3 4 1 and reading interrupt vecto
136. e the results of AD conversion ADREGOH L to ADREG7H L are read only registers In channel fixed repeat conversion mode the conversion results are stored successively in registers ADREGOH L to ADREGS3H L In other modes the ANO AN1 AN2 AN3 AN5 AN6 conversion results are stored in ADREGOH L ADREG1H L ADREG2H L ADREGS3H L ADREG4H L ADREG5H L ADREG6H L ADREG7HIL respectively Table 3 11 3 shows the correspondence between the analog input channels and the registers which are used to hold the results of AD conversion Table 3 11 3 Correspondence between Analog Input Channel and AD Conversion Result Register AD Conversion Result Register Analog Input Channel Fixed Repeat Channel Conversion Modes Other than at Right Conversion Mode ADMODO ITMO 1 ADREGOH L ADREG1H L ADREG2H L ADREGOH L ADREG3H L ADREG1H L ADREG4H L ADREG2H L ADREGS5H L ADREG3H L ADREG6H L ADREG7H L lt ADRxRF gt bitO of the AD conversion data lower register is used as the AD conversion data storage flag The storage flag indicates whether the AD conversion result register has been read or not When a conversion result is stored in the AD conversion result register the flag is set to 1 When either of the AD conversion result registers ADREGxH or ADREGxL is read the flag is cleared to 0 Reading the AD conversion result also clears the AD conversion end flag lt
137. east 20 system clocks 16 at fe 40 MHz When the reset has been accepted the CPU performs the following Sets the program counter PC as follows in accordance with the reset vector stored at address FFFFOOH to FFFFO2H PC lt 7 0 gt lt Data in location lt 15 8 gt lt Data in location PC lt 23 16 gt lt Data in location FFFF02H e Sets the stack pointer XSP to 00000000H e Sets bits lt IFF0 2 gt of the status register SR to 111 Thereby setting the interrupt level mask register to level 7 e Clears bits lt 1 gt of the status register to 00 Thereby selecting register bank 0 When the reset is released the CPU starts executing instructions according to the program counter settings CPU internal registers not mentioned above do not change when the reset is released When the reset is accepted the CPU sets internal I O ports and other pins as follows e Initializes the internal I O registers as Table of Special Function Registers SFRs in Section 5 Sets the input or output port to general purpose input port Internal reset is released as soon as external reset is released and RESET input pin is set to H The operation of memory controller cannot be insured until power supply becomes stable after power on reset The external RAM data provided before turning on the TMP92CM22 may be spoiled because the control signals are unstable until power supply beco
138. ed by any one of 34 different interrupts the 33 interrupts shown in the micro DMA start vectors in Table 3 4 1 and a micro DMA soft start Figure 3 4 2 shows a 2 byte transfer carried out using a micro DMA cycle in transfer destination address INC mode micro DMA transfers are the same in every mode except counter mode The conditions for this cycle are as follows Both source and destination memory are internal RAM and multiples by 4 numbered source and destination addresses 1 state CLK Figure 3 4 2 Timing for Micro DMA Cycle States 1102 Instruction fetches cycle Gets next address code If the instruction queue buffer is FULL this cycle becomes a dummy cycle State 3 Micro DMA read cycle State 4 Micro DMA writes cycle State 5 same as state 1 2 92CM22 35 2007 02 16 TOSHIBA TMP92CM22 2 Soft start function In addition to starting the micro DMA function by interrupts TMP92CM22 includes a micro DMA software start function that starts micro DMA on the generation of the write cycle to the DMAR register Writing 1 to each bit of DMAR register causes micro once If write 0 to each bit micro DMA doesn t operate At the end of transfer the corresponding bit of the DMAR register is automatically cleared to 0 Only one channel can be set for DMA request at once Do not write 1 to more than one bit When writing again 1 to the DMAR register check whether the b
139. ed in this document shall be made at the customer s own risk 021023 B The products described in this document shall not be used or embedded to any downstream products of which manufacture use and or sale are prohibited under any applicable laws and regulations 060106 Q The information contained herein is presented only as a guide for the applications of our products No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties 021023 C The products described in this document are subject to foreign exchange and foreign trade control laws 060925 E For a discussion of how the reliability of microcontrollers can be predicted please refer to Section 1 3 of the chapter entitled Quality and Reliability Assurance Handling Precautions 030619 S 92CM22 1 2007 02 16 TOSHIBA TMP92CM22 4 External memory expansion e Expandable up to 16 Mbytes Shared program data area e Can simultaneously support 8 16 bit width external data bus Dynamic data bus sizing e Separate bus system 5 Memory controller e Chip select output 4 channels 6 8 bit timers 4 channels 7 16 bit timers 2 channels 8 General purpose serial interface 2 channels UART synchronous mode e IrDA 9 Serial bus interface 1 channel e 2C bus mode e Clock synchron
140. einforcement EMS Measure of endure noise allowing implementation of the following features 1 Reduced drivability for high frequency oscillator 2 Single drive for high frequency oscillator 3 SFR protection of register contents These functions need setting by EMCCRO to EMCCR2 1 Reduced drivability for high frequency oscillator Purpose Reduces noise and power for oscillator when connect oscillator to outside Block diagram fOSCH x1 tor Oscillation enable STOP EMCCRO lt EXTIN gt EMCCRO lt DRVOSCH gt X2 i Setting method The drivability of the oscillator is reduced by writing 0 to EMCCRO DRVOSCH register By reset DRVOSCH is initialized to 1 and the oscillator starts oscillation by normal drivability when the power supply is on Note When use drivability reduction function of oscillator please use in case of foscH 4 MHz to 10 MHz condition 92CM22 19 2007 02 16 TOSHIBA TMP92CM22 2 Single drive for high frequency oscillator Purpose Not need twin drive and protect mistake operation by inputted noise to X2 pin when the external oscillator is used Block diagram i fOSCH 1 pin Oscillation enable STOP lt EXTIN gt lt gt 2 Setting method The oscillator is disabled and starts operation as buffer by writing 1 to EMCCRO EXTIN register X2 pin is always outputted 1 By re
141. el by lt IxEDGE gt until be started interrupt process If changed level before interrupt process starting interrupt isn t processed correctly Example Case of set H level interrupt lt IxLE gt 1 IXEDGE 0 Keep H level until be started interrupt process If changed to L level before interrupt process starting interrupt isn t processed correctly 92CM22 42 2007 02 16 TOSHIBA TMP92CM22 Table 3 4 2 Function Setting of External Interrupt Pin IIMC IOLE 1 INTOEDGE 1 IIMC2 I1LE 1 INTTEDGE 1 TX High level 2 lt 121 gt 1 INT2EDGE 0 f Rising edge IIMC2 lt I3LE gt 0 INT3EDGE 0 NT p s 7 Falling edge IIMC2 I3LE 0 INT3EDGE 1 High level IIMC2 lt I3LE gt 1 0 _f Rising edge 1 lt 1 1 0 gt 0 0 or 0 1 or 1 0 Falling edge TB1MOD lt TB1CPM1 0 gt 1 0 Low level IIMC2 lt I2LE gt 1 INT2EDGE 1 Low level IIMC2 I3LE 1 INT3EDGE 1 92CM22 43 2007 02 16 TOSHIBA TMP92CM22 3 SIO receive interrupt control Symbol Name Address 7 6 5 4 3 2 1 Lo mug SIO Interrupt de Prohibit mode RMW edge mode control 1 INTRX1 level mode level mode INTRX1 level enables Detect edge INTRX1 H level INTRX1 INTRXO rising edge enable Detect edge INTRXO H Level INTRXO 92CM22 44 2007 02 16 TOSHI
142. ement mode e Time differential measurement mode Figure 3 8 1 to Figure 3 8 2 show block diagram of TMRBO and TMRB1 Each timer event counter consists of a 16 bit up counter two 16 bit timer registers One of them with a double buffer structure two 16 bit capture registers two comparators a capture input controller a timer flip flop and a control circuit Each timer event counter is controlled by 11 byte control register SFR This chapter consists of the following items 3 8 1 Block diagram 3 8 2 Operation 3 8 3 SFRs 3 8 4 Operation in Each Mode 1 16 bit interval timer mode 2 16 bit event counter mode 3 16 bit programmable pulse generation PPG output mode 4 Capture function examples Table 3 8 1 Pins and SFR of TMRB External 1 0 Share with PDO External pin triggr input pin TB1IN1 Share with PD1 Timer Timer tiptopouputpin flop output pin TBIOUTO Share uid Share with PC6 100 1 Share with SFR Timer register T m 118BH TB1RG1H 119BH Capture register TBOCP1L 118EH TB1CP1L 119EH TBOCP1H 118FH TB1CP1H 119FH 92CM22 120 2007 02 16 TMP92CM22 TOSHIBA Block Diagram 3 8 1 01010081 doy diy Jeu uonoejep YALEN 044081 Jeuut LOg LLNI 01009 0
143. enable 0 Receive disable 1 Receive enable Wakeup function 0 Disable 1 Enable 00 I O interface mode 01 7 bit mode 10 8 bit UART mode 11 9 bit UART mode After reset capp Serial transmission mode Serial transmission clock UART 00 Timer trigger 01 Baud rate generator 10 Internal clock fio 11 External clcok SCLKO input Serial transmission clock source UART umAoWggerowpursiga Note The clock selection for the interface mode is controlled by the serial control register SCOCR Serial transmission mode 00 interface mode mode Sum T S bitmode mode 9 bitmode bit mode Wakeup function 9 bit UART Interrupt generated when data is received Don t care 1 Interrupt generated only when SCOCR lt RB8 gt 1 Receiving function Receive disabled Receive enabled Handshake function CTS pin Disabled Always transferable Enabled Transmission data bit8 Figure 3 9 7 Serial Mode Control Register 0 for SIOO and SCOMODO 92CM22 154 TOSHIBA TMP92CM22 SC1MODO Bit symbol CTSE quee si um rode p e TB8 RXE WU 5 0 1 SCO SEA o o o o Function Transfer Handshake Receive Wakeup Serial transmission Serial transmission clock data bit8 function control function mode UART control 0 Receive 0 D
144. er for TMRAO1 92CM22 106 2007 02 16 TOSHIBA TMP92CM22 TMRA23 Mode Register rom a TA23MOD Bit TA23M1 TA23MO TASCLK1 TA3CLKO TA2CLK1 TA2CLKO 89 Sw coe o 26 9 9 Function Operation mode PWM cycle TMRAS source clock TMRA2 source clock 00 8 bit timer mode 00 Reserved 00 TA2TRG 00 Reserved 01 16 bit timer mode 01 26 01 1 01 1 10 8 bit PPG mode 10 27 10 716 10 4 11 8 bit PWM mode 11 7256 2 input clock 00 Don tset input clock TA23MOD TA23MOD EXPE 0 gt 01 lt TA23M1 0 gt 01 EN output 2 Overflow output for ims T 16 bit timer mode 47256 Select cycle PWM mode Resmed Select operation mode for TMRA23 00 8 bit timer x 2ch 16 bit timer 8 bit PPG 11 8 bit PWM TMRA2 8 bit timer Figure 3 7 6 Register for TMRA23 92CM22 107 2007 02 16 TOSHIBA TMP92CM22 TMRAt Flip Control TA1FFCR Bit symbol a TA1FFCIS 1105H 098 Readrwrite ME After reset cred ades den no im Read modify Function 00 Invert TA1FF TA1FF TA1FF m ioni 01 Set to 1 control for Inversion instruction is E prohibited 10 Clear TA1FF to 0 inversion signal select 11 Don t care
145. er in lt WDTP1 0 gt This 2 bit register is used for setting the watchdog timer interrupt time used when detecting runaway On a reset this register is initialized to WDMOD WDTPI1 0 00 The detection time for is 21 5 fsys 5 The number of system clocks is approximately 65 536 2 Watchdog timer enable disable control register lt WDTE gt At reset the WDMOD WDTE is initialized to 1 enabling the watchdog timer To disable the watchdog timer it is necessary to set this bit to 0 and to write the disable code B1H to the watchdog timer control register WDCR This makes it difficult for the watchdog timer to be disabled by runaway However it is possible to return the watchdog timer from the disabled state to the enabled state merely by setting lt WDTE gt to 1 3 Watchdog timer out reset connection lt RESCR gt This register is used to connect the output of the watchdog timer with the RESET terminal internally Since WOMOD lt RESCR gt is initialized to 0 at reset reset by the watchdog timer will not be performed 2 Watchdog timer control register WDCR This register is used to disable and clear the binary counter for the watchdog timer e Disable control The watchdog timer can be disabled by clearing WOMOD lt WDTE gt to 0 and then writing the disable code B1H to the WDCR register WDCR 01001 1 1 0 Write the clear code 4EH WDMOD 0 0 0 Clear WDMOD lt WDTEs to 0 WDCR 1 0 1 1000 1 Write the d
146. erent electrical sensitivity and vulnerability to physical stress It is the responsibility of the buyer when utilizing TOSHIBA products to comply with the standards of safety in making a safe design for the entire system and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life bodily injury or damage to property In developing your designs please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications Also please keep in mind the precautions and conditions set forth in the Handling Guide for Semiconductor Devices or TOSHIBA Semiconductor Reliability Handbook etc 021023 e The TOSHIBA products listed in this document are intended for usage in general electronics applications computer personal equipment office equipment measuring equipment industrial robotics domestic appliances etc These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and or reliability or a malfunction or failure of which may cause loss of human life or bodily injury Unintended Usage Unintended Usage include atomic energy control instruments airplane or spaceship instruments transportation instruments traffic signal instruments combustion control instruments medical instruments all types of safety devices etc Unintended Usage of TOSHIBA products list
147. ersion Inverted when the UC12 value matches the value in TB1RG1H L Disable inversion Enable inversion Inverted when the UC12 value is loaded into TB1CPOH L Disable inversion Enable inversion when the UC12 value is loaded into TB1CP1H L Disable inversion Enable inversion TB1FF1 control 00 Invert value of TB1FF1 Set TB1FF1 to 1 Set TB1FF1 to 0 Figure 3 8 7 Register for TMRB 92CM22 131 2007 02 16 TOSHIBA TMP92CM22 TMRBO register KO TBORGOL bit Symbol 1188 Read Write After reset TBORGOH bit Symbol 1189H Read Write After reset TBORGIL bit Symbol 118 Read Write After reset TBORG1H bit Symbol 118BH Read Write After reset Undefined Undefined Undefined Undefined TBOCPOL 118 Read Write Undefined TBOCPOH 118DH Read Write Undefined TBOCP1L 118EH Read Write After reset Undefined TBOCP1H 118FH Read Write After reset gt gt pl o 9 o 9 7 lt lt lt lt 3 3 9 3 9 5 5 2 5 Undefined TMRB1 register TB1RGOL 1198H Undefined TB1RGOH 1199H Undefined TBIRGIL 119 Undefined TBIRGHH bitSymbol TBICPOL es TBICPOH bit Symbol ae TBICPIL TBICPIH Undefined Note All registers are prohibited to execute read
148. eserved Others Reserved BE _ BOREC B00M1 00 0 BOBUSI BOBUSO 0 0 0 o 0 CS select Always Always 0 No insert 00 ROM SRAM Data bus width 0 Disable write 0 write 0 dummy 101 Reserved 00 8 bits 1 Enable cycle 10 Reserved 01 16 bits Default 11 Reserved 10 Reserved 1 Insert 11 Reserved dummy cycle 010 1 wait 110 3 waits 011 WAIT pin 010 1 wait 110 3 waits 011 WAIT pin Read waits 001 0 waits 101 2 waits 111 4 waits Others Reserved Write waits 001 0 waits 101 2 waits 111 4 waits Others Reserved 010 1 wait 110 3 waits 011 WAIT pin 010 1 wait 110 3 waits 011 WAIT pin 0 No insert 00 ROM SRAM dummy 101 Reserved cycle 10 Reserved Default 11 Reserved 1 Insert dummy Data bus TN 8 bits 16 bits Reserved Reserved ce e Jm o 1 0 0 1 0 Write waits Read waits 001 0 waits 001 0 waits 101 2 waits 101 2 waits 111 4 waits 111 4 waits Others Reserved Others Reserved B Bem B2REC B20M1 20 0 B2BUS1 B2BUSO a o o 0o o 0 v CS select Always 0 No insert 00 ROM SRAM Data bus width 0 Disable write 0 dummy 01 Reserved 00 8 bits 1 Enable cycle 10 Reserved 01 16 bits Default 11 Reserved 10 Reserved 1 Insert 11 Reserved dummy cycle BSWW2 B3WW1 BSWWO B3WR2 B3WR1 B3WRO
149. et by the lt PR1 0 gt of the PMEMCR register When data is read out up to the border of the set page the controller completes the page reading operation The start data of the next page 15 read in the normal cycle The following data is set to page read again PR1 PRO Bit PMEMCR register Pai Pao ROM Page Size o e se 2 Signal pulse CLKOUT 1 1 to A23 D 0 1 oc 2 1 52 aoe 1 1 1 RD 1 Do dq tabs ES us 1 1 1 1 FD Dat Dat DO to 031 E Figure 3 6 2 Page mode access Timing 8 example 92CM22 90 tAD2 De Data input tHR 2007 02 16 TOSHIBA 3 6 5 TMP92CM22 List of Registers The memory control registers and the settings are described as follows For the addresses of the registers see list of special function registers in section 5 1 Control registers The control register is a pair of BnCSL and BnCSH n is a number of the block address area BnCSL has the same configuration regardless of the block address areas In BnCSH only B2CSH which is corresponded to the block address area 2 has a differe
150. evel After detecting this situation master B resets a counter of high level width of an own clock pulse and sets the internal SCL output to the low level Master A finishes counting low level width of an own clock pulse at point b and sets the internal SCL output to the high level Since master B holds the SCL line of the bus at the low level master waits for counting high level width of an own clock pulse After master B finishes counting low level width of an own clock pulse at point c and master A detects the SCL line of the bus at the high level and starts counting high level of an own clock pulse The clock pulse on the bus is determined by the master device with the shortest high level width and the master device with the longest low level width from among those master devices connected to the bus 4 Slave address and address recognition mode specification When the TMP92CM22 is used as a slave device set the slave address lt SA6 0 gt and ALS to the I2COAR Clear the ALS to 0 for the address recognition mode b Master slave selection Set the SBIOCR2 lt MST gt to 1 for operating the TMP92CM22 as a master device Clear the SBIOCR2 lt MST gt to 0 for operation as a slave device The lt MST gt is cleared to 0 by the hardware after a stop condition on the bus is detected or arbitration is lost 92CM22 179 2007 02 16 TOSHIBA TMP92CM22 6 Transmitter receiver selection Set the SBIOCR2 lt
151. fer 0 Stop prescaler counter 0 Disable 1 Operate UC3 UC2 1 Enable 0 Stop and clear 1 Run Count up TA2REG double buffer control Count operation pene stop and sear Note The values of bits 4 to 6 of TA23RUN are undefined when read Figure 3 7 4 Register for TMRA 92CM22 105 2007 02 16 TOSHIBA TMP92CM22 TMRAO1 Mode Register nec qp TAO1MOD Bit symbol 01 1 01 0 TA1CLK1 TA1CLKO TAOCLK1 TAOCLKO MU eo op Function Operation mode PWM cycle source clock TMRAO source clock 00 8 bit timer mode 00 Reserved 00 TAOTRG 00 TAOIN pin input Note 01 16 bit timer mode 01 26 01 1 01 1 10 8 bit PPG mode 10 27 10 716 10 4 11 8 bit PWM mode 11 7256 11 9T16 input clock TAOIN External 1 input clock mma mma lt 01 1 0 gt 01 lt 01 1 0 gt 01 00 Matching output for Overflow output for TMRAO 16 bit timer mode Select cycle in PWM mode 00 Reseved ooo 2 x Source clock 10 27 x Source clock 28 x Source clock Select operation mode for TMRO1 00 8 bit timers x 2ch 16 bit timer 8 bit PPG 11 8 bit PWM TMRAO 8 bit timer TMRA1 Note When set TAOIN pin set TAO1MOD after set port C Figure 3 7 5 Regist
152. first As entering data in TAOREG temporarily disables the compare while entering data in TA1REG starts the compare Example To generate INTTA1 interrupt every 0 4 s at 40 MHz set the timer registers TAOREG and TA1REG as follows If 16 256 fc s at fc 40MHz is used as the input clock for counting set the following value in the registers 0 4 s 256 fc s 62500 F424H e g set TATREG to F4H and TAOREG to 24H 92CM22 113 2007 02 16 TOSHIBA TMP92CM22 The comparator match signal is output from TMRAO each time the up counter UCO matches TAOREG though the up counter UCO is not cleared In the case of the TMRA1 comparator the match detect signal is output on each comparator pulse on which the values in the up counter UC1 and TA1REG match When the match detect signal is output simultaneously from both the comparator TMRAO and TMRA1 the up counters UCO and UCI are cleared to 0 and the interrupt INTTA1 is generated Also if inversion is enabled the value of the timer flip flop TA1FF is inverted Example When TA1REG 04H and TAOREG 80H Value of up counter 0080H 0180H 02804 0380H 0480H 0080H UC1 UCO comparator match detect signal TMRA1 comparator match detect signal Interrupt INTTAO Interrupt INTTA1 Timer output TA1OUT X Inversion Figure 3 7 12 Timer Output by 16 Bit Timer Mode 3 8 bit PPG Pro
153. format Format of transmission receiving must set to data length 8 bit without parity bit 1 bit of stop bit Any other settings don t guarantee the normal operation 4 SFR Figure 3 9 27 shows the control register SIRCR If change setting this register must set it after set operation of transmission receiving to disable Both lt gt and lt gt of this register should be clear to 0 Any changing for this register during transmission or receiving operation doesn t guarantee the normal operation The following example describes how to set this register 1 SIO setting Set SIO side 2 LD SIRCR 07H Set receiving effect pulse width to 16X 3 LD SIRCR 37H TXEN RXEN enable the transmission and receiving 4 Transmission receiving The modem operates as follows 5100 starts transmitting receiver starts receiving b Notes 1 Making baud rate when using IrDA In baud rate during using IrDA must set 01 to SCOMODO lt SC1 0 gt in SIO by using baud rate generator TAOTRG SCLKO input of except for it can not using 2 Output pulse width and baud rate generator during transmission IrDA As the IrDA 1 0 physical layer specification the data transfer speed and infra red pulse width is specified Table 3 9 4 Specification of Transfer Rate and Pulse Width Transfer Modulation 1422 Minimum of Typical of Pulse Maximum of Rate 96 of Rate Pulse Width Width 3 16 Pu
154. grammable pulse generation output mode Square wave pulses can be generated at any frequency and duty ratio by TMRAO The output pulses may be active low or active high In this mode TMRAI cannot be used TMRAO outputs pulses on the TA1OUT pin Shared with PC1 lt TA1FFC1 0 gt 10 lt TA1FFC1 0 gt 01 Example lt 1 1 0 gt 01 TAOREG UCO match Interrupt INTTAO TA1REG and UCO match Interrupt INTTA1 TA1OUT TAOREG Figure 3 7 13 8 Bit PPG Output Waveforms 92CM22 114 2007 02 16 TOSHIBA TMP92CM22 In this mode a programmable square wave 15 generated by inverting the timer output each time 8 bit up counter UCO matches the value in one of the timer registers TAOREG or TAIREG The value set in TAOREG must be smaller than the value set in TAIREG Although the up counter for TMRA1 UC1 is not used in this mode TAOLRUN lt TA1RUN gt should be set to 1 so that UCI 18 set for counting Figure 3 7 14 shows a block diagram representing this mode TAO1RUN TAORUN Selector 8 bit up counter TAO1MOD lt TAOCLK1 0 gt Inversion Comparator INTTA1 T Register buffer TAOREG WR TA1REG TA01RUN lt TAORDE gt Internal data bus Figure 3 7 14 Block Diagram of 8 Bit PPG Output Mode If the TAOREG double buffer is enabled in this mode the value of the register buffer will be shifted into TAO
155. he HALT instruction exceeds the value of interrupt mask register the interrupt due to the source is processed after release the HALT mode and CPU status executing an instruction that follows the HALT instruction When the interrupt request level set before executing the HALT instruction is less than the value of the interrupt mask register release the HALT mode is not executed In non maskable interrupts interrupt processing is processed after release the HALT mode regardless of the value of the mask register However only for INTO to INT3 interrupts even if the interrupt request level set before executing the HALT instruction is less than the value of the interrupt mask register release the HALT mode is executed In this case interrupt processing and CPU starts executing the instruction next to the HALT instruction but the interrupt request flag is held at 1 e Release by resetting Release all halt status is executed by resetting When the STOP mode is released by RESET it is necessary enough resetting time Refer Table 3 3 4 to set the operation of the oscillator to be stable When release the HALT mode by resetting the internal RAM data keeps the state before the HALT instruction is executed However the other settings contents are initialized Release due to interrupts keeps the state before the HALT instruction is executed 92CM22 23 2007 02 16 TOSHIBA TMP92CM22 Table 3 3 3 Source of Halt State Release an
156. he serial bus interface is connected to an external device through P91 SDA and P92 SCL in the I2C bus mode and through P90 SCK P91 SO and P92 51 in the clocked synchronous 8 bit SIO mode Each pin is specified as follows P9ODE P9CR P9FC eos P91ODE lt P92C P91C P90C gt P92F 90 gt bus mode Cbusmode mode Clocked 011 011 8 54 SIO mode 010 010 X Don t care Note Note When using SI and SCK input function set P9FC lt P92F P90F gt to 0 Function setting 3 10 1 Configuration INTSBEO pe requests P90 SCK control L P91 Divider Transfer control circuit Er 0 P92 SI SCL canceller i i C bus data control m SBIOCRA 2 SBIOBR SBIOCR1 SBIOBRO 1 SBIOSR SBIO control register 2 bus SBIO data SBIO control SBIO status register address register _ buffer register register 1 SBIO baud rate registers 0 and 1 Figure 3 10 1 Serial Bus Interface 0 SBIO 92CM22 172 2007 02 16 TOSHIBA TMP92CM22 3 10 2 Control The following registers are used to control the serial bus interface and monitor the operation status Serial bus interface control register 1 SBIOCR1 Serial bus interface control register 2 SBIOCR2 e Serial bus interface 0 data buffer register SBIODBR bus 0 address register I2COAR e Serial bus interface 0 statu
157. ial 0 BR LM INTTA2 8 bit timer 2 0060H FFFF60H 18H Reserved 0074H FFFF74H 1DH INTRX1 Serial 1 INTRX1 Serial 1 5101 receive receive 0088H FFFF88H 22H Note 1 INTTX1 transmission 31H 92CM2 32 2007 0216 n FEQ Se Lm xl 0 EE RENE ee a m 26 28 O 29 Ps ue 32 b c cu d v p e NEE 039 _ 42 NES ay EE 081 ae ae pa NR ANN a a NM TOSHIBA TMP92CM22 t Vector Andrass Micro DMA Default Priority Interrupt Source Value idea Start Vector INTAD AD conversion end FFFFCCH 33H INTTCO Micro DMA end Channel 0 INTTC1 Micro DMA end Channel 1 INTTC2 Micro DMA end Channel 2 INTTC3 Micro DMA end Channel 3 Maskable INTTC4 Micro DMA end Channel 4 INTTC5 Micro DMA end Channel 5 INTTC6 Micro DMA end Channel 6 INTTC7 Micro DMA end Channel 7 Reserved 00FCH FFFFFCH Note 1 When initiating initiating micro set at edge detect mode Note 2 Micro DMA default priority Micro DMA initiation takes priority over other maskable interrupts 92CM22 33 2007 02 16 TOSHIBA 3 4 2 TMP92CM22 Micro DMA In addition to general purpose interrupt processing the TMP92CM22 also includes a micro function Micro processing for interrupt requests set by micro 15 performed at the highest priority level
158. ilable in I O interface mode Clear BROCR lt BROADDE gt to 0 before dividing by The method for calculating the transfer rate when the baud rate generator is used is explained below mode Input clock of baud rate generator Baud rate 16 Frequency divider for baud rate generator I O interface mode Baud rate Input clock of baud rate generator 2 Frequency divider for baud rate generator 92CM22 146 2007 02 16 TOSHIBA TMP92CM22 e Integer divider divider For example when the fc 39 3216 MHz the input clock frequency 2 the frequency divider BROCR BR0S3 0 8 and BROCR lt BROADDE gt 0 the baud rate in UART mode is as follows Clock state Clock gear 1 1 fc 32 Baud rate 16 39 3216 x 10 16 8 16 9600 bps Note The 16 K 16 division function is disabled and setting BROADD lt BROK3 0 gt is invalid e 16 K 16 divider UART mode only Accordingly when fc 31 9488 MHz the input clock frequency 2 the frequency divider N BROCR BR0S3 0 6 BROADD lt BROK3 0 gt 8 and BROCR lt BROADDE gt 1 the baud rate is as follows Clock state Clock gear 1 1 fc Baud rate R a 16 31 9488 10 32 6 16 9600 bps Table 3 9 3 show examples of UART mode transfer rates Additionally the external clock input is available in the serial clock Serial channels 0 and 1 The method for calc
159. includes 2 serial I O channels Each channel is called SIOO and SIO1 For both channels either UART Mode Asynchronous transmission or I O interface mode Synchronous transmission can be selected e l Ointerface mode Mode 0 For transmitting and receiving data using the synchronizing signal SCLK for extending I O Mode 1 7 bit data mode Mode 2 8 bit data Mode 3 9 bit data In mode 1 and mode 2 a parity bit can be added Mode 3 has a wakeup function for making the master controller start slave controllers via a serial link Multi controller system Figure 3 9 2 and Figure 3 9 3 are block diagrams for each channel Each channel is structured in prescaler serial clock generation circuit receiving buffer and control circuit and transfer buffer and control circuit Serial channels 0 and 1 can be used independently Both channels operate in the same function except for the following points hence only the operation of channel 0 is explained below Table 3 9 1 Differences between Channels 0 to 1 _ Channel o Channel 1 TXDO PFO TXD1 PF3 RXDO PF1 RXD1 PF4 CTS0 SCLKO PF2 CTSi SCLK1 IrDA mode This chapter contains the following sections 3 9 1 Block Diagram 3 9 2 Operation of Each Circuit 3 9 3 SFRs 3 9 4 Operation in Each Mode 3 9 5 Support for IrDA Mode 92CM22 141 2007 02 16 TOSHIBA TMP92CM22 e Mode 0 I O interface mode 1X 2X 3X 4X 5K 6X7 Transfer dire
160. ing Select receiving effective pulse width transmission data logic pulse width 0 H pulse 0 3 16 1 L pulse 1 1 16 data operation Set effective pulse width for equal or 0 Disable 0 Disable more than 2x x Value 1 100 ns 1 Enable 1 Enable Can be set 1 to 14 Cannot be set 0 15 Select receiving effective pulse width Formula Receiving effective pulse width gt 2x x Setting value 1 100 ns 1 fsys 0000 Cannot be set 0001 Pulse width of equal or more than 4x 100 ns is effective 1110 Pulse width of equal or more than 30x 100 ns is effective 1111 Cannot be set Enable of receiving operation Disable receiving operation Received input is ignored Enable receiving operation Enable of transmission operation Disable transmission operation Input from SIO is ignored Enable transmission operation Select transmission pulse width 0 Pulse width of 3 16 Pulse width of 1 16 Note If a pulse width complying with the IrDA 1 0 standard 1 65 min can be guaranteed with a low baud rate setting this bit to 1 will result in reduced power dissipation Figure 3 9 27 IrDA Control Register 92CM22 171 2007 02 16 TOSHIBA TMP92CM22 3 10 Serial Bus Interface SBI The TMP92CM22 has a 1 1 serial bus interface Serial bus interface SBIO include following 2 operation modes DC bus mode Multi master Clocked synchronous 8 bit SIO mode T
161. interface input SCK Clock signal in SIO mode SO Data output signal in SIO mode SDA Data signal in bus mode SI Data input signal in SIO mode and SCL Clock signal in I2C bus mode These settings operate by programming to the corresponding bit of P9FC Resetting set value of P9CR and P9FC to 0 all bits are set to input port And all bits of output latch are set to 1 Reset Direction control on bit basis P9CR write 2 Function control on bit basis w T 2 8 S A Output latch Selector B Open drain enable P9ODE lt P910DE gt P9 write lt P920DE gt SCK output SO output SDA output SCL output 5 Selector A P9 read SCK input SDA input SI SCL input Figure 3 5 14 Port 9 P90 to P92 92CM22 63 LI P90 SCK P91 SO SDA P92 SI SCL 2007 02 16 TOSHIBA TMP92CM22 Port 9 Register prece wieder og imei a NINE TUR RN a After reset aon from external port Output latch register is set to 1 Port 9 Control Register Bit After reset_ Function Jo o qp Port 9 Function Register 0027H Readwrite e e Func
162. interface mode Note2 Set BROCR BROADDE to 1 after setting 1 to 15 to BROADD lt BROK3 0 gt when 16 K 16 division function is used Writes to unused bits in the BROADD register do not affect operation and undefined data is read from these unused bits Figure 3 9 11 Baud Rate Generator Control for 5100 BROCR and BROADD 92CM22 158 2007 02 16 TOSHIBA TMP92CM22 BR1CR Bit symbol BR1ADDE BR1CK1 BR1CKO BR1S3 BR1S2 BR1S1 150 208 Mereset o Function Always 16 K 16 00 pTO write 0 division 01 2 m 0 Disable 10 6T8 Divided frequency setting 1 Enable 11 6732 16 K 16 divisions enable Input clock selection for baud rate generator Disabled 0 mtemalcock TO sw spes xe gb o9 Reddite o a PO Function Set frequency divisor K Divided by N 16 K 16 Baud rate generator frequency divisor setting BR1CR lt BR1ADDE gt 1 BR1CR lt BR1ADDE gt 0 0000 16 0010 N 2 0001 1 _ 1111 N 15 RIR 0001 N 1 1111 N 15 lt BR1K3 0 gt 2 0000 0001 1 Divided by Divided by N 2 Disable 1111 K 15 16 16 Note1 Availability of 16 K 16 division function UART mode mode a
163. ircuit does not support Fast mode it supports standard mode only Although the bus circuit itself allows the setting of a baud rate over 100 kbps the compliance with the specification is not guaranteed in that case Figure 3 10 3 Register for Bus Mode 92CM22 174 2007 02 16 TOSHIBA TMP92CM22 Serial Bus Interface Control Register 2 gt x 7 SBIOCR2 symbol SBIM1 SBIMO SWRST1 SWRSTO 1243H Read Write W Note 1 W Note 1 Aterreset 1 Read Function Master Transmitter Start stop Release Serial bus interface m control modify write slave receiver condition INTSBEO Note 2 write 10 and 017 in instruction is selection selection generation interrupt 00 port mode order then an internal prohibited request 01 SIO mode software reset signal is enerated 10 bus mode 9 11 Reserved Serial bus interface operating mode selection Note 2 Port mode Serial bus interface output disabled Clocked synchronous 8 bit SIO mode bus mode 1 Reserved 01 aja INTSBEO interrupt request EE Release interrupt request Start stop condition generation Generates the stop condition Generates the start condition Transmitter receiver selection Receiver Transmitter Master slave selection Slave Master Note 1 Reading this register function as SBIO
164. isable 00 I O interface mode 00 Timer AO trigger 0 CTS disable 1 Enable 01 7 bit UART mode 01 Baud rate generator disable 1 10 8 UART mode 10 Internal clock 1 CTS 11 9 bit UART mode 11 External clcok enable SCLK1 input Serial transmission clock source UART 00 trigger output signal Baud rate generator Internal clock fio External clock SCLK1 input Note The clock selection for the interface mode is controlled by the serial control register SC1CR Serial transmission mode 00 interface mode bit mode 10 UART mode 8 bit mode Wakeup function 9 bit UART Other modes Interrupt generated when data is received Don t 1 Interrupt generated only when SC1CR lt RB8 gt Receiving function Receive disabled Receive enabled Handshake function CTS pin Disabled Always transferable Enabled Transmission data bit8 Figure 3 9 8 Serial Mode Control Register for SIO1 and SC1MOD 92 22 155 2007 02 16 TOSHIBA TMP92CM22 EON SCOCR Bit symbol EVEN OERR PERR FERR SCLKS IO AW miesseowenen 7 1 0 Function Received i Parity 1 Se Le 0 SCLKO 0 Baud rate data bit addition Overrun Parity Framing 0 Disable 1 SCLKO 1 SCLKO 1 Enable l pin in
165. isable code B1H e Enable control Set WOMOD lt WDTE gt to 1 e Watchdog timer clear control To clear the binary counter and cause counting to resume write the clear code 4 to the register WDCR 0 1 0 0 1 1 1 0 Write the clear code 4EH Note1 If the disable control set the disable code B1H to WDCR after weirint the clear code 4EH once Please refer to setting example Note2 If the Watchdog timer setting change setting after setting to disable condition once 92CM22 213 2007 02 16 TOSHIBA TMP92CM22 WDMOD Bit symbol WDTE WDTP1 WDTPO I2WDT RESCR Us Ne 1 o Function WDT control Select detecting time Always 1 Internally Always 1 Enable 00 2 fjo write 0 connects write 0 WDT out 01 27 5 to the reset pin a 10 2 11 20 Watchdog timer out control 1 Connects WDT out to a reset IDLE2 control Operation 1 Watchdog timer detection time 00 25 Approximately 3 28 ms at fogcH 40 MHz 2 fio Approximately 1 31 ms at 40 MHz 2 fio Approximately 52 4 ms at fogcH 40 MHz 22 Approximately 210 ms at foscH 40 MHz Watchdog timer enable disable control Dsabed Figure 3 12 4 Watchdog Timer Mode Register Eras EE E 9024 eade write Function B1H W
166. isters and thus cannot be read 92CM22 124 2007 02 16 TOSHIBA TMP92CM22 4 Capture registers TBOCPOH L TBOCP1H L TB1CPOH L and TB1CP1H L These 16 bit registers are used to latch the values in the up counters UC10 Data 1n the capture registers should be read both upper and lower all 16 bits For example using 2 byte data transfer instruction or using 1 data transfer instruction twice for lower 8 bits and upper 8 bits in order The addresses of the capture registers are as follows pus 0 1 TBOCPOH L TBOCP1H L Upper 8 bits Lower 8 bits Upper 8 bits Lower 8 bits i 118DH 118CH 118FH 118 1 1 OR E T DOOR IE URS Su NE CR RAE S NODE S DES RCN 1 1 i TB1CPOH L TB1CP1H L Upper 8 bits Lower 8 bits Upper 8 bits Lower 8 bits i 119DH 119CH 119FH 119EH 1 1 1 The capture registers are read only registers and thus cannot be written b Capture and external interrupt control This circuit controls the timing to latch the value of up counter UC10 into TBOCPOH L TBOCP1H L and generating for external interrupt Interrupt timing of capture register and selection edge of external interrupt are set by TBOMOD lt TBOCPM1 0 gt TMRBO does not include the selec
167. istor up resistor _ Programmable pull up resistor P90 to P92 to PA2 PA7 s PCO PC1 PC5 PC6 PF1 PF4 RESET NMI SET E wee ES 92CM22 217 2007 02 16 TOSHIBA TMP92CM22 4 2 AC Characteristics 4 2 1 Basis Bus Cycle Read cycle Vcc 3 3 0 3 V fc 4 to 40 MHz Ta 40 to 85 C fsys fsys No Parameter Symbol Min Max 20 MHz 125 kHz Unit fc 40 4 MHz oscan _ x _ system clock so s soo fns os ____ 8 e owourmanwan wo 5 1 A0 to A23 valid d tap 2 0T 30 70 15970 ns DO to D15 input at O waits 5 2 A0 to A23 valid taps 3 0T 30 120 23970 ns DO to D15 input at 1 wait RD fall MT 1 5T 30 45 11970 ns DO to D15 input at 0 waits 2 RD fall 6 all gt 2 5T 30 19970 DO to D15 input at 1 wait RII MEER INE m MES wm ros trax ost 20 90 o moasa w 9 o o r 9 l o o w warsupime ______ 3 3 55 s 5 5 Ls Write cycle Vcc 3 3 0 3 V fc 4 to 40 MHz Ta 40
168. it is 0 before writing 1 If read 1 micro transfer isn t started yet When a burst is specified by DMAB register data 18 continuously transferred until the value in the micro DMA transfer counter is 0 after start up of the micro DMA If execatee soft start during micro DMA transfer by interrupt source micro DMA transfer counter doesn t change Don t use Read modify write instruction to avoid writign to other bits by mistake Symbol Name 7 e 5 2 3 DMAR DMA request 109H R W Prohibit ww L9 1 DMA request in software 3 Transfer control registers The transfer source address and the transfer destination address are set in the following registers Data setting for these registers is done by an LDC cr 1 instruction Channel 0 DMA Source address register 0 only use LSB 24 bits DMA Destination address register 0 only use LSB 24 bits DMA Counter register 0 1 to 65536 DMA Mode register 0 Channel 7 DMA Source address register 7 DMA Destination address register 7 DMA Counter register 7 DMA Mode register 7 32 bits 92CM22 36 2007 02 16 TOSHIBA TMP92CM22 4 Detailed description of the transfer mode register 000 zz Destination address INC mode DMADn lt DMASn lt DMAOn 1 5 states If DMACn 0 then INTTC 001 zz Source address DEC mode DMADn lt DMASn DMACn lt 1
169. k TXDSFT 92CM22 150 2007 02 16 TOSHIBA TMP92CM22 Handshake function Use of CTSO pin allows data to be sent in units of one data format thus overrun errors can be avoided The handshake function is enabled or disabled by the SCOMODO xCTSE setting When the CTSO pin condition is high level after completed the current data transmission data transmission is halted until the CTSO pin state is low again However the INTTXO interrupt is generated and it requests the next send from data to the CPU The next data is written in the transmission buffer and data transmission 1s halted Though there is no RTS pin a handshake function can be easily configured by setting any port assigned to be the RTS function The RTS should be output High to request send data halt after data receive is completed by software in the receive interrupt routine TMP92CM22 TMP92CM22 Transmission side Receiving side Figure 3 9 5 Handshake Function Timing of writing data to transmission buffer Ki X Send is ee from a to b 13 14 15 16 1 2 3 14 15 16 1 2 3 TXDCLK T 1 Ifthe CTS signal goes high during transmission will be stop next transmission data after completion the current transmission Note 2 Transmission starts on the first falling edge of the TXDCLK clock after the CTS signal has fallen Figure 3 9 6 CTS Clear to send Signal Timing 92CM22 151 2007 02 16 TOSHIBA TMP92CM
170. k register lt IFF2 0 gt to 7 disabling all maskable interrupts Table 3 4 1 shows the TMP92CM22 interrupt vectors and micro DMA start vectors The address to FFFFFFH 256 bytes is assigned for the interrupt vector area 92CM22 31 2007 02 16 TOSHIBA TMP92CM22 Table 3 4 1 TMP92CM22 Interrupt Vectors and Micro DMA Start Vectors Address Vector Micro DMA Default Priority Interrupt Source 2 Start Vector Resetor SWiO instrucion 5 11 instruction Illegal instruction SWI2 instruction SWI3 instruction Non maskable SWI4 instruction 0010H FFFF10H SWIS5 instruction 0014H FFFF14H SWI6 instruction 0018H FFFF18H 9 2 5 17 instruction NMI External interrupt input pin INTWD Watchdog Timer Maskable Micro DMA Note 2 INTO External interrupt input pin H Note 1 INT1 External interrupt input pin H Note 1 INT2 External interrupt input pin H Note 1 External interrupt input pin H Note 1 Reserved Reserved Reserved 10H Reserved 11H Reserved 12H Reserved 13H INTPO Protect 0 WR to SFR 14H Reserved 15H INTTAO 8 bit timer 0 16H INTTA1 8 bit timer 1 17H INTTA3 8 bit timer 3 19H INTTBOO 16 bit timer 0 1AH INTTBO1 16 bit timer 0 1BH Reserved 1CH INTTBOO 16 bit timer 0 Overflow 1EH Reserved 1FH receive 20H Note 1 transmission 21H 5 0 5100 INTTXO Ser
171. l register2 SBIOCR2 when write 92CM22 246 01 SIO mode 10 bus mode 11 Reserved generated Serial bus interface operating mode selection 00 Port mode 01 SIO mode 10 bus mode 11 Reserved 2007 02 16 TOSHIBA TMP92CM22 bus Serial channel 2 2 Symbol Name Address 7 6 5 4 3 2 EMI ese ac SS 1244H uw a Ae c mode TTSS Prohibi s SBIOBRO baud rate 1 em SIO mode SS SSS Pri ccc oL eer SBIO eee a SBIOBR1 baud rate 1245H em Aways register 1 control write 0 1 Operate 92CM22 247 2007 02 16 TOSHIBA TMP92CM22 10 AD converter 1 2 em 7 1 2 1 REPEAT tase 5 pred s ADMODO control write 9 1 register 0 RARA 0 Single 0 Fixed 0 End mode 1 Busy 1 Repeat mode mode 1 Channel scan mode perge o o o o Always Always Input channel i write 0 write 0 write 0 000 001 ANT ANO AN1 AD mode 010 2 2 ADMOD1 control 011 2 register 1 100 ANOCAN1 AN2 AN3 101 1 gt 2 gt gt 4 gt 110 6 ANOS
172. le 3 7 2 Prescaler Output Clock Resolution Clock gear System clock Timer counter input clock selection selection TMRA prescaler SYSCR1 SYSCR1 TAxMOD lt TAxCLK1 0 gt 9 1 1 2 9 4 1 8 er16 1 32 07256 1 512 2 Up counters UCO and UC1 These are 8 bit binary counters which count up the input clock pulses for the clock specified by TAOIMOD The input clock for UCO is selectable and can be either the external clock input via the TAOIN pin or one of the three internal clocks 4 or 16 The clock setting is specified by the value set in TAOLMOD lt TA01CLK1 0 gt The input clock for UC1 depends on the operation mode In 16 bit timer mode the overflow output from UCO is used as the input clock In any mode other than 16 bit timer mode the input clock is selectable and can either be one of the internal clocks 1 16 or 256 or the comparator output The match detection signal from TMRAO For each interval timer the timer operation control register bits lt gt and TAO1RUN TA1RUN can be used to stop and clear the up counters and to control their count reset release both up counters stopping the timers 92CM22 102 2007 02 16 TOSHIBA TMP92CM22 3 Timer registers TAOREG and TAIREG These are 8 bit registers which can be used to set a time interval When the value set in the timer register TAOREG or TA1REG matches the value in the corresponding
173. lect signal CS0 to CS3 These settings operate by programming 1 to the corresponding bit of P8FC Resetting set all bits of P8FC to 0 these pits set output mode Function control on bit basis P8FC write Internal data bus S Output latch A P80 CS0 Selector P81 651 P8 write P82 C82 P83 CS3 P8 read Figure 3 5 12 Port 8 Port 8 Register p Jesum Rewe were JU d 0 Io Port 8 Function Register Ecco aes eu es DI er eame 0023H Function 0 Port 0 Port 0 Port x Port 1 CS3 1 CS2 1 CS1 1 50 Note 1 Read modify write instruction is prohibited for the registers P8FC Note 2 When set P82 pin as Cs2 after release reset set function register PBFC P82F 1 in keep output latch of P82 to 0 8 lt 82 gt 0 If set function register P8FC lt P82F gt 1 after set output latch to 1 P8 lt P82 gt 1 maybe operation become to error because CS2 output don t output correctly Figure 3 5 13 Register for Port 8 92CM22 62 2007 02 16 TOSHIBA 3 5 7 Port 9 P90 to P92 TMP92CM22 Port 9 is 3 bit general purpose I O port Each bit can be set individually for input or output In addition to functioning as a general purpose I O port port 9 can also function as a serial bus
174. led ARBITRATION LOST Master B device that loses arbitration releases the internal SDA output in order not to affect data transmitted from other masters with arbitration When more than one master sends the same data at the first word arbitration occurs continuously after the second word Internal SDA output Master A Internal SDA output Set internal SDA output to 1 Master B SDA line after arbitration has been lost w Figure 3 10 11 Arbitration Lost 92CM22 181 2007 02 16 TOSHIBA TMP92CM22 The TMP92CM22 compares the levels on the bus s SDA line with those of the internal SDA output on the rising edge of the SCL line If the levels do not match arbitration is lost and SBIOSR lt AL gt is set to 1 When SBIOSR lt AL gt is set to 1 SBIOSR lt MST TRX gt are cleared to 00 and the mode is switched to slave receiver mode Thus clock output 13 stopped in data transfer after setting AL 1 SBIOSR AL is cleared to 0 when data is written to or read from SBIODBR or when data is written to SBIOCR2 Internal SCL Master Output A Internal SDA X D7A D6A X D4A X X D2A X DOA 7 X X DAA output i Stop the clock pulse Internal SCL 1 2 3 4 Master output B Internal SDA 078 Keep internal SDA output to high level as losing arbitration output AL lt MST gt lt T
175. lowing is a setting example for PLL starting and PLL stopping Example 1 PLL starting PLLCR EQU 10E8H LD PLLCR 10XXXXXXXB Enables PLL operation and starts lockup LUP BIT 5 PLLCR Detects end of lockup JR Z LUP LD PLLCR 11XXXXXXB Changes fc from 10 MHz to 40 MHz X Don t care lt PLLON gt lt FCSEL gt PLL output Count up by foscH 5 7 75757527575 v Changes from 10 MHz to 40 MHz Ends of lockup Starts PLL operation and starts lockup 92CM22 17 2007 02 16 TOSHIBA TMP92CM22 Example 2 PLL stopping PLLCR EQU 10E8H LD PLLCR 10XXXXXXB Changes fc from 40 MHz to10 MHz LD PLLCR OOXXXXXXB Stop PLL X Don t care lt FCSEL gt lt PLLON gt 1 Y Changes from 40 MHz to 10 MHz Stops PLL operation Limitation point on the use of PLL 1 When PLL is started don t set fc from foscH to fPLL at same time Don t setting LD PLLCR 00H LD PLLCR COH 2 When PLL is started don t set fc from foscH to fprr at same time Don t setting LD PLLCR COH LD PLLCR 00H 92CM22 18 2007 02 16 TOSHIBA TMP92CM22 3 3 5 Noise Reduction Circuits Noise reduction circuits are built in for reduction EMI Unnecessary radius noise and r
176. lse Width 2 4 kbps 78 13 us 88 55 9 6 kbps 19 53 us 22 13 us 115 2 The infra red pulse width is specified either baud rate T x 3 16 or 1 6 us 1 6 us is equal to T x 3 16 pulse width when baud rate is 115 2 kbps The TMP92CM22 has function which is selectable the transmission pulse width either 3 16 or 1 16 But T x 1 16 pulse width can be selected when the baud rate is equal or less than 38 4 kbps only When 57 6 kbps and 115 2 kbps the output pulse width should not be set to T x 1 16 92CM22 170 2007 02 16 TOSHIBA TMP92CM22 As same reason 16 K 16 division function in the baud rate generator of SIOO cannot be used to generate 115 2 kbps baud rate Also when the 38 4 kbps and 1 16 pulse width 16 K 16 division function cannot be used Table 3 9 5 shows baud rate and pulse width for 16 K 16 division function Table 3 9 5 Baud Rate and Pulse Width for 16 K 16 Division Function Output Pulse Baud Rate fne dL e MI Eee nane qp se Pe Can be used 16 K 16 division function x Cannot be used 16 K 16 division function Cannot be set to T x 1 16 pulse width od 7 6 5 4 3 2 j t SIRCR Bit symbol PLSEL RXSEL TXEN RXEN SIRWD3 SIRWD2 SIRWD1 SIRWDO 1207 Read Write R W ME MM SES s po 1 Ah Function Selection Receiving Transmission Receiv
177. lt register Internal data bus AD Channel converter selector AD read ADTRG only PG3 Figure 3 5 30 Port G Port G Register poer pe pese dome sg qum Bit symbol Data from external port Note The input channel selection of AD converter and the permission of ADTRG input are set by AD converter mode register ADMOD1 Figure 3 5 31 Register for Port G 92CM22 77 2007 02 16 TOSHIBA TMP92CM22 3 6 Memory Controller 3 6 1 Function TMP92CM22 has a memory controller with a variable 4 block address area that controls as follows 1 4 block address area support Specifies a start address and a block size for 4 block address area 2 Connecting memory specifications Specifies SRAM and ROM as memories to connect with the selected address areas 3 Data bus size selection Whether 8 bit or 16 bit is selected as the data bus size of the respective block address areas 4 Wait control Wait specification bit in the control register and WAIT input pin control the number of waits in the external bus cycle Read cycle and write cycle can specify the number of waits individually The number of waits is controlled in 6 mode mentioned below 0 waits 1 wait 2 waits 3 waits 4 waits N waits Control with WAIT pin 92CM22 78 2007 02 16 TOSHIBA TMP92CM22 3 6 2 Control Register and Operation after Reset Release This section describes the register
178. lue set if the latter is higher the interrupt is accepted Then the CPU sets a value higher than the priority value by 1 1 in the CPU SR lt IFF2 0 gt Interrupt request where the priority value equals or is higher than the set value are accepted simultaneously during the previous interrupt routine When interrupt processing is completed after execution of the RETI instruction the CPU restores the priority value saved in the stack before the interrupt was generated to the CPU SR lt IFF2 0 gt The interrupt controller also has registers 8 channels used to store the micro DMA start vector Writing the start vector of the interrupt source for the micro DMA processing See Table 3 4 1 enables the corresponding interrupt to be processed by micro DMA processing The values must be set in the micro DMA parameter register e g DMAS and DMAD prior to the micro DMA processing 92CM22 38 2007 02 16 TMP92CM22 TOSHIBA uoneoyioeds jauueyo oN 0 Z ddl 1senbei YG 901 Buung dal lt 0 01 19 epis U jdnueju Jepooue Jeuueuo YING peal 2 S ysay6iH 129Jes 01 euis 1senbei HOdJ
179. m illustrates this mode TBORUN lt TBORUN gt TBOOUTO PPG output Selector F F 1 bi 16 bit up counter TBOFFO UC10 TBORGO WR Register buffer 10 TBOREG1H L TBORUN lt TBORDE gt Internal data bus Figure 3 8 11 Block Diagram of 16 Bit PPG Mode The following example shows how to set 16 bit PPG output mode TBORUN 00 Disable the TBORGOH L double buffer and stop TMRBO TBORGOH L lt Set the duty ratio 1 6 bits TBORG1H L lt Set the frequency dk C SE 1 6 bits TBORUN lt 10 X X 0x0 Enable the TBORGO double buffer The duty and frequency are changed on an INTTBO1 interrupt TBOFFCR X X00 1 11 0 Set the mode to invert TBOFFO at the match with TBORGOH L TBORG1H L Clear TBOFFO to 0 TBOMOD 001001 Set input clock to prescaler output clock and disable the capture function 01 10 11 PCCR X 1 X X PCFC X 1 X X TBORUN 10 X X 1 X Don t No change Set PC6 to function as TBOOUTO X 1 Start TMRBO 92CM22 135 2007 02 16 TOSHIBA TMP92CM22 4 Capture function examples Used capture function they can be applicable in many ways for example 1 One shot pulse output from external trigger pulse 2 Frequency measurement 3 Pulse width measurement 4 Measurement of difference time 1 One shot pulse output from external trigger pulse
180. mes stable after power on reset Figure 3 1 1 shows the timing of a reset for the TMP92CM22 92CM22 8 2007 02 16 TOSHIBA TMP92CM22 Voc 3 3 V iS 1 Oscillator 0 s Min operation time 20 system clocks Figure 3 1 1 Reset Timing Example 3 1 3 Outline of Operation Mode Set AM1 and AMO pins to 10 to use 8 bit external bus or set it to 01 to use 16 bit external bus Table 3 1 2 Operation Mode Setup Table Mode Setting Input Pin M 8 16 bit dynamic bus sizing 8 16 bit dynamic bus sizing 92CM22 9 2007 02 16 TOSHIBA TMP92CM22 3 2 Memory Figure 3 2 1 shows memory map of TMP92CM22 000000H Direct area n 000100H ___ 001 002000H 64 Kbyte area Internal RAM nn 32 Kbytes 00A000H 010000H External memory F00000H Provisinal emulator control area 4K F10000H External memory 16 Mbyte area R R R8 16 R d8 16 nnn FFFFOOH Vector table 256 bytes FFFFFFH Internal area Figure 3 2 1 Memory Map Note 1 When use emulator optional 64 Kbytes of 16 Mbyte area are used to control emulator Therefore don t use this area Note 2 Don t use the last 16 byte area FFFFFOH to FFFFFFH This area is reserved Note 3 On emulator signal wRLU signal and RD signal are asserted when provisional emulator control area is accessed Be careful to use extend me
181. modify write instruction Figure 3 8 8 Register for TMRB 92CM22 132 2007 02 16 TOSHIBA TMP92CM22 3 8 4 X Operation in Each Mode 1 16 bit interval timer mode Generating interrupts at fixed intervals 1n this example the interval time is set the timer register TBORG1H L to generate the interrupt INTTBO1 6543210 TBORUN lt 00 X 0x0 Stop TMRBO INTETBO X100x000 Enable 01 and set interrupt level 4 Disable INTTBOO TBOFFCR lt 1 10000 1 1 Disable the trigger TBOMOD 001001 Set input clock to prescaler clock and set capture function 01 10 11 to disable TBORG1 lt Set the interval time de cie lie COR 1 6 bits TBORUN lt 00X X 1X 1 Start TMRBO X Don t care No change 2 16 bit event counter mode In 16 bit timer mode as described in above the timer can be used as an event counter by selecting the external clock TB1INO pin input as the input clock Up counter counting up by rising edge of TB1INO pin input And execution software capture and reading capture value enable reading count value 76543210 TB1RUN 00 X 0x0 Stop TMRB1 PDCR 0 Set PDO to TB1INO input mode PDFC X XXX 1 INTETB1 X100x000 Set INTTB11 to enable Interrupt level4 Set INTTBOO to disable TBIFFCR 110000 1 1 Set trigger to disable TB1MOD 00100100 Set input clock to TB11NO pin input TB1RG1 e gel e Set
182. mory 92CM22 10 2007 02 16 TOSHIBA 3 3 Clock Function and Standby Function TMP92CM22 92 22 contains 1 Clock gear 2 Standby controller and 3 Noise reducing circuit It 1s used for low power low noise systems This chapter 1s organized as follows 3 3 1 Block Diagram of System Clock 8 8 2 SFRs 3 3 3 System Clock Controller 3 3 4 Clock Doubler PLL 3 3 5 Noise Reduction Circuits 3 3 6 Standby Controller 92CM22 11 2007 02 16 TOSHIBA TMP92CM22 The clock operating modes are as follows a Single clock mode X1 and X2 pins only b Dual clock mode X1 X2 pins and PLL Figure 3 3 1 shows a transition figure Reset foscH 32 Release reset Instruction IDLE2 mode I O operation IDLE1 mode Operate only oscillator NORMAL mode Instruction Instruction fosci gear value 2 Interrupt STOP mode Stop all circuit a Single clock mode transition figure Reset foscH 32 Release reset IDLE2 mode Instruction operation NORMAL mode Instruction IDLE1 mode Instruction foscH gear value 2 Interrupt Operate only oscillator Instruction STOP mode Stop all circuit Instruction IDLE2 mode I O operation IDLE1 mode Operate oscillator and PLL NORMAL mode Instruction 4 x foscu gear value 2 Using PLL b Dual clock mode transition figure Figure
183. mpared or not is set to register Note When the set block address area overlaps with the built in memory area or both two address areas overlap the block address area is processed according to priority as follows Built in gt Built in memory gt Block address area 0 gt 1 gt 2 3 CSEX Also that any accessed areas outside the address spaces set by CSO to CS3 are processed as the CSEX space Therefore settings of CSEX apply for the control of wait cycles data bus width etc 92CM22 81 2007 02 16 TOSHIBA 2 3 TMP92CM22 Connection memory specification Setting the BnOM1 to BnOMO bit of the control register BnCSH specifies the memory type to be connected with the block address areas The interface signal is output according to the set memory as follows TMP92CM22 prohibit changing default SRAM ROM BnOM1 BnOMO Bit BnCSH ae e Dead ae m Reseved eee SS ae SEES ee ese Reserved Data bus width specification The data bus width is set for every block address area The bus size is set by the BnBUS1 and 050 bits of the control register as follows BnBUS Bit BnCSH dele po foetus mode peau eee Reserved Reserved This way of changing the data bus size depending on the address being accessed 15 called dynamic bus sizing The part where the data is output to is depended on the data size the bus width and the start address Note
184. nal data bus Internal data bus AD mode control register 1 AD mode control register 0 ADMODO ADMOD1 lt ADTRGE gt lt ADCH2 0 gt lt VREFON gt rend selection rend circuit AD conversion result register ADREGOL to ADREG7L lt EOCF gt lt ADBF gt lt ITM0 gt lt REPEAT gt lt SCAN gt lt ADS gt Multiplexer to ADREG7H Comparater Figure 3 11 1 Block Diagram of AD Converter 92CM22 199 2007 02 16 TOSHIBA TMP92CM22 3 11 1 Analog Digital Converter Registers The AD converter is controlled by the three AD mode control registers ADMODO ADMODI ADMOD2 The eight AD conversion data result registers ADREGOH L to ADREG7H L store the results of AD conversion Figure 3 11 2 shows the registers related to the AD converter AD Mode Control Register 0 po m ow o3 3 neamme SOSS Function Always Interrupt Repeat Scan mode conversion conversion rite 0 specification mode specification conversion end flag busy flag w 1 Specification 0 Conversion start 0 Conversion 0 Conversion i 0 Single channel 0 Don t care in progress stopped gt conversion fixed mode 1 Start 1 Conversion 1 Conversion 1 Repeat 1 Conversion Conversion complete in progress conversion channel Always 0 when conversion scan mode 1 Every fourth conversion AD conversion sta
185. ng as slave device Address modify write recognition instruction is mode prohibited specification Address recognition mode specification Slave address recognition Non slave address recognition Figure 3 10 6 Register for Bus Mode 92CM22 177 2007 02 16 TOSHIBA TMP92CM22 3 10 5 Control in Bus Mode 1 Acknowledge mode specification 2 3 Set the SBIOCR1 lt ACK gt to 1 for operation in the acknowledge mode The TMP92CM22 generates an additional clock pulse for an acknowledge signal when operating in master mode In the transmitter mode during the clock pulse cycle the SDA pin is released in order to receive the acknowledge signal from the receiver In the receiver mode during the clock pulse cycle the SDA pin is set to the low in order to generate the acknowledge signal Clear the lt gt to 0 for operation in the non acknowledge mode the TMP92CM22 does not generate a clock pulse for the acknowledge signal when operating in the master mode Select number of transfer bits The SBIOCR1 lt BC2 0 gt is used to select a number of bits for next transmission receiving data Since the lt BC2 0 gt is cleared to 000 as a start condition a slave address and direction bit are transferred in 8 bits Other than these the BC2 0 retains a specified value Serial clock 1 Clock source The SBIOCR1 SCK2 0 is used to select maximum transfer frequency outputted on the SCL pin in master m
186. nt configuration from the others BnCSL EC E oH ETE Exp e 1 ReadWrite aerer o coser posee ei BnWWY 2 0 Specifies the number of write waits 001 2 states 0 waits access 010 3 states 1 wait access 101 4 states 2 waits access 110 5 states 3 waits access 111 6 states 4 waits access 011 2 WAIT pin input mode Others Reserved BnWR 2 0 Specifies the number of read waits 001 2 states 0 waits access 010 3 states 1 wait access 101 4 states 2 waits access 110 5 states 3 waits access 111 6 states 4 waits access 011 WAIT pin input mode Others Reserved B2CSH S ETSI BT ONES Pw pierres vae np EGRE ID une 2 Enable bit 0 No chip select signal output 1 Chip select signal output Default Note After reset release only the enable bit B2E of B2CSH register is valid 1 B2M Specifies the block address area 0 Sets the block address area of CS2 to addresses 000000H to FFFFFFH Default 1 Sets the block address area of CS2 to programmable Note After reset release the block address area 2 is set to addresses 000000H to FFFFFFH 92CM22 91 2007 02 16 TOSHIBA TMP92CM22 B2REC Sets the dummy cycle for data output recovery time 0 Not insert a dummy cycle Default 1 Insert a dummy cycle B20N 1 0 00 SRAM or ROM Default Others Reserved B2BUS 1 0 Set
187. ntrol register 0 or ADMOD1 lt ADTRGE gt in AD mode control register 1 and input falling edge ADTRG pin When AD conversion starts the AD conversion busy flag lt gt will be set to 1 indicating that AD conversion is in progress AD conversion modes and the AD conversion end interrupt The four AD conversion modes are Channel fixed single conversion mode Channel scan single conversion mode Channel fixed repeat conversion mode Channel scan repeat conversion mode The ADMODO lt REPEAT gt and ADMODO lt SCAN gt settings in AD mode control register 0 determine the AD mode setting Completion of AD conversion triggers an INTAD AD conversion end interrupt request Also lt gt will be set to 1 to indicate that AD conversion has been completed 1 Channel fixed single conversion mode Setting ADMODO lt REPEAT gt and lt gt to 00 selects conversion channel fixed single conversion mode In this mode data on one specified channel is converted once only When the conversion has been completed the ADMODO lt EOCF gt flag is set to 1 lt gt is cleared to 0 and an INTAD interrupt request is generated 2 Channel scan single conversion mode Setting ADMODO lt REPEAT gt and lt gt to 01 selects conversion channel scan single conversion mode In this mode data on the specified scan channels is converted
188. number of count 16 bits TB1RUN lt 00 XX 1 X 1 Start TMRB1 X Don t care No change Note When used as an event counter set the prescaler to RUN TB1RUN TB1PRUN 1 92CM22 133 2007 02 16 TOSHIBA TMP92CM22 3 16 bit programmable pulse generation PPG output mode Square wave pulses can be generated at any frequency and duty ratio The output pulse may be either low active or high active The PPG mode is obtained by inversion of the timer flip flop TBOFFO that is to be enabled by the match of the up counter UC10 with timer register TBORGOH L or TBORG1H L and to be output to TBOOUTO In this mode the following conditions must be satisfied Set value of TBORGOH L lt Set value of TBORG1H L Match with TBORGOH L INTTBOO interrupt Match with TBORG1H L INTTBO 1 interrupt TBOOUTO pin Figure 3 8 9 Programmable Pulse Generation PPG Output Waveforms When the TBORGOH L double buffer is enabled in this mode the value of register buffer 10 will be shifted into TBORGOH L at match with TBORGI1H L This feature makes easy the handling of low duty waves Match with TBORGOH L 1 Up counter Q2 Match with TBORG1H L Shift in to TBORG1H L TBORGOH L Compare value Z Register buffer 10 Q2 Q3 Write TBORGOH L Figure 3 8 10 Operation of Register Buffer 92CM22 134 2007 02 16 TOSHIBA TMP92CM22 The following block diagra
189. o D7 P1 D8 to D15 A0 to A7 P5 8 to A15 P6 A16 to A23 P76 WAIT PD2 TB10UTO PD3 TB10UT1 PF6 and PF7 Output data P ch Output enable Stop N ch Input data Input enable P90 SCR PCO TAOIN PC1 TA1OUT INT1 INTO PC5 TASOUT INT2 6 TBOOUT INT3 PDO INT4 TB1INO PD1 NT5 TB1IN1 PF1 RXDO SCLKO CTSO0 4 RXD1 and PF5 SCLK1 CTS1 VCC Output data Bich Output enable Stop Input data mile Input enable 92CM22 251 2007 02 16 TOSHIBA TMP92CM22 m P70 RD P71 WRLL P72 WRLU P73 CLKOUT P75 R W P80 CSO P81 CS1 P82 CS2 and P83 CS3 VCC Output data P ch Output Stop N ch m PA2 and VCC Input Input data m P91 SO SDA and P92 SI SCL Output data Open drain output enable Stop Input data Input enable 92 22 252 2007 02 16 TOSHIBA TMP92CM22 m PFO TXDO and TXD1 VCC Output data P ch Open drain output enable N ch Stop Input data Input enable m ANO PG1 AND PG2 AN2 AN3 ADTRG PG4 PG5 AN5 PG6 AN6 and AN7 Analog input channel select P ch Analog input Input N ch Input data Input enable VCC 100 kQ Typ RESET Input Schmitt WDTOUT Reset enable 92CM22 253 2007 02 16 TOSHIBA m XI and X2 Clock Oscillator High frequency oscillation enable
190. ode Set the baud rates which have been calculated according to the formula below to meet the specifications of the bus such as the smallest pulse width of tLow tHIGH tLOW tLow 2 SBIOCR1 lt SCK2 0 gt 2 fsgi fscl 1 tHiGH _ fsBI 2748 5 5 6 7 8 9 Note fsg shows fsys Figure 3 10 7 Clock Source 92CM22 178 2007 02 16 TOSHIBA Internal SCL output Master A Internal SCL output Master B SCL line TMP92CM22 Clock synchronization In the bus mode in order to wired AND a bus a master device which pulls down a clock line to low level in the first place invalidate a clock pulse of another master device which generates a high level clock pulse The master device with a high level clock pulse needs to detect the situation and implement the following procedure The TMP92CM2z2 has a clock synchronization function for normal data transfer even when more than one master exists on the bus The example explains the clock synchronization procedures when two masters simultaneously exist on a bus Wait counting high level width of a clock pulse w Start couting high level width of a clock pulse Reset a counter of high level width of 1 1 1 1 b Figure 3 10 8 Clock Synchronization As master pulls down internal SCL output to the low level at point the SCL line of the bus becomes the low l
191. ode Control Regsiter SIO and SC1MOD1 92CM22 160 2007 02 16 TOSHIBA TMP92CM22 3 9 4 Operation in Each Mode 1 Mode 0 I O interface mode This mode allows an increase in the number of I O pins available for transmitting data to or receiving data from an external shift register This mode includes the SCLK output mode to output synchronous clock SCLK and SCLK input mode to input external synchronous clock SCLK Output extension Input extension TMP92CM22 Shift register TMP92CM22 Shift register A lt lt gt lt D D lt E lt gt lt H gt lt TC74HC595 or equivalent TC74HC165 or equivalent Figure 3 9 17 Example of SCLK Output Mode Connection Output extension Input extension TMP92CM22 Shift register TMP92CM22 Shift register gt lt gt D F lt lt lt TC74HC595 or equivalent TC74HC165 or equivalent External clock External clock Figure 3 9 18 Example of SCLK Output Mode Connection 92CM22 161 2007 02 16 TOSHIBA TMP92CM22 1 Transmission In SCLK output mode 8 bit data and a synchronous clock are output on the TXDO and SCLKO pins respectively each time the CPU writes the data to the transmission buffer When all data is outputted INTESO lt ITX0C gt will be set to generate the INTTXO interrupt Timing of writing transmission data
192. once only When scan conversion has been completed ADMODO lt EOCF gt is set to 1 lt gt is cleared to 0 and an INTAD interrupt request is generated 92CM22 207 2007 02 16 TOSHIBA TMP92CM22 Channel fixed repeat conversion mode Setting ADMODO lt REPEAT gt and ADMOD0 lt SCAN gt to 10 selects conversion channel fixed repeat conversion mode In this mode data on one specified channel is converted repeatedly When conversion has been completed ADMODO lt EOCF gt is set to 1 and lt gt is not cleared to 0 but held at 1 INTAD interrupt request generation timing is determined by the setting of ADMODO ITMO Clearing lt ITMO gt to 0 generates an interrupt request every time an AD conversion is completed Setting lt ITMO gt to 1 generates an interrupt request on completion of every fourth conversion Channel scan repeat conversion mode Setting ADMODO lt REPEAT gt and lt gt to 11 selects conversion channel scan repeat conversion mode In this mode data on the specified scan channels is converted repeatedly When each scan conversion has been completed ADMODO lt EOCF gt is set to 1 and an INTAD interrupt request is generated lt gt is not cleared to 0 but held at 1 To stop conversion in a repeat conversion mode e g in cases c and d program a 0 to ADMODO lt REP
193. ous mode 10 10 bit AD converter 8 channels 11 Watchdog timer 12 Interrupts 41 interrupts 9 CPU interrupts Software interrupt instruction and illegal instruction 25 internal interrupts Seven selectable priority levels 7 external interrupts Seven selectable priority levels INTO to INT5 and NMI INTO to INTS selectable edge or level interrupt 13 Input output ports 50 pins exclude Data bus 8 bit Address bus 24 bit and RD pin 14 Standby function e Three HALT modes IDLE2 Programmable IDLE1 STOP 15 Dual clock controller PLL fe foscH x 4 fe 40 MHz at foscH 10 MHz e Clock gear function Select a high frequency clock fc to 16 16 Operating voltage e DVCC 3 0 V to 3 6 V fc max 40 MHz 17 Package 100 pin QFP P LQFP100 1414 0 50F 92CM22 2 2007 02 16 TOSHIBA to PG7 ANO to AN7 ADTRG AVCC AVSS VREFH VREFL TXDO PF1 RXDO SCLKO CTSo PF3 TXD1 PF4 RXD1 SCLK1 CTS1 PF6 to PF7 P90 SCK P91 SO SDA P92 SI SCL PCO TAOIN PC1 TA1OUT INT1 PC5 2 PC6 TBOOUTO INT3 PDO TB1INO INTA PD1 TB1IN1 INT5 PD2 TB1OUTO TB1OUT1 900 H1 CPU 10 bit 8 ch AD converter 79 H OSC Clock gear Serial I O 500 controller Serial SIO1 Interrupt controller Data bus Port 1 Port 4 Port 5 8 bit timer Timer
194. p Condition Generation Multi master 92CM22 188 2007 02 16 TOSHIBA TMP92CM22 5 Restart SCL bus SCL pin SDA pin LRB BB PIN Restart is used during data transfer between a master device and a slave device to change the data transfer direction The following description explains how to restart when this device is in the master mode Clear the SBIOCR2 lt MST BB to 000 and set the SBIOCR2 lt PIN gt to 1 to release the bus The SDA line remains the high level and the SCL pin is released Since a stop condition is not generated on the bus other devices assume the bus to be in a busy state Check the SBIOSR lt BB gt until it becomes 0 to check that the SCL pin of this device is released Check the lt LRB gt until it becomes 1 to check that the SCL line on a bus is not pulled down to the low level by other devices After confirming that the bus stays in a free state generate a start condition with procedure described in 3 10 6 2 In order to meet setup time when restarting take at least 4 7 us of waiting time by software from the time of restarting to confirm that the bus is free until the time to generate the start condition 0 gt lt MST gt 1 gt lt MST gt 0 gt lt TRX gt 1 2 lt TRX gt 0 BB 1 2 BB 1 2 PIN 1 2 PIN Start condition r Figure 3 10 19 Timing Diagram when Restarting 92CM22 189 2007
195. port function to CS function set need bit of P8FC register to 1 Note When set P82 as CS2 after release reset set function register remain output latch of P82 is 0 P8 lt P82 gt 0 PBFC P82F 1 If set function register PBFC P82F 1 after set output latch of P82 to 1 8 lt 82 gt 1 maybe don t read ROM data during changing from port function to CS2 92CM22 89 2007 02 16 TOSHIBA 3 6 8 Control Page mode TMP92CM22 This section describes ROM page mode accessing and how to set registers ROM page mode is set by the page ROM control register 1 Operation and how to set the registers The TMP92CM22 supports access of the page mode ROM access of the page mode is specified only in block address area 2 ROM page mode is set by the page ROM control register PMEMCR Setting OPGE of the PMEMCR register to 1 sets the memory access of the block address area to ROM page mode access The number of read cycles is set by the lt OPWR1 0 gt bit of the PMEMCR register Note OPWR1 OPWRO Bit PMEMCR register OPWR1 OPWRO Number of Cycle in A Page 0 jtstate n 1 1 1 mode n2 2 2 states n 2 2 2 mode gt 3 wi 3states n 3 3 3 mode n gt 4 Reserved Set the number of waits area using the control register BnCSL in each block address The page size The number of bytes of ROM in the CPU side is s
196. put interface input clock selection Baud rate generator SCLKO pin input Edge selection for SCLKO I O mode Transmits and receivers data on rising edge of 1 Transmits and receivers data on falling edge SCLKO Framing error flag Cleared to 0 Parity error flag when read Overrun error flag Parity addition enables O Disabed Even parity addition check Odd parity Received data bit8 Note As all error flags are cleared after reading do not test only a single bit with a bit testing instruction Figure 3 9 9 Serial Control Register for SIOO and SCOCR 92CM22 156 2007 02 16 TOSHIBA TMP92CM22 prae EE SC1CR Bit SUDO EVEN OERR PERR FERR SCLKS IO E E E Function Received i Parity 1 0 SCLK1 10 Baud rate databit8 addition Overrun Parity Framing generator 0 Disable 1 6 1 1 Enable pin input interface input clock selection Baud rate generator SCLK1 pin input Edge selection for SCKL1 pin I O mode Transmits and receives data on rising edge of owl Transmits and receives data on falling edge of TES Framing error flag Cleared to 0 Parity error flag when read Overrun error flag Parity addition enables O Disabed Even parity addition check Odd parity Received data bit8 Note As all error flags are cleared after reading do not test only a single bit wi
197. r Slave Master Note Writing in this register functions as SBIOCR2 Figure 3 10 5 Register for Bus Mode 92CM22 176 2007 02 16 TOSHIBA TMP92CM22 Serial Bus Interface Baud Rate Register 0 Lo 5 8 pe senno LLL aza reaa w m tne HN Es Ra Read Functi nction modify write 47019 vay 1 instruction is prohibited Operation during IDLE 2 mode o so Serial Bus Interface Baud Rate Register 1 M MM SBIOBR1 Bit symbol we mec mense 9 UI Tq ID modify write Function Internal n clock 0 instruction is 0 Stop prohibited 1 Run Operation during IDLE 2 mode o sod Sirial Bus Interface Data Buffer Register NE NES AE E SBIoDBR 1241H Read Write R Receiving W Transmission After reset Undefined Read Note 1 When writing transmission data start from the MSB Bit7 Receiving data is placed from LSB Bit0 modify write Note 2 SBIODBR can t be read the written data Therefore read modify write instruction e g BIT instruction is instruction is prohibited prohibited Bus Address Registr Bones ea 1242H After reset Ea Re RET A A Read Function Slave address selection for when device is operati
198. r STOP mode depending on the contents of the SYSCR2 lt HALTM1 0 gt register The subsequent actions performed in each mode are as follows a IDLE2 Only the CPU halts The internal I O is available to select operation during IDLE2 mode by setting the following register Table 3 3 1 shows the registers of setting operation during IDLE2 mode Table 3 3 1 SFR Seting Operation during IDLE2 Mode b IDLE1 Only internal oscillator operates STOP internal circuit stop The operation of each of the different HALT modes is described in Table 3 3 2 Table 3 3 2 Each Block Operation in HALT Mode HALT Mode IDLE2 IDLE1 STOP port Keep the state when the HALT Refer Table 3 3 5 Table 3 3 6 instruction is executed TMRA TMRB SIO SBI Selection enable operation Stop block to programmable Except clocked synchronous 8 bit SIO mode for SBI x 5 w 5 92CM22 22 2007 02 16 TOSHIBA TMP92CM22 2 How to release the HALT mode These halt states can be released by resetting or requesting an interrupt The halt release sources are determined by the combination between the states of interrupt mask register lt 2 0 gt and the HALT modes The details for release the halt status are shown in Table 3 3 3 e Released by requesting an interrupt The operating released from the HALT mode depends on the interrupt enabled status When the interrupt request level set before executing t
199. r is 0 The 92 22 detects arbitration lost when transmitting a slave address or data and transfer of word terminates In slave receiver mode the TMP92CM22 receives a slave address or GENERAL CALL for which the value of the direction bit sent from the master is 0 In slave receiver mode the 92 22 Set bit number of single word to terminates receiving word data lt 2 0 gt and read the receiving data from SBIODBR 92CM22 187 2007 02 16 TOSHIBA TMP92CM22 4 Stop condition generation When SBIOSR lt BB gt 1 the sequence for generating a stop condition is started by writing 111 to SBIOCR2 MST TRX PIN 0 to SBIOCR2 lt BB gt Do not modify the contents of SBIOCR2 MST PIN BB until a stop condition has been generated on the bus When the bus s SCL line has been pulled low by another device the TMP92CM22 generates a stop condition when the other device has released the SCL line and SDA pin rising 1 2 lt MST gt 1 gt lt TRX gt 0 gt BB 1 gt PIN SCL SDA pin PIN SBIOSR lt BB gt Reading Figure 3 10 17 Stop Condition Generation Single master 1 gt MST 1 gt TRX 0 gt 1 gt PIN Stop condition Internal SCL The case of pulled low SCL pin by another device SDA pin PIN BB Read Figure 3 10 18 Sto
200. r with setting below The vector shifts to that of INTyyy at the time This is because the priority level of INTyyy is higher than that of INTxxx In the interrupt routine CPU reads the vector of INTyyy because cheking of micro DMA has finished And INTyyy is generated regardless of transfer counter of micro DMA INTxxx level 1 without micro DMA INTyyy level 6 with micro DMA 92CM22 34 2007 02 16 TOSHIBA TMP92CM22 Although the control registers used for setting the transfer source and transfer destination addresses are 32 bits wide this type of register can only output 24 bit addresses Accordingly micro DMA can only access 16 Mbytes the upper eight bits of a 32 bit address are not valid Three micro DMA transfer modes are supported one byte transfers two byte one word transfer and four byte transfer After a transfer in any mode the transfer source and transfer destination addresses will either be incremented or decremented or will remain unchanged This simplifies the transfer of data from memory to memory from I O to memory from memory to I O and from I O to I O For details of the various transfer modes see section 3 4 2 1 detailed description of the transfer mode register Since a transfer counter is a 16 bit counter up to 65536 micro DMA processing operations can be performed per interrupt source provided that the transfer counter for the source is initially set to 0000 Micro DMA processing can be initiat
201. rating the interrupt INTTB11 92CM22 137 2007 02 16 TOSHIBA TMP92CM22 Co unt clock Prescaler output clock __ JUUUUL AE input Load int t ister TB1CPOH L External trigger pulse Ree S Load into capture register 1 gt Generate INTTB11 generate INT4 TB1CP1H L 1 Match with TB1RG1H L 1 1 Timer output TB1OUTO pin Set it to disable that inversion caused by Set it to enable that inversion loading into TB1CP1H L caused by loading into TB1CPOH L Figure 3 8 13 One shot Pulse Output without delay 2 Frequency measurement The frequency of the external clock can be measured in this mode Frequency is measured by the 8 bit timers TMRA23 and 16 bit timer event counter TMRA23 is used to setting of measurement time by inversion TA3FF Counter clock in TMRBO select TB1INO pin input and count by external clock input Set to TB1MOD lt TB1CPM1 0 gt 11 The value of the up counter UC12 is loaded into the capture register TBOCPOH L at the rise edge of the timer flip flop TA1FF of 8 bit timers TMRA1 and into TBOCP1H L at its fall edge The frequency is calculated by difference between the loaded values in TB1CPOH L and when the interrupt INTTA2 or INTTA3 is generates by either 8 bit timer Count clock _ SULA TB11NO pin input Zad C1 C2 TA3FF Load into TB1CPOH L
202. re 3 10 23 Maximum Data Transfer Frequency when External Clock Input 92CM22 192 2007 02 16 TOSHIBA TMP92CM22 2 Shiftedge Data is transmitted on the leading edge of the clock and received on the trailing edge Leading edge shift Data is shifted on the leading edge of the serial clock on the falling edge of the SCK pin input output Trailing edge shift Data is shifted on the trailing edge of the serial clock on the rising edge of the SCK pin input output SCK pin SO pin Shift register SCK pin SI pin Shift register b Trailing shift Don t care Figure 3 10 24 Shift Edge 92CM22 193 2007 02 16 TOSHIBA TMP92CM22 2 Transfer modes The SBIOCR1 lt SIOM1 0 gt is used to select a transmit receive or transmit receive mode 1 8 bit transmit mode Set a control register to a transmit mode and write transmission data to the SBIODBR After the transmit data has been written set the SBIOCR1 lt SIOS gt to 1 to start data transfer The transmitted data 15 transferred from the SBIODBR to the shift register and output starting with the least significant bit LSB via the SO pin and synchronized with the serial clock When the transmission data has been transferred to the shift register the SBIODBR becomes empty The INTSBEO Buffer empty interrupt request is generated to request new data When the internal clock is used the serial clock will stop and the automati
203. refore no need to read it When the transfer mode is changed the contents of the SBIODBR will be lost If the mode must be changed conclude data receiving by clearing the lt SIOS gt to 0 read the last data then change the mode 92CM22 196 2007 02 16 TOSHIBA lt 5105 gt lt SIOF gt lt SEF gt SCK pin Output SI pin INTSEBO interrupt request SBIODBR TMP92CM22 I Clear lt SIos gt Read receive data Read receive data Figure 3 10 27 Receiver Mode Example Internal clock 8 bit transmit receive mode Set a control register to a transmit receive mode and write data to the SBIODBR After the data is written set the SBIOCR lt SIOS gt to 1 to start transmitting receiving When data is transmitted the data is output from the SO pin starting from the least significant bit LSB and synchronized with the leading edge of the serial clock signal When data is received the data is input via the SI pin on the trailing edge of the serial clock signal 8 bit data is transferred from the shift register to the SBIODBR and the INTSBEO interrupt request is generated The interrupt service program reads the received data from the data buffer register and writes the data which is to be transmitted The SBIODBR is used for both transmitting and receiving Transmitted data should always be written after received data is read When the internal clock is used the automatic wait function will be in effect un
204. register setting HALT mode lt DRVE gt lt SELDRV gt IDLE1 STOP e CondtionB Condition 92CM22 28 2007 02 16 TOSHIBA TMP92CM22 3 4 Interrupt Interrupts of TLCS 900 H1 are controlled by the CPU interrupt mask flip flop IFF2 0 and by the built in interrupt controller The TMP92CM22 has a total of 41 interrupts divided into the following types Interrupts generated by CPU 9 sources Software interrupts 8 sources illegal instruction interrupt 1 source External interrupts NMI and INTO to INT5 7 sources Internal I O interrupts 17 sources High speed DMA interrupts 8 sources A individual interrupt vector number Fixed is assigned to each interrupt One of six priority level Variable can be assigned to each maskable interrupt The priority level of non maskable interrupts are fixed at 7 as the highest level When an interrupt is generated the interrupt controller sends the priority of that interrupt to the CPU If multiple interrupts is generated simultaneously the interrupt controller sends the interrupt with the highest priority to the CPU The highest priority is level 7 using for non maskable interrupts The CPU compares the priority level of the interrupt with the value of the CPU interrupts mask register lt IFF2 0 gt If the priority level of the interrupt is higher than the value of the interrupt mask register the CPU accepts the interrupt The interrupt mask regis
205. rement Pulse Width measure by setting 10 to TB MOD lt TB1CPM1 0 gt The external interrupt INT4 is generated in timing of falling edge of TB1INO input In other modes it is generated in timing of rising edge of TB1INO input The width of low level can be measured from the difference between the first C2 and the second C1 at the second INT4 interrupt 92CM22 139 2007 02 16 TOSHIBA Count clock Prescaler output clock TB1INO pin input TB1IN1 pin input Load into TB1CPOH L Load intoTB1CP1H L INT4 INTS TMP92CM22 Measurement of difference time This mode is used to measure the difference in time between the rising edges of external pulses input through TB1INO and 1 Keep the 16 bit timer event counter TMRB1 counting Free running with the prescaler output clock and load the UC12 value into TB1CPOH L at the rising edge of the input pulse to TB1INO Then the interrupt INT4 is generated Similarly the UC012 value is loaded into 1 1 at the rising edge of the input pulse to TB1INI generating the interrupt INT5 The time difference between these pulses can be obtained by multiplying the value subtracted TB1CPOH L from TB1CP1H L and the internal clock cycle together at which loading the UC12 value into TB1CPOH L and TB1CP1H L has been done Difference time Figure 3 8 16 Measurement of Difference Time 92CM22 140 2007 02 16 TOSHIBA TMP92CM22 3 9 Serial Channels SIO The TMP92CM22
206. ress register respectively correspond with addresses A23 to A16 The lower start address A15 to are always set to address 0000H Therefore the start address of the block address area are set to addresses 000000H to FF0000H every 64 Kbytes 1 Setting memory address mask registers The memory address mask register sets whether an address bit is compared or not Set the register to 0 to compare or to 1 not to compare The address bit to be set is depended on the block address area Block address area 0 A20 to A8 Block address area 1 A21 to A8 Block address area 2 to 3 A22 to A15 The above mentioned bits are always compared The block address area size is determined by the compared result The size to be set depending on the block address area is as follows pner qos sp 1 eerte Note After reset release only the control register of the block address area 2 is valid The control register of the block address area 2 has B2M bit Setting lt B2M gt bit to 0 sets the block address area 2 to addresses 000000H to FFFFFFH State of after reset release is set this Setting lt B2M gt bit to 1 specifies the start address and the address area size as it is in the other block addres
207. rogram The watchdog timer begins operating immediately on release of the watchdog timer reset The watchdog timer is halted in IDLE1 or STOP mode The watchdog timer counter continues counting during bus release when BUSAK goes low When the device is in IDLE2 mode the operation of WDT depends on the WDMOD lt I2WDT gt setting Ensure that WOMOD lt I2WDT gt is set before the device enters IDLE2 mode The watchdog timer consists of a 22 stage binary counter which uses the clock 2 0 as the input clock The binary counter can output 215 60 217 0 219 60 and 22 0 WDT counter X 0 interrupt Write clear code WDT clear 0 Software Figure 3 12 2 Normal Mode The runaway detection result can also be connected to the reset pin internally In this case the reset time will be between 22 and 29 system clocks 35 2 to 46 4 us at foscH 40 MHz as shown inFigure 3 12 3 After a reset the fsys clock is frpu 2 where fFPH is generated by dividing the high speed oscillator clock foSCH by sixteen through the clock gear function Overflow WDT counter n X interrupt Internal reset 22 to 29 clocks 35 2 to 46 4 us at foscH 40 MHz Figure 3 12 3 Reset Mode 92CM22 212 2007 02 16 TOSHIBA TMP92CM22 3 12 3 Control Registers The watchdog timer WDT is controlled by two control registers WDMOD and WDCR 1 Watchdog timer mode register WDMOD 1 Setting the detection time for the watchdog tim
208. rol on bit basis PDCR write E Function control on bit basis Output latch 25 PDO INT4 TB11NO PD1 INT5 TB1IN1 5 i Selector Internal address bus PD read INT4 TB1INO INT5 TB1IN1 Note Can not read the output latch data when output mode Figure 3 5 22 Port D PDO and 1 92CM22 70 2007 02 16 TOSHIBA TMP92CM22 2 PD2 TB1OUTO and TB10UT1 In addition to function as I O port port PDO and PD1 can also function as timer channel output pins TB1OUTO and TBIOUT1 Reset Direction control on bit basis PDCR write Internal data bus PD2 TB1OUTO LI TB10UT1 gt PD write TB1O0UTO TB10UT1 Figure 3 5 23 Port D PD2 and PD3 92CM22 71 2007 02 16 TOSHIBA TMP92CM22 Port D Register from external port Output latch register is set to 1 Port D Control Register PDCR ERE 0036H pec eer ree E After reset Function 0 Input uu Input uL Input a Input 1 Output 11 Output 1 Output 1 Output ee D I O setting Fo mu Port D Function Register uc x90 me quiu og ec JL e o o d REESE Read Witte T e Function 0 Port ai Port Port 1 TB1OUT1 1 TBTOUTO 1 TBOIN1 1 TBOINO INT5 Input INT4 Input PD2 output setting asTB1OUTO lt gt PDCR lt PD2C gt output setting as BT
209. rpH The clock frequency that is give by divided by 2 is called fsys One cycle of is referred to as one state 92CM22 255 2007 02 16 TOSHIBA TMP92CM22 2 Points to note a AMO and AMI pins This pin is connected to the VCC Power supply level or VSS Ground level pins Do not alter the level when the pin is active b Reservation area of address area TMP92CM22 don t include reservation area c Warm up counter The warm up counter operates when STOP mode is released even if the system is using an external oscillator As a result a time equivalent to the warm up time elapses between input of the release request and output of the system clock d Watchdog timer The watchdog timer starts operation immediately after a reset is released When the watchdog timer is not to be used disable it AD converter The string resistor between the VREFH and VREFL pins can be cut by a program so as to reduce power consumption When STOP mode is used disable the resistor using the program before the HALT instruction is executed f CPU micro DMA Only the LDC cr r and LDC r cr instructions can be used to access the control registers in the CPU e g the transfer source address register DMASn g Undefined SFR bit The value of an undefined bit in an SFR Special function register is undefined when read h POP SR instruction Please execute the POP SR instruction during DI condition
210. rt Don t care Start AD conversion 1 Note Always read as 0 AD scan mode setting AD conversion channel fixed mode 1 AD conversion channel scan mode AD repeat mode setting AD single conversion mode 1 AD repeat conversion mode Specify AD conversion interrupt for channel fixed repeat conversion mode ES Channel fixed repeat conversion mode SCAN 0 REPEAT 1 Generates interrupt every conversion 1 Generates interrupt every fourth conversion AD conversion busy flag AD conversion stopped AD conversion in progress AD conversion in progress o Before or during AD conversion AD conversion complete Figure 3 11 2 Register for AD Converter 92CM22 200 2007 02 16 TOSHIBA TMP92CM22 AD Mode Control Register 1 a ej s 2syjsy 2 tj 0 varon wo _ RW o o o o Function VREF IDLE2 Analog input channel selection application 0 Stop ADMOD1 12B9H control 0 OFF 1 1 Analog input channel selection 0 1 scanned ANO 1 gt 1 gt AN2 ANO gt gt AN2 gt AN3 Note ANO gt gt AN2 gt AN3 101 Note AN5 ANO gt gt AN2 gt AN3 gt gt 110 Note AN6 ANO gt gt AN2 gt AN3 gt gt 6 111
211. rt vector register The interrupt request flag latches interrupt requests from the peripherals The flag is cleared to 0 in the following cases When reset occurs When the CPU reads the channel vector after accepted its interrupt When executing an instruction that clears the interrupt Write DMA start vector to INTCLR register When the CPU receives a micro DMA request When the micro DMA burst transfer is terminated An interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting register e g INTEOAD or INTE1Q2 6 interrupt priorities levels 1 to 6 are provided Setting an interrupt source s priority level to 0 or 7 disables interrupt requests from that source If interrupt request with the same level are generated at the same time the default priority The interrupt with the lowest priority or in other words the interrupt with the lowest vector value is used to determine which interrupt request is accepted first The 3rd and 7th bits of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred The interrupt controller sends the interrupt request with the highest priority among the simultaneous interrupts and its vector address to the CPU The CPU compares the priority value lt IFF2 0 gt in the status register by the interrupt request signal with the priority va
212. s area 92CM22 80 2007 02 16 TOSHIBA TMP92CM22 Example of register setting set the block address area 1 to 512 bytes from address 110000H set the register as follows MSAR1 Register pote uie a 28 Settingvaue 1 1 M1823 to 1516 bits of memory start address register MSAR1 correspond with address A23 to A16 15 to AO are cleared to 0 Therefore setting MSARI to the above mentioned value specifies the start address of the block address area to address 110000H The start address is set as it is in the other block address areas 1 Register reed ems www o o 9 o o 1 1 21 to M1V16 and M1V8 bits of the memory address mask register 1 set whether address A21 to A16 and A8 are compared or not Set the register to 0 to compare or to 1 not to compare A23 and A22 are always compared Setting the above mentioned compares A23 to A9 with the values set as the start addresses Therefore 512 bytes of addresses 110000H to 1101FFH are set as the block address area 1 and compared with the addresses on the bus If the compared result is a match the chip select signal CS1 is set to low The other block address area sizes are specified like this Similarly A23 is always compared in block address areas 2 to 3 Whether A22 to A15 are co
213. s register SBIOSR Serial bus interface 0 baud rate register 0 SBIOBRO Serial bus interface 0 baud rate register 1 SBIOBR1 The above registers differ depending on a mode to be used Refer to Section 3 10 4 2 Bus Mode Control Register and 3 10 7 Clocked synchronous 8 Bit SIO Mode Control 3 10 3 Data Format in Bus Mode Data format in I2C bus mode is shown Figure 3 10 3 a Addressing format 8 bits gt 1 e 1 to 8 bits gt 1 1 to 8 bits 1 5 Slave address Data C Data C k b Addressing format with restart k 8 bits gt 1 k 1 to 8 bits 5 1 8 bits gt 1 J 1 to 8 bits 1 RJA A 5 Slave address Data 5 Slave address Data C K 1 56 4 k 1 C Free data format transfer format transfer from master device to slave device e 8 bits 1 k 1 to 8 bits 5 1 k 1 to 8 bits 1 A A A S Slave address C Data C Data C K K K 1 11 or more S Start condition R W Direction bit Acknowledge bit P Stop condition Figure 3 10 2 Data Format in Bus Mode 92CM22 173 2007 02 16 TOSHIBA TMP92CM22 3 10 4 Bus Mode Control Register The following registers are used to control and monitor the operation status when using the serial
214. s the data bus width 00 8 bits Default 01 16 bits 10 Reserved 11 Reserved Note The value of B2BUS bit is set according to the state of AM 1 0 pin after reset release BnCSH 0 1 3 Bit symbol SAA ee LANES S S S fk perit prm pow pese Tm BnE Enable bit 0 No chip select signal output Default 1 Chip select signal output Note After reset release only the enable bit 2 of B2CSH register is valid 1 BnREC Sets the dummy cycle for data output recovery time 0 Not insert a dummy cycle Default 1 Insert a dummy cycle BnON 1 0 00 SRAM or ROM Default 01 Reserved 10 Reserved 11 Reserved BnBUS 1 0 Sets the data bus width 00 8 bits Default 01 16 bits 10 Reserved 11 Reserved 92CM22 92 2007 02 16 TOSHIBA TMP92CM22 BEXCSL ee Pa Z w BeadW te o W _ Arem oec ug spo ae BEXWW 2 0 Specifies the number of write waits 001 2 states 0 waits access 010 3 states 1 wait access 101 4 states 2 waits access 110 5 states 3 waits access 111 6 states 4 waits access 011 WAIT pin input mode Others Reserved BEXWR 2 0 Specifies the number of read waits 001 2 states 0 waits access 010 3 states 1 wait access 101 4 states 2 waits access 110 5 states 3 waits access 111 6 states 4 waits access 011 2 WA
215. s to control the memory controller the state after reset release and necessary settings 1 Control register The control registers of the memory controller are as follows e Control register BnCSH BnCSL 0 to 3 EX Sets the basic functions of the memory controller that is the connecting memory type the number of waits to be read and written e Memory start address register MSARn n 0 to 3 Sets a start address in the selected block address areas e Memory address mask register MAMRn n 0 to 3 Sets a block size in the selected address areas In addition to setting of the above mentioned registers it is necessary to set the following registers to control ROM page mode access e Page ROM control register PMEMCR Sets to executed ROM page mode accessing 2 Operation after reset release The start data bus width is determined depending on state of 1 and AMO pins just after reset release Then the external memory is accessed as follows Start Mode rs is sting ___ Pp 1 Statwith 16 bit data bus cen Start with 8 bit data bus Don t use this setting pins are valid only just after reset release In the other cases the data bus width is set to the value set to BnBUS bit of the control register By reset only control register B2CSH B2CSL of the block address area 2 is automatically effective B2CSH lt B2E gt is set to 1 by reset The data bus width which is
216. s2wwe sewwi __ ______ ewe 0148H Read Write B2CSH Bitsymbol 2 B20M B2OMO B2BUSi B2BUSO O Ow y O 0149H Read Write LARerreset 1 0 omw MAMR2 014AH Read Write MSAR2 014BH Read Write R W aterese IT 1 1 1 LLLI Bacs Bit symbol Bowne sowat Readwite fe ee Bae B3BUSO 014DH Read Write After reset 0 o Note o Noe o MAMR3 014EH Read Write R W ECCE ESSE ENSE EINE SCA ENS EE 014FH Read Write DU OR SEI MR UNE BEXCSH Bit symbol_ gt BEXBUS1 BEXBUSO 0159H rr BEXCSL 0158H PMEMCR 0166H Note1 Always write 0 Note2 Read modify write instruction is prohibited for BnCSL BnCSH registers 0 to 3 EX 92CM22 96 2007 02 16 TOSHIBA TMP92CM22 3 6 6 Caution If the parasitic capacitance of the read signal Output enable signal is greater than that of the chip select signal it 15 possible that an unintended read cycle occurs
217. set lt gt is initialized to 0 92CM22 20 2007 02 16 TOSHIBA TMP92CM22 3 Runaway provision with SFR protection register Purpose Provision in runaway of program by noise mixing Write operation to specified SFR is prohibited so that provision program in runaway prevents that is in the state which is fetch impossibility by stopping of clock memory control register Memory controller is changed And error handling in runaway becomes easy by INTPO interruption Specified SFR list 1 Memory controller BOCSL H B1CSL H B2CSL H B3CSL H BEXCSL H MSARO MSAR1 MSAR2 MAMRO MAMR1 MAMR2 and PMEMCR 2 Clock gear EMCCR1 EMCCR2 write enable SYSCRO SYSCR1 SYSCR2 EMCCRO Operation explanation Execute and release of protection write operation to specified SFR becomes possible by setting up a double key to EMCCR1 and EMCCR2 registers Double key 1st KEY Succession writes in at EMCCR1 and at EMCCR2 2nd KEY Succession writes in at EMCCR1 and at EMCCR2 A state of protection can be confirmed by reading EMCCRO lt PROTECT gt By reset protection becomes OFF And INTPO interruption occurs when write operation to specified SFR was executed with protection on state 92CM22 21 2007 02 16 TOSHIBA TMP92CM22 3 3 6 X Standby Controller 1 HALT modes When the HALT instruction is executed the operating mode switches to IDLE2 IDLE1 o
218. slave controller receives above frame If it matches with own select code clears WU bit to 0 5 The master controller transmits data to the specified slave controller whose SCOMODO WU bit is cleared to 0 The MSB Bit8 lt 8 gt is cleared to 0 6 The other slave controllers whose lt WU gt bits remain at 1 ignore the received data because their MSB Bit8 or lt 8 gt are set to 0 disabling INTRXO interrupts The slave controller lt WU gt bit 0 can transmit data to the master controller and it is possible to indicate the end of data receiving to the master controller by this transmission 92CM22 167 2007 02 16 TOSHIBA TMP92CM22 Example To link two slave controllers serially with the master controller using the system clock fjo as the transfer clock Select code Select code 00000001 00001010 e Master controller setting Main routine PFCR lt lt INTESO 1100 1 SCOMODO lt 1 0 1 0 1 SCOBUF 00 0 0 Interrupt routine INTTXO SCOMODO lt 0 0 1 X Set to TXDO and set PF1 to RXDO pin SCOBUF lt Slave setting Main routine PFCR INTESO 1 10 1 1 SCOMODO 0 0 1 1 1 Interrupt routine INTRXO lt SCOBUF if Select code 01 Set INTTXO to enable and set interrupt level to level 4 Set INTRXO to enable and set interrupt level to level 5 10 Se
219. specified by AM1 AMO pin is loaded to the bit to specify the bus width of the control register in the block address area 2 The block address area 2 is set to address 000000 to FFFFFFH by reset After reset release the block address areas are specified by the memory start address register MSAR and the memory address mask register MAMR Then the control register BnCS is set Set the enable bit BnE of the control register to 1 to enable the setting 92CM22 79 2007 02 16 TOSHIBA TMP92CM22 3 6 3 Basic Functions and Register Setting In this section setting of the block address area the connecting memory and the number of waits out of the memory controller s functions are described 1 Block address area specification The block address area is specified by two registers The memory start address register MSAR sets the start address of the block address areas The memory controller compares between the register value and the address every bus cycles The address bit which is masked by the memory address mask register MAMR is not compared by the memory controller The block address area size is determined by setting the memory address mask register The set value in the register is compared with the block address area on the bus If the compared result is a match the memory controller sets the chip select signal CS to low i Setting memory start address register The MS23 to MS16 bits of the memory start add
220. sters of two channels the interrupt generated in the channel with the lower number is executed until micro DMA transfer is completed If the micro DMA start vector for this channel is not set again the next micro DMA is started for the channel with the higher number Micro DMA chaining 92CM22 45 2007 02 16 TOSHIBA _ __ ________________ 7 RN RN NRI DMAOVS 4 DMAOV3 DMAOV2 DMAOV1 DMAOV start iod EE gt vector mcr m start vector buds o oats DMAtV4 DMATV2 DMA1V start 101H R W vector posue o MAT startvector start N Lou 32 5 94 PAR start vector m DMA3 DE ERE R W DMA3V 103H vector DMA2 R W DMA2V 102H start vector pc poseer nts guise PMA start vector 02 o 4 5 DMA4VA 4 4 2 4 DMAAVO DMA4V UE RS UMEN e SFR HELM 4 start vector p owasva omasve vector DMA5 DMA5V start 105H vector es a DVASVO zn sub aor reel o n e sspe ee xy apo s
221. struction after the execution of clearing instruction execute EI instruction after clearing and more than 3 instructions e g NOP x 3 times If placed EI instruction without waiting NOP instruction after execution of clearing instruction interrupt will be enable before request flag is cleared Thus when be changed interrupt request level to 0 change it after cleared corresponding interrupt request by INTCLR instruction In the case of changing the value of the interrupt mask register lt IFF2 0 gt by execution disable an interrupt by DI instruction before execution of POPSR instruction In addition please note that the following two circuits are exceptional and demand special attention In level mode INTO to INT3 are not an edge triggered interrupt Hence in level mode the interrupt request flip flop for INTO to INT3 does not function The peripheral interrupt request passes through the S input of the flip flop and becomes the Q output If the interrupt input mode is changed from edge mode to level mode the interrupt request flag is cleared automatically If the CPU enters the interrupt response sequence as a result of INT x x 0 1 2 or 3 going from 0 to 1 INTx must then be held at 1 until the interrupt response sequence has been completed If INTx is set to Level mode so as to release a Halt state INTx must be held at 1 from the time INTx changes from 010 1 until the Halt state is released Hence it is necessary
222. such as noise When the watchdog timer detects a malfunction it generates a non maskable interrupt INTWD to notify the CPU of the malfunction Connecting the watchdog timer output to the reset pin internally forces a reset The level of external RESET pin is not changed 3 12 1 Configuration Figure 3 12 1 is a block diagram of the watchdog timer WDT WDMOD lt RESCR gt control OG RESET pin 2 Internal reset Interrupt request INTWD WDMOD lt WDTP1 0 gt Selector flo Binary counter 22 Stage Internal reset Internal data bus Figure 3 12 1 Block Diagram of Watchdog Timer Note Care must be exercised in the overall design of the apparatus since the watchdog timer may fail to function correctly due to external noise etc 92CM22 211 2007 02 16 TOSHIBA TMP92CM22 3 12 2 Operation The watchdog timer generates an INTWD interrupt when the detection time set in the WDMOD lt WDTP1 0 gt has elapsed The watchdog timer must be cleared 0 in software before an INTWD interrupt will be generated If the CPU malfunctions e g if runaway occurs due to causes such as noise but does not execute the instruction used to clear the binary counter the binary counter will overflow and an INTWD interrupt will be generated The CPU will detect malfunction runaway due to the INTWD interrupt and in this case it is possible to return to the CPU to normal operation by means of an anti malfunction p
223. t 5105 gt lt SIOF gt 1 1 lt 5 gt o SCK pin Output 1 1 Xas Abo Xb2 Aba Xba Xbe Xo SO pin interrupt request A SBIODBR aX b Writing transmission data a Internal clock i Clear lt SIOS gt a lt 5105 gt 1 lt SIOF gt 1 1 lt SEF gt SCK pin Input J UUUUUUUUUUUUUUUN SO pin Xas Ab Ab Abs Abs Xes interrupt request SBIODBR aX b tu Writing transmission data b External clock Figure 3 10 25 Transmission Mode Example Program to stop data transmission when an external clock is used STEST1 2 SBIOSR If SEF 1 then loop JR NZ STEST1 STEST2 0 P9 If SCK 0 then loop JR Z STEST2 LD 5 0 1 000001118 SIOS 0 92CM22 195 2007 02 16 TOSHIBA Note TMP92CM22 tSODH 3 5 15 6 s Min Figure 3 10 26 Transmission Data Hold Time at End Transmit 8 bit receive mode Set the control register to receive mode and set the SBIOCR1 lt SIOS gt to 1 for switching to receive mode Data is received into the shift register via the SI pin and synchronized with the serial clock starting from the least significant bit LSB When the 8 bit data is received the data is transferred from the shift register to the SBIODBR The INTSBEO Buffer full interrupt
224. t from the clock specified by TBOMOD lt TBOCLK1 0 gt register As the input clock one of the prescaler internal clocks 1 4 and 16 can be selected Counting or stopping and clearing of the counter is controlled by timer operation control register TBORUN TBORUN And an external clock from TB1INO pin can be selected in TB1MOD When clearing is enabled the up counter UC10 will be cleared to zero each time its value matches the value in the timer register TBORG1H L Clearing can be enabled or disabled using TBOMOD lt TBOCLE gt If clearing is disabled the counter operates as a free running counter A timer overflow interrupt INTTBOFO is generated when UC10 overflow occurs 92CM22 123 2007 02 16 TOSHIBA TMP92CM22 3 Timer registers TBORGOH L and TBORG1H L These two 16 bit registers are used to set the interval time When the value in the up counter UC10 matches the value set in this timer register the comparator match detect signal will go active Setting data for both upper and lower timer registers TBORGOH L and TBORG1H L is always needed For example either using 2 byte data transfer instruction or using 1 byte data transfer instruction twice for lower 8 bits and upper 8 bits in order The TBORGOH L timer register has a double buffer structure which 1s paired with register buffer 10 The value set in TBORUN lt TBORDE gt determines whether the double buffer structure is enabled or disabled It is
225. t signal and the other signals is unsettled The timing chart above is an example 92CM22 219 2007 02 16 TOSHIBA TMP92CM22 2 Write cycle 0 waits fc foscH fFPH fc 1 tosc x1 tcyc a tTK WAIT A0 to A23 ee Ws pz 0 gm tww tpw 00 to D31 Data output O RD Note The phase relation between X1 input signal and the other signals is unsettled The timing chart above is an example 92 22 220 2007 02 16 TMP92CM22 TOSHIBA 3 Read cycle 1 wait CLKOUT WAIT to A23 tAD3 JS Q S wo eo 5 4 Write cycle 1 wait L_jJ__ 9 es a eee E ERE Sahel PI 4 5 5 alls EMI Lal c a co N TE o x lt qm s a 2007 02 16 92CM22 221 TOSHIBA TMP92CM22 4 2 2 ROM Read Cycle 1 3 2 2 2 mode Vcc 3 3 0 3 V fc 4 to 40 MHz Ta 40 to 85 No fsys fsys Parameter Symbol Min Max 20 MHz 125 kHz fc 40 MHz fc 4 MHz 2 __ A0 A1 gt DO to D31 input tape zor so so 1590 3_ A2 to 23 gt DO to D31 input 80T 50 100 23950 ns 4 RD falling gt DO to D31 input 25T 45 90 19955
226. t to 9 bit UART mode and set transfer clock to fio 0 1 Set select code of slave 1 Set TB8 to 0 Set transmission data 0 0 Set to TXD open drain output and PC1 to X 1 0 Set and INTRXO to enable 0 Set to WU 1 in 9 bit UART mode transfer clock 0 Clear to WU 0 Then lt 0 SCOMODO 92CM22 168 2007 02 16 TOSHIBA TMP92CM22 3 9 5 Support for IIDA Mode SIOO includes support for the IrDA 1 0 infrared data communication specification Figure 3 9 24 shows the block diagram IR output IR input TMP92CM22 Figure 3 9 24 Block Diagram of IrDA 1 Modulation of transmission data When the transmission data is 0 output H level with either 3 16 or 1 16 times for width of baud rate Selectable in software When data is 1 modem output L level Transmission Start data Output after modulation Figure 3 9 25 Example of Modulation of Transmission Data 2 Modulation of receiving data When the receive data has the effective high level pulse width Software selectable the modem outputs 0 to SIOO Otherwise modem outputs 1 to SIOO Receive pulse logic is selectable by SIRCR lt RXSEL gt Receiving pulse lt RXSEL gt 0 Receiving pulse lt RXSEL gt 1 Data after modulation Figure 3 9 26 Example of Modulation of Receiving Data 92CM22 169 2007 02 16 TOSHIBA TMP92CM22 3 Data
227. tarts the interrupt processing routine When the CPU completed the interrupt processing use the RETI instruction to return to the main routine RETI restores the contents of program counter PC and status register SR from the stack and decreases the interrupt nesting counter INTNEST by 1 1 Non maskable interrupts cannot be disabled by a user program Maskable interrupts however can be enabled or disabled by a user program program can set the priority level for each interrupt source A priority level setting of 0 or 7 will disable an interrupt request If an interrupt request which has a priority level equal to or greater than the value of the CPU interrupt mask register lt IFF2 0 gt comes out the CPU accepts its interrupt Then the CPU interrupt mask register lt IFF2 0 gt is set to the value of the priority level for the accepted interrupt plus 1 1 Therefore if an interrupt is generated with a higher level than the current interrupt during it s processing the CPU accepts the later interrupt and goes to the nesting status of interrupt processing Moreover if the CPU receives another interrupt request while performing the said 1 to b processing steps of the current interrupt the latest interrupt request is sampled immediately after execution of the first instruction of the current interrupt processing routine Specifying DI as the start instruction disables maskable interrupt nesting A reset initializes the interrupt mas
228. ter lt IFF2 0 gt value can be updated using the value of the EI instruction EI num sets lt IFF2 0 gt data to num For example specifying EI3 enables the maskable interrupts which priority level set in the interrupt controller is 3 or higher and also non maskable interrupts Operationally the DI instruction lt IFF2 0 gt 7 is identical to the EI7 instruction DI instruction is used to disable maskable interrupts because of the priority level of maskable interrupts is 1 to 6 The EI instruction is valid immediately after execution In addition to the above general purpose interrupt processing mode TLCS 900 H1 has a micro DMA interrupt processing mode as well The CPU can transfer the data 1 2 4 bytes automatically in micro DMA mode therefore this mode is used for speed up interrupt processing such as transferring data to the internal or external peripheral I O Moreover TMP92CM22 has software start function for micro DMA processing request by the software not by the hardware interrupt Figure 3 4 1 shows the overall interrupt processing flow 92CM22 29 2007 02 16 TOSHIBA General purpose interrupt processing TMP92CM22 Interrupt processing Interrupt Micro DMA specified by Soft start request micro DMA start vector Clear interrupt request flag Data transfer by micro DMA COUNT COUNT 1 ISR IFF2 0 Level of accepted Generating INTTC interrupt 1 interrupt INTNEST lt INTNE
229. teristics 1 2 Vcc 3 3 0 3 V fc 4 to 40 MHz Ta 40 to 85 Parameter Symbol Ooniion Mm Mex Unt Power supply voltage fc 4 to 40 MHz DVCC AVCC 125 kHz to 20 MHz Lx Input low voltage POO to P07 DO to 07 I Input low voltage 40 10 47 P50 to P57 P60 to P67 0 3 x VCC PD2 PD3 PFO PF3 PF6 PF7 PGO to PG7 Input low voltage P90 to P92 to PA2 PA7 PCO PC1 PC5 PC6 yon PDO PD1 PF1 PF4 RESET NMI Input low voltage ViL3 AMO 1 Input low voltage ViLA 2 Input high voltage to P07 DO to D7 20 P10 to P17 D8 to 015 Input high voltage P40 to P47 P50 to P57 P60 to P67 P76 0 7 x PD2 PD3 PF6 PF7 yeu ndr VCC 0 3 V Input high voltage 90 92 2 7 PCO 1 PC5 PC6 2 0 1 PF1 PF2 PF4 Input high voltage 0 Input high voltage 92CM22 216 2007 02 16 TOSHIBA TMP92CM22 DC Characteristics 2 2 Vcc 3 3 0 3 V fc 4 to 40 MHz Ta 40 to 85 C LN Input leakage current 0 0 x Vin lt Output leakage current DER 0 2 lt Vin lt 0 2 Power down voltage V VIL2 0 2 x Vcc at STOP RAM Lor STOP VIH2 0 8 x Vcc RESET RESET pull up res
230. terrupt Interval at fsys 20 MHz 9 1 8 fsys 0 4 us to 102 4 us 4 32 fsys 1 6 us to 409 6 us 16 128 fsys 6 4 us to 1 638 ms 256 2048 fsys 102 4 us to 26 21 ms Note The input clocks for TMRAO and 1 differ as follows TMRAO Uses TMRAO input TAOIN and can be selected from 1 4 or 16 TMRA1 Matches output of TMRAO TAOTRG and can be selected from 1 16 256 92CM22 111 2007 02 16 TOSHIBA TMP92CM22 2 Generating a 5096 duty ratio square wave pulse The state of the timer flip flop 1 is inverted at constant intervals and its status output via the timer output pin TA1OUT Example To output a 2 4 us square wave pulse from the TA1OUT pin at fc 40 MHz use the following procedure to make the appropriate register settings This example uses TMRA1 however either TMRAO or TMRA1 may be used MSB LSB TAO1RUN lt X Stop 1 and clear it to 0 TAO1MOD 0 0 X X 0 1 Select 8 bit timer mode and select 1 16 fc s at fc 40MH2 as the input clock TA1REG lt 000000 1 1 Set the timer register to 2 4 us 1 2 3 TA1FFCR X X X X 1011 Clear TA1FF to 0 and set it to invert on the match detect signal from PCCR X X X 1 PCFC X X X Wo Set PC1 to function as the TA1OUT pin TAO1RUN XXX 1 1 Start TMRA1 counting Don t care No change my qd
231. th a bit testing instruction Figure 3 9 10 Serial Control Register for SIO1 and SC1CR 92CM22 157 2007 02 16 TOSHIBA TMP92CM22 pec amo 255 BROCR Bit symbol BROADDE 1 BROCKO BROS3 BROS2 BROS1 BROSO EN Function Always 16 K 16 00 0 write 0 division 01 2 m 0 Disable 10 T8 Divided frequency setting 1 Enable 11 6732 16 K 16 divisions enable Setting the input clock of baud rate generator Disable 00 jlmtemalcock TO se spen i noa eos s Broe Wear Read Witte gt Function Sets frequency divisor K Divided by N 16 K 16 Sets baud rate generator frequency divisor BROCR lt BROADDE gt 1 BROCR lt BROADDE gt 0 BROCR 0000 N 16 0010 N 2 0001 N 1 UART only BR0S3 0 2 2 BROADD 0001 N 1 1111 N 15 1111 N 15 lt BROK3 0 gt 0000 N 16 0000 NUN Divided by Divided by N N 16 16 1111 15 Availability of 16 K 16 division function FEES UART mode mode The baud rate generator can be set to 1 in UART mode only when the 16 K 16 division function is not used Do not use in
232. the lt TRX gt and determine whether the mode is a transmitter or receiver When the lt gt 1 Transmitter mode Check the lt LRB gt When lt LRB gt is 1 a receiver does not request data Implement the process to generate a stop condition Refer to 3 10 6 4 terminate data transfer When the LRB is 0 the receiver 18 requests new data When the next transmitted data 1s 8 bits write the transmitted data to SBIODBR When the next transmitted data is other than 8 bits set the lt 2 0 gt lt gt and write the transmitted data to SBIODBR After written the data PIN becomes 1 a serial clock pulse is generated for transferring a new 1 word of data from the SCL pin and then the 1 word data is transmitted After the data is transmitted an INTSBE interrupt request generates The PIN becomes 0 and the SCL line is pulled down to the low level If the data to be transferred is more than one word in length repeat the procedure from the lt LRB gt checking above SCL Pin 1 2 3 4 5 6 7 8 9 Write to SBIODBR SDA Pin X X o X D4 X o X m X bi X Do KX Ack n Acknowledge signal from a receive PIN lt INTSBEO request Output of master Output of slave Figure 3 10 14 Example in which BC2 0 000 and lt gt 1 Transmitter mode 92CM22 185 2007 02 16 TOSHIBA SCL line SDA line PIN
233. til the received data is read and the new data is written When the external clock is used since the shift operation is synchronized with the external clock the received data is read and transmitted data is written before a new shift operation is executed The maximum transfer speed when external clock is used is determined by the delay time between the time when an interrupt request is generated and the time at which received data is read and transmitted data is written When the transmit is started after the SBIOSR lt SIOF gt goes 1 output from the SO pin holds final bit of the last data until falling edge of the SCK Transmitting receiving data ends when the lt SIOS gt is cleared to 0 by the INTSBEO interrupt service program or when the SBIOCR1 SIOINH is set to 1 When the lt SIOS gt is cleared to 0 received data is transferred to the SBIODBR in complete blocks The transmit receive mode ends when the transfer is completed In order to confirm whether data is being transmitted received properly by the program set the SBIOSR to be sensed The lt SIOF gt is cleared to 0 when transmitting receiving is completed When the lt SIOINH gt is set to 1 data transmitting receiving stops The lt SIOF gt is then cleared to 0 Note When the transfer mode is changed the contents of the SBIODBR will be lost If the mode must be changed conclude data transmitting receiving by clearing the lt SI
234. tion 0 Port SI 0 Port 1 SCL SCK input Note 1 SCK output Note Port 9 ODE Register eor 0025H Reaarwrte gt ee meme eec en __________________ _____ Note1 Read modify write instruction is prohibited for the registers POCR and Note2 When using SI and input function set P9FC lt P92F P90F gt to 0 Function setting Figure 3 5 15 Register for Port 9 92CM22 64 2007 02 16 TOSHIBA TMP92CM22 3 5 8 Port A to Port Ais 4 bit general purpose input port with pull up resistor Pull up resistor PAO 1 ox pas 7 Internal data bus Figure 3 5 16 Port A Port A Register posco wedge itus p qose Jp oe esame Se eec prse ee e aoe S Data from external port Figure 3 5 17 Register for Port A 92CM22 65 2007 02 16 TOSHIBA TMP92CM22 3 5 9 Port C PCO PC1 PC5 and PC6 Port C is 5 bit general purpose I O port Each bit can be set individually for input output Resetting sets port C to input port In addition to functioning as a general purpose I O port port C can also function as a input output pin TAOIN TA1OUT TA3OUT and TBOOUTO
235. tion edge of external interrupt External interrupt INT5 is fixed to rising edge The value in the up counter UC10 can be loaded into a capture register by software Whenever 0 is programmed to lt gt the current value in the up counter is loaded into capture register TBOCPO It is necessary to keep the prescaler in Run mode e g TBORUN lt TBOPRUN gt must be held at a value of 1 92CM22 125 2007 02 16 TOSHIBA TMP92CM22 6 7 Comparators CP10 and 11 CP10 and CP11 are 16 bit comparators which compare the value in the up counter UC10 with the value set in TBORGOH L or TBORG1H L respectively in order to detect a match If a match is detected the comparator generates an interrupt INTTBOO or 01 respectively Timer flip flop TBOFFO and TBOFF1 These flip flops TBOFFO and TBOFF1 are inverted by the match detect signals from the comparators and the latch signals to the capture registers Inversion can be enabled and disabled for each element using TBOFFCR lt TBOCOT1 TBOE1T1 TBOEOT1 gt After a reset the values of TBOFFO and TBOFF1 are undefined If 00 is programmed to TBOFFCR lt TBOFFO0C1 0 gt or lt TBOFF1C1 0 gt TBOFFO will be inverted If 01 is programmed to the capture registers the value of TBOFFO will be set to 1 If 10 is programmed to the capture registers the value of TBOFFO will be cleared to 0 The values of TBOFFO can be output
236. to 85 C fsys fsys No Parameter Symbol Min Max 20 MHz 125 kHz fc 40 fc 4 MHz tm lose o 3 cxourwswan tw osr w 10 3s rs 57 DiS vaia gt 28 9005 ns DiS vaid rise at wat tows sssr as 17905 61 win ow wan 39 ooo __ no Wi ow wan ws 2 s 17970 rs osr w 1 35 ns Wi CLKOUTfal osr a 5 39 ns o Win se ______ twa omr s 1995 s Wim rise gt Do1 w 1907 s 5 WaT holgtime s 5 rse gt Doro DiS output osre 20 9 vs AC condition Output High 0 7Vcc Low 0 3Vcc C lt 50 pF Input High 0 9Vcc Low 0 1Vcc 92CM22 218 2007 02 16 TOSHIBA TMP92CM22 1 Read cycle 0 waits fc foscH fFPH fc 1 tosc ec ce up 1 tCH 1 1 CLKOUT j i i 1 tk lt 7 WAIT 1 1 1 1 1 1 1 1 i 3 1 1 1 1 CSx 1 R W 1 1 1 1 RD 1 1 1 1 1 1 DO to 031 i i Data input M Note The phase relation between X1 inpu
237. to ADMODI VREFON wait us until the internal reference voltage stabilizes This is not related to fsyg then set ADMODO ADS to 1 Analog input channel selection The analog input channel selection varies depends on the operation mode of the AD converter e In analog input channel fixed mode ADMODO SCAN 0 Setting ADMOD1 lt ADCH2 0 gt selects one of the input pins ANO to AN7 as the input channel In analog input channel scan mode ADMODO0 lt SCAN gt 1 Setting ADMOD1 lt ADCH2 0 gt selects one of the eight scan modes Table 3 11 1 illustrates analog input channel selection in each operation mode On a reset ADMODO lt SCAN gt is set to 0 and ADMOD1 lt ADCH2 0 gt is initialized to 000 Thus pin ANO is selected as the fixed input channel Pins not used as analog input channels can be used as standard input port pins Table 3 11 1 Analog Input Channel Selection Channel fixed Channel scan lt gt 0 SCAN 1 mw o m 100 AN4 ANO gt AN1 gt AN2 gt AN3 gt 101 AN5 gt AN1 gt AN2 gt AN3 gt AN4 gt AN5 110 AN6 ANO gt AN1 gt AN2 gt AN3 gt AN4 gt AN6 111 AN7 ANO gt AN1 gt AN2 AN3 gt AN4 gt AN5 gt AN6 gt AN7 92 22 206 2007 02 16 TOSHIBA 3 4 TMP92CM22 Starting AD conversion To start AD conversion program 1 to ADMODO lt ADS gt in AD mode co
238. to ensure that input noise is not interpreted as a 0 causing INTx to revert to O before the Halt state has been INTO to level mode released When the mode changes from level mode to edge mode interrupt request flags which were set in level mode will not be cleared Interrupt request flags must be cleared using the following sequence DI LD IIMC 00H Changes from level to edge LD INTCLR OAH Clears interrupt request flag NOP Wait El execution NOP NOP EI INTRX The interrupt request flip flop can only be cleared by a reset or by reading the serial channel receive buffer It cannot be cleared by writing INTCLR register Note The following instructions or pin input state changes are equivalent to instructions that clear the interrupt request flag INTO to INT 3 Instructions which switch to level mode after an interrupt request has been generated in edge mode The pin input change from high to low after interrupt request has been generated in level mode H gt L L 5 H INTRX Instruction which read the receive buffer 92CM22 48 2007 02 16 TOSHIBA TMP92CM22 3 5 Function The TMP92CM22 features 50 bit settings which relate to the various ports As well as general purpose I O port functionality the port pins also have I O functions which relate to the built in CPU and internal I Os Table 3 5 1 lists the functions of each port pin Table 3 5 2 and Table 3 5 3 lists
239. troller 5 Clock gear PLL SYSCRO SYSCR1 SYSCR2 EMCCRO 1 EMCCR2 PMEMCR Reserved BEXCSL BEXCSH PLLCR Reserved 92 22 230 2007 02 16 TOSHIBA TMP92CM22 8 bit timer 16 bit timer 8 UART SIO TAO1RUN TAOREG TA1REG 01 TA1FFCR TA23RUN TA2REG TASREG TA23MOD TA3FFCR 9 I2C bus SIO SBIOCR1 SBIODBR l2COAR SBIOCR2 SBIOSR SBIOBRO SBIOBR1 TBORUN TBOMOD TBOFFCR TBORGOL TBORGOH TBORG1L TBORG1H TBOCPOL TBOCPOH TBOCP1L TBOCP1H 10 10 bit ADC ADREGOL ADREGOH ADREGIL ADREG1H ADREG2L ADREG2H ADREGSL ADREG3H ADREG4L ADREG4H ADREGSL ADREG5H ADREG6L ADREG6H ADREG7L ADREG7H TB1RUN TB1MOD TB1FFCR TB1RGOL TB1RGOH TB1RG41L TB1RG1H TB1CPOL TB1CPOH TB1CP1L TB1CP1H ADMODO 1 ADMOD2 Reserved 92CM22 231 SCOBUF SCOCRS COMODO BROCR BROADD SCOMOD1 SIRCR SC1BUF SC1CR SC1MODO BR1CR BR1ADD SC1MOD1 11 WDT 1300H WDMOD 2007 02 16 TOSHIBA 1 I O port 1 3 ases 7 6 5 7 9 U E 7 7 Port 1 Port 4 0004H TMP92CM22 R W Data from external latch is cleared to 0 L R W Data from external port Output latch register is cleared to 0 R W Data from external port Output latch register is cleared to 0 P6 Pes pes pes 262 Pet Peo W Data from external port Output latch register is cle
240. ty bit P Overrun error Center of last bit Center of last bit Center of stop bit generation timing Bit8 Parity bit Note1 In 9 Bits mode and 8 Bits Parity mode interrupts coincide with the ninth bit pulse Thus when servicing the interrupt it is necessary to wait for a 1 bit period to allow the stop bit to be transferred to allow checking for a framing error Note2 The higher the transfer rate the later than the middle receive interrupts and errors occur Transmission Mode 8 Bits Parity 8 Bits 7 Bits Parity 7 Bits Interrupt generation Just before stop bit is timing transmitted 2 In interface mode Transmission SCLK output mode Immediately after last bit data interrupt See Figure 3 9 19 timing SCLK input mode Immediately after rise of last SCLK signal rising mode or immediately after fall in falling mode See Figure 3 9 20 timing SCLK input mode Timing used to transfer received data to receive buffer 2 SCOBUF e g immediately after last SCLK See Figure 3 9 22 Receiving SCLK output mode Timing used to transfer received to data receive buffer 2 SCOBUF interrupt e g immediately after last SCLK See Figure 3 9 21 92CM22 153 2007 02 16 TOSHIBA 3 9 3 SFRs TMP92CM22 SCOMODO Es us 8E 1202H Read Write Transfer data bit8 Function Handshake Receive function control control 0 CTS disable 1 CTS
241. ud Rate Register 1 p ew mpm meme mer o IEEE Read Write eo rr Read a modify write Function _ Internal clock 0 ins ion is 0 Stop prohibited 1 Operate Baud rate clock control Figure 3 10 21 Register for the SIO Mode 92CM22 191 2007 02 16 TOSHIBA TMP92CM22 1 Serial Clock 1 Clock source SBIOCR1 lt SCK2 0 gt is used to select the following functions Internal clock In internal clock mode one of seven frequencies can be selected The serial clock signal is output to the outside on the SCK pin When the device is writing in transmit mode or reading in receive mode data cannot follow the serial clock rate so an automatic wait function is executed which automatically stops the serial clock and holds the next shift operation until reading or writing has been completed Automatic wait SCK pin output 1 J2 3 7 8 1 2 6 7 18 1 2 8 SO pin output Writing transmission data Figure 3 10 22 Automatic Wait Function External clock lt SCK2 0 gt 111 An external clock input via the SCK pin is used as the serial clock In order to ensure the integrity of shift operations both the high and low level serial clock pulse widths shown below must be maintained The maximum data transfer frequency is 1 25 MHz when fsys 20 MHz gt 1 1 1 tSCKL and tSCKH gt 8 fsvs Figu
242. uest level INT3 _ 1 enable INTTA1 TMRA1 INTTAO TMRAO INTTAO amp rR PWT RW enable INTTA3 INTTA2 TMRA2 INTTA2 amp ITA3M2 ITA3M1 ITA3MO ITA2C ITA2M2 ITA2M1 ITA2MO R R W R R W INTETA23 enable mela 4 93 cp INTTBOO RW RW TRE Y 0 enable 1 INTTB1 Interrupt request level 1 INTTBO Interrupt request level INTTBOO INTTBOO TL T 718996 1189096 INTETBOO Overtow w _____ _ enable 1 INTTXO INTRXO INTRXO amp INTESO ooDBH R R W R R W INTTXO enable Eee INTTX1 enable _o 5 S amp INTES oH R w RWC 1 0 11 1 10 1 10 ITB11C ITB11M2 ITB11M1 ITB11MO ITB10C ITB10M2 ITB10M1 ITB10MO INTETBI R AW INTTB11 enable IVRBT NTETBO ____ _ __ _ _ __
243. uffer is written to The address of each timer register is as follows TAOREG 001102H 1 001103H TA2REG 00110AH 00110BH All these registers are write only and cannot be read 92CM22 103 2007 02 16 TOSHIBA 4 5 TMP92CM22 Comparator The comparator compares the value in an up counter with the value set in a timer register If they match the up counter is cleared to 0 and an interrupt signal INTTAO or INTTA1 is generated If timer flip flop inversion is enabled the timer flip flop is inverted at the same time Timer flip flop TA1FF The timer flip flop TA1FF is a flip flop inverted by the match detects signal 8 bit comparator output of each interval timer Whether inversion is enabled or disabled is determined by the setting of the bit 1 lt 1 gt in the timer flip flops control register A reset clears the value of to 0 Programming 01 or 10 to TALFFCR lt TA1FFC1 0 gt sets to 0 or 1 Programming 00 to these bits inverts the value of TAIFF This is known as software inversion The TAIFF signal is output via the TA1OUT pin which can also be used as PC1 When this pin is used as the timer output the timer flip flop should be set beforehand using the port C function register PCFC Note When the double buffer is enabled for an 8 bit timer in PWM or PPG mode caution is required as explained below If new data
244. ulating the baud rate is explained below In UART mode Baud rate External clock input frequency 16 It is necessary to satisfy External clock input cycle gt 4 fsys e interface mode Baud rate External clock input frequency It is necessary to satisfy External clock input cycle gt 16 fsys 92CM22 147 2007 02 16 TOSHIBA TMP92CM22 Table 3 9 3 UART Baud Rate Selection when using baud rate generater and BROCR BROADDE 0 Unit kbps 2 9 8 9 32 fevs fsys 4 16 64 256 Frequency Divider s 4 amp e 080 A 080 394 950 240 060 c y 9a 080 4 7 iae eo 120 3949 950 249 060 4 f ew 24000 600 1500 s 7 amp 8 1200 4e 120 s 4 amp 9 00 999 075 Note 1 Transfer rates in interface mode are eight times faster than the values given above o 8 14 7456 5 gt als In UART mode TMRA match detect signal TAOTRG can be used for serial transfer clock Method for calculating the timer output frequency which is needed when outputting trigger of timer TAOTRG frequency Baud rate x 16 Note The TMRAO match detect signal cannot be used as the transfer clock in Interface mode 92CM22 148 2007 02 16 TOSHIBA TMP92CM22 3 Serial clock generation circuit This circuit

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