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Texas Instruments MSP50C6xx Calculator User Manual

1. mov a0 6553 setup a 200 ms period out TIM2 a0 load TIM2 and PRD2 in one fell swoop mov a0 TIM2ENABLE TIM2REFOSC TIM2IMR out IntGenCtrl a0 use 32 kHz crystal as source wake up from TIM2 out ClkSpdCtrl a0 set clock to full speed idle go to sleep nop wake up 200 ms later clock running at full speed nop nop PRR RRR RR RRR KKK HR KK KKK KKK KEK RAR kk ke RK KKK KKK KK ER KKK KR KKK KEK KEK KKK KK Upon reset all ports are set to input and port G output is set low 0x0000 Therefore it remains only to enable the pullups on pork Es pOCKOKCKCkCk RRR KKK KHER KKK KKK KK RK KK KK KKK KEK KEK RRE RAR RAR RAR RRA RAR in a0 IntGenCtrl or a0 PFPULLUPS enable port F pullups and a0 TIM2IMR turn off TIMER 2 interrupt and a0 TIM2ENABLE turn off TIMER 2 added 28 11 99 out IntGenCtrl a0 pOCKOKCKCKCk kk Ck KKK KK RK KEK KKK KK RK kc kk koc ke kk ke RK KKK k ke kk ke ER KEK koc ke kk ke kk KEK KKK KK Set the DAC to 10 bits C3x style For C5x style set bit 3 high RARE RRS TERRACE RAR SR NON REN TAS RE HER deseo ok ooa OIE BN EN A movb a0 0x02 choose 10 bit DAC C3x style orb a0 DACON enable DAC out DACCTRL a0 switch DAC on p RRR RRR ARRE KK RK KKK KKK KK RK KKK KKK KK RRR KKK KKK KEK KKK koc ke kk ke kc ko KKK KKK KK Initialization complete Now tidy up and branch to the main user code p RRR RRR RRR kk kk ke RK k
2. Program Counter PC T Protection Register PR T Data Pointer DP t MUX String Registert 4 Test Code 7 2k x 17 bit Program Memory Repeat Countert 30k x 17 bit Status Register STAT Macro Calls Flag Registert MSP50C6xx Architecture Figure 2 2 Computational Unit Block Diagram 16 Shift Value SV 16 pas Multiplexer 16 MSB Product High PH Product Low PL 16 LSB 16 Internal Databus 16 bit Computation Unit 2 2 Computation Unit 2 2 1 Multiplier The computational unit CU is comprised of a 17 bit by 17 bit Booth s algorithm multiplier and a 16 bit arithmetic logic unit ALU The block diagram of the CU is shown in Figure 2 2 The multiplier block is served by 4 system registers a 16 bit multiplier register MR a 16 bit write only multiplicand register a 16 bit high word product register PH and a 4 bit shift value register SV The output of the ALU is stored in one 16 bit accumulator from among the 32 which compose the accumulator register block The accumulator register block can supply either one operand to the ALU addressed accumulator register or its offset register or two operands to the ALU both the addressed register and its offset The multiplier executes a 17 bit by 17 bit 2s complement multiply and multiply accumulate in a single instruction cycle The sign bit within each operand is bit 16 and its value extends from bit O LSB to bit 15 MSB
3. TIMER1 Control 0 TIM1 stopped Comparator ENABLE Bit 15 IntGenCtrl 0x38 The comparator along with all of its associated functions is enabled by setting bit 15 of the interrupt general control register IntGenCtrl address 0x38 The default value of the register is zero comparator disabled 1 TIM1 running p Note IntGenCtrl Register Bit 15 At the time that bit 15 in the IntGenCtrl is set PD4 and PDs become the comparator inputs At any time during which bit 15 is set PD4and PD5 MUST be set to INPUT I O Port D Control address 0x1C bits 4 and 5 CLEARed Failure to do so may result in a bus contention D Comparator The function of pins PD4 and PDs and the behavior of events COND2 INT6 INT7 and TIMER1 are different depending on whether the comparator has been enabled or disabled A summary of the various states appears in the fol lowing table Comparator ENABLED SET bit 15 in the IntGenCtrl address 0x38 PDA functions as comparator negative input PDs functions as comparator positive input COND2 maps to the state of the comparator INT6 is triggered by PDs rising above PD4 INT is triggered by PDs falling below PD4 TIMER1 may be started by PDs rising above PD4 TIMER will be stopped by PDs falling below PD4 port D Control 0x1C bit 4 MUST be 0 port D Control 0x1C bit 5 MUST be 0 PDs relative to PD4 IntGenCtrl 0x38 bit 6 must be 1
4. tros rjo os s an ifilo opo a a Description Shift left accumulator string or data memory string pointed at by adrs by nsy bits as specified by the SV register The result is zero filled on the right and either zero filled or sign extended on the left based on the setting of the Extended Sign Mode XM bit in the status register The upper 16 bits are latched into the PH register The result is transferred to the destination accumulator or its offset This instruction propagates the shifted bits to the next accumulator including one accumulator past the string length which receives the same data as PH SHLTPLS An adrs Shift data memory string left transfer result to An SHLTPLS Ar An Shift An string left transfer result to An See Also SHLTPL SHLAPL SHLAPLS SHLSPL SHLSPLS Example 4 14 75 1 SHLTPLS A0 R4 R5 Shift the string pointed by the byte address stored in R4 by nsv bits to the left and store the result in accumulator string AO Add R5 to R4 and store result in R4 After execution of the instruction PH is copied to the next to the last accumulator of the string Example 4 14 75 2 SHLTPLS A2 R1 Shift the string pointed by the byte address stored in R1 by ngy bits to the left and store the result in accumulator string AO Increment R1 by 2 at each execution to get the next memory value Example 4 14 75 3 SHLTPLS A1 A1 Shift the accumulator string A1 by nay bits to the left
5. 3 1 3 Ll Ta Execution dest src PC PC w Flags Affected dest is An OF SF ZF CF are set accordingly dest is Rx RCF RZF are set accordingly dest is adrs XSF XZF are set accordingly src is adrs TAG bit is set accordingly Opcode framectons opeope e 0 To TS 21S 00 E ON meer e a a o dma16 for direct or offset16 long relative see section 4 13 x MOVB acts An jops ojsjo ojo An as x dma16 for direct or offset16 long relative Cisi section 4 13 move anme p epp j ple imma wowwnme hohl him imme move Rx imma 1 ol o a k e ez eje rx xt ko Description Copy value of unsigned src byte to dest byte MOVB An adrs Move data memory byte to Ant MOVB adrs An Move An byte to data memory MOVB An imm8 Move immediate byte to Ant MOVB MR imm8 Move immediate byte to multiply register MR MOVB Rx imma Move immediate byte to Rx t Zeros loaded to upper 8 bits of An t Status flags are not modified See Also MOVU MOV MOVT MOVBS MOVS Example 4 14 29 1 MOVB A0 R2 Copy data memory byte pointed by R2 to accumulator AO Assembly Language Instructions 4 123 Individual Instruction Descriptions Example 4 14 29 2 OVB R2 AO Copy lower 8 bits of accumulator AO to the data memory byte pointed by R2 Example 4 14 29 3 OVB A0 Oxf2 Load accumulator AO with value of Oxf2 Example 4 14 29 4 OVB MR 34 Load MR register with immidiate value of 34 decim
6. Example 4 14 68 1 SHLACS Al A1 Shift accumulator string A1 one bit to the left store the result in accumulator string A1 Note that this instruction alters the content of all accumulators in the string 4 164 Individual Instruction Descriptions 4 14 69 SHLAPL Shift Left with Accumulate Syntax label name dest src mod Clock clk With RPT clk P SHLAPL Anti rebeca tables as 1b SHLAPL aro Arto 1 next A Execution premodify AP if mod specified PH PL src lt lt SV dest dest PL PC PC 1 Flags Affected OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode francis 10 111101100 0100 314 14 T4 T 52 a ns 0 a dma16 for direct or offset16 long relative see section 4 13 ES SHLAPL Ar An pnetA 1 Jo Po netA An s s tvpojryo A a amar ar the accumulator pointer if specified Shift accumulator word or data memory word pointed by adrs to left nsy bits as specified by the SV register into a 32 bit result This result is zero filled on the right and either zero filled or sign extended on the left based on the setting of the extended sign mode XM bit in the status register The upper 16 bits are latched into the product high PH register The lower 16 bits of the result product low PL register is added to the destination accumulator or its offset This instruction propagates the shifted bits to the next acc
7. kk ck ck ck ck Ck KKK KKK KK KKK KKK KKK ck ck ck KKK KK KKK ck kk ck kk ck kk ck kk kk ck kk ck kk ck kk ko kk Ck kk kk KK KKK KKK KKK KK Return to Texas Instruments Inc Attn Code Release Team P O Box 660199 M S 8718 Dallas TX 75266 0199 OR Fax to 214 480 7301 Attn Code Release Team Have Questions CALL Code Release Team 214 480 4444 OR E MAIL code rel msp sc ti com 7 16 New Product Release Forms NPRF NEW PRODUCT RELEASE FORM FOR MSP50C604 SECTION 1 OPTION SELECTION This section is to be completed by the customer and sent to TI along with the mi croprocessor code and speech data Company Division Project Name Purchase Order Management Contact Phone ___ Technical Contact Phone ___ Customer Part Number Customer Code Version and Revision a of format vv rr vv version rr revision numeric values only Package Type check one PM 64 Pin die Customer Code Version and Revision of format vv rr vv version rr revision numeric values only Ck Ck ck ck ck ck ck ck ck Ck Sk ck Ck Sk ck KK KK KKK KKK KKK KKK KKK KKK KKK Ck ck ck kk ck kk kk ck ck kk kk ck ko kk Sk ko ko k kc KK KKK SECTION 2A ASSIGNMENT OF TI PRODUCTION PART NUMBER This section is to be completed by TI TI Part Number CSM604xxxY or CSM604xxxPM SECTION 2B PACKAGE UNIT SYMBOLIZATION This section is to be completed by the customer The first line of the sym
8. 31 3 T 9 D 4 202 Instruction Set Summary pane ersan senmo ESE Words wannen er omn bm frenos p 3 3 Eom T8 os rentar INC INICIO ICI CS om Ame lt i me pm mum 22 CS o fons __ aacianchonaie ICI 2 wm E ow tama ne EO EEC P ours eei 9 T L9 EC mm em e ws E mer me id E T pe E E a mas CECI Pt m9 EC m TUS EU e row fd pe imc um ANC MIC E YA TS rus earshot B USES TIS Assembly Language Instructions 4 203 Instruction Set Summary dest src src1 mod Clock c k Words w An adrs Table 4 46 With RPT clk Table 4 46 Ari Ani ng 3 1 um ELATI ml A RATIO nl A adrs Table 4 46 Table 4 46 N R Table 4 46 i An An adrs next A Table 4 46 la An An imm16 next A An An PH next A An An An next A An An An next A D o na 3 na 3 NR 3 D Rx imm16 Rx R5 NR 3 lt m o O An imm8 fo Zz JJ 4A o Rx imm8 An An adrs Table 4 46 1a An An pma16 N R An An An An An An An An PH m na 3 m el ej d J olo XM ame 7 sow sue CN sus sus CN m m mms sus sws sus mms sums sms N R An adrs Table 4 46 Table 4 46 1b vector8 w N WO wo wo o X X An An imm16 next A An An An next A TFn flagaars TFn cc Rx
9. Speech editing tools These are the hardware and software tools for analyzing speech files editing speech data and generating coded speech 5 2 1 1 Code Development Tools J If the user is developing code for an MSP50C604 being used in master mode MSP50C601 MSP50C605 or MSP50C614 the following tools are needed B Hardware MSPSCANPORTI F SDK50P614 kit of 15 MSP50P61 4s SPEEC EVMf or EVA50C605t EPC50C605f B Software m MSP50C6xx code development software EMUC6xx Lj If the user is developing code for an MSP50C604 being used in slave mode the following tools are needed B Hardware MSPSCANPORTI F SDK50P614 kit of 15 MSP50P61 4s SPEECH EVM EPC50C604 B Software m MSP50C6xx code development software EMUC6xx 5 4 MSP50C6xx Development Tools Guidelines Y Ifthe user is developing host code to be used with a catalog MSP50C604 operating in slave mode B Hardware m Catalog device m SPEECH EVMt PC50C604t t These items are not needed if the customer designs their own preproduction application boards t Speech EVM and EVA50C605 have similar functionality They both function as basic target boards that support code development For more information about these boards refer to Section 5 2 2 5 2 1 2 Speech Editing Tools For editing and analyzing speech for the MSP50C6xx family the following is needed B Hardware m SDS 6000 B Software m SDS 6000 speech editing software 5 2 2 Tools Definitions
10. As an example of a barrel shift operation a coded value of 0x7 in the SV register results in a multiplier operand of 0000000010000000 1 at bit 7 This causes a left shift 7 times on the 16 bit multiplicand The output result is 32 bit On the other hand if the status bit FM multiplier shift mode is SET then the multiplier operand 0000000010000000 is left shifted once to form a 17 significant bit operand 00000000100000000 This mode is included to avoid a divide by 2 of the product when interpreting the input operands as signed binary fractions The multiplier shift mode status bit is located in the status register STAT All three multiplier registers PH SV and MR can be loaded from data memory and stored to data memory In addition data can be transferred from an accumulator register to the PH or vice versa Both long and short constants can be directly loaded to the MR from program memory The multiplicand is latched in a write only register from the internal data bus The value is not accessible by memory or other system registers Computation Unit Figure 2 3 Overview of the Multiplier Unit Operation MULTIPLIER UNIT INPUTS Multiplicand 16 bit latched in a write only register writeable and readable by Data Memory from one of the following sources as one of the following Data Memory MULTIPLYING MR Multiplier Registert 16 bit or e A l ceumuator SHIFTING SV e Shift Value Register 4
11. JMP pma16 mod PC is replaced with second word operand Post modification of Rx register is done if specified JMP An PC is replaced with content of accumulator An See Also Jcc CALL Ccc Example 4 14 26 1 JMP 0x2010 R2 Jump unconditionally to program memory location 0x2010 Decrement R2 by 2 Example 4 14 26 2 JMP A3 Jump unconditionally to program memory location stored in accumulator A3 4 114 Individual Instruction Descriptions 4 14 28 MOV Move Data Word From Source to Destination Syntax MR ATT next A NIN Rx 2 1 H 4a 4a 4c d 6 6 aars Rx Table 4 46 Table 4 46 R adrs MR Table 4 46 adrs STR Table 4 46 mov aars DP Table 4 46 adrs SV Table 4 46 i A E ERE E p EE HE SS a je a c pu cd REN poris Hopes Mov Sv aars 4 Hmm E EY pz NEN HUE Ee EA NNI NEN Ed EE Assembly Language Instructions 4 115 Individual Instruction Descriptions Taba ame E EE Word E wo ren eats INICIO CIEN EE NN N Mov STR imm to NR jJ 9 movisvimme 1 m ob wov amims wa e Execution premodify AP if mod specified dest src PC PC w Flags Affected destis An OF SF ZF CF are set accordingly dest is Rx RCF RZF are set accordingly dest is aars XSF XZF are set accordingly src is adrs TAG bit is set accordingly src is flagadrs TAG bit is set accordi
12. add string p pp p lgml ti 1 if sign 1 neg string pp p STR LENGTH 1gp 2 E copy_string p pp STR_LENGTH 19p 2 free mm1 free mm2 free pp int m1 4 m2 4 product 9 xfer const m1 M1 STR Ll X ENG fer const m2 M2 STR Ll ENG string multiply product S func main int argc char argv H 4 H 4 Implementation Details R_LENGTH 9 m1 STR_LI ENGTH 4 m2 STR_LI 5 6 5 Programming Example C With Assembly Routines ENGTH 4 There are several important considerations when using the C compiler The ram allocation must be coordinated so that a location isn t accidentally used twice In assembly this is usually done with IRX files by making each label equalto the location of the previous one plus whatever storage space is need ed All of the IRX files for a project are then combined in a master IRX file so that the space for each sub file can be allocated For example a master IRX file STACK RAM SIZI Gl BEGIN_RAM RESERVE D equ 640 equ2 RAM SIZE 14 equO UJ equ include RAMSTART INT equRESERVED include NinterNinter ram RAMSTART ASM equRAMEND INT EGIN RAM 2 1 TEXT Nasm ram irx Code Development Tools 5 29 Implementation Details 5 30 Here the sub files are inter_ram irx a
13. DE equ equ equ equ equ save timl a0a 2 1 save tim2 stat 2 1 save tim2 a0 2 1 new var RAMEND CUSTOMER Since the location and size of a variable depends on a previously declared variable it is possible to misspell a variable and end up with one or more variables starting at the wrong address Therefore it is worthwhile checking the MAIN LST file and searching for RHAMSTART CUSTOMER to ensure that all the customer variables are at the proper address Also when modifying MAIN RAM IRX or any of the module RAM IRX files it is a good idea to build the project rather than doing a make Applications 6 11 Chapter 7 Customer Information Customer information regarding package configurations development cycle and ordering forms are included in this chapter Topic Page 7 1 Mechanical Information i e maere eee nee a a eee 7 2 7 2 Customer Information Fields in the ROM 7 11 7 3 Speech Development Cycle ssseeeeeeeeeese 7 12 7 4 Device Production Sequence eeeeeeeese 7 12 5wEOrderingilnformationg e cr rreEr seen ert 7 14 7 6 New Product Release Forms eeeeeeeeeeee 7 14 Mechanical Information 7 1 Mechanical Information The MSP50C614 MSP50C605 and the MSP50C601 are normally sold in die form but are also available in a 100 pin QFP package The MSP50C604 is a available in die form and in a 64 pin QF
14. Execution premodify AP if mod specified PH PL MR src dest dest PL PC PC 1 Flags Affected OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode Instructions Pro Profra fis 12 P to 9 Js v e S a ja 32 Jo MULSPL A adi opa 1 x dma16 for direct or offset16 long relative see section 4 13 wutsPL An LAn texta 1 1 Po o rea an tjs o Jo fo Jo A A Description Perform multiplication of multiply register MR and value of src The 16 MSBs of the 32 bit product are stored in the product high PH register The 16 LSBs of the product contained in product low PL register are subtracted from dest Certain restrictions apply to the use of this instruction when interrupts are occuring in the background See Section 4 8 for more details MULSPL adrs Multiply MR by RAM word substract PL to An MULSPL Ar An next A Multiply MR by An word substract PL to An See Also MULSPLS MULTPL MULTPLS MULAPL MULAPLS Example 4 14 43 1 MULSPL AO R3 Multiply MR with the contents of R3 subtract PL from accumulator AQ and store result in accumulator AO post increment Post increment R3 by 2 Example 4 14 43 2 MULSPL A2 A2 A Predecrement accumulator pointer AP2 Multiply MR register to accumulator A2 subtract PL from accumulator A2 and store result to accumulator A2 4 138 Individual Instruction Descriptions 4 14 44 MULSPLS M
15. I m T7 Description Bitwise logical XOR of src and dest Result is stored in dest If three operands are specified then logical XOR src and src1 store the result in dest Pre modification of accumulator pointers is allowed with some operand types XOR An aars XOR RAM word to An XOR An An imm16 next A XOR immediate word to An store result in An XOR An An An next A XOR An word to An word store result in An XOR TFn flagadrs XOR TFn either TF1 or TF2 with memory tag store result in TFn bit in STAT XOR TFn cc Rx XOR test condition with TFn either TF1 or TF2 bit in STAT register Rx must be provided if cc is one of RZP RNZP RLZP RNLZP to check if the selected Rx is zero or negative Rx should not be provided for other conditionals Assembly Language Instructions 4 183 Individual Instruction Descriptions See Also XORB XORS AND ANDS OR ORS ORB NOTAC NOTACS Example 4 14 85 1 XOR Al Al 0x13FF XOR immediate value Ox13FF to A1 and store result in A1 Example 4 14 85 2 XOR AO AO 2 A Pre increment pointer APO then XOR immediate value 2 to new AO and store result in AO Example 4 14 85 3 XOR Al Al Al XOR accumulator A1 to accumulator A1 put result in accumulator A1 Example 4 14 85 4 XOR A3 R4 XOR word at address in R4 to accumulator A3 decrement value in R4 by 2 word mode after the operation Example 4 14 85 5 XOR A2 A2 R2 R5 A
16. This section is to be completed by the customer and sent to TI along with the mi croprocessor code and speech data Company Division Project Name Purchase Order Management Contact Phone ___ Technical Contact Phone ___ Customer Part Number Customer Code Version and Revision a of format vv rr vv version rr revision numeric values only Package Type check one PJM 100 pin QFP Die Ck Ck ck ck ck ck ck ck ck kk ck kk ck Ck KK KKK KKK KKK KKK KK KKK KKK KKK ck kk KK KKK KKK KKK KKK KKK KKK Ck kk Sk kc ko kk ck KKK KKK SECTION 2A ASSIGNMENT OF TI PRODUCTION PART NUMBER This section is to be completed by TI TI Part Number CSM614xxxY or CSM614xxxPJM SECTION 2B PACKAGE UNIT SYMBOLIZATION This section is to be completed by the customer The first line of the symboliza tion is fixed Except EIA Logo The second and third lines are to be filled in by the customer Top Side Symbolization 100pin PJM LLLL LOT TRACE CODE 227 YMLLLLT YM DATE CODE lt optional 13 char gt T ASSY SITE lt optional 12 char gt TI EIA NO or 4 TI LOGO For 100 PJM package the customer may choose between TI EIA No 980 or the TI LOGO on the first line 2nd Line is typically the TI Part Number ACKCK C Ck kk I SI I SI I SI I I I I I ICI II II II II II I I I I I KK KK III III III I I II II II II I KKKKKKKKKKKKKKKKKKkKkAk S
17. m 2 D Co E X Com je Com fa X gt lt HE HH X O J Ww An imm8 4 204 Instruction Set Summary pare TETAS ESE Words w IE oues pus emm es reo fr E OE CI NR CI EN mc artesa o 3 Dan mes a 2 ET cc names Description Ce nana True Condition Not true condition z Ww Conditional on ZF 1 Not condition ZF 0 s Ns Conditional on SF 1 Not condition SF 0 Conditional on CF 1 Not condition CF 0 Conditional on ZF 0 and CF 0 Not condition ZFz0 or CF 0 Conditional on ZF 0 and CF 1 Not condition ZFz0 or CF 1 Conditional on SF 0 and ZF 0 Not condition SF 0 or ZF 0 Conditional if ZF 1 and OF 0 Not condition ZFz1 or OF 0 Conditional if OF 1 Not condition OF 0 Conditional on RCF 1 Not condition RCF 0 Conditional on RZF 0 and RCF 1 Not condition RZF 0 or RCFz1 Conditional on RZF 1 Not condition RZF ll ll opu li l Oju n I Il o 2 e NN Ea E EN Een EX me RZP Conditional on value of Rx 0 Not condition Rxx0 Not available on Calls RNLZP Conditional on MSB of Rx 1 Not condition MSB of Rx 0 Not available on Calls Conditional on ZF 0 and SF 1 Not condition ZF 0 or SFz1 NTF1 Conditional on TF1 1 Not condition TF1 0 NTF2 NTAG Conditional on TF2 1 Not condition TF2 0 Conditional on TAG 1 Not condition TAG 0 Conditional on IN1 1 status Not condition IN1 0 Conditional on IN2 1 status Not condition IN2 0 Conditional
18. 5 2 2 1 Hardware Tools Definitions Note All the following TI part numbers can be purchased through authorized TI distributors see http www ti com sc docs general distrib htm Please contact TI speech applications group email Speak2Me list ti com for the latest version of the software OU MSPSCANPORTI F The MSP scanport interface board connects the PC s parallel port to the MSP50P614 or MSP50C6xx scanport The user must provide a way of connecting the MSP scanport interface to their application board See Section 5 1 for more details about this requirement O SDK50P614 This is a software developers kit that contains 15 units of MSP50P614s EPROM devices The customer will need to have access to an EPROM eraser not supplied by TI to erase these devices O EPC50C605 Code Development Tools 5 5 MSP50C6xx Development Tools Guidelines 5 6 The emulation personality card for the speech EVM that supports code development on the MSP50C614 MSP50C605 MSP50C601 and MSP50C604 being used in master mode A MSP50P614 is used on this board to emulate the MSP50C6xx core An EPROM is used on the SPEECH EVM board to emulate the data ROM of the MSP50C601 and the MSP50C605 EPC50C604 The emulation personality card forthe SPEECH EVM that supports code development on the MSP50C604 being used in slave mode A MSP50P614 is used on this board to emulate the MSP50C6xx core and the external logic devices that are built
19. A n 2 adrs RO R5 x 0 next A A MOV A3 R1 0x12ef n 3 adrs R1 0x12ef x 1 offset16 0x12ef MOV AQ R2 n 0 adrs R2 x 2 MOV A1 R3 A n 1 adrs R3 x 3 next A A MOV A2 R4 n 2 adrs R4 x 4 MOV A3 R7 4 R5 A n 3 adrs R7 R5 x 7 next A A Flag instructions apply to certain classes of instructions Class 8a They ad dress only the flag bit by either a 6 bit global address or a 6 bit relative address from the indirect register R6 If bit O of these instructions is O then bits 1 to 6 of the opcode are taken as the bit address starting from data memory location 0000h If bit O is 1 then bits 1 to 6 are used as an offset from the page register R6 to compute the relative address Bits 0 to 6 of flag instructions are written as flagadrs throughout this manual When this symbol appears it should be replaced by the syntax and bits shown in Table 4 7 For example AND TFn flagadrs can be written as follows not all possible combinations are shown AND TF1 0x21 global flag addressing flag address is 0x21 absolute AND TF2 R6 0x21 relative flag addressing flag address is R6 0x21 absolute Table 4 7 Flag Addressing Field flagadrs for Certain Flag Instructions Class 8a a flagadrs flag addressing mode encoding flagadrs ag Rada Addressing Clocks pus st Mets operions Sm s Ts s fe Modes e clk fla
20. In addition to repeat and string instructions the combination of repeated string instructions has a very useful function Since there is only one counter to control the hardware repeat count itis not possible to nest repeats and strings When a repeat instruction is followed by a string instruction the string register count is replaced by the value in the preceding repeat instruction This offers greater utility in some programs and avoids load and store operations on the string register Loop Instructions This is a software loop with an explicit reference to R4 The beginning of the loop is marked with the BEGLOOP instruction which pushes the next sequential address to a temporary register A second instruction ENDLOOP marks the end of the loop When executed ENDLOOP loads the temporary register to the program counter if R4 is positive and then post decrements R4 If R4 is negative the program counter executes a NOP instruction and exits the loop Since interrupts are queued during the execution of the loop no provision for saving the contents of the temporary register is made Interrupts if enabled before the execution of BEGLOOP will automatically be re enabled after exiting the loop Enabling interrupts inside the loop have no effect Queued interrupts are processed according to their priority after the loop exits provided the corresponding interrupt is enabled The loop overhead is 1 instruction cycle per loop cycle ideal for repeating
21. IntGenCtrl register address 0x38 16 bit wide location 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 CE AR PD EP E2 El S2 Si D5 D4 PF D3 D2 T2 Ti DA low high priority priority 0x0000 State after RESET low Interrupt mask register Comparator enable port Ds falling edge ARM bit port D4 rising edge Pulse density clock PDMCD any port F falling edge Enable pullup resistors on port F port D3 falling edge Enable TIMER2 1 value starts timer port Do rising edge Enable TIMER 1 1 value starts timer TIMER2 underflow Clock source for TIMER2 0 MC 2 1 ref Osc TIMER1 underflow Clock source for TIMER1 0 MC 2 1 ref Osc DAC timer underflow 1 value enables interrupt service The remaining bits in the IntGenCtrl have various control functions which are not directly related to the interrupt system Four of these are related to the timer functions Bits 8 and 9 are used to select the clock sources which govern the rates of TIMER1 and TIMER2 Clearing bit 8 chooses 1 2 MC as the source for TIMER i e the TIMER runs at one half the frequency of the Master Clock Setting bit 8 chooses the reference oscillator RTO or CRO as the source for TIMER1 The same applies for bit 9 and TIMER2 Bits 10 and 11 are used to enable TIMER1 and TIMER2 respectively Setting bit 10 starts TIMER1 and clearing bit 10 stops TIMER1 The same applies for bit 11 and TIMER2 Interrupi General Contr
22. Multiply MR with the content of data memory location pointed by RO and store the rounded upper 16 bits of the result in PH Increment RO by 2 4 134 Individual Instruction Descriptions 4 14 40 MULS Multiply String With No Data Transfer Syntax mus A nws 1 ms a Execution PH PL MR src string PC PC 1 Flags Affected None Opcode Instructions re rs 14 13 12 11 o o o 7 e s a jo 2 1 o mues arg tjstjol o st Ao its i fs foto fa o Description Multiply MR and the value in src The 16 MSBs of the ng 3 x 16 bit product are stored in the PH register The value in src is unchanged and the value in PL is ignored This instruction rounds the upper 16 bits Note that Anis a string of length ns 2 where ng is the value in STR register See Also MUL MULR MULAPL MULSPL MULSPLS MULTPL MULTPLS MULAPL Example 4 14 40 1 MULS AO Multiply MR with AO and store the upper 16 bits with rounding to PH register Assembly Language Instructions 4 135 Individual Instruction Descriptions 4 14 41 MULAPL Multiply and Accumulate Result Syntax label name dest src mod Clock clk With RPT cik C maer anes O eese Table as 0 maca As arith net Execution premodify AP if mod specified PH PL MR src dest dest PL PC PC 1 Flags Affected OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode
23. Not condition on conditional jumps conditional calls or test flag instructions Not repeatable or not recommended Assembly Language Instructions 4 71 Legend Symbol NR Ng OF offsei n OM PC pmaln porin PH PL RCF Rx RZF SF STAT STR SV TAG TF1 TF2 TOS UM XM XSF XZF ZF 4 72 Meaning Value in repeat counter loaded by RPT instructions Value in string register STR Overflow flag n bit offset from a reference register Overflow mode Program counter 16 bits n bit program memory address For example pma8 means 8 bit program memory address If nis not specified defaults to pma16 n bit 1 O port address Certain instructions multiply this port address by 4 Product high register 16 bits Product low register 16 bits cannot be read written directly Rx register treated as a general purpose register This bit is not related to any addressing mode Register carry flag Indirect register x where x 0 7 Register zero flag Represents string mode if 1 otherwise normal mode Sign flag Status register 17 bits String register 8 bits Shift value register 4 bits Memory tag Test flag 1 Test flag 2 Top of stack register 16 bits Unsigned mode Word s taken by instruction Don t care Extended sign mode Transfer TX sign flag Transfer TX zero flag Zero flag Legend Table 4 45 Auto Increment and Decrement Operation No modification 0 0 Auto increment A
24. PC 1 Flags Affected OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode Instructions Pro Pis fra fis 2 to o Js v e 8 a s 2 1 o MULAPLS An adis eppliebbbieli as x dma16 for direct or offset16 long relative see section 4 13 murar s ani arid fnextAl 1o o 2 J Ao Jif fofof fofa a Description Perform multiplication of multiply register MR and value of src The 16 MSBs of the ng 3 x 16 bit product are stored in the product high PH register The 16 LSBs of the product contained in product low PL register added to dest string MULAPLS adrsj Multiply MR by RAM string add PL to An MULAPLS Ar An next A Multiply MR by An string add PL to An See Also MULAPL MULSPL MULSPLS MULTPL MULTPLS Example 4 14 42 1 MULAPLS AO R3 Multiply MR with the content of data memory word string store at byte location pointed by R3 add accumulator string AO to PL and store result in accumulator AO string Increment R3 by 2 Example 4 14 42 2 MULAPLS A2 A2 A Multiply MR register to accumulator A2 add accumulator string A2 to PL and store result to accumulator A2 Assembly Language Instructions 4 137 Individual Instruction Descriptions 4 14 43 MULSPL Multiply and Subtract PL From Accumulator Syntax label name dest src mod Clock clk With RPT cik C moser fanta tebeo Taea 0 Tute Ari anti new A
25. iae ame aesti mod Glock ok Word w With RPT ok crass Ll sh An next A Execution Flags Affected Opcode Instructions Pis 5 14 13 12 Jm 10 o jo v Je s Ja Ha 2 1 premodify AP if mod specified PH PL src SV PC PC 1 OF SF ZF CF are set accordingly sul Anji neta Lt i foto nexta An filililiji fola o Description See Also Example 4 14 66 1 Premodify the accumulator pointer if specified Shift accumulator word left nsy bits as specified by the SV register into a 32 bit result This result is zero filled or sign extended on the left based on the setting of the extended sign mode XM bit in the status register The upper 16 bits are latched into the PH register Accumulator content is not changed The lower 16 bit value PL is discarded The SHL instruction can be used with a RPT instruction but without much advantage since the instruction does not write back into the accumulator Use SHLAC for this purpose SHLS SHL AO A Preincrement accumulator pointer APO Shift accumulator word AO to the left by SV bits Accumulator content is not changed PH contains the upper 16 bits of the shifted result 4 162 Individual Instruction Descriptions 4 14 67 SHLAC Shift Left Accumulator Syntax label name dest src mod Clock clk With RPT cik SHLAC An Ani next A Execution premodify AP if mod specified dest src lt l
26. next A NEGACS Ar Ar OR An adrs OR Anr An imm16 next A OR Ar An An next A OR TFn flagadrs ER ER CER ER ne 9 dma16 for direct or offset16 long relative see section 4 13 ppepepnwistepepe x dma16 for direct or offset16 long relative see section 4 13 oE p ppe ID nppliepbiebe l as dma16 for direct or offset16 long relative see section 4 13 Ps eo Jo rena Tan Joo Jo Ir ppp a dma16 for direct or offset16 long relative see section 4 13 OA O ES Pa oan ads dma16 for direct or offset16 long relative see section 4 13 ro o nea an t ojo o Jo fa a EREBREREBRERIETZM adrs dma16 for direct or offset16 long relative see section 4 13 ooo it an ej s ojo ojo fa a ojojoj an An An adrs o nexta an 1 fo 1 1 Jo Ja a o an alif an rio ro fafa neta An oo o loo o JA Instruction Set Encoding Instructions ORS Ar gt An pma16 ORS Ar An cal OUT port4 adrs EN dma16 for direct or offset16 long relative see section 4 13 is sa is 12 Pro fo fa 7 Jo 5 a 9 2 t Jo ER Kg ofofo EE ER RFLAG flagadrs flagadrs adrs X dma16 for direct or offset16 long relative see section 4 13 ROVM RTAG adrs SFLAG flagadrs flagadrs alefi ft a fs i fots s fo fo o fo o fo o neta An 2 1 ors io ao potas fa Ao fifilii i o fafo deloda adr
27. AC11 0x0400 Example 4 3 6 MOV Al 0x01F2 2 A Refer to the initial processor state in Table 4 8 before execution of this instruc tion Preincrement AP1 After preincrement A1 is AC22 and A1 is AC6 The content of data memory location 0x01F2 0x12AC is then loaded to accumu lator AC22 offset of AC6 Final result AP1 22 AC6 0x12AC Example 4 3 7 SUB Al Al 0x02A1 2 A Refer to the initial processor state in Table 4 8 before execution of this instruc tion Predecrement AP1 After predecrement A1 is AC20 and A1 is AC4 Sub tract the content of 0x02A1 0x1001 in data memory from AC20 and store result to AC4 Final result AP1 20 AC4 AC20 0x1001 0x3321 0x1001 0x2320 Example 4 3 8 MOV 0x012F 2 AO Refer to the initial processor state in Table 4 8 before execution of this instruc tion This is a table lookup instruction This instruction reads the program memory address stored in AO or AC2 and stores the data in data memory loca tion 0x012F Final result 0x012F 0x1B12 Example 4 3 9 MULR 0x02A1 2 Refer to the initial processor state in Table 4 8 before execution of this instruc tion Multiply MR with the contents of 0x02A1 The MSB of the result is stored in PH register and rounded The LSB is ignored Final result multiply MR e 0x02A1 0x1A15 e 0x1001 2 0x1A16A15 PH 0x01A1 4 3 5 Instruction Syntax and Addressing Modes Indirect Addressing Indirect addressing us
28. ADD AO A0 AO In this example saturation on a string value is illustrated A 2 word string is loaded into the STR register The accumulator string AO is loaded with 0x7F001234 and accumulator string AO is loaded with 0x10001000 When the two values are added together it causes an overflow The OF bit of the STAT is set to 1 the 16 bit MSBs of the string become Ox7FFF and the lower bits of the string become 0x2234 The final result is Ox7FFF2234 Note that if overflow mode was not set the result would have been 0x8F002234 Fractional Mode Multiplier fractional mode may be enabled disabled by setting resetting the FM bit of STAT When the multiplier is in fractional mode the multiplier is shifted left 1 bit to form a 17 significant bit operand Fractional mode avoids a divide by 2 of the product when interpreting the input operands as signed binary fractions Q formats Fractional mode works with string mode as well Example 4 6 1 SXM MOV AO Ox7FFF MOV MR Ox7FFF MULTPL AO AO Ox7FFF Ox7FFF PH Ox3FFF A0 0001 SFM MULTPL A0 A0 PH Ox7FFE AO 0002 This example illustrates the differences between a regular multiply and a frac tional mode multiply The first multiply in the above code is nonfractional The Hardware Loop Instructions high word of the result is stored in the PH register and is Ox3FFF The low word is stored in AO as 0x0001 If the two numbers are considered as Q15 fraction
29. Although we have tried to keep the differences between regular C and C to a minimum there are still a few that require explanation 5 5 6 Function Prototypes and Declarations 5 5 7 Initializations 5 5 8 RAM Usage C function prototypes and declarations MUST be preceded with the keyword cmm func Since all functions return through accumulator AO all functions are of type integer The function type may be omitted in the function declaration If present it is ignored anyway Trying to typecast a function as returning a pointer will result in a compiler error Note To change a C program back into a regular C program at least from the point of view of function prototypes and declarations the following line can be inserted at the beginning of the C program define cmm func A library of regular C functions to substitute for the special MSP50C6xx functions is supplied with the C compiler allowing the user to compare the results of regular C programs with those of C programs The library is contained in the C source file cmm func c It should be linked with the C equivalent of the C program and run in Borland C __ USB OSSA Note To use external functions in C a function prototype should be placed in the file that calls the external function AE Due in part to the architecture of the MSP50C6xx processors initialization is only allowed for global variables
30. Assembly Language Instructions 4 145 Individual Instruction Descriptions 4 14 51 NOTACS One s Complement Negation of Accumulator String Syntax iae name sess Clock ok wora w With RPT ok crass NOTACS Ari An Execution dest NOT src PC PC 1 Flags Affected OF SF ZF CF are set accordingly Opcode Instructions Pro Pis 14 fia 12 to o e 7 e 8 a 3 2 r fo INotacs Amb an tjs tjolfo s t an ojojojo t o a a Description Perform one s complement of src accumulator string and store result in dest accumulator string See Also NOTAC AND ANDB ANDS OR ORB ORS XOR XORB XORS NEGAC NEGACS Example 4 14 51 1 NOTACS A3 A3 Take the one s complement invert bits of the accumulator string A3 and put result in accumulator string A3 4 146 Individual Instruction Descriptions 4 14 52 OR Bitwise Logical OR Syntax Clare name dest sel ili mod Glock ok Word w win RPT ci ass p ommum O ere aves 10 O Ari Arti ito next OR An An Anf next A or ren ffagadrs t t NR ea OR TFn cd Ax m Execution premodify AP if mod specified dest e dest OR src1 for two operands dest src OR src1 for three operands PC PC w Flags Affected destis An OF SF ZF CF are set accordingly dest is TFn TFn bits in STAT register are set accordingly src is adrs TAG bit is set accordingly src is flagadrs
31. Assembly Language Instructions 4 171 Individual Instruction Descriptions 4 14 76 SHRAC Shift Accumulator Right Syntax label name dest src mod Clock clk With RPT cik SHRAC An Ani next A Execution premodify AP if mod specified dest src 1 PC PC 1 Flags Affected OF SF ZF CF are set accordingly Opcode Instructions Pis 5 14 13 12 11 10 o jo 7 e s a Pa 2 1 o SHRAC ani Art L nextal_ 1 1 fo o nexta An foto 1 fofa a Description Premodify accumulator pointer if specified Shift source accumulator src or its offset to right one bit and store the result into dest accumulator or its offset MSB of result will be set according to extended sign mode XM bit in the status register Example 4 14 76 1 SHRAC A1 A1 Shift right one bit the accumulator A1 Example 4 14 76 2 SHRAC Al Al A Preincrement by one accumulator pointer AP1 Shift right one bit the newly pointed accumulator A1 and store result to offset accumulator A1 4 172 Individual Instruction Descriptions 4 14 77 SHRACS Shift Accumulator String Right Syntax iae rame sess crock ok Word w With RPT ok crass SHRACS Ari Ani Execution dest src gt gt 1 PC PC 1 Flags Affected OF SF ZF CF are set accordingly Opcode Instructions Pro 15 1a H3 12 fn to o e v e s a jo 2 1 o SHmACS Ah And if fijofof an Jol
32. C Efficiency C allows top level control code to be written in a C like language It does have limitations though Assembly routines are needed to support C function calls for operations such as reading writing ports and speaking The assembly code produced by the C compiler is not optimized and will not be as efficient as hand written assembly Because C is not optimized time critical operations should always be written in assembly Since the compiler does not optimize the assembly writing C code in different ways results in different levels of overhead While and do while loops have similar overhead one conditional jump and 1 unconditional jump per Code Development Tools 5 37 C Efficiency 5 38 repetition but for loops are implemented with much greater overhead one conditional jump and three unconditional jumps per repetition For this reason it is best to replace for loops with while loops This was not done in the example projects for the sake of readability and to provide an example of a C for loop If the number of repetitions is both fixed and small the code will execute faster if the loop is unwrapped Switch statements and if else blocks have similar overhead Switch statements are slightly more efficient because the values being compared are only looked up once while an if else block looks up the values for each comparison Switch statements do not use atable lookup they use a fall throu
33. Execution memory flag bit at flagadrs data memory location 1 PC PC 1 Flags Affected None Opcode Instructions Pro Pis 14 fia 12 to o e v e s a a 2 Jo seLaG pagar tjo ojstjs o tro t flags Description Set flag at addressed memory location flagadrs includes two groups of memory flag adrresses global flags which are the first 64 words in RAM and relative flags which are 64 locations relative to the page register R6 Flag address flagadrs only accesses the 17th bit See Also RFLAG STAG RTAG Example 4 14 64 1 SFLAG R6 0x12 Sets the flag bit of the RAM word addressed by R6 plus 0x0002 Note that R6 contains a byte address and 0x0002 is interpreted as a word offset 4 160 Individual Instruction Descriptions 4 14 65 SFM Set Fractional Mode Syntax label Clock clk Word w With RPT c k Class label name Clockck Wordw withRPT cik Class ESPA or oed ed Execution STAT FM amp 1 PC PC 1 Flags Affected None Opcode Instructions Pro 15 fra H3 12 m to o e v e s a jo 2 1 o o i Tt lili fifififolif fofofofofo o Description Sets bit 3 the FM bit in status register STAT to 1 Enable multiplier shift mode for signed fractional arithmetic Example 4 14 65 1 SFM Set fractional mode Set FM bit of STAT to 1 Assembly Language Instructions 4 161 Individual Instruction Descriptions 4 14 66 SHL Syntax Shift Left
34. FAX this form to 214 480 7301 Attn Code Release Team kk ck ck ck ck Ck Ck KKK ck Ck ck KK KKK KKK KKK ck Ck Sk KKK KK KKK KKK ck Ck Sk ck kk ck kk Ck kk kk ck kk KKK KKK KK KKK KKK SECTION 4 APPROVAL OF PROTOTYPES AND AUTHORIZATION TO START PRODUCTION This section is to be completed by the customer after prototype devices have been received and tested I hereby certify that the prototype devices have been received and tested and found to be acceptable and I authorize TI to start normal production in accordance with purchase order By Title Date kk ck ck ck ck C Ck ck Ck KKK KKK KK KKK KKK ck Ck Sk KKK ck kk Ck ck ck kk ck kk ck kk KK KKK KKK Sk kk Sk ko ko KKK KKK KK KKK Return to Texas Instruments Inc Attn Code Release Team P O Box 660199 M S 8718 Dallas TX 75266 0199 OR Fax to 214 480 7301 Attn Code Release Team Have Questions CALL Code Release Team 214 480 4444 OR E MAIL code rel msp sc ti com 7 18 New Product Release Forms NPRF NEW PRODUCT RELEASE FORM FOR MSP50C605 SECTION 1 OPTION SELECTION This section is to be completed by the customer and sent to TI along with the mi croprocessor code and speech data Company Division Project Name Purchase Order Management Contact Phone ___ Technical Contact Phone ___ Customer Part Number Customer Code Version and Revision a of format vv rr vv version rr revision n
35. Instructions Pie fas J 14 13 12 11 10 o Js v e s a a pa n lo MULAPL An adis epplebblielel ams x dma16 for direct or offset16 long relative see section 4 13 MULAPLAm Art next 1 1 1 Jo o nwa an tjs jojo Jo A A Description Perform multiplication of multiply register MR and value of src The 16 MSBs of the 32 bit product are stored in the product high PH register The 16 LSBs of the product contained in product low PL register added to dest Certain restriction applies to the use of this instruction when interrupts are occuring in the background See Section 4 8 for more detail MULAPL aars Multiply MR by RAM word add PL to An MULAPL Ar An next A Multiply MR by An word add PL to An See Also MULAPLS MULSPL MULSPLS MULTPL MULTPLS Example 4 14 41 1 MULAPL AO R3 Multiply MR with the content of data memory word stored at byte location pointed by R3 add PL to accumulator AO and store result in accumulator AO Increment R3 by 2 Example 4 14 41 2 MULAPL A2 A2 A Multiply MR register to accumulator A2 add PL to accumulator A2 and store result to accumulator A2 4 136 Individual Instruction Descriptions 4 14 42 MULAPLS Multiply String and Accumulate Result Syntax labe name dest src mod Clock clk With RPT clk C maes aneas tebeo rasos 10 Pwr wi Art Execution PH PL MR src dest dest PL PC
36. IntGenCtrl 0x38 bit 7 must be 1 assuming TIMER1 Enable is O and INT6 flag is 0 assuming TIMER1 Enable is O and INT7 flag is 1 Comparator DISABLED CLEAR bit 15 in the IntGenCtrl address 0x38 PDA functions as a general purpose I O pin PDs functions as a general purpose l O pin COND maps to the state of the I O pin PD INT6 is triggered by a rising edge at PD4 INT7 is triggered by a falling edge at PDs See Section 3 1 1 See Section 3 1 1 See Section 3 1 4 IntGenCtrl 0x38 bit 6 must be 1 IntGenCtrl 0x38 bit 7 must be 1 TIMER is started stopped in software by setting clearing TIMER1 enable IntGenCtrl 0x38 bit 10 Peripheral Functions 3 17 Interrupi General Control Register 3 4 Interrupt General Control Register The interrupt general control IntGenCtrl is a 16 bit wide port mapped register located at address 0x38 The primary component in the IntGenCtrl is the 8 bit interrupt mask register IMR The IMR is used to individually enable all interrupts except RESET Each bit of the IMR is associated with one of the interrupts described in Section 3 1 5 An interrupt is enabled when the appropriate IMR bit is set The IMR is located at bits O through 7 in the IntGenCirl Bit O is associated with INTO which is the highest priority interrupt Bit 7 is associated with INT7 Refer to Section 2 7 Interrupt Logic for more information regarding the interrupt system logic and initialization sequence
37. MOVS An An Move An string to An MOVS An An Move An string to An string MOVS Ar PH Move product high reg to An string mode This instruction ignores the string count executing only once but maintains the CF and ZF status of the previous multiply or shift operation as if the sequence was a single string MOVS Ar An Move program memory string at An to An See Also MOVU MOV MOVT MOVB MOVBS Example 4 14 31 1 OVS A2 R6 Load the string pointed by R6 to accumulator string A2 Example 4 14 31 2 OVS R4 A2 Copy the accumulator string A2 to data memory location pointed by R4 Example 4 14 31 3 OVS 0x0100 2 AO Transfer the program memory word string pointed by content of AO to the data memory word location 0x0100 This is a lookup instruction Example 4 14 31 4 OVS A2 0x1400 Transfer program memory string at 0x1400 to accumulator string A2 Example 4 14 31 5 OVS Al Al Transfer accumulator string A1 to accumulator string A1 Example 4 14 31 6 OVS Al A1 Transfer accumulator string A1 to accumulator string A1 Example 4 14 31 7 OVS A2 PH Transfer value in PH to accumulator string A2 PH is copied to the second word of the string Assembly Language Instructions 4 127 Individual Instruction Descriptions 4 14 34 MOVSPH Move With Subtract from PH Syntax Jabol name dest re se Clock ok With RPT ck MOVSPH An MR aars Table 4 46 Table 4 46 Execution An
38. RAM Usage dee RE CREER RE RE EE ect a ee 5 21 5 5 9 String Functions 0 0 cee teens 5 22 5 5 10 Constant FUNCHONS sss usi pee ta ie 5 23 Contents ix Contents 5 6 Implementation Details oocccooccconccconncco teens 5 24 5674 Comparisons iii a ure sec pe a t a 5 24 5 6 2 DIVISION A IRE ne STA 5 26 5 6 3 Function e allsa e DE ee EP TC LIS be bos 5 26 5 6 4 Programming Example o oocoocccoccccocncc eh 5 27 5 6 5 Programming Example C With Assembly Routines 5 29 bi O EMICIONOY vaccae Ape ras whe CRRIQUPEEQU MRRUN OPENPR 5 37 5 7 1 Real Time Clock Example 0c cece cece eee teens 5 39 5 8 Beware of Stack Corruption 0 000 cece eet en 5 57 5 9 Reported Bugs With Code Development Tool 0 0c cece eee ees 5 58 6 Applications s 0000 sea cheese Cha eae inu x da eee te ances 6 1 6 1 Application Circuits 0 RII ete ees 6 2 6 2 Initializing the MSP50C6xx 0 eet nee ees 6 4 622 1 lA ELS 6 5 6 3 TI TALKS Example Code o ooocccoccocccccccn ee 6 8 6 44 RAM Overlays ses tht eters neg unes oats tese A Oe Ge Lawes 6 9 6 4 1 RAM Usage sch c2 cat e cae iaie E E E T edad 6 9 6 4 2 RAM Overlay ssssssssee een eee eee 6 10 6 4 8 Adding Customer Variables 00 cece eects 6 10 6 44 Common Problems ssssssssssse e 6 11 7 Customer Information 0 0 anaa eee eee eee 7
39. al numbers all bits are to the right of the decimal point then the result will be a Q30 number To translate a Q30 number back to a Q15 number first left shift the number MOV AO PH SHL A0 A0 and then truncate the lower word ig nore A0 When fractional mode is set the left shift is done automatically MOV AO PH Thus the desired Q15 result is already in the PH register 4 7 Hardware Loop Instructions These instructions enhance both execution speed and code space requirements for procedures that use short loop sequences Because of pipeline delays and the software overhead associated with counting comparing and branching software controlled structures are very inefficient for short loops To ease this burden two basic types of hardware assisted loop structures are included in the MSP50P614 MSP50C614 processor Hardware loop instructions are summarized in Table 4 42 Repeatable Instructions Most instructions can be repeated N 2 times with zero software overhead Repeated instructions are functionally identical to coding the same instruction N 2 times in sequence Repeat loops require a RPT instruction to set a count length N This immediately precedes the instruction to be repeated This next instruction is repeated N 2 times The RPT instruction is useful for clearing RAM locations filtering etc If the repeating instruction utilizes auto increments decrements to either Rx or AC registers i e R2 or 4A then the repeated
40. 2 6 2 Peripheral Communications Ports 00 cc cece eee eee eee 2 16 2 6 3 Interrupt Vectors rre ekina AURAT PR EEPE eee nne 2 18 2 6 4 ROM Code Security 0 0 cee eens 2 19 2 6 5 Macro Call Vectors 0 2 22 Sr interrupt LOGIC ue tidad 2 22 2 8 Glock Control urna enon Oe NEB ENU ENEK EETU AA 2 26 2 8 1 Oscillator Options irs a Rc ceto pue ws A Ghia 2 26 2 8 2 PLE Performance eot eer Ce oe a n ees 2 26 2 8 3 Clock Speed Control Register 00 0 eee 2 28 2 8 4 RTO Oscillator Trim Adjustment 00002 c cece eee eee eee 2 29 29 Timer Registers arco t4usetai a MURIS ELI IMPR 2 31 2 10 Reduced Power Modes 0 cece en 2 33 211 Execution TIMING 4 6 end ved deed ave Mattel enifeljetreDirreli dele OL EE EA 2 40 vii Contents 3 Peripheral Functions 0oocccocccconn II III I m m 3 1 co MENTO cr MEET 3 2 3 1 1 General Purpose I O PortS oococccccocccoccccco nn 3 2 3 1 2 Dedicated Input Port P 0 teens 3 4 3 1 8 Dedicated Output Port G ooocccccccccccocnccc ees 3 5 3 1 4 Branch on DRO uui oer A Os Ge Phases 3 6 3 1 5 Internal and External Interrupts ooocccocccocccconcrn 3 7 3 2 Digital to Analog Converter DAC sssssssssssee 3 9 3 2 1 Pulse Density Modulation Rate o ooooccccccccccccnnrrn 3 9 3 2 2 DAC Control and Data Registers 00 c cece ees 3 9 3 2 3 PDM Clock Divider sssssssss
41. 4 41 4 42 4 43 4 44 4 45 4 46 4 47 4 48 5 1 7 4 7 2 7 3 7 4 Tables Class 6a Instruction Encoding coccccccccccccc coo 4 38 Class 6a Instruction Description iiisssssslsssese I 4 38 Class 6b Instruction Description oooooocccccccoocccoc 4 39 Class 7 Instruction Encoding and Description 0 0 cece eee eee eens 4 40 Class 8a Instruction Encoding 0occcooccccccccc ooo 4 41 Class 8a Instruction Description 00 0c ec cece eee eh 4 42 Class 8b Instruction Description ooooocccccccoonccon II 4 42 Class 9a Instruction Encoding ooccccccccccccc ooo 4 43 Class 9a Instruction Description 00 00 c cece ee tee eee 4 43 Class 9b Instruction Description oooooocccccccoooocon eee eee 4 43 Class 9c Instruction Description 0 000 cece teens 4 44 Class 9d Instruction Description oooooocccccccoonccor tenes 4 44 Data Memory Address and Data Relationship 0 00 c eee eee eee ee 4 46 MSP50P614 MSP50C614 Computational Modes 0 000 cece eee eee 4 50 Hardware Loops in MSP50P614 MSP50C614 0 4 54 Initial Processor State for String Instructions 0 06 eee 4 55 Lookup Instructions 4 eas AE EERE ROER PECORE N PEKERE PREN br meets 4 57 Auto Increment and Decrement 0 cece eee ene een etn eens 4 73 Addressing Mode Bits and adrs Field Description eee eee eee 4 73 Flag Addressing Synta
42. AO A Preincrement accumulator pointer APO Copy content of accumulator AO to word memory location 0x0200 Example 4 14 28 3 OV 0x0200 2 A1 Transfer content of program memory location pointed by A1 to word data memory location 0x0200 Example 4 14 28 4 OV A2 Oxf200 A Predecrement accumulator pointer AP2 Load accumulator A2 with immediate value Oxf200 Example 4 14 28 5 OV AO A0 Copy content of accumulator AO to accumulator AO Example 4 14 28 6 OV AO AO Copy content of accumulator AO to accumulator AO Example 4 14 28 7 OV AO PH Copy content of PH to accumulator AO Example 4 14 28 8 OV SV A3 A Predecrement accumulator pointer AP3 Copy content of accumulator A3 to SV Example 4 14 28 9 OV PH A3 Copy content of accumulator A3 to PH Example 4 14 28 10 OV MR A3 A Predecrement accumulator pointer AP3 Copy content of accumulator A3 to MR Example 4 14 28 11 OV Al A1 Transfer program memory value pointed by accumulator A1 to accumulator A1 This is a table lookup instruction Example 4 14 28 12 Mov 0x0200 2 RO Store content of RO to data memory word location 0x0200 Assembly Language Instructions 4 119 Individual Instruction Descri Example 4 14 28 13 jptions OV R1 0x0200 2 Load immediate word memory address 0x0200 to R1 Example 4 14 28 14 Load R7 stack register OV R7 0x0280 32 2 with the starting value of stack i e 0x0260 Example 4 14 28 15 MOV
43. For example if APO has a value of 25 then it is pointing to accumulator AC25 If the offset bit is 1 AO then it is pointing to accumulator AC9 25 16 9 Because accumulators can only be addressed through accumulator pointers special symbols are used in MSP50P614 MSP50C614 instructions Accumulators are indicated by the symbol An where nranges from 0 to 3 The symbol indicates that the accumulator pointed to by APnis the referring accumulator If APn has a value of k it is pointing to accumulator ACK Similarly An points to the offset accumulator pointed by APn For example if AP3 22 then A3 is accumulator AC22 and A3 is accumulator AC6 System Registers During accumulator read operations both An and offset An are fetched Depending on the instruction either or both registers may be used In addition some write operations allow either register to be selected The accumulator block can also be used in string operations The selected accumulator An or An is the least significant word LSW of the string and is restored at the end of the operation String instructions are described in detail in section 4 8 4 2 9 Accumulator Pointers APO AP3 The accumulator pointer AP registers are 5 bit registers which point to one of the 32 available accumulators The APs contain the index of accumulators Many instructions allow preincrement or predecrement accumulator pointers Such instructions have a suffix of A for preincreme
44. Miscellaneous This instruction class includes all the remaining instructions that do not fit in the previous classes Some instructions have byte wide operand fields and others have no operands One subclass is a set of instructions that provide specific DSP functions FIR filters Another subclass provides some hardware software loop capability Ten instructions provide the means to set or reset five different status mode bits independently 4 42 Instruction Classification Table 4 35 Class 9a Instruction Encoding imma CO D Cose rr COIT 9 pe ee CE 0000010 e hb Table 4 36 Class 9a Instruction Description me merone ems 0000 FIRK An Rx Finite impulse response tap execution When used with repeat counter will execute a 16 bit x16 bit multiplication between an indirect addressed data memory buffer and program memory coefficients 32 bit accumulation Circular buffering Each tap executes in 2 cycles Rx automatically increments by 2 per tap 1 FIR An Rx Finite impulse response tap execution When used with the repeat counter it will execute a 16 bit x16 bit multiplication between two indirect addressed data memory buffers into a 32 bit accumulator Circular buffer operation Executes in 2 instruction cycles Rx and R x 1 automatically increments by 2 per tap 1 CORK An Rx Correlation function When used with repeat will execute 16x16 multiplication between data memory and program memory 48 bit accumulation and
45. On the P614 part the above method does not cause in the correct trim value to be loaded in ClkSpdCtrl MSP50P614 is an EPROM device Any preprogrammed value is erased when the chip goes through a UV erase procedure The RTO trim value must therefore be computed separately for each chip RTO trim values differ from one chip to another is identical for the same chip LI UR A Note Register Trim Value A resistor trim value is only needed when the resistor trimmed oscillator RTO is used The MSP50P614 device must determine the trim value sepa rately and use this value in the ClkSpdCtrl register bits 15 11 and 9 but C6xx device needs to copy bit 0 of I O location Ox2F to bit 9 of the ClkSpdCtrl regis ter and bits 5 through 1 to bits 15 through 11 of ClkSpdCtrl register tU ee 2 30 Timer Registers This software controlled trim for the RTO is not a replacement for the external reference resistor mounted at pins OSC y and OSCoyt Also note that this adjustment has no effect on the rate of the CRO reference oscillator 2 9 Timer Registers The C6xx contains two identical timers TIMER1 and TIMER2 Each includes a period register and a count down register The period register PRD1 or PRD2 defines the initial value for the counter and the count down register TIM1 or TIM2 does the counting When the count down register decrements to the value 0x0000 then the value currently stored in the period register is l
46. R3 R5 Load the contents of the byte address created by adding R3 and R5 to the MR register At the same time add accumulator AO to the PH register and store the result in AO Assembly Language Instructions 4 121 Individual Instruction Descriptions 4 14 30 MOVAPHS Move With Adding PH Syntax Tae meme dest se ot OR WI APT ok MOVAPHS An MR aars Table 4 46 Table 4 46 Execution An amp An PH MR contents of adrs PC PC w Flags Affected TAG OF SF ZF CF are set accordingly Opcode Instructions Pis 15 14 13 12 11 10 o jo v Je sa aja Jo URINE oa es dma16 for direct or offset16 long relative see section 4 13 Description Move RAM word to MR add PH to second word in Anstring Certain restriction applies to the use of this instruction when interrupts are occuring on the background See section 4 8 for more details See Also MOVAPH MOVTPH MOVTPHS MOVSPH MOVSPHS Example 4 14 35 1 MOVAPHS AO MR R3 R5 Load the content of byte address created by adding R3 and R5 to MR register At the same time add second word in accumulator string AO to PH register store result in AO string 4 122 Individual Instruction Descriptions 4 14 31 MOVB Move Byte From Source to Destination Syntax ae name des sc TR With RPT ok MOVB An aars Table 4 46 Table 4 46 MOVB aars An Table 4 46 Table 4 46 move anima Ja a a movem ms 3 fa move Jima
47. SHLTPL SHLTPLS SHLAPL SHLAPLS Example 4 14 72 1 SHLSPL A0 R4 R5 Shift the word pointed by the byte address stored in R4 by ngv bits to the left subtract the shifted PL from Accummulator AO and store the result in accumulator AO Add R5 to R4 and store result in R4 PH holds the upper 16 bits of the shift Example 4 14 72 2 SHLSPL A2 R1 Shift the word pointed by the byte address stored in R1 by nsv bits to the left subtract the shifted value PL from the accumulator A2 and store the result in accumulator A2 Increment R1 by 2 PH holds the upper 16 bits of the shift Example 4 14 72 3 SHLSPL Al Al A Preincrement accumulator pointer AP1 Shift the accumulator A1 by nsy bits to the left subtract PL from A1 and store result in accululator A1 After execution PH contains the upper 16 bits of the 32 bit shift 4 168 Individual Instruction Descriptions 4 14 73 SHLSPLS Shift Left String With Subtract PL Syntax aba name dest se 00 ok Word w wi RPT c lass P SHusPLs antos aso mese 1b smsms Wil an Execution PH PL src lt lt SV dest dest PL PC PC 1 Flags Affected OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode instructions Pro fis fra H3 2 fu tro o Js v e 8 a 3 2 1 lo SHLSPLS An adis Se aaa gt x dma16 for direct or offset16 long relative see section 4 13 SHLSPLS Art An s t fot
48. When an interrupt service branch is taken the global interrupt enable is automatically cleared by the core processor This disables all further interrupt service branches while still in the pending service routine As a result the programmer must re enable the interrupts globally using the INTE instruction If performed as the second to last instruction in the service routine then no nesting of multiple interrupts will occur If on the other hand a nesting of certain interrupts is desired then the INTE instruction may be included as the first instruction or anywhere else within the service routine When an interrupt service branch is taken the processor core also clears another status namely the respective bit in the IFR This action automatically communicates to the IFR that the current pending interrupt is now being serviced Once cleared the IFR bit is ready to receive another SET whenever the next trigger event occurs for that interrupt p Note Interrupt Service Branch If the interrupt service branch is not enabled by the respective bit in the mask register then neither the global interrupt enable nor the respective flag bit is cleared No program vectoring occurs L Interrupt Logic Figure 2 8 provides an overview of the interrupt control sequence INTO is the highest priority interrupt and INT is the lowest priority interrupt Fi
49. bit O or XM bit of STAT j Unsigned mode bit 1 or UM bit of STAT YU Overflow mode bit 2 or OM bit of STAT Y Fractional mode bit 3 or FM bit of STAT These modes can be set by setting the appropriate status register bits or by special instructions Class 9 as shown in Table 4 41 Assembly Language Instructions 4 49 MSP50P614 MSP50C614 Computational Modes Table 441 Computational Mode Sign extension SXM RXM STAT XM 1 produces sign extension on data as it is passed into accumulators This mode copies the 16th bit of the data in the multiplier multiplicand to the 17 bit This causes signed multiplication of two signed numbers STAT XM 0 suppresses sign extension Unsigned none none STAT UM 1 causes unsigned multiplication where the mul tiplier assumes its arguments as unsigned value MOVU instruction can be used to enable this mode STAT UM 0 disables unsigned multiplication SOVM ROVM STAT OM 1 initiates overflow mode Overflows cause the accumulator to acquired the most positive or most negative value In the case of string values only the MSB 16 bits are modified The remaining bits in the string are unchanged overflow operation and the accumulator content is unchanged if any overflow occurs Affects OF bit of STAT in case of overflow SFM RFM STAT FM 1 enables fractional multiplication shift mode The multiplier is shifted left 1 bitto produce a 17 bit operand This mode is used on signed b
50. for direct or offset16 long relative see section 4 13 ANDS An An pma16 ANDS An An An CALL pma16 ojo ofi jna ce fo fo fo Jo Assembly Language Instructions 4 189 Instruction Set Encoding COTO 0 5 0000010100000 01000 Cur An ads fof fots fofolm dma16 for direct or offset16 long relative see section 4 13 CMP Ari immi6l nexa 1 1 o o nea An o3 t ojo A A x imm16 CMP An An next A 1 1 a fofo nea An 1 o o o o o o o CMP An Anl next A rs foto neta an 1 folo o ofo jo CMP Rx imm16 Pt pi fofofof rx oJo X imm16 1 1 1 1 1 1 imm8 ophi h ieee e Ire o jofijijo fi a dma16 for direct or offset16 long relative see section 4 13 x gt 3 Ese E Q z y o gt 5 8 OIIO lt l lt lt mi x 21s 12 2 3 2 3 3 Co Oo GE 3 a gt 3 CMPS An pma16 1 x pma16 emps anar i fofo 1 1 an ofojofofofofo emps ar an asi fofo 1 an io fo ofo fo a cor antr tt a tt ota fofol an aia fot me fifi ko wow Tape proto jas E11 Tr CO 010000 0000 0 001010 0 01 El CS rr pe p pen t 01 01 00 fs fs 01 01 E3 CS 0 1 10 1010 p e I ppp O fo ES iran reo Pipi prfoj fopjoj an o tr o rx fafi RK An Rx tit tt ots foto an fofofo rx fifi me fofofof fofofofofo IN adrs porta Ft 1fofofo pm as dma16 for direct or offset16 long relative s
51. from accumulator string A2 put result in accumulator string A2 Example 4 14 82 4 SUBS A2 A2 A2 Subtract accumulator string A2 from accumulator string A2 put result in accumulator string A2 Example 4 14 82 5 SUBS A3 A3 PH Subtract PH from accumulator string A3 put result in accumulator string A3 This instruction ignores the string count 4 180 Individual Instruction Descriptions 4 14 83 SXM Set Extended Sign Mode Syntax iaa rame Y Glo ok wora With RT ok ass Sx NR od Execution STAT XM lt 1 PC PC 1 Flags Affected None Opcode instructions Pio 15 14 18 12 m to 9 a 7 e 15 4 a 2 1 isxm papa ffs i Tit Jt Jo Tt fo is Joo Jo Jo Description Sets extended sign mode status register STAT bit 0 to 1 See Also RXM Example 4 14 83 1 SXM Set XM bit of STAT to 1 Now all arithematic operation will be in sign extention mode Assembly Language Instructions 4 181 Individual Instruction Descriptions 4 14 84 VCALL Vectored Call Syntax Taba rame ss Clock ok wora w With RPT ok Class PP veaut ess 2 l w amp ta Execution Push PC 1 PC 0x7F00 vector8 R7 R7 2 Flags Affected None Opcode Instructions Pro Profra 8 12 t to o 8 v e S a js J2 1 Jo veatt vectors Lt t oe it fs loli Description Unconditional vectored call Macro call Push next address onto stack load PC with the content of the address
52. general purpose l O ports are bit wise programmable as either high impedance inputs or as totem pole outputs They are controlled via addressable I O registers The input only port has a programmable pullup option 100 kQ minimum resistance and a dedicated service interrupt These features make the input port especially useful as a key scan interface A simple one bit comparator is also included in the periphery The comparator is enabled by a control register and its input pins are shared with two pins in one of the general purpose l O ports Introduction to the MSP50C6xx 1 7 Functional Description for the MSP50C614 Rounding out the MSP50C6xx periphery is a built in pulse density modulated PDM digital to analog converter DAC with direct speaker drive capability Typical connections to implement reset functionality are shown in Figure 1 3 An external reset circuit is required to hold the reset pin low until the MSP50C6xx power supply has stabilized in the specified voltage range In some cases a simple reset circuit as shown in Figure 1 3 can be used for this purpose However this simple circuit may not be suitable for all applica tions For example if the power supply has an unpredictable rise time or has intermittent voltage sags the device may not initialize properly The diode and the switch shown in Figure 1 3 may be optional for some applications The diode provides a lower impedance path for the capacitor to discha
53. status e Assuming TIMER is enabled 1 running 1 stopped 1 stopped 1 TIMER source 1 2 MC 2 running 2 running 2 stopped 2 TIMER source RTO or CRO If the reference oscillator is stopped by a programmed disable or by an IDLE instruction then on re enable or wake up the oscillator requires some time to restart and resume its correct frequency This time imposes a delay on the core processor resuming full speed operation The time delay required for the CRO to start is greater than the time delay required for the RTO to start There are a number of ways to wake the C6xx from the IDLE induced sleep state The various options are summarized as a function of the reduced power mode in Table 2 5 Naturally the RESET event happens after the RESET pin has gone low to high causes an immediate escape from sleep whereby the program counter assumes the location stored in the RESET interrupt vector The RESET escape from sleep is always enabled regardless of the depth of sleep or the state of programmable controls The more functional methods available for waking the device are 1 the Internal TIMER interrupt and 2 the external input port interrupt For either of these options to work the respective bit in the interrupt mask register address 0x38 must be set to enable the associated interrupt service If the appropriate IMR bit is not set before the IDLE instruction then the interrupt trigger event will not be capable of waking the d
54. 0 1 Auto Decrement A 1 0 Stringt Relative Repeat locks Words Addressing e Operation Modes clk w Clocks Be e p pem OO le Short relative Pot o1 ome R6 offset7 ER offset7 E A A R NN CC Long relative Long relative ome ne e Rx offsett Indirect nR 2 ii Replace ng with ng for string operation Note dma16 and offset16 is the second word Table 4 47 Flag Addressing Syntax and Bits flagadrs flag addressing mode encoding flagadrs Flag Repeat ai E Perera Addressing Clocks ords Operation Syntax Modes Sin ENENE E NN e T np is RPT instruction argument clk flag address bits Assembly Language Instructions 4 73 Individual Instruction Descriptions 4 14 Individual Instruction Descriptions In this section individual instructions are discussed in detail Use the conditionals in Section 4 12 and the legend in Section 4 13 to help with individual instruction descriptions Each instruction is discussed in detail and provides the following information Assembler syntax Clock cycles required with or without repeat instructions Words required Limitation and restrictions Execution Affected flags Opcode Description Recommendation to other related instructions See Also field Examples O O O O O O O O L L 4 74 Individual Instruction Descriptions 4 14 1 ADD Add word Syntax Faber name dest ct serre eoo wt Art
55. 16 bit accumulator the desired bits width of location should be right justified The write operation is accomplished using the OUT instruction with the address of the I O port as an argument A read from these locations is accomplished using the IN instruction with the address of the I O port as an argument When reading from the I O port to a 16 bit accumulator the IN instruction automatically clears any extra bits in excess of width of location The desired bits in the result will be right justified within the accumulator Allowable access indicates whether the port is bidirectional read only or write only The last column of the table points to the section in this manual where the functions of each bit have been defined in more detail Table 2 2 Summary of MSP50C614 s Peripheral Communications Ports Control Register Address Location Access Name I O port A control I O port B control I O port C control I O port D control I O port E control mu Interrupt general Ctrl t Input states are provided by the external hardware t A control register value of 0x00 yields a port configuration of all inputs ae m State after Section for Abbreviation RESET LOW Reference PAg 7 Data unknownt PCo 7 Data 3 1 1 PGo 15 Data 0x0000 RTRIM 0x0000 DAC Data 0x0000 IntGenCtrl 0x0000 MSP50C6xx Architecture 2 17 Memory Organization RAM and ROM Table 2 2 Summary of C614 s Peripheral Communications Ports Continued I
56. 29 Clock Control RTRIM Register Read Only Applies to MSP50C6xx Device Only I O Address 0x2Fh 17 bit wide location 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 R RH R R R R R R R R R T5 T4 T3 T2 Ti TO T RTO oscillator trim storage device specific R reserved for Texas Instruments use CIkSpaCtrl Value Copied Shaded E E EE EE RT RES ER SR See E E E IA OA M7 vo ue ve vo uz ms mo When selecting and enabling the RTO oscillator therefore the bits at positions 05 through 01 should be read from I O location 0x2F MSP50C6xx device only then copied to the ClkSpdCtrl trim adjust bits 15 through 11 of control register 0x3D and bit 0 of Ox2F I O port should be copied to bit 9 of ClkSpdCtrl register The bit ordering is the same bit 04 of I O Ox2F copies to bit 15 of register OX3D Likewise bit 00 of I O Ox2F copies to bit 9 of register Ox3D However the general specification of the adjustment can be useful in certain circumstances For example the adjustment can be used to obtain a program matic increase or decrease in the speed of the RTO reference The default val ue for the adjustment after RESET low is all zeros The zero value generates the slowest programmable rate for the RTO reference The maximum value OxSF generates the fastest programmable rate for the RTO reference The full range from 0x00 to Ox3F effects an approximate 62 change based on the RTO resistor value specification
57. 3 MIETALKS Example Code repeteret 6 8 6 4 CRAM Overlayz aerate crc e 6 9 6 1 Application Circuits 6 1 Application Circuits Figure 6 1 Minimum Circuit Configuration for the C614 P614 Using a Resistor Trimmed Oscillator To pin 2 of Scan Port Connectort optional MSP50P614 only RREFERENCE E Reset Switch MSP50C614 MSP50P614 3300 pF T t The diode across VDD and Vpp may be omitted shorted if the application does not require use of the scan port interface The same applies for the 1 kQ resistor which appears at the RESET pin the resistor may be shorted if not using the scan port However the footprint for the resistor is strongly recommended for any MSP50C614 production board Refer to the Important Note regarding Scan Port Bond Out appearing in Chapter 7 Note that there are five Vpp pins and five Ves pins Each of these should be connected with the separate decoupling capacitors 0 1 uF included for each 6 2 Application Circuits Itis of particular importance to provide a separate decoupling capacitor for the Vpn Vss pair which services the DAC These pins are pad numbers 21 and 19 respectively The relatively high current demands of the digital to analog circuitry make this a requirement An alternate circuit for better clock precision and better battery life includes a crystal oscillator See Figure 6 2 Figure 6 2 Minimum Circuit Configuration for the C614 P614
58. 4 14 5 ANDB Bitwise AND Byte Syntax Tate meme asse ESE Word w Win PT hk Css Fon anima 1 3 Lo ov fa Execution dest dest AND src byte PC PC 1 Flags Affected OF SF ZF CF are set accordingly Opcode PB e a pe e esos pos osi h 0 CC O vd eo Description Bitwise AND src byte and byte stored in dest register and store result in dest register See Also AND ANDS OR ORB ORS XOR XORB XORS Example 4 14 5 1 ANDB A2 0x45 AND immediate value 0x45 to A2 byte mode Store result in A2 Upper 8 bits of A2 will be ANDed with zeros 4 82 Individual Instruction Descriptions 4 14 6 ANDS Bitwise AND String Syntax name dest src src1 Clock clk With RPT c k Class ANDS An adrs Table 4 46 Table 4 46 1 A Execution dest string dest string AND src string for two operands dest string src string AND src string for three operands PC PC w Flags Affected destis An OF SF ZF CF are set accordingly srcis adrs TAG bit is set accordingly Opcode CO 000000000000 00 00101 I MEME popa sn dma16 for direct or offset16 long relative see section 4 13 pr Le A ES X pma16 ANOS An Ar An 1 1fofof 1 an orrjogi o o A Description ANDS dest src Bitwise AND of src string and dest string and store result in dest string ANDS dest src src1 Bitwise AND src1 string src string and store result in dest string See Also AND ANDB OR
59. 4 8 before execution of this instruc tion Preincrement AO After preincrement AO is AC3 and AO is AC19 Load the contents of the data memory byte location R1 0x0254 into AC19 R1 re mains unchanged Final result APO 3 AC19 R1 0x0254 0x022A 0x0400 Example 4 3 23 MOV R7 0x0442 MR Refer to the initial processor state in Table 4 8 before execution of this instruc tion Store the value in MR to data memory byte location R7 0x0442 R7 re mains unchanged Final result 0x02A1 0x1A15 Instruction Syntax and Addressing Modes 4 3 7 Flag Addressing This addressing mode addresses only the 17th bit the flag tag bit located in data memory This addressing applies to Class 8a instructions as explained in section 4 4 Using flag addressing the flag bit can be loaded or saved In addition various logical operations can be performed without affecting the re maining 16 bits of the selected word Two addressing modes are provided The first addressing mode global flag addressing has bit O set to zero and a six bit field D1 b6 that defines the flag word address The second mode relative flag addressing has bit O set to one and a 6 bit field b1 b6 that defines the flag address relative to R6 see Figure 4 2 In other words the i e effective address contents of R6 6 bit offset In flag addressing R6 contains the address that points to the 17h bit This should not be confused with byte ad dresses and word add
60. 40 2 1 2 1 Architecture Overview The core processor in the C6xx is a medium performance mixed signal proces sor with enhanced microcontroller features and a limited DSP instruction set In addition to its basic multiply accumulate structure for DSP routines the core provides for a very efficient handling of string and bit manipulation A unique accumulator register file provides additional scratch pad memory and mini mizes memory thrashing for many operations Five different addressing modes and many short direct references provide enhanced execution and code efficiency The basic elements of the C6xx core are shown in Figure 2 1 In addition to the main computational units the core s auxiliary functions include two timers an eight level interrupt processor a clock generation circuit a serial scan port interface and a general control register Figure 2 1 MSP50C6xx Core Processor Block Diagram Multiplier MR T 17 x 17 Multiplier Shift Value SV t d i Product High PH MU Interrupt Inputs Column Exchange 32 Accumulators ACO AC31 t APO AP3 Accumulator Pointer 1 Incrementor Stack R7 Page R6 Loop R4 ARA T Indicates internal programmable registers Data Memory 640 x 17 bit Top Of Stack TOS t Peripheral Interface Serial Interface vco Frequency Divider Instruction Decoder
61. 5 ADD R3 0x1000 Add 0x1000 to register R3 store result in R3 Example 4 14 1 6 ADD R2 R5 Add R2 to R5 store result in R2 Example 4 14 1 7 ADD AP3 0x10 Add immediate Ox10 to accumulator pointer AP3 store result in accumulator pointer AP3 4 76 Individual Instruction Descriptions 4 14 2 ADDB ADD BYTE Syntax Execution dest dest src PC PC 1 Flags Affected dest is An OF SF ZF CF are set accordingly dest is Rx RCF RZF are set accordingly Opcode Ea NE EEIEER ER GC CA ER EGRE CREE EIER ERI IC LCD papel 9 III DO m eT See Also ADD ADDS SUB SUBB SUBS Description Add immediate value of unsigned src byte to value stored in dest register and store result in the same dest register Example 4 14 2 1 ADDB A2 0x45 Add immediate 0x45 to A2 Example 4 14 2 2 ADDB R5 Oxf2 Add immediate Oxf2 to R5 Assembly Language Instructions 4 77 Individual Instruction Descriptions 4 14 3 ADDS Add String Syntax ADDS An An adrs Table 4 46 Table 4 46 Table 4 46 t This instruction ignores the string count executing only once but maintains the CF and ZF status of the previous multi ply or shift operation as if the sequence was a single string This instruction should immediately follow one of the fol lowing class 1b instructions MOVAPH MULAPL MULSPL SHLTPL SHLSPL and SHLAPL An interrupt should not occur between one of these instructions and ADDS An interrupt may cause incorrect resul
62. A Premodify APn if next A specified Shift An left transfer PL to An See Also SHLTPLS SHLAPL SHLAPLS SHLSPL SHLSPLS Example 4 14 74 1 SHLTPL AO R4 R5 Shift the word pointed by the byte address stored in R4 by ngy bits to the left and store the result in accumulator AO Add R5 to R4 and store result in R4 at each execution to get the next memory value After execution PH contains the upper 16 bits of the 32 bit shift Example 4 14 74 2 SHLTPL A2 R1 Shift the value pointed by the byte address stored in R1 by ngy bits to the left and store the result in accumulator AO Increment R1 by 2 at each execution to get the next memory value After execution PH contains the upper 16 bits of the 32 bit shift Example 4 14 74 3 SHLTPL Al Al A Preincrement accumulator pointer AP1 Shift the accumulator A1 by nsy bits to the left After execution PH contains the upper 16 bits of the 32 bit shift 4 170 Individual Instruction Descriptions 4 14 75 SHLTPLS Shift Left String and Transfer PL to Accumulator Syntax SHLTPLS An adrs Table 4 46 Table 4 4 1b SHLTPLS Ani Arf Execution PH PL src SV dest PL PC PC 1 Flags Affected OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode emos feje pee e 10 5 5 1 21 4 T3 T 3 12 T 752 SHLTPLS An adi eppbbiblel ae dma16 for direct or offset16 long relative see section 4 13 sHLTPLS AnD An
63. A1 put result in accumulator string A1 Example 4 14 3 4 MULAPL AO A0 ADDS AO A0 PH The first instruction multiplies MR and AO adds PL to AO and stores the result in AO The second instruction adds PH to the second word of memory string AO and puts the result in accumulator string AO Note that MULAPL and ADDS constitute a special sequence When this sequence occurs interrupts are NOT disabled so interrupts should be disabled for correct operation In extended sign mode if AO is ACO 0x0000 AO is AC16 0xFFFF and MR OxFF after execution ACOZOXxFFO 1 AC1 0xFFFF Assembly Language Instructions 4 79 Individual Instruction Descriptions 4 14 4 AND Bitwise AND Syntax label name dest src src1 mod Clock clk With RPT clk PEL AND An aars Table 4 46 Table 4 46 Ao aer Ah nmi nese mo SECT ION HACI mms 8 mo mem mess 70 1 E morae eT Execution premodify AP if mod specified dest dest AND src for two operands dest src AND src for three operands PC amp PC w Flags Affected destis An OF SF ZF CF are set accordingly destis TFn TFn bits in STAT register are set accordingly src is adrs TAG bit is set accordingly src is flagaars TAG bit is set accordingly Opcode knee 00000000000 00000101 io OCC dma16 for direct or offset16 long relative see section 4 13 aa Poco eee A 00 AA 000000053 ano rattan e eh fs epe ope teats merca o Total e Toe Is Descr
64. AE Description Copy accumulator sign flag SF to all 16 bits of An See Also EXTSGNS Example 4 14 16 1 EXTSGN AO A Preincrement accumulator pointer APO Sign extend the accumulator AO 4 98 Individual Instruction Descriptions 4 14 17 EXTSGNS Sign Extend String Syntax Tess JT ms 13 1 oe a Execution new most significant word of dest STAT SF PC PC 1 Flags Affected None Opcode LL RC CELER CLE EC EXER ERLEd EH EAE ES ERES esews An gt gt gt f f fofof 1 a fofrf f f fofo fa Description Extend the sign bit SF of most significant word an additional 16 bits to the left The accumulator address is preincremented internally causing the sign of the addressed accumulator to be extended into the next accumulator address This instruction ignores the string count executing only once but maintains the CF and ZF status of the previous multiply or shift operation as if the sequence was a single string IMPORTANT At this stage of documentation a bug in this instruction causes the processor to stall when an attempt is made to sign extend a string that has all zeros in it Also the same interrupt problem on the accumulator pointers exists if the instruction just before is not a string instruction For customers who need the EXTSGNS function now as it was originally intended for string data there is a workaround Unfortunately it involves the use of two accumulator pointers the second point
65. CAO EAR E Stee alee hea cto ated ate aches 2 27 Instruction Execution and Timing 0 cece eect eee I 2 40 PIDNM Olock Divider oon eem Road Ret 3 11 Relationship Between Comparator Interrupt Activity and the TIMER1 Control 3 16 Top of Stack TOS Register Operation cece eee 4 3 Relative Flag Addressing 0 06 cece cece eee III 4 19 Data Memory Organization and Addressing 000ee eee e eee cn 4 45 Data Memory Example 000 cece cee ene eee nene 4 47 FR Eller Structure eso laredo dado ead A e ime wane das 4 59 Setup and Execution of MSP50P614 MSP50C614 Filter Instructions N 1 Taps 4 67 Filter Instruction and Circular Buffering for N 1 Tap Filter ooooooo ococooo 4 68 Valid Moves Transfer in MSP50P614 MSP50C614 Instruction Set 4 132 10 Pin IDC Connector top view looking at the board ooococcoccococccccnco 5 3 Hardware Tools Setup ococococcoccccconn rn 5 10 Minimum Circuit Configuration for the C614 P614 Using a Resistor Trimmed Oscillator ssssssssssesee III 6 2 Minimum Circuit Configuration for the C614 P614 Using a Crystal Referenced Oscillator 00 0 cece eee teen eh 6 3 100 Pin QFP Mechanical Information 0 0 0 c cee teeta 7 7 64 Pin QFP Mechanical Information 00 cece eee ees 7 8 120 Pin Grid Array Package for the Development Device MSP50P614 7 9 Bottom View of 120 P
66. COR ERR ERA loce oae MAIN_RAM IRX Start of memory for MAIN module is defined in include NramNram irx BERERE IEE KERKEE KIKER ERE ORG EERE RARER ER AR HORE BIRR ERS BRR el ec tocar Timer 2 interrupt variables save tim2 stat equRAMSTART CUSTOMER 2 1 save tim2 a0 equsave tim2 stat 2 1 seconds passed equsave tim2 a0 2 1 RAMSTART CMM1 equ seconds passed include cmml ram irx End of RAM RAMEND CUSTOMER equ RAMEND_CMM1 RAMLENGTH CUSTOMER equ RAMEND CUSTOMER RAMSTART CUSTOMER Any additional ram that is used in an ISR or in mainasm asm should be allocated here RAM is allocated by making a new label and setting it equal to the previous label plus an offset A variable called some variable could be allocated by changing seconds passed equ save_tim2_a0 2 1 RAMSTART_CMM1 equ seconds passed to seconds passed equsave tim2 a0 2 1 some variable equseconds passed 2 1 RAMSTART CMM1 equsome variable The next important file is vroncof2 asm Most of this file is used to support standard C functionality and will not need to be changed The part that will Code Development Tools 5 41 C Efficiency change is the table of interrupt vectors At the top of the file is a list of interrupt labels The ones that are not used are commented out with a semicolon gt external DAC ISR external timerl_isr external timer2_isr E external pd2 external pd
67. CT IT Em em E 3 99 nooo Ja pe m qem E 9 T CCSS RN RR NC NN NN ms fo wem o mem Remo AR I kr imp ECOS ow R m 1 pw wre fe mr ap or fs e qme E 2 NS Ih e menme 0 o2 2 8 CI e mem Te CI oa gps gp s p oec CIN CITE CIS ERC RET M CR Assembly Language Instructions 4 199 Instruction Set Summary dest src src1 mod Clock c k With RPT c k adrs An next A Table 4 46 Table 4 46 Weser INACIO E ura fe Eo P hw emp E Eo po P ur CISCO 3 om B ur CTI 0 3 om B pia 3 0 om p fm wiretap o T M aars Rx Table 4 46 mes j 1 MOV MOV MOV OV MOV MOV OV Bum RUI IAN adrs STR Table 4 46 Table 4 46 adrs DP Table 4 46 Table 4 46 t Signed multiplier mode resets UM bit 1 in status register to O MOV MOV MOV MOV OV 4 200 Instruction Set Summary name dest src src1 mod Clock clk With RPT clk adrs SV Table 4 46 Table 4 46 5 adrs APn Table 4 46 Table 4 46 5 E E o CC FCO p sow CC mor pmmeus FOIE p 3 om T ww mme E 3 ww CC a was man o T os man pos p 3 om CI t Flagadrs is 64 locations global or relative to R6 Co wo Assembly Language Instructions 4 201 Instruction Set Summary ECON EEE EE wes IE Sess ess av ag eg see mc awa I ow p mc em ess 999 S mas em we p om9 EA mus er fea B me ION Los m qme ome m9 Th Em LESS 3 8 18 kx erhaemuem
68. Clock Runs Periphery 131 07 kHz 33 554 MHz CPU Clock Core Processor Speed 65 536 kHz FMAX FMAX 8 MHz MSP50C6xx Architecture 2 27 Clock Control 2 8 3 Clock Speed Control Register 2 28 The ClkSpdCtrl is a 16 bit memory mapped register located at address Ox3D The reference oscillator RTO or CRO is selected by setting one of the two control bits located at bits 8 and 9 Setting bit 8 configures the C6xx for the RTO reference option and simultaneously starts that oscillator Setting bit 9 configures the C6xx for the CRO reference option and simultaneously pulses the crystal which starts that oscillator e _ __ ___ a E L a Note ClkSpdCirl Bits 8 and 9 When bit 8 is set in the ClkSpdCtrl register the crystal oscillator bit bit 9 be comes the least significant bit of the 6 bit resistor trim value Thus bits 15 11 and 9 make up the 6 bit resistor trim value For example if the ClkSpdCtrl register is 00010X11XXXXXXXX X means don t care bold numbers are re sistor trim bits then the resistor trim value is equal to five a The default value of the ClkSpdCtrl is 0x0000 which means that neither option is enabled by default Immediately after a RESET LOW to HIGH and regardless of whether a resistor or a crystal is installed across OSCw OSCour the C6xx does not have a reference oscillator running In the absence of a reference however the PLL still oscillates it bottoms out at a minimum freque
69. Compare accumulator string A2 to accumulator string A2 and change the STAT flags accordingly 4 94 Individual Instruction Descriptions 4 14 13 COR Correlation Filter Function Syntax eo d 3 dm en Execution With RPT N 2 mask interrupts RPT counter N 2 MR 0 first filter coefficient x sample data pointed by RXeven h 1 second filter coefficient pointed by Rxeyent1 y result stored in three consecutive accumulators 48 bit pointed by An between every accumulation IF TAG 1 RXeven RXeven R5 for circular buffering ELSE RXeven if Rx is specified in the instruction ENDIF PC PC 1 final result y 2 coa MK XIN Execution is detailed in section 4 11 Flags Affected none Opcode LI RR a E EROR ER e E E ERES on ant f f ifofifofjoj an rjroo rs Jiji Description When used with repeat will execute 16 x 16 multiplication between two indirectly addressed data memory buffers 48 bit accumulation and a circular buffer operation Each tap takes 3 instruction cycles The selected register Rx must be even This instruction also uses R x 1 This instruction must be used with RPT instruction See section 4 11 for more detail on the setup of coefficents and sample data During COR execution interrupts are queued See Also RPT CORK FIR FIRK Example 4 14 13 1 RPT 0 COR A0 RO Computes the calculation for 2 tap correlation filter with 48 bit accumulation See sect
70. ELSE NOP PC PC 2 Flags Affected none Opcode Demum aero esce pee ee Es Gee pra UE CA C2 ERN CR ER EA pma16 Assembly Language Instructions 4 87 Individual Instruction Descriptions Table 4 48 Names for cc True editor NOH IDE condition ccname name FERRE T ow pem ee EEDOUNEEENSE AAA BRODER eee ERN ioe TOT e AAA _ HO EA LI NNI Apra AE AAA JOTA SA AE EN E EN NO EA AE EEE EIS a JENS A SAN pura 0 APA REED po f1fo f1 me me Conditional on value of Rx 0 Not available on calls Not condition Rx 0 ERES ERE AAA eoe ic a Oe reer ae EXTERIS CA VIDA ANN A AM E a e ARI ppal a A A INGRESO TESI EIS TEL e TA AA apar A A AO ECO Mn aura me ANA NNNM Ree o A 000 00 0 00 0 0 y e e FE lt A EA A NEN ER ERES CIERRE EO APA a MOE EA E UT 3 BE A 00 0 009 AAA a AR INN AE e t 9 Been meme 0 0 0 0 o PELET 00 o mendo ooo 4 88 Description Syntax CA pma16 CNA pma16 CB pma16 CNB pma16 CC pma16 CNC pma16 CE pma16 CNE pma16 CG pma16 CNG pma16 CIN1 pma16 CNIN1 pma16 CIN2 pma16 CNIN2 pma16 CL pma16 CNL pma16 CO pma16 CNO pma16 CS pma16 CNS pma16 CTAG pma16 CNTAG pma16 CTF1 pma16 CNTF1 pma16 CTF2 pma16 CNTF2 pma16 CZ pma16 CNZ pma16 CRA pma16 CRNA pma16 Individual Instruction Descriptions If cc condition in Table 4 48 is true PC 2 is pushed onto the stack and the second word operand is
71. F falling edge port D4 rising edget T2 TIMER2 underflow port Dz falling edge T1 TIMER1 underflow port Do rising edge DA DAC timer underflow A bit value 1 indicates pending interrupt waiting to be serviced RESET The IFR is left in the same state it was before RESET low assuming no interruption in power T INT6 and INT7 may be associated instead with the Comparator function if the Comparator Enable bit has been set Refer to Section 3 3 Comparator for details Individual interrupts are enabled or disabled for service by setting or clearing the respective bit in the interrupt mask register IMR 8 bits If an interrupt level has its bit cleared in the IMR then the interrupt service associated with that interrupt is disabled Setting the bit in the IMR allows service to occur pending the trigger event which is registered in the IFR The IMR is accessible as part of another larger register namely the interrupt general control register peripheral port 0x38 After a RESET LOW the default value of each bit in the IMR is zero no interrupt service enabled A full description ofthe bit locations in the interrupt general control register can be found in Section 3 4 nterrupt General Control Register The IMR functions independently of the IFR in the sense that interrupt trigger events can be registered in the IFR even if the respective IMR bit is clear Both the IFR and IMR are readable and writeable as port address
72. FM Ew est A eem NY Note Block Protection Mode When applying the block protection mode bits FM5 through FMO must be programmed as the logical inverse of bits TM5 through TMO respectively Across the span of the 32k word ROM space there are 64 possible values for NTM including zero Hence the 6 bit wide locations for TM and FM The two single bit fields found within the block protection word are the block protection bit BP and the global protection bit GP If BP and GP are both SET erased then no protection is applied to the ROM If BP is CLEAR and GP is SET then the block protection mode is engaged This means that read and write access is prevented at locations 0x0000 through NTM 1 x 512 1 Read and write access is permitted at locations NTM 1 x 512 through Ox7FFF If GP is CLEAR then the global protection mode is engaged This prevents read and write access to all addresses of the ROM regardless of the value of BP ER e a a a a Note Block Protection Word The remaining bits in the block protection word are reserved for future use but must remain set in order to ensure future compatibility These bits are numbers 6 15 and 16 ss MSP50C6xx Architecture 2 21 Interrupt Logic When the device is powered up the hardware initialization circuit reads the value stored in the block protection word The value is then loaded to an inter nal register and the security state of th
73. Hz Hz Interrupts Interrupts 8 bits 2 10M 2 10M 1 05 M 8 19k 4 06 M 4 06 M 2 03 M 15 87 k 8 26 M 8 26 M 4 13M 32 26 k 16 38 M 16 38 M 8 19M 64 00 k 4 06 M 2 03 M A 8 26 M 4 13M 16 38 M 8 19 M 8 26M 8 26 M 4 13M 16 38 M 16 38 M 8 19 M 8 26M 4 13M 4 13M 8 06 k 16 38 M 8 19 M 8 19 M 16 00 k 10 bits 8 26M 8 26M 4 13M 8 06 k 16 38 M 16 38 M 8 19 M 16 00 k 0 16 38 M 8 49 M 8 19 M 8 00 k 9 bits 4 06 M 4 06 M 2 08M ABWILUNG les uogoni su suononasu ebenbue7 Ajquiassy 60c v 10 kHz Nominal Synthesis Rate 32 768 kHz oscillator reference CIkSpdCtrl Master CPU Output Number of Number of IntGenCtrl PLLM Clock Clock Sampling Instructs Instructs DAC PDMCD Over Sampling Register Rate Rate Rate btwn DAC btwn 10 kHz Precision Bit Factor Value Hz Hz Hz Interrupts Interrupts 10 24 k 19 97 k 39 94 k 79 87 k 10 bits 20 45 M 10 22M 10 22M 9 98 k 1024 Aewumns les uogoni su Instruction Set Summay 4 210 Assembly Language Instructions Chapter 5 Code Development Tools This chapter describes the code development tools for the MSP50C6xx family of devices The MSP50C6xx code development tool is used to compile assemble link and debug programs A reduced function C compiler called C is also part of the code development tool Topic Page Si tod UC ON E E E a a 5 2 5 2 MSP50C6xx Development Tools Guidelines 5 4 5 3 MSP50C6xx Code Development Tools oooooooo
74. It is controllable by eleven different instructions which generate the decision flags for conditional program control The results of operations performed by the bit logic unit are sent either to the flag bit of RAM memory or to the TF1 and TF2 bits of the status register STAT Memory Organization RAM and ROM 2 6 Memory Organization RAM and ROM Data memory RAM and program memory ROM are each restricted to internal blocks on the C6xx The program memory is read only and limited to 32K 17 bit words The lower 2048 of these words is reserved for an internal test code and is not available to the user The data memory is static RAM and is limited to 640 17 bit words 16 bits of the 17 bit RAM are used for the data value while the extra bit is used as a status flag The C6xx does not have the capability to execute instructions directly from external memory However additional program memory external ROM can be accessed using the general purpose I O The interface for external ROM must be configured in the software 2 6 1 Memory Map The memory map for the C6xx is shown in Figure 2 7 Refer to Section 2 6 3 Interrupt Vectors for more detailed information regarding the interrupt vectors and to Section 2 6 2 Peripheral Communications Ports for more information on the l O communications ports MSP50C6xx Architecture 2 15 Memory Organization RAM and ROM Figure 2 7 C6xx Memory Map not drawn to scale Program Memory
75. Language Instructions 4 167 Individual Instruction Descriptions 4 14 72 SHLSPL Shift Left With Subtract PL Syntax label name dest src mod Clock clk With RPT cik P SHUSPL Ants rebeca tables as 1b SHLSPL ari Arto 1 next A Execution premodify AP if mod specified PH PL src lt lt SV dest dest PL PC PC 1 Flags Affected OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode Weudes 0 51 01010 0 01010 0 101 0101 E 01 esco 2 ee ocn ceca x dma16 for direct or offset16 long relative see section 4 13 SHLSPL Ani Ant ILnextAl 1 1 1 fo o nexa An 1 1 i Jo o Jo Ja A Description Premodify the accumulator pointer if specified Shift accumulator or data memory value pointed by adrs to left nsy bits as specified by the SV register into a 32 bit result This result is zero filled on the right and either zero filled or sign extended on the left based on the setting of the extended sign mode XM bit in the status register The upper 16 bits are latched into the product high PH register The lower 16 bits of the result product low PL register is subtracted from the destination accumulator or its offset This instruction propagates the shifted bit to the next accumulator SHLSPL An aars Shift data memory word left substract PL from An SHLSPL An An next A Shift An left substract PL to An See Also SHLSPLS
76. O Map Width of Allowable y V ers State after Section for Read amp Write TIMER1 period PRD1 0x0000 EN 2 8 2 6 3 Interrupt Vectors When its event has triggered and its service has been enabled an interrupt causes the program counter to branch to a specific location The destination location is stored programmed in the interrupt vector which resides in an up per address of ROM The following table lists the ROM address associated with each interrupt vector ROM address of Interrupt Name Vector Event Source Interrupt Priority INTO Ox7FFO DAC Timer Highest INT1 Ox7FF1 TIMER1 2nd INT2 Ox7FF2 TIMER2 3rd INT3 Ox7FF3 port Do 4th INT4 Ox7FF4 port D3 5th INT5 Ox7FF5 all port F eth INT6 Ox7FF6 port D4 7th INT7 Ox7FF7 port D5 Lowest Ox7FFE storage for ROM Protection Word RESET Ox7FFF storage for initialization vector p Note ROM Locations that Hold Interrupt Vectors ROM locations that hold interrupt vectors are reserved specifically for this purpose Additional ROM locations Ox7FF8 Ox7FFD are reserved for future expansion Like the interrupt vectors they should not be used for general program storage A a 2 18 Memory Organization RAM and ROM The branch to the program location that is specified in the interrupt vector is of course contingent on the occurrence of the trigger event Refer to Section 3 1 5 Internal and External Interrupts for more information regarding the specific
77. ORB ORS XOR XORB XORS Example 4 14 6 1 ANDS AO R2 AND data memory string beginning at address in R2 to AO put result in AO Example 4 14 6 2 ANDS AO AO 0x1400 AND program memory string beginning at address in 0x1400 to AO put result in AO Example 4 14 6 3 ANDS AO A0 AO AND accumulator string AO to accumulator string AO put result in accumulator string AO Example 4 14 6 4 ANDS AO AO R2 AND memory string beginning at address in R2 to AO put result in AO Assembly Language Instructions 4 83 Individual Instruction Descriptions 4 14 7 BEGLOOP Begin Loop Syntax tater CS EI EEE mmo 1 3 Lo lw lw t Loop must end with ENDLOOP Execution Save next instruction address PC 1 mask interrupts PC PC 1 Flags Affected none Opcode Pp merecen ata pectcop aptior rfofofofofofofofafo Description This instruction saves the next sequential address in a shadow register and masks interrupts Interrupts occurring during execution of this and following instructions are actually queued until the loop is complete see ENDLOOP The loop executes N number of times Thus N 2 should be loaded in R4 in order to loop N times BEGLOOP and ENDLOOP block has following restrictions No CALL instructions can be used Lj All maskable interrupts are queued UY BEGLOOP ENDLOOP block cannot be nested See Also ENDLOOP Example 4 14 7 1 OV R4 count 2 init R4 with loop c
78. PD5 vs PD4 RESET Initialization CU Computational Unit 5 Logic OSCIN OSCOUT PLL TIMER1 PRD1 TIM1 D port I O Ox3A Ox3B Data 0x18 TIMER2 PRD2 TIM2 Control 0x1C Ox3E Ox3F Clock Control Ox3D E port I O Gen Control 0x38 Data Control OSC Reference Resistor Trimmed 32 kHz nominal Interrupt Processor FLAG MASK 0x39 0x38 F port INPUT DMAU Data Mem Addr Data 0x28 r E Crystal Referenced 32 768 kHz PLL Filter RAM 640 x 17 bit G port OUTPUT data 0x000 to Data 0x2C 0x027F Introduction to the MSP50C6xx 1 5 Functional Description for the MSP50C614 The core processor is a general purpose 16 bit micro controller with DSP capability The basic core block includes a computational unit CU data address unit program address unit two timers eight level interrupt processor and several system and control registers The core processor provides break point capability to the MSP50C6xx code development software EMUC6xx The processor is a Harvard type for efficient DSP algorithm execution It re quires separate program and data memory blocks to permit simultaneous ac cess The ROM has a protection scheme to prevent third party pirating It is configured in 32K 17 bit words The total ROM space is divided into two areas 1 The lower 2K words are re served by Texas Instruments for a built in self test 2 the upper 30K is for user program data The data memory is internal stat
79. R5 to MR register At the same time subtract PH register from second word of AO string store result in AO string Assembly Language Instructions 4 129 Individual Instruction Descriptions 4 14 36 MOVT Move Tag From Source to Destination Syntax iae name dest we Geek ok Word w With RPT ok crass MOVT adrs TFn Table 4 46 Table 4 46 Execution dest src PC PC w Flags Affected None Opcode Instructions Pi 15 14 13 12 11 10 o e 7 fo fsfafofafrfo MOVE ad TFI hpdebiebbbib e 16 for direct or offset16 long relative see section 4 13 Description Move TFn from STAT register to memory tag All addressing modes are available See Also MOVU MOV MOVT MOVB MOVBS MOVS Example 4 14 32 1 MOVT R3 TF2 Copy the TF2 flag bit to the 17th bit of the word pointed by R3 Increment R3 by 2 4 130 Individual Instruction Descriptions 4 14 37 MOVU Move Data Unsigned Syntax label name dest src mod Clock clk With RPT cik ova MR Ar next wow weary des meris 5 Execution premodify AP if mod specified dest src PC PC w Flags Affected src is adrs TAG bit is set accordingly UM is set to 1 Opcode awe 5000000000050 2 E 194 owner i pp po p pea am DHS DE D ES TD Le d MOVU MA aci a BRE NAME dma16 for direct or offset16 long relative see section 4 13 Description Copy value of srcto dest Premod
80. THIS IS IMPORTANT rovm This line is MANDATORY sxm Sample values are signed mov filterSTAT tag STAT Three more details in the above example merit an explanation The first detail is the pointer to the start of the circular buffer startOfBuff This keeps track of the location of the newest or current sample in the circular buffer It moves backwards by one location in the buffer each time the FIR or COR instruction is executed so that the oldest sample in the buffer is overwritten with the next sample This backwards movementis also circular For example sup pose that startOfBuff points to the first RAM location of the circular buffer Assembly Language Instructions 4 61 Special Filter Instructions 4 62 After the FIR or COR instruction executes the new startOfBuf f will be the last location in the circular buffer After another FIR COR instruction the new startOfBuff will be the second to last location in the circular buffer and so on The second detail is the STAT register The STAT register must be saved im mediately after every FIR or COR instruction Consequently this saved value must be loaded before every FIR or COR instruction If the tag bit in the STAT register is set before an FIR or COR instruction this tells the processor two things First it knows that it must wrap around to the first RAM location of the circular buffer Second it knows that the startOfBuff and RO currently points to the last locati
81. Table 4 46 ors annann m 2 NR 2 P ons jui An An Execution dest dest OR src fortwo operands dest src OR src for three operands C PC w Flags Affected dest is An OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode Instructions Pro Pis 1a fis 12 P1 to 9 Js v e S a fs 32 1 Jo ORS An adis oplo lol m ams x dma16 for direct or offset16 long relative see section 4 13 ORS Anri Art pmat 1 i o o s t Ao i fo fo o o fa A ors An jAm An f fofoJ an ojs ojo t o A A Description Bitwise OR of src and dest Result is stored in dest If three operands are specified then logical OR src and src store result in dest ORS An adrs OR RAM string to An string ORS An An pma16 OR ROM string to An string store result in An string ORS Ar An An OR An string to An string store result in An string See Also OR ORB AND ANDS XOR XORS NOTAC NOTACS Example 4 14 54 1 ORS A0 R2 OR data memory string beginning at address in R2 to accumulator string AO Result stored in accumulator string AO Example 4 14 54 2 ORS AO A0 Ox13F0 OR program memory string beginning at address in 0x13F0 to accumulator string AO put result in accumulator string AO Note that the address Ox13F2 is a program memory address Example 4 14 54 3 ORS AO A0 AO OR accumulator string AO to accumulator string AO
82. The Trace mode also requires the code to be programmed into the EPROM If a change is made to the code the code will need to be updated and programmed into another device while erasing previous devices This cycle of programming debugging and erasing typically requires several devices to be in the eraser at any time so 10 15 devices may be required to operate efficiently The MSP50C6xx code development tool also supports non real time debugging by scanning the code sequence through the scanport without programming the EPROM However the rate of code execution is limited by the speed of the PC parallel port These modes are called Run and Fast Run Any preproduction applications boards being used for code development must have a 13x13 121 pin zero insertion force ZIF PGA socket that allows the MSP50P614 to be easily changed Use the PGA package pin assignments shown in Figure 7 4 These preproduction boards also have the following requirements for the development tool to function properly 1 A 10 pin keyed IDC connector as shown in Figure 5 1 that connects the MSP50P614 to the MSP scanport interface should be provided 2 The VPP pin of the MSP50P614 must be pulled up with a diode connected to VDD so the development tool can apply 12 V to this pin 3 The development tool must be allowed to toggle the RESET pin without being loaded by any low impedance reset circuit This can be accomplished by inserting a 1 kQ resistor between the
83. The contents of the data memory address in RO are loaded into A2 AC11 Final result AC11 0x0400 Note the addressing is byte addressing Thus RO 0x0454 indicates the word memory location 0x454 2 0x022A Example 4 3 14 IN R4 0x00 The contents of the I O port location 0x00 port PPA are stored in the location pointed to by R4 R4 is incremented by 2 after this operation Example 4 3 15 MOVB R7 A3 Refer to the initial processor state in Table 4 8 before execution of this instruc tion Store the lower 8 bits of A3 AC29 in the data memory byte address pointed to by R7 R7 is then incremented by one Notice that to find the word address divide the address in R7 by 2 Final result R7 0x0101 0x0100 OxAB byte address or 0x80 OxABOO word address Example 4 3 16 OUT 0x08 R1 Refer to the initial processor state in Table 4 8 before execution of this instruc tion The contents of the data memory byte location stored in R1 are placed on port 0x08 port PPB R1 is then decremented by 2 Final result R1 Ox01FE 0x08 OxCB Port PPB is 8 bits wide so the upper 8 bits of R1 0x0A are ignored 4 3 6 Relative Addressing There are three types of relative addressing on the MSP50P614 MSP50C614 short relative long relative and relative to the index register R5 These ad dressing modes are described below 4 3 6 1 Relative to Index Register R5 4 16 This relative addressing mode uses one of the 8 addre
84. The frequency of the various timer interrupts will therefore vary depending upon the operating master clock frequency ee 3 8 Digital to Analog Converter DAC 3 2 Digital to Analog Converter DAC The MSP50C6xx incorporates a two pin pulse density modulated DAC which is capable of driving a 32 Q loudspeaker directly To drive loud speakers other than 32 Q an external impedance matching circuit is required 3 2 1 Pulse Density Modulation Rate The rate of the master clock MC determines the pulse density modulation PDM rate and this governs the output sampling rate and the achievable DAC resolution In particular the sampling rate is determined by dividing the PDM rate by the required resolution Output sampling rate PDM Rate 2 DAC resolution bits PDM Rate DAC resolution bits Set in ClkSpdCtrl register Set in DAC control register Address 0x3D Address 0x34 For example a 9 bit PDM DAC at 8 kHz sampling rate requires a PDM rate of 4 096 MHz There are four sampling rates which may be used effectively within the constraints of the MSP50C6xx and the various software vocoders provided by Texas Instruments These are 7 2 kHz 8 kHz 10 kHz and 11 025 kHz Other sampling rates however may also be possible From the MC to the PDM clock there is an optional divide by two in frequency This option is controlled by the PDM clock divider in the interrupt general control register This means that the PDM rate can be s
85. Timer 2 interrupt PD2 rising edge interrupt PD3 falling edge interrupt F port falling edge interrupt PDM clock Timer1 enable PDA rising edge interrupt MC Timer2 enable PD5 falling edge interrupt MC O disable 024 MC 1 enable 1 MC 0 disable 1 enable Interrupt left Flag unchanged Register PD5 falling edge interrupt flag DAC Timer interrupt flag PDA rising edge interrupt flag Timer 1 interrupt flag PD3 falling edge interrupt flag Timer 2 interrupt flag F port falling edge interrupt flag PD2 rising edge interrupt flag Ox3A 16 Timer 1 period 0x0000 Ox3B Timer 1 preset 0x0000 Ox3D 16 Clock 0x0000 Speed Idle bit PLLM bits Control CRO MC PLLM value 1 x 131 07 kHz disable CPU clock PLLM value 1 x 65 536 kHz enable Timer2period 2 a 0x0000 Timer 2 Timer2preset 0x0000 Keuiung les uogoni jsu 80c v suogonujsu eGen6ue Ajquassy IT vector Source TE Prony comment U OE wn oo ters ETT e SSCS wre E ETT 58 T INT6 and INT7 may be associated instead with the Comparator function if the Comparator Enable bit has been set Refer to section 3 3 for details 8 kHz Nominal Synthesis Rate 32 768 kHz oscillator reference CIkSpdCtrl Output Number of Number of IntGenCtrl PLLM Master Clock PDM CPU Clock Sampling Instructs Instructs DAC PDMCD Over Sampling Register Rate Rate Rate Rate btwn DAC btwn 8 kHz Precision Bit Factor Value Hz Hz
86. a 16 bit arithmetic block for incrementing and loading addresses It also consists of the program counter PC the data pointer DP a buffer register a code protection write only register and a hardware loop counter for strings and repeated instruction loops The program counter unit generates a ROM address as output The program counter value PC is automatically saved to the stack on various CALL instructions and interrupt service branches The stack consists of one hardware level register TOS which points to the top of stack The TOS is followed by a software stack The software stack resides in RAM and is addressed using the STACK register R7 in indirect mode see Section 2 3 Data Memory Address Unit The hardware loop counter controls the execution of repeated instructions using one of two modes 1 consecutive iterations of a single instruction following the repeat RPT instruction or 2 a single instruction which operates on a string of data values string loops For all types of repeated execution interrupt service branches are automatically disabled temporarily The data pointer DP register is loaded at two instances 1 from the accumulator during lookup table instructions and 2 from the databus during the fetch of long string constants To simplify algorithms which require sequential indices to lookup tables the DP register may be stored in RAM The bit logic unit is a 1 bit unit which operates on flag bit data
87. add and subtract between accumulator and data memory Either the accumulator or the offset accumulator A bit dependent can be stored in memory with the MOV instruction The MOV instruction can load the accumulator or its offset depending on the A bit The ADD or SUB instructions add or subtract memory from an accumulator register and save the results in the accumulator register A 0 or its offset A 1 Two of the four codes provided by the next A field will cause a pre increment or a predecrement of the accumulator register pointer AP prior to execution This preincrement is a permanent change to the referenced AP and further expands the use of the accumulator block as an efficient workspace Preincrements and predecrements are not available in string mode One ofthe four codes of the Anfield An 11 binary will cause the instruction to be treated as a multicycle string instruction This will not result in any perma nent modification to the referenced AP Since there is no reference to offset accumulators in Class 1b instructions the execution operates on memory and accumulators All other modes of control string preincrement predecrement AP data memory addressing modes etc are provided for logical byte multiply accumulate and barrel shift instructions Table 4 13 Class 1 Instruction Encoding ppp paja Jo A Table 4 14 Class la Instruction T Mnemonic Description O ADD An An adrs next A A
88. bit at addressed memory location All addressing modes are available Note that this instruction accesses only the 17th bit of the RAM location For odd RAM byte addresses the least significant bit is ignored See Also STAG RFLAG SFLAG Example 4 14 62 1 RTAG 0x0200 2 Reset the tag bit of data memory word location to O Note that this operation can also be done with RFLAG by loading the R6 register with 0200 2 Example 4 14 62 2 RTAG R6 0x0002 Reset the tag bit of RAM location 0x0082 Assume R6 0x0080 Unlike the SFLAG and RFLAG instructions the argument of the STAG RTAG instruction is interpreted as bytes Example 4 14 62 3 RTAG R6 0x0003 Reset the tag bit of RAM location 0x0082 Assume R6 0x0080 4 158 Individual Instruction Descriptions 4 14 63 RXM Reset Extended Sign Mode Syntax iaa name os ok Word w With RPT ok ass Pxm NR Execution STAT XM 0 PC PC 1 Flags Affected None Opcode instructions Pio fas Pia 13 2 tole 8 6 5 4 a 2 5 xu i tt Tt eo i ft Js Jo Tt fo fis is Joo Jo Description Reset extended sign mode status register bit 0 the XM bit to 0 See Also SXM Example 4 14 63 1 RXM Resets the sign extension mode to normal mode Sets XM bit of STAT to 0 Assembly Language Instructions 4 159 Individual Instruction Descriptions 4 14 64 SFLAG Set Memory Flag Syntax iae name ss Clock ok wora w With RPT ok crass SC jme TT 1 NR l8
89. bits The overflow bits function in different ways depending on the drive mode selected The two DAC drive modes are informally named C3x style and C5x Digital to Analog Converter DAC style Their selection is made at bit 3 of the DAC control register 0x34 The C3x style is selected by clearing bit 3 and the C5x style is selected by setting bit 3 The default value of the selection is zero which yields the C3x style The overflow bits appear in the DAC data register 14 and 13 to the left of the MSB data bit 12 In the C3x style mode the overflow bits serve as a 2 bit buffer to handle overflow in the value field bits 12 3 Any magnitude written to the value field which is greater than 1023 up to the limit 4095 lands a 1 in the overflow The overflow state when a 1 appears in either bit 13 or 14 yields the maximum PDM saturation and delivers the maximum possible current drive to the loudspeaker The overflow bits thus help to ensure that the audible artifacts of wrap around do not occur 3 2 3 PDM Clock Divider The pulse density modulation rate is determined by the master clock The PDM rate may be set equal to the rate of the MC or it may be set at one half the rate ofthe MC This option is controlled by the PDM clock divider PDMCD in the interrupt general control register IntGenCtrl The PDMCD is located at bit 18 in IntGenCtrl address 0x38 Clearing the PDMCD bit results in a PDM rate equal to 1 2 MC i e the
90. data source Optional for some instructions or not used Post modification of a register This can be either next A or Rmod and will be specified in the instruction Meaning The following table describes the meanings of the symbols used in the instruction set descriptions Bold type means it must be typed exactly as shown italics type means it is a variable square brackets enclose optional arguments Operands 0 x dma6 x 63 0 lt dma16 lt 65535 0 x imm5 x 31 0 lt imm16 lt 65535 0 lt offset6 lt 63 0 x offset7 x 127 0 lt offset16 65535 0 lt pma8 x 255 0 lt pma16 lt 65535 0 lt port4 x 15 0 x port6 x 63 dma16 x 639 for MSP50P614 MSP50C614 pma16 x 32767 for MSP50P614 MSP50C614 Invert the bit of the source Used with flag addressing only Accumulator selector where n 0 3 Anis the accumulator pointed by APn Offset accumulator selector where n 0 3 Anis the accumulator pointed by APn 16 APn wraps after 31 CC cc CF clk ama n DP flagadrs flg flagadrs FM g r IM imm n k0 kn MR next A Not N R Legend Meaning Select offset accumulator as the source if this bit is 1 Used in opcode encoding only Select offset accumulator as the destination accumulator if this bit is 1 Used in opcode encod ing only Select offset accumulator as the source if this bit is O Used in opcode encoding only Can be either A or A based on opcode or instruct
91. following note to the SPEECH EVM or EVA50C605 board Note The SPEECH EVM or EVA50C605 supports following speaker drive op tions L LM386 with volume control Y H bridge Y Direct drive If you choose LM386 or H bridge as the speaker drive option you have to use a 8 O speaker If you choose direct drive as the speaker drive option you have to use a 32 O speaker a e Step 3 Use the provided parallel cable to connect the PC s parallel port and scanport interface Step 4 Connect the scanport interface to the SPEECH EVM or EVA50C605 Step 5 Connect the scanport interface to a power supply The red light on the scanport interface should be ON Step 6 Place a MSP50P614 device on the personality card that you use in Step 1 Step 7 Apply power to SPEECH EVM see the following note or EVA50C605 The green light on the scanport interface should be ON Code Development Tools 5 9 MSP50C6xx Development Tools Guidelines Note There is a three way switch at the edge of the SPEECH EVM board After you apply power to the SPEECH EVM you have to turn on the SPEECH EVM There are two ways to turn on the board depending on the power Sources If you are using the on board with AAA batteries as the power source you have to slide the switch to the BATT position to turn on the board Y Ifthe power is provided externally from TB1 connector you have to slide the switch to the EXT position to turn on the b
92. for MUL adrs Pre modify the accumulator pointer if specified MUL Anr next A Multiply MR by An word store result in An t MUL aars Multiply MR by data memory wordt t Round upper 16 bits t No status change See Also MULR MULAPL MULSPL MULSPLS MULTPL MULTPLS MULAPL Example 4 14 38 1 MUL AO A Predecrement accumulator pointer APO Multiply MR with accumulator AO and store upper 16 bits of the result rounded PH Accumulator AO is left unchanged Example 4 14 38 2 MUL R3 Multiply MR with the value pointed at by R3 and store the upper 16 bits of the result rounded into PH Decrement R3 by 2 Assembly Language Instructions 4 133 Individual Instruction Descriptions 4 14 39 MULR Multiply Rounded With No Data Transfer Syntax abel name se Tos ok Word w win RPT ok Grass mur Table 4 0 46 Table 4 0 46 Execution PH PL MR src PC PC 1 Flags Affected TAG bit is set accordingly Opcode Instructions Pi 15 14 13 12 11 10 o e 7 esa aja Jo MULA as Ec Ee dma16 for direct or offset16 long relative see Section 4 13 Description Perform multiplication of multiply register MR and effective data memory value add 08x00 to the product The 16 MSBs of the 32 bit product are stored in the product high PH register No status change Round upper 16 bits See Also MULS MUL MULAPL MULSPL MULSPLS MULTPL MULTPLS MULAPL Example 4 14 39 1 MULR RO
93. high priority repeated blocks in DSP routines Table 4 42 Hardware Loops in MSP50P614 MSP50C614 Syntax RPT mm8 adrs g repeatable instruction STR ns string instruction R4 N gop BEGLOOP body of loop ENDLOOP 4 54 Operation Limitations repeatable instruction is executed nR 2 times where np is the value in repeat counter If the instruction following RPT isa string instructions then string length used will be np not the value in the STR register All interrupts are queued during loop execution Queued interrupts are processed according to priority after the completion of the RPT loop 0 lt ngx 255 String length for the string instruction is ng 2 All interrupts are queued during loop execution Queued interrupts are processed according to priority after the completion of the string instruction The maximum accumulator string length is 32 i e 0 ng x 29 O lt ng lt 255 NOTE 0 lt ng x 29 for accumulator strings The number of times the body of loop is executed is NLoop 2 All interrupts are queued during loop execution Queued interrupts are processed according to priority after the completion of the BEGLOOP ENDLOOP block 0 lt NL oop lt 32767 String Instructions 4 8 String Instructions Class 1 2 3 and 6 instructions can have string modes During the execution of string instruction STR register value plus 2 is assumed as string length An acc
94. immediately following Respective IMR bit is SET the IDLE which initiated sleep e Global interrupt enable is SET Wake up cannot occur from the programmed Interrupt under these Respective IMR bit is CLEAR conditions If RESET low to high occurs then program goes to the location stored in the RESET interrupt vector MSP50C6xx Architecture 2 39 Execution Timing 2 11 Execution Timing For executing program code the C6xx s core processor has a three level pipeline The pipeline consists of instruction fetch instruction decode and instruction execution A single instruction cycle is limited to one program Fetch plus one data memory read or write The master clock consists of two phases with non overlap protection A fully static implementation eliminates pre charge time on busses or in memory blocks This design also results in a very low power dissipation Figure 2 10 illustrates the basic timing relationship between the master clock and the execution pipeline Figure 2 10 Instruction Execution and Timing CLOCK DATA ADD 1 PC ADD N N 1 N 2 N 3 N 4 N 5 N 6 N 7 2 40 Chapter 3 Peripheral Functions This chapter describes in detail the MSP50C6xx peripheral functions i e I O control ports general purpose l O ports interrupt control registers compara tor and digital to analog DAC control mechanisms Topic Page MIMO tala esent ell ra olaaa 3 2 3 2 Digital to Analog Conver
95. infinite loop if inportD amp SWL1 setTime if inportD amp SW2 speakTime updateTime cmm func speakHours if hours lt 10 The main routine now reads keys by calling the inportD which was added to cmm1 asm as _inportD The value is compared against a constant to see if a certain key was pressed and then the function for that key is called Key checking and updates to time are all done inside the infinite loop Speaking the time is very simple using the routines that were added to cmm1 asm Af is SpeakOnes hours else must be 10 11 or 12 speakTeens hours 10 The appropriate speak function is called and the parameters are passed to it The program flow does not return to C until the speech file has finished Code Development Tools 5 51 C Efficiency playing In some cases speech files can be played to debounce keys This is why there is no delay in the main function Pressing SW2 calls a function but the switch will not be read again until the time has been spoken so there is no need for a delay there Example 5 3 Third Project C with an LCD int a 3 4 value a 3 1 0 5 52 The main difference between this project and the second project is the addition of an LCD display The variables storing the time were also changed to an array of ints instead of separate int variables to demonstrate the use of C arrays This is n
96. k 3 is overwritten by the next sample to be filtered x k 1 RO is saved in the startofBuff pointer for the next FIR COR instruction Notice that RO points backwards by one location from its starting point each time an FIR COR instruction is executed In the above figure RO would end up at successive locations in a clockwise manner 4 64 Special Filter Instructions Important Note About Setting the STAT Register It is very important to consider the initial value of the filterSTAT_tag variable Failure to set up the filerSTAT tag variable can cause incorrect results in FIR COR operations Overflow mode must always be reset The overflow bit of the STAT register may not be set For samples or filter coefficients that are signed the sign extension mode bit must also be set Use the following set up for the filterSTAT_tag variable rovm Mandatory Any addition modes can be set hereafter sxm For signed samples coefficients filter output mov filterSTAT tag STAT The FIRK CORK instructions are almost identical to the FIR COR instructions The main difference is that the filter coefficients are placed in ROM instead of RAM In other words the filter coefficients are in a look up table As a result the R1 register is not used Before a FIRK CORK instruction executes the data pointer register DP must be set by the following code rovm reset overflow mode mov RE S2 N circular buffer length 3 wo
97. loaded into the PC If the condition is false execution defaults to a NOP A Ccc instruction cannot be followed by a return RET instruction No restriction applies if IRET is used instead of RET Alternate Syntax CNBE pma16 CBE pma16 CNLE pma16 CLE pma16 CNGE pma16 CGE pma16 CRNBE pma16 CRBE pma16 Description Conditional call on above unsigned t Conditional call on not above unsigned Conditional call on below unsigned Conditional call on not below unsigned Conditional call on CF 1 Conditional call on CF 0 Conditional call on equal Conditional call on not equal Conditional call on greater signed t Conditional call on not greater signed t Conditional call on IN1 1 Conditional call on IN1 0 Conditional call on IN2 1 Conditional call on IN2 0 Conditional call on less signed Conditional call on not less signed Conditional call on OF 1 Conditional call on OF 0 Conditional call on SF 1 Conditional call on SF 0 Conditional call on TAG 1 Conditional call on TAG 0 Conditional call on TF1 1 Conditional call on TF1 0 Conditional call on TF2 1 Conditional call on TF2 0 Conditional call on ZF 1 Conditional call on ZF 0 Conditional call on Rx above unsigned t Conditional call on Rx not above unsigned Assembly Language Instructions 4 89 Individual Instruction Descriptions Syntax Alternate Syntax Description CRC pma16 Conditional call on RCF 1 C
98. modification controls will be permanent If the repeatable instruction is a string instruction then the string register STR will be replaced by N During the execution of a RPT instruction interrupts are queued Queued interrupts are serviced after the RPT operation completes according to their priority String Instructions String loops are enabled by direct field decodes in classes 1 2b 3 and 6b and have no counter overhead These instructions automatically load the counter using the contents of the STR String instruction loops are different because they assume the references made to data memory and accumulators are long data strings causing pointers to auto increment Incrementing pointers does not affect the permanent value stored in Rxor APn registers For arithmetic string operations carries from one word operation will automatically be linked to the carry in of the next word operation Additionally status equal to zero will be detected on the result as a long string These combinations provide efficient and convenient means to operate between lists or stings or between a fixed location and a list or string All string instructions have a suffix S In this text string instructions are written as nameS During Assembly Language Instructions 4 53 Hardware Loop Instructions the execution of astring instruction interrupts are queued Queued interrupts are serviced according to their priority after the string operation is complete
99. more location than Special Filter Instructions theory requires The second to last RAM location in the circular buffer is tagged using an STAG instruction Below is an example of how to set up circu lar buffering with FIR or COR When using the FIR or COR instruction with circular buffering RAM needs to be allocated forthe circular buffer and the filter coefficients Therefore the filter coefficient RAM locations must be loaded into RAM and the circular buffer must be cleared before the first FIR or COR instruction is executed Set up for FIR filtering N 3 First clear circular buffer and set tag of second to last gt sample zac a0 mov r0 circBuff point to circular buffer rpt N 2 repeat N times mov r0 a0 clear RAM locations in circular buffer mov r0 a0 N 1 sample in buffer mov 552 now step back one word and set tag sub LOES point r0 back to 2nd to last sample in buffer stag r0 set tag Second initialize filter coeffs to proper values ai ae NOTE In this code N must be less than 33 since EE ETE there are only 32 accumulator registers mov STR N 2 set string length to N zacs a0 zero out N accumulators mov a0 FIR COEFFS point to filter coeffs movs a0 a0 get N filter coeffs mov r0 coef s point to RAM locs for filter coeffs movs r0 a0 put filter coeffs into RAM locs mov a0 circBuff set up pointer to start of circular buffer mov startOfBuff a0 Initialize filterSTAT tag
100. negative numbers 0x80000000 and 0x8000 are multiplied to obtain a positive number 0x400000000000 If the signs were not extended we would have obtained 0xC00000000000 a negative number Unsigned Mode The multiplier unsigned mode may be enabled disabled by setting resetting the UM bit of the STAT When in unsigned mode the 1 7th bit of the multiplier is loaded as zero to indicate an unsigned value When UM is setto zero signed multiplication is enabled and the multiplier copies the MSB of the multiplier 16th bit to the 17th bit of the multiplier Example 4 6 1 MOV A0 0x8000 MOVU MR AO MOV AO 0x80 MULTPL AO AO In this example we do an unsigned multiplication between 0x8000 and 0x80 The first two lines set up the MR register with value 0x8000 and switch to unsigned multiplication mode Line 3 loads AO with 0x80 and line 4 multiplies the values in unsigned mode The lower 16 bits of the result is stored in AO and the upper 16 bits are stored in PH The final result is 0x400000 where PH holds the value 0x0040 and AO holds the lower 16 bits Notice that if the multiplication is not done in unsigned mode the MR is treated as negative We would have obtained OxFFC00000 PH OxFFCO AO 0000 which is the negative value of the previous result The key to unsigned multiplication is the MOVU instruction in the second line which set the UM bit to 1 in the STAT register and switches the multiplication mode to unsigned Overflow Mode The
101. obtained by adding vector8 to 0x7F00 The execution of the instruction continues from the new PC location RET instruction is used to return from VCALL RET cannot immediately follow VCALL IRET can be used instead of RET and IRET can immidiately follow VCALL VCALL is used to call frequently used routines and takes 1 word See Also RET IRET CALL Ccc Example 4 14 84 1 VCALL 0x7F02 Loads PC value with the program memory address stored in program memory location 0x7F02 4 182 Individual Instruction Descriptions 4 14 85 XOR Logical XOR Syntax abel name est sr seri mod Glock cic Word w with RPT cc lass or aneas wers rasos ta or annan mere 2 2 we 2 on Anh An Anl next A on rnm Jar e Dion rnor 1 3 1 Te Execution premodify AP if mod specified dest dest XOR src for two operands dest lt src XOR src for three operands PC PC w Flags Affected dest is An OF SF ZF CF are set accordingly dest is TFn TFn bits in STAT register are set accordingly src is adrs TAG bit is set accordingly src is flagadrs TAG bit is set accordingly Opcode Instructions 16 fas fra Pra fra ri 0 9 e v e fs a ya 2 fo CERA Poli fofol fofo m as SS x dma16 for direct or offset16 long relative see section 4 13 rama Japo Dreh an E D T9 E D DT or ansans anna papi o o ree an o T Eo To o dn I om enga folol i opel fo mes KOR TEn od RA Edo To trol Ie
102. on XZF 1 Not condition XZF 0 Conditional on XSF 1 Not condition XSF 0 DT rie oe ee pa p a m I 2 2 2 108 T c Conditional on XSF 0 and XZF 0 Not condition XSF 0 or XZFz0 Assembly Language Instructions 4 205 n m o o suojoniysul eGen6ue A quiessy Address 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x2F 0x30 Port A Data bidirectional ea Port A Contro Port B Data bidirectional a Port B Contro Port C Data bidirectional E Port C Control Port D Data multifunction port bidirectional Port D Control multifunction control Port E Data bidirectional Port E Control Port F Data input only 16 Port G Data output only RTOTRIM tMSP50C614 only 16 DAC Data MSP50C614 MSP50P614 IO Port Description Mame Rw as a 13 2 m o fo Je 7 e s a o 2 o anorneser eee R W R W R W R W R W R W R W R W R W C 0 for interrupts IO 0x18 d bit Ey 0 PE low A bit Ay 0 PA low ud bit C 0 PA as input m bit By 0 PBy low m bit C 0 PB as input lii bit Cy 2 0 PCy low m bit C 0 PCy as input AO e fos pst fost vs oz pt vo bit Ay 1 2 PAy high bit C 1 PAx as output ar ge gs B4 Be ez 61 60 bit By 1 2 PB high bit C 1 PBy as output bit Cy 1 PCy high bit C 1 PCy as output bit Dy 0 PD low bit C 0 PD as input r3 F
103. on the personality card emulate the slave mode of MSP50C604 The board has a 25 pin connector that allows a PC parallel port to emulate the host processor PC50C604 The personality card forthe SPEECH EVM that has a 64 pin QFP socket for a catalog MSP50C604 and a 16 pin DIP socket for a catalog MSP53C39x see the following note This board can be used to develop host codes for use with either a MSP50C691 or MSP53C392 slave device It also can be used with the SDS3000 software which is a MSP50C3x speech editing system Note The MSP50C691 and the MSP53C392 are catalog slave speech synthesizers in the MSP50C6xx and the MSP50C3x family of speech devices SPEECH EVM see the following note This board along with the appropriate personality card provides a basic target board that a customer can use to begin code development The SPEECH EVM can be used with the following personality cards m EPC50C605 m EPC50C604 m PC50C604 This board supports the following speaker drive options B LM386 with volume control B H bridge B direct drive There is a socket for an EPROM on the SPEECH EVM to emulate the DATA ROM in the MSP50C601 and the MSP50C605 MSP50C6xx Development Tools Guidelines EVA50C605 see the following note Same as SPEECH EVM Note The SPEECH EVM and EVA50C605 have similar functionality They both function as basic target boards that support code development One of the differences is that th
104. or Ccc instruction must have executed before Assembly Language Instructions 4 153 Individual Instruction Descriptions 4 14 58 RFLAG Reset Memory Flag Syntax Trias mes TT Tn Toa Execution memory flag bit at flagadrs data memory location 0 PC PC 1 Flags Affected None Opcode Instructions Pro Pis fia fia 12 to o e v e s a a 2 1 Jo arLAG faga tjojojs ojo o o t fagars Description Reset flag at addressed memory location to 0 flagadrs includes two groups of memory flag addresses global flags which are the first 64 word locations in RAM and relative flags which are 64 locations relative to the page register R6 Flag address flagadrs only addresses the 17th bit See section 4 3 7 for more information See Also SFLAG STAG RTAG Example 4 14 58 1 RFLAG 0x21 Resets the flag bit at RAM byte location 0x0042 to zero Example 4 14 58 2 RFLAG R6 0x0002 Resets the flag bit at RAM byte location 0x0084 to zero Assume R6 0x0080 The R6 register is represented in bytes but the 0x0002 is represented in words Thus 0x0080 bytes plus 0x0002 words or 0x0004 bytes equals 0x0084 bytes 4 154 Individual Instruction Descriptions 4 14 59 RFM Reset Fractional Mode Syntax iaa rame Glo ok wora w win RPT ok ass Arm NR od Execution STAT FM 0 PC PC 1 Flags Affected None Opcode Instructions Pro 15 Pta H3 12 m to o e v
105. pam as dma16 for direct or offset16 long relative see section 4 13 EJ MOV STAT ads Fn Ee CEE Ee ES EO ES dma16 for direct or offset16 long relative see section 4 13 MOV TOS adrs ipfrfof fifofolrfol____ as dma16 for direct or offset16 long relative see section 4 13 El MOV ads PA prefe Te To ES dma16 for direct or offset16 long relative see section 4 13 MOV scs WR Oe reeeo IE dma16 for direct or offset16 long relative see section 4 13 El MOV ads STAT HEIDBISDBISDBISD as El dma16 for direct or offset16 long relative see section 4 13 MOV ads STR OLEC 3 ES dma16 for direct or offset16 long relative see section 4 13 MOV sc DP Popper feo E dma16 for direct or offset16 long relative see section 4 13 MOV ad SV CEIDBIIDISDPII as 3 E dma16 for direct or offset16 long relative see section 4 13 MOV eds AP Oe eeiam 03 dma16 for direct or offset16 long relative see section 4 13 El MOV ausi TOS Eeee eE El dma16 for direct or offset16 long relative see section 4 13 MOV STR adsis pepe pere pe e E 1 x dma16 for direct or offset16 long relative see section 4 13 mov agas ren ifofo i opalo jep wes mov ren teoa apo o ejw e o o m mov renta rad r e epepepe I II wwvsmms npppppl
106. put result in accumulator string AO 4 150 Individual Instruction Descriptions 4 14 55 OUT Output to Port Syntax labe rame sess Goo ok wora w With RPT ck crass P out pons teary oere muss n Tout ooren tae ae me oa Execution port4 or port6 src PC PC w Flags Affected XSF XZF are set accordingly src is adrs TAG bit is set accordingly Opcode instructions Pro Pis fra H3 12 fu Jo Jo fs v e stats 2 fo OUT por adis ato To E e as dma16 for direct or offset16 long relative see section 4 13 jour pors An Lt Tt Tt tots ts fo an po t aI Description Output to I O port Words 16 bits in memory can be output to one of 16 port addresses Words 16 bits in the accumulators can be output to these same 16 port addresses or to an additional 48 port addresses Note that port4 address is multipled by 4 to get the actual port address See Also OUTS IN INS Example 4 14 55 1 OUT 3 0x0200 2 Outputs the content of word memory location value stored in 0x0200 to I O port at location 0x0C PBDIR port Note that address 3 converts to 3 4 Oxc Assembly Language Instructions 4 151 Individual Instruction Descriptions 4 14 56 OUTS Output String to Port Syntax iae name sess Clock ok wora w With RPT ok crass p ours pong arty me 1 me 6 Execution port6 src PC PC 1 Flags Affected XSF XZF are set accordingly Op
107. section 4 13 mov Rx immis its 1 1 1 ofo o fo m jojo mov rars a fif f9 19 1 0fo fo me Jofo mov svimma 1 1 1 1f0 fo ofofofo imm pas ppal d dma16 for direct or offset16 long relative see section 4 13 t Signed multiplier mode resets UM bit 1 in status register to O Assembly Language Instructions 4 191 Instruction Set Encoding Instructions MOV PH aars ae EA ES aCeee 7 MOV MR adrs dma16 for direct or offset16 long relative MOV APn adrs dma16 for direct or offset16 long relative MOV STAT adrs dma16 for direct or offset16 long relative MOV TOS adrs dma16 for direct or offset16 long relative MOV adrs PH dma16 for direct or offset16 long relative MOV adrs MR dma16 for direct or offset16 long relative MOV adrs STAT dma16 for direct or offset16 long relative MOV adrs STR dma16 for direct or offset16 long relative MOV adrs DP dma16 for direct or offset16 long relative MOV adrs SV dma16 for direct or offset16 long relative MOV adrs APn dma16 for direct or offset16 long relative MOV adrs TOS dma16 for direct or offset16 long relative MOV STR adrs x dma16 for direct or offset16 long relative movemur Papo Yo rf e vqo tmm mov wen aast fo o fr 3 eolo fo o ram Qe Te Tele mov TFn opt Rd 1 o o 1 o i Not mov stR ima a Ja a Ja t t oo i MO
108. status regis ter Global flag addressing or relative flag addressing is used to address flags Flag bits can be set or reset using flag instructions in addition to various logical operations The flag address does not have a string mode Rx Post Modifications Indirect addressing allows post modification of Rx For byte and byte string mode Rxis post modified by 1 for each byte For word and word string mode Rxis post modified by 2 for each word Post modification of Rx is not available for flag addressing Table 4 40 Data Memory Address and Data Relationship Mode Address Used Data Order Rx Post modify Single byte Absolute 16 bit address 8 bit data 1 Byte string Beginning of string at lower address String length times 8 bit data 1 per byte in string by Incrementing addresses Single word Even address if odd address is used 16 bit data 2 the LSB bit of address is assumed 0 Word string Even address beginning at a lower String length times 16 bit data 2 per word in address if odd address is used the by incrementing addresses string LSB bit of address is assumed 0 Flag Address is considered as holding 17 bit 1 bit data not available data but only 17th bit is accessed Rx post modification is available by various addressing modes see 4 3 Instruction Syntax and Addressing Modes for detail Example 4 5 1 MOVB AO 0x0003 Refer to Figure 4 4 for this example This instruction loads the value 0x78 to the accumulator The upp
109. string int result int strl int str2 int 1g exclusive ors strings strl and str2 of length lg 2 and puts the result in string result not string int result int strl int 1g takes the l s complement of string strl of length lg 2 and puts the result in strings result neg string int result int strl int 1g takes the 2 s complement of string strl of length lg 2 and puts the result in strings result test string int stringl int string2 int lg int oper performs a logical test operation on strings stringl and string2 of length lg 2 The logical value is returned in AO If string2 is NULL the logical test is performed between string stringl and a zero string operator can take the following values predefined constants EQS N zz NES N LTS N LES N lt GES N gt GTS_N gt ULTS_N lt unsigned ULES_N lt unsigned UGES_N gt unsigned UGTS_N gt unsigned A major feature of the MSP50C6xx is that the string length present in the string register is the actual length of the string minus two To avoid confusion a macro is supplied that automatically translates the real length of the string to 5 22 C Compiler the MSP50C6xx length of the string It is included in the cmm macr h file and is called STR LENGTH lstr For example STR LENGTH 8 is 8 2 6 Also note that the user has to supply the length of the input string and the length of the output str
110. tabadr equ RAMSTART CUSTOMER 2 1 equ ledpattern 2 1 equ leypress 2 1 Time 1 interrupt variables save timl stat save tim2 a0 save tim2 a0a equ save timl a0a 2 1 equ save tim2 stat 2 1 equ save tim2 a0 2 1 Time 2 interrupt variables save_tim2_stat save_tim2_a0 save tim2 a0a End of RAM RAMEND CUSTOMER E RAMLENGTH CUSTO RAMSTART CUSTOME MAIN RAM IRX AE equ equ equ equ equ RAM Overlay save timl a0a 2 1 save tim2 stat 2 1 save tim2 a0 2 1 save tim2 a0a RAMEND CUSTOMER After adding new var the MAIN RAM IRX file would look like this PR RR RRR kc kk kk kk ke RK kc kk KKK KK RK KK KK KKK KEK KKK KKK KK kc ko koc EK koc ke kk ke ck KEK KKK KK Start of memory for MAIN module is defined in include ram ram irx SABRE ARERR EBA RAR ER BRR EE BRS AR RRR ENE RE RAR RRR woe po RR RAR General purpose variables ledpattern keypress tabadr equ equ equ RAMSTART_CUSTOMER 2 1 ledpattern 2 1 leypress 2 1 Time 1 interrupt variables save timl stat save tim2 a0 save tim2 a0a equ equ equ save timl a0a 2 1 save tim2 stat 2 1 save tim2 a0 2 1 Time 2 interrupt variables save tim2 stat save tim2 a0 save tim2 a0a End of RAM RAMEND CUSTOMER E RAMLENGTH CUSTOMI RAMSTART CUSTOME 6 4 4 Common Problems
111. the original mnemonic For example JA jump above tests the same conditions as JNBE jump not below or equal but may have more meaning in a specific section of code See Also JMP CALL Ccc Example 4 14 27 1 JNZ 0x2010 Jump to program memory location 0x2010 if the result is not zero Example 4 14 27 2 JE 0x2010 R3 R5 Jump to program memory location 0x2010 if flag RZF 1 Increment R3 by R5 Since this jump instruction does not have a P at the end post modification is NOT reflected in the STAT register Thus if R8 becomes zero RZF is not updated Example 4 14 27 3 JIN1 0x2010 R1 Jump to program memory location 0x2010 if I O port address PDg pin has a value of 1 Decrement R1 by 2 Example 4 14 27 4 JTAG 0x2010 R2 Jump to program memory location 0x2010 if TAG bit of STAT is zero Increment R2 by 2 Assembly Language Instructions 4 113 Individual Instruction Descriptions 4 14 27 JMP Unconditional Jump Syntax MEA EE E ok Word wine ok eee fair foi a pe o e ee Re ef ef IEC we mas fe o pe pmesmm f e 3 pow p we pe e 2 AO e Execution PC dest Post modify Rx if specified Flags Affected RCF and RZF affected by post modification of Rx Opcode ps NE EE EE e E ERREUR IER AME pina EE ERES EORR Ee pma16 ES me epee t EX pma16 mem Ee e Ls pma16 JMP mat Rex FES EE CREE E EA pma16 5 01010 001001000 0000 015 Description LL NENNT IEMEMEMEERECENENE NENNEN
112. the accumulator A 0 or 1 SUBS An An pma16 Store the result in accumulator A 0 or offset accumulator A 1 ALU status is modified CMP An imm16 next A Modify ALU status by subtracting a long constant from accu CMPS An pma16 mulator A 0 or from offset accumulator A 1 Neither ac cumulator or offset accumulator is modified 1 0 OR An An imm16 next A Logical OR a long constant with accumulator A 0 or 1 ORS Ar An pma16 Store the result in accumulator A 0 or offset accumulator A 1 ALU status is modified 1 0 1 AND An An imm16 next A Logical AND a long constant with accumulator A 0 or ANDS An An pma16 1 Store the result to accumulator A 0 or 1 ALU status is modified 1 1 0 XOR An An imm16 next A Logical exclusive OR a long constant with accumulator A 0 XORS An An pma16 or 1 Store the result to accumulator A 0 or 1 ALU status is modified 1 1 1 MOV MR mm16 next A Load a long constant to MR in signed mode No change in status 4 4 3 Class 3 Instruction Accumulator Reference 4 30 These instructions reference the accumulator and in some instances specific registers for transfers Some instructions use a single accumulator operand and others use both the accumulator and the offset accumulator to perform operations between two accumulator values The A bit in the instruction word reverses the s
113. the chip is installed label EQU expression Associates the value of expression with label EXTERNAL symbol symbol This directive is used to indicate to the assembler that one or more symbols are external references i e symbols that will be resolved by the linker GLOBAL symbol symbol This directive is used to indicate to the assembler that one or more symbols are global references These symbols MUST be defined in the current file and will be used by the linker to resolve external references present in other files GLOBAL should only be used for PROGRAM labels RAM variables are handled with the GLOBAL VAR directive GLOBAL VAR symbol symbol This directive allows a RAM variable to be referenced from another file GLOBAL VAR should be used prior to defining a RAM variable with the RESW directive for example The file that references the variable should declare it as EXTERNAL of REF Note that this technique can also be used to make constants defined with the EQU statement available to other files INCLUDE filename This directive is used to insert another file in the current assembly file The name of the file must be enclosed in double quotes If the file name itself is enclosed in angled brackets lt gt then the assembler will first look for the include file in the include directory list that is passed as an argument during the DLL call LIST The lines following this directive are included in the listing file exte
114. ti com 7 1 2 Package Information 7 2 The MSP50C614 MSP50C605 and the MSP50C601 are available in the 100 pin QFP package See Figure 7 1 and Tables 7 1 thru 7 3 The MSP50C604 is a available the 64 pin QFP package See Figure 7 2 and Table 7 4 For more detailed information please refer to the device datasheets available on the TI speech web site http www ti com sc speech Mechanical Information Table 7 1 Signal and Pad Descriptions for the MSP50C614 SIGNAL PIN NUMBER PAD NUMBER y o DESCRIPTION Input Output Ports PAO PA7 66 59 75 68 1 0 Port A general purpose I O PBO PB7 76 69 85 78 1 0 Port B general purpose I O PCO PC7 90 83 8 1 1 0 Port C general purpose l O PDO PD7 100 93 18 11 1 0 Port D general purpose l O PEO PE7 51 44 63 56 1 0 Port E general purpose I O PFO PF7 16 9 31 24 l Port F dedicated input PGO PG7 37 30 49 42 O Port G dedicated output PG8 PG15 25 18 39 32 O Port G dedicated output Pins PD4 and PD5 may be dedicated to the comparator function if the comparator enable bit is set Refer to Section 3 3 Comparator for details Scan Port Control Signals SCANIN 42 54 Scan port data input SCANOUT 38 50 Scan port data output SCANCLK 41 53 Scan port clock SYNC 40 52 l Scan port synchronization TEST 39 51 MSP50C6xx test modes The scan port pins must be bonded out on any MSP50C6xx production board Consult the Important Note regarding Scan
115. to R5 INDEX SYNTAX name dest src dma16 2 next A name dma16 2 src next A name dest src Rx offset16 next A name Rx offset16 src next A name dest src Rx R5 next A name Rx R5 src next A OPERATION Second word operand dma16 used directly as memory address Selects one of 8 address registers as base value and adds the value in the second word operand Does not modify the base address register Selects one of 8 address registers as base value and adds the value in R5 Does not modify the base address register Indirect Short Relative name dest src Rx R5 next A name dest src Rx next A name dest src Rx next A name dest src Rx next A name Rx R5 src next A name Rx src next A name Rx src next A name Rx src next A name dest src R6 offset7 next A name R6 offset7 src next A Selects one of 8 address registers to be used as the ad dress post modifications of increment decrement and INDEX R5 are possible Selects PAGE R6 register as the base address and adds a 7 bit positive address offset from operand field b6 b0 This permits the relative addressing of 128 bytes or 64 words Does not modify the PAGE address register k is shown as constant Global Flag Relative Flag name TFn dma6 name dma6 TFn name TFn R6 offs
116. to access individual bytes with an instruction in byte mode Such instructions have a suffix B at the end of instruction name for example ADDB MOVB etc A byte string 4 44 Bit Byte Word and String Addressing is a string of bytes The length of the byte string is stored in the string register STR To define the length of a string the STR register should hold the length of the string minus 2 For example if the length of a byte string is 10 then STR should be 8 A byte string address can be even or odd Byte string data is fetched from the lower address starting address one byte at a time to consec utive addresses p M A NOTE Data Memory Access Data memory access RAM is always accessed with byte addresses Pro gram memory ROM is accessed with 17 bit words Rx registers autoincre ment or autodecrement by 1 for byte addressing by 2 for word addressing or by the length of the string in bytes if Rx or Rx is used Word and Word String Addresses One data memory word is composed of two consecutive bytes A word address is always an even byte address and the least significant bit of the byte address is assumed to be zero Instructions that operate on words have internal hardware which increments the byte ad dress appropriately to load the two consecutive bytes in one clock cycle To use an absolute word address the address should be multiplied by 2 A word string is a str
117. to initial the processor state in Table 4 43 AO points to AC2 Consider a program memory location string of length 4 at 0x1400 OxCDEF89AB45670123 STR equal to 4 2 2 defines a string length of 4 Final result AC220x0123 AC3 0x4567 AC4 0x89AB and AC5 0xCDEF Example 4 8 2 MOV STR 3 2 string length 3 ADDS Al Al 0x0200 Refer to the initial processor state in Table 4 43 A1 is AC21 A1 is AC5 the Assembly Language Instructions 4 55 String Instructions 4 56 A1 string is OX233EFBCA1223 and 0x200 0x9086EE3412AC STR 3 2 1 defines a string length of 3 Final result Al string 0x233EFBCA 1223 0x9086EE3412AC 0xB3C5E9FE24CF AC5 0x24CF AC6 0xE9FE AC7 0xB3C5 STR 2 unchanged Notice that this instruction has accumulated a carry Special String Sequences There are two string instructions that have a special meaning If any of the following instructions MULAPL MULSPL MULTPL SHLAPL SHLSPL SHLTPL EXTSGNS MOVAPH immediately precedes ADDS An An PH and SUBS An An PH the following things happen 1 Carry generated by the preceding instruction is used in computation 2 Interrupts can occur between these instructions 3 Allinstructions in the sequence execute as a single string operation So An accumulator pointed by the first instruction of the sequence should be used for the remaining instructions in the sequence and changing the value of non one of the above instructions in the sequence
118. within the accumulator The following table shows the bit locations of the port F address mapping F port Input Data register address 0x28h 8 bit wide location READ only 07 06 05 04 03 02 01 00 E7 F6 F5 F4 F3 F2 F1 FO The external interrupt INT5 is triggered by a falling edge event on any of the eight port F input pins see Section 3 1 5 nternal and External Interrupts The F port input pins are gated through an eight input AND gate such that any input pin going low causes the output of the AND gate to go low Therefore if any input pin is held low the device will not trigger INT5 when another input is taken low Specifically INT5 is triggered if all eight port F pins are held high and then one or more of these pins is taken low This allows port F to be espe cially useful as a key scan interface 3 1 3 Dedicated Output Port G Port G is a 16 bit wide output only port The output drivers have a Totem Pole configuration The data driven by the output pin can be controlled by setting or clearing the appropriate bit in the G port data register address 0x2C This is done using the OUT instruction with the 0x2C address as an argument The port G outputs are set to 0 logic low when the RESET pin is taken low This condition is maintained after RESET is taken high and until the G port data register is modified Peripheral Functions 3 5 VO Totem Pole Output Port G 0x2Ch N A Data register address Possible input da
119. zero status flag bit 16 bits This bit is set to 1 if the result of previous instruction cause the destination accumulator to become zero Accumulator carry out status flag bit 16th ALU bit Test Flag 1 Test flags are related with Class 8 instructions discussed later Test Flag 2 Test flags are related with Class 8 instructions discussed later Memory tag Holds the 17th bit whenever a memory value is read Assembly Language Instructions 4 7 Instruction Syntax and Addressing Modes 4 3 Instruction Syntax and Addressing Modes MSP50P614 MSP50C614 instructions can perform multiple operations per instruction Many instructions may have multiple source arguments They can premodify register values and can have only one destination The addressing mode is part of the source and destination arguments In the following subsec tion a detail of the MSP50P614 MSP50C614 instruction syntax is explained followed by the subsection which describes addressing modes 4 3 1 MSP50P614 MSP50C614 Instruction Syntax All MSP50P614 MSP50C614 instructions with multiple arguments have the following syntax name dest src src1 mod where the symbols are described as follows name name of the instruction Instruction names are shown in bold letters If the instruction name is followed by a B the arguments are all byte types If name is followed by an S all arguments are word string strings of words types If name is followed by BS a
120. 0x0200 2 RO Store RO to data memory word location 0x0200 Example 4 14 28 16 Transfer R5 to RO Example 4 14 28 17 Copy content of data me Example 4 14 28 18 OV RO R5 OV AP2 R3 mory location stored in R3 to accumulator pointer AP2 OV R6 8 2 DP Copy data pointer DP to data memory word location pointed by R6 offset by 8 location short relative addressing Example 4 14 28 19 Copy the STR register w Example 4 14 28 20 Copy TF2 flag to the flag Example 4 14 28 21 Copy status of ZF flag in Example 4 14 28 22 OV STR 0x0200 2 ith the content of word memory location 0x0200 OV R6 0x20 TF2 bit in relative flag location R6 offset by 0x20 OV TF1 ZF STAT register to TF1 OV SV 4 2 Load SV register with a constant value 2 Example 4 14 28 23 OV AP3 23 16 Load accumulator pointer AP3 with value 7 4 120 Individual Instruction Descriptions 4 14 29 MOVAPH Move With Adding PH Syntax MOVAPH An MR aars Table 4 46 Table 4 46 Execution An An PH MR lt contents of adrs PC PC w Flags Affected TAG OF SF ZF CF are set accordingly Opcode Instructions 1e rs rera 12 11 o Jo Je v e sajoja Jo a Puna a 0i dma16 for direct or offset16 long relative see section 4 13 Description Move RAM word to MR register add PH to An in parallel See Also MOVAPHS MOVTPH MOVTPHS MOVSPH MOVSPHS Example 4 14 34 1 MOVAPH A0 MR
121. 1 7 1 Mechanical Information isses IH 7 2 7 1 4 Die Bond Out Coordinates 0 ccc ees 7 2 7 1 2 Package Information reiks tenka AE A eh 7 2 7 2 Customer Information Fields in the ROM ooococccccccccncccncc eee es 7 11 7 8 Speech Development Cycle 0 cc ee 7 12 7 4 Device Production Sequence 0 cece ees 7 12 7 5 Ordering Information 00 hh 7 14 7 6 New Product Release Forms NPRF 0 cece eee eee eee eee eee 7 14 A Additional Information essseeeeeee III A 1 A 1 Additional Information oococcccccccccccc e A 2 Lod ot d omn WDM Ld l 00 Y O Ol Op nm 4 4 7 5 Figures Functional Block Diagram for the MSP50C614 MSP50P614 Lussssss 1 5 Oscillator and PLL Connection sesanan aaen eee eens 1 7 RESET GIrcult tnni Pate Siete LU PUT EE RD PHA cee eee 1 8 MSP50C6xx Core Processor Block Diagram 0006c cece cece 2 3 Computational Unit Block Diagram 0c cece eens 2 4 Overview of the Multiplier Unit Operation sunaa cece eee 2 7 Overview of the Arithmetic Logic Unit 0 2 9 Overview of the Accumulators 0000 o 2 10 Data Memory Address Unit 0 00 ccc cee ene ee 2 12 C6xx Memory Map not drawn to scale 000 cece eee eee 2 16 Interrupt Initialization Sequence 0 00 ce eee eee 2 25 PLE Performarice oret ERN
122. 3 H external portF H external pd4 i external pd5 At the bottom of the file are a dummy interrupt routine and the interrupt vector table pd2 pd3 portF pd4 pd5 DAC ISR timerl_isr timer2 isr nop INTE iret AORG 07F00h DATA EQ NE LT LE GE GT ULT ULE UGE UGT LNEG DATA EQS ES LTS LES GES GTS ULTS ULES UGES UGTS DATA DIV DIVU EXTB ASR AORG 07FFO0h data DAC ISR the DAC interrupt is used for synthesis data timerl_isr this is the timerl isr data timer2 isr this is the timer2 isr data pd2 data pd3 data portF data pd4 data pd5 aorg Ox7ffe data CXL ELE ROM protection word 0x7ffe data init614 reset address 0x7fff Notice that timer2 was not commented out at the top of the file but it is commented out in the dummy interrupt routine External interrupt routines are switched on by not commenting them at the external statement at the top of the file and commenting them in the dummy interrupt routine They are switched off by commenting their external statement at the top and not commenting the label in the dummy routine at the bottom Note that this does not enable or disable an interrupt it just controls what is executed when it fires Interrupt routines will be enabled and disabled in the next file but itis important to provide a dummy routine for unused interrupts in case a programm
123. 4 32 Instruction Classification Table 4 20 Class 3 Instruction Description Continued e CN peseinin 1 1 MOV SV An next A Transfer accumulator A 0 or offset accumulator A 1 MOVS SV An to SV register Transfer status is modified MOV PH An next A Transfer accumulator A 0 or offset accumulator A 1 MOVS PH An to PH register Transfer status is modified MOV MR An next A Transfer accumulator A 0 or offset accumulator A 1 MOVS MR An to MR register in the signed multiplier mode UM bit in status register set to 0 Transfer status is modified MOVU MR An next A Transfer accumulator A 0 or 1 to MR register in the unsigned multiplier mode UM bit set to 1 Transfer status is modified MULSPL An An L next A Multiply the MR register by accumulator A 1 or offset MULSPLS An An accumulator A 0 subtract lower 16 bits of the product from the offset accumulator A 1 or accumulator A 0 Store in the accumulator A 0 or offset accumulator A 1 Latch the upper 16 bits in PH ALU status is modified MULAPL An An next A Multiply MR register by accumulator A 1 or offset MULAPLS An An accumulator A 0 add lower 16 bits of product to offset accumulator A 1 or accumulator A 0 and store to accumulator A 0 or offset accumulator A 1 Latch upper 16 bits in PH ALU status is modified SHLTPL An An next A Barrel sh
124. 5 04 03 02 01 00 R R IM TM TM TM TM TM GP BP R FM FM FM FM FM FM 05 04 03 02 01 00 05 04 03 02 01 00 True Protection Marker Ny GP Global Protection 0 value protects False Protection Marker Nep BP Block Protection 0 value protects Reserved for future use must be 1 1 Default value of cells on erasure The two 6 bit fields are designated as the true protection marker TM5 through TMO and the false protection marker FM5 through FMO When setting up a partition for partial ROM protection the address of the partition must be spe cified as 2 20 Memory Organization RAM and ROM Nim 1 512 1 highest ROM address within the block to be protected NTM 1 512 lowest ROM address which is left unprotected NTM the value programmed at TM5 TMO true protection marker Nem the binary complement of Nr y Nem the value programmed at FM5 FMO false protection marker The purpose of the true and false protection markers is to provide parity An erased P614 EPROM cell defaults to the value 1 Once programmed from 1 to 0 it cannot be programmed back to 1 unless the cell and all other cells along with it are subject to erasure A multi pass programming therefore can only lower the value stored at an EPROM address and never raise it Once a valid block partition address has been properly specified in both TM and FM itis impossible to change TM to another address and still maintain parity with
125. 6 Hmod Rmod Rx Rx Rx R5 Execution IF condition true OR unconditional PC pmal6 ELSE NOP PC PC 2 if post modification specified IF Rmod Rx Rx Rx 2 ELSE IF Rmod Rx Rx Rx 2 ELSE IF Rmod Rx R5 Rx Rx R5 Flags Affected RCF and RZF affected by post modification of Rx 4 110 Individual Instruction Descriptions Opcode instructions pre fas f a Pta 12 f to e e ejs a a 2 o dcc pmat t p os pono ope Non s prec po ees EA p iH uuo o m E Jeo pma16 Rx ipofofolofofwr _ c rx oj Jeo pma16 Rx ipofofofofofwr _ oc Rc ito A ee e Joo pma16 Rx R5 CMA A EE Bl mms pma16 cc names _ Description m B be name True condition Not true condition Z Conditional on ZF 1 Not condition ZF 0 Conditional on SF 1 Not condition SF 0 Conditional on CF 1 Not condition CF 0 Conditional on ZF 0 and CF 0 Not condition ZF 0 or CF 0 Conditional on ZF 0 and CF 1 Not condition ZF 0 or CFz1 Conditional on SF 0 and ZF 0 Not condition SF 0 or ZF 0 Conditional if ZF 1 and OF 0 Not condition ZFz1 or OFzO Conditional if OF 1 Not condition OF 0 Conditional on RCF 1 Not condition RCF 0 Conditional on RZF 0 and RCF 1 Not condition RZF 0 or RCFz1 Conditional on RZF 1 Not condition RZF 0 RZP Conditional on value of Rx 0 Not condition RxzO RLZP RNLZP Conditional on MSB of Rx 1 Not condition MSB of Rx 0 NL Conditional on ZF 0 and SF 1 Not condi
126. 6 Table 4 46 Execution memory tag bit at address adrs 1 PC PC w Flags Affected None Opcode Ez jejsjajsja o EEN STAG adis EME IE E E IS 3 dma16 for direct or offset16 long relative see section 4 13 Description Sets the tag bit at the addressed memory location All addressing modes are available Note that this instruction accesses only the 17th bit of the RAM location The argument adrs is interpreted as bytes For odd RAM byte addresses the least significant bit is ignored See Also RTAG RFLAG SFLAG Example 4 14 79 1 STAG R2 R5 Set TAG bit of the word in RAM byte address R2 R5 R2 and R5 remain unchanged Example 4 14 79 2 STAG 0x200 2 Set TAG bit of RAM word 0x200 RAM byte address 0x400 Example 4 14 79 3 STAG 0x401 Set TAG bit of RAM word 0x200 RAM byte address 0x400 Assembly Language Instructions 4 175 Individual Instruction Descriptions 4 14 80 SUB Subtract Syntax iate name dest se ser renal Gies ok Word w win ner ok Toress sus Ani An acts next A su Jaca anh mis nena 2 2 NR 2 sua am Ani nea ma 3 sus aranana 1 mma a sue arctan ant nena 1 ma a O su anime a e m we su cs A a 4 Execution premodify AP if mod specified dest dest src1 for two operands dest src src for three operands PC PC w Flags Affected destis An OF SF ZF CF are set accordingly dest is Rx RCF RZF are set accordin
127. 6 vector at OX7FF6 Refer to Section 2 7 Interrupt Logic for more details Peripheral Functions 3 15 Comparator The INT6 Flag may also be SET or CLEARed deliberately at any time in software Use the OUT instruction with the associated l O port address IFR address 0x39 INT7 flag refers to bit 7 within the interrupt flag register This bit is automatically SET anytime that an INT7 event occurs This causes the device to branch to the INT7 vector if the associated mask bit is set IntGenCtrl address 0x38 bit 7 The INT7 flag is automatically cleared when the device branches to the INT7 vector at OX7FF7 The INT7 Flag may also be SET or CLEARed at any time in software Use the OUT instruction with the associated I O port address IFR address 0x39 The TIMER1 enable bit is set or cleared in software bit 10 of the IntGenCtrl Similarly the falling edge event in the comparator is a trigger for INT7 This happens independently of any activity associated with TIMER1 TIMER1 can be started by the falling edge of the comparator The INT6 flag must be cleared and the TIMER1 ENABLE must be cleared before the event Figure 3 2 Relationship Between Comparator Interrupt Activity and the TIMER1 Control INT Trigger Event Associated With the Interrupt Trigger Event Interrupt Flag Register 0x39 INT Service port addressed Branch write instruction INT Flag bits IFR TIMER1 ENABLE Bit 10 IntGenCtrl 0x38
128. 7 NEGAC Two s Complement Negation of Accumulator Syntax label name dest src mod Clock clk With RPT clk NEGAC Ar Art next A Execution premodify AP if mod specified dest src PC PC 1 Flags Affected OF SF ZF CF are set accordingly Opcode instructions Pro 15 14 fia 12 n 10 o Je 7 e 8 a Pa 2 1 fo NEGAC An An p nexa 1 1 1 fo o neta an fo foo foo o a A Description Perform two s complement negation of srcaccumulator and store result in dest accumulator See Also NEGACS SUB SUBB SUBS ADD ADDB ADDS NOTAC NOTACS Example 4 14 47 1 NEGAC A3 A3 A Predecrement accumulator pointer AP3 Negate accumulator A3 and store result in accumulator A3 4 142 Individual Instruction Descriptions 4 14 48 NEGACS Two s Complement Negation of Accumulator String Syntax labe rame aest sre crock ok Word w With RPT ck Class NEGACS Ari Ari Execution dest src PC PC 1 Flags Affected OF SF ZF CF are set accordingly Opcode Instructions Pro 15 1a ra 12 fn to o e v e s a js 2 Jo wursPLSAn An t rs rjo ojs t an jo ojopog opo a A Description Perform two s complement negation of src accumulator string and store result in dest accumulator string See Also NEGAC SUB SUBB SUBS ADD ADDB ADDS NOTAC NOTACS Example 4 14 48 1 NEGACS A3 A3 Negate accumulator string A3 and stor
129. 9 4 12 Conditionals rasen ea adi 4 69 4 13 MOON ori a AA Acn dco a REOR CEDERE Md 4 70 4 14 Individual Instruction Descriptions ooooocococcccccocncn RR 4 74 4 15 Instruction Set Encoding ssssa sssaaa aaeeea ees nh 4 189 4 16 Instruction Set Summary 000 cc tee nent eee 4 198 Code Development Tools 0c ccc cece cece cece eee eee ene eeeeeeeennnees 5 1 5 1 INWOGUCTION conmocionado dales 5 2 5 2 MSP50C6xx Development Tools Guidelines 0 00 eee eee 5 4 5 2 1 Categories of MSP50Cxx Development Tools 00222e cece eee 5 4 5 2 2 Tools Definitions lt 2 20 0 Ero e eke beeen A ree ane 5 5 5 2 3 Documentation omitir aia peso i Qe 5 8 5 3 MSP50C6xx Code Development Tools cece eee eee eee eee eae 5 8 5 3 1 System Requirements 000 c cece eee eens 5 8 5 3 2 Hardware Tools Setup 00 5 9 5 4 Assembler seso a E cerae ati tr ab e e R 5 11 5 4 4 Assembler Directives ssseessseeseseee eee 5 11 5 US Compiler iets cee ssf A E 5 16 DoT cEOLGWOIO it treten ied ee ete 5 16 5 5 2 Variable Types sis cicle ater wd Ga ae wd PERRA ERR ea a RE 5 17 5 5 3 External References 0 cece cece eee eee eens 5 17 5 5 4 C Directives ori at iaaa i iiaa a iA a A E EE 5 18 5 5 5 INCIUGS FoS oan a EH EE eR eH EA 5 19 5 5 6 Function Prototypes and Declarations usuau aaan nee 5 21 5 5 4 InrtialiZatiOris iaa teed aed des 5 21 5 5 0
130. AO by a 16 bit integer located in AO We return the quotient in AO and the remainder in AO We make use of A3 and A3 for scratch pads We also set flag 1 if a division by zero is attempted and zero out the quotient and the remainder in this case We also use PH for temporary storage of the divisor 5 6 3 Function Calls 5 26 Every function is associated with a stack frame A regular C program is initially given control by a call to main A C program starts with a jump to the _main symbol which must therefore be present in the C source code The stack frame has the following structure First Argument Low Adaress eee v i i SP MEE High Address BP is the frame pointer base pointer SP the stack pointer We use R7 for stack pointer and yet another register for BP REG BP R5 because of its special arithmetic capabilities Before a function is called the arguments are pushed on the stack first argument first The function call automatically pushes the return address on the stack Immediately upon entering the function body the current BP is pushed on the stack to preserve it so that the stack pointer now points to the next location This location is copied to REG BP which becomes our fixed reference point for the current function Locals are then allocated on the stack from this starting location When the function returns SP is made to point to the return address after the previous BP is poppe
131. Al Subtract accumulator A1 from accumulator A1 put result in accumulator A1 Example 4 14 80 4 SUB Al Al Al A Pre decrement AP1 Subtract accumulator A1 from accumulator A1 put result in accumulator A1 Example 4 14 80 5 SUB A3 A3 R4 Subtract word at address in R4 from A3 store result in A3 decrement value in R4 by 2 word mode after the subtraction Example 4 14 80 6 SUB R3 R5 Subtract R5 from R3 put result in R3 Assembly Language Instructions 4 177 Individual Instruction Descriptions 4 14 81 SUBB Subtract Byte Syntax iae rame ses se Clock ok wora w With RPT ok crass P suse jam wa a sws rx imma a Execution dest dest imm8 PC PC 1 Flags Affected dest is An OF SF ZF CF are set accordingly dest is Rx RCF RZF are set accordingly Opcode DL rara EDI EC ERE su i ppp fet me TINI dele Tere Description Subtract value of src byte from value of destbyte and store result in dest Note that subtraction is performed in 2 s complement and therefore the CF carry flag may get set even when subtracting a smaller value from a larger value SUBB An imma Subtract immediate byte from An SUBB Rx imm8 Subtract immediate byte from Rx Example 4 14 81 1 SUBB A2 0x45 Subtract 0x45 from accumulator A2 byte Example 4 14 81 2 SUBB R3 OxF2 Subtract OxF2 from register R3 byte 4 178 Individual Instruction Descriptions 4 14 82 SUBS Sub
132. As a side effect local static variables are not allowed For example a global array can be declared and initialized as follows int int array 5 1 2 3 4 5 Initialization values are stored in program memory RAM location 0 is reserved and used intensively by the compiler The choice of location O does not conflict with the usual definition of a NULL pointer Code Development Tools 5 21 C Compiler 5 5 9 String Functions Arithmetic string functions are special functions that perform string arithmetic The functions currently implemented are shown in Table 5 1 Table 5 1 String Functions add_string int result int strl int str2 int lg adds strings strl and str2 of length lg 2 and puts the result in string result sub string int result int strl int str2 int 1g subtracts strings str2 from str1 of length lg 2 and puts the result in string result mul string int result int strl int mult int lgl int lgr multiplies string strl of length lg1 2 by integer multiple and puts the result in string result of length lgr 2 umul string int result int strl int mult int lgl int lgr same as previous one with UNSIGNED multiply or string int result int strl int str2 int 1g ors strings strl and str2 of length lg 2 and puts the result in string result and string int result int strl int str2 int 1g ands strings strl and str2 of length lg 2 and puts the result in string result xor
133. Books Medical Aids for the Handicapped Y Security Security Systems Home Monitors Introduction to the MSP50C6xx 1 3 Development Device MSP50P614 1 3 Development Device MSP50P614 The MSP50P614 is an EPROM based version of the MSP50C614 and is available in a 120 pin windowed ceramic pin grid array This EPROM based version of the device is only available in limited quantities to support software development Since the MSP50P614 program memory is EPROM each person doing software development should have several of these PGA packaged devices The MSP50P614 is also used to emulate the MSP50C601 MSP50C604 and MSP50C605 with the addition of external logic The MSP50C6xx code development software EMUC6xx supports non real time debugging by scanning the code sequence through the MSP50C6xx MSP50P614 scanport without programming the EPROM However the rate of code execution is limited by the speed of the PC parallel port Any MSP50C6xx MSP50P614 can be used in this debugging mode The MSP50P614 EPROM must be programmed to debug the code in real time The EMUC6xx software is used to program the EPROM set a break point and evaluate the internal registers after the breakpoint is reached If a change is made to the code the code will need to be updated and programmed into another device while erasing previous devices This cycle of program ming debugging and erasing typically requires 10 15 devices to be in the eraser at
134. C once reference is enabled RTO oscillator trim bits are set to zero renders slowest speed for RTO once enabled Interrupt mask register is Ox00 Global interrupt enable is clear All Interrupts are disabled I O Ports A through E and output Port G have the same state as in RESET low All pull up resistors on input Port F are disabled DAC circuitry is disabled no PDM pulsing Both TIMER1 and TIMER are disabled Count down and period registers are 0x0000 The status register is partially initialized as specified in Table 3 2 Idle state clock control and ARM bit are both set to zero E C DOT O LE dB The processor begins by executing the following steps k ROM block protection word is read from address Ox7FFE 2 ROM block protection word is loaded to an internal register 3 RESET interrupt vector is read from address Ox7FFF 4 Program counter is loaded with the value read from 3 execution re sumes there A eee n5 Note Stack Pointer Initialization The software stack pointer R7 must be initialized by the programmer so that it points to some legitimate address in data memory RAM This must be done prior to any CALL or Ccc instruction If this is not done then the first push pop operation performed will use the current location pointed to by R7 o Peripheral Functions 3 21 Hardware Initialization States Table 3 2 State of the Status Register 17 bit after RESET Low to Hig
135. CC oe dma16 for direct or offset16 long relative see section 4 13 wwxusw 1010 0 001010 0100101015835 Movs PH An Pa Pipi fofoji 1 an tjogso 1o a jo CA 5159 5 Ce ON EA EA EEES E Movs agp rn t a a fofoj1 1 an fojifaiji fojo fa f a CA EE AECA CA EAN E Movs MRA Pa ip fofoj1 1 an fijofiji fojo fafo EE 7 05 poter AECA A EE MOVT add TFn npliebliebbble ses x dma16 for direct or offset16 long relative see section 4 13 e es eee pe edee i acabar dma16 for direct or on long relative see section 4 13 ee peo 0s dma16 for direct or offset16 long relative see section 4 13 SN OCC m dma16 for direct or offset16 long relative see section 4 13 menus peheee e dma16 for direct or offset16 long relative see section 4 13 r ojojs oto An gt gt gt as dma16 for direct or offset16 long relative see section 4 13 mut anneta Ji f 1fofofrera Ao 1 1 11 1 Jo o JA o MOVSPHS An MR aars Assembly Language Instructions 4 193 Instruction Set Encoding Instructions fa fas papis feju Hope fs 7 e s a a 2 t o MUL adrs MULR aars MULS An MULAPL An aars MULAPL An An next A MULAPLS An adrs MULAPLS Ar An MULSPL An adrs MULSPL Ar An next A MULSPLS An aars MULSPLS Ar An MULTPL Ar adrs MULTPL An An next A MUL TPLS An aars MULTPLS An Ar NEGAC Ar An
136. COND2 TRUE CIN2 has its conditional call taken JIN2 has its conditional jump taken CNIN2 has its conditional call ignored JNIN2 has its conditional jump ignored 2 Steady State Comparator FALSE Vpps5 lt Vpp4 COND2 FALSE CIN2 has its conditional call ignored JIN2 has its conditional jump ignored CNIN2 has its conditional call taken JNIN2 has its conditional jump taken 3 Comparator transition FALSE to TRUE Vpps rises above Vpp4 INT6 trigger event If interrupt mask bit D4 is set TIMER1 stops counting If INT7 flag was set and TIMER1 ENABLE was cleared 4 Comparator transition TRUE to FALSE Vpps falls below Vpp4 INT trigger event If interrupt mask bit D5 is set TIMER1 starts counting If INT6 flag was cleared and TIMER1 ENABLE was cleared With regards to the transition events the rising edge in the comparator is a trigger for INT6 This happens independently of any activity associated with TIMER1 TIMER1 on the other hand can be stopped by a rising edge of the comparator The INT7 flag must be set and the TIMER1 ENABLE must be cleared before the event INT6 flag refers to bit 6 within the interrupt flag register IFR peripheral port 0x39 This bit is automatically SET anytime that an INT6 event occurs This causes the device to branch to the INT6 vector if the associated mask bit is set IntGenCtrl address 0x38 bit 6 The INT6 flag is automatically CLEARed when the device branches to the INT
137. CPU Clock rate Setting the PDMCD bit results in a PDM rate equalto the MC After RESET is held low the default setting for the PDMCD bit is zero PDM rate 1 2 MC Figure 3 1 PDM Clock Divider MC PDMCD PDM Clock Divider Bit 13 in IntGenCtrl PDM Rate Master Clock 131 07 kHz 33 554 MHz Pulse Density Modulation Rate Governs DAC Capacity rate adjusted in ClkSpdCtrl 65 536 kHz FMAX frequency or 131 07 33 554 MHz CPU Clock Core Processor Speed 65 536 kHz FMAX 8 MHz is max assured see Chapter 9 Peripheral Functions 3 11 Digital to Analog Converter DAC For a given sampling rate and DAC resolution the CPU clock rate may be increased if necessary through the use of over sampling In the previous example an original sampling rate of 8 kHz and a PDM rate of 4 MHz was used A 2 times over sampling therefore would require the PDM rate to be 8 MHz This can be accomplished in two ways PDM rate 8 MHz Set the master clock to 8 MHz also CIkSpdCtrl Set the PDMCD bit to 1 1x master clock IntGenCtrl CPU clock rate will be 4 MHz PDM rate 8 MHz Set the master clock to 16 MHz Set the PDMCD bit to 0 1 2 master clock CPU clock rate will be 8 MHz In the case of over sampling the same number of instructions are achievable between each INTO interrupt Not every INTO however requires an independently computed synthesis value hence the advantage in increased instruction c
138. Condition mnemonic mnemonic mnemonic mnemonic Zero flag ZF NZF Sign flag SF NSF Carry flag CF NCF Below unsigned B NAE NB AE Above unsigned A NBE NA BE Greater signed G NLE NG LE Equal E NE Overflow flag OF NOF Less signed L NGE NL GE Rx carry flag RCF RNCF Rx above unsigned RA RNBE RNA RBE Rx equal RE RZ RNE RNZ Test flag 1 TF1 NTF1 Test flag 2 TF2 NTF2 Memory tag TAG NTAG Input line 1 IN1 NIN1 Input line 2 IN2 NIN2 Transfer zero flag XZF XNZF Transfer sign flag XSF XNSF Transfer greater signed XG XNLE XNG XLE T Alternate mnemonics are provided to help program readability They generate the same opcodes as the associated condition t Status register STAT bit settings are inverted for NOT conditions Hardware lines used for I O expansion design These lines are PAO and PA1 Assembly Language Instructions 4 69 Legend 4 13 Legend name dest src Src1 mod Symbol An An 4 70 All instructions of the MSP50P614 MSP50C614 use the following syntax name dest src src1 mod Name of the instruction Instruction names are shown in bold letter through out the text Destination of the data to be stored after the execution of the instruction Optional for some instructions or not used Destination is also used as both source and destination for some instructions Source of the first data Optional for some instructions or not used Source of the second data Some instructions use a second
139. D instruction INTE sets the global interrupt enable bit and INTD clears the global interrupt enable bit The state of this bit specifically determines whether any interrupt service branches will be taken The global interrupt enable appears as bit 4 within the status register STAT q d Note To ensure proper executions of the INTD instruction itis recommended that the INTD instruction be prescaled with a RPT 2 2 instruction Cd Each interrupt level waits for the conditions of its trigger event refer to Figure 2 8 At the time that a trigger event occurs the respective bit is Interrupt Logic automatically SET in the interrupt flag register IFR The IFR is an 8 bit wide port addressed register wherein each interrupt level is represented A set bit in the IFR indicates that the interrupt is pending and waiting to be serviced A clear bit indicates that the interrupt is not currently pending The address of the IFR is 0x39 After a RESET low the IFR is left in the same state it was before the RESET low assuming there is no interruption in power For a full description of the interrupt trigger events refer to Section 3 1 5 nternal and External Interrupts 8 bit wide location 07 06 05 04 03 02 01 00 lt INT number IFR Interrupt Flag register D5 D4 PF D3 D2 T2 Ti DA address 0x39 low high priority priority port Ds falling edget PF any port
140. Data Memory Peripheral Ports 0x0000 Internal Test Code X0000 RAM 0x00 PAg_7 data CELL 640 x 17 bit 0x04 PAg_7ctrl 0x027F 0x08 PBg 7 data Ox07FF reserved 0x0800 0x0C PBo 7 ctrl 0x10 PCo 7 data User ROM 30704 x 17 bit 0x14 PCo 7 ctrl C6xx read only 0x18 PDo 7 data P614 EPROM oxic PDo_7 ctrl 0x7F00 0x20 PEg_7 data Macro Call Vectors 0x24 PE 7 ctrl 255 x 17 bit overlaps interrupt 0x28 PFo_7 data vector locations 0x2C PGo 15 data Ox7FFO Usable Interrupt 0x2F RTRIM DECRE 0x30 DAC data 8 x 17 bit Ox7FF7 0x34 DAC ctrl Ox7FF8 Unusable Interrupt Vectors 0x38 IntGenCtrl QUFEE RESET vector Ox3A PRD1 0x3B TIM1 0x3D ClkSpdCtrl Shaded boxes highlight dedicated ROM and control registers Ox3E Ox3F TIM2 2 6 2 Peripheral Communications Ports 2 16 Peripheral functions in the C6xx are controlled using one or more of the I O address mapped communications ports Table 2 2 describes the ports The width of each mapped location shown in width of location is independent of the address spacing In other words some registers are smaller in width than the spacing between neighboring addresses The few unused bits appear to the right of the LSB values within the DAC Data register address 0x30 refer to Section 3 2 2 DAC Control and Data Registers Memory Organization RAM and ROM When writing to any of the locations in the I O address map therefore the bit masking need only extend as far as width of location Within a
141. ECTION 3 AUTHORIZATION TO GENERATE MASKS PROTOTYPES AND RISK UNITS This section is to be completed by the customer and sent to TI after the following criteria have been met 1 The customer has verified that the TI computer generated data matches the original data Customer Information 7 15 New Product Release Forms NPRF 2 The customer approves of the symbolization format in Section 2B Applies to packaged devices only I hereby certify that the TI generated verification data has been checked and found to be correct and I authorize TI to generate masks prototypes and risk units in accordance with purchase order in section 1 above In addition in the instance that this is a packaged device I also authorize TI to use the symbolization format illustrated in section 2B on all devices By Title Date FAX this form to 214 480 7301 Attn Code Release Team kk Ck ck ck ck Ck Sk ck Ck ck Ck Sk ck Ck ck KK KKK KKK ck Ck ck KKK KK KKK ck kk ck kk ck kk ck kk kk ck kk ck kk ck kk ko kk Ck kk ko kk kk KKK KK KKK KK SECTION 4 APPROVAL OF PROTOTYPES AND AUTHORIZATION TO START PRODUCTION This section is to be completed by the customer after prototype devices have been received and tested I hereby certify that the prototype devices have been received and tested and found to be acceptable and I authorize TI to start normal production in accordance with purchase order By Title Date
142. FIR instruction 32 bit accumulation COR instruction uses 48 bit accumulation and includes accumulator ACr 2 Assembly Language Instructions 4 67 Special Filter Instructions Figure 4 7 Filter Instruction and Circular Buffering for N 1 Tap Filter Rxeven 4 if TAG 2 1 6 4H R5 2 N 1 16 Bits CORK FIRK only COR FIR only 17th Bit STAT 16 Bits 171 Bit X K N 1 is replaced by x k 1 sample buf coeff array is stored in program or data memory based on filter instruction program memory FIRK CORK data memory FIR COR H y Eco N him x xfk m MM N 48 bit accumulation for COR CORK l 32 bit accumulation for FIR FIRK 4 68 Conditionals 4 12 Conditionals STAT register bit settings ZF 1 SF 1 CF 1 ZF 0 amp CF 0 ZF 0 amp CF 1 ZF 1 amp SF 0 ZF 1 amp 0F 0 OF 1 ZF 0 amp SF 1 RCF 1 RZF 0 amp RCF 1 RZF 1 TF1 1 TF2 1 TAG 1 IN18 IN28 XZF 1 XSF 1 XZF 0 amp XSF 0 The condition bits in the status register STAT are used to modify program control through conditional branches and calls Various combinations of bits are available to provide a rich set of conditional operations These condition bits can also be used in Boolean operations to set the test flags TF1 and TF2 in the status register NOT t NOT condition Arithmetic Logic Condition Alternatet condition alternatet
143. ISRs and mainasm asm Assembly routines for built in C functions and ISR vector table Project file generated by MSP50C6xx development tool Directory for ISRs general purpose files and plugable modules Directory holding general purpose files for initialization and mnemonics Initializes the clock on startup Mnemonics for the io ports Directory for ISRs Timer 2 interrupt service routine Directory for top level ram allocation files Holds the bogus array used by C Top level memory allocation C Efficiency Seven of the files are important to the functionality of this project The Timer2 ISR tim2_isr asm forms the basis for the RTC so it will be discussed first timer2_isr mov save tim2 stat STAT save status mov save tim2 a0 a0 save a0 timer fired so 1 second passed update the variable storing the seconds passed so far mova0 seconds passed adda0 a0 1 mov seconds passed a0 mov a0 save tim2 a0 restore a0 mov STAT save tim2 stat restore status inte turn interrupts back on iret The Timer2 ISR is configured to fire at 1 second intervals Each time the ISR executes it saves any registers that it will modify increments the RAM location seconds passed and restores the registers it modified The second important file is main ram irx It is used to allocate RAM for seconds passed and for saving and restoring registers in the Timer2 ISR PRE EREKE KERER ERR ERS PERLRA RE EEE AERA RAR oleae ARE ge OE
144. If used in a called subroutine return from subroutine Assembly Language Instructions 4 109 Individual Instruction Descriptions 4 14 26 Jcc Conditional Jumps Syntax label name pma16 Rmod Clock clk With RPT clk vec pmat6 Rmod If true If Not true label JZ pma16 Rmod label JNZ pma16 Rmod label JS pma16 Rmod label JNS pma16 Rmod label JC pma16 Rmod label JC pma16 Rmod label JG pma16 Rmod label JNG pma16 Rmod label JE pma16 Rmod label JNE pma16 Rmod label JA pma16 Rmod label JNA pma16 Rmod label JB pma16 Rmod label JNB pma16 Rmod label JO pma16 Rmod label JNO pma16 Rmod label JRC pma16 Rmod label JRNC pma16 Rmod label JRE pma16 Rmod label JRNE pma16 Rmod label JL pma16 Rmod label JNL pma16 Rmod label JTF1 pma16 Rmod label JNTF1 pma16 Rmod label JTF2 pma16 Rmod label JNTF2 pma16 Rmod label JTAG pma16 Rmod label JNTAG pma16 Rmod label JIN1 pma16 Hmod label JNIN1 pma16 Hmod label JIN2 pma16 Rmod label JNIN2 pma16 Rmod label JXZ pma16 Hmod label JXNZ pma16 Rmod label JXS pma16 Rmod label JXNS pma16 Rmod label JXG pma16 Rmod label JXNG pma16 Rmod label JRA pma16 Rmod label JRNA pma16 Rmod label JRZP pma16 Rmod label JRNZP pma16 Hmod label JRLZP pma16 Hmod label JRNLZP pma1
145. KKKKKKK pEE x KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK init614 zac a0 clear a0 mov 0x001 a0 clear second RAM location leave first for C mov STAT 0x001 clear status register mov STR 32 2 set string register to loop 32 times Zacs a0 clear all accumulators out IFR a0 clear pending interrupts out IntGenCtrl a0 clear all interrupt mask bits disable timers mov r0 0x000 point to beginning of RAM mov r4 RAM SIZE 2 do a loop RAM SIZE times BEGLOOP rtag XEO reset tag mov r0 a0 clear the RAM ENDLOOP mov STR 0 clear string register Applications Initializing the MSP50C6xx mov ap0 0 clear accum pointer 0 mov ap1 0 clear accum pointer 1 mov ap2 0 clear accum pointer 2 mov ap3 0 clear accum pointer 3 mov r0 0 clear register 0 mov r1 0 clear register 1 movr2 0 clear register 2 mov r3 0 clear register 3 mov r4 0 clear register 4 movr5 0 clear register 5 movr6 0 clear register 6 movr7 0 clear register 7 mov sv 0 clear shift value register mov TOS 0x000 clear top of stack register mov PH 0x000 clear product high register mov MR 0x000 clear multiplier register PR RRR RRR KKK KEK RRR KKK RK RK KR KK KKK ke kk KR KKK KKK KEK KEK KKK RAR RARA ke ke kk ke ek RK Choose the source for the reference oscillator Set the PLLM vegister accordingly in this case for a CPU clock of 8 MHz and then set TIMER 2 t
146. KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK SECTION 3 AUTHORIZATION TO GENERATE MASKS PROTOTYPES AND RISK UNITS This section is to be completed by the customer and sent to TI after the following criteria have been met 1 The customer has verified that the TI computer generated data matches the original data Customer Information 7 21 New Product Release Forms NPRF 2 The customer approves of the symbolization format in Section 2B Applies to packaged devices only I hereby certify that the TI generated verification data has been checked and found to be correct and I authorize TI to generate masks prototypes and risk units in accordance with purchase order in section 1 above In addition in the instance that this is a packaged device I also authorize TI to use the symbolization format illustrated in section 2B on all devices By Title Date FAX this form to 214 480 7301 Attn Code Release Team kk ck KK KKK KKK ck Ck ck KKK ck Sk ck Ck Sk KKK KKK ck kk ck kk kk ck kk ck kk kk ck ck kk ko kk kk Sk kk ko ko ko Sk Sk ko k ko kc KKK ko SECTION 4 APPROVAL OF PROTOTYPES AND AUTHORIZATION TO START PRODUCTION This section is to be completed by the customer after prototype devices have been received and tested I hereby certify that the prototype devices have been received and tested and found to be acceptable and I authorize TI to start normal production in accordance with purchase o
147. MSP50C604 production board Consult the Important Note regarding Scan Port Bond Out Reference Oscillator Signals OSCOUT Resistor crystal reference out OSCIN Resistor crystal reference in PLL Phase lock loop filter Digital to Analog Sound Outputs 22 O Digital to analog plus output 20 O Digital to analog minus output Initialization 38 40 Initialization Power Signals 17 50 90 1004 32 52 9 19t Ground 61 8 31 32 91 21T 23 33 34 10 Processor power tThe Vss and Vpp connections service the DAC circuitry Their pins tend to sustain a higher current draw A dedicated decoupling capacitor across these pins is therefore required 7 6 Mechanical Information Figure 7 1 100 Pin QFP Mechanical Information 18 85 TYP 20 20 19 80 23 45 22 95 0 16 NOM Y Gage Plane y T 0 25 MIN y Seating Plane 7 0 10 3 40 MAX 4040022 B 03 95 NOTES A Alllinear dimensions are in millimeters B This drawing is subject to change without notice C Falls within JEDEC MS 022 Customer Information 7 7 Mechanical Information Figure 7 2 64 Pin QFP Mechanical Information 0 13 NOM PREIS 7 50 TYP TN 10 20 9 80 sa 12 20 SQ 0 05 MIN 11 80 1 60 MAX N
148. MSP50C6xx Mixed Signal Processor User s Guide Mixed Signal Products SPSU014A X PUTET TEXAS ds 2 SOY INK m INSTRUM ENTS Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments and its subsidiaries Tl reserve the right to make changes to their products orto discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subjectto the terms and conditions of sale supplied atthe time of order acknowledgment including those pertaining to warranty patent infringement and limitation of liability TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements Customers are responsible for their applications using Tl components In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards TI assumes no liability for applications assistance or customer product design TI does not warrant or represent that a
149. N NE GNREENGE O O E 1 A LO eesppp bbb mre cr CTTIENENENENERERERKNKEENRC o ERES 4 34 Instruction Classification Table 4 22 Class 4a Instruction Description CI nei 0 MOV aars Rx Store Rx register to data memory referred by addressing mode adrs Modify transfer status 1 MOV Rx adrs Load Rx with the value in data memory referred by addressing mode adrs Modify transfer status Table 4 23 Class 4b Instruction Description Cen usi esie o v estem or o messer mes AKSa or sumere sensnm corsa Fon mense apis DON 1 1 CMPB Rx imm8 Store the status of the subtraction Rx 8 bit positive constant into RZF and RCF bits of the STAT register Rx remains unchanged Table 4 24 Class 4c Instruction Description EIC o v pe sas 6 pot cone eden es Ras OO DOE 1 1 CMP Rx imm16 Store the status of the subtraction Rx 16 bit positive constant into RZF and RCF bits of the STAT register Rx remains unchanged Table 4 25 Class 4d Instruction Description cw wem mew o o ADD Rx R5 Add R5 to Rx register Modify RX status E SUB Rx R5 Subtract R5 from Rx register Modify RX status EA MOV Rx R5 Load Rx with R5 Modify RX status 1 1 CMP Rx R5 Store the status of the subtraction Rx R5 into RZF and RCF bits of the STAT register Rx and R5 remain unchanged Assembly Language Instructions 4 35 Instruction Classification 4 4 5 Class 5 Instructi
150. OTES A gom Seating Plane 0 08 All linear dimensions are in millimeters This drawing is subject to change without notice Falls within JEDEC MS 026 May also be thermally enhanced plastic with leads connected to the die pads 0 25 d 3 Y m Plane 4040152 C 11 96 Mechanical Information The MSP50C614 is available in a windowed ceramic 120 pin grid array PGA packaged for use in software development and prototyping This PGA package is shown in Figure 7 3 Figure 7 3 120 Pin Grid Array Package for the Development Device MSP50P614 N Nlo oo ooo M Mjo o o ooo L Llooo ooo K Klooo ooo J Jlooo ooo H Hlooo ooo G Glooo ooo F Flo oo extra pin mo E Elooo ooo D Dloooo ooo C Clooooooo ooo 3 B Blooooooo ooo A Alooooooo ooo 131211 10987654321 1234567 8 9101112 13 TOP VIEW BOTTOM VIEW Ss Note The PGA package is only available in limited quantities for development purposes The pin assignments for the 120 pin PGA are outlined in Figure 7 4 Customer Information 7 9 Mechanical Information Figure 7 4 Bottom View of 120 Pin PGA e of the MSP50P614 uoomiuncozrzrc u TrT x Is ane E pgmpuls SYNC bottom view RESET ee Pes vos s gt II peo Fee PAo Pa Ps P osco IMA me Fe ver Von m eso os NN 12 titis important to provide a separat
151. Opcode CEMA EOS 0 CA 0 C C E A IE COCOS fe ee CA E A E e A E Description Subtract value of src1 zero filled in upper 8 bits from src i e src src1 and only modify the status flags Contents of src not changed See Also CMP CMPS Jcc Ccc Example 4 14 11 1 CMPB AO Oxf3 Compare immediate value Oxf3 to accumulator AO Example 4 14 11 2 CMPB R3 0x21 Compare immediate value 0x21 to R3 Assembly Language Instructions 4 93 Individual Instruction Descriptions 4 14 12 CMPS Compare Two Strings Syntax Tabet rame EEE ESE raw E PI a E PE cmPs An pma16 ne EM An An Ng 3 HN CMPS An An Execution status flags set by src src1 string PC PC w Flags Affected srcis An OF SF ZF CF are set accordingly src is aars TAG bit is set accordingly Opcode COM 00000000000 00000101 IS O e dma16 for direct or offset16 long relative see section 4 13 pma16 Ms ao ERE sale wes aman Pf f foto an f fofofofofo fo EN DN AO Description Subtract src string from src string and only modify the status flags Content of accumulators are not changed See Also CMPB CMP Jcc Ccc Example 4 14 12 1 CMPS AO RO Compare string at data memory location pointed by RO to AO and change the STAT flags accordingly Example 4 14 12 2 CMPS Al 0x1400 Compare string at program memory location 0x1400 to A1 and change the STAT flags accordingly Example 4 14 12 3 CMPS A2 A2
152. P package The MSP50P614 is available in a 120 pin PGA windowed ceramic package LLL M 1 NOTE Scan Port Bond Out The scan port interface on the MSP50C6xx devices has five dedicated pins and one shared pin that need to be used by the MSP50Cxx code development tools The SCANIN SCANOUT SCANCLK SYNC and TEST pins are dedicated to the scan port interface The RESET pin is shared with the application These pins may play an important role in debugging any system problems For this reason these pins must be bonded out on any MSP50C614 production board Furthermore it is recommended that these pins be connected to test points so the development tool can be connected Since the development tool requires Vpp and Vss test points connected to these signals are also needed LLLLLL The application circuits appearing in section 6 1 show the minimum recommended configuration for any MSP50C614 application board For production purposes the 1 kQ resistor which appears at the RESET pin is optional It is required for use with the scan port interface but they may be shorted otherwise The footprints for this resistor are strongly recommended 7T 1 1 Die Bond Out Coordinates Die bond out coordinates are available upon request from Texas Instruments email speak2me list
153. Port Bond Out OSCOUT Resistor crystal reference out OSCIN Resistor crystal reference in Phase lock loop filter arenal ou opus Digital to analog plus output Digital to analog minus output Initialization l Initialization Power Signals 11 26 52 67 91 9 19t 40 64 76 Ground 6t 8 27 68 92 10 211 23 41 77 Processor power 4 t The Vss and Vpp connections service the DAC circuitry Their pins tend to sustain a higher current draw A dedicated decoupling capacitor across these pins is therefore required Customer Information 7 3 Mechanical Information Table 7 2 Signal and Pad Descriptions for the MSP50C605 SIGNAL PIN NUMBER PAD NUMBER 1 0 DESCRIPTION Input Output Ports PCO PC7 89 82 8 1 1 0 Port C general purpose l O PDO PD7 99 92 18 11 1 0 Port D general purpose l O PEO PE7 46 39 48 41 1 0 Port E general purpose I O PFO PF7 16 9 31 24 l Port F dedicated input Pins PD4 and PD5 may be dedicated to the comparator function if the comparator enable bit is set Refer to Section 3 3 Comparator for details 1 Byte 1 Byte 1 Byte 1 Byte Scan Port Control Signals SCANIN 37 39 Scan port data input SCANOUT 33 35 Scan port data output SCANCLK 36 38 Scan port clock SYNC 35 37 Scan port synchronization TEST 34 36 l C605 test modes The scan port pins must be bonded out on any MSP50C605 production board Consult the Important Note regardi
154. Pre decrement pointer AP2 XOR word at effective address R2 R5 to new accumulator A2 put result in accumulator A2 Value of R2 is not modified Example 4 14 85 6 XOR TF1 0x21 XOR TF1 with the flag at global address 0x21 and store result in TF1 in STAT Example 4 14 85 7 XOR TF2 R6 0x21 XOR TF2 with the flag at effective address R6 0x21 and store result in TF2 Example 4 14 85 8 XOR TF1 CF XOR TF1 with the condition code CF Carry Flag and store result in TF1 Example 4 14 85 9 XOR TF1 RZP R3 XOR TF1 with the condition code RZP Rx 0 flag for R3 and store result in TF1 If the content of R3 is zero then RZP condition becomes true otherwise false 4 184 Individual Instruction Descriptions 4 14 86 XORB Logical XOR Byte Syntax labe name sess crock ok wora w With RPT ck crass xor Anime 1 NR Execution An An XOR imma for two operands PC PC 1 Flags Affected dest is An OF SF ZF CF are set accordingly Opcode Instructions re rs 14 J 13 12 11 o o jo v e s aoa Jo Ll mms xorB An imme to ols jo tito an imm8 Description Bitwise logical XOR lower 8 bits of An and dest byte Result is stored in accumulator An Upper 8 bits of accumulator An is not affected See Also XOR XORS AND ANDS OR ORS ORB NOTAC NOTACS Example 4 14 86 1 XORB A2 0x45 XOR 0x45 to accumulator A2 byte mode Upper 8 bits of A2 is unchanged Assembly Language Instruc
155. RNC pma16 Conditional call on RCF 0 CRE pma16 CRZ pma16 Conditional call on RZF 1 equal t CRNE pma16 CRNZ pmal6 Conditional call on RZF 0 not equal CXG pma16 CXNLE pma16 Conditional call on transfer greater signed t CXNG pma16 CXLE pma16 Conditional call on transfer not greater signed t CXS pma16 Conditional call on XSF 1 CXNS pma16 Conditional call on XSF 0 t Alternate mnemonics are provided as a way of improving source code readability They generate the same opcode as the original mnemonic For example CA call above tests the same conditions as CNBE call not below or equal but may have more meaning in a specific section of code See Also CALL VCALL RET IRET Example 4 14 9 1 CZ 0x2010 Call routine at program memory address 0x2010 if a previous operation has set the ZF 1 flag in STAT Example 4 14 9 2 CTF1 0x2010 Call routine at program memory address 0x2010 if a previous operation has setthe TF1 1 flag in STAT Example 4 14 9 3 CRNBE 0x2010 Call routine at program memory address 0x2010 if a previous operation has set the flags RCF 1 RZF 0 in STAT 4 90 Individual Instruction Descriptions 4 14 10 CMP Compare Two Words Taba vame EI EI Word w Wino ss few anions tates rasos E O mS t CMP An An next A jewt mens gt mes 4 T Does not modify An status Execution premodify AP if mod specified STAT flags set by src src operation PC PC w Fl
156. RO now points to the last sample movs ySampleOut A0 FIR outputs bits 0 15 in ACO 16 32 in AC1 mov A0 nextSample Replace last sample with newest sample and update mov RO AO the start of the mov startOfBuff RO circular buffer to here RO The setup for the FIRK CORK instruction is the same as the set up for the FIR COR instruction with the exception that the filter coefficients do not need to be loaded into RAM locations Rather they can be included just before speech data or elsewhere in the program code as follows FIRK COEFFS include NV NtablesNcoeffs dat Special Filter Instructions Figure 4 6 Setup and Execution of MSP50P614 MSP50C614 Filter Instructions N 1 Taps coeff_array address Rx 1 RIAS BRA coeff array address sample buf address DP FIRK CORK only Program memory FIRK CORK BXeven coeff array RO R2 R4 R6 Coefficients h k FIR COR only k 0 N Circular buffer operation only R5 Circular buffer length 2N Data memory FIR COR Accumulators Pointer Point to accumulator ACr An ACn sample_buf Past N samples X K TAG 1 for 2N0 to last sample for Circular buffer operation Multiplier Accumulators ee I 15th bits of yt fe BOG Ooi SOR Y a For COR CORK ACr 1 16 315t bits of yt G re ACr2 32 471 bits of yt For FIR FIRK YI Zm o n Mimi y t The value of y is stored in ACrand ACr 1 for
157. T EXTENDED SIGN WORD FOR NEG CASE POSITIV E Sign extend accumulator string A0 See the previous italic text on the bug in this instruction at the present time 4 100 Individual Instruction Descriptions 4 14 18 FIR FIR Filter Function Coefficients in RAM Syntax Tabet rame uses EE was Win RPT cx onse EN SA AA Execution With RPT N 2 mask interrupts RPT counter N 2 MR h 0 first filter coefficient x sample data pointed at by RXeyen h 1 second filter coefficient pointed at RXeyen 1 y result stored in three consecutive accumulators 32 bit pointed by An between every accumulation IF TAG 1 RXeven RXeven R5 for circular buffering ELSE RXeventt if Rx is specified in the instruction ENDIF PC PC 1 final result y ERANS AO Execution is detailed in section 4 11 Flags Affected None Opcode Pp aaa Brotes EVA KE ERES ARO A EEN Description Finite impulse response FIR filter Execute finite impulse response filter taps using coefficients from data memory and samples from data memory The instruction specifies two registers Rx and R x 1 which sequentially address coefficients and the sample buffer in the two instruction FIR tap sequence This instruction must be used with RPT instruction When used with the repeat counter it will execute a 16 x 16 multiplication between two indirect addressed data memory buffers 32 bit accumulat
158. T none RESET LOW to HIGH always wakes device DAC Timer D e Assuming PDM bit is clear as in D No wake up from DAC Timer The external interrupt is the other programmable option for waking the C6xx from sleep The associated interrupt trigger event is in some cases a rising edge at the input port in some cases itis a falling edge Refer to Section 3 1 5 Internal and External Interrupts for a full description of these events Consider also the comparator driven interrupts described in Section 3 3 Comparator The input ports which are supported by external interrupt include the entire F Port and when programmed as inputs Ports Do Dz D4 and Ds Refer to Sec tion 3 1 O for a description of the various I O configurations External interrupts 2 38 Reduced Power Modes Under normal operation the DAC timer when IMR enabled triggers an interrupt on underflow Before any IDLE instruction however the entire DAC circuitry should be disabled This ensures the effectiveness of the reduced power mode and prevents any wake up from the DAC timer In order to wake the device using a programmable interrupt the interrupt mask register must have the respective bit set to enable interrupt service see Sec tion 2 7 Interrupt Logic In some cases the ARM bit must also be set in order for the interrupts to be visible during sleep After the C6xx wakes from sleep the program counter assumes a specific location resuming normal operat
159. T8 E Description Subtract the value of the src string from value of the dest string and store the result in the dest string If three operands are specified then subtract value of src string from value of srcstring i e src src1 and store result in deststring Note that substraction is performed in 2 s complement and therefore the CF carry flag may get set even when subtracting a smaller value from a large value Assembly Language Instructions 4 179 Individual Instruction Descriptions SUBS ANI An adis SUBS Ariz An An SUBS Ar An An Subtract An string from An string store result in An string SUBS An An PH Subtract product high PH register from An string mode This instruction ig nores the string count executing only once but maintains the CF and ZF status of the previous multiply or shift operation as if the sequence was a single string Word alignment with PH is maintained i e PH is subtracted from the second word of the string Also only the second word is copied to the destination string Example 4 14 82 1 SUBS AO AO R2 Subtract data memory string beginning at address in R2 from accumulator string AO put result in accumulator string AO then increment R2 by 2 Example 4 14 82 2 SUBS Al Al 0x1220 Subtract program memory string at address 0x1220 from accumulator string A1 put result in accumulator string A1 Example 4 14 82 3 SUBS A2 A2 A2 Subtract accumulator string A2
160. TAG bit is set accordingly Opcode CA 0110 1010105000002 01010251015 19 OR An adii Lo Pa folofofofo wm am X dma16 for direct or offset16 long relative see section 4 13 on Ari Ari imme nea 3 3 3 o 9 v5 an i e o 9 9 D D E on ana Ans tren 1 1 1 o o vec o To To D To D for ten crasas ilolo O lepel Ti lo e on Tented Rd tr j ojojrj ojfg Nt ce rx 0 1 Description Bitwise OR of src and dest Result is stored in dest If three operands are specified then logical OR src and src store result in dest Premodification of accumulator pointers are allowed with some operand types OR TFn flagadrs OR TFn with memory tag store result in TFn bit in STAT OR TF cc Rx OR test condition with TFn bit in STAT register Rx must be provided if cc is one of RZP RNZP RLZP RNLZP to check if the selected Rx is zero or negative Rx should not be provided for other conditionals Assembly Language Instructions 4 147 Individual Instruction Descriptions See Also ORB ORS AND ANDS XOR XORS NOTAC NOTACS Example 4 14 52 1 OR A0 RO R5 OR accumulator AO with the value in data memory address stored in RO and store result in accumulator AO Add R5 to RO after execution Example 4 14 52 2 OR Al Al OxFOFF A Preincrement pointer AP1 OR immediate OxFOFF to accumulator A1 Store result in accumulator A1 Example 4 14 52 3 OR Al Al Al A Pre decrement accumu
161. The sign bit for either operand multiplier or multiplicand can assume a positive value zero or a value equal to the MSB bit 15 In assuming zero the extra bit supports unsigned multiplication In assuming the value of bit 15 the extra bit supports signed multiplication Table 2 1 shows the greater magnitude achievable when using unsigned multiplication 65535 as opposed to 32767 Table 2 1 Signed and Unsigned Integer Representation Unsigned Signed Decimal Hex Hex 65535 OxFFFF OxFFFF 32768 0x8000 0x8000 32767 Ox7FFF Ox7FFF 0 0x0000 0x0000 During multiplication the lower word LSB of the resulting product product low is multiplexed to the ALU Product low is either loaded to or arithmetically combined with an accumulator register These steps are performed within the same instruction cycle Refer to Figure 2 3 for an overview of this operation Atthe end of the current execution cycle the upper word MSB of the product is latched into the product high register PH MSP50C6xx Architecture 2 5 Computation Unit 2 6 The multiplicand source can be either data memory an accumulator or an accumulator offset The multiplier source can be either the 16 bit multiplier register MR or the 4 bit shift value SV register For all multiply operations the MR register stores the multiplier operand For barrel shift instructions the multiplier operand is a 4 to 16 bit value that is decoded from the 4 bit shift value register SV
162. The include statement at the top of the program is for memory allocation purposes The C compiler is not aware that RAM has been allocated for assembly and must be kept from overwriting it This is done with an integer array called bogus The array is set to the size of the RAM allocated for Code Development Tools 5 45 C Efficiency assembly divided by two because C integers are 16 bit The perl script in the main project directory can be used to resize bogus automatically or it can be done manually To use the perl script build the project after making any changes to assembly ram allocation Run the perl script and then rebuild the project To manually adjust bogus build the project and then examine the list file mainasm Ist Find RAMEND_ASM in the cross reference table and use it to replace the value in the define statement in ram h Rebuild the project to put the changes into effect This only needs to be done when changes are made to assembly RAM allocation Changes to C or assembly code other than RAM allocation do not require adjustments to bogus The next items in the program are function prototypes All C functions have areturn type of int 16 bit and are declared with the mnemonic cmm func The first one is goasm Notice that there is no leading underscore because it is being called from C instead of assembly The second one is the function in cmm1 asm for reading the value of seconds passed Global variab
163. The program counter PC holds the program memory location to be used for the next instruction s execution It increments by 1 for single word instructions 4 2 4 2 5 Top of Stack System Registers or by 2 for double word instructions each execution cycle and points to the next program memory location to fetch During a maskable interrupt the next PC address is stored in the TOS register and is reloaded from TOS after the interrupt encounters an IRET instruction Call and jump instructions also store the next instruction address by adding PC 2 and then storing the result in the TOS register Upon encountering a RET instruction the TOS value is reloaded to the PC Call instructions may not precede RET instructions Similarly a RET instruction may not immediately follow another RET instruction In these conditions pipeline operations breaks down and the PC never recovers its re turn address from the TOS register The processor stalls and the only solution is to reset the device On the other hand RET can be safely replaced by IRET eliminating processor stalls in all conditions However IRET takes one more cycle than RET TOS Thetop of stack TOS register holds the value of the stack pointed by the stack register R7 The MSP50P614 MSP50C61 4 hardware uses TOS register for very efficient returns from CALL instructions Figure 4 1 shows the operation of the TOS register When call instructions are executed the old TOS register valu
164. Using a Crystal Heferenced Oscillator To pin 1 of Scan Port Connectort optional To pin 2 of Scan Port Connectort optional 1N914 MSP50P614 only 22 pF L 100 kQ RESET 1 kat 32kHq 1 1 uF E Reset gt Switch OSCouT 20 22 pF MSP50C614 MSP50P614 3300 pF 5 T The diode across Vpp and Vpp may be omitted shorted if the application does not require use of the scan port interface The same applies for the 1 kQ resistor which appears at the RESET pin the resistor may be shorted if not using the scan port However the footprint for the resistor is strongly recommended for any MSP50C614 production board Refer to the mportant Note regarding Scan Port Bond Out appearing in Chapter 7 Applications 6 3 Initializing the MSP50C6xx In any MSP50C614 application it is important for certain components to be located as close as possible to the MSP50C614 die or package These include any of the decoupling capacitors at Vpp 0 1 uF It also includes all of the components in the crystal reference network between OSC n and OSCouT 22 pF 10 MO 32 kHz 6 2 Initializing the MSP50C6xx 6 4 The initialization code for the MSP50C6xx is in the file INIT ASM in the MODULES GENERAL directory of the TI TALKS code see the following information The initialization routine does the following Clears the status registers Clears all 32 accumulators Clears all 640 words of RAM Clears all syst
165. VB An ads lo 1 ojo 1 1 0 an cc t Flagadrs is 64 locations global or relative to R6 4 192 adrs Ee fis 1 fis 12 11 0 e fs 7 e fs fa a 2 t 0 AAA see section 4 13 Eqr ojysis ore aem ads see section 4 13 x Aa as see section 4 13 x AR see section 4 13 x ttafofafofofofofs as see section 4 13 ttafoftafofifofofof as see section 4 13 x AA see section 4 13 x a filojijolojojili as see section 4 13 Eqrlojsjojepo ejo ads see section 4 13 x Eqrlojsjojoro o o ces see section 4 13 x 1pifof fofofrf an fo ads see section 4 13 x ee ee a ae ee 1 see section 4 13 x jrjo e efojo e e as see section 4 13 imma o imme rgo fr Ae fofofo imm o ads aars move agar Potato Tilo Toto Tan as Instruction Set Encoding COI 0000000 0000000000 MOVB adrs An dma16 for direct or offset16 long relative see section 4 13 wove anna Pppp m mowwhms prr a om perom 000000000000 Tere Ads MOVBS An aarsj adrs ERERES REN a or offset16 long relative see section 4 13 mus OO CA o dma16 for direct or offset16 long relative see section 4 13 MOVE Art adi peehea wm dma16 for direct or offset16 long relative see section 4 13 WOVE adh AT ete De Tan aie dma16 for direct or offset16 long relative see section 4 13 mee ete
166. XORB An imm8 XORS An aars XORS An Ar pma16 XORS An An An 4 196 pt fa a jojo fa 4 Jo o fa A A next an o fo a 3 pt fa a fos tots ts fo fa a A ro An pt a fo lr pee Lre re us EM An imma Low epe aars ENEREBERERERERERERERERES fel Fac An aars Instruction Set Encoding Instructions rs fis fra fra i2 n 00 9 8 7 e 5 4 a 2 1 o zac An L next Ap tt ht t fo fo netA an o o o 1 t o o A ZACS Arf Es tats fofofts s an Jo ojo t s opo A cc names Description True condition Not true condition Conditional on ZF 1 Not condition ZF 0 Conditional on SF 1 Not condition SF 0 Conditional on CF 1 Not condition CF 0 Conditional on ZF 0 and CF 0 Not condition ZF 0 or CFzO Conditional on ZF 0 and CF 1 Not condition ZF 0 or CFz1 Conditional on SF 0 and ZF 0 Not condition SF 0 or ZF 0 Conditional if ZF 1 and OF 0 Not condition ZFz1 or OF 0 Conditional if OF 1 Not condition OF 0 Conditional on RCF 1 Not condition RCF 0 Conditional on RZF 0 and RCF 1 Not condition RZF 0 or RCFz1 Conditional on RZF 1 Not condition RZF 0 Conditional on value of Rx 0 Not available on Calls Not condition RxzO Conditional on MSB of Rx 1 Not available on Calls Not condition MSB of Rx 0 Conditional on ZF 0 and SF 1 Not condition ZFz0 or SFz1 reserved reserved Conditional on TF1 1 Not condition TF1 0 Con
167. Z MHz kHz Interrupts Interrupts 8 bits 1 1x 0x 13 2 62 2 62 1 31 10 24 128 128 2x Ox 26 5 11 5 11 2 56 19 97 128 256 4x 0x 4D 10 22 10 22 5 11 39 94 128 512 8x 0x 9B 20 45 20 45 10 22 79 87 128 1024 0 1x Ox 26 5 11 2 56 2 56 9 98 256 256 2x Ox 4D 10 22 5 11 5 11 19 97 256 512 4x 0x 9B 20 45 10 22 10 22 39 94 256 1024 9 bits 1 1x Ox 26 5 11 5 11 2 56 9 98 256 256 2x Ox 4D 10 22 10 22 5 11 19 97 256 512 4x 0x 9B 20 45 20 45 10 22 39 94 256 1024 0 1x Ox 4D 10 22 5 11 5 11 9 98 512 512 2x 0x 9B 20 45 10 22 10 22 19 97 512 1024 10 bits pus 1x Ox 4D 10 22 10 22 5 11 9 98 512 512 2x 0x 9B 20 45 20 45 10 22 19 97 512 1024 0 1x 0x 9B 20 45 10 22 10 22 9 98 1024 1024 3 14 3 3 Comparator Comparator The MSP50C6xx provides a simple comparator that is enabled by a control register option The inputs of the comparator are shared with pins PD4 and PDs PDs is the noninverting input to the comparator and PD is the inverting input When the comparator is enabled the conditional operation COND2 normally associated with PD4 becomes associated with the comparator result In addi tion the interrupts associated with PD4 and PDs namely INT6 and INT7 be come interrupts based on a transition in the comparator result Finally the start stop function of TIMER1 may be controlled indirectly by a comparator transition When enabled the comparator controls the following four events 1 Steady State Comparator TRUE Vpp5 gt Vpp4
168. a circular buffer operation Each tap takes 3 instruction cycles Rx automatically increments by 2 per tap 1 1 COR An Rx Correlation function When used with repeat will execute 16x16 multiplication between two indirectly addressed data memory buffers 48 bit accumulation anda circular buffer operation Each tap takes 3 instruction cycles Rx and R x 1 automatically increments by 2 per tap cs 4 37 Class 9b Instruction Description Mnemonic Description A o imm8 NNNM the repeat counter with an 8 bit constant and execute the instruction that follows imm8 2 times Interrupts are queued during execution EXER MOV STR imm8 Load the STR register with an 8 bit constant EJ MOV SV imm4 Load the SV shift value register with a 4 bit constant Assembly Language Instructions 4 43 Bit Byte Word and String Addressing Table 4 38 Class 9c Instruction Description XT PEA A O MOV APn imm6 Load the accumulator pointer AP with a 5 bit constant ADD APn imm5 Add a 5 bit constant imm5 to the referenced accumulator pointer AP Table 4 39 Class 9d Instruction Description B l l C9d 1 ENDLOOP n If R4 is not negative pops the temporary stack value back on the PC and decrements R4 by n If R4 is negative the instruction is a NOP and execution will exit the loop nis either 1 or 2 DLE Stops processor clocks Device enters low power mode waiting on an interrupt to restart the clocks and exe
169. accordingly Opcode nswoins 0000000000050 0 a nac eoceoe es dma16 for direct or offset16 long relative see section 4 13 ES shares Ad An tjs tjo ojs t an i s i Jott Jo A A Description Shift accumulator string or data memory string pointed by adrs to left nsy bits as specified by the SV register The resultis zero filled on the right and either zero filled or sign extended on the left based on the setting of the extended sign mode XM bit in the status register The upper 16 bits are latched into the product high PH register The lower 16 bits ofthe result product low PL register are added to the destination accumulator or its offset This instruction propagates the shifted bits to the next accumulators in the string SHLAPLS An adrs Shift data memory string left add PL to An SHLAPLS Ar An Shift An string left addb PL to An See Also SHLAPL SHLTPL SHLTPLS SHLSPL SHLSPLS Example 4 14 70 1 SHLAPLS A0 R4 R5 Shift the string pointed by the byte address stored in R4 by ney bits to the left add the shifted value PL with accumulator string and store the result in accumulator string AO Add R5 to R4 and store result in R4 PH holds the upper 16 bits of the shift Example 4 14 70 2 SHLAPLS A2 R1 Shiftthe string pointed by the byte address stored in R1 by nsy bits to the left add the shifted value PL with accumulator string the accumulator and store the result in accumula
170. accumulator s overflow mode may be enabled disabled by setting resetting the OM bit of STAT When the computation is in the overflow mode and an overflow occurs the overflow flag is set and the accumulator is loaded with either the most positive or the most negative value representable in the accumulator depending upon the direction of the overflow In string mode instead of representing the most positive or most negative value only the 16 bit MSB is set to Ox7FFF or 0x8000 depending on direction of overflow The remaining words of the accumulator string are unchanged If the OM status register bit is reset and an overflow occurs the overflowed results are placed in the accumulator without modification Note that logical operations cannot result in overflow Assembly Language Instructions 4 51 MSP50P614 MSP50C614 Computational Modes 4 52 Example 4 6 1 SOVM MOV AO Ox7FFE ADD AO 5 In this example we set the overflow mode OM 1 of STAT Adding 0x7FFE with 5 causes an overflow OF 1 of STAT Since the expected result is a positive value the accumulator saturates to the largest representable value Ox7FFF If overflow mode was not set before the ADD instruction then the accumulator would overflow Therefore the result 0x8003 would be a negative value Example 4 6 2 SOVM MOV STR 2 2 string length 2 MOV APO 0 MOV A0 0x1234 OV A0 0x1000 OV AO Ox7F00 A OV A0 0x1000 MOV APO 0 point to beginning of string
171. accumulators starting from AC2 The result is AC2 0x0078 AC3 0x009A AC4 0x00BC AC5 0x00DE Example 4 5 5 Refer to Figure 4 4 for th 4 2 2 0x0003 The byte string length is 4 APO is loaded MOV STR MOV APO MOVS AO is example with 2 and points to AC2 The third instruction loads the value of the string at address 0x0002 LSB bit is assumed 0 and stored into four consecutive accumulators starting from AC2 The result is AC2 0x5678 AC3 Ox9ABC ACA OxDEFO AC5 0x1122 Same result can be obtained by replacing the third instruction by which uses the absolute Example 4 5 6 OVS AO 0x0001 2 word memory address OV STR 4 2 OV APO 2 OV RO 0x0005 OVBS A0 RO Refer to Figure 4 4 for this example The byte string length is 4 APO points to AC2 RO is loaded with 0x0005 The fourth instruction loads the value of the byte string at the address in RO i e 0x0005 in byte mode RO auto incre ments by 1 after every fetch and stores the RAM contents into four consecutive accumulators starting from AC2 The result is AC2 0x00BC AC3 OxOODE ACA 0x00F0 AC5 0x0011 There were four byte fetches and the new value of RO 0x0009 Assembly Language Instructions 4 47 Bit Byte Word and String Addressing 4 48 Example 4 5 7 MOV STR 4 2 MOV APO 2 MOV RO 0x0001 2 MOVBS A0 RO Refer to Figure 4 4 for this example The word string length is 4 APO points to AC2 acc
172. ags Affected srcis An OF SF ZF CF are set accordingly srcis Rx RCF RZF are set accordingly srcis adrs TAG bit is set accordingly Opcode CO 000000000000 00 0010 er rape tar e 3 dma16 for direct or offset16 long relative see section 4 13 ig aene O AO OO E imm16 A O e ee 0 00 O A 0000623000000 00 OW Fon OOOO O ES imm16 eme RRS fai sgope ogoojo s ejtr e ojo Description Subtract value of src1 from src i e src src and only modify the status flag Premodification of accumulator pointer is allowed with some operand types See Also CMPB CMPS Jcc Ccc Example 4 14 10 1 CMP AO RO Compare value at accumulator AO and the content of data memory location pointed by RO and change the STAT flags accordingly Example 4 14 10 2 CMP A0 0x1400 A Predecrement accumulator pointer APO Compare value at accumulator AO to immediate value at 0x1400 and change the STAT flags accordingly Assembly Language Instructions 4 91 Individual Instruction Descriptions Example 4 14 10 3 CMP R2 Oxfe20 Compare value at R2 to immediate value Oxfe20 and change the STAT flags accordingly Example 4 14 10 4 CMP RO R5 Compare value at RO to R5 and change the STAT flags accordingly 4 92 Individual Instruction Descriptions 4 14 11 CMPB Compare Two Bytes Syntax Execution status flags set by src src byte PC PC 1 Flags Affected srcis An OF SF ZF CF are set accordingly srcis Rx RCF RZF are set accordingly
173. al Example 4 14 29 5 MOVB R2 255 Load R2 with immidiate value of 255 decimal 4 124 Individual Instruction Descriptions 4 14 32 MOVBS Move Byte String from Source to Destination Syntax iae rame dest se eee ok Word w With RPT ok crass Moves An aars g Table 4 46 Table 4 46 moves aars An Table 4 46 Table 4 46 Execution dest src PC PC w Flags Affected destis An OF SF ZF CF are set accordingly dest is adrs XSF XZF are set accordingly src is adrs TAG bit is set to bit 17th value Opcode Instructions Pie fis 14 r2 2 11 10 o jo v e S a s pa 1 fo MOVES Ar adis Fopfeletrb lil ms SS x dma16 for direct or offset16 long relative see section 4 13 MOVES adi An OCA l e ac dma16 for direct or offset16 long relative see section 4 13 Description Copy value of src byte to dest MOVBS An adrs Move data memory byte string to An word string MOVB aars An Move An byte string to data memory See Also MOVU MOV MOVT MOVB MOVS Example 4 14 30 1 MOVBS A2 0x0200 Transfer the byte string at data memory location 0x0200 to accumulator string A2 Example 4 14 30 2 MOVBS 0x0200 A2 Transfer accumulator string A2 to data memory byte string location 0x0200 Assembly Language Instructions 4 125 Individual Instruction Descriptions 4 14 33 MOVS Move String from Source to Destination Syntax Cip name dest sc Gl
174. amp An PH MR lt contents of adrs PC PC w Flags Affected TAG OF SF ZF CF are set accordingly Opcode Instructions Pis 5 14 13 12 11 10 o jo v Je s a aja Jo a con rasar ESDNE dma16 for direct or offset16 long relative see section 4 13 Description Move data memory to MR subtract PH from An store result in An See Also MOVSPHS MOVAPH MOVAPHS MOVTPH MOVTPHS Example 4 14 36 1 MOVSPH AO MR R3 R5 Loadthe content of byte address created by adding R3 and R5 to MR register At the same time subtract PH register from accumulator AQ store result in AO 4 128 Individual Instruction Descriptions 4 14 35 MOVSPHS Move String With Subtract From PH Syntax mMOvSPHS An MR aars Table 4 46 Table 4 46 Execution An An second word PH MR lt contents of adrs PC PC w Flags Affected TAG OF SF ZF CF are set accordingly Opcode Instructions re rs ires 12 11 o Jo Je v Jef stats fey Jo a a 2 dma16 for direct or offset16 long relative see section 4 13 Description Move data memory word string to MR subtract PH from second word An string Store result in An Certain restrictions apply to the use of this instruction when interrupts are occuring on the background See Section 4 8 for more details See Also MOVSPH MOVAPH MOVAPHS MOVTPH MOVTPHS Example 4 14 37 1 MOVSPHS AO MR R3 R5 Load the content of byte address created by adding R3 and
175. amples and interactive displays are shown ina special typeface similar to a typewriter s Examples use a bold version of the special typeface for emphasis interactive displays use a bold version ofthe special typeface to distinguish commands that you enter from items that the system displays such as prompts command output error messages etc Notational Conventions Here is a sample program listing 0011 0005 0001 field iy e2 0012 0005 0003 field 3 4 0013 0005 0006 field 65 43 0014 0006 even Here is an example of a system prompt and a command that you might enter C csr a user ti simuboard utilities In syntax descriptions the instruction command or directive is in a bold typeface font and parameters are in an italic typeface Portions of a syntax that are in bold should be entered as shown portions of a syntax that are in italics describe the type of information that should be entered Here is an example of a directive syntax asect section name address asectis the directive This directive has two parameters indicated by sec tion name and address When you use asect the first parameter must be an actual section name enclosed in double quotes the second parameter must be an address Square brackets and identify an optional parameter If you use an optional parameter you specify the information within the brackets you don t enter the brackets themselves Here s an example of an instruct
176. and accumulator In addition IN and OUT instructions in class 6b can communicate with an extra 48 ports a total of 64 including the shared ports Class 6b instructions also have reference to the string bit for checking the arithmetic status of a string transfer Table 4 28 Class 6a Instruction Encoding BE ER CO ERI E E E ES E i Table 4 29 Class 6a Instruction Description C6a Mnemonic Description 0 IN adrs port4 Transfer a 16 bit value of addressed port to data memory location referred by addressing mode adrs Refer to port address map Transfer status is modified 1 OUT port4 adrs Transfer a 16 bit value in the data memory location referred by addressing mode aars to addressed port Refer to Port address map Transfer is sta tus modified 4 38 Instruction Classification Table 4 30 Class 6b Instruction Description C6b Mnemonic Description 0 IN An port6 Transfer the port s 16 bit value to an accumulator Port addresses 0 63 INS An port6 are valid ALU status is modified 1 OUT port6 An Transfer a 16 bit accumulator value to the addressed port Port address OUTS port6 An es 0 63 are valid Transfer status is modified 4 4 7 Class 7 Instructions Program Control This class of instructions provides the logical program control of conditional branches jumps and calls subroutines Both branch and call instructions require a 32 bit instruction word The first word contains the opcode and c
177. any one time so 15 20 devices may be required to operate efficient ly The windowed PGA version of the MSP50P614 is required for this debug ging mode y Note The MSP50P614 operates with a voltage range of 4 V to 6 V However the MSP50C6xx devices operate at a different voltage range 3 V to 5 2 V Please refer to the data sheet for specific device information Functional Description for the MSP50C614 1 4 Functional Description for the MSP50C614 The MSP50C614 device consists of a micro DSP core embedded program and data memory and a self contained clock generation system General pur pose periphery is comprised of 64 bits of flexible I O The block diagram ap pearing in Figure 1 1 gives an overview of the MSP50C614 MSP50P614 functionality Figure 1 1 Functional Block Diagram for the MSP50C614 MSP50P614 SCANIN SCANOUT SCANCLK SYNC TEST PGMPULSE DACP DACM Vss Vpp VpP Scan Interface Power P614 only A port I O EP ROM 32k x 16 1 bit mata 9x00 EP X 16 TD Control 0x04 Test Area 0x0000 to reserved 0x07FF B port O User ROM 0x0800 to Data 0x08 QABER Control 0x0C INT vectors Ox7FFO to Ox7FFF Break Point Emulation OTP Program Serial Comm C6xx only P614 only C port VO ERES LT E Data 0x10 DAC 0x30 Control 0x14 Instr Decoder PESRE 32 Ohm PDM PCU Prog Counter Unit Comparator 1 bit
178. apacity A 2 times over sampling means that every 2nd INTO requires a computed update from the synthesis algorithm The other INTO may be satisfied with an interpolating filter computation then a return to the main program As stated previously the maximum ensured CPU clock frequency for the MSP50C6xx operates over the entire Vpp range This rate applies to the speed of the core processor Operating the processor higher than the listed specification is not recommended by Texas Instruments The following tables illustrate a number of possible combinations with respect to sampling rate PDM rate DAC resolution master clock rate and CPU clock rate The first table applies to the 8 kHz sampling rate and N times 8 kHz over sampling The second applies to the 10 kHz sampling rate and N times 10 kHz over sampling p 7H Note The value programmed to the PLLM register is not exactly the multiplicative factor between the 32 kHz reference and the master clock Refer to Section 2 9 3 Clock Speed Control Register for more information on the relationship between the PLLM and the resulting MC rate a e The column in these tables output sampling rate reports the true audio sampling rate achievable by the MSP50C6xx usingthe 32 768 kHz CRO The values reported are not always exact multiples of the 8 kHz and 10 kHz options however they are the closest obtainable using the PLLM multipl
179. argument is read as 1 2 1 but writing the argument as 1 2 may or may not give the correct result Outside parenthesis are not allowed in instruction arguments For example ADD A0 A0 1 2 300 256 causes a compile time syntax error But removing the outside parenthesis i e ADD A0 A0 1 2 300 256 causes no error ELSE see IF and IFDEF END FT This directive is created by the C compiler when it outputs assembly code to afile It marks the end of the function table used to track function calls and C variables in the emulator Users should NEVER use this directive in an assembly language program ENDIF marks the end of a conditional assembly structure started by IF or IFDEF 5 12 Assembler HIF expression The start of a conditional assembly structure expression is an arithmetic expression that can contain symbols Caution since conditional assembly is resolved during the first pass of the assembler no forward referenced symbols should be used in a conditional assembly expression lf an expression is TRUE non zero then the lines following this directive are assembled until a ZELSE or a ENDIF directive is encountered If an expression is FALSE equal to zero then all input lines are skipped until a ELSE or a ENDIF directive is encountered If a ELSE directive is encountered first all lines following it are assembled until a HENDIF directive is found Example HIF expressi
180. at could potentially cause harm to you The information in a caution or a warning is provided for your protection Please read each caution and warning carefully Trademarks Intel i486 and Pentium are trademarks of Intel Corporation Microsoft Windows Windows 95 and Windows 98 are registered trademarks of Microsoft Corporation Read This First V vi Contents 1 Introduction to the MSP50C6XX sess n nnn 1 1 dat Features of the MSPBO0COXX isslubieserikietkk pata desde pened riw nensis 1 2 1 2 Application id Ro eel a e Renal 1 3 1 3 Development Device MSP50P614 0c cee eee 1 4 1 4 Functional Description for the MSP50C614 0 cece eee 1 5 1 5 MSP50C601 MSP50C604 and MSP50C605 occcccccccccccccc eee 1 9 2 MSP50C6xx Architecture 0c cece eee eee 2 1 2 1 Architecture Overview 002 cece nent need eee 2 2 2 2 Gomputation Wit coc ita 2 5 22 1 Multtiplier skeet gases Gt cine ai a E 2 5 2 2 2 Arithmetic Logic Unit oeseri parera Eaa AEA Ie 2 7 2 3 Data Memory Address Unit 0 enient DEES EEEE SEREA R EEA I ERES EY 2 11 2 3 1 RAM Configuration ssssssssssssse RI nn 2 12 2 3 2 Data Memory Addressing Modes ssseselsseeeseeeeseeeeh 2 13 2 4 Program Counter Unit 0 0 cee sn 2 14 2 5 Bit Logics Unicorn AAA 2 14 2 6 Memory Organization RAM and ROM 00 cece ee eect eee 2 15 2 6 1 Memory Map irrati e RI mme 2 15
181. ata Directory holding MELP speech data Speech file of AM and PM Speech file of Sun Sat Speech file of 0 9 Speech file of 10 19 Speech file of 20 30 40 50 Five of the important files from the first project have been modified and there are many new files C Efficiency In main ram irx two variables were added to save and restore r3 and r5 when speaking These registers are used by C so it is a good idea to save and restore them in case they are modified by the speech routines This is a good example of adding RAM for use by cmm1 asm p RRR RRR RRR KKK KK RK koc RAR kk ke RK KEK KKK KK RK KR KKK KKK ke kk KEK koc ke kk ke ck koc KK KKK KK MAIN RAM IRX i Start of memory for MAIN module is defined in include NramNram irx OR KREE EK KER ELL ARE SERRE ORO y SOR GER AH A EORR ORO ORE CC AU oboli e e v EEE stole eee Timer 2 interrupt variables save tim2 stat equRAMSTART CUSTOMER 2 1 save tim2 a0 equsave tim2 stat 2 1 seconds passed equsave tim2a0 2 1 csave r3 equseconds passed 2 1 csave r5 equcsave r3 2 1 RAMSTART CMM1 equcsave r5 include cmml1 ram irx End of RAM RAMEND CUSTOMER equ RAMEND_CMM1 RAMLENGTH CUSTOMER equ RAMEND CUSTOMER RAMSTART CUSTOMER The new variables csave r3 and csave r5 were added by using the mnemonic for the previous variable plus an offset The next modified file is vroncof2 asm Here new interru
182. atch the rounded upper 16 bits of the resulting product into the PH register SHL An next A Barrel shift the accumulator A 1 or offset accumulator SHLS An A 0 value n bits left n stored in SV register Store the upper 16 bits of the 32 bit shift result to PH 4 4 4 Class 4 Instructions Address Register and Memory Reference Class 4 instructions operate on the indirect register Rx that exists in the ad dress unit ADU Even though the last three registers R5 R7 are special INDEX PAGE and STACK class 4 instructions uniformly apply to all regis ters Subclass 4a provides transfers to and from memory In indirect mode any one auxiliary register can serve as the address for loading and storing the con tents of another Subclass 4b instructions provide some basic arithmetic operations between referenced auxiliary register and short 8 bit constants from program memory These instructions are included to provide efficient single cycle instructions for loop control and for software addressing routines Subclass 4c provide basic arithmetic operations between the referenced auxil iary register and 16 bit constants from program memory These instruction re quire 2 instruction cycles to execute Also a compare to R5 INDEX is provided for efficient loop control where the final loop counter value is not chosen to be zero Table 4 21 Class 4a Instruction Encoding MEE EC EC ECS e ee eee Sa eee O EN E E E E E A HO
183. bal flags are located at fixed locations in the first 64 RAM addresses and 2 flag relative address whereby a reference is made relative to the current PAGE R6 The relative address supports 64 different flags whose PAGE offset values are stored in the PAGE register The flag mode instructions cannot address memory in the INDEX relative modes See Chapter 4 Assembly Language Instructions for more details 2 3 2 Data Memory Addressing Modes The DMAU provides a powerful set of addressing modes to enhance the per formance and flexibility of the C6xx core processor The addressing modes for RAM fall into three categories _j Direct addressing Indirect addressing with post modification _j Relative addressing The relative addressing modes appear in three varieties Immediate Short relative to the PAGE R6 register The effective RAM address is R6 a 7 bit direct offset _j Relative to the INDEX R5 register The effective RAM address is R5 an indexed offset Lj Long Immediate relative to the register base The effective RAM address is Rx a 16 bit direct offset Refer to Chapter 4 Assembly Language Instructions for a full description of how these modes are used in conjunction with various instructions MSP50C6xx Architecture 2 13 Program Counter Unit 2 4 Program Counter Unit 2 5 Bit Logic Unit The program counter unit provides addressing for program memory onboard ROM It includes
184. bit O Offset Accumulator MULTIPLIER UNIT performs multiplication and barrel shifting MULTIPLIER UNIT INPUTS MSB 16 bit LSB 16 bit PH Product High PL Product Low readable and writeable by Data Memory a simulated register PL is realized in ALU A readable and writeable by ALU A t Also write able by Program Memory 2 2 2 Arithmetic Logic Unit The arithmetic logic unit is the focal point of the computational unit where data can be added subtracted and compared Logical operations can also be performed by the ALU The basic hardware word length of the ALU is 16 bits however most ALU instructions can also operate on strings of 16 bit words i e a series or array of values The ALU operates in conjunction with a flexible 16 bit accumulator register block The accumulator register block is composed of thirty two 16 bit registers which further enhances execution and promotes compact code The ALU has two distinct input paths denoted ALU A and ALU B see Figure 2 4 The ALU A input selects between all zeros the internal databus the product high register PH the product low PL or the offset output of the accumulator register block The ALU B input selects between all zeros and the output from the accumulator register block MSP50C6xx Architecture 2 7 Computation Unit The all zero values are necessary for data transfers and unitary operations All zeros also serve as default values for the registers which
185. bled See MSP50P614 MSP50C614 Computational Modes Section 4 6 Unsigned multiplier mode This bit is one if unsigned multiplier mode is enabled See MSP50P614 MSP50C614 Computational Modes Section 4 6 Overflow mode This bit is one if overflow saturation mode is enabled See MSP50P614 MSP50C614 Computational Modes Section 4 6 Fractional multiplication shift mode This bit is set if fractional mode is enabled See MSP50P614 MSP50C614 Computational Modes Section 4 6 Maskable interrupt enable mode If this bit is zero all maskable interrupts are disabled Reserved for future use Transfer x equal to zero status flag bit In transfer instructions this bit is set if the operation cause the destination result to become zero excluding accumulator and Rx registers Transfer x sign status flag bit In transfer instructions the sign bit of the value is copied to this bit if the destination is not accumulator or Rx registers Indirect register carry out status flag bit This bitis setifan addition to the value of Rxregister caused a carry Indirect register equal to zero status flag bit This bit is set if the Rx register content used by the instruction is zero Accumulator overflow status flag bit This bitis set if an overflow occurs during computation in ALU Accumulator sign status flag bit extended 17th bit This bit is set if the 16 bit the sign bit of the destination accumulator is 1 Accumulator equal to
186. boliza tion is fixed Except EIA Logo The second and third lines are to be filled in by the customer Pop Side Symbolization 64pin PM LLLL LOT TRACE CODE 7 YMLLLLT YM DATE CODE optional 10 char T ASSY SITE optional 10 char 7 TI EIA NO or TI LOGO For 64 PM package the customer may choose between TI EIA No 980 or the TI LOGO on the first line ck ck ck ck ck Ck ck ck 0k ck 0k Ck ck Ck KKK ck Ck ck KKK KKK ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck KKK KK KKK KK ck ck ck ko ck ck ko ck ko ck ck Pk Sk AAA SECTION 3 AUTHORIZATION TO GENERATE MASKS PROTOTYPES AND RISK UNITS This section is to be completed by the customer and sent to TI after the following criteria have been met 1 The customer has verified that the TI computer generated Customer Information 7 17 New Product Release Forms NPRF data matches the original data 2 The customer approves of the symbolization format in Section 2B Applies to packaged devices only I hereby certify that the TI generated verification data has been checked and found to be correct and I authorize TI to generate masks prototypes and risk units in accordance with purchase order in section 1 above In addition in the instance that this is a packaged device I also authorize TI to use the symbolization format illustrated in section 2B on all devices By Title Date
187. by content of data memory location referred by addressing mode adrs and store the most significant 16 bits of product into the PH register No status change 1 1 1 0 O RETf Return from subroutine Load data memory location value addressed by R7 STACK to program counter 1 1 1 0 1 IRETT Return from interrupt routine Load data memory location value ad dressed by R7 STACK to program counter T The entire 17 bit is encoded See Table 4 26 Assembly Language Instructions 4 37 Instruction Classification Table 4 27 Class 5 Instruction Description Continuea Mnemonic Description RPT adrstg Load repeat counter with lower 8 bits of data memory location referred by addressing mode adrs Interrupts are queued during execution MOV STAT adrs Load status STAT register with effective data memory location referred by addressing mode adrs 17 bits with TAG 4 4 6 Class 6 Instructions Port and Memory Reference These instructions provide the basic expansion port of the MSP50P614 MSP50C614 processor IN instructions transfer 16 bit data from one of 16 expansion ports OUT instructions transfer 16 bit data to one of the 16 expansion ports In atypical system the expansion ports are divided into those that serve internal peripheral functions and those that serve external pins For subclass 6b IN and OUT provide bidirectional transfers between the same port address 16
188. clock control The level of deep sleep generated by the IDLE instruction is partially controlled by this bit When this bit is cleared default setting the CPU clock is stopped during the sleep but the MC remains running When the idle state clock control bit is set both the CPU clock and the MC are stopped during sleep Refer to section 2 11 for more information regarding the C6xx s reduced power modes Note Reference Oscillator Stopped by Programmed Disable If the reference oscillator is stopped by a programmed disable then on re enable the oscillator requires some time to restart and resume its correct fre quency This time imposes a delay on the core processor resuming full speed operation The time delay required for the CRO to start is GREATER than the time delay required for the RTO to start a eo e 2 8 4 RTO Oscillator Trim Adjustment Bits 15 through 11 and bit 9 6 bits total in the ClkSpaCtrl effect a software control for the RTO oscillator frequency The purpose of this control is to trim the RTO to its rated 32 kHz specification The correct trim value varies from device to device The user must program bits 15 through 11 and 9 in order to achieve the 32 kHz specification within the rated tolerances Texas Instruments provides the trim value to the programmer of the P614 part with a sticker on the body of the chip For the C6xx parts the correct trim value is located at I O location Ox2Fh MSP50C6xx Architecture 2
189. code Instructions Pro 15 14 fia 12 to o Je v e S a js j2 r Jo outs pore An Lt tt tt tots sit an poo 1 J a Description Output to I O port Word in the accumulator string can be output to one of 64 port addresses String operation writes several consecutive ports starting from port6 specified in the instruction See Also OUT IN INS Example 4 14 56 1 OUTS 0x04 A3 Put the content of acccumulator string A3 to I O port string address 0x04 PADIR port Note that based on string length other consecutive ports may also be written 4 152 Individual Instruction Descriptions 4 14 57 RET Return From Subroutine CALL Ccc Syntax Rep rame Cloak ok wora w With RPT ok Grass RET N R Execution PC TOS TOS R7 R7 R7 2 Flags Affected None Opcode Instructions Pro 15 fia H8 12 fn to o e v oe 5 4s fet CI A E A E E esee EA E e ee B Description Return from call or vectored call Pop stack to program counter continue execution Returns from subroutine calls CALL Cece instructions and interrupts are different because of the way each process is handled In order to prevent execution pipeline problems the interrupt return IRET instruction uses two cycles and the Return RET instruction cannot immediately follow a CALL i e RET followed by a RET should not be allowed See Also CALL Ccc IRET Example 4 14 57 1 RET Returns from subroutine A CALL
190. conditions for each interrupt trigger event The branch operation however is also contingent on whether the interrupt service has been enabled This is done individually for each interrupt using the interrupt mask bits within the interrupt general control register Refer to Section 2 7 Interrupt Logic for more details The ROM location Ox7FFF holds the program destination associated with the hardware RESET event branch happens after RESET LOW to HIGH The location Ox7FFE holds the read write block protection word Refer to Sec tion 2 6 4 HOM Code Security for an explanation of the ROM security scheme 2 6 4 ROM Code Security The C6xx provides a mechanism for protecting its internal ROM code from third party pirating The protection scheme is composed of two levels both of which prevent the ROM contents from being read Protection may be applied to the entire program memory or it can be applied to a block of memory beginning at address 0x0000 and ending at an arbitrary address The two levels of ROM protection are designated as follows Y Direct read and write protection via the ROM scan circuit Lj Indirect read protection which prohibits the execution of memory lookup instructions Forthe purposes of direct security the ROM is divided into two blocks The first block begins at location 0x0000 and ends inclusively at location m x 512 1 where m is some integer Each address specifies a 17 bit word location The sec
191. ctions 4 10 Input Output Instructions The MSP50P614 MSP50C614 processor communicates with other on chip logic as well as external hardware through a parallel I O interface Up to 40 I O ports are addressable with instructions that provide bidirectional data transfer between the I O ports and the accumulators Data input is performed with the IN instruction Class 6 This instruction uses a memory address and a 4 bit port address It can also use an accumulator or offset accumulator and a 6 bit port address String transfers are allowed between the accumulators and the input port Data output is performed with the OUT instruction Class 6 The OUT instruction can specify a memory address and a 4 bit port address It can also use an accumulator or offset accumulator and a 6 bit port address String transfers are allowed between the accumulators and the output port 4 11 Special Filter Instructions The MSP50P614 MSP50C614 processor can perform some DSP functions Fundamental to many filtering algorithms is the FIR structure which requires several parallel operations to execute for each tap of the filter as shown in Figure 4 5 Each tap has 1 multiply and 1 accumulation to obtain the output y for N 1 taps Figure 4 5 FIR Filter Structure N 1 Tap FIR filter Newest sample Oldest sample x k xii x k 2 X k N Y OMM x k 3 A x k 2 xk 2 74 Xxk 1 x k 1 i ui 32 or 48 T YIK Emo hm tm y
192. cution Sets IM bit in status register to a 1 thus enabling interrupts INTD Sets IM bit in status register to a 0 thus disabling interrupts EGLOOP Marks the beginning of loop Queue interrupts and pushes the next PC value onto a temporary stack location 1 1 Sets XM in status register to 1 enabling sign extension mode Sets XM in status register to 0 disabling sign extension mode SFM Sets FM in status register to 1 enabling multiplier shift mode for signed fractional arithmetic RFM Sets FM in status register to 0 enabling multiplier shift mode for unsigned fractional or integer arithmetic SOVM Set OM bit in status register to 1 enabling ALU saturation output DSP mode ROVM Set OM bit in status register to 0 disabling the saturating ALU operation normal mode 4 5 Bit Byte Word and String Addressing The MSP50P614 MSP50C614 has instructions which address bits bytes words and strings in data memory or program memory Data memory is always accessed in bytes by the hardware but is based on the instruction The data memory location is treated as a byte word or flag address There are five different kinds of addresses byte addresses byte string addresses word addresses word string addresses and flag addresses Each type of address is described below Refer to Figure 4 3 and Table 4 40 for reference 1 1 1 1 p p Ud a0 T Byte and byte string address Byte addressing is used
193. d The return is performed by a RET instruction The calling routine is then responsible for moving the stack pointer to its previous location before the arguments were put on the stack Because all functions return via AO the only function return type allowed is integer Our implementation of C allows for function prototyping and checks that prototype functions are called with the correct number of arguments Function Implementation Details declarations or function prototypes are introduced by the mnemonic cmm_func We only allow the new style of function declarations prototypes where the type of the arguments is declared within the function s parentheses For example cmm func bidon int il char i2 is valid but cmm func bidon il i2 int il char i2 is invalid Note The exact implementation of the MSP50C6xx stack is as follows on CALL 1 Increment R7 2 Transfer TOS top of stack register to R7 3 Transfer return address to TOS register on RET 1 next PC TOS 2 transfer R7 to TOS 3 decrement R7 We can freely manipulate R7 before a CALL Ccc and after a RET to load and unload arguments to and from the stack The TOS register should never be altered in the body of a function 5 6 4 Programming Example else inclu inclu inclu inclu inclu endif inclu ifdef CMM The following example implements string multiplication i e the multiplication of 2 integer strings T
194. d in C to C function calls Parame ters are passed on the stack and the return value is always int and always lo cated in a0 The stack usage for function calls is as follows C to C function call The stack is shown after the operation on the bottom is performed Implementation Details R7 Param 2 Param 2 R7 Param 1 Param 1 Param 1 Param 1 R7 R5 Stack data R5 Stack data R5 Stack data Before call Parameter 1 Parameter 2 Code Development Tools 5 31 Implementation Details 5 32 R7 RS Function call R7 R5 ADDB R7 2 MOV R7 R5 R5 R7 MOV 0 R7 MOV R5 0 This is the SP before the C function call C to C function return in ronco return R5 R7 SUBB R7 2 R7 R5 MOV A0 R7 MOV 0 A0 MOV R5 0 R7 R5 Code Development Tools Implementation Details 5 33 Implementation Details 5 34 R7 R5 SUBB R7 4 Implementation Details C to ASM function call The stack is shown after the operation on the bottom is performed R7 R5 Before call R7 R5 Parameter 1 R7 R5 Parameter 2 Code Development Tools 5 35 Implementation Details 5 36 R7 R5 Function call 5 7 C to ASM function return R7 R5 C Efficiency R7 R5 SUBB R7 4
195. d with a jumper or etch on a surface layer of the board The jumper could be removed or etch could be cut and the resistor added when needed TI has two evaluation systems that may be used to develop code The EVA50C605 and the SPEECH EVM requires the appropriate personality card are basic target boards The EVA50C605 has the minimum circuits required for supporting code development It has a socket for the MSP50P614 a socket for a 4M bit EPROM a reset circuit test points for power DAC and I O ports the external oscillator and PLL filter components and the scanport connector The SPEECH EVM is a generic board that supports several TI speech devices by accepting different personality cards This board has the same features as the EVA50C605 plus a battery holder two different speaker Code Development Tools 5 3 MSP50C6xx Development Tools Guidelines amplifiers an 8 position DIP switch and two momentary switches connected to I O pins These boards are discussed more in Sections 5 2 2 and 5 2 4 5 2 MSP50C6xx Development Tools Guidelines This is a summary of the tools needed for code development and speech edit ing for the MSP50C6xx family of speech processors MSP50C614 MSP50C605 MSP50C601 and MSP50C604 5 2 1 Categories of MSP50Cxx Development Tools There are two kinds of tools Code development tools These are hardware and software tools for compiling assembling linking and debugging code for the MSP50C6xx devices
196. d xFLAG instructions is the addres sing modes STAG and RTAG can use adrs addressing modes This in cludes direct short relative relative to R5 long relative and indirect addres sing modes This affects the number of clock cycles it takes to execute xTAG instructions Instruction Syntax and Addressing Modes However xFLAG instructions use flagadrs addressing modes This includes global dma6 and relative R6 6 bit offset Both take only one clock cycle Possible sources of confusion Consider the following code ramo equ0x0000 2 RAM word zero raml equ0x0001 2 RAM word one ram2 equ0x0002 2 RAM word two STAG raml MOV AO raml TAG bit is set in STAT register RTAG raml SFLAG raml This sets the TAG bit of ram2 MOV AO raml TAG bit is not set in STAT register MOV TF1 raml TF1 bit in STAT is set Explanation The first three instructions perform as you would expect The TAG bitis set at the RAM variable ram1 The TAG bitis set in the STAT register when the MOV instruction executes Finally ram1 s TAG bit is cleared The next two instructions are problematic When SFLAG sets the tag bit it will set the tag bit for the second word location ram2 This does not set the TAG bit for ram1 What is worse is that the value in ram1 must be less than 64 dma6 since this is global addressing for SFLAG To access TAG bits for high er RAM the R6 PAGE register is needed The last instructi
197. dd contents of data memory location referred by adrs to accumulator An ADDS An An adrs and store the results in the same accumulator An if A 0 or offset accumulator An A 1 ALU status is modified SUB An An adrs next A Subtract contents of data memory location referred by adrs from SUBS Anr An adrs accumulator An and store the results in the same accumulator An if A 0 or offset accumulator An A 1 ALU status is modified uE An adrs next A Load accumulator An A 0 or offset accumulator An A 1 from data es An adrs memory location referred to adrs ALU status is modified MOV aars An next A Store accumulator A 0 or offset accumulator A 1 to data memory MOVS aars An location referred to by addressing mode adrs Transfer status is modified 4 26 Instruction Classification Table 4 15 Class 1b Instruction Description me eme emm OR An adrs ORS An adrs AND An adrs ANDS An adrs XOR An aars XORS An adrs MOVB An adrsjg MOVBS An adrs g MOVB adrs g An MOVBS adrsjg An CMP An adrs CMPS An adrs MOV aars An MOVS adrs An MULTPL An adrs MULTPLS An aars MOVSPH An MR aars MOVSPHS An MR aars MOVAPH An MR adrs MOVAPHS An MR aars Logical OR the contents of the data memory location in adrs and the selected accumulator Result s stored in accumulator s ALU stat
198. ddressing modes Addressing mode bits except immediate and flag addressing come with an am Rx and pm field These are combined into a single field called adrs The appropriate decoding and syntax for each ad dressing mode with the adrs field is described in Table 4 4 The pmfield only applies to indirect addressing For other addressing modes itis coded as zero Table 4 2 Addressing Mode Encoding EENILICIEIEREIERUIESESENENESERERESENES owes p ye oe A am contains addressing mode bits 5 7 See Table 4 4 for details Rxis the register being used See for Table 4 3 for details pm is the post modification flag See Table 4 3 for details next A is the accumulator pointer premodification field See Table 4 5 for details Assembly Language Instructions 4 9 Instruction Syntax and Addressing Modes Table 4 3 Rx Bit Description Operation Table 4 4 Addressing Mode Bits and adrs Field Description addressing mode encoding adrs Relative epeat Addressing os odios Operationt adrs GENE Modes H clk am Rx x 20 7 pm Be x xe pee e O Dope eem pp oo ar ee qm PT fle Ea RAN Cows DU DEI 111 Rx og Relative to R5 Long relativet t dma16 and offset16 is the second word t np is RPT instruction argument 4 10 Instruction Syntax and Addressing Modes Table 4 5 MSP50P614 MSP50C614 Addressing Modes Summary ADDRESSING Direct Long Relative Relative
199. derflow conditions When properly enabled any of these interrupts may be used to wake the de vice up from a reduced power state In a deep sleep state they can also be used to wake the device when used in conjunction with the ARM bit Please refer to Section 2 11 Heduced Power Modes for information regarding the MSP50C6xx s reduced power modes Peripheral Functions 3 7 VO A summary of the interrupts is given in Table 3 1 Table 3 1 Interrupts Interrupt Vector Source Trigger Event Priority Comment INTO Ox7FFO DAC Timer Timer underflow Highest Used to synch speech data INTA Ox7FF1 TIMER1 Timer underflow 2nd INT2 Ox7FF2 TIMER2 Timer underflow 3rd INT3 Ox7FF3 PDo Rising edge 4th Port D goes high INT4 Ox7FF4 PD Falling edge 5th Port Dz goes low INT5t Ox7FF5 All port F Any falling edge eth Any F port pin goes from all high to low INT6 Ox7FF6 PDa Rising edge 7th Port D4 goes high INT7 Ox7FF7 PDs Falling edge Lowest Port Ds goes low T All F port pins must be high previous to one or more going low t INT6 and INT7 may be associated with the Comparator function if the Comparator Enable bit has been set i 1 ries E oc Note Interrupts in Reduced Power Mode An interrupt may be lost if its event occurs during power up or wake up from a reduced power mode Also note that interrupts are generated as a divided signal from the master clock
200. ditional on TF2 1 Not condition TF2 0 Conditional on TAG 1 Not condition TAG 0 Conditional on IN1 1 status Not condition IN1 0 Conditional on IN2 1 status Not condition IN2 0 Unconditional Conditional on XZF 1 Not condition XZF 0 Conditional on XSF 1 Not condition XSF 0 Conditional on XSF 0 and XZF 0 Not condition XSF 0 or XZFz0 reserved reserved 1 reserved 0 reserved 1 reserved Assembly Language Instructions 4 197 Instruction Set Summary 4 16 Instruction Set Summary Use the legend in Section 4 13 and the following table to obtain a summary of each instruction and its format For detail about the instruction refer to the detail description of the instruction eme etsare ESE eris winner or ons hom a me ia mers u po arciancimmietron 2 p 2 we a oo LSSI e P pos CUSCO II 4 ms P we fome fe Rm M em Lo mm nme LL IS mos nme uerie p merus Tees qu pes arcianchenat ws 2 wR fa pes Jem wee Lom P pes jwunam wee ms P pw ewm mer Teens e CON CESTAS E 2 p 3 gt CCOO arci arantnewa 3 4 se _ no mue me fe E SI ons PA E es aaa Ta ICI mos anar EA NE 2e 2 m Table 4 46 Table 4 46 ee po pl Le LEN Ey 4 198 Instruction Set Summary CAN CTS ANI jew aria jour antimmreinona 2 ET VE RENS ws Janie ee LC SENE RUN E ee CMPS An An INICIO FCI
201. dressed by the instruction and store back to TF1 or TF2 respectively XOR TFn flagadrs Logically exclusive OR either TF1 or TF2 with flag bit 17th bit from data memory in flagaars if Not 1 or inverted value if Not 0 addressed by the instruction and store back to TF1 or TF2 respectively MOV flagadrs TEn Store TF1 or TF2 to flag bit 17th bit from data memory referred by flag addressing mode flagadrs Table 4 32 RFLAG flagadrs Reset flag bit 17th bit from data memory referred by flag addressing mode flagadrs to 0 Table 4 32 SFLAG flagadrs Set flag bit 17th bit from data memory referred by flag addressing mode flagadrs to 1 Table 4 34 Class 8b Instruction Description Description cop Wemone MOV TFn cc Rx Load a logic value of the tested condition to one of the test flag bits in status register TF1 or TF2 1 OR TFn cc Rx Logically modify one of the two test flags in status register TF1 or TF2 by ORing it with the status condition specified 1 0 AND TFn cc Rx Logically modify one of the two test flags in status register TF1 or TF2 by ANDing it with the status condition specified 1 1 XOR TFn cc Rx Logically modify one of the two test flags in status register TF1 or TF2 by EXCLUSIVE ORing it with the status condition specified For this instruction the polarity of Not is inverted Not 1 for XOR Not 0 for XNOR 4 4 9 Class 9 Instructions
202. e s a ja fet e Tt it it it fs Ps Fo Ts Ts Jos fofofo o Description Resets fractional mode Clears bit 3 in status register STAT Disable multiplier shift mode for unsigned fractional or integer arithmetic See Also SFM Example 4 14 59 1 REM Resets the fractional mode Clears FM bit of STAT Assembly Language Instructions 4 155 Individual Instruction Descriptions 4 14 60 ROVM Reset Overflow Mode Syntax abel rame Glo ok wora w wit RPT ok Grass swm l3 l1 ws ls Execution STAT OM 0 PC PC 1 Flags Affected None Opcode Instructions Pro 15 14 fia 12 to o e v e 8 a a 2 1 fo m a Tt i it i fs Ts Jo it Js To fs To fofo Jo Description Resets overflow mode in status register bit 2 the OM bit Disable ALU saturation output normal mode See Also SOVM Example 4 14 60 1 ROVM Resets the overflow mode to zero 4 156 Individual Instruction Descriptions 4 14 61 RPT Repeat Next Instruction Syntax A a Execution IF RPT adrs g load src to repeat counter ELSE load imm8 to repeat counter mask interrupt repeat next instruction repeat counter value 2 times PC PC w next instruction 1 Flags Affected None Opcode instructions Pro fis fra H3 12 fu to o e v e 8 a s fet fo RPT de Lt Tt fod tt Poe ts fof as aer imme tt tt Tt tt tt st fofofot imme Description Loads srcvalue to repeat counter Execu
203. e 4 6 next A The preincrement A or predecrement A operation on accumulator pointers An or An Not NOT condition on conditional jumps conditional calls or test flag instructions Value in the repeat counter loaded by repeat instruction Value in string register STR offset n n bit offset from a reference register pma n n bit program memory address For example pma8 means 8 bit program memory address If n is not specified defaults to pma16 port n n bit I O port address Rx registers are treated as general purpose registers These bits are not related to any addres sing modes Indirect register bits as described in Table 4 3 S Represents string mode if 1 otherwise normal mode X Don t care Instructions on the MSP50P614 MSP50C614 are classified based on the op erations the instruction group performs see Table 4 11 Each instruction group is referred to as a class There are 9 instruction classes Classes are subdivided into subclasses Classes and opcode definitions are shown in Table 4 11 Table 4 11 Instruction Classification Class Sub Description Class 1 Accumulator and memory reference instructions A Accumulator and memory references with or without string operations and accumulator preincrementing B Accumulator and memory references with or without string operations 2 Accumulator constant reference A Short constant to accumulator Long constant to accumulator 3 Accumulator
204. e ROM is identified Until this occurs execution of any instructions is suspended The same initialization sequence is executed before entry into the special test modes available on the P614 and C6xx EPROM mode emulation mode and trace mode This insures that the protection scheme is always in force when running the processor in one of these modes A dedicated circuit ensures that a switch between emulation mode and trace mode cannot occur without going through the initialization security check This forces all look up tables and long constant references to originate from an external program source when in emulation mode It is possible to switch from trace mode to emulation mode by lowering Vpp but this transition by design does not jeopardize code security 2 6 5 Macro Call Vectors Macro call vectors are similar to CALL instructions except they take an 8 bit address The upper 8 bits is always 7Fh See Section 4 14 84 VCALL for more information on the VCALL instruction 2 7 Interrupt Logic 2 22 An eight level interrupt system is included as part of the C6xx s core processor The initialization and control of these interrupts is governed by the following components the global interrupt enable the interrupt flag register the interrupt mask register and the interrupt service branch Each of these is described below Interrupts must be globally enabled using the INTE instruction and they are globally disabled using the INT
205. e SPEECH EVM has a battery holder and the EVA50C605 does not The SPEECH EVM also has the hardware circuits to drive an 8 Q speaker using the LM386 or H bridge option However the EVA50C605 can only be used with a 32 Q speaker direct drive SDS 6000 The hardware works with SDS6000 software to allow speech editing as well as verification of speech quality through a MSP50x6xx device It connects to a PC through a parallel port 5 2 2 2 Software Tools Definitions MSP50C6xx code development software EMUC6xx The PC based software is used for MSP50C6xx code development and requires Microsoft Windows 957 or 98M operating systems It is one part of the MSP50C6xx code development tools along with the MSP scanport interface and the MSP50C6xx device on an application board Lj TITALKS zip formerly known as FIXEDxx zip This contains the latest version of TI compression algorithms The file TITALKS ZIP contains the base code for the MSP50C6xx which includes all the TI coders MELP CELP LPC and ADPCM There are some sample codes for LCD drivers timer 1 and timer 2 interrupts etc This software provides a good starting point for the customer to develop the code for MSP50C6xx devices Examples of RAM overlay methods have been included for the customers benefit U SDS6000 This software is used for speech editing and is designed to be used with the SDS 6000 hardware Note Please contact TI Speech Applications Grou
206. e address of the previous variable plus the size of that variable The size of VAR1 thus depends on the start address of the next variable In the example below dac buffer starts 2 bytes one word after current buffer This means that current buffer must be one word long The variable after dac buffer save dac r0 starts 2 bytes one word after dac buffer Therefore dac buffer is one word long Similarly save dac stat starts 10 bytes 5 words after save dac regs therefore save dac regs is a variable five words long current buffer 2 1 RESW 1 dac_buffer 2 1 RESW 1 save dac r0 2 1 RESW 5 save_dac_regs 2 5 RESW p The above method should be used to declare all customer variables This is illustrated in the next section 6 4 3 Adding Customer Variables New variables should either be added directly to MAIN RAM IRX or should be included as a module RAM IRX file To add a variable new var size one word would require adding the variable itself and modifying the RAMEND_CUSTOMER constant The original MAIN_RAM IRX file is shown below PRR KR RRR HK RAR RARA KR KKK KEK KR KK KKK KKK KKK KKK KKK KEK KKK KKK KEK KKK KK EK RK MAIN RAM IRX Start of memory for MAIN module is defined in include NramNram irx ck ck ck ck ck ck kk Ck Ck ck kk Sk ck ck kk Ck Ck ck kk Sk ck ck kk Sk ck ck kk Sk KKK KKK KKK KKK kk Sk kk kk kv ko ko ko ko ko kockockokok General purpose variables ledpattern keypress
207. e decoupling capacitor for the Vpp Vss pair which services the DAC These pins are PGA numbers N3and L4 respectively The relatively high current demands of the digital to analog circuitry make this a requirement Refer to section 6 1 for details 7 10 Customer Information Fields in the ROM 7 2 Customer Information Fields in the ROM Customer code information is inserted in the ROM by Texas Instruments This information appears as seven distinct fields within the ROM test area The ROM test area extends from address 0x0000 to 0x07FF The code release information is stored in locations 0x0006 through 0x000C Assuming these addresses are not specifically read protected by the ROM security they are read accessible to the programmer The fields appear as follows MSP50C614 EPROM Test Area Customer Information Fields 16 bit wide the 17th bit is ignored Address 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C Field Description Device number Mask number assigned by TI Reserved Customer code version number Customer code revision number Year mask generated Data mask generated mm dd Example Value 0x0614 for MSP50C614 0x0005 0x0001 0x0005 e g version 1 5 0x1999 0x0816 e g 8 16 1999 Customer Information 7 11 Speech Development Cycle 7 3 Speech Development Cycle A sample speech development cycle is shown in Figure 7 5 Some of the components such as speech recording speech analysis speech
208. e is pushed into the stack by pre incrementing R7 The current PC value is incremented by 2 to compute the final return address and is then stored in the TOS register Thus the TOS register holds the next PC value pointing to the next instruction When the subroutine reaches the RET instruction the program counter PC is loaded with the TOS register Next the TOS is loaded with the value pointed to by R7 Finally the stack register R7 is decremented Figure 4 1 Top of Stack TOS Register Operation Program counter PC Top of stack register TOS Read before incrementing R7 store TOS value Data memory stack area Stack register R7 2 Preincrement during write 2 Postdecrement Increment R7 then guring read 2 The MSP50P614 MSP50C614 development tools use the TOS register for parameter passing The TOS register must be used with caution inside user programs If the TOS register and stack register R7 are not restored to their previous values after using the TOS register in an application the program can hang the processor or cause the program to behave in an unpredictable way Assembly Language Instructions 4 3 System Registers It is recommended to avoid using the TOS register altogether in applications and leave its operation to development tools only 4 2 6 Product High Register PH This register holds the upper 16 bits of the 32 bit result of a multiplication multiply accum
209. e result in accumulator string A3 Assembly Language Instructions 4 143 Individual Instruction Descriptions 4 14 49 NOP No Operation Syntax abel rame Glo ok wora w wit RPT ok Grass jo we 3 l3 lows ls Execution PC PC 1 No operation Flags Affected None Opcode Instructions Pro 15 14 fia 12 to o e v e 8 a H3 2 1 oe AAA EEE et Description This instruction performs no operation lt consumes 1 clock of execution time and 1 word of program memory See Also RPT Example 4 14 49 1 NOP Consumes 1 clock cycle 4 144 Individual Instruction Descriptions 4 14 50 NOTAC One s Complement Negation of Accumulator Syntax labe name dest src mod Clock clk With RPT clk NOTAC An Ani next A Execution premodify AP if mod specified dest NOT src PC PC 1 Flags Affected OF SF ZF CF are set accordingly Opcode Instructions Pro 15 1a ra 12 fro o fe v e 8 a js 2 1 o NOTAC Art Art 1b nexa 1 1 1 fo o neta An ofo foots fo a a Description Premodify accumulator pointer if specified Perform one s complement of src accumulator and store result in dest accumulator See Also NOTACS AND ANDB ANDS OR ORB ORS XOR XORB XORS NEGAC NEGACS Example 4 14 50 1 NOTAC A3 A3 A Predecrement accumulator pointer AP3 One s complement invert bits accumulator A3 and put result in accumulator A3
210. ead the value in seconds passed and clear it in an atomic operation If the value is read and the timer fires before it is cleared one second will be lost The next important feature to note is the inclusion of rpt2 2 before the intd instruction Because of pipeline latency interrupts can still fire for two clock cycles after anintd instruction The rpt temporarily disables interrupts and ensures that an interrupt does not fire and execute an inte before the intd makes it through the pipeline Disabling interrupts ensures that the timer will not fire while the value in seconds passed is being read and altered The sixth file cmm1_ram asm allocates memory for cmm1 asm p RRR RRR RHR KKK RRR KKK KK RK KKK KKK KK EK KEK ko ke RAR RARA koc ek kc ke ck koc kk koc ke ke ke ke ek CMM1_RAM IRX Start of memory for asmroutines module is defined in include NramNram irx PR RK RRR KKK RAR RAR kk kc kk KEK RK KK KKK KEK KKK KKK KK RK KER koc ke kk ke ck koc KKK ke kk ke ek Variables RA End of memory END CMM1 equ RAMSTART CMM1 RA ENGTH CMM1 Variables tempa RA equRAMEND CMM1 RAMSTART_CMM1 In this project cmm1 asm did not use any RAM but it can be allocated just like the RAM for the ISRs For example a variable named tempa could be allocated as follows equ RAMSTART_CMM1 2 1 End of memory END CMM1 equ tempa The last file is the C program main cmm Th
211. ecisions and constructing a logical statement through a branch decision tree the program can sequentially combine several status conditions to directly construct a final logic value TF1 or TF2 which can be used to control a subsequent branch or call This class includes two subclasses Class 8a instructions update one ofthe test flags TF1 or TF2 with alogical combination of the old test flag value and an addressed memory flag value Subclass 8b provides a flexible means of logically combining the test flag TF1 or TF2 with a status condition and storing the results back to the test flag Table 4 32 Class 8a Instruction Encoding MECO ERR CHER ERI CORN NN IA mes pp pj Te To SE ts To D ECTS TEE mh soa nos 1 CC ELE ED DLL tem Assembly Language Instructions 4 41 Instruction Classification Table 4 33 Class 8a Instruction Description MN CN CT MOV TFn flagadrs Load flag bit 17th bit from data memory referred by flag addressing mode flagadrs to either TF1 or TF2 in status register Load with inverted value if Not 1 OR TFn flagaars Logically OR either TF1 or TF2 with flag bit 171 bit from data memory referred by flag addressing mode flagadrs or inverted value if N21 addressed by the instruction and store back to TF1 or TF2 respectively AND TFn flagadrs Logically AND either TF1 or TF2 with flag bit 17th bit from data memory referred by flag addressing mode flagadrs or inverted value if Not 1 ad
212. ed registers To read the register use the IN instruction in conjunction with the port address 0x38 or 0x39 Use the OUT instruction to write Refer to Section 2 6 2 Peripheral Communications Ports for more information MSP50C6xx Architecture 2 23 Interrupt Logic 2 24 Note Setting a Bit in the IFR Using the OUT Instruction Setting a bit within the IFR using the OUT instruction is a valid way of obtain ing a software interrupt An IFR bit may also be cleared using OUT at any time a Assuming the global interrupt enable is set and the specific bit within the IMR is set then at the time of the interrupt trigger event an interrupt service branch is initiated The trigger event is marked by a 0 to 1 transition in the IFR bit At that time the core processor searches all interrupt levels which have both 1 pending interrupt flag and 2 interrupt service enabled The highest priority interrupt among these is selected The program then branches to the location which is stored in the associated Interrupt Vector Section 2 6 3 Inter rupt Vectors This location constitutes the start of the interrupt service routine Instructions in the interrupt service routine are executed until the IRET return instruction is encountered Afterwards any other pending interrupts will be similarly serviced in the order of their priority Eventually the program returns to whatever point it was before the first interrupt service branch
213. ed with 0x100 2 0x200 Example 4 3 10 MOV Al R1 R5 A Refer to the initial processor state in Table 4 8 before execution of this instruction Preincrement AP1 After preincrement A1 is AC22 and A1 is AC6 The contents of the data memory location stored in R1 are loaded into accumulator AC6 R1 is then incremented by R5 Final result AP1 22 AC6 Oxacb R1 R1 R5 0x0202 Note that the addressing of the Rx registers is byte addressing Example 4 3 11 ADD A3 A3 R6 R5 A Refer to the initial processor state in Table 4 8 before execution of this instruction Predecrement AP3 After predecrement A3 is AC28 and A3 is AC12 The contents of the data memory location stored in R6 are added to AC28 The result is stored in accumulator AC12 R6 is then incremented by R5 Final result AP3 28 AC12 AC28 R6 2 0x11A2 0x12AC Ox244E R6 R6 R5 OxSE6 Note that the Rx registers use byte addresses Assembly Language Instructions 4 15 Instruction Syntax and Addressing Modes Example 4 3 12 MOV R5 R5 AO A Refer to the initial processor state in Table 4 8 before execution of this instruction Preincrement APO After preincrement AO is AC3 and AO is AC19 The contents of AC19 are stored in the data memory location in R5 R5 is then incremented by R5 Final result APO 3 R5 0x0004 0x0002 OxFEED Example 4 3 13 MOV A2 RO Refer to the initial processor state in Table 4 8 before execution of this instruc tion
214. editing and speech evaluation require different hardware and software TI provides a speech development tool called the SDS6000 which allows the user to perform speech analysis using various algorithms speech editing for certain algorithms and to evaluate synthesis results through playback of encoded speech Design of the software and hardware development of software and prototype construction are all customer dependent aspects of the speech development cycle Figure 7 5 Speech Development Cycle Speaker Selection Speech Recording Software Writing Prototype Construction Speech Analysis Speech Editing Speech Evaluation Speech Specification Recording Script Software Design Preparation Hardware Design Software Debugging System Evaluation 7 4 Device Production Sequence 7 12 For the speech development group at TI to accept a custom device program the customer must submit a new product release form NPRF This form describes the custom features of the device e g customer information prototype and production qualities symbolization etc Section 1 is completed by the customer and Section 2B is completed by the customer for package sales Section 2A is completed by TI personnel A copy of the NPRF can be found in section 7 6 Copies can be downloaded at www ti com sc speech Device Production Sequence Tl generates the prototype photomask then processes manufactures and tests prototype dev
215. ee section 4 13 Oppa e foja n eppppe 9 E E PETE Ey fe fo fo a JoJo fo oy red te foo fo fo fo fo fo oy mro o hhee Eeee Ce EE ipo ed x peeumes 2 NS NN pepe epe pee Px fom k pma16 4 190 Instruction Set Encoding instructions Ps Pis 14 fia i2 10 9 8 v Fe 5 sa fa 2 1 fo Lis EH de X Eeee IT IT X pma16 EBCRERERERERCRIE CM ERERECRERERERERES C efeje elo we oloo x JMP pma16 Rx JMP pma16 Rx R5 Jcc pma16 Jcc pma16 Rx Jcc pma16 Rx Jcc pma16 Rx R5 MOV adrs An next A MOV An adrs next A MOV aars An MOV Anp imm16 next A MOV MR imm16 next A MOV An An next A MOV An PH next A MOV SV An next A MOV PH Ar next A MOV An gt An next A x ofo p Ti eala e ofo opea an e lojs orse s o a as dma16 for direct or offset16 long relative see section 4 13 Er 1 o lo rea Ao oo 1 o o 1 o A Pt a a foto neta an a Pt 1 jo o 1 oo ft a o fo newa Ao o fo 1 3 1 jo A A ft a 1 o fo rea Ao ols 1 1 o jo fa a Pt a o lo newa an 150 1 0 o o a o Er a fa fo fo neta an 150 90 1 fofa o t 1 o lo eva an o o jo 1 o jo fa A mov MRAn L nexal 1 4 1 fo o nea an 1 50 1 t ojo A o X MOV adrs Rx MOV Rx adrs npbbpbrbI x iati GGC prt e D ae dma16 for direct or offset16 long relative see
216. eees eee eens 3 11 23 9 Gompatalor s ceres arca eu iaa ira Rs 3 15 3 4 Interrupt General Control Register 00 0 c cece eee ees 3 18 3 5 Hardware Initialization States liliis esses 3 20 4 Assembly Language Instructions eseeeeeeeee III 4 1 4 1 Introd ctlOn 2 mehr er Let one ae A n Remb ep a DE 4 2 4 2 System Registers oo occccccccocccccccc eh 4 2 4 2 1 Multiplier Register MR sssseseeee RR 4 2 4 2 2 Shift Value Register SV ssuueusssssseeeese eee 4 2 4 2 3 Data Pointer Register DP ooccccocccccccnoncnn 4 2 4 2 4 Program Counter PC ssssssssessssssesse n 4 2 4 2 5 Top of Stack TOS 0 cece teens 4 3 4 2 6 Product High Register PH 0 cece eee eens 4 4 4 2 7 Product Low Register PL 0 0 cece teens 4 4 4 2 8 Accumulators ACO AC31 0 0 0 2 0c cts 4 4 4 2 9 Accumulator Pointers APO AP3 0 cece eee ees 4 5 4 2 10 Indirect Register RO R7 eect nes 4 5 4 2 14 String Register STR 0 2 e cece eee eens 4 6 4 2 12 Status Register STAT 2 2 cece eect eee eee 4 6 4 3 Instruction Syntax and Addressing Modes 00 cece cece eee e eee eee eee 4 8 4 3 1 MSP50P614 MSP50C614 Instruction Syntax 00 0 0 e cece eee 4 8 4 3 2 Addressing Modes oooccccccccoocccc eet teens 4 9 4 3 3 Immediate Addressing 0c cece eects 4 13 4 3 4 D
217. egister Assembly Language Instructions 4 57 Lookup Instructions 4 58 Lookup instructions make use of the data pointer DP internally The DP stores the address of the program memory location loads the value to the destination and increments it automatically after every load Thus the value of the DP is always the last used program memory address plus one The content of DP changes after the execution of lookup instructions If filter instructions FIRK and CORK are used it is required to context save DP in the interrupt service routine Since these filter instructions use DP to read coefficient data see section 4 10 any interrupt occurring between loading the first coefficient and the execution of a FIRK CORK will change the last value of DP if the interrupt routine uses a lookup instruction DP can be stored in RAM MOV aars DP and a restoration is done as follows MOV An adrs SUB An 0x1 MOV An An Context save and restore of instructions are not required if filter instructions are not used Example 4 9 1 MOV AO 0x100 MOV AO AO DP 0x101 after execution RPT N 2 FIRK A2 RO Beginning of interrupt service routine context save MOV ctx_DP DP ctx_DP stores the present DP 0x101 Some lookup instructions context restore MOV AO ctx DP DP 0x101 SUB AO 0x1 AO 0x100 after execution MOV AO AO DP 0x101 after execution IRET Input Output Instru
218. em registers Sets the clock to run at8 192 MHz If CRO_FLAG is 1 the crystal oscillator is used Otherwise If CRO_FLAG is 0 the resistor trimmed oscillator is used Enables port F pullups Sets the DAC to 10 bits and turns it on Jumps to the label_main in MAIN ASM O O O O L L C L Note Care must be taken when branching to the init code to perform a software reset on parts using resistor trim The resistor trim is set based on the value of fuses blown by the tester when the parts are manufactured The P part does not have these fuses so initially the value at that location is zero If the init routine encounters a zero it knows that it is running on a P part and sets the resistor trim to a constant value RESISTORTRIM This will always work properly after a hardware reset because all IO port locations are set to zero If the programmer branches to the init code to perform a software reset the value at 0x2F may not necessarily be zero The IO addresses are not fully decoded on the P part so writing to Ox2C port G also writes to OX2D Ox2E and Ox2F This means that the value may not be zero during a software reset If this occurs the init code will misidentify the P part as a C part and will use the value at 0x2C as the trim This may cause the P part to run at the wrong speed It is important to consider this if the init code is used as a software reset The C part has fuses at location 0x2C and fully decoded IO port ad dres
219. ength is defined in STR register The program memory string address is stored in accumulator Anor its offset An Store the contents of this address to the accumulator string An or its offset An The string length is defined in STR register Data Manipulation on Strings ADDS An An pma16 ANDS An An pma16 CMPS An pma16 SUBS An An pma16 XORS An An pma16 ADD the accumulator string Anor its offset An with the program memory string at location pma16 and store the result to the accumulator string An or its offset An The string length is defined in STR register Bitwise logical AND the string An or its offset An with the program memory string at location pma16 and store the result in the accumulator string An or its offset An The string length is defined in STR register Compare the accumulator string An or its offset An with the program memory string at location pma16 and store the result in accumulator string An or its offset An The string length is defined in STR register Subtract accumulator string An or its offset An with program memory string at location pma 16 and store the result in accumulator string An or its offset An The string length is defined in STR register Bitwise Logical XOR the accumulator string An or its offset An with program memory string at location pma16 and store the result to accumulator string An or its offset An The string length is defined in STR r
220. ense of the addressed accumulator and the addressed offset accumulator In general if A 1 the instruction uses the offset accumulator as the input operand on single accumulator operand instructions It interchanges the arithmetic order Subtract compare multiply accumulate etc of the two operands when both are used Exceptions to the rule are the instructions NEGAC S NOTAC S MULSPL S MULAPL S MULTPL S SHLSPL S SHLTPL S and SHLAPL S which use the reverse A control A 1 for accumulator A 0 for offset accumulator The A bit in the instruction word controls the destination of the result to be the accumulator A 0 or the offset accumulator A 1 In addition to basic accumulator arithmetic functions this class also includes an accumulator lookup instruction and several register transfer instructions Instruction Classification between the accumulator and the MR SV or PH register As with all accumula tor referenced instructions string operations are possible as well as premodi fication of one of 4 indirectly referenced accumulator pointer registers AP Table 4 19 Class 3 Instruction Encoding CONDON Table 4 20 Class 3 Instruction Description INICIAN CN CN NEGAC An An next A NEGACS An An NOTAC An An next A NOTACS An An MOV An An next A MOVS An An Store the 2 s complement of the source accumulator A 0 or 1 to the destination accumula
221. epp RO AO rd een rl eee ERES Lows Jpop os om oe om i Toese 1 3 5 5 fos none m IE om _ Lowe be Es Lo oes dee a Len r1 ED p EE DL owe S ESA Comer rs 5 lololo n m aes epo 9 9 DE T LOS PEST RTT L esr 1 fo o e 9 pw m TRI Fon 1 9 9 E 1D E99 TE EE x x E T Pow 1 o o i u om mew w Lowe 1 o o m w a Temes Lows prp lo b o o m o o mm i aaa a a AAA 1 1 Wen of this bit depends on at class 3 instruction is SBE 4 4 1 Class 1 Instructions Memory and Accumulator Reference This class of instructions controls execution between data memory and the accumulator block In addition to the explicit opcode field that specifies an arithmetic operation an eight bit data memory addressing mode reference field am Rx pmi e adrs field controls the addressing of one input operand and a 4 bit field An and next Ain class 1a or 2 bit field Anin class 1b selects an accumulator location as the other input operand The results are written to the addressed accumulator location or to the offset accumulator in class 1a if A bit 1 In addition each instruction can be treated as a single word length operation or as a string depending on the string control encoded in the op code s 1 in class 1b and An 11 binary in class 1a Assembly Language Instructions 4 25 Instruction Classification Class 1a provides the four basic instructions of load store
222. er 8 bits of the accumulator is padded with zeros Example 4 5 2 MOV AO 0x0000 MOV AO 0x0001 Refer to Figure 4 4 for this example Both instructions will load the value 0x1234 to the accumulator In word addressing the LSB bit of the address is assumed to be zero Thus in the second instruction the least significant bit of the address is ignored Example 4 5 3 MOV AO 0x0004 2 Refer to Figure 4 4 for this example The word address 0x0004 is referred Multiplication by 2 is necessary to convertthe word address into the equivalent byte address After multiplication the byte address is 0x0008 This instruction will load the value 0x1122 to the accumulator 4 46 Figure 4 4 Data Memory Example Absolute Word Memory Location 0x0000 0x0000 0x0001 0x0002 0x0002 0x0004 0x0003 0x0006 0x0004 0x0008 0x0005 0x000a Example 4 5 4 Data Memory Location even 2 Absolute word memory location Bit Byte Word and String Addressing Data Memory MS Byte LSByte Location odd 0x12 0x34 0x0001 0x56 0x78 0x0003 0x9a Oxbc 0x0005 Oxde OxfO 0x0007 0x11 0x22 0x0009 0x33 0x44 0x000b MOV STR 4 2 MOV APO 2 MOVBS A0 0x0003 Refer to Figure 4 4 for this example The byte string length is 4 It is loaded to the string register STR in the first instruction APO is 2 and it points to AC2 Third instruction loads the value of the string at byte address 0x0003 and subsequently stores its contents into four consecutive
223. er in the PLL circuit therefore allows the master clock and the CPU clock to be adjusted between their minimum and maximum values For either oscillator option the reference frequency 32 768 kHz is multiplied by four before itis accessed by the PLL circuit The base frequency forthe PLL Clock Control therefore is 131 07 kHz and the multiplier operates in increments of this base frequency The minimum multiplication of the base frequency is 1 and the maximum multiplication is 256 The resulting master clock frequency there fore can be varied from a minimum of 131 07 kHz to a maximum of 33 554 MHz in 131 07 kHz steps From the master clock to the CPU clock there is a divide by two in frequency The CPU clock therefore can be setto run between 65 536 kHz and the maxi mum achievable refer to the data sheet in 65 536 kHz steps The maximum required CPU clock frequency for the C6xx is 8 MHz over the entire Vpp range This rate applies to the speed of the core processor Higher CPU clock frequencies may be achieved but these are not qualified over the complete range of supply voltages in the guaranteed specification Figure 2 9 PLL Performance Oscillator Reference Timer Source Option 32 kHz Selected in IntGenCtrl Resistor crystal Trimmed RTO or CRO referenced TIMER2 Selection Made in CIkSpdCtrl TIMER TIMER2 PLL Phase Locked Loop circuit Multiplier Adjusted in ClkSpdCtrl X1 x 256 Master
224. eral init asm io ports irx Sleep asm m isr tim2 isr asm dac isr asm tim1 isr asm B speech m celp ampm qfm days qfm ones qfm teens qfm Code Development Tools 5 47 C Efficiency dsp 5 48 tens qfm melp ampm qfm days qfm ones qfm teens qfm tens qfm ram h ram irx Descriptions of files that are also in Project 1 have been omitted Directory holding files for speech synthesis celp celp irx celp4 obj common util obj util2 0bj general dsp var irx dsputil asm getbits asm speak asm speak irx speak ram irx melp melp irx melp obj sleep asm dac isr asm tim1 isr asm speech celp melp ampm qfm days qfm ones qfm teens qfm tens qfm Directory holding files for celp synthesis Mnemonics used by celp obj Celp synthesis routines Directory holding utility routines Utilities used for synthesis Utilities used for synthesis Directory for non coder specific routines Constants used by the synthesis routines Routines common to the synthesis algorithms Routines for requesting speech data Routines for speaking a phrase Combines irx files for each synthesis algorithm Allocates RAM for speech synthesis Directory holding files for melp synthesis Mnemonics used by melp obj Melp synthesis routines Functions to enter sleep modes DAC interrupt service routine Timer 1 interrupt service routine Directory holding speech data Directory holding CELP speech d
225. es the MSP50C605 can provide up to 37 minutes and the MSP50C604 can provide up to 6 5 minutes of uninterrupted speech The MSP50C604 is de signed to support slave operation with an external host microcontroller In this mode the MSP50C604 can be programmed with a code that communicates with the host via a command set This command set can be designed to sup port LPC CELP MELP and ADPCM coders by selecting the appropriate com mand The MSP50C604 can also be used stand alone in master mode The MSP50C601 MSP50C604 and MSP50C605 use the MSP50P614 as the de velopment version device Introduction to the MSP50C6xx 1 9 Chapter 2 MSP50C6xx Architecture A detailed description of the MSP50C6xx architecture is included in this chap ter After reading this chapter the reader will have in depth knowledge of inter nal blocks memory organization interrupt system timers clock control mech anism and various low power modes Topic Page 2 1 Architecture Overview oseese samne nennen se oneness ee eere 2 2 2 2 Computational ios 2 5 2 3 Data Memory Address Unit Leeeeeeeeeees 2 11 2 47 Program Gounter nit latest 2 14 2 5 E BitiEogiciUnit A t rn A T 2 14 2 6 Memory Organization RAM and ROM 2 15 ZA teruel 2 22 2 8 Clock Control e o a 2 26 2 9 TImeriRteglisterst nna aia 2 31 2 10 Reduced Power Modes seeeeeeeeeeeee 2 33 2 11 Execution Timing2 a area RES 2
226. es on the MSP50P614 MSP50C614 are immediate di rect indirect with post modification and three relative modes The relative modes are Lj Relative to the INDEX or R5 register The effective address is indirect reg ister INDEX Short relative to the PAGE or R6 register The effective address is PAGE 7 bit positive offset Y Long relative to Rx The effective address is indirect register Rx 16 bit positive offset When string instructions are executed the operation of the addressing mode used is modified For all addressing modes except indirect with post modifica tion a temporary copy of the memory address is used to fetch the least signifi cant data word of the string Over the next n instruction cycles the temporary copy of the address is auto incremented to fetch the next n words of the string Since the modification of the address is temporary all Rx registers are un changed and still have reference to the least significant data word in memory String data fetches using the indirect with post modification addressing mode and writes the modified address back to the indirect register at each cycle of the string This will leave the address in the Rx register pointing to the data word whose address is one beyond the most significant word of the string All addressing modes except immediate addressing are encoded in bits O to 7 ofthe instruction s op code Table 4 2 through Table 4 6 show the encoding of various a
227. es one of 8 registers RO R7 to point memory addresses The selected register can be post modified Modifications include increments decrements or increments by the value in the index register R5 For post modifications the register increments or decrements itself by 2 for word operands and by 1 for byte operands Syntaxes are shown in Table 4 9 Table 4 9 Indirect Addressing Syntax Syntax Operation name dest src Rx R5 next A Premodify accumulator pointer if next A is included Add Rx with R5 name Rx R5 src next A name dest src Rx next A Premodify accumulator pointer if next A is included Use address name Rx src next A pointed by Rx Rx content unchanged name dest src Rx next A Premodify accumulator pointer if next A is included Use address name Rx src next A pointed by Rx post increment Rx after use name dest src Rx next A Premodify accumulator pointer if next A is included Use address name Rx src next A pointed by Rx post decrement Rx after use x 0 7 R5 Note that the Rx registers treats data memory as a series of bytes Therefore when a word is loaded Rx increments by 2 Rx decrements by 2 When loading a word address into Rx the address must be converted into a byte ad dress by multiplying by 2 For example if we want Rxto point to the word ad dress 0x100 Rx should be load
228. et to run between 131 07 kHz and 33 554 MHz in 131 07 kHz steps the same as the MC Or the PDM rate can be set to run between 65 536 kHz and the maximum achievable CPU frequency see the MSP50C6xx data sheet SPSS023 Electrical Specifications in 65 536 kHz steps The PDM clock divider determines which of these two ranges apply Within these ranges it is the PLLM that sets the rate ClkSpdCtrl Ox3D Refer to Section 3 2 3 PDM Clock Divider for more information regarding the PDM clock divider and the available combinations of CPU clock rates vs sampling rates Section 2 9 3 Clock Speed Control Register contains more details regarding the PLLM 3 2 2 DAC Control and Data Registers The resolution of the PDM DAC is selected using the control bits in the DAC control register address 0x34 The available options are 8 9 or 10 bits of res olution Bits 0 and 1 in the DAC control register control this option Peripheral Functions 3 9 Digital to Analog Converter DAC DAC Control register Address 0x34 4 bit wide location 03 02 01 00 Set DAC resolution to 8 bits Set DAC resolution to 9 bits Set DAC resolution to 10 bits DM Drive Mode selection 0 C3x style 1 C5x style E pulse density modulation Enable overall DAC enable 0x0 default state of register after RESET low Bit 2 in the DAC control register is used to enable disable the pulse density modulation This bit must be set in order to enable the overall
229. et6 name R6 offset6 TF n For use with flag instructions only Adds lower 7 bits of instruction to a fixed address base reference of zero 64 fixed flags are addressed by this mode beginning at ad dress 0000h For use with flag instructions only Adds lower 7 bits of instruction Isb set to zero to a address base reference stored in the PAGE register R6 64 flags relative to PAGE may be addressed with this mode Table 4 6 Auto Increment and Auto Decrement Modes Operation No modification Aufto decrement Auto increment String mode Table 4 6 describes the accumulator pointer auto preincrement or predecrement syntax Not all instructions can premodify accumulator pointers The next A field is a two bit field using bits 10 and 11 of only certain classes of instructions Instructions with a next A have either a A or a A in the instruction See Table 4 6 Assembly Language Instructions 4 11 Instruction Syntax and Addressing Modes For any particular addressing mode replace the adrs with the syntax shown in Table 4 4 To encode the instruction replace the am Rx and pm bits with the bits required by the addressing mode Table 4 4 For example the instruction MOV An adrs next A indicates all of the following only partial combinations are shown MOV AQ Oxab12 n 0 adrs dma16 Oxab12 MOV A1 R6 0x2f A n 1 adrs R6 0x2f offset7 Ox2f next A A MOV A2 RO R5
230. evice from sleep Note also the state of the idle state clock control bit and the ARM bit if you expect to wake up using MSP50C6xx Architecture 2 37 Reduced Power Modes either type of interrupt internal or external In most cases the state ofthese bits should coincide The interrupt trigger event associated with each of the two internal TIMERs is the underflow condition of the TIMER In order for a TIMER underflow to occur during sleep the TIMER must be left running before going to sleep In certain cases however the act of going to sleep can bring a TIMER to stop thereby preventing a TIMER induced wake up The bottom row of Table 2 4 llustrates the various conditions under which the TIMER will continue to run after the IDLE instruction Note that the reduced power mode DEEP leaves both TIMERs stopped after IDLE This mode cannot therefore be used for a timed wake up sequence Table 2 5 How to Wake Up from Reduced Power Modes Refer to Table 2 3 and Table 2 4 deeper sleep relatively less power Determined by Controls LIGHT MID DEEP Timer interrupts TIMER1 and TIMER2 e Assuming respective IMR bit is set e Assuming ARM bit is set as in C j No wake up If TIMER is running from TIMER then Underflow wakes device A B C Port F and D 3 4 5 if input e Assuming respective IMR bit is set e Assuming ARM bit is set as in C Rising Edge or Falling Edge as appropriate wakes device RESE
231. fected None Opcode pa ae tao ee SEN i oq s on puc Ae E er Nose A E SPP n Description Disables interrupts Resets bit 4 the IM interrupt mask bit of status register STAT to 0 See Also INTE IRET Example 4 14 23 1 INTD Disable interrupts INTD must be always be immediately followed by a NOP Any maskable interrupt occurring after the INTD NOP sequence will not be serviced Assembly Language Instructions 4 107 Individual Instruction Descriptions 4 14 24 INTE Interrupt Enable Syntax Taba same Sek ck wars v wine ok ese m AO OTI Execution STAT IM 1 IM is STAT bit 4 PC PC 1 Flags Affected None Opcode A OA pene ps prepa fi fifififrf frfof fofjofofofofofo Description Enables interrupts Sets bit 4 the IM interrupt mask bit of status register STAT to 1 See Also INTD IRET Example 4 1 INTE Enables interrupts Any maskable interrupts occurring after this instruction is serviced 4 108 Individual Instruction Descriptions 4 14 25 IRET Return From Interrupt Syntax Taba O a Word WP ax ene Fee I2 ICI ICI LE Execution PC lt TOS R7 R7 2 TOS R7 Flags Affected None Opcode ps ee ee E EE ERE E ER ER E ELEC peer pepe penpegason ponere as eee Yo See Also RET CALL Ccc INTE INTD Description Return from interrupt Pop top of stack to program counter Example 4 1 IRET Return from interrupt service routine
232. functionality of the DAC After RESET is held low the default state of bit 2 is clear In this state the output atthe DAC pins is guaranteed to be zero no PDM pulsing During DAC activity the PDM enable bit may also be toggled at any time to achieve the zero state In other words toggling the PDM enable bit from high to low to high brings the DAC output to the known state of zero e A E E Se an A Note PDM Enable Bit By default the PDM enable bit is cleared DAC function is off Data values are outputto the DAC by writing to the DAC data register address 0x30 The highest priority interrupt INTO is generated at the sampling rate governed by the ClkSpdCtrl and the DAC control register The program in software is responsible for writing a correctly scaled DAC value to the DAC data register in response to each INTO interrupt The register at 0x30 is 16 bits wide The data is written in sign magnitude format Bit 15 of the register is the sign bit Bits 14 and 13 are the overflow bits Bits 12 through 3 are the data value bits The MSB is bit 12 and the LSB is bit 5 4 or 3 depending on the resolution DAC Data register Address 0x30 16 bit wide location Write Only 15 14 13 12 10 bit DAC resolution S O O M 9 bit DAC resolution S O O M 8 bit DAC resolution S O O M D D S Sign bit M Most significant data value D Data magnitude O Overflow bits L Least significant data value X ignored
233. g address bits gir EJIIS tnp is RPT argument 4 12 Instruction Syntax and Addressing Modes 4 3 3 Immediate Addressing The address of the memory location is encoded in the instruction word or the word following the opcode is the immediate value Single word instructions take one clock cycle and double word instructions take two clock cycles Syntax name dest src imm next A Where immis the immediate value of a 16 bit number Example 4 3 1 ADD APO Ox1A Assume the initial processor state in Table 4 8 before execution of this instruc tion This instruction adds the immediate value 0x1A to APO Final result APO 0x1A 2 Ox1C Table 4 8 Initial Processor State for the Examples Before Execution of Instruction Registers register value APO 2 AP1 21 0x15 AP2 11 0x0B AP3 29 0x1D RO 0x0454 R1 0x0200 R2 0x0540 R3 0x03E2 R4 0x0000 R5 2 R6 0x03E4 R7 0x0100 AC2 0x13F0 AC1 0x0007 AC17 0x0112 AC20 0x3321 AC3 OXFEED AC28 0x11A2 AC29 0xAB AC19 0x1200 MR 0x1A15 data memory address data word address to convert to byte address multiply by 2 0x022A 0x0400 0x01F2 0x12AC 0x02A1 0x1001 0x012F 0x0000 0x0100 OXOABC 0x0080 0x0000 0x0001 0x499A 0x01FA 0x0112 program memory address data 0x13F0 0x1B12 Example 4 3 2 MOV R5 OxF000 Loads the immediate value OxFO000 to R5 register Final result R5 OxFOOO Examp
234. gh structure like an if else block Because of the fall through structure of switch and if else blocks items occurring first are executed with less overhead than items occurring last If it is known that certain cases will occur more frequently than others the code will execute fastest if the most frequently occurring cases are put before the less frequently occurring ones Space for global variables is allocated at compile time Space for local variables is allocated on the stack at run time This means that the compiler will not generate a warning if local variables exceed the available RAM The compiler will generate an error message if the global variables exceed the available RAM Caution must be used to avoid overflowing the stack by allocating too many local variables During a call parameters return address local variables and the frame pointer are stored on the stack using a stack frame The stack frame structure allows recursive calls but the elegant solution provided by a recursive program is often offset by inefficiency Using recursive calls is not recommended with the C compiler Dividing the program into too many functions can be inefficient also It may be stylish to separate portions of the program into functions based on what they are designed to do but unless the functions will be used in multiple places in the program it is better not to make a function call There is a tradeoff between ROM usage and RAM usage dependi
235. gly src1 is adrs TAG bit is set accordingly Opcode Instructions te fas fra fra rz m o o fe 7 fofsfafsfaf1fo E o o loloLalmenl an ate 0 CL amare fr ar or oferia long rato se seoton ii ae mera an 2 3 To o o 2 7 SUB An Ani PHL next 1 1 oo neta An Joji o fo o fa a SUB ACA NL na Fifi Pipo fo neca an olo tjo ojo o A SUB Art An AnLnexA 3 o o neta An ofo 1fofofo a sus Rx imme o 1 fofofofo m Jojo sue es ilslrleisde slololslol mx Jofo Description Subtract value of src from value of dest and store result in dest If three operands are specified then subtract value of src from value of src i e src src1 and store result in dest string Premodification of accumulator pointers is allowed with some operand types Note that subtraction is performed in 2 s complement and therefore the CF carry flag may get set even when subtracting a smaller value from a larger value 4 176 Individual Instruction Descriptions SUB Ari 1 An ads next A Subtract Product High PH register from An store result in An See Also SUBB SUBS ADD ADDB ADDS Example 4 14 80 1 SUB Al Al 74 Subtract 74 decimal immediate from accumulator A1 put result in accumulator A1 Example 4 14 80 2 SUB AO AO 2 A Pre increment pointer APO subtract 2 from new accumulator AO put result in accumulator AO Example 4 14 80 3 SUB Al Al
236. gure 2 8 Interrupt Initialization Sequence INTD instruction Global Interrupt Enable Interrupt Trigger Event Internal Timer Underflow INTE A x CLEAR instruction External Input Falling Edge e External Input Rising Edge e Software Write Instructiont SET BIT v INT Flag bits IFR Associated With the Interrupt Trigger Event Interrupt Flag Register 0x39 INT Mask bits IMR Specific Enable for Interrupt Service Interrupt General Control Register 0x38 t Interrupt Interrupt Service Branch Service Routine Highest Priority INT is Selected From 1 of 8 Among Those Flagged and Enabled Program Branches to Location Stored in Interrupt Vector Interrupt Vector Storage Ox7FFO Ox7FF2 0x7FF4 0x7FF6 Ox7FF1 Ox7FF3 Ox7FF5 0x7FF7 t The port addressed write instruction OUT can be used to SET or CLEAR bits in the IFR and IMR MSP50C6xx Architecture 2 25 Clock Control 2 8 Clock Control In addition to being individually enabled all interrupts must be GLOBALLY enabled before any one can be serviced Whenever interrupts are globally disabled the interrupt flag register may still receive updates on pending trigger events Those trigger events however are not serviced until the next INTE instruction is encountered After an interrupt service branch it is the responsibility of the programmer to re SET the global interrupt enable using the INTE instruction 2 8 1 Oscillat
237. h Bits 5 through 16 are left uninitialized Bit Bit Name Initialized Value Description 0 Extended sign mode disabled Unsigned multiplier mode disabled allows signed multiplier mode D 3 1 Overflow mode disabled allows ALU normal mode Shift mode for fractional multiplication disabled allows unsigned fractional integer arithmetic mm 4 Global interrupt enable bit 5 reserved Reserved for future use 6 XZF Transfer equal to zero status bit 7 XSF Transfer sign status bit 8 RCF Auxiliary register carry out status bit 9 Auxiliary register equal to zero status bit e o O tH o JJ N ste i Accumulator overflow status bit Same state as before RESET Accumulator sign status bit extended 17th bit 12 ZF Accumulator equal to zero status bit 16 bits 13 CF Accumulator carry out status bit 16th ALU bit 14 TF1 Test flag 1 15 TF2 Test flag 2 16 TAG Memory tag 3 22 Chapter 4 Assembly Language Instructions This chapter describes in detail about MSP50P614 MSP50C614 assembly language Instruction classes addressing modes instruction encoding and explanation of each instruction is described Topic Page AT introductiong remos SI 4 2 4 2 System Registers on 4 2 4 3 Instruction Syntax and Addressing Modes 4 8 4 4 Instruction Classification eese 4 22 4 5 Bit Byte Word and String Addressing 4 44 4 6 MSP50P614 MSP50C614 Comp
238. h 48 bit accumulation See section 4 11 for more detail on the setup of coefficents and sample data 4 96 Individual Instruction Descriptions 4 14 15 ENDLOOP End Loop Syntax A ETE E A PAE A E O E Execution If R4 0 decrement R4 by n 1 or 2 PC e first address after BEGLOOP else NOP PC PC 1 Flags Affected None Opcode LC M NN E E 0 EL ERES ESTEE E EE ERE ESTO EF ERES ESER ED EXER E ES DICERE E EUH Description This instruction marks the end of a loop defined by BEGLOOP If register R4 is not negative R4 is decremented by n and the loop is executed again beginning with the first instruction after the BEGLOOP If R4 is negative a NOP instruction is executed and program exits the loop Interrupts queued by BEGLOOP are processed according to their priority This instruction results in an overhead of one instruction cycle per loop cycle compared to two instruction cycle if branching is used If ENDLOOP is used without any argument it assumes n 1 See Also BEGLOOP INTE Example 4 14 15 1 See Example 4 14 7 1 in BEGLOOP Assembly Language Instructions 4 97 Individual Instruction Descriptions 4 14 16 EXTSGN Sign Extend Word Syntax label name dest mod Clock clk With RPT clk eese wipes 3 1 3 1 089 E Execution premodify AP if mod specified new most significant word of dest STAT SF PC PC 1 Flags Affected None Opcode Es NR 9 EB ERES ER EC EXI BEA peo
239. has no effect 4 Accumulators used by ADDS and SUBS when used with PH auto incre ment internal registers not APn So subsequent ADDS and SUBS im mediately following instructions write into higher accumulators 5 The sequence ends with ADDS or SUBS used with PH 6 These sequences may not give same result when single step debugging because single stepping changes the internal state They should be used either with a hardware breakpoint or with fast run mode The breakpoint should be set after the sequence ends For example MULAPL AO AO ADDS AO AO PH The first instruction performs a multiply accumulate with MR and AO and stores PL in AO The second instruction adds PH to the second word of memory string AO and puts the result in accumulator string AO The MULAPL ADDS sequence is a special sequence If A0 is ACO 0xFFFF and MR OxFF after execution ACO 0xFF01 AC1 0x00FE If you replace ADDS AO AO PH with ADDS A1 A1 PH and A1 points to a different accumulator the result is still the same This is because the state generated by MULAPL and other similar instructions described above is used by ADDS instruction If another ADDS AQ AO PH instruction follows the previous one AC2 0x00FE since the ADDS instruction auto increments an internal register not APn The same reason applies for SUBS An An PH instruction IMPORTANT Interrupts may occur between these sequences and the result can be incorrect if the in ter
240. he MSP50C6xx family is quite complex Here the method of overlaying the RAM is explained together with examples of how to add variables for customer code Information about the RAM overlay is contained in the following three include files IRX J MAIN RAM IRX J RAM IRX Y SPK RAM IRX MAIN RAM IRX contains definitions for customer RAM Variable and RAM for other modules in the form of RAM IRX files see below should be added here RAM IRX contains definitions for the RAM used by the coders MELP CELP LPC and ADPCM The only constants which should be changed by the user are STACK and RAMEND DSP The former defines the size of the stack which is 20 words by default The latter defines the amount of RAM consumed by the largest coder in use and hence defines the location of the beginning of customer RAM For example if a program uses both the MELP and CELP coders then RAMEND DSP must be equal to RAMEND MELP If CELP and ADPOM are being used the RAMEND DSP must be setto RAMEND CELP SPK RAM IRX contains definitions for the RAM used by the coders Three of these variable TEMP1 TEMP2 and TEMP3 may be used as general purpose temporary variables SPK RAM IRX should never be edited or modified in anyway Applications 6 9 RAM Overlay 6 4 2 RAM Overlay dac_buffer equ save dac rO equ save dac regsequ save dac statequ RAM is reserved for variables in the following way The start address of the variable is equal to th
241. he same source file with the exception of the first line can be used for C or regular C In the case of regular C ithas to be compiled and linked with cmm_func c define CMM must be present for C compiler ONLY lt stdio h gt S s tdlib h tring h math h el mm_back h mm_func h Code Development Tools 5 27 Implementation Details include cmm_macr h constant int M1 4 0x04C1 constant int M2 4 0x85 1 El note length of p lgp 2 must be at least B 0x71FB 0x011F 0x0 B 0x8FD9 0x08FB 0x0 1gm1 2 lgm2 2 4 cmm func string multiply int p int lgp int ml int lgml int m2 int lgm2 F1 this function string multiplies string ml of length lgml 2 by string m2 of length lgm2 2 and puts the result into string p of length lgp4 int sign i j int mml mm2 pp sign 1 mml calloc sizeof int lgm1 2 mm2 calloc sizeof int lgm2 2 pp calloc sizeof int lgpt2 if test_string m1 0 1gm1 LTS_N neg string mml ml lgml sign 1 else copy string mml1 ml lgml if test string m2 0 1gm2 LTS N neg string mm2 m2 1gm2 sign 1 else copy string mm2 m2 1gm2 for 3 0 3 lt 1gp 2 j 4 pljl1 0 for i 0 i lt lgm2 2 i4 Ft for j 0 j lt lgp 2 j pp j 0 umul_string amp pp 5 28 i mm1 mm2 i 1gm1 F2 cmm
242. he state of ClkSpdCtrl register bit 8 through bit 10 and the ARM bit in IntGenCtrl register Example 4 14 20 1 MOV AO 0 OUT 0x34 AO Turn off DAC MOV AO 0x0400 Turn off clock idle bit 1 OUT 0x3d AO Write in ClkSpdCtrl write only IN AO 0x38 Read IntGenCtrl register value OR AO AO 0x4000 Set ARM 1 OUT 0x38 AO Write to IntGenCtrl IDLE Go to deep sleep mod To understand this routine refer to the Reduced Power Modestable in section 2 11 The bits to be set up to switch to deep sleep mode are as follows set bits 10 of ClkSpdCtrl IO address 0x3d register to 1 and reset bits 8 and 9 of CIkSpdCtrl register to O The PLLM bits are reset to zero in this example which is not a necessary operation Note that the ClkSpdCtrl register is write only Set the ARM bit in the IntGenCtrl I O address 0x38 register to 1 program line 2 and 3 above The lastline executes the IDLE instruction which switches the processor to deep sleep mode 4 104 Individual Instruction Descriptions 4 14 21 IN Input From Port Into Word adrs port4 Table 4 46 Table 4 4 6a A pont Espa e Execution dest content of port6 or port4 PC PC w Flags Affected dest is An OF SF ZF CF are set accordingly dest is adrs XZF XSF are set accordingly Opcode CO 000000000000 00000 Nur peii oe I oc dma16 for direct or offset16 long relative see section 4 13 par eo fol 9 I Descrip
243. helpsto minimize residual power consumption The databus path through ALU A is used to input memory values RAM and constant values program memory to the ALU The PH and PL inputs are useful for supporting multiply accumulate operations refer to Section 2 2 1 Multiplier The operations supported by the ALU include arithmetic logic and comparison The arithmetic operations are addition subtraction and load add to zero The logical operations are AND OR XOR and NOT Comparison includes equal to and not equal to The compare operations may be used with constant memory or string values without destroying any accumulator values 2 2 2 1 Accumulator Block The output of the ALU is the accumulator block The accumulator block is com posed of thirty two 16 bit registers These registers are organized into two ter minals denoted accumulator and OFFSET accumulator The terminals pro vide references for all of the data which is to be held in the accumulator block The accumulator incorporates one half of the 32 accumulator registers ACO AC15 The OFFSET accumulator incorporates the other half AC16 AC31 2 8 Computation Unit Figure 2 4 Overview of the Arithmetic Logic Unit ALU INPUTS ALU A 16 bit ALU B 16 bit selects between selects between all 0 s 9 all 0 s Offset Accumulator Register Accumulator Register Data Memory Program Memory Product Hight Product Lowt ARITHMETIC LOGIC UNIT performs arithme
244. hifted value PL from A1 and store the result in A1 After execution PH contains the upper 16 bits of the 32 bit shift Assembly Language Instructions 4 169 Individual Instruction Descriptions 4 14 74 SHLTPL Shift Left and Transfer PL to Accumulator Syntax label name dest src mod Clock clk With RPT cik sme ants meas Texas to p sure Ash AE not Execution premodify AP if mod specified PH PL src lt lt SV dest PL PC PC 1 Flags Affected OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode CET NN 1 01 01 01101 Ee 8T4 01 T2 8 01 a ao aoe ee eee dma16 for direct or offset16 long relative see section 4 13 EN SHLTPL Art Anie nextal_ 1 1 Jo o neta an tjs fo fo Jo A A Description mm the accumulator pointer if specified Shift accumulator or data memory value pointed by adrs to left nsy bits as specified by the SV register into a 32 bit result The result is zero filled on the right and either zero filled or sign extended on the left based on the setting of the extended sign mode XM bit in the status register The upper 16 bits are latched into the PH register The lower 16 bits of the result PL are transferred to the destination accumulator or its offset This instruction propagates the shifted bit into PH SHLTPL An adrs Shift data memory word left transfer PL to An SHLTPL Ar An next
245. his directive in an assembly language program AORG expression Marks the start of an ABSOLUTE segment code i e a segment that cannot be relocated by the linker expression evaluates to the starting address of the absolute segment in the program memory BYTE expression expression Introduces one or more data items of BYTE size 8 bits The bytes are placed in program memory in the order in which they are declared CHIP TYPE chip name This directive is provided for compatibility with future chips in the same family It defines chip parameters such as RAM and ROM size for the assembler For now the only defined chip name is MSP50C6xx DATA expression expression Introduces one or more data items of WORD size 16 bits The words are placed in the program memory in the order in which they are declared Even though the program memory is 17 bits wide only 16 bits can be read using assembly instructions like MOV A0 AO0 so the DATA directive only stores 16 bits per data expression DB expression expression Equivalent to BYTE directive DEF symbol symbol Equivalent to GLOBAL directive DW expression expression Equivalent to DATA directive Assembler END expression Expression defines the start vector for the current assembly program This directive generates the following assembly code AORG OxFFFF DATA expression which defines the start vector of the program i e the program address where execution begins when
246. ibp mov APnimms 1 tt itis tots an fofofo immo Assembly Language Instructions 4 117 Individual Instruction Descriptions Description Copy value of srcto dest Premodification of accumulator pointers is allowed with some operand types MOV An Arr L next A Move data memory word lower 6 bits to APn register Move product high PH register to data memory Move string register STR byte to data memory Move data pointer DP to data memory Move data memory byte to string register STR Move top of stack TOS to data memory word Load logic value of test condition to TEn bit in STAT registerll MOV SV imm4 Move immediate value to shift value SV register MOV Rx R5 Move R5 to Rx MOV PH Ar next A Move An to PH register 4 118 Individual Instruction Descriptions MOV STR imma Move immediate byte to String Register STR MOV APn imm5 Move immediate 5 bit value to APn register t Accumulator condition flags are modified to reflect the value loaded into either An or An t Signed multiplier mode resets UM bit 1 in status register to O Tl Load the logic value of the test condition to the TFn bit in the status register STAT If the condition is true TFn 1 else TFn 0 See Also MOVU MOVT MOVB MOVBS MOVS Example 4 14 28 1 MOV AO 0x0200 2 A Preincrement accumulator pointer APO Copy content of word memory location 0x0200 to accumulator AO Example 4 14 28 2 MOV 0x0200 2
247. ic RAM The RAM is configured in 640 17 bit words Both memories are designed to consume minimum power at a given System clock and algorithm acquisition frequency A flexible clock generation system is included that enables the software to control the clock over a wide frequency range The implementation uses a phase locked loop PLL circuit to generate the processor clock The Processor clock is programmable in 65 536 kHz steps between 64 kHz and 12 82 MHz The PLL reference clock is also selectable either a resistor trimmed oscillator or a crystal referenced oscillator may be used Internal and peripheral clock sources are controlled separately to provide different levels of power management see Figure 1 2 Functional Description for the MSP50C614 Figure 1 2 Oscillator and PLL Connection a Crystal Reference Oscillator Connections MSP50P614 MSP50C6xx OSCIN OSCOUT PLL 10 MOT 32 768 kHzt ee MOf 22 pFt 75 22pFf C PLL 3300 pFt T Keep these components as close as possible to the OSC N OSCQuT and PLL pins b Resistor Trim Oscillator Connections MSP50C6xx MSP50P614 OSCIN OSCOUT PLL R RTO 470 kQ 1 t 7T C PLL 3300 pFt T Keep these components as close as possible to the OSC y OSCQyrt and PLL pins The peripheral consists of five 8 bit wide general purpose I O ports one 8 bit wide dedicated input port and one 16 bit wide dedicated output port The
248. icable Not Applicable int array 12 Array of characters char Not Applicable forced to even char text 20 Pointer to integer int Not Applicable 2 int j Pointer to character char Not Applicable 2 char string Notes 1 There is a major difference between an MSP50C6xx integer string and an array of 5 5 3 External References integers an array of integers is an ordered set of n 16 bit integers whereas an integer string of length n represents a single integer with 16 n bits In C MSP50C6xx strings are declared as arrays of integers but must be operated upon using the special purpose string arithmetic functions described below As in regular C the above types can be qualified with the word unsigned There is another important qualifier that is special to C constant We made the mnemonic purposely different from the usual C constqualifier because it is not exactly equivalent It is used to initialize arrays in program ROM A good use of it would be for a sine table for example The syntax is simple for example constant int array 10 2 1 2 3 4 5 6 7 8 9 10 dummy will create a series of DATA statements in the assembly language output file Uninitialized constants like dummy above generate a warning and are initialized to zero Constants are to be handled with care Since they cannot be accessed the same way as RAM variables special purpose functions have to be used to utilize constants in a program The most general of
249. ices the customer needs to send the code in QBN format and speech data in BIN format t For MSP50C601 and MSP50C605 devices Texas Instruments will send the verification code in QBN format and the verification speech data in BIN format Texas Instruments recommends that prototype devices not be used in production systems The expected end use failure rate of these devices is undefined however it is predicted to be greater than that of the standard qualified production Customer Information 7 13 Ordering Information 7 5 Ordering Information Because the MSP50C6xx are custom devices they receive a distinct identifi cation as follows CSM 6xx XXX X X Gate Code Family ROM Revision Package or Die CSM Custom Member Code Letter PJM Loopin 100 Pin QFP Synthesizer 614 605 etc PM 64 Pin QFP MSP50C604 With Memory Y Die 7 6 New Product Release Forms NPRF The new product release form is used to track and document all the steps involved in implementing a new speech code onto one of the parent speech devices Section 1 of the NPRF is completed by the customer and section 2B if for package sales and sent to TI with the code Please refer to Section 7 4 of the manual for more information on device production sequence Thefollowing are the NPRFsforthe MSP50C614 MSP50C604 MSP50C605 and the MSP50C601 7 14 New Product Release Forms NPRF NEW PRODUCT RELEASE FORM FOR MSP50C614 SECTION 1 OPTION SELECTION
250. ices for shipment to the customer The number of prototypes is 25 for package sales and 200 for die sales plus additional units if requested All prototype devices are shipped with the following disclaimer Itis understood that for expediency purposes the initial 25 prototype devices and any additional prototype devices purchased were assembled on a prototype i e not production qualified manufacturing line whose reliability has not been characterized Therefore the anticipated inherent reliability of these devices cannot be expressly defined The customer verifies the operation and quality of the prototypes and responds with either written customer prototype approval or disapproval A nonrecurring mask charge that includes the 25 prototype devices is incurred by the customer A minimum purchase is required during the first year of production tCustomer Sends Code in TI sends sample devices QBN or TITAG format and to customer for completes Section 1 of the verification NPRF TI completes Section 2A Customer verifies the of NPRF and sends verifi devices work properly and cation code in QBN for completes Section 4 of the mat with BIST included amp NPRF NPRF form to customer B TI produces the chip Customer verifies in production quantities code is correct Customer signs Section 3 of the NPRF and sends it to TI TI generates prototype parts for Customer verification t For MSP50C601 and MSP50C605 dev
251. ied constant into accumulator ALU status is modified SUBB An imm8 Subtract 8 bit positive constant from accumulator and store result accumulator ALU status modified CMPB An imm8 Modify ALU status with the result of 8 bit positive value subtracted from accumulator Original accumulator value not modified 1 ORB An imm8 Logical OR 8 bit positive constant with accumulator and store result to accumulator ALU status modified 1 1 ANDB An imm8 Logical AND 8 bit positive constant with accumulator Store result to accumulator ALU status modified 111 XORB An imm8 Logical XOR 8 bit positive constant with accumulator Store result to accumulator ALU status modified MOVB MR imm Load 8 bit constant to Multiplier register MR Does not change UM mode in status register but will zero fill the top 8 bits in MR register No change in status Assembly Language Instructions 4 29 Instruction Classification Table 4 18 Class 2b Instruction Description C2b Mnemonic Description 0 0 ADD An An imm16 next A Add long constant to accumulator or offset accumulator if 1 ADDS An An pma16 A 1 and store result to accumulator A 0 or offset accumulator A 1 ALU status modified 1 MOV An imm16 next A Load long constant to accumulator A 0 or 1 ALU status is MOVS An pma16 modified 0 1 SUB Ar An imm16 next A Subtract a long constant from
252. ier under the given set of constraints Digital to Analog Converter DAC Example 3 1 8 kHz Sampling Rate 8 kHz Nominal Synthesis Rate 32 768 kHz Oscillator Reference CIkSpdCtrl Number of Number of PLLM Master CPU Output Instructs Instructs IntGenCtrl Over Register Clock PDM Clock Sampling Between Between DAC PDMCD Sampling Value Rate Rate Rate Rate DAC 8 kHz Precision Bit Factor hex MHz MHz MHz kHz Interrupts Interrupts 8 bits 1 1x Ox OF 2 10 2 10 1 05 8 19 128 128 2x Ox 1E 4 06 4 06 2 03 15 87 128 256 4x Ox 3E 8 26 8 26 4 13 32 26 128 512 8x 0x 7C 16 38 16 38 8 19 64 00 128 1024 0 1x Ox 1E 4 06 2 03 2 03 7 94 256 256 2x Ox 3E 8 26 4 13 4 13 16 13 256 512 Ax 0x 7C 16 38 8 19 8 19 32 00 256 1024 9 bits 1 1x Ox 1E 4 06 4 06 2 03 7 94 256 256 2x Ox 3E 8 26 8 26 4 13 16 13 256 512 4x 0x 7C 16 38 16 38 8 19 32 00 256 1024 0 1x Ox 3E 8 26 4 13 4 13 8 06 512 512 2x 0x 7C 16 38 8 19 8 19 16 00 512 1024 10 bits 1 1x Ox 3E 8 26 8 26 4 13 8 06 512 512 2x 0x 7C 16 38 16 38 8 19 16 00 512 1024 0 1x Ox 7C 16 38 8 19 8 19 8 00 1024 1024 Peripheral Functions 3 13 Digital to Analog Converter DAC Example 3 2 10 kHz Sampling Rate 10 kHz Nominal Synthesis Rate 32 768 kHz Oscillator Reference CIkSpdCtrl Number of Number of PLLM Master CPU Output Instructs Instructs IntGenCtrl Over Register Clock PDM Clock Sampling Between Between DAC PDMCD Sampling Value Rate RATE Rate Rate DAC 10 kHz Precision Bit Factor hex MHz MH
253. ification of accumulator pointers is allowed with some operand types MOVU MR Ar next A Move An to MR register in unsigned multiplier mode MOVU MR aars Move data memory word to MR reset multiplier signed mode See Also MOV MOVB MOVT MOVBS MOVS Example 4 14 33 1 MOVU MR AO A Preincrement accumulator pointer APO Copy the content of accumulator AO to MR register Example 4 14 33 2 MOVU MR R3 Copy the value pointed by R3 to MR Assembly Language Instructions 4 131 Individual Instruction Descriptions Figure 4 8 Valid Moves Transfer in MSP50P614 MSP50C614 Instruction Set Immediate NOTE B Byte move possible S String move possible R5 can be moved to Rx An to An 4 132 Individual Instruction Descriptions 4 14 38 MUL Multiply Rounded Syntax iae rame sre i mod rock ok Word w With RPT ck Class Lowe arth no Execution premodify AP if mod specified PH PL MR src PC PC w Flags Affected srcis An OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode awe 0000000000000 00 pus arizona pro po fees a pop III TUNI ES ECR E t dma16 for direct or offset16 long relative see section 4 13 Description Multiply MR and src The 16 MSBs of the 32 bit product are stored in the the PH register The contents of the accumulator are not changed The upper 16 bits of the result are rounded for MUL An but not
254. ift the accumulator A 1 or 1 value n bits left SHLTPLS An An SV reg Store the upper 16 bits of the 32 bit shift result to PH msbs extended by XM mode bit Transfer the lower 16 bits to accumulator A 0 or offset A 1 ALU status is modified MULTPL An An next A Multiply MR register by accumulator A 1 or offset MULTPLS An An A720 transfer lower 16 bits of product to accumulator 7 A20 or offset accumulator A 1 Latch upper 16 bits of Product to PH register ALU status is modified SHLSPL Ar An next A Barrel shift the accumulator A 1 or offset accumulator SHLSPLS An An A720 value n bits left SV reg Store the upper 16 bits to PH Subtract the lower 16 bits of value from offset A 1 or accumulator A 0 and store in accumulator A 0 or offset accumulator A 1 ALU status is modified SHLAPL An An next A Barrel shift the accumulator A 1 or offset accumulator SHLAPLS An An A 0 value n bits left SV reg Store the upper 16 bits to PH Add the lower 16 bits of value to offset accumulator A721 or accumulator A 0 and store in accumulator A 0 or offset accumulator A 1 ALU status is modified Assembly Language Instructions 4 33 Instruction Classification Table 4 20 Class 3 Instruction Description Continuea INN CN CS MUL An next A Multiply MR register by accumulator A 1 or offset MULS An accumulator A 0 and l
255. ik h 0 x k h 1 x k 1 h 2 x k 2 h N x x k N Assembly Language Instructions 4 59 Special Filter Instructions 4 60 N tap filters ideally require 2N multiply accumulates Four instructions are provided to compute this equation FIR FIRK COR and CORK All filter instructions require overflow modes to be reset since these instructions have built in overflow hardware In addition these instructions must be used with a RPT instruction FIR and FIRK instructions perform 16 16 bit multiplies and 32 bit accumulation in 2 clock cycles per tap The FIR FIRK instruction takes 2N clock cycles for N taps to execute once inside the RPT loop FIRK is useful for fixed filters and requires the minimum amount of data memory However the DP register may need to be context saved and restored since the filter coefficients are in ROM FIR is useful for adaptive filtering or applications where coefficients are provided from an external source FIR does not require a context save and restore for the DP register since both the buffer and the coefficients are in RAM COR and CORK instructions perform 16 x 16 bit multiplies and 48 bit accumulation in 3 clock cycles per tap Once inside the RPT loop the total number of clock cycles for an N tap filter is 3N The COR and CORK instructions are identical in operation and arguments to FIR and FIRK However an additional 16 bit extended accumulate cycle is added to prevent the arithmetic overf
256. in PGA Package of the MSP50P614 sss 7 10 Speech Development Cycle 000 c cece cece es n n 7 12 Contents xi Tables om dg oOo ww ISI IS IN IO N EELE d amp ommo 4 6 4 7 4 8 4 9 4 10 4 11 4 12 4 13 4 14 4 15 4 16 4 17 4 18 4 19 4 20 4 21 4 22 4 23 4 24 4 25 4 26 4 27 xii Signed and Unsigned Integer Representation n nnana onanan 2 5 Summary of MSP50C614 s Peripheral Communications Ports oooo o o 2 17 Programmable Bits Needed to Control Reduced Power Modes oooo o 2 36 Status of Circuitry When in Reduced Power Modes Refer to Table 2 3 2 37 How to Wake Up from Reduced Power Modes Refer to Table 2 3 and Table 2 4 2 38 Destination of Program Counter on Wake Up Under Various Conditions 2 39 Interr pts cis aos A ae eee as 3 8 State of the Status Register 17 bit after RESET Low to High Bits 5 through 16 are left uninitialized 2 0 0 eee 3 22 Status Register S FAT 15 ida LE nee ed rise tu ed ese ee 4 7 Addressing Mode Encoding ooocccccccconcc n 4 9 FocBrti Descrplion A E ARDOR 4 10 Addressing Mode Bits and adrs Field Description oooooccccoccccococon o 4 10 MSP50P614 MSP50C614 Addressing Modes Summary 00200eeee eens 4 11 Auto Increment and Auto Decrement Modes oooccccccccccc eese 4 11 Flag Addressing Field flagadrs for Certain Flag Instruc
257. inary fractions and does not require the user to left shift as it would have been required if the FM bit was not set STAT FM 1 turns off fractional mode Overflow Fractional 4 50 MSP50P614 MSP50C614 Computational Modes Setting Resetting Function Instruction Instruction STAT OM 0 normal Sign Extension Mode Sign extension mode can be enabled disabled by setting resetting the XM bit of STAT When in sign extension mode a multiply operation will copy the 16th bit of the multiplier multiplicand to the 17th bit When multiplied this will give a 17 x 17 bit multiplication producing 34 bit result where the upper two bits 33 d and 34th bits are the sign bits and discarded by the processor Sign extension is also applicable in string mode Sign extension mode is the recommended mode to use for signed number multiplication Example 4 6 1 SXM MOV A0 0x8000 MOV MR 0x8000 MULTPL AO AO This example illustrates the sign extension mode during multiplication Here two negative number 0x8000 are multiplied with 0x8000 to obtain a positive number 0x40000000 If the signs were not extended we would have obtained 0xC0000000 a negative number MSP50P614 MSP50C614 Computational Modes Example 4 6 2 SXM MOV STR 2 2 String length 2 MOV MR 0x8000 MOV AO 0x8000 A load MS Byte MOV A0 0x0000 A load LS Byte MULTPLS AO AO This example illustrates the sign extension mode on a string during multiplication Here two
258. ing after a RESET LOW is zero both TIMERs disabled Refer to Section 3 4 Interrupt General Control Register for sum mary information regarding the IntGenCtrl The TIMER enable bits may be used to start and stop the TIMERs repeatedly in software Switching the enable bit from 1 to O stops the TIMER but the current value in the count down register is retained When the enable bit is subsequently switched from 0 to 1 count down then resumes from the held value The following procedure outlines one of many possible ways to start the TIMERs TIMER2 is given as an example 1 Select the TIMER2 clock source 1 2 MC or RTO CRO bit 9 of the Int GenCtrl address 0x38 2 Clear the TIMER2 enable bit 11 in the IntGenCtrl 3 Loadthe count down register TIM2 with the desired period value ahead of time This prepares TIM2 for counting and also loads the period regis ter PRD2 with its value 4 Be sure the TIMER2 interrupt INT2 has been enabled for service set bit 2 of IntGenCtrl 5 Flip the TIMER2 enable bit from 0 to 1 at the precise time you want count ing to begin 2 10 Reduced Power Modes The power consumption of the C6xx is greatest when the DAC circuitry is called into operation i e when the synthesizer speaks There are however a number of reduced power modes sleep states on the C6xx which may be engaged during quiet intervals The performance and flexibility of the reduced power modes make the C6xx ideal f
259. ing error causes them to be accidentally enabled 5 42 C Efficiency Mainasm asm contains the most complex assembly It is responsible for initializing assembly variables enabling or disabling interrupts and setting up any timers or I O ports It also enables the interrupts The part that is important to the project goasm is called at the beginning of the C main routine LERNER RE A ALS oe CC e ERR RAE ON E p ck ER e c e Main program i Set i o for any peripherals eg ADC chip flash card or LCD and initialize variables as necessary All user code should start here RN EER K EIE KERE EERE AEE e CN EROR SG E AE oes e EERE AE CIS ORO vob heo ce Geo SO E RARA E ER clear the seconds passed counter zaca0 mov seconds_passed a0 Set TIMER2 to run from the RTO CTO 32 kHz and with a 1000ms period Set this by loading TIM2 with 32768 x 1000 1000 minus 1 in a0 IntGenCtrl or a0 TIM2REFOSC set bit 9 CTO clock 32 kHz and a0 TIM2ENABLE clear bit 11 TIM2 enable out IntGenCtrl a0 mova0 32768 1 setup a 250ms period out TIM2 a0 load TIM2 and PRD2 in one step in a0 IntGenCtrl or a0 TIM2IMR TIM2ENABLE set bit 2 TIM2 interrupt enable and bit 11 out IntGenCtrl a0 inte ret In this example it clears seconds passed which was used in the first file timer2 isr asm sets up timer2 to run at a 1Hz interval and enables the interrupts The fifth important file is c
260. ing in the string multiply operations the result of multiplying a string by aninteger can be one word longerthan the input string Unpredictable results may occur if parameter Igr is not at least equal to Igr 1 5 5 10 Constant Functions The only two constant functions implemented in C are x er const and xfer single cmm func xfer const int out int constant in int lg It transfers 1g 2 integers from program ROM starting at address constant in to RAM starting at address out Note that constant inis not doubled because it is used in AO in a MOV AO A0 operation The C compiler takes care of this cmm func xfer single int out int constant in transfers a single value An example of the use of x er const is int array 8 i const int atan 80 8 640 integers hui for 1 0 1 lt 80 1 xfer_const array amp atan i 8 STR_LENGTH 8 now use array normally Sdn BRA Code Development Tools 5 23 Implementation Details 5 6 Implementation Details This section is C specific 5 6 1 Comparisons We use the CMP instruction for both signed and unsigned comparisons The two integers a and b to be compared are in AO and AO CMP AO A0 AO contains a AO contains b AO A0 ACO AZ ANEG 5 0 1 0 0 5 1 1 0 0 0 5 0 0 1 1 5 0 0 1 0 0 1 1 0 5 5 1 1 0 FFFF 0 1 0 1 0 FFFF 0 0 0 FFFF FFFF 1 1 0 FFFF FFFE 1 0 0 FFFE FFFF 0 0 1 Signed comparison of a and b a is i
261. ing of consecutive words Like a byte string word strings use the STR register to define the string length Word strings always start at an even byte address When string instructions are used words are fetched from the first word string memory location to consecutive addresses The word address is the data memory address in bytes This is obtained by multiplying the byte address by two Figure 4 3 Data Memory Organization and Addressing Global flags Relative flags Data memory Data memory 1 Word Flag address even address odd addressest 0000h 0000h 0001h 0001h 0002h 0003h 0002h 0004h 0005h e e nnnn e e e e nnnn MS Byte LS Byte nnnn 1 Note Word address is data memory address or byte address divided by 2 17th Bit T Flag address always accesses the 17th bit of 17 bit wide data word in data memory Assembly Language Instructions 4 45 Bit Byte Word and String Addressing Flag Address The flag or TAG address uses linear addressing from 0 to the size of data memory in 17 bit wide words 0 to 639 for MSP50P614 MSP50Ce61 4 Only the 17th bit is accessible When a word memory location is read the corresponding flag for that location is always loaded into the TAG bit of the status register STAT The flag address always corresponds to a 17 bit wide word address If string instructions are used then the flag bit of the last memory location of the string is loaded into the TAG bit of the
262. ing to the position in the accumulator register file that would correspond to the extended word location For example if a string exists in memory with the value Ox943500000000 3 word string and the value was to be moved to a accumulator as a 64 bit sign extended value the following code would have been without bugs OV APO 0 OVS A0 RO RO POINTS TO VALUE IN MEMORY EXTSGNS AO EXTENDS THE SIGN OF ABOVE ADD IN ACC 3 Since the bug causes the above function to fail the status of the 2 least signifi cant words is equal to zero However the same case will be correctly executed with the desired result with the existing bug MOV APO O0 POINT TO LSW OF ACCUM STRING Assembly Language Instructions 4 99 Individual Instruction Descriptions See Also Example 4 14 17 1 OV AP1 3 OVS A0 RO EXTSGN Al OV APO O OV AP1 3 ZAC Al MOVS AO RO JNS POSITIV E EXTSGN EXTSGNS A0 Point to loc corresponding to extended word in acc RO POINTS TO VALUE IN MEMORY not string version as above Alternatively the following code can do the same thing but requires more code POINT TO LSW OF ACCUM STRING Point to loc corresponding to extended word in acc INITIALIZE EXTENDED SIGN VALUE as positive RO POINTS TO VALUE IN MEMORY branch around negative extension accepting default pos extension INVER
263. ion Used in Opcode encoding only Can be either An or An where n 0 3 Accumulator Pointer register where n 0 3 Low order 5 bits select one of 32 accumulators Addressing mode bits am Rx pm See Table 4 46 Addressing mode which must be provided It should be of the format shown in Table 4 46 The curly braces are not included in the actual instruction The subscript n represents the data size in bits the instruction will use For example adrs g means that the instruction will use 8 bit data from the addressed memory and the upper bits may not be used If nis not provided data width is 16 bits Condition code bits used with conditional branch calls and test flag bit instructions Conditional code mnemonic used with conditional branch calls and test flag bit instructions Curly braces indicates this field is not optional Carry flag Total clock cycles per instruction n bit data memory address For example dma8 means 8 bit location data memory address If nis not specified defaults to dma16 Data pointer register 16 bits Flag addressing syntax as shown in Table 4 47 Test flag bit Used in opcode encoding only Flag addressing syntax as shown in Table 4 48 Fractional mode Global relative flag bit for flag addressing Interrupt enable mode n bit immediate value If n is not specified defaults to imm16 Constant field bits Multiply register 16 bits Accumulator pointer premodification See Table 4 45
264. ion and circular buffer operation Executes in 2 instruction cycles Selected register Rx must be even This instruction also uses R x 1 See section 4 11 for more detail on the setup of coefficients and sample data During FIR execution interrupt is queued Assembly Language Instructions 4 101 Individual Instruction Descriptions See Also RPT FIRK COR CORK Example 4 14 18 1 RPT 0 FIR AO RO Computes the calculation for 2 tap FIR filter with 32 bit accumulation See section 4 11 for more detail on the setup of coefficients and sample data 4 102 Individual Instruction Descriptions 4 14 19 FIRK FIR Filter Function Coefficients in ROM Taba mme CC Sek c Word wine ok ee Syntax rmK An x 0 2 j Am 9a Execution With RPT N 2 mask interrupts RPT counter N 2 MR h 0 first filter coefficient x sample data pointed by Rxeyen h 1 second filter coefficient pointed by DP y result stored in three consecutive accumulators 32 bit pointed by An between every accumulation IF TAG 1 RXeyen RXeven R5 for circular buffering ELSE RXeven if Rx is specified in the instruction ENDIF PC PC 1 final result y Zonas PI ANAA Execution is detailed in section 4 11 Flags Affected None Opcode TE ES EE EE a EE ERR EE ER ER ES ERE rie Anc i tjs oj s o o A jojojo rx fiji Description Finite impluse response FIR filter Execute finite i
265. ion that has an optional parameter LALK 16 bit constant shift The LALK instruction has two parameters The first parameter 16 bit con stant is required The second parameter shift is optional As this syntax shows if you use the optional second parameter you must precede it with a comma Square brackets are also used as part of the pathname specification for VMS pathnames in this case the brackets are actually part of the path name they are not optional Y Braces and indicate a list The symbol read as or separates items within the list Here s an example of a list posu eue Vg This provides three choices or Unless the list is enclosed in square brackets you must choose one item from the list Some directives can have a varying number of parameters For example the byte directive can have up to 100 parameters The syntax for this di rective is Information About Cautions and Warnings byte value values This syntax shows that byte must have at least one value parameter but you have the option of supplying additional value parameters separated by commas Information About Cautions and Warnings This book may contain cautions and warnings This is an example of a caution statement A caution statement describes a situation that could potentially damage your software or equipment This is an example of a warning statement A warning statement describes a situation th
266. ion 2B Applies to packaged devices only I hereby certify that the TI generated verification data has been checked and found to be correct and I authorize TI to generate masks prototypes and risk units in accordance with purchase order in section 1 above In addition in the instance that this is a packaged device I also authorize TI to use the symbolization format illustrated in section 2B on all devices By Title Date FAX this form to 214 480 7301 Attn Code Release Team kk ck ck ck ck Ck Ck ck Ck ck Ck KKK KKK KKK KKK ck Ck Sk KKK ck kk Ck Sk ck kk ck kk ck kk ck kk Ck kk kk Sk kk KKK KKK KKK koko ko ko SECTION 4 APPROVAL OF PROTOTYPES AND AUTHORIZATION TO START PRODUCTION This section is to be completed by the customer after prototype devices have been received and tested I hereby certify that the prototype devices have been received and tested and found to be acceptable and I authorize TI to start normal production in accordance with purchase order By Title Date kk ck KK KKK ck Ck ck Ck ck KKK Ck ck ck Ck Sk KKK KKK ck kk ck kk KK KKK KKK KKK KKK Ck kk kk Sk kk KKK KK KKK KKK KKK Return to Texas Instruments Inc Attn Code Release Team P O Box 660199 M S 8718 Dallas TX 75266 0199 OR Fax to 214 480 7301 Attn Code Release Team Have Questions CALL Code Release Team 214 480 4444 OR E MAIL code rel msp sc ti com 7 20 New Product Release F
267. ion 4 11 for more detail on the setup of coefficents and sample data Assembly Language Instructions 4 95 Individual Instruction Descriptions 4 14 14 CORK Correlation Filter Function Syntax labe ame aes se look ok Word w vine ok ones C eom m em a oe Execution With RPT N 2 mask interrupts RPT counter N 2 MR A O first filter coefficient x sample data pointed at by RXeyen h 1 second filter coefficient pointed by DP y result stored in three consecutive accumulators 48 bit pointed by An between every accumulation IF TAG 1 RXeven RXeven R5 for circular buffering ELSE RXeven if Rx is specified in the instruction ENDIF PC PC 1 final result Y Y p o n PIK gt ANA Execution is detailed in section 4 11 Flags Affected None Opcode pau 1 EEE E eS pesa 08 om Ane tts Jods foto an js ojo me ii Description When used with repeat will execute 16 x 16 multiplication between data memory and program memory 48 bit accumulation and a circular buffer operation Each tap takes 3 instruction cycles Selected register Rx must be even This instruction also uses R x 1 This instruction must be used with RPT instruction See Section 4 11 for more detail on the setup of coefficents and sample data During CORK execution interrupt is queued See Also RPT COR FIR FIRK Example 4 14 13 1 RPT 0 CORK AO RO Computes the calculation for 2 tap correlation filter wit
268. ion of the device Normally the destination of the program on wake up is the interrupt service routine associated with the interrupt which initiated the wake up The start of the interrupt service routine is defined by the program location stored in the respective interrupt vector see Section 2 6 3 Interrupt Vectors This wake up response requires that the global interrupt enable is set before going to sleep use the INTE instruction If the global interrupt enable is CLEAR before going to sleep then the programmed interrupt can still wake the device provided that the respective IMR and ARM bits are set as in Table 2 3 The program counter returns to the location immediately following the IDLE instruction This wake up response may be useful for putting the C6xx into a hold sleep where any number of programmable interrupts can wake the device To accomplish this the appropriate interrupts should be enabled in the IMR Table 2 6 lists the possible destinations of the program counter on wake up Table 2 6 Destination of Program Counter on Wake Up Under Various Conditions State of Interrupt Controls Assuming Wake Up can occur before IDLE Instruction Destination of Program Counter after Wake Up e Global interrupt enable is SET Program counter goes to the location stored in the interrupt vector Respective IMR bit is SET associated with the waking Interrupt e Global interrupt enable is CLEAR Program counter goes to the next instruction
269. ional unit for signed or unsigned arithmetic operations see Section 2 2 1 Multiplier Thesize of the C6xx RAM block is 640 17 bit locations Each address provided by the DMAU causes 17 bits of data to be addressed These 17 bits are operated on in different ways depending on the instructions being executed For most instructions the data is interpreted as 16 bit word format This means that bits O through 15 are used and bit 16 is either ignored or designated as a flag or status bit Data Memory Address Unit There are two byte instructions for example MOVB which cause the proces sor to read or write data in a byte 8 bit format The B appearing at the end of MOVB designates it as an instruction that uses byte addressable argu ments The byte addressable mode causes the hardware to read write either the upper or lower 8 bits of the 16 bit word based on the LSB of the address In this case the address is a byte address rather than a word address Bits O through 7 within the word are used so that a single byte is automatically right justified within the databus Bits 8 through 15 may also be accessed as the up per byte at that same address A third data addressing mode is the flag data mode whereby the instruction operates on only the single flag bit bit 16 at a given address All flag mode instructions execute in one instruction cycle The flags can be referenced in one of two addressing modes 1 global address whereby 64 glo
270. iption AND dest src src mod Bitwise AND src and src and store result in dest Premodification of accumulator pointers are allowed with some operand types AND dest src Bitwise AND dest and src and store result in dest AND TF 7 flagaars AND TFn bit with 17th bit of data memory address referred by addressing mode flagadrs store result in TFn bit in STAT register nis either 1 or 2 AND TFn cc Rx AND test condition cc with TFn bit in STAT register Rx must be provided if cc is one of RZP RNZP RLZP RNLZP to check if the selected Rxis zero or negative Rx should not be provided for other conditionals nis 1 or 2 4 80 Individual Instruction Descriptions See Also ANDS ANDB OR ORB ORS XOR XORB XORS Example 4 14 4 1 AND A3 R4 And word at address in R4 to A3 store result in A3 Decrement value in R4 by 2 word mode after the AND operation Example 4 14 4 2 AND AO AO OxffOf A Predecrement accumulator pointer APO And immediate value OxffOf to register accumulator AO store result in accumulator AO Example 4 14 4 3 AND TF2 0x0020 AND global flag bit at RAM word location 0x0020 to TF2 in the STAT Store result in the TF2 bit in the STAT register Note that flagadrs cannot exceed values greater than Ox003F Example 4 14 4 4 AND TF1 TF2 AND TF1 with TF2 bit in the STAT register and store result in TF1 Assembly Language Instructions 4 81 Individual Instruction Descriptions
271. iption Zero the specified accumulator string See Also ZAC Example 4 14 89 1 ZACS Al Reset the content of offset accumulator string A1 to zero Example 4 14 89 2 MOV STR 32 2 ZACS AO Reset the content of all accumulators to zero It does not matter which accumulator APO is pointing at since all the accumulators are zeroed 4 188 Instruction Set Encoding 4 15 Instruction Set Encoding as De ps s e sIv T RERRAT aDD aria an taa nexra a 1 i o alnowal a ade ADD Ai Art mol noa 3 1 o To Do rea an 9 To To Do To T1 DTE x imm16 CAES ADD ari an Antena 3 1 3 o o ron an o o 3 lo Do fa LUE nma x imm16 wo amp m hE EEEE E ee h ee me Tolo ADD AP mms ajaja apo ff ar oft fol m anos arms popa fofofofo am mm8 n o imm8 fave mina 1 Jo 1 Jo fo melee ele a Tolo ADDS Ar An adrs fo ofo fo al1 1 an X dma16 for direct or offset16 long relative see section 4 13 ADDS Ari Ar pma 6 Eo o ojojs ot Ao ojojojo jo t A EA adrs pmat16 X ADDS Arf An An pita prpofof an fofo ts fofi o PA ADDS Ar Ar PH EREBEBERCREREEIE O ots fo fafa AND An ad ople hll m as dma16 for direct or offset16 long relative see section 4 13 x TETUER O E x imm16 a GO ER ER CR E ea DS aaa AND TEN faga jeep epep lelel 7 9 AND TEn cd Fa Toto oleh e I ajo ANDE An imm afoje foil o 7 ANDS An ads ohil Elm as x dma16
272. irect Addressing 00 c cee eee eens 4 14 4 3 5 Indirect Addressing 000 cece eee 4 15 4 3 6 Relative Addressing 0 cece eects 4 16 4 3 7 Flag Addressing eeri ienne n E E EATR REEERE TRETAT RS 4 19 4 9 8 Tag Fag Bits colita ai ete 4 20 viii Contents 4 4 Instruction Classification 0 ccc nana 4 22 4 4 2 Class 2 Instructions Accumulator and Constant Reference 4 28 4 4 8 Class 3 Instruction Accumulator Reference ococccocccccccccoo 4 30 4 44 Class 4 Instructions Address Register and Memory Reference 4 34 4 4 5 Class 5 Instructions Memory Reference oococcccccccccccccc 4 36 4 46 Class 6 Instructions Port and Memory Reference 4 38 4 4 7 Class 7 Instructions Program Control 00sec ee eee 4 39 4 48 Class 8 Instructions Logic and Bit auauua ananena 4 41 4 4 9 Class 9 Instructions Miscellaneous 0 0c cece eee ee eee 4 42 4 5 Bit Byte Word and String Addressing 0c cece eee eee eee 4 44 4 6 MSP50P614 MSP50C614 Computational Modes 00 ce eee eee eee 4 49 4 7 Hardware Loop Instructions 0 0 cece cette 4 53 48 String INStructions ciber Mi ree ate e breed seep a 4 55 4 9 Lookup Instructions 0 eect II Ih 4 57 4 10 Input Output Instructions 6 0 IIR I 4 59 411 Special Filt rInstr ction escocia dinero rein QEYW SP Y 4 5
273. is provides all of the top level functionality for the project Once all of the previous supporting files have been written writing the C program is very much like writing a regular C program KK RR RR RR RR RR RR RR RR RR RRA RARA e e ke He 5 44 C Efficiency MAIN CMM Revision 1 00 HRK RR RA RAR RAR RAR RARA RARA RR RRA RARA RARA ck k ck ck RARA AAA ke e ke X e x f tinclude ramlram h cmm func goasm an pseudo main asm routine cmm func getSecondsPassed Retrieves the counter maintained by the Timer2 ISR and resets the counter int days 0 int hours 12 int minutes 0 in seconds 0 int ampm 0 Dk ck ck ck Ck ck ck Ck ck Ck Ck ck Ck ck Ck Ck ck Ck ck ck ck ck Ck ck ck ck ck ck ck ck ko ck kk ck ko Sk ko kx kv Mk ko ko kockok Updates time variables for clock ticks that have occured COKXCKCKCKCKCKCKkCKCkCkCkCkCkCkCkCkCkCkCk kCkCkCkCkCkCkCk Ck k Ck ck k ck k ckckckok ck kk ke ke ke X e x ESG cmm func updateTime seconds seconds getSecondsPassed while seconds gt 59 seconds seconds 60 minutes if minutes gt 59 minutes 0 hours if hours 12 if ampm 0 ampm 1 else ampm 0 days if days gt 6 days 0 end days if hours gt 12 hours 1 end hours end minutes end seconds cmm_func main goasm run any assembly stuff that needs to be run while 1 infinite loop updateTime
274. ively incremented to fetch the next n words of the string At the completion of the consecutive operations the actual address stored in the AP register is left unchanged its value still points to the least significant location The AP register therefore is loaded and ready for the next repeatable operation Data Memory Address Unit For some instructions the 5 bit string processor can also preincrement or predecrement the AP pointer value by 1 or 1 before being used by the accumulator register block This utility can be effectively used to minimize software overhead in manipulating the accumulator address The premodification of the address avoids the software pipelining effect that post modification would cause Some C6xx instructions reference only the accumulator register and cannot use or modify the offset register that is fetched at the same time Other instruc tions provide a selection field in the instruction word A or A op code bit This has the effect of exchanging the column addressing sense and thus the source or order of the two registers Also some instructions can direct the ALU output to be written either to the accumulator register or to the offset accumula tor register Refer to Chapter 4 Assembly Language Instructions for more de tails The ALU s accumulator block functions as a small workspace which elimi nates the need for many intermediate transfers to and from memory This al leviates the memory thrashi
275. lacing a breakpoint within two cycles of an IDLE instruction causes a breakpoint while the part is still in a low power mode This will cause the code development tool to lose sync with the hardware This is the same effect as trying to stop execution from the tool while the part is in a low power mode Hardware breakpoints should not be placed within two cycles of a label accessed with a CALL instruction or as an ISR This results in unreliable performance of the breakpoint The breakpoint may not be triggered even though the code is executed Placing the breakpoint a few lines into the routine solves this issue Placing a hardware breakpoint within two cycles of a RET can be unreliable also In general it is best not to place hardware breakpoints at the very beginning or end of subroutines or ISRs Hardware Presence If the tool tries to communicate with the hardware and the hardware is not connected or is powered down it will lose sync It is important to always keep the chip in the socket and powered unless the tool is stopped The tool also communicates with the hardware after linking and when the tool is started Chapter 6 Applications This chapter contains application information on application circuits processor initialization sequence resistor trim setting synthesis code memory overlays and ROM usage Topic Page 6 0 v ApplicationiCircuits dalla ld 6 2 6 2 Initializing the MSP50C6xx seeeeeeeeeenee 6 4 6
276. lator pointer AP1 OR accumulator A1 to accumulator A1 put result in A1 Example 4 14 52 4 OR TF1 R6 0x22 OR TF1 bitin STAT with tag bit 17th bit at relative flag address 0x22 relative to R6 i e R6 0x22 store result in TF1 flag in STAT Example 4 14 52 5 OR TF1 ZF OR ZF flag in STAT register with to TF1 put result in TF1 bit in STAT Example 4 14 52 6 OR TF2 RZP R2 OR TF2 with the condition code RZP Rx 0 flag for R2 and store result in TF2 If the content of R2 is zero then RZP condition becomes true otherwise false TF2 bit in STAT is modified based on this result 4 148 Individual Instruction Descriptions 4 14 53 ORB Bitwise OR Byte Syntax iae rame sese crock ok Word w With RPT ok Class or N R Execution dest dest OR src PC PC 1 Flags Affected OF SF ZF CF are set accordingly Opcode Instructions Pro 15 14 H3 12 fn to o e v e s aaa Jo imm8 JORB An imme Lt ro tjo tjo o an imm8 Description Bitwise OR byte of src and dest Result is stored in dest Only lower 8 bits of accumulator is affected See Also OR ORS AND ANDS XOR XORS NOTAC NOTACS Example 4 14 53 1 ORB A2 0x45 OR 0x45 immediate to accumulator A2 lower 8 bits Assembly Language Instructions 4 149 Individual Instruction Descriptions 4 14 54 ORS Bitwise OR String Syntax label name dest src src1 Clock clk With RPT clk ors an aars Table 4 46
277. le 4 3 3 MOVB MR OxF2 Loads the immediate byte Oxf2 to MR register Final result MR Oxf2 Example 4 3 4 AND AO AO OxFF20 A Assume the initial processor state in Table 4 8 before execution of this instruc tion The source accumulator pointer APO is predecremented After predecre ment AO points to AC1 and AO points to AC17 AC17 is anded with the im mediate 16 bit value OxFF20 and the result is stored in AC1 Final result APO 1 AC1 OxFF20 AND AC17 OxFF20 AND 0x0112 0x0100 Assembly Language Instructions 4 13 Instruction Syntax and Addressing Modes 4 3 4 Direct Addressing 4 14 Direct addressing always requires two instruction words The second word operand is used directly as the memory address The memory operand may be a label or an expression Syntax name dest src dmat16 2 next A name dma16 2 src next A Note the multiplication by 2 with the data memory address This only needs to be done for word addresses i e the address that points to 16 bit words This is not required for byte addresses This is explained in detail in section 4 5 Example 4 3 5 MOV A2 0x022A 2 Refer to the initial processor state in Table 4 8 before execution of this instruc tion Loads the contents of data memory location 0x022A 20x0400 to A2 or AC11 The MSP50P614 MSP50C614 always accesses data memory as byte addresses To read a word address multiply the address by 2 Final result A2
278. les are defined next An integer is used to keep track of each element of the time Global variables can be initialized when they are declared The function updateTime is used to update the time lt calls getSecondsPassed to determine the number of seconds that have passed since the time has been updated It then recalculates the time variables hours minutes etc updateTime does not pass any values when it returns although it is technically of type int like all C functions The main function is the starting point for user code After the 6xx part has been initialized main is called from vroncof2 asm The first call from main is to doasm which is in mainasm asm This is the function that sets up the timer and initializes seconds passed The program then goes into an infinite loop where updateTime is called In later projects this infinite loop will be expanded to scan keys and write to the LCD Example 5 2 Second Project C With Speech 5 46 Adding speech to the first project increases functionality but also increases the complexity of the project C Efficiency Y Root B cmmi asm B cmmi ram irx B flags irx B main cmm B main irx B main ram irx B mainasm asm MW vroncof2 asm B rtc rpj m dsp m celp celp irx celp4 obj common util obj util2 obj m general dsp var irx dsputil asm getbits asm speak asm speak irx spk ram irx m melp melp irx melp obj B modules m gen
279. lized using software The 8 bit width is the true size of the mapped location This is independent of the address spacing which is greater than 8 bits When writing to any of the locations in the I O address map therefore the bit masking need only extend across 8 bits Within a 16 bit accumulator the desired bits should be right justified When reading from these locations to a 16 bit accumulator the IN instruction automatically clears the extra bits in excess of 8 The desired bits in the result will be right justified within the accumulator Peripheral Functions 3 3 VO The following table shows the bit locations of the I O port mapping 8 bit wide location 07 06 05 04 03 02 01 00 A port data register address 0x00 B port data register address 0x08 D port data register address 0x18 E port data register address 0x20 A7 B7 C7 D7 E7 data register C control register 0 IN 1 OUT 0x00 _ state of control register after RESET low t Ports D4 and Ds may be dedicated to the Comparator function if the Comparator Enable bit is set If so then bits 4 and 5 of the D port Control register mustbe CLEAR Please refer to Section 3 3 Comparator for details Port Do is connected to the branch condition COND1 Port D4 is connected to the branch condition COND2 assuming the comparator is disabled Please refer to Section 3 1 4 Branch on D Port and to Section 3 3 Comparator for more info
280. ll arguments are byte string types dest destination of data to be stored after the execution of an instruction Op tional or not used for some instructions Destination is also used as both a source and a destination for some instructions If a destination is specified it must always be the first argument Destinations can be system registers or data memory locations referred by addressing modes This is instruc tion specific src source of first data Optional or not used for some instruction Source can be a system register a data memory location referred by addressing modes or a program memory location This is instruction specific Src1 source of second data Some instructions use a second data source Op tional or not used for some instructions Source 1 can be a system register a data memory location referred by addressing modes or a program memory location This is instruction specific mod pre or post modification of a register The meaning of mod is instruction specific Square brackets represent optional arguments Some instructions have many combinations of source and destination registers and addressing modes The combination is instruction class specific The possible combinations of sources destinations and modifications are de pendent on the instruction class Instruction classes are discussed in detail in Section 4 4 4 8 Instruction Syntax and Addressing Modes 4 3 2 Addressing Modes The addressing mod
281. location 2 2 2 5 2 3 2 0x0F amp 0x04 equates to 0x15 Note that bitwise AND amp operator and OR operator operations are allowed 10 2 5 0x120 expression points to data memory content at 0x120 multiplies decimal 5 to it and finally adds decimal 20 Note that a space is required between successive asterisks Also note that 0x120 indicates content of memory location at 0x120 hex The grammar for expressions and symbols are as follows number number O 1 213 1 41 51 6 7 89 expression number expression expression expression expression expression expression expression expression expression expression expression amp expression expression expression expression expression Code Development Tools 5 11 Assembler expression indicates bitwise complement symbol is any alphanumeric text starting with an alphabetic character a number or an expression Examples SYM1 EQU 12 256 SYM2 EQU SYM1 32 4 SYM3 EQU SYM1 SYM2 0x200 From the above example SYM1 SYM2 and SYM3 are symbols for some ex pression The grammar for a Symbol is as follows symbol expression symbol Expression Restrictions It is recommended that a space be inserted between the operator i e 8 and the symbol or numeric expression to perform arithmetic and bitwise operations For example ADD AO AO 1 2 adds a 1 to AO because the
282. low common in auto correlation filters FIR COR Instructions The execution of the filter instructions is shown in Figure 4 6 To use FIR COR instructions some initial setup is required Consecutive Rxpair RXeven RXeven 1 shouldbe chosen with Rxeyen pointing to the RAM sample buffer array and RXeyen 1 pointing to the RAM coefficient array The MR register should be loaded with the first coefficient A O FIR COR can now execute with a repeat instruction for N taps The value of RXeven is incremented during execution After execution the last value of RXeven points to the sample buffer location where the next sample can be stored FIRK CORK Instructions FIRK CORK instructions work exactly the same was as FIR COR instructions however the coefficient array is located in program memory ROM Instead of loading RXeyen 1 with the pointer to coefficient array in RAM the data pointer DP is loaded with the value of the coefficient array Circular Buffering The easiest way to understand circular buffering is by example Suppose a filter h n has three coefficients Then theoretically to calculate one output sample of the filter the buffer should contain the current sample plus the past 2 samples Since the output y k for a three tap filter is y k h 0 ex k h 1 x k 1 h 2 x k 2 On the C614 the circular buffer must contain N 1 samples In the above ex ample the buffer must contain four locations which is one
283. mer Registers 2 32 Reading from either the PRD or the TIM returns the current state of the register This can be used to monitor the progress of the TIM register at any time Writing to the PRD register does not change the TIM register until the TIM register has finished decrementing to 0x0000 The new value in the PRD register is then loaded to the TIM register and counting resumes from the new value A Note Writing to the TIM Register Writing to the TIM register causes the same value to be written to the PRD register In this case the TIM register is immediately updated and counting continues immediately from the new value LLLLSS S O OOY IAYy290Om iI Each TIMER decrements its count down register at a fixed clock rate The rate is selectable between two existing clock sources the reference oscillator or 1 2 Master Clock The rate of the master clock MC is programmable It is determined by the value loaded to the PLL multiplier Section 2 9 3 Clock Speed Control Register The source to the TIMER is therefore one half the frequency of the programmed master clock 1 2 MC If instead the reference oscillator is selected as the source to the TIMER then the source is either a resistor trimmed oscillator RTO or a crystal oscillator CRO Both reference oscillators are desig
284. mis net ws eo ac jvc PH ne qwe seris nt ne T Does not affect the status flags Execution premodify AP if mod specified dest dest src for two operands dest src src for three operands PC PC w Flags Affected destis An OF SF ZF CF are set accordingly destis Rx RCF RZF are set accordingly src1 is adrs TAG is set accordingly Opcode EX 19 0 01810 aE EIER ELE El ADD An An adrs next A BiB EE EE adrs dma16 for direct or offset16 long relative see section 4 13 amv TESTS Je TIS TIS TA TET A x imm16 pomis P EPPPISLDSPPEPRPEBII aa ppal pp ROD oni A E Ol muc CA 0000000000 CE E fo EA E Assembly Language Instructions 4 75 Individual Instruction Descriptions Description ADD FADD dest sro src ADD src with dest and store the result to dest ADD dest src src LII ADD src with src and store the result to dest Premodify the mod before execution if provided See Also ADDB ADDS SUB SUBB SUBS Example 4 14 1 1 ADD A2 A2 R2 R5 A Decrement accumulator pointer AP2 Add word at address in R2 to A2 put result in A2 Add value in R5 to R2 and store in R2 Example 4 14 1 2 ADD A1 A1 0x1221 Add immediate value of 0x1221 to A1 and store result in A1 Example 4 14 1 3 ADD AO AO PH Add PH to accumulator AO and store result in accumulator AO Example 4 14 1 4 ADD Al Al Al Add accumulator A1 to accumulator A1 put result in accumulator A1 Example 4 14 1
285. mm1 asm This file is responsible for supporting C toassembly function calls Ittakes parameters passed on the stack processes them and returns a 16 bit value in AO In C the 16 bit return value is always of type int g EAK K K K RRR KKK KKK KR KK KKK ke RAR KKK KK RK KEK KKK ko ke kk kc kk koc ke ck ke kc ko RK k KKK KK CMM1 ASM i Revision 1 00 KERER EAE SRA ROB TOS RAROS RIOS AROS BER RM E RRA EREE E E EREE ROS rorg 0x0 global _getSecondsPassed include ramNram irx retrieve the seconds that have passed and reset the counter _getSecondsPassed rpt2 2 interrupt can still fire for 2 cycles intd leaving these out can cause loss of a second movaO0 seconds passed zaca0 Code Development Tools 5 43 C Efficiency mov seconds_passed a0 inte mova0 a0 ret int result The file only has one C callable function getSecondsPassed The function reads the value in seconds passed and returns itin AO All C functions have an underscore preceding their name in assembly The underscore is ignored when programming in C In C a call to this function would look like getSecondsPassed Notice that the underscore is not used here because C is being used instead of assembly getSecondsPassed has very simple functionality but it illustrates several important points First interrupts are disabled with the intd instruction This is extremely important because it is not possible to r
286. mpulse response filter taps using coefficients from program memory and samples from data memory Address reference for data memory is indirect using specified Rx and address reference for program memory is contained in DP register This instruction must be used with RPT instruction When used with the repeat counter it will execute 16 x 16 multiplication between indirect addressed data memory buffer and program memory coef 32 bit accumulation and circular buffer operation Each tap executes in 2 cycles See section 4 11 for more detail on the setup of coefficents and sample data Selected register Rx must be even During FIRK execution interrupts are queued See Also RPT FIR COR CORK Example 4 14 19 1 RPT 0 FIRK AO RO Computes the calculation for 2 tap FIR filter with 32 bit accumulation See section 4 11 for more detail on the setup of coefficients and sample data Assembly Language Instructions 4 103 Individual Instruction Descriptions 4 14 20 IDLE Halt Processor Syntax Tate same Sek ck wars WP ss Lug 3 Lo lw fa Execution Stop processor clocks PC PC 1 Flags Affected None Opcode Lc NN E EET EE ER ER ER ERE ELE E ERES ER EI LONE ET EE ERE EZ ES EREZEZ CHERERERENESEH Description Halts execution of processor An external interrupt wakes the processor This instruction is the only instruction to enter one of the three low power modes defined in section 2 11 Low power modes depend on t
287. mulator A2 4 140 Individual Instruction Descriptions 4 14 46 MULTPLS Multiply String and Transfer PL to Acumulator Syntax labe name sess crock ok Word w With RPT ck crass p wurms aGes ees meras 0 mocos wi Art Execution PH PL MR src An PL PC PC 1 Flags Affected OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode instructions Pro fis fra fis 12 fu to o Js v fofsfofofa rjo MULSPLS An adr rpplebebbiel as x dma16 for direct or offset16 long relative see section 4 13 wusPLSAn An 11 foto st Ao i s fos Jo a a Description Perform multiplication of multiply register MR and value of src string The 16 MSBs of the ng 3 x 16 bit product are stored in the product high PH register The 16 LSBs of the product contained in product low PL register stored in An string MULTPLS An adrs Multiply MR by effective data memory string move PL to An MULTPLS Ar An Multiply MR by An string move PL to An See Also MULTPL MULAPL MULAPLS MULSPL MULSPLS Example 4 14 46 1 MULTPLS A0 R3 Multiply the contents of R3 with MR register and store PL in accumulator string AO Increment R3 by 2 Example 4 14 46 2 MULTPLS A2 A2 Multiply MR register to accumulator string A2 and store PL to accumulator string A2 Assembly Language Instructions 4 141 Individual Instruction Descriptions 4 14 4
288. multiply instructions All multiply multiply accumulate instructions and filter instructions FIR FIRK COR and CORK use the MR register see Section 4 11 for detail 4 2 2 Shift Value Register SV The shift value register is 4 bits wide For barrel shift instructions the multiplier operand decodes a 4 bit value in the shift value register SV to a 16 bit value For example a value of 7H inthe SV register is decodedto a multiplier operand of 0000000010000000 binary In effect this causes a left shift of 7 bits to in the final 32 bit product In other words a nonzero value say k Ox k x 15 in the SV register means padding K number of zeros to the right of the final result 4 2 3 Data Pointer Register DP The data pointer register DP is a 16 bit register that is used to point to a program memory location for various look up table instructions DP is not directly loaded by the user It is loaded during the execution of lookup instructions overwriting the previous content of the DP register Lookup instructions are described in detail in Section 4 9 The DP register auto increments the next logical program memory location after the execution of a lookup instruction In addition to lookup instructions the filter instructions FIRK and CORK see Section 4 11 for detail use the DP pointer to look up filter coefficients It may be required to context save and restore the DP in interrupt service routines 4 2 4 Program Counter PC
289. n mainasm asm two calls are made to setup and initialize the Icd To allow this the labels for the routines were declared external external lcd setio external lcd init set up the LCD _writeNum mova0 r7 2 Call lcd wrbca2 ret _writeCharacter mova0 r7 2 Call lcd setio call lcd init call lcdwchr ret rOWZero call lcd rowO reu rowOne call led_rowl reu In _goasm they are then called to initialize the LCD before it is used In cmm1 asm simple routines for writing characters and numbers were added along with routines to bring the cursor to the beginning of the first and second row writeNum and writeCharacter get a value to write from the stack and then call routines in Icd asm _rowZero and rowOne simply call routines in Icd asm main cmm has been modified by the addition of a function showTime JAAK KKK Ck RR RR RR RR RR RR RRA RA AR Display the time on the LCD AAA cmm func showTime 5 54 int temp rowZero writeNum time WIDTH 0 0 hours writeCharacter 22 writeNum time WIDTH 0 1 minutes C Efficiency writeCharacter writeNum time WIDTH 0 2 writeCharacter if time WIDTH 1 1 0 ampm writeCharacter A seconds else writeCharacter P writeCharacter M writeCharacter switch time WIDTH 1 0 days case 0 wri wri wri bre case 1 wri wri wri bre ca
290. n AO b is in AO Assembly Test Condition eq a b AEQ _ne al b IAEQ t a lt b ALZ _le a lt b IAGT ge a gt b IALZ _gt a gt b AGT 5 24 Implementation Details Unsigned comparison of a and b a is in AO b is in AO Assembly Test Condition ult a b AULT ule a b IAUGT uge a gt b IAULT ugt a gt b AUGT The small number of comparisons was an invitation to use them as vector calls We return a 1 or 0 in AO as the result of the comparison and also set flag 2 if the comparison is true The flag is not currently used by the compiler It is important to note that functions return their results via AO but there is no guarantee that the absolute value of the AO pointer is not changed by the function To compare integers a and b after loading a in AO and b in AO do a vector call to the appropriate comparison routine Assembly Vector eq 0 _ne 1 It 2 _le 3 _ge 4 gt 5 ult 6 ule 7 uge 8 ugt 9 _Ineg 10 We return the result of the comparison in Flag 2 set for TRUE reset for FALSE and in AO 1 for TRUE O for FALSE We have also implemented vector calls for string comparisons There are a few C callable routines that make use of those calls test_string or_string and_string xor_string neg_string not_string Code Development Tools 5 25 Implementation Details 5 6 2 Division Integer division currently requires the use of several accumulator pointers We divide a 16 bit integer located in
291. n Descriptions 4 14 45 MULTPL Multiply and Transfer PL to Accumulator Syntax label name _ dest src mod Clock clk With RPT cik p were fanta oeras ranas Uo ocre Ai arene Execution premodify AP if mod specified PH PL MR src An amp PL PC PC 1 Flags Affected OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode Instructions Pro 15 1a fis 12 P1 Jo 9 Js v e 8 a ja 12 1 Jo MULTPL An dis pplefefbebe fil ams gt x dma16 for direct or offset16 long relative see section 4 13 wutTPL Ari Ari pera 1 1 Jo o neta an ejs ojs t Jo fa a Description Perform multiplication of multiply register MR and value of src The 16 MSBs of the 32 bit product are stored in the product high PH register The 16 LSBs of the product contained in product low PL register are stored in An Certain restrictions apply to the use of this instruction when interrupts are occuring in the background See Section 4 8 for more detail MULTPL aadrs Multiply MR by data memory word move PL to An MULTPL Ar An next A Multiply MR by An word move PL to An See Also MULTPLS MULAPL MULAPLS MULSPL MULSPLS Example 4 14 45 1 MULTPL A0 R3 Multiply the contents of R3 with MR register and store PL in accumulator AO Increment R3 by 2 Example 4 14 45 2 MULTPL A2 A2 A Multiply MR register to accumulator A2 and store PL to accu
292. nDpmPDp i LM pmarol Amod Condionaljump on por D pin PDy 0 nz pmai6I mod ondional ump on portD pin Poi ININ2 pma mod Conaiional jump on por D pin PDO 30 pmai6t mod Oon iionaljampon OF 1 LNOpmat mod __ ConditonaljumponOF 0 JRA omaro Aamo Condionalump on Rabove unsigned IRC omaro Amoa Oon iionaljampon XCE 1 smc prato Amod Conoiionariumponxerz0 Conditional jump on XZF 1 equal t JRNBE pmarol Amo Conditional jump on Rxnot below or equal unsigned JRLZP pma16 Amo _ Conditional jump on Rx lt 0 after post mod 4 112 Individual Instruction Descriptions Instruction JS pmat6 Amod cwdWojmpoF INS pmai6 Rmod CowMenajumpensF O lt JNTAG pma16 Rmod Conditional jump on TAG 0 JTF1 pma16 Rmod Conditional jump on TF1 1 JNTF1 pma16 Rmod Conditional jump on TF1 0 aTFZ omare Ame CemdWondjumponTFa 1 aNTFz omare Amo ___ ConditonaljumponTF2 0 O XSpmariRmod Conditional jump onwansferSF 1 O INS pmarol Amo __ CondionaljumpontransferSF 0 MXZpmat6 Rmod Conditional jump on transfer ZF 1 zero INZ omare Fmd Conditional jump on anster ZF O not equa sZpmat6l Amod CedWendhmponzrF i O INZ pma16 Rmod CondiionaljumponZF 0 t Alternate mnemonics are provided as a way of improving source code readability They generate the same opcode as
293. nc cmm func cmm func cmm func cmm func add string int result int strl int str2 int lg sub string int result int strl int str2 int lg mul string int result int strl int mult int lgl int lgr umul string int result int strl unsigned int mult int lgl int lgr or string int result int strl int str2 int 19g and string int result int strl int str2 int 19 xor string int result int strl int str2 int lg not string int result int strl int 19g neg string int result int strl int 19g copy string int output int input int 19g rshift string int output int input int rshift int lg Hifdef CMM cmm func cmm func cmm func cmm func cmm func Hendif cmm_func cmm_func cmm_func strcpy char outstring char instring strlen char instring calloc int nitems int size malloc int size free int ptr test string int stringl int string2 int lg int oper xfer const int out int cst addr int lg xfer single int out int cst addr ROK CKCKCK KR Ck kk k kk AA 5 20 Note the requirement that C function declarations including main be preceded by the keyword cmm func Also note the conditional assembly portion used for compatibility with Borland C f REA e e x e e e e e e e x KK Macros for C fk Kk ke ke ke ke ke e ke e e e e x f define STR LENGTH i i 2 ES FER ERE o eor Major Differences between C and C C Compiler
294. ncy The master clock in turn runs at a very slow frequency less than 100 kHz in the absence of a reference oscillator Under this condition program execution is supported at a slow rate until one of the two references RTO or CRO is enabled in software Refer to the data sheets for the MSP50Cxx devices Once a reference oscillator has been enabled the speed of the master clock MC can be set and adjusted as desired Bits 7 through 0 in the ClkSpdCtrl constitute the PLL multiplier PLLM The value written to the PLLM controls the effective scaling of the MC relative to the 131 07 kHz base frequency A 0 value in PLLM yields the minimum multiplication of 1 and a 255 value in PLLM yields the maximum multiplication of 256 The resulting MC frequency therefore is controlled as follows MC Master clock frequency kHz PLLM register value 1 x 131 07 kHz CPU Clock frequency kHz PLLM register value 1 x 65 536 kHz Clock Control The configuration of bits in the clock speed control register appears below CIkSpdCtrl register address Ox3D 16 bit wide location WRITE only 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 T5 T4 T8 T2 Ti CoTOR M M M M M M M M T RTO oscillator Trim adjust R enable Resistor trimmed oscillator Idle State clock Control M PLLM multiplier bits for MC C enable Crystal oscillator 0x0000 default state after RESET LOW or TO if R is set Bit 10 in the ClkSpaCtrl is idle state
295. nd asm ram irx The allocation for in ter ram irx begins at memory location 2 This is because the memory location 0 is reserved for use by the C compiler The allocation for asm ram irx be gins where the allocation ended for inter ram irx More irx files can be chained on in this manner and all of the allocation is kept organized When C is add ed to a project it is important to make sure that the C variables are not allo cated in locations already used by assembly variables This is accomplished with a dummy array bogus located in the file ram irx It is simply an integer array that is included in the C program so thatitis the first variable allocated By making its size equivalentto the amount of memory used for assembly vari ables the C variables that the user defines are allocated in unused memory It can be set by building the project and finding the location of the last assembly variable This can then be converted from hexadecimal to decimal and divided by two because a C int is 16 bits to find the correct size for bogus Bogus can be made larger for extra safety as long as enough memory is left over for the C variables and the stack If space allows it is a good idea to add a few extra words to bogus in case assembly variables are added to the project with out modifying bogus It is also important not to alter the contents of registers R5 and R7 R7 is the stack pointer and R5 is a frame pointer use
296. nd select Blank Check Program to burn the code onto a P614 device Alternatively press F3 then Enter Set the breakpoint at the _main label To do this click on the blue magnifying glass icon at the top of the screen then from the Symbol list choose main Click OK and the Program Window will display the label and the surrounding code The line of code at main MOV R7 STACK is highlighted in cyan Setthe breakpoint by moving the mouse to this line holding the SHIFT key and clicking the right mouse button Click on nit Init Allto reset the P614 All the values in the RAM window should turn blue and should be zero 0000 To runthe program click on the yellow lightning black centipede Run Internal icon at the end of the tool bar The program should halt at the main label All the values in the CPU window should be blue and zero apart from PC STAT DP RZF and ZF To continue click on the Run Internal icon again A bugle call is synthesized in CELP and then the program loops round continuously 6 4 RAM Overlay 6 4 1 RAM Usage RAM Overlay Creating a New Project The easiest way to create a new project is to copy the entire TI TALKS604 directory into another directory and renaming the project file as desired It is not necessary to change the paths of the files in the project this will be done automatically by the code development tool Note that TI TALKS604 indicates version 604 of TI TALKS code The RAM map for t
297. ndasm must be at the beginning of a line and that all text following them on the same line is ignored Signals the end of assembly language insertion Must be paired with a asm directive 5 5 4 6 Fitdef Zifndef 5 5 4 7 Hif 5 5 4 8 else 5 5 4 9 Hendif 5 5 5 Include Files Starts conditional assembly if token following it has been defined not been defined by a define directive These directives are terminated by a endif directive and can be coupled with a else directive as in regular C Note that the test can only check if the named token is currently defined or undefined Starts conditional assembly if the expression following it evaluates to a non zero value This directive is terminated by a Hendif directive and can be coupled with a else directive as in regular C See Af directive Must be present to terminate a ifdef or ifndef directive Ee Note Typedef is not supported in C There are currently two include files supplied with C cmm_func h which contains function prototypes for the C functions and cmm macr h which contains some predefined macros Both files are listed below Code Development Tools 5 19 C Compiler KK Ck Ck kk kk kk ke ko ke ke ke ke e ke e e e ee e x x f Prototypes for C functions CK KKK kk Ck kk k kk AA cmm func cmm func cmm func cmm func cmm func cmm func cmm fu
298. ned to run at a nominal 32 kHz Refer to Section 2 9 Clock Control for more information regarding the oscillator configuration and clock programmability Selection between the timer source options is made using two control bits in the interrupt general control register IntGenCtrl The IntGenCtrl is a 16 bit port addressed register at 0x38 Clearing bit 8 selects 1 2 MC as the source for TIMER1 Setting bit 8 selects the reference oscillator as the source for TIM ER1 Similarly clearing bit 9 of the IntGenCtrl selects 1 2 MC as the source for TIMER2 Setting bit 9 selects the reference oscillator as the source for TIM ER2 The default value after a RESET LOW is zero select 1 2 MC as the source Each of the TIMERs counts from the value stored in its period register to 0x0000 These maximum and minimum counts each receive a full clock cycle from the TIMER source This means that the true period of the TIMER from one underflow event to the next is the value stored in the period register plus one Time duration btwn underflows value in PRD 1 frequency of Timer Source TIMER1 and TIMER2 must be enabled for use This is done at the IntGenCtrl register Bit 10 of the IntGenCtrl is the enable bit for TIMER1 and bit 11 is the Reduced Power Modes enable bit for TIMER2 Setting the enable bit enables the TIMER e starts count down running Clearing the enable bit disables the TIMER e stops the count down The default sett
299. ng Scan Port Bond Out Reference Oscillator Signals OSCOUT Resistor crystal reference out OSCIN Resistor crystal reference in PLL Phase lock loop filter Digital to Analog Sound Outputs 22 O Digital to analog plus output 20 O Digital to analog minus output Initialization 38 40 Initialization Power Signals 17 50 90 1004 32 52 9 19t Ground 61 8 31 32 91 21T 23 33 34 10 Processor power tThe Vss and Vpp connections service the DAC circuitry Their pins tend to sustain a higher current draw A dedicated decoupling capacitor across these pins is therefore required 74 Mechanical Information Table 7 3 Signal and Pad Descriptions for the MSP50C601 SIGNAL PIN NUMBER PAD NUMBER y o DESCRIPTION Input Output Ports PCO PC7 89 82 8 1 1 0 Port C general purpose I O PDO PD7 99 92 18 11 1 0 Port D general purpose I O PEO PE7 46 39 48 41 yo Port E general purpose I O PFO PF7 16 9 31 24 Port F dedicated input Pins PD4 and PDs may be dedicated to the comparator function if the comparator enable bit is set Refer to Section 3 3 Comparator for details SCANIN 37 39 Scan port data input SCANOUT 33 35 Scan port data output SCANCLK 36 38 Scan port clock SYNC 35 37 Scan port synchronization TEST 34 36 C605 test modes The scan port pins must be bonded out on any MSP50C601 production board Consult the Important Note regarding Scan Port Bond Out OSCOUT 49 51 O Resistor crys
300. ng on the number of times a function will be needed Using a function call requires more RAM and instruction overhead Not using a function call can require more ROM depending on the size of the function and the number if times it is used C Efficiency 5 7 1 Real Time Clock Example The C clock works as follows The Timer2 ISR is set to fire at 1 second intervals Inside the ISR a counter is incremented by one each time it fires An assembly routine in cmm1 asm _getSecondsPassea disables the interrupts retrieves the counter resets it and turns the interrupts back on The C program calls getSecondsPassed whenever it is not busy and uses the return value to update the clock This keeps the assembly code to a minimum and allows all of the calculations to be handled in C The interrupts are disabled when the counter is being read to prevent possible loss of time _getSecondsPassed rpt2 2 interrupt can still fire for 2 cycles intd leaving these out can cause loss of a second mova0 seconds passed zaca0 mov seconds passed a0 inte movaO a0 ret The example is divided up into three projects The first one is a minimal implementation It does not have support for speech LCD key scanning or setting the time It offers minimum functionality to keep the number of files small It is meant to show the basics of a C project The second project adds speech and key scanning The speech provides output and the ke
301. ng which frequently occurs with single accumula tor designs 2 3 Data Memory Address Unit The data memory address unit DMAU provides addressing for data memory internal RAM The block diagram of the DMAU is shown in Figure 2 6 The unit consists of a dedicated arithmetic block and eight read write registers RO through R7 Each read write register is 16 bits in size The arithmetic block is used to add subtract and compare memory address operands The register set includes four general purpose registers RO to R3 and four special purpose registers The special purpose registers are the LOOP control register R4 the INDEX register R5 the PAGE register R6 and the STACK register R7 The DMAU generates a RAM address as output The DMAU functions completely in parallel with the computational unit which helps the C6xx maintain a high computational throughput MSP50C6xx Architecture 2 11 Data Memory Address Unit Figure 2 6 Data Memory Address Unit Arithmetic Block RAM Address R7 STACK Register Addressing Mode Internal Databus Internal Program Bus 2 3 1 RAM Configuration The data memory block RAM is physically organized into 17 bit parallel words Within each word the extra bit bit 16 is used as a flag bit or tag for op codes in the instruction set Specifically the flag bit directs complex branch conditions associated with certain instructions The flag bit is also used by the computat
302. ngly Opcode mes 0000 0000000000000 pep pea ara dma16 for direct or offset16 long relative see section 4 13 MOV Ar acr nox A SELBE ee dma16 for direct or offset16 long relative see section 4 13 MOV aci An ca ee MOV Ar immi6L nex A ERR ERN EHE TN RR EI EHPHENEA EBENE imm16 a I a wav wR miei vora pIBII bere Pi EEC e x CRUS tse Dl EA ER CHEN ER EH EN CERES mov Ani LPH nextal 1 1Po o neta an jo 1 i oo fa a mov svAri linextal F1 1 i o o neta an 1 o o Jo Jo a o Mov PH anit neta 1 i o o nea an o irpo foja o MOV Ant An LnextA 1 1 oo nexra an ojo toj o o fa I A Mov MR anien 1 1Po o nea an Jof fofofa po MOV acta Rx ENER RERNE U LL dma16 for direct or offset16 long relative see section 4 13 EEE tet eee pms EBBBEBERBBRBRI BIS plu ue imm16 4 116 Individual Instruction Descriptions instructions Pie fi v4 is 12 vo o 7 o 5 o fa 2 t o mov RxR5 Jr sgsis pe 1 1 foo fo me Jo fo mov svimma Jti ro 1 o 1 fo fofofolo mm MOV SY adrsja pi fol fofofofof______ as x dma16 for direct or offset16 long relative see section 4 13 MOV PI ad PPP ON CO EC E 3 dma16 for direct or offset16 long relative see section 4 13 El mune OPLO Eeee as El dma16 for direct or offset16 long relative see section 4 13 MOV APA ad Pope t fol
303. nsion Ist created by the assembler REF symbol symbol Equivalent to EXTERNAL directive label RESB expression This directive is used to reserve the number of bytes indicated by expression starting at the current RAM address Label is given the value of the current RAM address Code Development Tools 5 15 C Compiler 5 5 C Compiler 5 5 1 5 16 label RESW expression This directive is used to reserve the number of words indicated by expression starting at the current RAM address label is given the value of the current RAM address If the current RAM address is not EVEN the assembler increments it by 1 before allocating the desired amount Note that RAM locations are accessed by their BYTE address in MSP50C6xx assembly language i e word 1 is at address 2 etc RORG expression Marks the start of a RELATIVE segment code i e a segment that can be relocated by the linker Expression is an arbitrary number but it must be present or an assembly error will occur STRING text string Equivalent to the TEXT directive but the text is terminated by a 0 automatically done by the assembler TEXT text string Equivalent to the BYTE directive but the data is a text string enclosed in double quotes UNLIST The lines following this directive are not included in the listing file extension Foreword st created by the assembler The C compiler generates an assembly language file of the same name wi
304. nt or A for predecrement Accumulator pointers can be stored or loaded from memory using various addressing modes Limited arithmetic operations can be performed on accumulator pointers m o E E APO AP3 Not used Points to An n val b0 b4 4 2 10 Indirect Register RO R7 Indirect registers RO R7 are 16 bit registers that are used in various addressing modes or as general purpose registers RO R1 R2 and R3 can be usedsolely as general purpose registers These registers can also be used as indirect registers with relative addressing The R4 or LOOP register is used with instructions BEGLOOP and ENDLOOP to define a hardware controlled loop If R4 is loaded with a value n 0 lt n lt 32767 the BEGLOOP and ENDLOOP block will be executed n 2times The loop stops when R4 becomes negative The R5 or INDEX register is used with indirect addressing and relative addres sing modes of certain instructions The R6 or PAGE register is used with page relative addressing and relative flag addressing The R7 or STACK register holds the pointer to the stack It can be used as a general purpose register as long as no CALL RET instructions are used before restoring it with its old value However this register can only be used as ageneral purpose register when maskable interrupts are disabled The old Assembly Language Instructions 4 5 System Registers value of the STACK register should be stored before use and restored af
305. ny license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used Tl s publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright O 2001 Texas Instruments Incorporated About This Manual Preface Read This First This user s guide gives information for the MSP50C6xx mixed signal proces sor This information includes a functional overview a detailed architectural description device peripheral functional description assembly language instruction listing code development tools applications customer informa tion and electrical characteristics in data sheet How to Use This Manual This document contains the following chapters a d d a a a d a Notational Conventions Chapter 1 Introduction to the MSP50C6xx Chapter 2 MSP50C6xx Architecture Chapter 3 Peripheral Functions Chapter 4 Assembly Language Instructions Chapter 5 Code Development Tools Chapter 6 Applications Chapter 7 Customer Information Appendix A Additional Information This document uses the following conventions a Program listings program ex
306. o a 200 ms period Go to sleep do an IDLE and wake up when the clock has veached full speed and is stable BERS RED deed de RI we olede BE Ae IE HE FE TENG IE EI BE IE dese EE DE IE AE IEE IE x orae s ok Ie IEE debe xe xoc e if CRO FLAG mov a0 CROENABLE enable crystal oscillator else Use BIST to determine P or C part PI BOB 5 00 IN A0 0x2F On uninitialized P parts port 0x2F is zero andb a0 0xff only want lower 8 bits JNZ ITS A C PART ITS A P PART mov A0 RESISTORTRIM for P614 the user supplies the trim value jmp setup trim Now set up the trim in ClkSpdCtrl ITS A C PART in AO RTRIM for C614 read trim value from register BOB 5 00 setup trim anda0 0x3 only want lower 6 bits mov a0 a0 save a copy for later mov sv 10 need to shift left by 10 shltpl a0 a0 bit 1 is now bit 11 bit 0 now bit 10 or a0 RTOENABLE enable resistor trimmed oscillator anda0 IDLEBI Clear bit 10 GUM 1 10 99 6 bit trim resides in bits 15 11 and bit 9 LSB of trim value and a0 a0 0x01 look at bit 0 of trim value jz trimbitO do nothing if it is zero or a0 0x0200 else set bit 9 trimbitO endif 6 6 Initializing the MSP50C6xx orba0 0x7c set PLLM for CPU clock of 8 MHz mov save clkspdctrl a0 save the ClkSpdCtrl value for later when waking up from mid or deep sleep mov a0 TIM2REFOSC TIM2IMR disable TIMER 2 out IntGenCtrl a0
307. o titi an Je s tr ojo o A A a Shift accumulator string or data memory string pointed by ads to left nsy bits as specified by the SV register This resultis zero filled on the right and either zero filled or sign extended on the left based on the setting of the extended sign mode XM bit in the status register The upper 16 bits are latched into the PH register The lower 16 bits of the result PL are subtracted from the destination accumulator or its offset This instruction propagates the shifted bit to the next accumulator See Also SHLSPL SHLTPL SHLTPLS SHLAPL SHLAPLS Example 4 14 73 1 SHLSPLS A0 R4 R5 Shift the string pointed by the byte address stored in R4 by nsy bits to the left subtract the shifted value PL from the value in the accumulator string in AO and store the result in accumulator string AO Add R5 to R4 and store result in R4 After execution of the instruction PH is copied to the next to the last accumulator of the string Example 4 14 73 2 SHLSPLS A2 R1 Shift the string pointed by the byte address stored in R1 by nsy bits to the left subtract the shifted value PL from the value in the accumulator string in A2 and store the result in accumulator string A2 Increment R1 by 2 After execution of the instruction PH is copied to the next to the last accumulator of the string Example 4 14 73 3 SHLSPLS A1 A1 Shift the accumulator string A1 by nsy bits to the left subtract the lower 16 bits of s
308. oaded to the count down register The count down register then resumes counting again from that value For each TIMER there is an interrupt trigger event associated with the TIMER s underflow condition the point of reaching 0x0000 and then re setting again When enabled the interrupt INT1 is triggered by the underflow of TIMER1 and the interrupt INT2 is triggered by the underflow of TIMER2 INT1 and INT2 are the second and third highest priority interrupts in the C6xx Refer to Section 2 7 Interrupt Logic for a summary of the interrupt logic and to Section 2 6 3 Interrupt Vectors for a listing of the interrupt vectors Both the period and the count down registers are readable and writeable as port addressed registers 16 bit wide location 15 14 13 12 11 05 04 03 02 01 00 PRD1 registert P P P P P P P p P P P address Ox3A TIMER1 Period TIM1 registert T T T T T T T TETTE address 0x3B TIMER1 Count Down Triggers INT1 on underflow PRD2 register P P_ P P P P_ P P_ P P P address 0x3E TIMER2 Period TIM2 register I T T T T T T eT E address 0x3F TIMER2 Count Down Triggers INT2 on underflow P period register initial counter value T count down register counts from the value in P 0x0000 default state of both registers after RESET LOW t TIMER1 may be associated with the comparator function if the comparator enable bit is set Refer to Section 3 3 Comparator for details MSP50C6xx Architecture 2 31 Ti
309. oard la e e Step 8 Open EMU50C6xx software The yellow light on the scanport interface should be ON Figure 5 2 Hardware Tools Setup MSP Scanport RED Target IEEE1284 Interface LED board MSPSCANPORTI F connector oes 9 MSP50P614 i Port Cable GREEN YELLOW Target development LED LED board e O PC Parallel port 18 V DC Target board power LED DESCRIPTION Red MSPSCANPORTI F power Yellow Emulation mode programming Emul Prog Target board power 5 10 Assembler 5 4 Assembler 5 4 4 Assembler Directives Assembler directives are texts which have special meaning to the assembler Some of these directives are extremely helpful during conditional compiling debugging adding additional features to existing codes multiple hardware development code release etc Other directives are an essential part of the assembler to initialize variables with values assigning symbols to memory locations assigning origin of a program etc The assembler directives that start with a hash sign cannot have spaces before the directive The following assembler directives are recognized by the assembler Some of these assembler directives use expressions and symbols These are explained below expression can be any numeric value Addition subtraction and multiplication are allowed Examples 128 2 2 220 5 2 0x200 equates to OxAE 0x200 where 0x200 indicates data memory
310. oc kk KKK KK RK KKK KKK KK kc kk kk KR KKK KERR KKK KKK KEK KEK KKK KK zac a0 tidy up zac a0 jmp main jump to the main program Applications 6 7 TI TALKS Example Code 6 3 TI TALKS Example Code 6 8 The TI TALKS code contains the four vocoders MELP CELP ADPCM and LPC and demonstrates how to use the interrupts to scan the keys and flash the LEDs An LCD driver module is also included TI TALKS should be used as a starting point for code development Updates to the vocoders and other modules are sent out by Texas Instruments as necessary Please contact the TI speech applications group email Speak2Me list ti com for the latest version of the TI TALKS example code Getting Started Connect the MSP scan port the small grey metal box to the PC and to the speech development board Ensure that the scan port and the development board are powered on the red LED and the green LED on the scan port are both illuminated before attempting to start the code development tool Click on Start go to Programs EMUC6xx and click on MSP50C6xx Code Development icon To open a project click on Project New Project and select the desired project file e g CA6144PROJECTSWI TALKS60ATTIGOOBJ RPJ Note that this is an example for TI TALKS code version 604 The file extension for the project file is RPJ Click on Project Build to assemble and link the constituent files of the project Then click Debug Eprom Programming a
311. ock ok Word w win ner ci laos P wovs writes O mesas aseado ta wow ioana O teves Ties ta os ian ere Tues 06 wow Jaime m 2 we 2 wos fans LE LE p wovs ma f mae a wow jatiwwt ea Pte 13 t Certain restriction applies to the use of this instruction when interrupts are occuring on the background See Section 4 8 for more detail Execution dest src PC PC w Flags Affected dest is An OF SF ZF CF are set accordingly dest is aars XSF XZF are set accordingly src is adrs TAG bit is set accordingly Opcode postions _fre fis fs fis fiz fs fro fo Lot Jods fa stati fo MOVS Ar ac o opio I D EC E ads dma16 for direct or offset16 long relative see section 4 13 El MOVE ada AE oppe COIN E ECO Er El dma16 for direct or offset16 long relative see section 4 13 MOVE ad An opLE O Ie El dma16 for direct or offset16 long relative see section 4 13 CNN ooo ao ae mos ena i EEES Ee 00 00 100 00 00 0005 01 mov swap popa trop p opo j po MOVS Ar PH EREBERERENERENB NN ERERENERERERESEY fwovs anan bp p pb p 0010000 01000553 moswi 01010 01101010 0700 010000 010005 02 mow a bri elo D E T9 To To Er To To fafa 4 126 Individual Instruction Descriptions Description Copy value of srcstring to deststring Premodification of accumulator pointers is allowed with some operand types
312. of the data memory loca SHLAPLS An adrs tion in adrs are placed into a 32 bit result Zeros fill the right and either zeros or sign extended ones fill the left in XSGM mode Add the lower 16 bits to the accumulator and latch the upper 16 bits in PH ALU status is modified MULSPL An aars Multiply the MR register by the contents of adrs and subtract MULSPLS An adrs the lower 16 bits of the product from the accumulator Latch the upper 16 bits into the PH register ALU status is modified 4 4 2 Class 2 Instructions Accumulator and Constant Reference 4 28 These instructions provide the capability to reference short 8 bits or long 16 bits or ng 2 16 bit string constants stored in program memory and to execute arithmetic and logical operations between accumulator contents and these constants Since the MSP50P614 MSP50C614 is a Harvard type processor these instructions are necessary and distinct from the general class of memory reference instructions Subclass 2a listed belows include references between accumulator and short 8 bit constants This class has the advantage of requiring only 1 instruction word to code and 1 instruction cycle to execute Thus is particularly useful for control variables such as loop counts indexes etc The short constants also provide full capability for byte operations in a single instruction word Subclass 2b references accumulator and long constants from program memory 16 bits for non
313. ol Register The upper four bits in the IntGenCtrl have independent functions Bit 12 is the enable bit for the pull up resistors on port F Setting this bit applies individual pull up resistors to each of the F port pins see Section 3 1 2 Dedicated Input Port F Bit 13 is the PDMCD bit for the pulse density modulation clock Clearing this bit yields a PDM clock rate equal to one half the frequency of the master clock i e the CPU clock rate Setting bit 13 yields a PDM rate equal to the rate of the master clock see Section 3 2 3 PDM Clock Divider Bit 14 is the ARM bit If the master clock has been suspended during sleep then the ARM bit must be set before the IDLE instruction in order to allow a programmable interrupt to wake the MSP50C6xx Refer to Section 2 11 Reduced Power Modes for more information Finally the top most bit in the IntGenCtrl is the comparator enable bit Setting bit 15 enables the comparator and all of its associated functions Some of the MSP50C6xx s conditions interrupts and timers behave differently depending on whether the comparator is enabled or disabled by this bit Refer to Section 3 3 Comparator for a full description Peripheral Functions 3 19 Hardware Initialization States 3 5 Hardware Initialization States 3 20 The RESET pin is configured at all times as an external interrupt It provides for a hardware initialization of the MSP50C6xx When the RESET pin is held low the device ass
314. on do something here HELSE do other things here HENDIF HIFDEF symbol Start of a conditional assembly structure If the symbol has been defined either with a DEFINE directive or an EQU directive then the lines following this directive are assembled until a ELSE or a ENDIF directive are encountered If symbol has not been defined then all input lines are skipped until a ELSE or a ENDIF directive is encountered If a ELSE directive is encountered first all lines following it are assembled until a HENDIF directive is found HIFNDEF Start of a conditional assembly structure If symbol has NOT been defined then the lines following this directive are assembled untila ELSE or a ENDIF directive is encountered If symbol has been defined either with a DEFINE directive or an EQU directive then all input lines are skipped until a ELSE or a ENDIF directive are encountered If a ELSE directive is encountered first all lines following it are assembled until a ENDIF directive is found Code Development Tools 5 13 Assembler 5 14 Example IFDEF symbol do something here HELSE do other things here HENDIF IFNDEF symbol do something here ELSE do other things here ENDIF START_FT This directive is created by the C compiler when it outputs assembly code to a file It marks the beginning of the function table used to track function calls and C variables in the emulator Users should NEVER use t
315. on in the circular buffer Thus RO will increment by R5 after the first multiply This will become more clear after examining the next ex ample code The third detail is that the filter coefficients take up only N RAM locations but the circular buffer takes up N 1 RAM locations Below is an example of the FIR or COR execution inside a DAC interrupt ser vice routine FIR Filtering routine N 3 rovm reset overflow mode mov R5 2 N circular buffer length 3 words mov R1 coeffs R1 points to first of N filter coefficients mov MR R1 must increment R1 mov RO startOfBuff RO points to start of circular buffer mov APO 0 set up room for the mov STR O 32 bit output sample ACO and AC1 Zacs AO STR should be 1 for COR CORK instructions mov STAT filterSTAT_tag load STAT with last filter tag status rpt N 2 fiw AO RO Do one sample gt 32 bit result mov filtersTAT_tag STAT save STAT with last filter tag status RO now points to the last oldest sample movs ySampleOut A0 FIR outputs bits 0 15 in ACO 16 32 in ACTI Special Filter Instructions mov A0 nextSample Replace last sample with newest sample mov R0 A0 and update the start of the mov startOfBuff RO0 circular buffer to here RO First the overflow mode must be reset Next R5 must be loaded with the wrap around value of the circular buffer Wrap around happens automatically This tells the processor how many words to s
316. on is also confusing Why is TF1 setin the STAT even though ram1 s TAG bit is not set The answer is that this MOV instruction considers the src argument to be a word value instead of the usual byte value Thus this MOV instruction operates on ram2 rather than on ram1 Assembly Language Instructions 4 21 Instruction Classification 4 4 Instruction Classification The machine level instruction set is divided into a number of classes The classes are primarily divided according to field references associated with memory hardware registers and control fields The following descriptions give class encode bit assignments the OP code value within the class and the abbreviated field descriptions Some ofthe following symbols will be used repeatedly throughout this chapter as shown in Table 4 10 for additional information see section 4 13 Table 4 10 Symbols and Explanation Symbol Explanation Invert the bit of the source Used with flag addressing only adrs n The contents of the effective data memory address referred to by the addressing mode syntax If n is specified n bits are involved If unspecified data is 16 bits See Table 4 4 cc Condition code mnemonic used with conditional branch calls and test flag bit instructions Curly braces indicate this field is not optional flagadrs Flag addressing syntax as shown in Table 4 7 A Select offset accumulator as the destination accumulator if thi
317. ond block begins at location m x 512 and ends inclusively at Ox7FFF the end of the ROM The first block is protected from reads and writes by programming a block protection bit and the second block is protected from reads and writes by programming a global protection bit The two block system is designed in such a way that a secondary developer is prevented from changing the partition address between blocks Once the block protection has been engaged then the only security option available to the secondary developer is engaging the global protection MSP50C6xx Architecture 2 19 Memory Organization RAM and ROM oS _ Co __ o 4 Note Instructions with References Care must be taken when employing instructions that have either long string constant references or look up table references These instructions will execute properly only ifthe address of the instruction and the address of the data reference are within the same block a eo e The protection modes are implemented on the C6xx as follows Within the ROM is a dedicated storage for the block protection word address Ox7FFE The block protection word is divided into two 6 bit fields and two single bit fields The remainder of the 17 bit word is broken into three single bit fields which are reserved for future use Block Protection Word address Ox7FFE 17 bit wide location WRITE only 16 15 14 13 12 11 10 09 08 07 06 0
318. ondition fields and the second word contains the destination address The condition field can specify the true Not 0 or false Not 1 condition of 22 different status conditions The status bits that es tablish the conditions are latched and remain unchanged until another instruc tion that affects them is executed In addition to call a macro call instruction is included This instruction is similar to an unconditional call instruction When executed it pushes the PC 1 value to the STACK and loads a paged vector 7F loaded in the upper 8 bits of PC and an 8 bit vector number loaded into the lower 8 bits of the PC This makes the macro call a single word instruction that take 2 instruction cycles to execute This instruction is useful for referencing frequently used subroutines A normal RET instruction is used to return to the main program from macro calls Auxiliary register R7 STACK is used as the program stack pointer and is automatically incremented on calls and macro calls It is automatically decremented on returns Interrupts are vectored in the same way as macro calls The stack pointer is incremented when interrupts fire and decremented when an IRET is executed One side effect of the program stack s operation is that it is not permissible to return to a RET instruction Either the compiler inserts a NOP between such occurrences or the programmer must avoid this sequence Assembly Language Instructions 4 39 Instruction Classifica
319. ons Memory Reference Class 5 instructions provide transfer to and from data memory and all registers except accumulators and Rx which are included in classes 1 and 4 The registers referenced for both read and write operations are the multiplier register MR the product high register PH the shift value register SV the status register STAT the top of stack TOS the string register STR and the four accumulator pointer registers APO to AP3 The data pointer register DP is read only since its value is established by lookup table instructions The RPT n repeat instruction is write only since repeated instructions cannot be interrupted IRET and RET instructions are read only operations for popping the stack and are included in this class because the stack is memory mapped Also included in this class are four flag instructions that modify flag memory and two instructions that multiply memory by MR storing the results in the PH register Table 4 26 Class 5 Instruction Encoding MEA E E EE EA ER EN REC EC EI EX E EE EMEN EEE EN CAEN NEN GENE lass 5 EIU EE ETE ERE E BERN EN Table 4 27 Class 5 Instruction Description Mnemonic Description MOV aars SV Store SV in the data memory location referred by addressing mode Cees MOV aadrs PH Store the PH in the data memory location referred by addressing mode 0 1 MOV aars STAT Store the status STAT register contents to the data memory location referred by addres
320. ons The two bit field serves as a reference to the accumulator pointer which in turn stores the address of the actual 16 bit accumulator Some MOV instructions store the contents of the APn directly to memory or load from memory to the APn register Other instructions can add or load 5 bit constants to the current APn register contents A full description of the C6xx instruction set is given in Chapter 4 Assembly Language Instructions Figure 2 5 Overview of the Accumulators Accumulator Block 32 16 bit registers AC 0 AC 31 Accumulator Block Pointers 4 5 bit registers AP 0 AP 3 The accumulator block pointers may assume values in one of two forms 1 DIRECT REFERENCE AC Register 2 INDIRECT REFERENCE 0 15 points to 0 15 0 15 OFFSET pointsto 16 31 15 31 OFFSET points to 0 15 AP registers are served by a 5 bit processor for sequencing addresses or repetitive operations Selection between the 4 AP s is made in the 2 bit An field in all accumulator referenced instructions 2 2 2 8 String Operations The AP registers are served by a 5 bit processor that provides efficient sequencing of accumulator addresses The design automates repetitive operations like long data strings or repeated operations on a list of data When operating on a multiword data string the address is copied from the AP register to fetch the least significant word of the string This copy is then consecut
321. ontents of the location referred by ad dressing mode adrsj Transfer status is modified 0 MOV PH aars Load Product High PH register with content of data memory location value referred by addressing mode aars Transfer is status modified MOV TOS adrs Load top of stack TOS register with content of data memory location referred by addressing mode aars MOV STR adrs g Load String STR register with content of data memory location referred by addressing mode adrs Only the lower 8 bits are loaded Transfer status modified MOV APn adrs Load lower 5 bits with content of data memory location referred by addressing mode aars to accumulator pointer AP register n Transfer status is modified 16 bit value MOV MR aars Load Multiplier MR register with content of data memory location referred by addressing mode adrs and set the multiplier signed mode UM 0 in STAT register Transfer status is modified MOVU MR adrs Load Multiplier MR register with content of data memory location referred by addressing mode aars and setthe multiplier unsigned mode UM 1 in STAT register Transfer status is modified MULR adrs Multiply MR register by content of data memory location referred by addressing mode adrs add 0x00008000 to the 32 bit product to produce a rounding on the upper 16 bits Store the upper rounded 16 bits to the PH register No status change MUL aars Multiply MR register
322. ontrol may be one of two bits depending on which oscillator reference is implemented in circuitry refer to Section 2 8 3 Clock Speed Control Register When using the resistor trimmed oscillator RTO the reference oscillator enable appears as bit 8 in the ClkSpdCtrl register When using the crystal referenced oscillator CRO the reference oscillator enable appears as bit 9 in the ClkSpdCtrl register If both bits 8 and 9 are clear then no reference oscillator is enabled Reduced Power Modes If either of bits 8 or 9 are set then the reference oscillator enable is considered set This enables the PLL circuitry to regulate to the reference frequency 32 kHz assuming the idle state clock control is clear Whichever state the reference oscillator is in before idle it remains in that state running or stopped after idle If the reference oscillator is left running during sleep however it comes at a cost to power consumption This may be a necessary cost if in your application elapsed time needs to be monitored during sleep The power consumed during sleep when the RTO oscillator is left running is greaterthan the power consumed during sleep when the CRO oscillator is left running Ifthe idle state clock control is clear then the PLL circuitry active during sleep will attempt to regulate the MC to whatever frequency is programmed in the PLL multiplier see Section 2 9 3 Clock Speed Control Register The MC con tinues to run at thi
323. oomomo 5 8 SATA SS O Da laa E E EE EE 5 11 SAC CO A A o 5 16 5 6 Implementation Details 00 cece eee eee eee 5 24 e ETiClenCy oro cacao aros conca coso oOnoa aos pones 5 37 5 8 Beware of Stack Corruption seeseeeeeeeeeeeee 5 57 5 9 Reported Bugs With Code Development Tool 5 58 5 1 Introduction 5 1 5 2 Introduction The MSP50C6xx code development tool is a system made up of a personal computer PC the EMUC6xx software an MSP scanport interface and a MSP50P614 connected to the application circuits EMUCE6xx is the software that executes on the PC and provides a user interface to the compiler assembler linker debugger and MSP50P614 programmer This software gains access to the MSP50P614 and MSP50C6xx devices through a serial interface called scanport The MSP scanport interface TI part number MSPSCANPORTI F is used to connect the scanport to an enhanced parallel port on the PC The MSP50P614 is an EPROM based device used to emulate the MSP50C6xx devices These EPROM based devices are packaged in a kit of 15 pieces TI part number SDK50P614 and are only available in limited quantities to support code development The MSP50P614 s EPROM must be programmed to debug the code in real time The MSP50C6xx code development tool is used to program the EPROM set a breakpoint and evaluate the internal registers after the breakpoint is reached This mode is called Run Internal
324. or Options The C6xx has two oscillator options available Either option may be enabled using the appropriate control bits in the clock speed control register ClkSpdCtrl The ClkSpdCtrl is described in Section 2 9 3 Clock Speed Con trol Register The first oscillator option called the resistor trimmed oscillator RTO is useful in low cost applications where accuracy is less critical This option utilizes a single external resistor to reference and stabilize the frequency of an internal oscillator The oscillator is designed to run nominally at 32 kHz Ithas alow Vpp coefficient and a low temperature coefficient refer to the data sheet The reference resistor is mounted externally across pins OSC y and OSCoyt The RTO oscillator is insensitive to variations in the lead capacitance at these pins The required value of the reference resistor is 470 kQ 1 The second oscillator option CRO for crystal referenced is a real time clock utilizing a 32 768 kHz crystal The crystal is mounted externally across pins OSCin and OSCour 2 8 2 PLL Performance 2 26 A software controlled PLL multiplies the reference frequency generated from either RTO or CRO by integer multiples This higher frequency drives the master clock which in turn drives the CPU clock The master clock MC drives the circuitry in the periphery sections ofthe C6xx The CPU Clock drives the core processor its rate determines the overall processor speed The multi pli
325. or battery powered operation Refer to data sheets for the MSP50C6xx devices The reduced power state on the C6xx is achieved by a call to the IDLE instruction The idle state is released by some interrupt event Different modes or levels of reduced power are brought about by controlling a number of different core and periphery components on the device These components are independently enabled disabled before engaging the IDLE instruction The number of subsystems left running during sleep directly impacts the MSP50C6xx Architecture 2 33 Reduced Power Modes 2 34 overall power consumption during that state The various subsystems that determine or are affected by the depth of sleep include the Processor core which is driven by the CPU clock PLL clock circuitry PLL reference oscillator C6xx periphery which is driven by the master clock TIMER1 and TIMER2 PDM pulsing O O O O O L The deepest sleep achievable on the C6xx for example is a mode where all of the previously listed subsytems are stopped In this state the device draws less than 10 uA of current and obtains the greatest power savings It may be awakened from this state using an external interrupt input port A number of control parameters determine which of the internal components are left running after the IDLE instruction In most cases the states of these controls may be mixed in any combination There are three combinations however which are primaril
326. ored JNIN2 has its conditional jump taken t COND2 may be associated instead with the comparator function if the comparator Enable bit is set Please refer to Section 3 3 Comparator for details 3 6 VO 3 1 5 Internal and External Interrupts INT3 INT4 INT6 and INT7 are external interrupts which may be triggered by events on the PD PD3 PD4 and PDs pins These interrupts are supported whether the D port pins are programmed as inputs or outputs When programmed as an output the pin effectively triggers a software interrupt INT5 is an external interrupt triggered by a falling edge event on any of the F port inputs It is triggered if all eight port F pins are held high and then one or more of these pins is taken low Only the transition from OxFFh all high to one or more pins low will trigger the INT5 event If any F port pin is continuously held low and another is toggled high to low no interrupt is detected at the toggling pin After all F port pins have been brought high again then it is possible for a new INT5 trigger to occur INTO is an internal interrupt highest priority which is triggered by an underflow condition on the DAC Timer see Section 3 2 2 DAC Control and Data Registers INT1 and INT2 are high priority internal interrupts triggered by the underflow conditions on TIMER1 and TIMER2 respectively Please refer to Section 2 8 Timer Hegisters for a full description of the TIMER controls and their un
327. orms NPRF NEW PRODUCT RELEASE FORM FOR MSP50C601 SECTION 1 OPTION SELECTION This section is to be completed by the customer and sent to TI along with the mi croprocessor code and speech data Company Division Project Name Purchase Order Management Contact Phone ___ Technical Contact Phone ___ Customer Part Number Customer Code Version and Revision a of format vv rr vv version rr revision numeric values only Package Type check one PJM 100 pin QFP Die Ck Ck ck ck ck ck ck ck ck Ck Sk ck Ck ck ck Ck ck KK KKK KK ck KKK ck kk ck kk ck kk Ck kk kk ck kk ck kk ck kk ck kk Sk kk ko ko Sk Sk ko ko k ko KK KKK SECTION 2A ASSIGNMENT OF TI PRODUCTION PART NUMBER This section is to be completed by TI TI Part Number CSM601xxxY or CSM601xxxPJM SECTION 2B PACKAGE UNIT SYMBOLIZATION This section is to be completed by the customer The first line of the symboliza tion is fixed Except EIA Logo The second and third lines are to be filled in by the customer Top Side Symbolization 100pin PJM LLLL LOT TRACE CODE 227 YMLLLLT YM DATE CODE lt optional 13 char gt T ASSY SITE lt optional 12 char gt TI EIA NO or 4 TI LOGO For 100 PJM package the customer may choose between TI EIA No 980 or the TI LOGO on the first line 2nd Line is typically the TI Part Number KKKKKKKKKKKKKKKKK
328. ot the clearest or easiest way to keep track of the time It was added as an example of C arrays Multidimensional arrays are not supported in C but the same functionality can be achieved by multiplying and adding the indices For example if an array is defined as equivalent to int a 3 4 in C Then the element at row x column y can be accessed by using index rowNum row column equivalent to value a 1 0 in C Y Root cmmd1 asm cmm1_ram irx flags irx main cmm main irx main ram irx mainasm asm vroncof2 asm rtc rpj dsp m celp celp irx celp4 obj common util obj util2 obj m general dsp var irx dsputil asm getbits asm speak asm speak irx spk ram irx m melp C Efficiency melp irx melp obj B modules general init asm io ports irx sleep asm m isr tim2 isr asm dac isr asm tim1 isr asm m lcd Icd asm Icd irx lcd ram irx B speech m celp ampm qfm days qfm ones qfm teens qfm tens qfm m melp ampm qfm days qfm ones qfm teens qfm tens qfm B ram ram h ram irx Code Development Tools 5 53 C Efficiency Descriptions of files that are also in Project 2 have been omitted lcd Directory holding files for writing to an LCD screen Icd asm Routines for writing to an LCD screen Icd irx Mnemonics used by lcd asm lcd ram irx Allocates RAM for Icd asm The only changes to the assembly are in mainasm asm and in cmm1 asm I
329. ount BEGLOOP ADD AO A0 AO add AO to AO count times ENDLOOP Initialize R4 with the loop count value minus 2 to repeat the loop for count times Execute the ADD AO AO AO instruction until R4 is negative R4 is decremented each time ENDLOOP is encountered When R4 is negative ENDLOOP becomes a NOP and execution continues with the next instruction after ENDLOOP 4 84 Individual Instruction Descriptions 4 14 8 CALL Unconditional Subroutine Call Syntax label name address eat fome L2 1 2 jo om eut T L2 Lo LC Execution R7 e R7 2 R7 TOS TOS PC 2 PC An or pma16 Flags Affected None Opcode E 9 E seqni iio o as ones es se ee a n ES emo 0 mpm pma16 I NENNEN aras aaa t The value of An is in the following table Description PC w is pushed onto the top of stack TOS and the second word operand or accumulator value is loaded into the PC Call instructions cannot immedi ately followed by RET instructions No restrictions apply if IRET is used instead of RET CALL pma16 Unconditional call to specified program memory address pma16 CALL An Call to address referenced by An See Also Ccc VCALL RET IRET Example 4 14 8 1 CALL 0x2010 Call unconditionally program memory address 0x2010 Example 4 14 8 2 CALL A0 Call unconditionally program memory address stored in accumulator AO Assembly Language Instructions 4 85 Individual Ins
330. p email Speak2Me list ti com for the latest version of the software Code Development Tools 5 7 MSP50C6xx Development Tools Guidelines 5 2 3 Documentation a MSP50C6xx Product Folders http www ti com sc docs products speechh index htm MSP50C6xx User s Guide Datasheet MSP50C614 MSP50C605 MSP50C601 MSP50C604 Applications Notes Documents that help users in developing code for MSP50C6xx devices are available SDS6000 Speech Editing Tool manual Schematics Reference designs schematics for the daughter cards Schematics of the SPEECH EVM and the EVA50C605 are also available 5 3 MSP50C6xx Code Development Tools 5 3 1 5 8 System Requirements O O O O L PC with Intel 486 or Pentium class processor Microsoft Windows 95 or Windows 98 operating system 16M Byte memory 8M Byte hard disk space Enhanced parallel port interface MSP50C6xx Development Tools Guidelines 5 3 2 Hardware Tools Setup Step 1 Plug in an appropriate personality card see the following note on the SPEECH EVM or EVA50C605 JL M M M S Note EPC50C605 developing code for MSP50C604 in master mode MSP50C601 MSP50C605 or MSP50C614 EPC50C604 developing code for a custom MSP50C604 used in slave mode PC50C604 developing host code to be used with a catalog MSP50C604 slave mode device a e Step 2 Connect a speaker see the
331. pt service routines were added This project adds speech so the DAC ISR needs to be added Timer 1 is also used for waking up from sleep routines so it was also added At the top of the file their labels were uncommented external DAC ISR external timerl isr external timer2_isr H external pd2 H external pd3 H external portF external pd4 external pd5 external init614 external _main0 At the bottom of the file their labels were commented out of the dummy interrupt routine pd2 pa3 portF pd4 pd5 DAC ISR timerl isr timer2 isr nop Code Development Tools 5 49 C Efficiency inte iret Cmm1 asm was modified to include routines for sleeping and speaking from C global _inportD global _getSecondsPassed global _sleepQuarterSec global _speakDays global _speakOnes global _speakTens global _speakTeens global _speakAMPM New C callable functions were declared global external sleep light external speak Assembly routines that will be called are declared external include speech celp days qfm include speech celp ones qfm include speech celp teens qfm include speech celp tens qfm include speech celp ampm gqfm Include statements were used to add speech files for all of the phrases that the clock will need to say _sleepQuarterSec mova0 8192 1 setup a 250ms period out TIM1 a0 load TIM1 and PRD1 mova0 TIMIIMR Call sleep_light nop ret A routine
332. rder By Title Date kk ck KK KKK ck Ck ck Ck ck KKK Ck ck ck Ck Sk KKK KKK ck kk ck kk KK KKK KKK KKK KKK Ck kk kk Sk kk KKK KK KKK KKK KKK Return to Texas Instruments Inc Attn Code Release Team P O Box 660199 M S 8718 Dallas TX 75266 0199 OR Fax to 214 480 7301 Attn Code Release Team Have Questions CALL Code Release Team 214 480 4444 OR E MAIL code rel msp sc ti com 7 22 Appendix A Additional Information This appendix contains additional information for the MSP50C6xx mixed sig nal processor Topic Page A 1 Additional Information A 1 Additional Information A 1 Additional Information For current information regarding the MSP50C6xx devices data sheets de velopment tools etc visit the TI Speech Web site http www ti com sc speech A 2
333. rds mov AO FIRK COEFFS Loads address of lookup table mov AO AO Loads first coefficient to AO and sets DE mov MR AO Load first coefficient in to MR register In the sequence of code above the DP register points to the first filter coeffi cient in program memory located at FIRK COEFFS This happens during the mov AO AO instruction In addition the DP register automatically incre ments to the next address It should be pointing to the second filter coefficient in program memory If the contents of the DP register are used somewhere else in the program a context save and restore must be performed on the DP register for each FIRK CORK instruction See the chapter 4 section called Lookup Instructions During FIRK CORK execution the MR register is loaded with the contents of the DP register the DP register increments pointing to the next filter coefficient and the multiply accumulate is performed The remaining FIRK CORK code is almost the same as the FIR COR code mov RO startOfBuff RO points to start of circular buffer mov APO 0 set up room for the mov STR 0 32 bit output sample ACO and AC1 zacs AO STR should be 1 for COR CORK instructions Assembly Language Instructions 4 65 Special Filter Instructions 4 66 mov STAT filterSTAT tag load STAT with last filter tag status rpt N 2 firk AO RO Do one sample gt 32 bit result mov filtersTAT_tag STAT save STAT with last filter tag status
334. reference instructions with no addressing modes Assembly Language Instructions 4 23 Instruction Classification Table 4 11 Instruction Classification Continued Class Sub Description Class 4 Register and memory reference Memory references that use Rx all addressing modes available Memory references with short constant fields operating on Rx Memory references with long constant fields operating on Rxin errata has not been connected ojojoj gt Memory references with R5 operating on Rx 5 General mMemory reference instructions 6 I O port and memory reference instructions A Port memory reference Port accumulator reference 7 Program control instructions A Macro call instructions Conditional and unconditional jump instructions C Conditional and unconditional call instructions 8 Logical bit instructions Logical flag instructions Test status instructions 9 Miscellaneous instructions Filter instructions Miscellaneous short constant instructions Accumulator address instructions ODO OQ a gt Other instructions 4 24 Instruction Classification Table 4 12 Classes and Opcode Definition Lom fps Ju o e Ju Te E Ts T7T8 T5 T3812 215 wen o fo cm wea an am me ow men fo 9 e o L9 lo own Jpop po joe mm me Lows ri o o resi am om I IS T a al owes 1 1 1 9 9 roa pe Ee e Lows a o prole am om Coss poo e ppp reps Jae Lowe paja papa DL CET pp ce nm x x see
335. relative also called PAGE Relative addressing selects the Page register R6 as a base value and adds a 7 bit positive offset from the operand The page register is not modified Syntax name dest src R6 offset 7 next A name R6 offset7 src next A R6 PAGE register 7 Bit positive offset Assembly Language Instructions 4 17 Instruction Syntax and Addressing Modes Example 4 3 20 MOV A3 R6 0x10 Refer to the initial processor state in Table 4 8 before execution of this instruc tion Load A3 AC29 with the contents of byte address R6 0x10 The value of R6 is unchanged Final result AC29 0x0112 Example 4 3 21 ADD A0 AO R6 0x10 A Refer to the initial processor state in Table 4 8 before execution of this instruc tion Preincrement APO After preincrement AO is AC3 and AO is AC19 Add AC3tothe contents of byte address R6 0x10 and store the resultin AC19 The value in R6 is unchanged Final result AC19 AC3 R6 0x10 OXFEED 0x01FA OxFEED 0x0112 OxFFFF 4 3 6 3 Long Relative 4 18 Long relative addressing selects one of the 8 address registers Rx as a base value and adds the value of the second word operand The base address reg ister is not modified Syntax name dest src Rx offset16 next A name Rx offset16 src next A Rx x 0 7 Memory Operand Example 4 3 22 MOV AO R1 0x0254 A Refer to the initial processor state in Table
336. reset circuit and the RESET pin and connecting the MSP scanport interface reset signal directly to the RESET pin See the reset circuit shown in Figure 1 3 Introduction Figure 5 1 10 Pin IDC Connector top view looking at the board Vpp PGMPULSE GND SCANIN SCANOUT IDC2X5M 0 35 10 PIN HEADER 3M PART 2510 6002UB A IDC2X5M RESET DEE PAD DIA 0 060 SCANCLK SYNC 0 800 N C HOLE DIA 0 038 0 1 VDD A 0 1 e PINOUT DETAILS LAYOUT DETAILS It is also recommended that all production boards provide a method for connecting the MSP50C6xx code development tool to the scanport This allows the developmenttool to facilitate any post production debugging There are several options for providing access to the scanport If the production board has enough room layout the footprint of the recommended connector and connect it to the scanport The connector could be added as need for debugging If the production board does not have enough room for the connector put test points for the scanport signals and a connector can be hand wired to these test points If the production boards use chip on board COB be sure to bond out the scanport signals It would also be helpful to layout the board so that a 1 kO resistor could be added in series with the reset circuit as described in requirement 3 for the preproduction board This resistor would not be added during production and would be shorte
337. resses Figure 4 2 Relative Flag Adaressing R6 PAGE register 6 Bit positive offset Syntax name des src Global Flag name TFn dma6 name dma6 TFn Relative Flag name TFn R6 offset6 name R6 offset6 TFn Example 4 3 24 MOV 0x02 TF2 Take the test flag 2 bit TF2 in the status register and place it into the 17th bit of the data memory location 0x02 Example 4 3 25 AND TF1 0x20 AND the test flag 1 bit TF1 in status register with the 17th bit of the data memory location 0x20 and store the result in the TF1 bit of the STAT Example 4 3 26 OR TF2 R6 0x02 OR the test flag 2 bit TF2 in status register with the 17h bit of the data memory location R6 0x02 and store the result in the TF2 bit in of the status register So if R6 0x0100 then relative flag address is 0x0102 Example 4 3 27 XOR TF1 R6 0x20 XOR the test flag 1 bit TF1 in status register with the 17th bit of the data memory location R6 0x20 and store the result in TF1 bit of the status register So if R620x0100 then relative flag address is 0x0120 Assembly Language Instructions 4 19 Instruction Syntax and Addressing Modes 4 3 8 Tag Flag Bits 4 20 The words TAG and flag may be used interchangeably in this manual The TAG bit is the 17th bit of a word of data memory There are 640 words of RAM each 17 bits wide on the C614 Therefore there are 640 TAG bits onthe C614 When an instruction of the format MOV accumula
338. rge when power is removed This make the circuit more reliable when power is removed and quickly reapplied Figure 1 3 RESET Circuit gt To Pin 1 of Optional Scanport MSP50P61 4 only Connector Vpp IN914t 5V VDD 100 ko INS IS RESET 1 kat Inside the RESET e MSP50P614 MSP50C6xx 1uF Reset 20 T o Switch To Pin 2 of optional scan port connectort Vss T If itis necessary to use the software development tools to control the MSP50P614 in an application board the 1 kQ resistor is needed to allow the development tool to over drive the RESET circuit on the application board This Diode can be omitted shorted if the application does not require use of the scanport interface See Section 7 1 regarding scan port bond out C _ MN Note This simple circuit may not be suitable for all applications For example if the power supply has an unpredictable rise time or has intermittent voltage sags the device may not initialize properly O o eee 1 8 MSP50C601 MSP50C604 and MSP50C605 1 5 MSP50C601 MSP50C604 and MSP50C605 Related products the MSP50C601 MSP50C604 and MSP50C605 use the MSP50C6xx core The MSP50C601 has a 128K byte data ROM built into the chip and 32 I O port pins The MSP50C605 has a 224K byte data ROM built into the chip and 32 I O port pins The MSP50C604 has a 64K byte data ROM built into the chip and 16 I O port pins The MSP50C601 can provide up to 24 minut
339. rmation External interrupts can be detected when transitions occur on ports Do Dz Da and Ds The interrupts associated with the D port are supported whether those pins are programmed as inputs or as outputs 3 1 2 Dedicated Input Port F Port F is an 8 bit wide input only port The data presented to the input pin can be read by referring to the appropriate bit in the F port data register address 0x28 This is done using the IN instruction with the 0x28 address as an argument The state of the F port data registers is not initialized with RESET After RESET is taken high the state of the F port data register is unknown Each of the pins at port F has a programmable pull up resistor All eight pullup resistors can be enabled by setting the enable pullup EP in the interrupt gen eral control register IntGenCtrl The address of the IntGenCtrl is 0x38 and the location of the EP bit is 12 Clearing the EP bit disables the eight pullups VO and setting the EP bit enables the eight pullups After RESET low the default setting for the EP bit is 0 F port pullups disabled Input Port F Data register address 0x28h Possible input data values Low 0 High 1 Possible output data values N A Value after RESET low Pullup resistors DISABLED When reading from the 8 bit F port data register to a 16 bit accumulator the IN instruction automatically clears the extra bits in excess of 8 The desired bits in the result will be right justified
340. rupt service changes the state of the processor To prevent interrupts from happening use the INTD instruction before the execution of the sequence and an INTE afterwards Lookup Instructions 4 9 Lookup Instructions Table lookup instructions transfer data from program memory ROM to data memory or accumulators These instructions are useful for reading permanent ROM data into the user program for manipulation For example lookup tables can store initial filter coefficients characters for an LCD display which can be read for display in the LCD screen etc There are four lookup instructions as shown in Table 4 44 Lookup instructions always read the program memory address from the second argument which is accumulator or its offset An asterisk always precedes this accumulator to indicate that this is an address Table 4 44 Lookup Instructions Instructions MOV aars An MOV An An next A MOVS adrs An MOVS An An Description Data Transfer The program memory address is stored in accumulator An Store the contents of this address in data memory location referred by addressing mode adrs The program memory address is stored in accumulator Anor its offset An Store the contents of this address in accumulator An or An The program memory string address is stored in accumulator An Store the contents of this address to the data memory string referred by the addressing mode aadrs The string l
341. s E e 15 aa peor 1 3 To 3 EE SHLAPLEAn eos o y to gt a los di duda SHLSPL An adrs o i otto tae adrs Oo raoba ES EE Instructions LORS An lAntlpmat ORS An An An O RFLAG fagadrs PRM ROM o RM i SFLAG flagadrs C SHL Anli nexta SHLAPL An adrs EN E EM SHL An next A EH EM o ES SHLSPL Ar An next A 1 SHLSPLS An adrs o EN ifofifif an J as dma16 for direct or offset16 long relative see section 4 13 SHLSPLS Ani Ani fofo an ise jo o o fa a SHLTPL An ad cA MEN o 0 DX amara tr reo or afst1 long relative see section 4131 sarpi aih ateren ER EN EN aaa SEE SE SHLTPLS An adi PotD ICC EC IO ae ES dma16 for direct or offset16 long relative see section 4 13 X Assembly Language Instructions 4 195 Instruction Set Encoding CT wmasATLAT SHAG AL ANILA SHLACS anan ENTE SHRAGS AA STAG adrs S An adrs next A UB An An SUB Anr An imm16 next A SUB Anr An PH next A SUB An An An next A SUB Ar An An next A SUB Rx imm16 SUB Rx R5 SUBB An imm8 SUBB Rx imma S eb OR An An SUBS An An adrs SUBS WARE ums AMI An Am sums Ada An sums anane VCALL vector8 XOR An adrs X imm16 next A XOR Ar gt An An next A XOR TFn flagadrs XOR TFn cc Rx
342. s bit is 1 A Can be either A or A based on the opcode or instruction A Select offset accumulator as source if this bit is 1 adrs Addressing mode bits am Rx pm See Table 4 4 An Accumulator pointed to by APn Accumulators cannot be referenced directly For example A22 is not valid since accumulators are only addressible though the accumulator pointers APO AP3 Therefore to access accumulators use AO A1 A2 and A3 This should not be confused with APn where AP is an accumulator pointer not an accumulator An Indicates the offset of the accumulator pointed to by accumulator pointer An This is also an ac cumulator not an accumulator pointer Apn Accumulator pointer APn where n 0 1 2 or 3 The difference between An and APn is that An is the accumulator pointed to by APn In both cases n ranges from 0 to 3 cc Condition code bits used with conditional branch calls and test flag bit instructions clk Clock cycles to execute the instruction dma n n bit data memory address For example dma8 means 8 bit location data memory address If n is not specified defaults to dma16 flagadrs Flag addressing bits as shown in Table 4 7 flg Test flag bit g r Global relative flag bit for flag addressing imm n n bit immediate value kO kn Constant field bits 4 22 Instruction Classification Table 4 11 Symbols and Explanation Continued Symbol Explanation next A Accumulator control bits as described in Tabl
343. s frequency even during sleep provided that the reference oscillator is enabled If the idle state clock control is set then neither the MC CPU clock nor the TIMER clocks run during sleep unless the TIMER source is linked to the reference oscillator Section 2 8 Time Registers These relationships are shown explicitly as a function of the reduced power mode in Table 2 4 Because the DAC circuitry is the single most source of power consumed on the C6xx itis important to disable the DAC entirely before engaging any IDLE instruction This is accomplished at the DAC control register address 0x34 Refer to Section 3 2 2 DAC Control and Data Registers The ARM bit is another important control to consider before engaging the reduced power mode It is recommended that the ARM bit be cleared whenever the idle state clock control is clear and set whenever the idle state clock control is set The set ARM bit causes an asynchronous response to all programmable interrupts when in the sleep state The cleared ARM bit yields the standard synchronous response at all times Affected interrupts include those tied to TIMER1 and TIMER2 as well as those tied to the inputs at Ports F D2 D3 Da and Ds The advantage to having the ARM bit set is that the device may be awakened by one of these interrupts even when the PLL clock circuitry is stopped in sleep by virtue of the idle state control The disadvantage of the asynchronous response however is
344. s is modified Load the MR register in signed mode from the data memory location in adrs In parallel add the PH register to the accumulator The string bit will string with the previous ALU status CF ZF but it will not load the string counter executes once ALU status is modified Assembly Language Instructions 4 27 Instruction Classification Table 4 15 Class 1b Instruction Description Continued EN IA MULAPL An aars Multiply the MR register by the addressing mode adrs and add MULAPLS An adrs the lower 16 bits of the product to the accumulator Latch the upper 16 bits into the PH register ALU status is modified SHLTPL An aars Shiftleftn bits SV reg The 16 bit contents of the data memory SHLTPLS An aars location in adrs are shifted and placed in accumulator string An Zeros fill from the right and either zeros or ones fill the left depending on the sign assuming XSGM mode is set Transfer the lower 16 bits to the accumulator and latch the upper 16 bits in PH ALU status is modified SHLSPL An adrs Shift left n bits SV reg The contents of the data memory SHLSPLS An adrs location in adrs are placed in a 32 bit result Zeros fill from the right and either zeros or sign extended ones fill the left if XSGM mode is set Subtract the lower 16 bits from the accumulator and latch the upper 16 bits in PH ALU status is modified SHLAPL An adrs Shift left n bits SV reg The contents
345. se 2 wri wri wri bre case 3 wri wri wri bre case 4 wri wri wri bre case 5 wri wri wri bre case 6 wri wri wri teC teC teC ak tec tec tec ak tec tec tec ak tec tec tec ak tec tec tec ak tec tec tec ak tec tec tec narac Narac Narac narac narac narac Narac Narac narac narac Narac narac narac narac narac narac narac Narac narac narac Narac ter M ter 0 ter N ter T ter U ter E ter W ter E ter D break switch pendulum case 0 writeCharacter writeCharacter rowOne for temp 0 temp lt 16 writeCharacter o temp writeCharacter Code Development Tools 5 55 C Efficiency writeCharacter break case 1 writeCharacter writeCharacter rowOne for temp 0 temp lt 17 temp writeCharacter writeCharacter o break case 2 writeCharacter writeCharacter rowOne for temp 0 temp 16 temp writeCharacter writeCharacter o writeCharacter break case 3 writeCharacter writeCharacter rowOne for temp 0 temp lt 15 temp writeCharacter writeCharacter o writeCharacter writeCharacter break rowOne setTime was also modified to place an indicator on the LCD below the val
346. sed in conjunction with the ifdef ifndef directives It is also possible to undefine a macro with the Zundefine directive With Arguments The macro name must be immediately followed by a pair of parenthesis which introduces the arguments This is completely compatible with the usual C definition Example define modulo i j i96j Every occurrence of the word modulo followed by an expression in parentheses will be replaced by i j where i is the first argument in the parenthesis and the second argument modulo a b c will thus be replaced by a b c The string following this directive is removed from the list of macros There is no warning if the string is not found in the macro list As in regular C this directive allows for the insertion of a file into the current file If the file name that follows is enclosed in lt gt the system searches the include directories for the file otherwise if it is enclosed in the current directory is searched 5 5 4 4 asm 5 5 4 5 endasm C Compiler Example include file h include lt stdio h gt The include directories are defined on the cmm_input structure passed to the compiler There is no limit to the nesting of include files All text following this directive is inserted as is in the output file and is considered as assembly language hence not compiled The insertion continues until a endasm directive is found Note that both asm and e
347. ses so this problem will not occur on masked parts LLLL L L MM Q 6 2 1 Initializing the MSP50C6xx File init asm p RRR RRR RRR KKK KK RK KEK KKK KK RK KK KK KKK KR KK KKK KKK KERR KKK KKK KEK koc kk KKK KK INIT ASM Revision 1 04 Modified from revision 1 03 if not CRO we check port 0x2F to distinguish between P and C parts Turn off TIMER 2 rather than leave it running Modified to cope with 6 bit trim value Top 5 bits go to bits 15 11 in ClkSpdCtrl LSB of trim goes to bit 9 in ClkSpdCtrl A fairly basic but compact initialization routine for the 614 This sets the 614 to run at 8 MHz 10 bit DAC at 8 kHz Geoff Martindale BP May 2000 pEE x FL Errr gr ng I KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK MELEE rrr rrr Gg GB G S Gg rrr ree be eee ea ESISTOR TRIM USERS DO NO T WRITE TO PORT G PRIOR TO READING THE RTRIM VALUE rrr g GN AER Start off by clearing all the RAM and tags and then zero very register The status register STAT must be cleared immediately upon power up HIS PRESERVES THE ZERO VALUE AT PORT 0x2F WHEN READING THE TRIM VALUE should be zero if P part should be non zero if C part 1 es ee TE EERE ET EUEER ETAC PEETS ELELU EOEEPEARE EE KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK
348. sing mode adrs 17 bits including TAG No 0 1 1 MOV aars STR Store string STR register contents to data memory location referred by addressing mode aars zero filled on upper 8 bits Transfer status is MOV aars APn Store the accumulator pointer APn register to the data memory location adrs zero filled on upper 12 bits Transfer status is modified adrs Transfer status is modified modification of status modified in adrs The upper 10 bits are zero filled Transfer status is modified MOV aars MR Store the contents of the multiplier MR register in adrs Transfer status is modified o 4 36 Reserved 0111011 MOV adrs DP Store the data pointer DP register contents to the location referred by adrs Transfer status is modified Instruction Classification Table 4 27 Class 5 Instruction Description Continued A MOV aars TOS Store the contents of the top of stack TOS register to the data memory location referred by addressing mode aars Transfer status is modified 1 STAG aars Store 1 to the 17th bit of data memory location referred by adrs Set the tag bit 1 0 RTAG aars Store 0 to the 17th bit of data memory location referred by adrs Clear the tag bit MOVT adrs TFn Store TF1 bit if n 1 TF2 bit if n 0 status bit to 17th bit of data memory location referred by addressing mode ads 1 MOV SV adrs 4 Load shift value SV register with c
349. sing the IN instruction with the address of the data register as an argument When configured as an output the data driven by the output pin can be controlled by setting or clearing the appropriate bit in the associated data register This is done using the OUT instruction with the address of the data register as an argument VO Port A Port B Port C Port D Port E Control register address OxO4ht OxOCh 0x14h 0x1Ch 0x24h Possible control values 0 High Z INPUT 12 TOTEM POLE OUTPUT Value after RESET low 0 High Z INPUT Data register address 0x20h Possible input data values Low 0 High 1 don t care on write Possible output data values O Low 1 High T Each of these I O ports is only 8 bits wide The reason for the 4 byte address spacing is so that instructions with limited addressability such as memory transfers can still access these registers Eee Note Reading the Data Register Whether configured as input or as output reading the data register reads the actual state of the pin ee The state of the control registers is initialized to 0x00 when the RESET pin is taken low This puts all of the programmable I O pins into an input state This condition is maintained after RESET is taken high and until the control regis ters are modified The state of the data registers is not initialized with RESET After RESET is taken high the state of the data registers is unknown and must be initia
350. ss registers RO R7 as a base value The index register R5 is added to the base address value in Rx The base address register is not modified Thus the effective address is Rx 4 R5 Syntax name dest src Rx R5 next A name Ro R5 src next A Instruction Syntax and Addressing Modes Rx x 0 7 Index Register R5 Example 4 3 17 AND AO R3 R5 Refer to the initial processor state in Table 4 8 before execution of this instruc tion AO is accumulator AC2 The contents of the data memory byte location pointed to by R3 R5 is ANDed with AC2 The result is stored in AC2 The val ues in R3 and R5 are unchanged Final result AC2 AC2 AND 0x01F2 0x13F0 AND 0x12AC 0x12A0 Example 4 3 18 MOV R2 R5 A2 A Refer to the initial processor state in Table 4 8 before execution of this instruc tion Preincrement AP2 After preincrement A2 is AC12 and A2 is AC28 Store AC28 in the data memory byte location R2 R5 The values in R2 and R5 are unchanged Final result 0x02A1 0x11A2 Example 4 3 19 ADD AO AO R4 R5 A Refer to the initial processor state in Table 4 8 before execution of this instruc tion Predecrement APO After predecrement AO is AC1 and A0 is AC17 Add AC1 to the contents of byte location R4 R5 and put the result in AC17 The values in R4 and R5 are unchanged Final result AC17 AC1 R4 R5 0x0007 0x0002 0x0007 0x499A 0x49A1 4 3 6 2 Short Relative Short
351. string constants and ng 2 16 bits for string constants Class 2b instructions take 2 instruction words to code The execu tion of these instructions is 2 instruction cycles when the long constant is a single word The execution is ng 2 execution cycles for ng word string Instruction Classification constants Long constants 16 bits and long string constants differ in that ref erences are made to constants in the second word of the two word instruction word References made to a single 16 bitinteger constant are immediate That is the actual constant value follows the first word opcode in memory For string constants the second word reference to the constants is immediate indirect which indicates that the second word is the address of the least significant word of the string constant This definition allows all long string constants to be located in a table and permits the reference in the machine language listing to be consistent with those of shorter constants Table 4 16 Class 2 Instruction Encoding aerea aaa mexppepipe fm me aem s OC EZ 199 IS EC E ES Table 4 17 Class 2a Instruction Description Cea pemo neci ADDB An imm8 Add an 8 bit positive constant to the accumulator and store the result in the accumulator ALU status is modified Eee MOVB An imma Load an 8 bit positive constant into accumulator ALU status is modified an 8 bit Load an 8 bit positive constant into accumulator ALU status is modif
352. t 1 PC PC 1 Flags Affected OF SF ZF CF are set accordingly Opcode Instructions re rs iners 12 11 10 o Je 7 e s a jo 2 1 o SHLAC An LAn p next 1 1 1 o o nexta An jojo o o JA a Description Premodify accumulator pointer if specified Shift source accumulator src or its offset left by one bit and store the result in the destination accumulator or its offset LSB of result is set to zero Example 4 14 67 1 SHLAC A1 A1 Shift accumulator A1 by one bit to the left Example 4 14 67 2 SHLAC Al Al A Predecrement accumulator pointer AP1 by 1 Shift the newly pointed accumulator A1 by one bit to the left store the result in accumulator A1 Assembly Language Instructions 4 163 Individual Instruction Descriptions 4 14 68 SHLACS Shift Left Accumulator String Individually Syntax iae rame ses se Clock ok wora w With RPT or crass SHLACS Jari Ari Execution dest src lt lt 1 PC PC 1 Flags Affected OF SF ZF CF are set accordingly Opcode Instructions Pro 15 14 fia 12 to o e 7 e 8 a 3 J2 t sHLacs apaid 1 11 1 foto titi an foto fo fo a a Description Shift the source accumulator string src or its offset left one bit and store the result in destination accumulator string or its offset Each accumulator is shifted individually The shifted bit is propagated through consecutive accumulators in the string
353. t fof 1 fo a a Description Shift accumulator string right one bit and store the result into An string MSB of each accumulator in the result will be set according to extended sign mode XM bit in the status register This instruction shifts each accumulator individually 1 bit to the right so shifts from one accumulator are not propagated to the next consecutive accumulator in the string See Also SHRAC SHL SHLS SHLAPL SHLAPLS SHLSPL SHLSPLS SHLTPL SHLTPLS Example 4 14 77 1 SHRACS AO AO Shift accumulator string AO 1 bit right individually Example 4 14 77 2 SHRACS Al Al Shift accumulator string A1 individually put result in accumulator string A1 Assembly Language Instructions 4 173 Individual Instruction Descriptions 4 14 78 SOVM Set Overflow Mode Syntax ime mame Tolo ok wora w With RPT ok Class som___ 3 NR joa Execution STAT OM lt 1 PC PC 1 Flags Affected None Opcode Instructions Pro Pis 14 fia 12 t to o e v oe 8 a a 2 iow tt i i it i fs Ts Fo it Js fo fs To Jofo Jo Description Sets overflow mode in status register STAT bit 2 to 1 Enable ALU saturation output DSP mode See Also ROVM Example 4 14 78 1 SOVM Set OM bit of STAT to 1 This is the mode DSP algorithms should use 4 174 Individual Instruction Descriptions 4 14 79 STAG Set Tag Syntax abel same dest Tos ok wora w win RPT ck ass STAG Table 4 4
354. t high register from accumulator A 0 or from offset accumulator A 1 and store the result into accumulator A 0 or into the offset accumulator A 1 ALU status is modified String bit causes subtract with carry status CF Add product high register to accumulator or to offset accumulator and store the result into accumulator A 0 or 1 ALU status is modified The string bit causes an add with carry status CF Transfer product high register to accumulator A 0 or offset accumulator A 1 ALU status is modified String bit will cause stringing with current ZF status bit Copy SF bit in status register to all 16 bits of the accumulator or offset accumulator On strings the accumulator address is preincremented causing the sign of the addressed accumulator to be extended into the next accumulator address Subtract offset accumulator from accumulator A 0 or subtract accumulator from offset accumulator A 1 and store the status of the result into ALU status Accumulator or offset accumulator original value remains unchanged DONE MS s Trpo ems NA efTe a t These instructions have a special 1 word string operations when string mode is selected The instructions ignore the string count executing only once but maintain the carry and comparison to zero operation of the previous arithmetic operation as if the sequence of the previous string instruction and current instruction were part of a larger string operation
355. t in R1 Example 4 14 87 3 XORS Al Al 0x100 2 XOR program memory string beginning at word address 0x0100 to accumulator string A1 put result in accumulator string A1 Example 4 14 87 4 XORS A2 A2 A2 XOR accumulator string A2 with accumulator string A2 string put result in accumulator string A2 4 186 Individual Instruction Descriptions 4 14 88 ZAC Zero Accumulator Syntax labe name aesti moa ces ok Word w With RPT ck crass zac Anf L next A Execution premodify AP if mod specified dest 0 PC PC 1 Flags Affected ZF 1 Instructions Pi 15 Pra fis 12 fio o fa 7 e js a 2 Jo zac An p nexa Lt 1 foto nea An Jofojojiji lo o a Description Zero the specified accumulator Preincrement or predecrement accumulator pointer APn if specified See Also ZACS Example 4 14 88 1 ZAC A2 Reset the content of accumulator AO to zero Example 4 14 88 2 ZAC Al A Preincrement AP1 by 1 Reset the content of new accumulator A1 to zero Assembly Language Instructions 4 187 Individual Instruction Descriptions 4 14 89 ZACS Zero Accumulator String Syntax iae rame ss Geek ok wora w With RPT ok crass p ze a a 3 ws 3 Execution dest 0 PC PC 1 Flags Affected ZF 1 Instructions Pie fas 94 13 12 11 to o jo 7 Je 8 a Pa 12 1 o zacs aj Tt Tt foto fits an fofofoJ Jofo J Aj Descr
356. ta values Possible output data values O Low 1 High Value after RESET low 0 Low The following table shows the bit locations of the port G address mapping G port Data address 0x2C 16 bit wide location read and write 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4G3 G2 Gi GO 0x0000 default state of data register after RESET low 3 1 4 Branch on D Port Instructions exist to branch conditionally depending upon the state of ports Do and D4 These conditionals are COND1 and CONDZ2 respectively The condi tionals are supported whether the Dg and D4 ports are configured as inputs or as outputs The following table lists the four possible logical states for Dg and D4 along with the software instructions affected by them Do 1 COND TRUE CIN1 has its conditional call taken CNIN1 has its conditional call ignored JIN1 has its conditional jump taken JNIN1 has its conditional jump ignored Do 20 COND FALSE CIN1 has its conditional call ignored CNIN1 has its conditional call taken JIN1 has its conditional jump ignored JNIN1 has its conditional jump taken t D421 COND2 TRUE CIN2 has its conditional call taken CNIN2 has its conditional call ignored JIN2 has its conditional jump taken JNIN2 has its conditional jump ignored t D420 COND2 FALSE CIN2 has its conditional call ignored CNIN2 has its conditional call taken JIN2 has its conditional jump ign
357. tal reference out OSCIN 48 50 Resistor crystal reference in PLL 47 49 O Phase lock loop filter DACP 7 22 O Digital to analog plus output DACM 1 Byte 1 Byte 1 Byte 1 Byte O Digital to analog minus output Initialization RESET 3 Initialization Power Signals Vss 17 50 90 100f 32 52 9 191 Ground VDD 6t 8 31 32 91 21t 23 33 34 10 Processor power t The Vss and Vpp connections service the DAC circuitry Their pins tend to sustain a higher current draw A dedicated decoupling capacitor across these pins is therefore required 5 20 8 40 Customer Information 7 5 Mechanical Information Table 7 4 Signal and Pad Descriptions for the MSP50C604 SIGNAL PIN NUMBER PAD NUMBER 1 0 DESCRIPTION Input Output Ports PCO PC7 89 82 8 1 1 0 Port C general purpose l O PDO PD7 99 92 18 11 1 0 Port D general purpose l O PEO PE7 46 39 48 41 1 0 Port E general purpose I O PFO PF7 16 9 31 24 l Port F dedicated input Pins PD4 and PD5 may be dedicated to the comparator function if the comparator enable bit is set Refer to Section 3 3 Comparator for details 1 Byte 1 Byte 1 Byte 1 Byte Scan Port Control Signals SCANIN 37 39 Scan port data input SCANOUT 33 35 Scan port data output SCANCLK 36 38 Scan port clock SYNC 35 37 Scan port synchronization TEST 34 36 l C605 test modes The scan port pins must be bonded out on any
358. te nextinstruction srcvalue 2 times Interrupts are queued during RPT instruction Queued interrupts are serviced after execution completes RPT adrs g Load data memory byte to repeat counter repeat next instruction RPT imm8 Load immediate byte to repeat counter repeat next instruction See Also BEGLOOP ENDLOOP Example 4 14 61 1 RPT 0x0100 2 MOV R1 A0 A Loads the repeat counter with value stored in word data memory location 0x0100 Only 8 bits of data from this location are used The next instruction stores content of AO to data memory address pointed by R1 Since R1 postincrements and AO preincrements in this instruction the overall effect of executing this instruction with RPT is to store accumulator contents to consecutive data memory locations See MOV instruction for detail of various syntax of MOV instruction Example 4 14 61 2 RPT 200 NOP Repeat the NOP instruction 202 times provided the next instruction is repeatable This causes 203 instruction cycle delay including 1 cycle for the RPT instruction Assembly Language Instructions 4 157 Individual Instruction Descriptions 4 14 62 RTAG Reset Tag Syntax iae rame ses Glock ok wora w With RPT ok crass mme ids Execution memory tag bit at adrs data memory location 0 PC PC 1 Flags Affected None Opcode RTAG adrs dma16 for direct or offset16 long relative see section 4 13 Description Resets tag
359. tep back when the end of the circular buffer is reached This value must be negative and equal to N words even though the buffer is N 1 words long For example suppose a four word circular buffer starts at RAM location 0x0100 and ends at 0x0106 N 3 In order to wrap around from location 0x0106 back to location 0x0100 the value 0x006 must be subtracted from 0x0106 giving 0x0100 TAGGED LOCATION Go back N words to wrap around RO must point to the current starting point of the circular buffer R1 must point to the filter coefficients The MR register must contain the first filter coefficient h 0 RO and R1 must be used this way The filtering operation will not work if the Rx registers are reversed The following are the only allowable register combinations RO points to circular buffer and R1 points to filter coefficients R2 points to circular buffer and R3 points to filter coefficients Assembly Language Instructions 4 63 Special Filter Instructions Any combination of registers different from the above will yield incorrect results with the FIR COR instruction 0x0106 0x010 Use R5 to wrap around RO 0x0100 9 After FIR COR execution The STAT register is saved in the filerSTAT tag location The output of the fil tering operation in the example is located in ACO lower word and AC1 high word This 32 bit result is stored in the SampleOut RAM location RO should be pointing to the oldest sample The oldest sample x
360. ter DAC leeeeeeeeeee 3 9 3 3 Comparators 5 5 o RETE NE iS 3 15 3 4 Interrupt General Control Register oooooocccoooo 3 18 3 5 Hardware Initialization States eee 3 20 3 1 y o 3 1 l O Device MSP50C614 MSP50C604 MSP50C605 MSP50C601 Ports Available This section discusses the I O capabilities of the MSP50C6xx family The fol lowing table shows the number and types of I O available on each device Please note that this section discusses all I O ports which are only available on the MSP50C614 device All other devices have only a subset of the I O that is available on the MSP50C614 No of General No of Dedicated No of Dedicated Purpose I O Inputs Outputs E o 3 1 1 General Purpose l O Ports 3 2 The forty configurable input output pins are organized in 5 ports A B C D and E Each port is one byte wide The pins within these ports can be individually programmed as input or output in any combination The selection is made by clearing or setting the appropriate bitin the associated control register Control A B C D or E Clearing the bit in the control register renders the pin as a high impedance input Setting the control bit renders the pin as a totem pole output When configured as an input the data presented to the input pin can be read by referring to the appropriate bit in the associated data register Data A B C D or E This is done u
361. ter The STAT should be initialized to 0000h after the processor resets The XSF and XZF flags are related to data flow to or from the internal data bus If the destination of the transfer is an accumulator then the SF ZF CF and OF flags are affected If the destination of the transfer is Rx the RCF and RZF flags are affected If the destination of the transfer is through the internal databus the XSF and XZF flags are affected The SF flag is the sign flag and itis equal to the most significant bit of an accumulator when an accumulator instruction is executed ZF is the zero flag and is set when the instruction causes the accumulator value to become zero CF is the carry flag and is set when the instruction causes a carry A carry is generated by addition subtraction multiplication multiply accumulate compare shifting and some MOV instructions that have accumulation features CF is reset if no carry Occurs after execution of an instruction OF is set when a computation causes overflow in the result It is reset if no overflow occurs during an accumulator based instruction Overflow saturation mode is set by the OM bit as explained in Section 4 6 System Registers Table 4 1 Status Register STAT Bit 0 10 11 12 13 14 15 16 Name XM UM OM FM IM Reserved XZF XSF RCF RZF OF SF ZF CF TF1 TF2 TAG Function Sign extended mode bit This bit is one if sign extension mode is ena
362. ter use This register must point to the beginning of the stack in the RESET initialization routine before any CALL instruction or maskable interrupts can be used CALL instructions increment R7 by 2 RET instructions decrement R7 by 2 The stack in MSP50P614 MSP50C614 is positively incremented 4 2 11 String Register STR The string register STR holds the length of the string used by all string instruc tions MOV instructions are used to load this register to define the length of a string The value in this register is not altered after the execution of a string instruction A value of zero in this register defines a string length of 2 Thus a numerical value ng in the STR register defines a string length of ng 2 The maximum string length is 32 Therefore 0 lt ng lt 30 corresponds to actual string lengths from 2 to 32 4 2 12 Status Register STAT 4 6 The status register STAT provides the storage of various single bit mode conditions and condition bits As shown in Table 4 1 mode bits reside in the first 5 LSBs of the status register and can be independently set or reset with specific instructions See section 4 6 for detail about these computational modes Condition bits and flags are used for conditional branches calls and flag instructions Flags and status condition bits are stored in the upper 10 bits of the 17 bit status register MOV instructions provide the means for context saves and restores of the status regis
363. th extension opt It also generates a file with extension y1b where global variable initialization is taken care of if the routine main was encountered in the current file A file with extension ext is also generated to take care of global and external declarations that will be used by the assembler These two files are included in the opt file generated by the C compiler Note that all symbols defined in C source code are changed before being written to assembly language an underscore character is put in front of the first character of each symbol Also note that local labels created by the C compiler are built using the current source file name followed by an ordinal number Consequently to avoid problems at link time due to symbols bearing the same name never use symbol names starting with an underscore in assembly language files It is imperative to use file names that are different for C files extension cmm and assembly language files extension asm C is a high level language to be used with the MSP50C6xx microprocessors Although it looks a lot like C it has some limitations restrictions which will be highlighted throughout the remainder of this chapter This language is compiled into MSP50C6xx assembly language 5 5 2 Variable Types C Compiler Type Name Mnemonic Range Size in Bytes Example Integer int 32768 32767 2 int i j Character char 0 255 1 char c d Array of integer int Not Appl
364. that it can render irregularities in the timing of response to these same inputs MSP50C6xx Architecture 2 35 Reduced Power Modes SSS S SS a a 600 00 aaa ee Note Idle State Clock Control Bit If the idle state clock control bit is set and the ARM bitis clear the only event that can wake the C6xx after an IDLE instruction is a hardware RESET low to high When at sleep the device will not respond to the input ports nor to the internal timers Table 2 3 Programmable Bits Needed to Control Reduced Power Modes deeper sleep relatively less power Label for Control Bit Control Bit Idle state clock control bit 10 CIkSpdCtrl register OX3D Enable reference oscillator bit 09 CRO or bit 08 RTO CIkSpdCtrl register OX3D ARM bit 14 IntGenCtrl register 0x38 Enable PDM pulsing bit 02 DAC Control register 0x34 IDLE instruction executes the mode PLL multiplier bits 07 through 00 Programmed value is 0 255 CIkSpdCtrl register OX3D 2 36 Reduced Power Modes Table 2 4 Status of Circuitry When in Reduced Power Modes Refer to Table 2 3 deeper sleep relatively less power Determined by Controls xe clock PLL clock circuitry running stopped stopped Master clock MC status Component LIGHT DEEP MC rate 131 kHz 34 MHz Synchrony of external interrupts C E Synchronous aes PDM pulsing stopped stopped stopped TIMER1 or TIMER
365. ther by the user of the device or by some other external circuitry referto the MSP50C6xx data sheet SPSS023 Electrical Specifications sec tion When the RESET pin is held low the MSP50C6xx is considered reset and has the following internal states RESET low I O ports are be placed in a high impedance Input condition Ports A B C D and E All outputs on Port Gi is are set to low 0x0000 Device is placed in a deep sleep state PLL circuitry master clock CPU clock and TIMERs are stopped Current draw from the Vpp is less than 10 uA in this condition Interrupt flag register IFR at address 0x39 is not automatically cleared Internal RAM is not automatically cleared COUCE LU Hardware Initialization States _ A A A AAAAAAUAAUOUS O AAALAAXC Note Internal RAM State after Reset The RESET low will not change the state ofthe internal RAM assuming there is no interruption in power This applies also to the interrupt flag register The same applies to the states of the accumulators in the computational unit When RESET is brought back high again many ofthe programmable controls and registers are left in their default states RESET high just after low No reference oscillator is enabled PLL runs at its minimum achievable rate Master clock runs at a very slow frequency less than 100 kHz PLL multiplier is set to 0x00 renders slowest speed for M
366. these functions is xfer const which transfers values from the program ROM to the RAM Also constants MUST BE GLOBAL Do not pass a constant as an argument The common C types float struct union and long are not implemented Note that long is a subset of string of integer All RAM allocations in the assembler are global This results in the following implications for C variables Only the file containing the main routine can contain global variable definitions Y Global variables referenced in other files must have been declared as ex ternal keyword extern at the beginning of the file Lj A function referenced in a file but not defined in that same file must be introduced with a function prototype in the file where it is referenced no need for the extern keyword Code Development Tools 5 17 C Compiler 5 5 4 C Directives 5 5 4 1 define 5 5 4 2 Zundefine 5 5 4 3 include 5 18 C has a limited number of directives and some additional directives not found in ANSI C compilers The following directives are recognized by the compiler This directive is used to introduce 2 types of macros in typical C fashion Without Arguments defines a replacement string for a given string Example define PI 3 1415926535 Every occurrence of the token Pl will henceforth be replaced with the string 3 1415926535 If there is no replacement string the given string is deemed defined this can be u
367. tic comparison and logic ALU OUTPUTS THE ACCUMULATOR BLOCK Accumulator Register OFFSET Accumulator Register 16 x 16 bit registers 16 x 16 bit registers ACO AC1 AC2 AC3 ACA AC5 AC6 AC7 AC8 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AC31 t For multiply accumulate operations 2 2 2 2 Accumwulator Pointer Block There are four 5 bit registers which are used to store pointers to members of the accumulator block The accumulator pointers APO AP1 AP2 AP3 are used in two modes 1 as a direct reference to one of 32 or 2 as an indirect reference The indirect reference includes a direct reference to one of 16 and an offset optional which increments the reference by 16 AC N 16 For example ACO has its offset register located at AC16 AC1 has an offset register located at AC17 and so on The block is circular address 31 when incremented results in address 0 The offsets of AC16 through AC31 therefore are ACO through AC15 respectively see Figure 2 5 Indirect referencing by the AP pointers is supported by most of the C6xx s accumulator referenced instructions MSP50C6xx Architecture 2 9 Computation Unit When writing an accumulator referenced instruction therefore the working accumulator address is stored in one of APO to AP3 The C6xx instruction set provides a two bit field for all accumulator referenced instructi
368. tion Table 4 31 Class 7 Instruction Encoding and Description E ELS ee RONECR ER ICE RARE ER ESERES ES ES poe TEE vector8 MEMES EA ARA AA a TE amp an o fo jo P r o x an a A EA cart san i o Jo fo x a Tox cc names Description cc ccname Notcc name Z Conditional on ZF 1 S Conditional on SF 1 N N wo eerte o ES Ww TT ws CE we EI o emsewoe o me foran Pua ooroo on nzr oaan R Led Ee ES far un NEU vg ed HEN xe EE NN Z S C A G E R R R C NC A NA D pgorag EGER ER CHER ERICH EB EE C IEA ER ER parag pocia ae EE E A ES puada CAEN EAS EN EJESERES EA EIER ICE EEN EXER KS ET CS pacad OO Ea ERES ES E monca CAAA AACA EA EN EEN lel fefe Instruction Classification Table 4 31 Class 7 Instruction Encoding and Description Continuea cames names ccnames Description cc cc name Not cc name Not cc name name KA E A a LL deem Er EIS E hee T EME EA E e To Joonitonsonxe CS Free LOS ns oae rper e e 286 oas PSP wem KE KE E A E esses 1 KE KE E CA TEE tesis rp ERST esie ETHER esses EA EN ENE EN EN ER EN Em 4 4 8 Class 8 Instructions Logic and Bit This class of instructions provides a flexible and efficient means to make complex logical decisions Instead of making a sequence of single bit d
369. tion Input from I O port Words can be input to memory from one of 16 port addresses or one of 48 port addresses The port4 address is multiplied by 4 to get the actual port address See Also INS OUT OUTS Example 4 14 21 1 IN RO 0x0c Input data from port address OxOc 4 0x30 to data memory location pointed by RO Example 4 14 21 2 IN A2 0x3d Input data from port address Ox3d to accumulator A2 Assembly Language Instructions 4 105 Individual Instruction Descriptions 4 14 22 INS Input From Port Into String Syntax Liner meme om scl Sook oh Word w AE Ts euge oe o l1 ow fe Execution dest content of port6 PC PC 1 Flags Affected destis An OF SE ZF CF are set accordingly Opcode pae area ae peers n mswues effete fa ome E ES Description Input string from same port port6 to accumulator string Strings can be input to accumulators from one of 64 port addresses In this instruction port6 is sampled ns 2 times The first sample is stored in the lowest order accumula tor of the string and the last sample is stored in the highest order accumulator of the string See Also IN OUT OUTS Example 4 14 22 1 INS A2 0 Input string starting from port O to accumulator string 4 106 Individual Instruction Descriptions 4 14 23 INTD Interrupt Disable Syntax Taba rama o w WPT ax ene EN EA A A O E A E Execution STAT IM 0 IM is STAT bit 4 PC PC 1 Flags Af
370. tion ZFz0 or SFz1 reserved TF2 NTF2 Conditional on TF2 1 Not condition TF2 0 TAG NTAG Conditional on TAG 1 Not condition TAG 0 Conditional on IN1 1 status Not condition IN1 0 IN1 IN2 NIN2 Conditional on IN2 1 status Not condition IN2 0 reserved Conditional on XZF 1 Not condition XZF 0 Conditional on XSF 1 Not condition XSF 0 Conditional on XSF 0 and XZF 0 Not condition XSFz0 or XZFzO reserved ojo ojojojo ojoljojo Oim o jom ojo 0 0 0 1 1 ojojojo PO ojo a 2 2loi o oloij2 2 2 2 2 m i J I zz Aajo O O O O O fO O O O O O O O a oOjo jojojojo OJIN x lt O ojojojo O OJO O O O O JO O OJO O azl lojol oloOl olol l lo0OloOl l lojol l o ol lolo a Assembly Language Instructions 4 111 Individual Instruction Descriptions cc names Description ee name kidtec name True condition Not true condition ENEE reserved EBEEESESES reserved EBEZEZEHEN reserved reserved Description PC is replaced with second word operand if condition is true or unconditional If test condition is false a NOP is executed Instruction Ic pma amoa ComWensimpongF i OO LNCpmat Amod ConMWendjumpontF 0 JE prar amoa _ Conditonaljumponequal INE prato Rmod ConWondjumponmtema LN parer mod GondWonaiumponpo
371. tion gets the lower byte of the 5th word of RAM and puts it in AO In addition the TAG bit of the STAT register is set Ifthe MOVB instruction addressed 0x000A instead of 0x000B the STAT register would still be updated with the same tag flag bit the 17h bit of the 5th word of RAM This means that odd byte locations in RAM RAMoqg have the same tag flag as the preceding byte location RAMggg 1 For exam ple the 7th word of RAM is made up of two bytes 0x000E and 0x000F These two byte locations share the same tag flag bit MSP50P614 MSP50C614 Computational Modes Example 4 5 10 MOV STR 0 SFLAG 0x00032 MOVS AO 0x0031 2 RFLAG 0x00032 MOVS AO 0x0031 2 Refer to Figure 4 4 for this example This example is to illustrate the effect of the tag flag bit when used with a string instruction The string register STR is loaded with O string length of 2 The second instruction sets the flag bit to 1 at flag address 0x0032 The next instruction reads the word string at word memory location 0x0031 into AO and also sets the TAG bit of STAT to 1 corre sponding to the last memory location of the string which is word address 0x0032 in this case The next two instructions verify this by setting the flag to zero and reading the memory string again 4 6 MSP50P614 MSP50C614 Computational Modes MSP50P614 MSP50C614 has the following computational modes which are the first 4 bits of the status register Sign extension mode
372. tions Class 8a 4 12 Initial Processor State for the Examples Before Execution of Instruction 4 13 Indirect Addressing Syntax occccccccccccccco n 4 15 Symbols and Explanation e esmi teniti nE i a ta ees 4 22 Instruction Classification s sssaaa aaaea aea 4 23 Classes and Opcode Definition ooocccooccconnroo eh 4 25 Class 1 Instruction Encoding 0 0c cece eee tenet e 4 26 Class 1a Instruction Description lliississssssseseee III 4 26 Class 1b Instruction Description 006 c cece RII 4 27 Class 2 Instruction Encoding 00 cece eee cece eee eet eee eee 4 29 Class 2a Instruction Description 0 0 c eect eens 4 29 Class 2b Instruction Description 0 0 eens 4 30 Class 3 Instruction Encoding 00 cee eens 4 31 Class 3 Instruction Description 006 eee eee 4 31 Class 4a Instruction Encoding 00sec eect cece tenet teens 4 34 Class 4a Instruction Description 0000 tenet eee 4 35 Class 4b Instruction Description 00 0 c cece eee eee eens 4 35 Class 4c Instruction Description 000 eee eee eee 4 35 Class 4d Instruction Description liiisssssssssssse III 4 35 Class 5 Instruction Encoding 00 00 cece eee eh 4 36 Class 5 Instruction Description 000 cece eect eee 4 36 4 28 4 29 4 30 4 31 4 32 4 33 4 34 4 35 4 36 4 37 4 38 4 39 4 40
373. tions 4 185 Individual Instruction Descriptions 4 14 87 XORS Logical XOR String Syntax label name dest src src1 Clock clk With RPT clk xoRrs An aars Table 4 46 Table 4 46 xons ani Arti amara ms Wiz An An Execution dest dest XOR src for two operands dest src XOR src for three operands PC PC w Flags Affected dest is An OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode COTT 195 001001001010 01010 01018 01 XORS An ai SEES ES IN EN E EH DU DR DC arara or areon or ofeert ong rave eee sexton 8 allas ps jaj or aleja Aa ao Description Bitwise XOR of src string and deststring Result is stored in deststring If three operands are specified then logical XOR srcstring and src string store result in dest string XORS An adrs XOR data memory string to An string XORS Ar An pma16 XOR program memory string to An string store result in An string XORS An An An XOR An string to An string store result in An string See Also XOR XORB AND ANDS OR ORS ORB NOTAC NOTACS Example 4 14 87 1 XORS AO AO R2 XOR data memory string beginning at address in R2 to accumulator string AQ put result in accumulator string AO Example 4 14 87 2 XORS A3 A3 R1 R5 XOR data memory string beginning at address in R1 to accumulator string A3 put result in accumulator string A3 Add value in R5 to the value in R1 and store resul
374. tor A 0 or 1 ALU status is modified Place the 1 s complement of the source accumulator A 0 or 1 into the destination accumulator A 0 or 1 ALU status is modified Look up a value in program memory addressed by accumulator A 0 or 1 Place the lookup value into the accumulator A 0 or 1 The lookup address is post incremented in the DP register ALU status is modified based on the lookup value ZAC An next A Zero accumulator A 0 or 1 ALU status is modified ZACS An SUB Ar An An next A SUB Ar An An next A SUBS An An An SUBS An An An 1 1 ADD An An An next A ADDS An An An SHLAC An An next A SHLACS An An MOV An Arn next A MOVS An An Subtract offset accumulator from accumulator A 0 or subtract accumulator from offset accumulator A 1 Store the result in accumulator A 0 or 1 ALU status is modified Add accumulator to offset accumulator and store result to accumulator A 0 or 1 ALU status is modified Shift accumulator left 1 bit and store the result into accumulator A 0 or offset accumulator A 1 The LSB is set to zero and the MSB is stored in a carryout status bit ALU status is modified Copy accumulator A 0 or 1 to accumulator A 0 or 1 ALU status is modified t These instructions have a special 1 word string operations when string mode is selected The instructions ignore the string count e
375. tor RAM is performed the STAT register is affected by various properties of this trans fer The TAG bit of the RAM location is copied into the TAG bit of the STAT reg ister during such transfers The TAG bit can be modified using several instructions STAG RTAG SFLAG RFLAG There are subtle differences between these instructions that the user must understand before using them The first difference between the XTAG and xFLAG instructions is the addressing STAG 0x0000 sets the TAG bit of RAM word zero RTAG 0x0002 clears the TAG bit of RAM word one STAG 0x0002 2 sets the TAG bit of RAM word two STAG and RTAG use RAM byte addresses to specify which TAG to set or clear This immediately causes confusion since there are 1280 bytes and only 640 TAGs What happens when an odd byte is used to set a tag with STAG STAG 0x0001 sets the TAG bit of RAM word zero STAG 0x0003 sets the TAG bit of RAM word one STAG 0x0005 2 sets the TAG bit of RAM word five All word boundaries in RAM start at even numbers RAMeven If an odd byte RAMeven 1 is used to set a TAG then the TAG for RAMgyeg is set Thus STAG 0x0000 STAG 0x0001 are functionally equivalent As a sharp contrast the SFLAG and RFLAG instructions use RAM word ad dresses to specify which TAG to set or clear SFLAG 0x0000 sets the TAG bit of RAM word zero SFLAG 0x0001 sets the TAG bit of RAM word one Another difference between the xTAG an
376. tor string A2 Increment R1 by 2 PH holds the upper 16 bits of the shift Example 4 14 70 3 SHLAPLS A1 A1 Shift the accumulator string A1 by nsy bits to the left add the shifted value PL to the accumulator and store the result in accumulator string A1 After execution PH contains the upper 16 bits of the 32 bit shift 4 166 Individual Instruction Descriptions 4 14 71 SHLS Shift Left Accumulator String to Product Syntax iaa rame dest Tos ok wora w win RPT ck ass sms jan nws 1 ms a Execution PH PL src SV PC PC 1 Flags Affected OF SF ZF CF are set accordingly Opcode Instructions re rs 14 J 13 12 11 o o jo v e s a jo 2 1 o sus Arf Tt tt Tt Foto st Ao sts i fs Js Jo ae o Description Shift accumulator string value left nsy bits as specified by the SV register into a ns 2 x 16 bit result The result is zero filled or sign extended on the left based on the setting of the extended sign mode XM bit in the status register The upper 16 bits are latched into the PH register Accumulator content is not changed The lower 16 bit value is discarded SHLS instruction can be used with RPT instructions but the string length used will be ng 2 See Also SHLS Example 4 14 71 1 SHLS AO Shift accumulator string AO to the left Accumulator content is not changed PH contains the upper 16 bits of the shifted result Assembly
377. tract Accumulataor String Syntax abel name dest se sel Glock ok Word w With RPT ok ass P suas annan O Texas Table dae ta sus aiios nea 2 NR aw sus art Anar suss JAn iAn An susst arts Arr PH t This instruction ignores the string count executing only once but maintains the CF and ZF status of the previous multi ply or shift operation as if the sequence was a single string This instruction should immediately follow one of the fol lowing class 1b instructions MOVAPH MULAPL MULSPL SHLTPL SHLSPL and SHLAPL An interrupt can occur betweenone ofthese instructions andthis instruction An interrupt may cause an incorrect result Also single stepping is not allowed for this instruction An in this instruction should be the same as An in one of the listed class 1b instruc tion Offsets are allowed See Section 4 8 for detail Execution premodify AP if mod specified dest dest src for two operands dest src src for three operands PC PC w Flags Affected dest is An OF SF ZF CF are set accordingly src1 is adrs TAG bit is set accordingly Opcode Instructions Pie fis ra a 12 10 o Js v e S a s pa n fo sus any ant ojojoj la 3 1 as x dma16 for direct or offset16 long relative see section 4 13 sus aiios ET I D Papi a DP DEDE DE TE ESTER suas aa Ib T E DE b p sus aia ele E D p b bp e al ws warum Tato o TEL To DE Eo Do Eo
378. truction Descriptions _ _ 2 Note You can not RET to a RET For example the following code can cause prob lems CALL my sub RE To eliminate any problem a NOP or other code should be inserted between the CALL and the RET For example CALL my sub NOP RE ef 4 86 Individual Instruction Descriptions 4 14 9 Ccc Conditional Subroutine Call Syntax Taba rame ases Geeks ci Word w Win RPT ok ee Fe Jonas 12 l2 1 9 17 t Cannot immediately follow a CALL instruction with a return instruction If true If Not true label CZ pma16 label CNZ pma16 label CS pma16 label CNS pma16 label CC pma16 label CNC pma16 label CG pma16 label CNG pma16 label CE pma16 label CNE pma16 label CA pma16 label CNA pma16 label CB pma16 label CNB pma16 label CO pma16 label CNO pma16 label CRC pma16 label CRNC pma16 label CRE pma16 label CRNE pma16 label CL pma16 label CNL pma16 label CTF1 pma16 label CNTF1 pma16 label CTF2 pma16 label CNTF2 pma16 label CTAG pma16 label CNTAG pma16 label CIN1 pma16 label CNIN1 pma16 label CIN2 pma16 label CNIN2 pma16 label CXZ pma16 label CXNZ pma16 label CXS pma16 label CXNS pma16 label CXG pma16 label CXNG pma16 label CRA pma16 label CRNA pma16 Execution IF cc true R7 TOS TOS PC 2 PC pma16 R7 R7 2
379. ts Interrupts must be explicitly disabled at least one instruction before the class 1b instruction This special sequence is protected inside a BEGLOOP ENDLOOP construct In addition single stepping is not allowed for this instruction An in this instruc tion should be the same as Anin one of the listed class 1b instruction Offsets are allowed See Section 4 8 for more LN ES lien ES detail Execution dest string src string src7 string PC PC w Flags Affected dest is An OF SF ZF CF are set accordingly src1 is adrs TAG is set accordingly Opcode COCO 910 91010010 0 0110 El 205808 O OO E CAE IA aie dma16 for direct or offset16 long relative see section 4 13 pma16 rae AA CR EOS E E RC OR REOR ESCUDO ECT EO 3I E EE acosan An Po i i foto a ofi rfo f fo a Description Add value of src string to the value of src string and store resulting string in dest String length minus two should be stored in STR before execution See Also ADD ADDB SUB SUBB SUBS Example 4 14 3 1 ADDS AO AO R2 Add data memory string beginning at address in R2 to accumulator string AO put result in accumulator string AO Example 4 14 3 2 ADDS AO A0 0x1400 Add program memory string beginning at address 0x1400 to accumulator string AO put result in accumulator string AO 4 78 Individual Instruction Descriptions Example 4 14 3 3 ADDS Al Al Al Add accumulator string A1 to accumulator string
380. ue that is being set updateTime was modified to call showTime after the time is updated 5 56 Beware of Stack Corruption 5 8 Beware of Stack Corruption MSP50C614 MSP50P614 stack pointed by R7 register can easily get corrupted if care is not taken Notice the following table read code SUBB R7 4 OV AO R7 ADD A0 address OV AO AO ADD AO R7 OV AO AO RET This code will work perfectly well if no interrupts happen before SUBB and MOV instruction If interrupts do happen between SUBB and MOV instructions the parameter in the stack is corrupted by the return address pushed by the hardware This problem may not be easily observed in the system level But once it happens it is very difficult to debug Use the following method to modify stack pointer instead OV AO R7 2 2 ADD AO address OV AO AO ADD AO R7 2 1 OV AO AO RET This method will not have the stack corruption problem since the MOV instruc tion performs the entire operation either before or after an interrupt Code Development Tools 5 57 Reported Bugs With Code Development Tool 5 9 Reported Bugs With Code Development Tool 5 58 The following are reported bugs for code development tool version 2 39 Breakpoint Placement of hardware breakpoints is important for reliable operation Pipeline latency and sleep modes affect the scan logic and prevent hardware breakpoints from working in the following cases P
381. ulate or shift operation The lower 16 bits of the result are stored in the PL register The PH register can be loaded directly by MOV instructions Special move accumulate instructions MOVAPH MOVAPHS MOVSPH MOVSPHS also use the PH register 4 2 7 Product Low Register PL This register holds the lower 16 bits of the 32 bit result of a multiplication multiply accumulate or shift operation The upper 16 bits of the result are stored in the PH register There are no instructions that load or save the PL register directly but multiply accumulate instructions allow the contents of the PL register to be added subtracted or transferred to the accumulator 4 2 8 Accumulators ACO AC31 4 4 There are 32 accumulators on the MSP50P614 MSP50C614 Each is 16 bits wide The first sixteen accumulators ACO AC15 have offset accumulators AC16 AC31 and vice versa At any one time four accumulators can be selected through accumulator pointer registers APO AP3 see section 4 2 9 Some instructions can specify offset accumulators which are the accumulators pointed to by APn 16 or APn 16 whichever is in the range 0 to 31 The offset accumulators are indicated by an offset bit A in some instructions When this bit is 0 An points to the accumulator directly If it is 1 then An points to the offset for some instructions this scheme changes The selected accumulator pointer register should contain the index to the corresponding accumulator
382. ultiply String and Subtract PL From Accumulator Syntax labe rame sess crock ok Word w With RPT ck crass p qwusms ates tebeo meras 10 mues wi Art Execution PH PL MR src dest dest PL PC PC 1 Flags Affected OF SF ZF CF are set accordingly src is adrs TAG bit is set accordingly Opcode instructions Pro Pis fra fis 12 fu tro o Js v e 8 a 3 2 1 fo MULSPLS An adr Pp as x dma16 for direct or offset16 long relative see section 4 13 wusPLSAn Ad gt gt trs rjo ojs t Ao j o sjopog opo a a Description Perform multiplication of multiply register MR and value of src The 16 MSBs of the ng 3 x 16 bit product are stored in the product high PH register The 16 LSBs of the product contained in product low PL register subtracted from dest string MULSPLS aars Multiply MR by data memory string subtract PL from An MULSPLS Ar An Multiply MR by An string subtract PL from An See Also MULSPL MULTPL MULTPLS MULAPL MULAPLS Example 4 14 44 1 MULSPLS A0 R3 Multiply MR with the contents of R3 subtract PL from accumulator string AO and store result in accumulator string AO Increment R3 by 2 Example 4 14 44 2 MULSPLS A2 A2 Multiply MR register to accumulator string A2 subtract PL from accumulator string A2 and store result to accumulator string A2 Assembly Language Instructions 4 139 Individual Instructio
383. umeric values only Package Type check one PJM 100 pin QFP Die Ck Ck ck ck ck ck ck ck ck Ck Sk ck Ck ck ck Ck ck KK KKK KK ck KKK ck kk ck kk ck kk Ck kk kk ck kk ck kk ck kk ck kk Sk kk ko ko Sk Sk ko ko k ko KK KKK SECTION 2A ASSIGNMENT OF TI PRODUCTION PART NUMBER This section is to be completed by TI TI Part Number CSM605xxxY or CSM605xxxPJM SECTION 2B PACKAGE UNIT SYMBOLIZATION This section is to be completed by the customer The first line of the symboliza tion is fixed Except EIA Logo The second and third lines are to be filled in by the customer Top Side Symbolization 100pin PJM LLLL LOT TRACE CODE 227 YMLLLLT YM DATE CODE lt optional 13 char gt T ASSY SITE lt optional 12 char gt TI EIA NO or 4 TI LOGO For 100 PJM package the customer may choose between TI EIA No 980 or the TI LOGO on the first line 2nd Line is typically the TI Part Number KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK SECTION 3 AUTHORIZATION TO GENERATE MASKS PROTOTYPES AND RISK UNITS This section is to be completed by the customer and sent to TI after the following criteria have been met 1 The customer has verified that the TI computer generated data matches the original data Customer Information 7 19 New Product Release Forms NPRF 2 The customer approves of the symbolization format in Sect
384. umes a deep sleep state and various control registers are initialized After the RESET pin is taken high the Program Counter is loaded with the value stored in the RESET Interrupt Vector Eo 7 Note Internal Power Reset Function There is no power on reset function internal to the MSP50C6xx After the ini tial power up or after an interruption in power the RESET pin must be cycled low to high The application circuitry must therefore provide a mechanism for accomplishing this during a power up transition or after a power fluctua tion LLLL L The application circuits shown in Section 6 1 Application Circuits illustrate one implementation of a reset on power up circuit The circuit consists of an RC network 100 kQ 1 uF When powering Vpp from 0 V the circuit provides some delay on the RESET pin s low to high transition This delay helps to en sure that the MSP50C6xx initialization occurs after the power supply has had time to stabilize between Vpp MIN and Vpp MAX Vpp MIN and Vpp MAX are the minimum and maximum supply voltages as rated for the device The circuit shown however may not shield the RESET pin from every kind of rapid fluc tuation in the power supply At any time that the power supply falls below Vpp MIN even momentarily then the RESET pin must be held low and then high once again ei
385. umulator SHLAPL An aars Shift data memory word left add PL to An SHLAPL Ar An next A Shift An left add PL to An See Also SHLAPLS SHLTPL SHLTPLS SHLSPL SHLSPLS Example 4 14 69 1 SHLAPL A0 R4 R5 Shift the word pointed by the byte address stored in R4 by nsy bits to the left add the shifted value PL with accumulator AQ store the result in accumulator AO Add R5 to R4 and store result in R4 PH holds the upper 16 bits of the shift Example 4 14 69 2 SHLAPL A2 R1 Shift the word pointed by the byte address stored in R1 by nsy bits to the left add the shifted value PL with the accumulator A2 and store the result in accumulator A2 Increment R1 by 2 PH holds the upper 16 bits of the shift Example 4 14 69 3 SHLAPL Al Al A Preincrement accumulator pointer AP1 Shift the accumulator A1 by ngv bits to the left add the shifted value PL to the accumulator and store the result in accumulator A1 After execution PH contains the upper 16 bits of the 32 bit shift Assembly Language Instructions 4 165 Individual Instruction Descriptions 4 14 70 SHLAPLS Shift Left String With Accumulate Syntax labe rame dest se Clock ok Word w with Rer c Cass p Semas aneas moeras meras 10 saris rt Art Execution PH PL src lt lt SV dest dest PL PC PC 1 Flags Affected OF SF ZF CF are set accordingly src is adrs TAG bit is set
386. umulator RO is loaded with 0x0002 The fourth instruction loads the value of the word string at the RAM address in RO 0x0002 RO autoincrements by 2 after each fetch and stores them into four consecutive accumulators starting from AC2 The result is AC2 0x5678 AC3 Ox9ABC AC4 OxDEFO AC5 0x1122 There were 4 word fetches and the new value of RO 0x000A Example 4 5 8 SFLAG 0x0003 MOV AO 0x0003 2 RFLAG 0x0003 MOV AO 0x0003 2 Refer to Figure 4 4 for this example This example illustrates the use of the TAG and flag bits Notice that SFLAG uses a word address 0x0003 while the MOV instruction uses a byte address 0x0003 2 The first instruction sets the flag tag bit at flag address 0x0003 Flag address 0x0003 represents the 17th bit of the 3rd word or 6th byte of RAM In the second instruction this flag bit is placed in the TAG status bit of the STAT and the value in RAM location 0x0003 2 is placed in AO The third instruction resets the flag tag to O at the same flag address The fourth instruction reads the same word memory loca tion and writes the TAG bit of STAT which is now 0 Note SFLAG 0x0003 could have been replaced by STAG 0x0003 2 and RFLAG 0x0003 could have been replaced by RTAG 0x0003 2 Example 4 5 9 SFLAG 0x0005 MOVB A0 0x000b RFLAG 0x0005 MOVB A0 0x000b Refer to Figure 4 4 for this example The SFLAG instruction sets the 17th bit tag flag of the 5th word of RAM The MOVB instruc
387. umulator string is a group of consecutive accumulators spanning from An to the next N consecutive accumulators N is the length ofthe string The STR register should be loaded with N 2 to define a string length N A value of zero in the STR register defines a string length of 2 string length 1 means the instruction is not in string mode Arithmetic string instructions treat the string as an N word arithmetic value The result is also an arithmetic value of the same length Conditionals are set as they would be set without string mode Comparing two strings is equivalent to comparing each bit of the string The accumulator status is modified representing the outcome of the entire operation Examine the following examples Table 4 43 Initial Processor State for String Instructions Registers register value APO 22 ACO AC4 AC8 AC12 OXAAAA AC16 AC20 AP1 21 0x15 AP2 11 0x0B AP3 29 0x1D ACI AC2 AC3 AC5 AC6 AC7 AC9 AC10 AC11 OXAAAA AC13 OxAAAA AC14 OXAAAA AC15 OxAAAA AC17 AC18 AC19 AC21 0x1223 AC22 OxFBCA AC23 0x233E data memory address data 0x0200 0x12AC 0x0201 OxEE34 0x0202 0x9086 0x0203 OxCDE5 program memory adaress data 0x1400 0x0123 0x1404 OXFEDC 0x1401 2 0x4567 0x1402 0x89AB 0x1403 OXCDEF 0x1405 0xBA98 0x1404 0x7654 0x1405 0x3210 Example 4 8 1 MOV STR 4 2 string length 2 MOVS A0 0x1400 Refer
388. us is modified Logical AND the contents of the data memory location in adrs and the accumulator Result s stored in accumulator s ALU status is modified Exclusive OR the contents of the data memory location in adrs and the accumulator Result s stored in accumulator s ALU status is modified Load the contents of the data memory location in adrs and to the lower 8 bits of the accumulator Zero fill the upper byte in the accumulator ALU status is modified Store the lower 8 bits of accumulator to the data memory location in adrs The data byte is automatically routed to either the lower byte or upper byte in the 16 bit memory word based on the LSB of the address Transfer status is modified Store the arithmetic status of the contents of adrs subtracted from accumulator into the ALU status bits The accumulator is not modified Look up the value stored in program memory addressed by the accumulator and store in the data memory location in adrs Transfer status is modified Multiply the MR register by the contents of adrs and transfer the lower 16 bits of the result to the accumulator Latch the upper 16 bits into the PH register ALU status is modified Load the MR register in signed mode from the data memory location in adrs In parallel subtract the PH register from the accumulator The string bit will string with the previous ALU status CF ZF but it will not load the string counter executes once ALU statu
389. utational Modes 4 49 4 7 Hardware Loop Instructions eese 4 53 4 8XsStng Instructions 3 5 ooo 4 55 AOR ookupiinstr ctions 07575 9 e os 4 57 4 10 Input Output Instructions 0 ae Ee a 4 59 4 11 Special Filter Instructions sees 4 59 4 12 Conditionals a tiro 4 69 4 13 kegend c eee 4 70 4 14 Individual Instruction Descriptions eese 4 74 A i5uInstructioniSetEncoding PTT 4 189 4 16 Instruction Set Summary eeeeeeeeeeee 4 198 Introduction 4 1 Introduction In this chapter each MSP50P614 MSP50C614 class of instructions is explained in detail with examples and restrictions Most instructions can individually address bits bytes words or strings of words or bytes Usable program memory is 30K by 17 bit wide and the entire 17 bits are used for instruction set encoding The execution of programs can only be executed from internal program memory Usable program memory starts from location 800h The data memory is 640 by 17 bits of static RAM 16 bits of which are an arithmetic value The 17th bit is used for flags or tags 4 2 System Registers A functional description of each system register is described below 4 2 1 Multiplier Register MR The multiplier uses this 16 bit register to multiply with the multiplicand MOV instructions are used to load the MR register The multiplicand is usually the operand of the
390. vanced integrated speech synthesizer for high quality sound Operates up to 12 32 MHz performs up to 12 32 MIPS Very low power operation ideal for hand held devices Low voltage operation sustainable by three batteries Reduced power stand by modes less than 10 uA in deep sleep mode Supports high quality synthesis algorithms such as MELP CELP LPC and ADPCM Contains 32K words onboard ROM 2K words reserved Up to 2 36 Mbits of internal data ROM for speech storage 640 words RAM Up to 64 input output pins Direct speaker driver 32 Q One bit comparator with edge detection interrupt service Resistor trimmed oscillator or 32 768 kHz crystal reference oscillator Serial scan port for in circuit emulation and diagnostics The MSP50C6xx is sold in die form or QFP package An emulator device MSP50P614 is sold in a ceramic package for development The MSP50P614 devices operate from 4 0 Vdc to 6 0 Vdc and the MSP50C6xx devices operate from 3 0 Vdc to 5 2 Vdc 1 2 Applications Due to its low cost low power Applications consumption and high programmability the MSP50C6xx is suitable for a wide variety of applications incorporating flexible I O and high quality speech Y Consumer Toys and Games Appliances Talking Clocks Navigation Aids _j Industrial Warning Systems Controls Y Telecom Answering Machines Voice Mail Systems J Education Electronic Learning Aids Talking Dictionaries Language Translators Talking
391. was added to sleep for a quarter second using Timer 1 to wake up The program loads the period into the timer 1 period register sets the wake up mask in a0 and calls sleep light which is in sleep asm _speakDays back up important registers mov csave r5 r5 protect r5 mov csave r3 r3 protect r3 mov a0 r7 2 synthesis table offset add a0 days table mova0 a0 ZAC A0 CALL SPEAK restore important registers movr3 csave r3 restore r3 movr5 csave r5 restore r5 ret days table table for table lookup 5 50 DATA MON 0 DATA UE 1 DATA WED 2 DATA HU 3 DATA FRI 4 DATA SAT 5 DATA SUN 6 cmm func main goasm C Efficiency C callable speech routines like the above for speaking days were added An integer phrase number is passed on the stack The routines get this value from the stack and do a table lookup to get the address of the correct phrase The address is loaded into a0 and a0 is cleared to indicate that the speech data is in internal ROM Then speak which is located in speak asm is called The final assembly file that was modified was mainasm asm The only change was setting up Timer 1 and enabling the Timer 1 interrupt The configuration of Timer 1 is similar to the configuration of Timer 2 The high level program main cmm was then modified to utilize the new functionality run any assembly stuff that needs to be run while 1
392. x 4 triggers INT5 bit Fx 0 input PF low bit Dy 1 PD high R W J falling edge f rising edge TPD inverting and PDs positive comparator inputs if CE 1 in lO 0x38 PD4 triggers INT6 PDs triggers INT7 PDoT triggers INT3 PD3 triggers INT4 bit Ey 1 gt PE high bit C 1 PD as output bit Fy 1 input PF high bit it Gx 0 PGx low output only m T4 To Resistor trim bits rw s fo tofo ot o p p p o o bp o 5 pisse RC bs qoe propo oos os pp pe E E ESTOS po je foo od ppp e A Ep TA S sign bit 10 bit DAC O overflow bit 19 bit DAC bit Gx 2 1 V 1 D data bit 8 bit DAC PGx high output only T4 TQ are valid dont care see P1 P0 in lO 0x34 external input states 0x00 external input states 0x00 external input states 0x00 external input states 0x00 external input states 0x00 external input states 0x00 all O outputs 0x0000 ABUWILUNG les uogoni su suoinonujsu ebenbue7 Ajquiassy L0c p MSP50C614 MSP50P614 IO Port Description WSOP TANTO Por Deseo news ua vee Tow Pe Tw Te e e ete Te T3 T4 8 2 2 o Tm Eo Jaw fe E E 0 a wwe ET mem 009 peas 3x Style DAC Disable DAC 8 bit 5x Style DAC Enable DAC 9 bits 10 bits EN General F port Pullup Timer Function Interrupt enable bits 1 enable O disable Control Arm bit Comparator Timer1 source DAC Timer interrupt Timer2 source Timer 1 interrupt
393. x and Bits 2 0 cece eee eee eee 4 73 Names TO list A Ferd Pap tne IO are hae AS 4 88 String FUNCIONS ecuador ia 5 22 Signal and Pad Descriptions for the MSP50C614 o o oococcccccccc nee 7 3 Signal and Pad Descriptions for the MSP50C605 o ococcccccocccc nee 7 4 Signal and Pad Descriptions for the MSP50C601 oocccccccccccc lees 7 5 Signal and Pad Descriptions for the MSP50C604 o oooocccccccccc eens 7 6 Contents xiii xiv Chapter 1 Introduction to the MSP50C6xx The MSP50C6xx is a low cost mixed signal controller that combines a speech synthesizer general purpose input output I O onboard ROM and direct speaker drive in a single package The computational unit utilizes a powerful new DSP which gives the MSP50C6xx unprecedented speed and computational flexibility compared with previous devices of its type The MSP50C6xx supports a variety of speech and audio coding algorithms providing a range of options with respect to speech duration and sound quality Topic Page 1 1 Features of the MSP50C6xx 2 cece eee eee eee eee 1 2 1 2 Applications o n eere tI 1 3 1 3 Development Device MSP50P614 oooooccccocccccccnc 1 4 1 4 Functional Description for the MSP50C614 1 5 1 5 MSP50C601 MSP50C604 and MSP50C605 1 9 Features of the MSP50C6xx 1 1 Features of the MSP50C6xx L LE LIB DO LB 0 E Bm ees i E d da L Ad
394. xecuting only once but maintain the carry and comparison to zero operation of the previous arithmetic operation as if the sequence of the previous string instruction and this instruction execution was a part of a larger string operation Assembly Language Instructions 4 31 Instruction Classification Table 4 20 Class 3 Instruction Description Continuea PE O E XOR An An An next A XORS An An An OR An An An next A ORS An An An AND An An An next A ANDS An An An SHRAC An An next A SHRACS An An SUB Ar An PH next A SUBS An An PH t ADD An An PH next A ADDS An An PH MOV An PH next A MOVS An PH T EXTSGN An next A EXTSGNS An T CMP An An next A CMP An An next A CMPS An An CMPS An An s Logically exclusive OR accumulator with offset accumulator and store the results in accumulator A 0 or 1 ALU status is modified Logically OR accumulator with offset accumulator and store results into accumulator A 0 or 1 ALU status is modified Logically AND accumulator with offset accumulator and store result s into accumulator A 0 or 1 ALU status is modified Shift accumulator or offset accumulator right 1 bit and store result in accumulator A 0 or 1 MSB will be set to zero or be set equal to the sign bit XSGM dependent ALU status is modified Subtract produc
395. y scanning is used for input Adding speech synthesis increases the number of files in the project dramatically but the C is still similar The main changes that relate to C are addition of a routine in cmm asm to read buttons on Port D and addition of a routine to speak from C The third project adds LCD support It offers the same speaking abilities as the third project but uses an LCD screen for additional output It also demonstrates the use of arrays in C Example 5 1 First Project The project is of limited use because there is no way to read the time or change the time without using a scanport It does provide a good example of a C project that contains a few simple files A minimum implementation of the real time clock contains the following files Code Development Tools 5 39 C Efficiency 5 40 Y Root cmm1 asm cmm1_ram irx flags irx main cmm main irx main ram irx mainasm asm vroncof2 asm rtc rpj modules m general init asm io ports irx m isr tim2 isr asm Ly ram cmm1 asm cmm1_ram asm flags asm main cmm main irx main ram irx vroncof2 asm rtc rpj modules general initasm io ports irx isr tim2 isr asm ram ram h ram irx m ram h m ram irx Assembly to support C function calls Allocates RAM for use in cmm1 asm Flags used in init asm and for speech routines C program Mnemonics for switches and ports used in main cmm Allocates RAM for
396. y useful The three modes light mid and deep sleep are executed through the independent control of two bits 1 the idle state clock control and 2 the reference oscillator enable The other pertinent controls simply enhance the performance of the modes dictated by these two Table 2 3 gives a listing of all of the controls which should be maintained by the programmer before engaging the IDLE instruction In some cases it will be impossible to wake from sleep unless certain controls are set appropriately before going to sleep In those cases only the hardware RESET low to high will bring the device back into its normal operating state The top row in Table 2 3 lists the first of the two primary controls namely the idle state clock control The idle state clock control determines the status of the master clock MC during sleep Setting the idle state control causes the CPU clock the PLL clock circuitry and the MC to stop after the next IDLE instruction Clearing the idle state control causes only the CPU clock to stop after IDLE The PLL clock circuitry governs the MC and determines its rate Whenever the PLL circuitry is suspended therefore the MC stops The idle state clock control is accessed at bit 10 in the CIkSpdCtrl register refer to Section 2 8 3 Clock Speed Control Register for more information The reference oscillator enable is the other control which selects between the three reduced power modes listed in Table 2 3 This c

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