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Tektronix 73A-270 Sprinkler User Manual

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1. Four LEDs for each channel provide visual indication of the transmit status resolution status and external trigger mode A readback mode provides the transm status and data list command accept status of either channel Finally the serial pattern output connections to the VXIbus TTLTRG lines allow checking the programming and output intervals by any counter resource in the same VXIbus card cage In A A A a A 73A 270 DESCRIPTION Time Duration Value One of 1600 values programmable on each channel with a value of to 999 999 This value 1s multiplied by A glossary of VXIbus terms is provided in the resolution programmed for the Appendix C In addition the following channel to determine the time a terms specific to the 73A 270 Module are particular output level active or defined inactive programmed in any one of the 1600 locations is present on the Bipolar Outputs pulse pattern output n output for each channel that provides the same pulse pattern output as the basic pulse pattern TTL output but at a programmable high and low level up to 17 4V for both the active and inactive states Breakpoint A programmed breakpoint temporarily holds the output at the last programmed level until a trigger instructs the module to continue Non Retriggerable Mode A programmed mode on the 73A 270 that ignores additional triggers while a channel is actually transmitting until transmission is completed or a breakpoint is ex
2. The format for each command is specified in the detailed command description section of this manual Commands may be strung together indefinitely Carriage return lt CR gt line feed lt LF gt or other separation characters such as slashes periods commas colons or semi colons are permitted but not required between commands Leaving out lt CR gt lt LF gt will usually significantly reduce a system controller s execution time However adding a lt CR gt lt LF gt following commands improves readability e Summary An overview of the commands in the order they typically would be programmed is as follows S Select selects the channel A or B for which all following commands except the T and X commands will apply Resolution specifies one of four time resolution ranges for the selected channel Address specifies any of the 1 600 addresses in the selected channel for loading data into memory List specifies the time duration and polarity active or inactive of the output at the selected address for the selected channel It can also Specify the selected address as a breakpoint or last address The programmed address will increment automatically at the end of each LIST command Count specifies the number of times the entire data list will be transmitted before stopping for the selected channel Mode specifies either the Triggerable or the Non retriggerable Mode for the selected ch
3. Verify that the pulse pattern stops 7 Verify channel B operation with the VXIbus TTL Trigger Lines with the following steps a Move the oscilloscope CH 2 coaxial cable from TTL OUT A to TTL OUT B b Reset the 73A 270 for channel B to generate a 500 kHz pulse pattern triggered by an external trigger from TTLITRGO and for channel A to provide the trigger pulse on TTLTRGO IBWRT 80X08T IBWRT OS3ROAOM51L54L1C IBWRT 1S1ROA1M11L14L0C IBWRT 1B c Verify a 500 kHz signal and then stop the pulse patter IBWRT Q Verify that the pulse pattern stopped d Check the remaining TTLTRG1 through TTLTRG7 lines by sending the commands in table A 7 and verifying the 500 kHz pulse pattern Table A 7 VXlbus TTL Trigger Line Verification Ch B triggered by Ch A TTLTRG Line Change Setup amp Restart Pattern TTLTRG1 IBWRT 81X18T IBWRT 1B Verify a 500 kHz pulse pattern TTLTRG2 IBWRT Q82X28T IBWRT 1B 70 73A 270 Arbitrary Pulse Pattern Generator Module Appendix D Performance Verification Table A 7 Cont VXIbus TTL Trigger Line Verification Ch B triggered by Ch A TTLTRG Line Change Setup amp Restart Pattern TTLTRG3 IBWRT Q83X38T IBWRT 1B TTLTRG4 IBWRT Q84X48T IBWRT 1B TTLTRG5 IBWRT Q85X58T IBWRT 1B TTLTRG6 IBWRT Q86X68T IBWRT 1B TTLTRG IBWRT Q87X78T IBWRT 1B e With the following commands disable both channels from the TTLTRGX lines and restart the channel
4. Verify 5 kHz The fourth parameter is numeric one followed by alphabetic O d Momentarily disconnect the SMB connector from the VX4790A and check that the 5 kHz pulse pattern is no longer present on TTL OUT A e Using the oscilloscope probe verify a 10 MHz clock signal on pin 17 of S1 4th pin up from bottom left 3 Verify the Transmission In Progress signal with the following steps a Turn the mainframe power off and remove the 73A 270 Return the SLOW EXTERNAL CLOCK switch to OFF and verify that the FAST EXTERNAL switch is in the C1 position Reinstall the 73 A 270 and turn on the mainframe power Reconnect the coaxial cable to TTL OUT A and the external clock to S1 pins 5 and 4 GND 14 73A 270 Arbitrary Pulse Pattern Generator Module Appendix D Performance Verification b Set the 73A 270 to generate a 500 Hz square wave and then stop the pulse pattern set VX270 IBWRT OS3ROAOM101L104LO0COB Verify a square wave IBWRT Q Verify no pattern c Using the oscilloscope probe check that S1 pin 2 Transmission In Progress A active high 1s a TIL low level and that pin 3 Transmission In Progress A active low is a TTL high level d Restart the 500 Hz pulse pattern with the command below and check that pin 2 of Sl is now a TTL high level and pin 3 is a TTL low level IBWRT OB Check that pin 2 1s high and pin 3 1s low e Move the coaxial cable to TTL OUT B Program the 73A 270 to generate
5. no no no no yes yes yes yes no no no no ves yes yes yes Memory Busy Overwrite Interrupt no no no no no no no no yes ves ves yes ves yes yes yes To check all possible causes of an interrupt an input request must be performed for both channels A and B Reading the data clears the above two interrupt bits XMIT Complete and Memory Busy Overwrite Interrupt for the selected channel In response to an Input Request to the 73A 270 Module the character string 02 lt CR gt lt LF gt might be returned For the selected channel A or B this response indicates that transmission is not in progress that an interrupt has been generated due to transmission completion or a breakpoint that the memory is not busy and that a Memory Busy Overwrite Interrupt has not been generated 73A 270 OPERATION Command I Interrupt Syntax z Purpose The I command enables or disables the XMIT Complete interrupt capability for the selected channel Description z isa l digit decimal integer 0 or that specifies Z Action 0 Disa bles the XMIT Complete interrupt capability for the selected channel l Enables the XMIT Complete interrupt capability for the selected channel Interrupts indicate that a channel has compieted transmission or that a breakpoint has occurred If an interrupt occurs a VXIbus Request True cvent is generated causing an interrupt at the VXIbus interrupt level selected by t
6. Connect TTL OUT A to Ch 2 of the oscilloscope 1 MQ input impedance 2 To verify Ch A operation with the VXIbus TTL trigger lines Set the 73A 270 for Ch A to generate a 500 kHz pulse pattern triggered by an external trigger from TTLTRGO and for Ch B to provide the trigger pulse on TTLITRGO Verify a 500 kHz pulse pattern and then stop the pattern SET VX270 IBWRT 08X80T IBWRT 1S3ROA0M51L54L1C IBWRT OS1ROA1M11L14LOC IBWRT 1B Observe 500 kHz IBWRT Q Verify that the pulse pattern stopped 3 Check the remaining TTLTRG1 through TTLTRG7 lines by sending the commands in table A 6 and verifying a 500 kHz pulse pattern Table A 6 VXIbus TTL Trigger Line Verification Ch A triggered by Ch B TTLTRG Line Change Setup Restart Pattern Verify 500 kHz Pulse Pattern TTLTRG1 IBWRT 18X81T IBWRT 1B Verify 500 kHz pulse pattern TTLTRG2 IBWRT Q28X82T IBWRT 1B TTLTRG3 IBWRT Q38X83T IBWRT 1B TTLTRG4 IBWRT Q48X84T IBWRT 1B TTLTRG5 IBWRT Q58X85T IBWRT 1B 73A 270 Arbitrary Pulse Pattern Generator Module Appendix D Performance Verification Table A 6 Cont VXIbus TTL Trigger Line Verification Ch A triggered by Ch B TTLTRG Line Change Setup Restart Pattern Verify 500 kHz Pulse Pattern TTLTRG6 IBWRT Q68X86T IBWRT 1B TTLTRG7 IBWRT Q78X87T IBWRT 1B 4 Using the following commands disable both channels from the TTLTRGX lines and then resend the trigger pulse fro
7. OSIRA20L41L50L11L65L2COB OS IR A 20L 41L 50L 11L 65L 2C OB Selects Channel A Selects 1 microsecond resolution Selects memory address 0 Sets first data duration for 2 psec inactive Sets second data duration for 4 psec active Sets third data duration for 5 psec inactive Sets fourth data duration for 1 psec active Sets fifth data duration for 6 usec active and specifies it as last duration in the list Specifies repeat of the data output two times Starts transmission on the selected channel Channel A 73A 270 31 OPERATION Command Syntax Purpose Description 73A 270 M Mode zM The M command specifies either the Retriggerable or Non Retriggerable modes for the selected channel Italso enables or disables external triggering z is a 1 digit decimal integer that specifies the following Mode Triggering Retriggerable Internal Retriggerable External Non Retriggerable Internal Non Retriggerable External Mn N The difference between the Retriggerable modes and the Non Retriggerable modes is that in the Non Retriggerable modes B Begin commands or external triggers during transmission are ignored For the Retriggerable modes Bcommands or external triggers during transmission will immediately restart transmission at the beginning of the list unless the channel is halted ata breakpoint If the module is stopped at a breakpoint in any mode a trigger will cause the module to exit the
8. B BNC may be used to observe a TTL signal with a one microsecond period and a high TTL pulse width of 100 nanoseconds LS 73A 270 40 OPERATION Command Syntax Purpose Description Example X External Trigger ZZ X The X command connects or disconnects the External Trigger Input for both channels A and B to or from any of the eight VXIbus backplane TTLTRG lines TTLTRGO through TTLTRG7 or to the VXIbus TRIGGER command or to the front panel BNC or DB25S connector External Trigger Input z and z are l digit decimal integers from 0 to 9 that specify the channel A z and Channel B z external trigger source as follows Connect to IN TTLTRGO TTLTRGI TTLTRG2 TTLTRG3 TTLTRG4 TTLTRGS5 TTLTRG6 TTLTRG7 front panel BNC or DB25S connector VXIbus TRIGGER command Oo Wm Ba Ww tt O When connected to a TTLTRG line a high to low transition generated by another VXIbus module or this module will trigger the connected channel On power up or reset a value of 8 is programmed disconnecting the External Trigger Input from all TTLTRG lines and the V XIbus trigger command and connecting it to the front panel BNC and DB25S connector External Trigger Signal Both channels may be connected to the same TTLTRG line allowing both channels to be triggered by the same signal Any external trigger input must be enabled by the M Mode command And external trigger from any of the TTLTRG lines the f
9. BNC connections provide analog output signals The signal level when the module is not transmitting or transmitting at an inactive level will be the voltage level programmed by the N command The signal level when the module is transmitting and at an active level will be the voltage level programmed by the P command External Trigger Inputs The EXT TRG A and EXT TRG B BNC connections are used to input front panel external triggers When Channei A or B is programmed for an external trigger and the front panel external trigger has been selected bv the X command transmission will start three to four clock cycles 400 ns maximum using the internal clock following a high to low transition of the channels external trigger input Internal IOK pull up resistors pull each input high when not connected DB25S Signals Additional signals provided at the 25 pin DB25S front panel connector are gt external clock input allows several modules to be programmed for parallel operation gt buffered internal clock allows any module to be the common clock source for a parallel module output configuration gt transmission in progress indicates whethertransmission is in progress for each channel See Appendix B for a complete description of these signals 73A 270 OPERATION The module will begin operations The 73A 270 Module will be ready for programming as soon as the VXIbus Resource Manager has initialized
10. System Item Number and Description Minimum Requirements Example Purpose 1 VXIbus Mainframe Two available slots for 73A 270 Tektronix VX1410 VX1400A Provides power cooling and and 73A 541 in addition to the backplane for VXlbus modules Slot 0 controller 2 Slot 0 Controller Resource Mgr Slot 0 Device GPIB VXI Provides Slot 0 functions Functions IEEE 488 GPIB Inter Resource Mgr and GPIB face VXIbus interface 3 VXIbus System Controller VXlbus Talker Listener Controller IBM 486 with National Instru Controlling the VXIbus ments GPIB PC2A card amp System NI 488 2M software and GPIB cable Tektronix part number 012 0991 00 Test System Configuration Table A 3 describes the VXIbus system configuration which is assumed in this procedure If your configuration is different you do not need to change it just note that you will observe your device names and addresses in the test sequence Table A 3 Test System Configuration VXIbus Logical Device GPIB Device Name VXI Slot Address El wl rn fe Test Record Photocopy the Test Record and use it to record the performance verification results for your module 73A 270 Arbitrary Pulse Pattern Generator Module of Appendix D Performance Verification 73A 270 Test Record 73A 270 Serial Number Temperature and Relative Humidity Date of Last Calibration Verification Performed by Certificate Number Date of Verification VXIbus Interface Checks Logical A
11. breakpoint state and start transmission of the next segment of the data list In this case the trigger will not restart transmission at the beginning of the list If the data list has breakpoints in it but is not paused at one of those breakpoints when a retriggerable trigger occurs transmission will restart at the beginning of the data list regardless of what segment of the list is transmitting If the module is retriggered to restart transmission at the beginning of the list the repeat count will not be reset or decremented but will remain at its present value The difference between internal and external triggering is that with internal triggering transmission in a channel will begin immediately when a B command is issued With external triggering the B command becomes an arming command only An external trigger at the front panel ona VXIbus TTLTRG line or a VXIbus TRIGGER command as programmed by the X command then starts transmission An external trigger at the front panel or on a VXIbus TTLTRG line initiates transmission three to four 100 nanosecond clock cycles 400 ns maximum using the internal clock following a high to low transition on the trigger line regardless of the resolution programmed for the channel Operation with Retriggerable mode Internal Triggering The B Begin command starts transmission Transmission will continue for the specified number of repeat times If a B command is issued during transmission tra
12. counter timer acquisition read one response and verify a return count of 42 events SET VX541 IBWRT QM IBRD 100 Observe return count of 42 events f Repeat the burst test sending the data list 21 times IBWRT JM SET VX270 IBWRT 21COB SET VX541 IBWRT QM IBRD 100 Observe return count of 21 events 6 This completes the TTL OUT signal test sequence If you have not checked both channels of the 73A 270 repeat the sequence for the other channel This sequence verifies the output voltage levels polarity and phase for the BPLR OUT A and BPLR OUT B signals Complete all steps in this section for BPLR OUT A and then repeat all steps for BPLR OUT B Equipment Oscilloscope item 1 nedurements Counter Timer item 3 50 Q BNC Coaxial Cable two required item 5 Prerequisites All prerequisites listed on page 56 All previous Performance Verification Sequences 1 Connect the BPLR OUT A or BPLR OUT B to Ch 1 of the oscilloscope 50 Q input impedance 2 Connect the TTL OUT A or TTL OUT B of the 73A 270 under test to Ch 2 of the oscilloscope 1 MQ input impedance 73A 270 Arbitrary Pulse Pattern Generator Module Appendix D Performance Verification 3 To verify the BPLR pulse pattern phase and 2 V accuracy set the 73A 270 to generate a continuous pulse pattern square wave from both the TTL and the BPLR outputs with a 10 us period and a bipolar amplitude of 2 0V Check that the BPLR OUT signal is in phase w
13. following completion of the transmission will repeat the transmission Operation With Non Retriggerable mode External Triggering A single B command to arm transmission and an external trigger to Start transmission are required External trigger inputs are then used to continue transmission after each memory address identified as a breakpoint address External triggers issued while the module is transmitting will be ignored unless the channel is halted ata breakpoint When the list has been transmitted the specified number of times an additional B command is required to arm the external trigger again The command string 8 XOSOMIS3MIB programs Channel A for the Retriggerable mode with internal triggering and Channel B for the Non retriggerable mode with external trigger 81X programs VXIbus TTLTRG as the source of the external trigger on Channel B 1B sends a software trigger to Channel A immediately starting transmission and arms Channel B for occurrence of an external trigger on TTLTRGI A subsequent OB command to Channel A during the transmission will restart Channel A transmission at the beginning of the data list A subsequent B command or external trigger to Channel B while it is transmitting will be ignored unless breakpoints have been programmed into the data list for Channel B 73A 270 33 OPERATION Command N Inactive Analog Bipolar Level Syntax ZN Purpose The N command programs the inactive level of the a
14. front panel BNC connections labeled TTL OUT A and B BPLR OUT A and B and EXT TRG A and B A description of each of the signals follows the pinout listing DB25S Pin No Function External Trigger A TTL active low Transmission In Progress A TTL active high Transmission In Progress A TTL active low Bipolar Out A 2 3 5 External Clock In gt 9 Bipolar Out B 11 Transmission In Progress B TTL active low 12 Transmission In Progress B TTL active high 13 External Trigger B TTL active low 14 Pulse Pattern Out A TTL active high 15 Pulse Pattern Out A TTL active low 17 External Clock Out 24 Pulse Pattern Out B TTL active low 25 Pulse Pattern Out B TTL active high 4 6 10 16 18 23 Digital Ground 8 19 20 21 22 Analog Ground Signal changes are clocked for a high to low transition of the External Clock In or Out signal Pulse Pattern Outputs Pulse pattern outputs for Channel A and B are provided at the TTL OUT A and B front panel BNCs and on the DB25S Pulse Pattern Out A and B TTL active high and Pulse Pattern Out A and B TTL active low connector pins The front panel BNCs and the DB25S Pulse Pattern Out TTL active high outputs are TTL high for an active pulse pattern level The DB25S Pulse Pattern Out TTL active low outputs are TTL low for an active pulse pattern level Analog Bipolar Pulse Pattern Outputs Analog bipolar pulse pattern outputs for Channel A and
15. kHz 0 5 Hz 50 step 3 repeated for table continuity 0 1 IBWRT 1ROA1001L1004LOC0B 100 1us 5 kHz 0 5 Hz 50 0 1 IBWRT 2ROA101L104LOCOB 10 10 us 5 kHz 0 5 Hz 50 0 1 IBWRT 3ROA11L14LO0COB 1 100 us 5 kHz 0 5 Hz 50 0 1 IBWRT 0A21L24L 100 us 2 5 kHz 0 25 Hz 50 IBWRT OROA8585851L4242424L0COB 858585 high 85 8585 ms 20 ns 424242 low 42 4242 ms 20 ns 5 Verify the pulse pattern burst count function with the following steps a Connect the TTL OUT A or TTL OUT B to the counter timer INPUT B input b Set the 73A 270 for a 10 us resolution to first address location to retriggerable mode for a first List entry of 550 us active high and for a second list entry of 550 us active low and designated as the Last Address IBWRT Q IBWRT 2ROA0M551L554L c Set the counter timer for Basic Timer Counter Measurement Mode to Function Event Count B for a Ch B Trigger at 1 V to Gate Indefinitely and to return an Integer Format of maximum 2 7 1 value IBFIND VX541 IBWRT ER Query for any pending ERROR conditions IBRD 100 Observe a 99 response no ERRORs IBWRT MMO FN4 BT 100 BZ1 G1 1F17 IBWRT JM Start the counter timer measurement cycle d Set the 73A 270 to generate the pulse pattern List 42 times and to begin 73A 270 Arbitrary Pulse Pattern Generator Module 65 Appendix D Performance Verification 66 BPLR OUT A and B SET VX270 IBWRT 42COB e Stop the
16. module s VXIbus Control register is set If the Halt Switch is in the ON position the 73A 270 Module is reset to its power up state and all programmed module parameters are reset to their default values If the Halt Switch is in the OFF position the module will ignore the Reset bit and no action will take place NOTE The module is not in strict compliance with the VXIbus Specification when the Halt switch is OFF Control of the Reset bit depends on the capabilities of the 73 A 270 s commander In a CDS 73A IBX System for example the Reset bit is set if the 73A 151 RM IEEE 488 Interface Module receives a STOP command via the IEEE 488 bus External Clock Switches The 73A 270 has two External Clock Switches Depending on the clock source and or frequency of the external clock either the Fast External Clock or the Slow External Clock switch must be activated The Fast External Clock switch is a two position rocker switch Switch to position C2 if an external clock with a frequency of greater than 250 KHz up to 10 MHz is being supplied Switch to position Cl if the internal clock is to be used or if an external clock witha frequency of less than 250 KHz is to be used NOTE If a frequency of less than 10 MHz is supplied VXIbus backplane handshake times for the 73A 270 will be lengthened to greater than 500 nanoseconds The Slow External Clock Switch is a two position slide switch The switch should be p
17. not need to be reprogrammed for each transmission The repeat count is undefined after reset or at power up A C command is required for each channel for predictable operation following a reset or power up The command string 0S0CIS20C specifies that Channel A 1s to repeat its data list continuously and Channel B is to repeat its data list 20 times 25 OPERATION Input Request Response Syntax Purpose Description z lt CR gt lt LF gt An Input Request to the 73A 270 returns status information for the last selected channel An input request is nota command output It is generated by reading inputting from the module The syntax shown is the syntax of the returned data z is a 2 digit decimal number from 00 to 15 encoding four status bits The four bits returned are 1 2 3 4 Transmit In Progress A B Indicates the transmission status A value of l indicates that the selected channel is transmitting This bit will be zero during a breakpoint or following completion of transmission This bit also reflects the state of the XMIT ACTIVE A or XMIT ACTIVE B output on the DB25S connector and the XMT A or XMT B LED on the front panel Transmit Complete Interrupt A B Indicates the status of the Transmit Complete Interrupt A value of indicates that a transmission is complete and an interrupt pending if the interrupt has been enabled by the I command This bit may be used to determine the source of an interr
18. the VXIbus system The 73A 270 Power LED will be on and all other LEDs off The MSG LED will blink during the power up sequence as the VXIbus Resource Manager addresses all modules in the card cage The default condition of the module after power up is described in the SYSFAIL Self Test and Initialization subsection Although these non data commands are initiated by the 73A 270 s commander for example the 73A 151 Module ina CDS 73A IBX System rather than the system controller they have an effect on the 73A 270 Module The following VXIbus instrument protocol commands will affect the 73A 270 Command Effect CLEAR The module clears its YXIbus interface The 73A 270 Module has no input or output command buffers so input and output data transfers are unaffected Current module functional operation is also unaffected TRIGGER The module triggers operation if the external trigger mode is programmed and the VXIbus TRIGGER command has been programmed as the source for the external trigger BEGIN NORMAL OPERATION e u aaae 73A 270 20 OPERATION READ PROTOCOL The module will return its protocol to its commander A summary of the 73A 270 s Module s commands is listed below This is followed by detailed descriptions of each of the commands A sample BASIC program using these commands is shown at the end of this section Command protocol and syntax for the 73A 270 Module are as follows L 3
19. 0 ns 100 nanoseconds to 99 9999 milliseconds l ps I microsecond to 0 999999 seconds 10 ys 10 microseconds to 9 99999 seconds 100 us 100 microseconds to 99 9999 seconds Internal 10 MHz Clock Four programmable resolution ranges 100 nanosecond psec 10 psec and 100 psec resolution External Clock 1 f 10 f 100 f 1000 f f external clock input frequency 6 decimal digits 20 bit resolution Single trigger for total number of output cycles without interruption Each trigger restarts output from first output duration An SS aan 73A 270 8 SPECIFICATIONS Trigger Capability Programmable Sources programmable External Trigger Input VXIbus TTLTRG Selection Trigger Delay Breakpoint Capability Programmed By On Card Memory Clock Source External Clock Input Type Input Range Loading External Clock Outputs Type Frequency TTL Outputs Channel A and B Pulse Pattern Outputs Trigger under program control or trigger with external trigger input from multiple sources Internal Software initiated External Front panel connector Any of 8 VXIbus TTLTRG lines VXIbus TRIGGER command Input Front Panel or VXIbus TTLTRG Trigger occurs on TTL transition from high to low Front Panel Loading 1 TTL load equivalent with 10K pullup Programmable TTLTRG 0 through 7 synchronous trigger protocol From receipt of trigger to start of output 315 ns Ons 100 ns fo
20. 80 Check to see if the status response is an odd number indicating that transmission is still active 120 PRINT 250 MILLISECOND UPDATE INPUT MISSED Print a message to the console if a 250 millisecond update was missed Channel A completed transmission 130 END NOTE Explanation of Line 60 78T87X TTLTRG7 is used to trigger Channel B if Channel A puts outa pulse on TTLTRG OSIM Channel A is sclected and programmed for retriggerable operation with an external trigger OA The address counter is reset 3R25000L15L A 100 psec pulse following a 250 millisecond delay is programmed for Channel A If an external trigger occurs on the Channel A External Trigger BNC within 250 milliseconds the retriggerable operation will start the 250 millisecond delay again without outputting the 100 usec trigger pulsc to Channel B IC Channel A is programmed for a repeat count ol I 1S 20N 52P3M Channel B is programmed for a 2 0V inactive bipolar output level and a 5 2V active bipolar output level and is programmed for external trigger mode to activate the VXIbus TTLTRG 7 trigger input DA The address counter is reset IR A l psec resolution is programmed 11L194L8C Programs a usec pulse followed by a 19 psec gap for transmission eight times IB Arms both Channels A and B for an external trigger Channel A from the front panel BNC and Channel B from VXIbus TTLTRG 7 Operation will start as soon as the first pulse occurs on the Channel A BNC i
21. A pulse pattern Verify that channel B is not putting out any pulse pattern and then stop the pulse transmission IBWRT Q88X88T IBWRT 1B Verify that channel B is not putting out any pattern IBWRT Q 8 Verify the EXT TRG B input with the following steps a Connect TTL OUT A to EXT TRG B Restart both channels by sending IBWRT 1B Verify a 500 kHz pulse pattern b Check that channel B is putting out a 500 kHz pulse pattern triggered by channel A and then stop the pattern by sending IBWRT Q Verify that the pattern stopped c Disconnect TTL OUT A from EXT TRG B 9 Verify channel B breakpoint recognition with the following steps 73A 270 Arbitrary Pulse Pattern Generator Module 11 Appendix D Performance Verification 72 a Program TTL OUT B to generate a continuous pulse pattern having a 10 ms active high level pulse with an active breakpoint followed by a 10 ms active low level pulse with an active breakpoint with the following steps IBWRT 1S3ROA0M1003L1006LO0C IBWRT 0B Check that TTL OUT B is held at a TTL high level which demonstrates that the pattern stopped at the active high pulse breakpoint Restart the pulse pattern several times and check each time that the TTL OUT B signal level alternates between a TTL low level and a TTL high level as the breakpoints are being recognized IBWRT OB IBWRT OB IBWRT Q Verify that the pulse pattern stopped 73A 270 Arbitrary Pul
22. Appendix A for definition of register contents All required de power is provided by the Power Supply in the VXIbus card cage 5 Volt Supply 4 75V dc to 5 25V dc 24 Volt Supply 23 2V de to 25 2V dc 24 Volt Supply 23 2V dc to 25 2V dc 5 2 Volt Supply 4 95V dc to 5 45V de 2 0 Volt Supply 1 9V de to 2 1V dc 5 volt supply 3 3 A 24 volt supply 120 mA 24 volt supply 100 mA 5 2 volt supply 35 mA 2 0 volt supply 26 mA 5 volt supply 150 mA ptp 23 MHz 24 volt supply 185 mA ptp 23 MHz 24 volt supply 245 mA ptp 17 MHz 5 2 volt supply 435 mA ptp 23 MHz 2 0 volt supply 435 mA ptp 22 MHz 424V de tested with 7V de MHz bipolar output into 50 Ohms on both channels Provided by the fan in the VXIbus card cage Less than 10 C temperature rise with 1 76 liters sec of air ata pressure drop of 0 099 mm of H O Replacement fuses 5V Littlefuse P N 273004 5 2V 2V Littlefuse P N 273002 24V Littlefuse P N 273001 10 C to 65 C operating assumes ambient temperature of 55 and airflow to assure less than 10 C temperature rise 40 C to 85 C storage Less than 95 R H noncondensing Complies with VXIbus Specification Complies with VXIbus Specification ae 73A 270 12 SPECIFICATIONS Dimensions Shipping Weight Weight Shipping Mounting Position Mounting Location Front Panel Signal Connectors Recommended Cable Equipment Supp
23. B are provided at the BPLR OUT A and B front panel BNCs and on the DB25S Bipolar Out A and Bconnector pins The signal level for both the BNC and DB25S connections when the module ts not transmitting or is transmitting at an inactive level will be as programmed by the N command The signal level when the module is transmitting and an active level is programmed will be as programmed by the P command 73A 270 APPENDIX B External Trigger Inputs The EXT TRG A and EXT TRG B BNC connections or the DB25S External Trigger A and B TTL active low connector pins are used to input external TTL trigger signals When Channel A or B is programmed for an external trigger and the front panel external trigger has been selected by the X command transmission will start three to four clock cycles 400 ns maximum using the internal clock 400 ns maximum using the internal clock following a high to low transition of the channel s external trigger input on cither the BNC or DB25S pin Internal 10K pull up resistors pull each input high when not connected Sl Connector Input Output Signals Sl is a 25 pin DB25S connector which provides several additional Input Output signals Additional signals provided at the DB25S front connector are gt an external clock input so that several modules may be programmed for parallel operation gt a buffered internal clock brought to the front connector of the APPG Module allowing any mod
24. Bit 4 0 This module supports the trigger command 73A 270 49 APPENDIX A 14 supports VXIbus 488 2 Instrument protocol Bit 3 This module does not support 488 2 protocol I supports VXIbus Instrument protocol Bit 2 0 This module supports instrument protocol ELW supports Extended Longword Serial protocol Bit This module does not support ELW protocol LW supports Longword Serial protocol Bit 0 l This module does not support LW protocol 73A 270 Interrupts The 73A 270 will interrupt its commander with the following events Unrecognized Command Event 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 11101111 lt Logical Address gt This event is generated by this module in response to any command sent to the data low register other than the following Byte Available Byte Request Begin Normal Operation Clear Read Protocol Trigger Identifv Commander Request True 1514 131211109876 5432510 1 1 1 1 1 0 I lt Logical Address gt This event is generated as programmed by the I command or in response to a memory busy overwrite error An SSS SSS Nana 73A 270 50 APPENDIX A APPENDIX B FRONT PANEL INPUT OUTPUT CONNECTIONS The signals listed below are available on a DB25S connector When seen from the front Pin l is on the bottom right and Pin 14 is on the bottom left Six of the signals Pulse Pattern Out A and B Bipolar Out A and B and External Trigger A and B are also available on the
25. E LIABLE FOR ANY INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER TEKTRONIX OR THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES EC Declaration of Conformity Tektronix Holland N V Marktweg 73A 8444 AB Heerenveen The Netherlands declare under sole responsibility that the 73A 270 meets the intent of Directive 89 336 EEC for Electromagnetic Compatibility Compliance was demonstrated to the following specifications as listed in the Official Journal of the European Communities EN 55011 Class A Radiated and Conducted Emissions EN 5008 1 1 Emissions EN 60555 2 AC Power Line Harmonic Emissions EN 50082 1 Immunity IEC 801 2 Electrostatic Discharge Immunity IEC 801 3 RF Electromagnetic Field Immunity IEC 801 4 Electrical Fast Transient Burst Immunity IEC 801 5 Power Line Surge Immunity To ensure compliance with EMC requirements this module must be installed in a mainframe which has backplane shields installed which comply with Rule B 7 45 of the VXIbus Specification Only high quality shielded cables having a reliable continuous outer shield braid amp foil which has low impedance connections to shielded connector housings at both ends should be connected to this product Table of Contents Description Igiigola 1 AA 1 Controls And Indicators esa as a dardo do aii 4 o A SA 4 FUSOS AA ud ree Paste Roh ek te BR a Se ee Ee Oe Ee eae hare Gees 5 LEDS orena reg eee PER hae ee
26. ED is lit whenever SYSFAIL is asserted indicating a module failure Module failure consists of loss of a power voltage NOTE If the module loses any of its power voltages the Failed LED will be lit and SYSFAIL asserted A module power failure is indicated when the modules Power LED is extinguished MSG LED This green LED is normally off When lit it indicates that the module is processing a VMEbus cycle The LED is controlled by circuitry that appears to stretch the length of the VMEbus cycle For example a five microsecond cycle will light the LED for approximately 0 2 seconds The LED will remain lit if the module is being constantly addressed Mode Resolution LEDs Four LEDs are provided for each of the two channels Channel A and Channel B The eight LEDs are arranged in the following order at the top front of the module When lit the LEDs indicate the following XMTA _hannel A is transmitting EXTA Channel A external trigger is enabled TBOA Channel A resolution least significant bit TBIA Channel A resolution most significant bit XMTB Channel B is transmitting EXTB Channel B external trigger is enabled TBOB Channel B resolution least significant bit TBIB Channel B resolution most significant bit The TBO and TBI resolution LEDs are encoded as follows TBI LED TBOLED Resolution OFF OFF 100 nanosecond OFF ON l microsecond ON OFF 10 microsecond ON ON 100 microsecond
27. TLTRG lines TTLTRGO through TTLTRG 7 z and z are l digit decimal integers from 0 to 8 that specify the connections of Channel A z and Channel B z output to the VXIbus TTLTRG lines as follows Connects to Zz TTLTRG Line 0 0 2 2 3 3 4 4 5 5 6 6 7 7 8 Disconnect from all TTLTRG lines The T command has no effect on connections to the front panel BNC or DB25S 25 pin connector pulse pattern outputs they are always connected On power up or reset a value of 8 is programmed disconnecting the pulse pattern output from all TTLTRG lines Both channels may be connected to the same TTLTRG line Since the V XIbus TTLTRG lines are open collector the line will be driven low if either channel is programmed for an active polarity level by the L command The TTLTRG line is driven low when an active pulse pattern output level is programmed to achieve this wired OR capability made possible by the open collector signals The pulse pattern output may also be connected to the same TTLTRG line as the external trigger see the X command of the opposite channel to use one channel to trigger another This command programs both Channel A and Channel B independent of the active channel programmed by the S Select command The command string 28T82X0S3R2MO0A 3600000LISLICISOR3MOAIIL94L0CIB programs Channel A for connection to VXIbus TTLTRG2 and Channel B for no connection to the TTLTRG lines It also programs a
28. User Manual Tektronix Y 73A 270 Arbitrary Pulse Pattern Generator Module 070 9148 03 la FA bus This document supports firmware version 1 00 and above Warning The servicing instructions are for use by qualified personnel only To avoid personal injury do not perform any servicing unless you are qualified to do so Refer to the Safety Summary prior to performing service CE Copyright O Tektronix Inc All rights reserved Tektronix products are covered by U S and foreign patents issued and pending Information in this publication supercedes that in all previously published material Specifications and price change privileges reserved Printed in the U S A Tektronix Inc RO Box 1000 Wilsonville OR 97070 1000 TEKTRONIX and TEK are registered trademarks of Tektronix Inc WARRANTY Tektronix warrants that this product will be free from defects in materials and workmanship for a period of three 3 years from the date of shipment If any such product proves defective during this warranty period Tektronix at 1ts option either will repair the defective product without charge for parts and labor or will provide a replacement in exchange for the defective product In order to obtain service under this warranty Customer must notify Tektronix of the defect before the expiration of the warranty period and make suitable arrangements for the performance of service Customer shall be responsible for pack
29. age is being used the jumper points may be reached through the front of the card cage There are five 5 jumpers that must be installed for each empty slot The five jumpers are the pins to the left of the empty Slot A O ssa aaa Pp i SS SSS i SSS i EE 73A 270 INSTALLATION CAUTION The 73A 270 Module is a piece of electronic equipment and therefore has some susceptibility toelectrostatic damage ESD ESD precautions must be taken whenever the module is handled ba xr 3 Record the module s Revision Level Serial Number located on the CDS label on the top shield of the 73A 270 and switch settings on the Installation Checklist on the next page Oniy qualified personnel should install the 73A 270 Module Verify that the Logical Address and Interrupt Level switches are switched to the correct value The Halt switch should be in the ON position unless it is desired to not allow the resource manager to reset this module Note that with either Halt Switch position a hard reset will occur at power on and when SYSRST is set true on the VXIbus backplane If the module s commander is a CDS 73A 151 RM IEEE 488 Interface Module SYSRST will be set true whenever the Reset Switch on the front panel of the 73A 151 is depressed Also note that when the Halt Switch is in the OFF position the module is not in strict compliance with the VXIbus Specification The module can now be inserted into any slot of t
30. aging and shipping the defective product to the service center designated by Tektronix with shipping charges prepaid Tektronix shall pay for the return of the product to Customer if the shipment is to a location within the country in which the Tektronix service center is located Customer shall be responsible for paying all shipping charges duties taxes and any other charges for products returned to any other locations This warranty shall not apply to any defect failure or damage caused by improper use or improper or inadequate maintenance and care Tektronix shall not be obligated to furnish service under this warranty a to repair damage resulting from attempts by personnel other than Tektronix representatives to install repair or service the product b to repair damage resulting from improper use or connection to incompatible equipment or c to service a product that has been modified or integrated with other products when the effect of such modification or integration increases the time or difficulty of servicing the product THIS WARRANTY IS GIVEN BY TEKTRONIX WITH RESPECT TO THIS PRODUCT IN LIEU OF ANY OTHER WARRANTIES EXPRESSED OR IMPLIED TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE TEKTRONIX RESPONSIBILITY TO REPAIR OR REPLACE DEFECTIVE PRODUCTS IS THE SOLE AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER FOR BREACH OF THIS WARRANTY TEKTRONIX AND ITS VENDORS WILL NOT B
31. ander for details on the operation of that device If the Module is being used in a CDS 73A IBX System card cage the module s commander will be the 73A 151 Resource Manager IEEE 488 Interface Module Refer to the 73A 151 Operating Manual and the programming examples at the end of this section for information on how the system controller communicates with the 73A 151 The module consists of two completely separate arbitrary pulse pattern generators with a common VXIbus backplane interface Each channel contains a 1600 word by six decimal digit high speed memory This memory is used to store up to 1600 six digit output duration time values The six digit data loaded into each memory location represents the length of time the output will remain active or inactive for that point in the data list A separate two digit decimal counter is provided for each channel to allow transmission of the data list from 1 to 63 times Separate circuitry is provided for each channel to allow channel specific selection of resolution start of transmission retriggering modes or interrupt enabling Very complex wave trains may be programmed For example up to 800 100 nsec pulses may be programmed with the intervals between each pulse varying from 100 nsec to 100 msec Or by programming 1500 consecutive 100 millisecond active levels followed by a 100 nsec inactive level a 100 nsec pulse may be accurately delayed 150 seconds In the higher resolu
32. annel It also enables or disables the external triggering for both modes TTLTRG specifies VXIbus TTLTRGO through TTLTRG7 for connection to Channel A and B s pulse pattern output or specifies no connection External Trigger specifies the source for an external trigger for Channel A and B as a VXIbus TTLTRGO through TTLTRG b the VXIbus TRIGGER command or 73A 270 OPERATION c the front panel BNC connector or the equivalent DB25S connector pin N Inactive Analog specifies the analog bipolar output voltage level tor the selected channel corresponding to an inactive pulse pattern signal output P Active Analog specifies the analog bipolar output voltage level for the selected channel corresponding to an active pulse pattern signal output Input Request An Input Request to the 73A 270 returns status information for the selected channel An input request is not a command output It is generated by reading from the module I Interrupt enables or disables interrupt capability for the selected channel B Begin triggers data transmission for one or both channels Transmission will begin immediately if external triggering is not active If external triggering is active for a channel the B command arms the external trigger input Subsequently received external trigger inputs will then initiate transmission Q Quit stops transmission in progress for one or both channels A detailed descr
33. annels Description zis a l digit decimal integer 0 or 1 that specifies the following Z Action 0 Begin or arm transmission for the channel last selected with an S command Begin or arm transmission for both channels simultaneously The type of triggering selected by the M command determines whether the B command starts or arms transmission With internal triggering the B command starts transmission With external triggering the B command is an ARM command for the external trigger Example The command string OSOM0OB1S1 MOB initiates transmission in Channel A then arms transmission in Channel B OS select Channel A OM enable internal trigger and retriggerable mode OB begin transmission IS select Channel B IM enable external trigger and retriggerable mode OB arm transmission for an external trigger E A ee ie EA 5 E E A 5 nn ng PP PP 73A 270 24 OPERATION Command Syntax Purpose Description Example 73A 270 C Count zC The C command specifies the number of times to transmit the entire data list in memory associated with the selected channel zisa l or 2 digit decimal integer from 0 to 63 that specifies the number of times to transmit the data list The value 0 specifies that the data list is to be transmitted continuously The repeat count value can not be changed during operation The last programmed repeat count is reloaded automaticaliy by the module at the completion of transmission It does
34. ave only Interrupter Fast Handshake capability No Shared Memory capability Not used Not used Per VXI Per VXI Not used Not used Not used Indicates that the instrument portion of the module has data available to be read Set by the instrument following a Byte Request command and cleared on a read from the Data Low register or on reset i 73A 270 48 APPENDIX A BIT DEFINITIONS continued Register Response cont d Bit Location Bit Usage 73A 270 Value 9 Write Ready l or 0 8 FHS Active 0 7 Locked 6 0 Device dependent 11 1111 Data High not implemented Data Low read write Word Serial Commands 73A 270 Usage Cleared upon receipt of a Byte Available command Set when the instrument is ready to receive a data byte or on reset FHS active FHS inactive Not used Not used A write to the Data Low Register causes this module to execute some action based on the data written This section describes the device specific Word Serial commands this module responds to and the results of these commands Read Protocol Command 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 1 1 0O 2 1 2 1 2 1 1 1 2 1 12 1 1 If the Data Low register is read after this command the contents are as follows VXIbus Revision Level Bit 15 0 VXIbus Revision 1 2 Device Device dependent unused Bits 14 13 12 11 l1 1 1 1 Reserved Bits 10 9 8 7 6 5 1 1 1 1 1 1 Triggered supports trigger command
35. ce Type definition below Status 0004H R 1X11 1111 1111 1111 BFFFh or FFFFh Control 0004H W 0111 1111 1111 110X 7FFCh or 7FFDh Offset 0006H WO Not used Protocol 0008H RO 11110111 1111 1111 F7FFh Response 000AH RO Defined by state of the interface Data High 000CH Not used Data Low OOOEH W See Data Low definition below Data Low 000EH R See Data Low definition below 73A 270 47 APPENDIX A BIT DEFINITIONS Register ID 15 14 13 12 11 0 Device Tvpe 15 0 Status 15 14 13 4 1 0 Control 15 14 2 Protocol 15 14 13 12 11 Response 15 13 12 11 10 Bit Location Bit Usage Device Class Address Space Manufact ID Device Type A24 32 Active MODID Device dependent Extended Passed Device dependent A24 32 Enable Device dependent SYSFAIL Inhibit Reset CMDR Signal Reg Master Interrupter FHS Shared Memory Reserved Device dependent Defined valuc of 0 Reserved DOR DIR ERR Read Ready 73A 270 Value 10 11 1111 1111 1100 1111 1110 1111 000 l 0 11 1111 1111 1 lor 0 111 1111 1111 11 l Oo 11 1111 1111 or 0 73A 270 Usage Message Based Al6 only Colorado Data Systems Ones comp of 270 Not used MODID line not active MODID line active Not used Not used Always passed Not used No effect Not used Disables module from driving Sysfail Enables module to drive Sysfail Reset Not reset Servant only No Signal Reg Sl
36. command is sent to the module during transmission and the command is different from that presently programmed for the channel the resolution multiplier for the channel will immediately change to correspond to the new programmed value l The command string OSORISIR programs Channel A for 100 nanosecond resolution and Channel B for microsecond resolution Programming a duration value of 6 with the L command will create a 600 nanosecond duration value on Channel A and a 6 microsecond duration value on Channel B If an external clock of 5 MHz is supplied and the command string OSOR is sent the resolution for Channel A will be 1 5 10 or 200 nanoseconds ho 73A 270 37 OPERATION Command S Select Syntax zS Purpose The S command selects Channel A or Channel B as the active channel for subsequent commands Description z is the l digit decimal integer 0 or 1 that selects the channel iN Channel Selected 0 Channel A l Channel B An S command can be sent while a transmission is in progress without affecting transmission operations Examples The command string 0S selects Channel A as the active channel for subsequent commands that affect only the active channel EEEE a a 73A 270 38 OPERATION Command Syntax Purpose Description Example T TTLTRG 2 271 The T command connects or disconnects the pulse pattern output forchannels A and B to or from any of the eight VXIbus backplane T
37. d data are sent via the VXIbus Byte Available command All module specific commands are made up of ASCII characters Module specific data may be in either ASCII or binary format Data transfer bus DTB slave A16 D16 only Switch selectable levels i highest priority through 7 lowest D16 lower 8 bits returned arc the logical address of the module Upper 8 bits contain the VXIbus protocol event code Active for internal clock and for recommended external clock switch settings for external clock All VXIbus commands are accepted e g DTACK will be returned The following commands have effect on this module all other commands will cause an Unrecognized Command Event BYTE AVAILABLE with or without END bit set BYTE REQUEST BEGIN NORMAL OPERATION CLEAR IDENTIFY COMMANDER READ PROTOCOL TRIGGER VXIbus events are returned via VME interrupts The following events are supported and returned to the 73A 270 Module s commander UNRECOGNIZED VXIbus COMMAND REQUEST TRUE In IEEE 488 systems such as the 73A IBX this interrupt will cause a Service Request SRQ to be generated on the IEEE 488 bus ID Device Type 73A 270 11 SPECIFICATIONS Power Requirements Voltage Current Peak Module Ip Current Dynamic Module lpm Cooling Fuses Temperature Humidity VXIbus Radiated Emissions V XIbus Conducted Emissions Status Control Protocol Response Data Low See
38. d for each channel to allow transmission of the data list from to 63 times Each location in memory can be identified aS an active or inactive output Any location in the memory can be identified as the last address to provide a variable length data list Any number of locations in the memory can be identified as breakpoints for pausing and then continuing transmission Like other CDS products the APPG Module combines ease of use and flexibility of function in its programmable features These features include gt four output modes per channel Retriggerable and Non Retriggerable Modes each with internal or external triggering gt breakpoint capability provided in all four modes at any location in the list gt interrupts can be programmed to generate an interrupt to the VxXIbus backplane when transmission is complete or at breakpoints gt four time resolutions ranges 100 nsec psec 10 psec or 100 usec gt initial polarity of transmission may be programmed so that a transition from the inactive state will occur either immediately on triggering or 73A 270 DESCRIPTION after one or more durations of output repeat count can be programmed to repeat from 1 to 63 times or indefinitely gt capability to drive any of the eight VXIbus TTLTRG backplane lines gt external triggering external trigger source may be selected under program control to be any of the eight V XIbu
39. ddress IEEE Address Slot No MFG Model etc Table Command Response II CI 7 Program Command Response 1 MHz Patterm mems TTL OUT A Checks Minimum Measured Value Maximum Time Base Resolution 100ns 10ns f99ns 110 ns 100us 10ns 99 99 ps PF 100 01 ss Pulse Duration Multiplier 1000 1005 49995 HZ 5 000 5 Hz 100 lps es5Hz oo Boosk 10x10ps e95Hz oo Boosk 1x100ps 499956 oo Boosk 85 8585 ms 20 ns 85 85848 ms 85 85852 ms AA Fale SustPaten axis CET TTL OUT B Checks Minimum Measured Value Maximum Time Base Resolution 100ns 10ns f90ns fp 110 ns 58 73A 270 Arbitrary Pulse Pattern Generator Module Appendix D Performance Verification 73A 270 Test Record Cont TTL OUT B Checks Minimum Measured Value Maximum Pulse Duration Multiplier 1000 100 05 AZ fe 5 000 5 Hz tooxips 49995Hz 5 000 5 2 1x100ps 499956 5 000 5 H 85 8585 ms 20 ns 85 85848ms 8585852ms DO CI LT CET o Votags ESTE anov w Opposite Phase with TTLOUT 8 7v 260mv E7I0W Law Voltage Easow eno OO w Opposite Phase with TTLOUT 8 7v 260mv E7I0W fee Triggering amp Breakpoint for Channel A Failed Trigger Lines mao ooo mwe ooo mw PSS mws mre mws mwe mwr eama S Breakpoint SONS 73A 270 Arbitrary Pulse Pattern Generator Module 59 Appendix D Performance Verification 73A 270 Test Record Cont Triggering 4 Breakpoint for Channel B Passed Failed Trigger Lines E o ree o Tres
40. delayed 100 usec 73A 270 39 OPERATION pulse on Channel A that is used to trigger a continuous waveform on Channel B 36 seconds later 28T connects Channel A to TTLTRG2 82X connects Channel B external trigger to TTLTRG2 OS selects Channel A 3R programs Channel A for 100 usec resolution 2M programs Channel A for non retriggerable internal trigger mode OA reset Channel A data list address to address 0 3600000L programs first data list as 360000 100 usec durations or 36 seconds at an inactive level IS5L programs second data list duration as a 100 usec active duration will drive TTLTRG2 active low and as the last data list value IC programs Channel A for a repeat count of 1 1S selects Channel B OR programs Channel B for 100 nanosecond resolution 3M programs Channel B for non retriggerable external trigger mode OA resets address counter IIL programs first Channel B data list value as 100 nanosecond active level 94L programs the second Channel B data list value as a 900 nanosecond inactive level and as the last data list value OC programs Channel B for continuous transmission IB triggers Channel A to start its delayed pulse program and arms Channel B for the external trigger to be generated by Channel A When this command is sent the XMTA TBOA TBIA and EXTB LEDs will light Exactly 36 seconds later the XMTA LED will go out and the XMTB will light continuously At this time an oscilloscope on the TTL OUT
41. described waveform An active level isa TTL high Example 2 This example programs the Channel B bipolar output to put outa steady state 2Y signal as long asa TTL active low pulse occurs on the Channel A External Trigger BNC input at least every 250 milliseconds If a pulse is missed a series of eight 1 psec pulses of 5 2V are output on the Channel B output with 19 usec gaps between the pulses The bipolar output is terminated with a 50 Ohm load Lines 10 through 40 initialize the PC s IEEE 488 interface card as a system controller with an EEE 488 address of decimal 21 Line 50 assigns the decimal IEEE 488 address of the 73A 270 to the variable ADDR270 10 DEF SEG amp HC400 Defines memory location of IBM PC IEEE 488 Interface Module 20 SEND 9 INIT 0 ENTER 2 Initialize PROM offsets for IBM PC IEEE 488 Interface Module a a _ K K 73A 270 44 OPERATION 30 PC ADDRESS 21 CONTROL 0 Define IEEE 488 Interface Modules IEEE 488 address and define it to be a controller 40 CALL INIT PC ADDRESS CONTROL 50 ADDR270 24 Define 73A 270 s IEEE 488 address 60 WRTS 78T87X0S1IM0A3R25000L15L 1ICIS 20N 52P3MO0AIRI1ILI94L8C1 BOS See the Note below 70 CALL SEND ADDR270 WRTS STATUS 80 RDS SPACES 4 90 CALL ENTER RD LENGTH ADDR270 STATUS Read the status of Channcl A to see if transmission ever completed 100 XMT VAL RD 110 IF XMT 2 INT XMT 2 gt 5 THEN GOTO
42. dth 50 Q input Tektronix TDS 460 Checking pulse pattern signal impedance lt 1 5 DC vertical timing amplitude and phase accuracy 250 MHz 10X 10 MQ 12 7 A P6130 Checking pulse pattern signal 1 amplitude and phase 10 MHz measurement a 73A 541 Checking pulse burst accuracy 25MH SY MHz Tektronix VX4790A VX4790A Checking external clock 50 Q impedance BNC male connec Tektronix part number a electrical tors 012 0057 01 signals SMB to BNC Adapter Cable 50 Q impedance SMB male BNC Tektronix VX1729 Interconnecting electrical female connectors signals BNC Female to BNC Fe male barrel BNC Male to Dual Binding Post DB 25 front panel intercon nectassembly 50 Q impedance Female to BNC Tektronix part number Dea electrical Female 103 0028 00 signals 50 Q impedance BNC male Dual Tektronix part number Interconnecting electrical Binding Post connectors 103 0035 00 signals Male DB 25 Connector with 6 inch DB 25 Tektronix part Interconnecting electrical jumper wires 26 AWG soldered to number 131 0570 00 signals pins 4 5 73A 270 Arbitrary Pulse Pattern Generator Module Appendix D Performance Verification 73A 270 Under Test Configuration In order to perform this verification procedure the 73A 270 under test must be installed in an approved VXIbus system At a minimum the system must contain the elements listed in Table A 2 Table A 2 Elements of a Minimum 73A 270 Under Test
43. e 73A 270 TTL OUT A to Ch 1 of the oscilloscope 2 V div 250 ns div 1 MQ input impedance b With the following commands set the 73A 270 to the beginning of the address space for the first List entry to have a duration of 500 ns 5x100 ns power on default resolution active high for the second List entry to have an active low duration of 500 ns and to be designated as the Last Address to transmit the list continuously and finally to begin transmission of the last selected channel in this case Ch A the power on default Verify a 1 MHz 50 duty cycle pulse pattern IBOC Start GPIB Talker Listen Controller program IBFIND VX270 IBRD 100 Observe 00 response IBWRT 0A51L54LOCOB Observe 1 MHz square wave IBWRT Q Observe waveform stops 3 To verify interrupt capability set the 73A 270 to enable the transmit complete interrupt XMIT and to generate a burst of 63 pulses Then read and verify a response of 02 This response means that there is no transmis sion in progress that an interrupt has been generated due to transmission completion or breakpoint that the memory is not busy and that a Memory Busy Overwrite interrupt has not been generated Following the read the Slot O controller will be un addressed and will acknowledge the interrupt as an SRQ pending 62 73A 270 Arbitrary Pulse Pattern Generator Module Appendix D Performance Verification NOTE Make sure the 73A 270 and the Slot O Resource Manager a
44. e Write to the 73A 270 Module proceeds as follows l The commander reads the 73A 270 s Response register and checks if the Write Ready bit is true If it is the commander proceeds to the next step If not the commander continues to poll the Write Ready bit until it becomes true 2 The commander writes the Byte Available command to the 73A 270 s Data Low register OBCXX or OBDXX depending on the End bit The module also supports the Fast Handshake mode during some commands In this mode the module is guaranteed to return DTACK within the 20 microsecond window defined by the VXIbus Specification If the internal 10 MHz clock is used the 73A 270 will return DTACK within 550 nanoseconds For non normal use where a slow external clock is used with the Clock switches set for fast external clock the 73A 270 Module asserts BERR to switch from Fast Handshake mode to Normal Transfer mode The 73A 270 s Read Ready and Write Ready bits react properly during Fast Handshake A Fast Handshake Transfer Mode Read of the 73A 270 Module proceeds as follows The commander writes the Byte Request command ODEFFh to the 73A 270 s Data Low register t The commander reads the 73A 270 s Data Low register A Fast Handshake Transfer Mode Write to the 73A 270 Module proceeds as follows i LR 73A 270 APPENDIX A The commander writes the Byte Available command which contains the data OBCXX or OBDXX dependin
45. e an interrupt to the V XIbus backplane when transmission 1s complete or at breakpoints to indicate the need for a trigger to continue transmission Time Duration Ranges The 6 digit output time duration values for each channel may be programmed using 100 nanosecond increments up to 100 milliseconds usec increments up to second 10 psec increments up to 10 seconds or 100 usec increments up to 100 seconds Other resolutions may be obtained by using an external clock available through the front panel DB25S connector The module uses the VXIbus slot 0 10 MHz ECL clock for its internal time base In applications requiring synchronous operation between multiple VXIbus mainframes multiple APPG modules may be driven by a single APPG or all modules can be driven by a Single external clock source Initial Polarity The initial polarity of transmission active or inactive level may be programmed so that a transition from the inactive state will occur either immediately on triggering or after one or more durations of output Both polarities of the output are available at the module s DB25S front connector so that nea 73A 270 OPERATION either polarity may be defined as the inactive state BNC connectors are provided on the front panel for TTL output and the bipolar analog output levels for cach of the two channels Repeat Count The complete output pulse train for each channel can be programmed to rep
46. e in a card cage conforming to the VXIbus Specification such as the 73A 021 used in the CDS 73A IAC System The module provides two completely independent output channels with a common VXIbus backplane interface Each channel can be individually programmed to generate an arbitrary string of active and inactive TTL or bipolar analog 17 4V pulse or pattern outputs Each channel contains a 1600 word by six decimal digit high speed memory This memory is used to store up to 1600 6 digit output duration time values Since the APPG allows programmingof 1600 duration values not just 1600 l s and 0 s very complex pulse trains may be programmed After initial programming these duration values may be updated in progress while the APPG is transmitting The APPG s ability to output short pulses repeatedly or short pulses delayed by long intervals make it ideal for triggering other VXIbus instruments using either front panel connectors or the VXIbus backplane TTLTRG bus for signal routing And in applications requiring synchronous operation between multiple VXIbus mainframes multiple APPG modules may be driven by a single APPG or all modules can be driven by a single external clock source The six digit data loaded into each memory location represents the duration time of the Output the length of time the output will remain active or inactive for that point in the data list A separate two digit decimal counter is provide
47. e module will go to the following known states Channel A Selected Resolution 100 nanosecond both channels Mode Retriggerable both channels External Trigger Disabled both channels External Trigger Source Front panel both channels VXIbus TTLTRG Pulse Pattern output not programmed Interrupt Capability Disabled both channels Pulse Pattern Memory Contents Undefined Channel A amp B Repeat Count Undefined LEDs Extinguished except for Power LED Pulse Pattern Outputs Inactive Transmission In Progress Outputs Transmission not in progress Bipolar Outputs OV de for both Active and Inactive levels Data Commands 1 8 Mbytes per second fast handshake mode Throughput will be affected by system controller and system controller VXIbus interface Normal Mode Word Serial transfer or Fast Handshake Word Serial mode Switch selectable 1 through 254 e e a 73A 270 10 SPECIFICATIONS VXIbus Compatibility VXI Device Type VXI Protocol VXI Card Size Module Specific Commands VMEbus Interface Interrupt Level Interrupt Acknowledge V XIbus Fast Handshake VXIbus Commands Supported VXIbus Protocol Events Supported VXIbus Registers Fully compatible with the VXIbus Specification for message based instruments with the Halt Switch in the ON position VXI message based instrument YV XIbus Revision 1 2 Word serial C size one slot wide All module specific commands an
48. e soldered to pins 4 and 5 of a male DB 25 connector d Set the clock source AWG to generate a 1 MHz square wave IBFIND VX4790 IBWRT SETSQUARE 0 2 5 1000000 10 T The fourth parameter is numeric one followed by alphabetic O 73A 270 Arbitrary Pulse Pattern Generator Module 73 Appendix D Performance Verification e Set the 73A 270 to divide the 1 MHz external clock source by 10 10 us resolution and to set the pulse duration multiplier to 10 to generate a square wave with a 200 us period 5 kHz with the following steps SET VX270 IBWRT OS1ROAOM101L104LOCOB Verify 5 kHz waveform f Momentarily disconnect the SMB connector from the VX4790A and check that the 5 kHz pulse pattern is no longer present on TTL OUT A 2 Verify the Slow External Clock input with the following steps a Turn the mainframe power off and remove the 73A 270 Return the FAST EXTERNAL CLOCK switch to the Cl position and change the SLOW EXTERNAL CLOCK switch to the ON external position Replace the 73A 270 and turn the mainframe power on Reconnect the coaxial cable to the TTL OUT A and the Arbitrary Waveform Generator clock source to pins 5 and 4 GND of S1 b Program the 73A 270 to select the 200 kHz external clock and to set its pulse duration multiplier to 20 to generate a 5 kHz square wave IBWRT OSOROAOM201L204LO0COB c Set the clock source to provide a 200 kHz square wave SET VX4790 IBWRT SETSQUARE 0 2 5 200000 10 T
49. eat from l to 63 times or indefinitely The individual output durations active or Inactive including the level duration presently transmitting may be updated in progress while the module is transmitting TTLTRG Capability Each channel s output may be programmed to drive any of the eight VXIbus TTLTRG backplane lines The 73A 270 s ability to output short pulses repeated or delayed by extremely long intervals makes it useful for triggering other V XIbus instruments External Triggering The external triggers for each channel may also be driven under program control by any of the eight VXIbus TTLTRG lines By Selecting the same TTLTRG line one channel s pulse pattern output may be used to externally trigger the other channel or other APPG modules Bipolar Analog Outputs The bipolar analog output for both the active and inactive states is programmable over the full voltage output range The outputs for each channel are 50 ohm sources capable of driving a 50 ohm load to 8 7V dc with a 100 mV resolution or a high impedance load to 17 4V de with a 200 mV resolution e Front Panel BNC Connectors TTL Pulse Pattern Outputs The TTL OUT A and TTL OUT B BNC connections provide the programmed active and inactive output pulse trains for each channel The TTL compatible outputs for each channel are at a TTL high when an active level is programmed Analog Bipolar Pulse Pattern Outputs The BPLR OUT A and BPLR OUT B
50. ecuted Repeat Count A programmable count on the 73A 270 Module that allows the pulse pattern output up to 1600 locations to be repeated a specified number of times up to 63 times or continuously Retriggerable Mode A programmed mode on the 73A 270 that allows the pulse pattern output to restart at the beginning of its transmission list if a trigger is received while the module is actively transmitting Pulse Pattern Outputs A series of active and inactive levels of varying programmable time durations provided on a single wire output Two independent outputs are provided on the 73A 270 Module 73A 270 7 DESCRIPTION SPECIFICATIONS Number of Channels Type Outputs Bipolar Outputs TTL Outputs Number of Sequentiai Output Durations Number of Repeat Times Time Period of Each Output Duration Programmable Resolution of Each Output Duration Significant Digits Time Period Programming Trigger Modes Non retriggerable Mode Retriggerable Mode T wo TTL active high and active low VXIbus TTLTRG bipolar analog each channel Programmable level 17 4 volts 8 7 into 50 ohms Transition time lt 70 nsec 10 to 90 points typical Drive capability 3 2 mA source 24 mA sink current l to 1600 per channel to 63 or continuous Programmable to 999 999 times the resolution range seleizd for each channel Resolution Range Time Period Duration 10
51. elected channel 1s programmed for the number of times the entire data list in memory is to be transmitted with the C Count command The selected channel may also be programmed with the M Mode command to select or deselect the retriggerable or non retriggerable modes with or without external trigger enabled or to enable or disable the VXIbus interrupt capability with the I Interrupt command Transmission is then initiated with the B Begin command e Programmable Features Modes Four output modes are provided for each channel The first two the Non Retriggerable Modes with internal or external triggering each transmit the string of active and inactive level outputs the specified number of times ignoring additional triggers dur ng transmission The second two the Retriggerable Modes with internal or external triggering reset the module to the beginning of the transmit string if an additional trigger is received during transmission Breakpoint Capability A breakpoint capability is provided in all four modes at any location in the list Transmission stops following any level programmed with a breakpoint and resumes when an additional trigger is received The external trigger modes may be triggered by a TTL signal on each channel cither through the VXIbus TTLTRG lines through a front panel BNC or DB25S connector or by the VXIbus TRIGGER command Interrupts The APPG Module can be programmed to generat
52. except when the 5V power is lost VXI Commands These are commands passed from a commander to a servant within the VXIbus environment A command may or may not be prompted bv an external event For example an EEE 488 GROUP ENECUTE TRIGGER wiil generate a trigger command to all addressed devices However a BEGIN NORMAL OPERATIONS command is generated by the V XI bus resource manager and has no external source VXI Events Events are passed trom a servant to a commander They may be generated by the servant either in response toa command forexample Unrecognized Command event or due to a condition detected in the module internal error V NI Message Based Instrument An intelligent instrument that implements the defined VXIbus registers and at a minimum the Word Serial Protocol All CDS VXIbus devices are message based SAI Word Serial Protocol The simplest required communication protocol supported bv Message Based devices in a VXIbus system It utilizes the Al6 communications registers to transfer data using a simple polling handshake method All CDS VXIbus devices impiement the Word Serial protocol 488 XIbus Interiace An EEE 488 to VXIbus interface Device is a message based device which provides between the EEE 488 bus and V XI bus instruments 73A a a f way APPENDIX C communication hh See Appendix D Performance Verification This procedure verifies the performance o
53. f the 73A 270 Arbitrary Pulse Pattern Generator It may be performed in your current V XIbus system if it meets the requirements described in Table A 2 Also it is not necessary to complete the entire procedure if you are only interested in a specific performance area Some tests depend on the correct operation of previously verified functions so it is best to perform the entire procedure in the order presented The following skills are required to perform this procedure m Thorough knowledge of test instrument operation and proper measurement techniques m Knowledge of VXIbus system components and command language programming m Ability and facility to construct interconnections and fixtures as needed to perform the procedure General Information and Conventions Please familiarize yourself with the following conventions which apply throughout the procedure m Each verification sequence begins with a table similar to the one below which provides information and requirements specific to that section Equipment Oscilloscope item 1 Requirements i qu Oscilloscope Probe item 2 Prerequisites Prerequisites listed on page 56 The item number after each piece of equipment refers to an entry in Table A 1 Required Test Equipment m This procedure assumes that your VXIbus system is configured as indicated in Table A 3 and that you will be using the National Instruments PC GPIB controller and software NI 488 2M In the verificatio
54. for their physical locations e Switches Logical Address Switches Each function module in a VXIbus System must be ae assigned a unique logical go address from to 255 decimal The base VMEbus address of the 73A 270 is set to a value between 1 and FFh 255d by two hexadecimal rotary switches Align the desired switch position with the arrow on the module shield LOGICAL ADDRESS The actual physical address of the 73A 270 Module is on a 64 byte boundary If the switch representing the most significant digit MSD of the logical address is set to position X and the switch representing the least significant digit LSD of the logical address is set to position Y then the base physical address of the 73A 270 will be 64d XYh 49152d For example L S Base Physical O Addr id A 64 101 49162 49792d 5 64 21 49152 50496d L A Logical ddress MSD Most Significant Digit LSD Least Significant Digit EEE 488 Address Using the 73A 270 Module in an IEEE 488 environment requires knowing the module s IEEE 488 address in order to program it Different manufacturers of IEEE 488 interface devices may have different algorithms for equating a logical address with an IEEE 488 address If the 73A 270 is being used ina CDS IEEE 488 IAC system consult the operating manual of the CDS 73A 151 RM 488 Interface Module If the 73A 270 is not being used in a CDS IAC System consult the operat
55. g on the state of the End bit to the 73A 270 s Data Low register The 73A 270 Module has no registers beyond those defined for VXIbus Message Based devices All communications with the module are through the Data Low register the Response register or the VXIbus interrupt cycle Any attempt by another module to read or write to any undefined location of the 73A 270 s address Space may cause incorrect operation of the module CAUTION If the user s card cage has other manufacturer s computer boards operating in the role of VXIbus foreign devices the assertion of BERR as defined by the VXIbus Specification may cause operating problems on these boards REGISTER DEFINITIONS As with all VXIbus devices the 73A 270 Module has registers located within a 64 byte block in the Al6 address space The base address of the 73A 270 device s registers is determined by the device s unique logical address and can be calculated as follows Base Address V 40H COOOH where V is the device s logical address as set in the Logical Address switches 73A 270 Configuration Registers Below isa list of the 73A 270 Configuration Registers with a complete description of each In this list RO Read Only WO Write Only R Read and W Write The offset is relative to the module s base address Register Address Type Value Bits 15 0 ID Register 0000H RO 1011 1111 1111 1100 BFFCh Device Type 0002H RO See Devi
56. guage that will give the same result L O a aaa 73A 270 OPERATION Command Result CALL ENTER R LENGTH ADDRESS STATUS The CALL ENTER statement inputs data into the string R from the EEE 488 instrument whose decimal primary address is contained in the variable ADDRESS Following the input the variable LENGTH contains the number of bytes read from the instrument The variable STATUS contains the number 0 if the transfer was successful or an 8 if an Operating system timeout occurred in the PC Prior to using the CALL ENTER statement the string R must be set to a string of spaces whose length 1s greater than or equal to the maximum number of bytes expected from the 73A 270 CALL SEND ADDRESS WRTS STATUS The CALL SEND statement outputs the contents of the string variable WRTS to the IEEE 488 instrument whose decimal primary address is contained in the variable ADDRESS Following the output of data the variable STATUS contains a if the transfer was successful and an if an operating timeout occurred in the PC END Terminates the program FOR NEXT Repeats the instructions between the FOR and NEXT statements for a defined number of iterations GOSUB n Runs the subroutine beginning with line n EX GOSUB 750 runs the subroutine beginning on line 750 The end of the subroutine is delineated with a RETURN statement When the subroutine reaches the RETURN statement executio
57. he 73A 270 to output a 2 psec pulse 4 psec after trigger followed 10 usec later by a ten millisecond 10 000 psec pulse The signal is output on Channel A and is repeated continuously The module is programmed for retriggerable operation with internal triggering Lines 10 through 40 initialize the PC s IEEE 488 interface card as a system controller with an IEEE 488 address of decimal 21 Line 50 assigns the decimal IEEE 488 address of the 73A 270 to the variable ADDR270 10 DEF SEG amp HC400 Defines memory location of IBM PC IEEE 488 Interface Module 20 SEND 9 INIT 0 ENTER 2 Initialize PROM offsets for IBM PC IEEE 488 Interface Module 30 PC ADDRESS 21 CONTROL 0 Define IEEE 488 Interface Module s IEEE 488 address and define it to be a controller 40 CALL INIT PC ADDRESS CONTROL 50 ADDR270 24 Define 73A 270 s IEEE 488 address 60 WRTS 0OSOCOA IROM40L21L100L100005LQ0B OS selects Channel A OC programs continuous output OA resets the data list address pointer and IR programs psec resolution The following four L commands program a 4 usec inactive level a 2 psec active level a 10 psec inactive level and a 10 millisecond active level output The 5 in the 100005L identifies the 10 millisecond duration as both active and the last item in the list OB starts transmission on Channel A 70 CALL SEND ADDR 270 WRT STATUS 380 END Connecting an oscilloscope to the TTL OUT A BNC will display the
58. he Interrupt Level Select Switch on the 73A 270 Module The VX Ibus Interrupt Acknowledge clears the interrupt Triggering the module to resume transmission arms the interrupt for the next transmission completion or breakpoint The 73A 270 generates two additional types of interrupts that cannot be disabled and are unaffected by the I command They are the VXIbus Unrecognized Command interrupt and the Memory Busy Overwrite interrupt see the L command The interrupt status may be read from the module atany time The interrupt status is returned in response to an input request to the module see input Request as a two digit decimal integer followed by a carriage return and line feed lt CR gt lt LF gt Example The command string 0S111SOI enables the XMIT Complete interrupt for Channel A and disables the XMIT Complete interrupt for Channel B See the Input Request command description for an example of the response to an Input Request A 73A 270 28 OPERATION Command L List Syntax ZZL Purpose For the selected channel the L command specifies the time duration and polarity of the output level breakpoint and last address determination for the current memory address Description Z is a l to 6 digit decimal integer from to 999999 that specifies the duration of the output level as z times 100 nanoseconds microsecond 10 microseconds or 100 microseconds depending upon the resolution programmed for that channel The z
59. he chassis other than slot 0 This module does not connect to the VXIbus local bus so no front panel keying is required NO TE Cable Installation If the DB25S connections are to be used use either a 73A 734 Data Cable or 73A 782P Hooded Connector to interface between the DB25S output connector and the UUT If the module is being installed in a CDS 73A Series card cage route the cable from the front panel of the module down through the cable tray at the bottom of the card cage and out the rear of the card cage No calibration is required for this module 73A 270 INSTALLATION INSTALLATION CHECKLIST Installation parameters may vary depending on the card cage being used Be sure to consult the card cage Operating Manual before installing and operating the 73A 270 Module Revision Level Serial No Card Cage Slot Number Switch Settings VXIbus Logical Address Switch Interrupt Level Switch Halt Switch Fast External Clock Slow External Clock Cable Installed Performed by Date A A Pa Pr PPPs Sn 73A 270 16 INSTALLATION OPERATION The 73A 270 Module is programmed by ASCII characters issued from the system controller to the 73A 270 Module via the modules VXIbus commander and the VXIbus card cage backplane The module isa VXIbus Message Based Instrument and communicates using VXIbus Word Serial Protocol Refer to the manual for the VXIbus device that will be the 73A 270 Module s comm
60. hese PEPE Re Peon ese nestles E A 6 BITE Built in lest EQuipmen 2221 22 2526 4dsadv ee ent a errada acabes 6 OSS ALY AAA oe ane ae a a ea eo ee eee eo RE as we 7 SDECINICAONS 2224 barr 0 ee eee ars es Eh 8 Installation Installation Requirements and Cautions 00 0 e eens 14 installation Procedure sc Secs nee ele et ee we E ewes yee Swe soe wae ewe Sows 15 installation Checklist 6 24 dt REA ebay eer deen ean asians 16 Operation O deck P Facet atic cB hace al cates hae a ete cima ttplcae acon E E AA es eae E EEEE 17 Programming Sequence o cccccccc een ee eet e eee e ee te ne enees 17 Programmable Features 0 ccc nc 18 Front Panel BNC Connectors 0 0 0 tent a e ete nnees 19 OW CI 3 tom Seid tes Qe Bias a Oe Bee eR Eh SES ASU OSL eee bee eth metab EEEO 20 System COMAN dS estadio taria toes eee tddi 20 Module Commands vezsicertar tirarte ras sas 20 SUMMA ea a o eee aes a 21 Command Descriptions xi aa 22 SYSFAIL Self Test and Initialization o o oooooooooooor eee eens 41 Programming ExXamples criar ai a ada sas 41 Definition of BASIC Commands 0 ccc ene n ene n een ne nnes 41 Programming Examples in BASIC 0 cc tte n nent n en enees 42 Appendices Appendix A VXlbus Operation nananana anaana een teen ene e ene eee eees 46 Appendix B Front Panel Input Output Connections 0 0 ees 51 Appendix C VXIbus Glossary iii e eo eee Seas 53 Appendix D Perf
61. ies are valid The default condition of the 73A 270 Module after the completion of power up is Channel A Selected Resolution 100 nanosecond both channels Mode Retriggerable both channels External Trigger Disabled both channels External Trigger Source Front panel both channels VXIbus TTLTRG Pulse Pattern Output Not connected Interrupt Capability channels Disabled both Channel A and B Pulse Pattern Memory Contents Undefined Channel A and B Repeat Count Undefined Power LED Lit All Other LEDs Extinguished Pulse Pattern Outputs Inactive Transmission In Progress Outputs Inactive SYSFAIL Operation SYSFAIL becomes active for any power supply failure or if the module loses any of its power voltages When the card cage Resource Manager detects SYSFAIL set it will attempt to inhibit the line This wall cause the 73A 270 Module to deactivate SYSFAIL in all cases except when 5 volt power is lost This section contains example programs which demonstrate how the various programmable features of the 73A 270 are used The examples are written in BASIC using an IBM PC or equivalent computer as the system controller e Definition of BASIC Commands The programming examples in this manual are written in Microsoft GW BASIC using the GW BASIC commands described below If the programming language you are using does not conform exactly to these definitions use the command in that lan
62. ified The outputs will hold the polarity programmed for the last time duration prior to the pause An interrupt may be enabled see I command which generates an interrupt when the breakpoint occurs The breakpoint is exited when the channel iS triggered again The last address capability allows variable line length data lists of less than 1600 items to be transmitted or repeated In Progress Updates An L command can be sent while the module is transmitting allowing in progress updating of the data stream output The new data can be specified at an address other than the address actively transmitting with minimal or no effect on the transmission A minimal output time duration distortion occurs if the output is transitioning exactly when the new data is strobed into memory in which case the transition is delayed two time increments i e 200 nanoseconds To avoid the time increment delay in progress commands should be timed to occur when the output data is not changing If in progress data updates occur when the data to be up dated is presently being transmitted the new data will be effective immediately allowing lengthening or shortening the duration change of polarity or change in breakpoint status or last address status of the data presently being transmitted If the new data duration is less than the duration time already elapsed the module will transition to the next data duration immediately NOTE For the special case of hav
63. ing manual of the IEEE 488 interface device being used for recommendations on setting the logical address VMEbus Interrupt Level Select Switch P Each function module in a a VXIbus System can generate DA an interrupt on the VMEbus S to request service from the interrupt handler located on its commander for example the 73A 151 RM IEEE 488 Interface Module in a CDS 73A IBX System The VMEbus interrupt level on which the 73A 270 Module generates interrupts is set by a BCD rotary switch Align the desired switch position with the arrow on the module shield Valid Interrupt Level Select switch settings are through 7 with setting equivalent to level 1 etc The level chosen should be the same as the level set on the 73A 270 s interrupt handler typically the module s commander Setting the switch to an invalid interrupt level 0 8 or 9 will disable the module s interrupts When using the 73A 270 in a CDS 73A IBX System set the interrupt level to the same level chosen on the 73A 151 Interrupts are used by the module to return VXIbus Protocol Events to the module s commander Refer to the Operation section for information on interrupts The VXIbus Protocol Events supported by the module are listed in the Specifications section eA tt A 55 5 5 5 5 5 rn a nn nn nn nn 73A 270 DESCRIPTION Halt Switch MALT This two position slide switch selects the response of the 73A 270 Module when the Reset bit in the
64. ing several successive duration outputs programmed to 100 nanoseconds in progress updating cannot always be done without error If several in progress updates are attempted in this situation the data may be overwritten and lost A status capability which indicates whether the memory is busy IS provided for these applications see Input Request An in progress update should not be attempted when the memory is busy The memory will not be accessible until the next time duration of 200 nanoseconds or more A Memory Busy Overwrite interrupt will be generated if an in progress data update occurs while memory is busy The command string OSIRA20L41L50L11L65L programs the first output level of Channel A to a 2 usec inactive output followed by a 4 psec active output followed by a 5 psec inactive ouput followed by a l psec and 6 psec active output The 6 psec output is also specified as the last output in the list for Channel A The IR characters preceding the L command specify a l usec resolution for Channel A The data is therefore in increments of usec Figure 270 2 illustrates the output resulting from this command when programmed to repeat twice using the C Count command ee hh i anne ur E SS E E nn E NN 73A 270 30 OPERATION INACTIVE INACTIVE i l i l l PASS 1 PASS 2 18 usec Total 18 usec Total Figure 270 2 Sample Waveform TTL BNC Output The above waveform would be output from Channel A as a result of the command
65. ion of 100 ns 10 ns 73A 270 Arbitrary Pulse Pattern Generator Module 63 Appendix D Performance Verification 64 IBWRT OROA11L14L0COB Observe 100 ns 10 ns pulse width c Verify the additional time base resolutions as directed in Table A 4 Table A 4 Time Base Resolution Verification Command to Send Pulse Width to Verify IBWRT OROA11L14LOCOB 100 ns 10 ns step 2b repeated for table continuity IBWRT Q1ROB 1 us 10 ns IBWRT Q2ROB 10 us 10 ns IBWRT Q3ROB 100 us 10 ns IBWRT Q Verify that the waveform stopped 3 To verify the pulse duration multiplier set the 734 270 for a 100 ns resolution to the beginning of the address space for a first List entry of 100 us active high for a second List entry of 100 us active low and designated as the Last Address to transmit the list continuously and finally to begin transmission of the last channel selected Verify a 5 kHz 0 5 Hz square wave IBWRT OR0OA10001L10004LOC0B Verify 5 kHz 0 5 Hz 4 Verify the additional pulse duration multipliers as directed in Table A 5 NOTE The last measurement in Table A 5 may require a Timer Counter if you wish to verify the precise tolerances listed 73A 270 Arbitrary Pulse Pattern Generator Module Appendix D Performance Verification Table A 5 Pulse Duration Multiplier Verification Multiplier Verify Period and Command to Send Resolution Duty Cycle IBWRT OAOR10001L10004LOC0B 1000 100ns 5
66. iption of each command in alphabetical order is given on the following pages e Command Descriptions Command A Address Syntax ZA Purpose The A command specifies a memory address in the selected channel s memory i 73A 270 22 OPERATION Description Example z isa l to 4 digit decimal integer from O to 1599 that specifies the current memory address for the selected channel If z is omitted the address will be set to address 0 The A command strobes the address specified by z into the memory address register of the selected channel An A command can be sent while a transmission is in progress The command will not affect the transmission nor will the transmission affect the contents of the address register Two independent address registers one for programming the other for transmission permit re programming without affecting transmission Since the A command doesn t require reloading of the complete data list any time duration value in memory can be changed by programming the appropriate address with the A command and updating the time duration value with the L command If Channel B has been selected as the active channel using the S command then the command string 44A programs Channel B memory address register to decimal value 44 73A 270 23 OPERATION Command B Begin Syntax ZB Purpose The B command either initiates or arms transmission for the selected channel or for both ch
67. ith the TTL OUT signal and that the amplitude is 42 0 V 2 mV SET VX270 IBWRT OS or IBWRT 1S Select Ch A or Ch B IBWRT 1ROAOC51L54L0B IBWRT 20P 20N Verify 2 0 V 260 mV 4 Reset 73A 270 for a BPLR OUT amplitudes of 5 0 V and 8 7 V and verify that the corresponding BPLR OUT signals are in phase with the TTL OUT signal and that the amplitude is within 260 mV of the value set Then change the polarity of the BPLR OUT signal and verify Finally set the BPLR OUT signal to 0 V and verify IBWRT 50P 50N Verify 45 0 V 260 mV IBWRT 87P 87N Verify 18 7 V 260 mV IBWRT 87P87N Verify 8 7 V 260 mV and opposite polarity IBWRT OOPOON Verify 0 0 V 260 mV IBWRT Q Verify that the pulse pattern 1s stopped 5 The verification steps in this section should be performed for both BPLR OUT A and BPLR OUT B channels If you have not tested both channels repeat the steps in this section for the other channel Triggering and This sequence verifies the operation of the 73A 270 with the VXIbus TTL Breakpoint Function trigger lines 8 internal and external triggering and breakpoint recognition 73A 270 Arbitrary Pulse Pattern Generator Module 67 Appendix D Performance Verification 68 Equipment Oscilloscope item 1 dia Counter Timer item 3 50 Q BNC Coaxial Cable two required item 5 Prerequisites All prerequisites listed on page 56 All previous Performance Verification Tests 1
68. laced in the ON position if an external clock with a frequency of less than 250 KHz is to be used NOTE For slow external clock operation the external clock is internally synchronized to the internal 10 MHz clock Phase jitter of up to 50 nsec will be introduced Slow external clock operation does not dela y the 500 nanosecond VXIbus backplane handshake times The Fast External Clock switch instead of the Slow External Clock switch may be used for slow external clocks if throughput ts not critical and elimination of phase jitter 1s required o Fuses The 73A 270 Module has 5V 5 2V 2V and 24V removable fuses The fuses protect the module in case of an accidental Shorting of the power bus or any other situation where excessive current might be drawn If any fuse opens the VXIbus Resource Manager will be unable to assert SYSFAIL INHIBIT on this module to disable SYSFAIL If any fuse opens remove the fault before replacing the tuse Replacement fuse information is given in the Specifications section of this manual 73A 270 DESCRIPTION o LEDs The following LEDs are visible at the top of the 73A 270 Module s front panel to indicate the status of the module s operation Power LED This green LED is normally lit and is extinguished if the 5V 5 2V 2V or 24V buses or the internally regulated 20 9V buses fail or if the 2V 5V 5 2V or 24V fuses open Failed LED This normally off red L
69. lied When ordered with a CDS card cage this module will be installed and secured in one of the instrument module slots slots 1 12 When ordered alone the module s shipping dimensions are 406 mm x 305 mm x 102 mm 16 in x 12 in x 4 in 1 4 kg 3 1 lbs When ordered with a CDS card cage this module will be installed and secured in one of the instrument module slots slots 1 12 When ordered alone the shipping weight 1s 1 9 kg 4 3 Ibs Any orientation Installs in an instrument module slot slots 1 12 of a Cor D size VXIbus card cage Refer to D size card cage manual for information on required adapters Six BNC jacks Pulse pattern outputs TTL Pulse pattern outputs bipolar External trigger inputs One DB 25S connector Pulse pattern outputs TTL active high and active low Pulse pattern outputs bipolar External trigger inputs Transmission in progress outputs TTL active high and active low External clock input and output for DB 25S connector 73A 734 Data Cable or 73A 782P Hooded Connector 1 73A 270 Arbitrary Pulse Pattern Generator Module 73A 270 13 SPECIFICATIONS INSTALLATION The 73A 270 Module is a C size VXIbus instrument module and therefore may be installed in any C or D size VXIbus card cage slot other than slot 0 If the module is being installed in a D size card cage consult the operating manual for the card cage to determine how to install the m
70. lified Suspected Failures service personnel 73A 270 Arbitrary Pulse Pattern Generator Module iil General Safety Summary Safety Terms and Symbols Terms in This Manual These terms may appear in this manual A WARNING Warning statements identify conditions or practices that could result in injury or loss of life CAUTION Caution statements identify conditions or practices that could result in damage to this product or other property Terms on the Product These terms may appear on the product DANGER indicates an injury hazard immediately accessible as you read the marking WARNING indicates an injury hazard not immediately accessible as you read the marking CAUTION indicates a hazard to property including the product Symbols on the Product The following symbols may appear on the product A A O DANGER Protective Ground ATTENTION Double High Voltage Earth Terminal Referto Manual Insulated Certifications and Compliances Overvoltage Category Overvoltage categories are defined as follows CAT III Distribution level mains fixed installation CAT II Local level mains appliances portable equipment CAT I Signal level special equipment or parts of equipment telecommunica tion electronics iv 73A 270 Arbitrary Pulse Pattern Generator Module 73A 270 ARBITRARY PULSE PATTERN GENERATOR DESCRIPTION The 73A 270 Arbitrary Pulse Pattern Generator APPG Module is a printed circuit board assembly for us
71. m channel B to restart the pulse pattern from channel A Check that channel A is not putting out a pulse pattern and then stop the pulse pattern IBWRT Q88X88T IBWRT 1B Verify no pulse pattern from channel A IBWRT Q 5 Verify the EXT TRG A input with the following steps a Connect TTL OUT B to EXT TRG A b Restart both channels with the following command IBWRT 1B Cc Verify a 500 kHz pulse pattern from channel A triggered by channel B and then stop the pattern IBWRT Q Verify that the pattern stopped d Disconnect TTL OUT B from EXT TRG A 6 Verify channel A breakpoint recognition with the following steps a Set the 73A 270 to generate a continuous pulse pattern having a 10 ms active high level pulse with an active breakpoint followed by a 10 ms active low level pulse with an active breakpoint with the following commands IBWRT OS3ROAOM1003L1006LOC b Trigger the pulse pattern and check that the TTL OUT A pulse pattern is held at a TTL high level confirming that the pattern stopped at the active high pulse breakpoint 73A 270 Arbitrary Pulse Pattern Generator Module 69 Appendix D Performance Verification IBWRT OB Verify a TTL high level c Retrigger the pulse pattern several times and check after each start that the TTL OUT A signal level alternates between a TTL low level and a TTL high level IBWRT OB Verify a TTL low level IBWRT OB Verify a TTL high level IBWRT Q
72. maining dirt with lint free cloth dampened in a general purpose deter gent and water solution Do not use abrasive cleaners User Replaceable Parts Replacement parts are available through your local Tektronix field office or representative Changes to Tektronix instruments are sometimes made to accommodate improved com ponents as they become available Therefore when ordering parts it is important to in clude the following information in your order m Part number m Instrument type or model number Instrument serial number m Instrument modification number if applicable 73A 270 77 78 Appendix E User Replaceable Parts Part Description User Manual Label Tek CDS Label VXI Fuse Micro 4 Amp 125 V Fast Fuse Micro 1 Amp 125 V Fast Fuse Micro 2 Amp 125 V Fast Collar Screw Metric 2 5 x 11 Slotted Shield Front Screw Phillips Metric 2 5 x 4 FLHD SS Part Number 070 9148 XX 950 4523 00 950 4522 00 159 0374 00 159 0116 00 159 0128 00 950 0952 00 950 4174 00 211 0867 00 73A 270
73. n sequences you will be instructed to issue Interface Bus Interactive Control ibic commands to set up the 73A 270 system Please refer to the NI 488 2M User Manual for additional information If you are using a different controller simply substitute the equivalent commands 73A 270 Arbitrary Pulse Pattern Generator Module 99 Appendix D Performance Verification Prerequisites Equipment Required The test sequences in this procedure are a valid verification of the 73A 270 when the following requirements are met m The 73A 270 has been calibrated within the last 12 months m The 73A 270 module covers are in place and the module is installed in an approved V XIbus mainframe according to the procedure in Section 2 of the Operating Manual m The 73A 270 has passed its power on self test m The 73A 270 is operating in an ambient environment as specified in Section 1 of the Operating Manual and has been operating for a warm up period of at least 10 minutes This procedure uses traceable signal sources and measurement instruments Table A 1 lists the required equipment You may use equipment other than the recommended examples if it meets the minimum requirements listed Table A 1 Required Test Equipment Item Number and Description Minimum Requirements Example si Purpose 1 56 Digitizing Oscilloscope Oscilloscope Probe Counter Timer External Clock Source 50 Q BNC Coaxial Cable two required 300 MHz bandwi
74. n will resume on the line following the GOSUB command GOTO n Program branches to line n EX GOTO 320 directs execution to continue at line 320 IF THEN Sets up a conditional IF THEN statement Used with other commands such as PRINT or GOTO so that IF the stated condition is met THEN the command following is effective EX IF I 3 THEN GOTO 450 will continue operation at line 450 when the value of variable I 1s 3 REM All characters following the REM command are not executed REM statements are used for documentationanduser instructions EX REM CLOSE ISOLATION RELAYS RETURN Ends a subroutine and returns operation to the line after the last executed GOSUB command lt CR gt Carriage Return character decimal 13 lt LF gt Line Feed character decimal 10 e Programming Examples In BASIC The following sample BASIC programs show how commands for the 73A 270 might be used These examples assume that the 73A 270 has logical address 24 and is installed in a VXIbus card cage that is controlled through an IEEE 488 interface from an external system controller such as an IBM PC or equivalent using a Capital Equipment Corp IEEE 488 interface The VXIbus IEEE 488 interface is assumed to have an IEEE 488 primary address of decimal 21 and to have converted the 73A 270 Module s logical address to an IEEE 488 primary address ol decimal 24 73A 270 OPERATION Example The following program causes t
75. nalog bipolar output for the selected channel Description zisa 2 digit signed decimal number from 00 to 87 that specifies the inactive output level into a 30 ohm load as a multiple of 100 millivolts Leading zeros are required the sign is optional The inactive level is the level resulting from programming the polarity bit associated with a time duration to inactive using the L command and the level present on the output when the module is not transmitting The output into a high impedance load will be twice the programmed output level providing a maximum output level of 17 4V The output level for loads other than 50 ohms or open high impedance may be calculated as follows Output Level 2 Programmed Voltage Value R R 50 where R is the load On power up or reset the module is programmed for an inactive output level of 0 volts dc Examples l 67N programs an inactive level of 6 7 into a 50 ohm load or 13 4 into an open load 2 09N programs an inactive level of 900 millivolts into a 50 ohm load or 1 800 volts into an open load 3 To determine the programmed voltage value needed to achieve a 12 volt output into a 300 ohm load use the above equation as follows Programmed Voltage Value Output Level R 50 2R or PVV 12 300 50 7 volts 2 300 The command 70N will achieve the desired inactive level output of 12V for a 300 ohm load a _ 73A 270 34 OPERATION Command Sy
76. nput OS Selects Channel A for the status response read in Line 90 et e PPP nn 73A 270 45 OPERATION APPENDIX A VXlbus OPERATION The 73A 270 Module is a C size single slot VXIbus Message Based Word Serial instrument It uses the Al6 DI6 VME interface available on the backplane Pl connector and does not require any A24 or A32 address space The module is a D16 interrupter The 73A 270 Module is neither a VXIbus commander nor VMEbus master and therefore it does not have a VXIbus signal register The 73A 270 isa VXIbus message based servant The module supports both the Normal Transfer mode and the Fast Handshake Mode of the V XIbus using the Write Ready and Read Ready bits of the module s Response register A Normal Transfer mode Read of the 73A 270 Module proceeds as follows i The commander reads the 73A 270 s Response register and checks if the Write Ready bit is true If it is the commander proceeds to the next step If not the commander continues to poll the Write Ready bit until it becomes true 2 The commander writes the Byte Request command to the 73A 270 s Data Low register QDEFFh 3 The commander reads the 73A 270 s Response register and checks 1f the Read Ready bit ts true If it is the commander proceeds to the next step If not the commander continues to poll the Read Ready bit until it becomes true 4 The commander reads the 73A 270 s Data Low register A Normal Transfer mod
77. nsmission will immediately restart at the 32 OPERATION Examples beginning of the data list The repeat count will not be changed Transmission will continue until the end of the data list has been sent the specified number of repeat times Operation with Retriggerable mode External Triggering The B command arms the external trigger When received the external triggerstarts transmission Transmission will continue for the specified number of repeat times An external trigger issued during transmission will immediately restart transmission at the beginning of the data list unless the channel is halted ata breakpoint The repeat count will not be changed Transmission will continue until the end of the data list has been sent the specified number of repeat times An additional B command is then required to rearm the external trigger If breakpoints have been programmed an external trigger is required to continue operation following each breakpoint occurrence Operation With Non Retriggerable mode Internal Triggering The B command is required to start transmission An additional B command is required to continue transmission after each memory address identified as a breakpoint address B commands issued while the module is transmitting will be ignored If no breakpoints are programmed the module will transmit the data list the number of times specified by the C command ignoring any triggers during transmission A new trigger
78. ntax Purpose Description Examples P Active Analog Bipolar Level zP The P command programs the active level of the analog bipolar output for the selected channel z is a 2 digit signed decimal number from 00 to 87 that specifies the active output level into a 30 ohm load as a multiple of 100 millivolts Leading zeros are required the sign is optional The active level is the level resulting from programming the polarity bit associated with a time duration to active using the L command The output into a high impedance load will be twice the programmed output level providing a maximum output level of 17 4V The output level for loads other than 50 ohms or open high impedance may be calculated as follows Output Level 2 Programmed Voltage Value R R 50 where R 1s the load On power up the module is programmed to an active output level of 0 volts dc l 67P programs an active level of 6 7 intoa 50 ohm load or 13 4 intoan open load 2 09P programs an active level of 900 millivolts into a 50 ohm load or 1 800 volts into an open load 3 To determine the programmed voltage value needed to achieve a 12 volt output into a 300 ohm load use the above equation as follows Programmed Voltage Value Output Level R 50 2R or PVV 12 300 50 7 volts 2 300 The command 70P will achieve the desired level output of 12V fora 300 ohm load 73A 270 35 OPERATION Command Q Q
79. o E TRG oo EXTTRGA Joo AA External Clock amp Transmission In Progress Passed Failed External Clock FASTEXTCLK f Transmission In Progress Transmit in Prog ress A Transmit in Prog ress B Breakpoint 60 73A 270 Arbitrary Pulse Pattern Generator Module Appendix D Performance Verification Self Test Following the VXIbus system startup sequence the green PWR light on the 73A 270 front panel indicates that all power supplies are operational If the 5 V 5 2 V 2 V 24 V or the internally regulated 20 9 V buses fail or if the 2 V 5 V 5 2 V or 24 V fuses open the PWR light will be off Additional ly the FAILED light will be on and SYSFAIL will be asserted indicating a module failure If any of the Mode or Resolution lights are on it usually is an indication that the 73A 270 has not completed its initialization correctly One typical reason for this condition is the FAST EXTERNAL CLOCK switch being in the external C2 position NOTE If you experience any error indication from the Slot 0 Resource Manager the 73A 270 or other VXIbus module investigate and correct the problem before proceeding Common items to check are logical address conflicts primary and secondary see Table A 3 breaks in the VXIbus daisy chain signals improper seating of a module loose GPIB cable Performance Verification Tests This procedure verifies the performance of the 73A 270 The test sequences contain set
80. odule in that particular card cage Setting the module s logical address switch defines the module s programming address Refer to the Controls and Indicators subsection for information on selecting and setting the 73A 270 Module s logical address CAUTION To avoid confusion it is recommended that the slot number and the logical address be the same Tools Required The following tools are required for proper installation Slotted screwdriver set CAUTION Note that there are two ejector handles on the module To avoid installing the module incorrectly make sure the ejector labeled 73A 270 is at the top CAUTION In order to maintain proper card cage cooling unused card cage slots must be covered with blank front panels supplied by the card cage manufacturer Based on the number of IAC Modules ordered with a CDS card cage blank front panels are supplied to cover ali unused slots CAUTION Verify that the card cage is able to provide adequate cooling and power for the 73A 270 Module Refer to the card cage Operating Manual for instructions on determining cooling and power compatibility CAUTION If the 73A 270 Module is inserted in a slot with any empty slots to the left of the module the VME daisy chain jumpers must be installed on the backplane in order for the 73A 270 Module to operate properly Check the manual of the card cage being used for jumpering instructions If a CDS 73A 021 Card C
81. ormance Verification 0 eee eee eens 55 Appendix E User SeiviCe 25 2223546642055 0346 ened Lenssen nt Genesee ert doeesateeheaed 77 73A 270 i Table of Contents 73A 270 ERA General Safety Summary Review the following safety precautions to avoid injury and prevent damage to this product or any products connected to it Only qualified personnel should perform service procedures While using this product you may need to access other parts of the system Read the General Safety Summary in other system manuals for warnings and cautions related to operating the system Injury Precautions Avoid Electric Overload To avoid electric shock or fire hazard do not apply a voltage to a terminal that is outside the range specified for that terminal Do Not Operate Without To avoid electric shock or fire hazard do not operate this product with covers or Covers panels removed Use Proper Fuse To avoid fire hazard use only the fuse type and rating specified for this product Do Not Operate in To avoid electric shock do not operate this product in wet or damp conditions Wet Damp Conditions Do Not Operate inan To avoid injury or fire hazard do not operate this product in an explosive Explosive Atmosphere atmosphere Product Damage Precautions Provide Proper Ventilation To prevent product overheating provide proper ventilation Do Not Operate With If you suspect there is damage to this product have it inspected by qua
82. parameter is not optional Z is a 1 digit decimal integer from 0 to 7 that specifies the output polarity active or inactive breakpoint and last address bits for the current memory address as shown Zo Last Break Command Value Address point Polaritv Format 0 No No Inactive ZOL No No Active ZIL 2 No Yes Inactive z 2L 3 No Yes Active z 3L 4 Yes No Inactive Z 4L 5 Yes No Active Z 9L 6 Yes Yes Inactive 2z 6L 7 Yes Yes Active Z 7L An active polarity output generates the following polarities TTL Out BNC connector TTL high Pulse Pattern DB25S Output active high TTL high Pulse Pattern DB25S Output active low TTL low VXIbus TTLTRG line open collector low Analog Bipolar Output as programmed by P command Z 15 not optional It must be the last number to precede the L character as Shown under Command Format in the table above A comma or carriage return line feed lt CR gt lt LF gt may be used to separate z and z but 1s not required The L command strobes the time duration data and polarity breakpoint and last address bits as specified by z and z into the present memory address The memory address register is incremented automatically after the data is stored allowing data to be stored in sequential addresses without sending an A Address command before each L command 73A 270 29 OPERATION Example A breakpoint causes the transmission to pause at the end of the time duration for which it is spec
83. r all resolution ranges l to 1600 programmable breakpoints for each channel Available in either Retriggerable or Non Retriggerable modes ASCII characters 3200 24 bit words 1600 words channel Internal VXIbus slot 0 10 MHz ECL clock External front panel connector TTL 1 kHz to 10 MHz 1 25 TTL load equivalents TTL 15 mA source 64 mA sink current 10 MHz TTL active high and TTL active low Channel A and B Transmission In Progress Outputs TTL active high and TTL active low 73A 270 9 SPECIFICATIONS Drive Capability Pulse Pattern Output Sense Transmission In Progress Output Sense Bipolar Analog Outputs Power Up Conditions VXIbus Data Rate Handshake Types Logical Address TTL 5 mA source 32 mA sink current BNC output TTL high when active VXIBus TTLTRG output TTL low when active DB25S TTL active high output TTL high when active DB25S TTL active low output TTL low when active TTL active high output TTL high for transmission in progress TTL active low output TTL low for transmission in progress Levels 50 ohm load Inactive level 8 7V dc Active level 8 7V dc Levels high impedance load Inactive level 17 4V dc Active level 17 4V dc Minimum load 50 ohms Resolution 100 mV with 50 ohm load 200 mV with high impedance DC accuracy 3 of full scale range 10 90 rise fall time less than 60 nanoseconds When power is applied th
84. re set to the same INT LEVEL Also Ifan embedded controller is being used follow the operating manual for displaying the state of the interrupt lines IBWRT 1163C0B IBRD 100 Observe 02 response 4 Check for VXIbus Request True event by performing a serial poll and verify that the response byte is 0x40 decimal 64 i e DIO7 1 IBRSP Observe 40 response TTLOUTAandB This sequence verifies the time base resolution the pulse duration multiplier and the burst mode for the TTL OUT A and B signals Complete all steps in this section for TTL OUT A and then repeat all steps for TTL OUT B Equipment Oscilloscope item 1 i i Counter Timer item 3 50 O BNC Coaxial Cable item 5 Prerequisites All prerequisites listed on page 56 All previous Performance Verification Tests 1 Connect the TTL OUT A or TTL OUT B output to Ch 1 of the oscillo scope 2 V div 1 ms div 1 MQ input impedance 2 Verify the time base resolution with the following steps a Select the channel to be tested IBWRT OS or IBWRT 1S Select TTL OUT A or TTL OUT B b Set the 73A 270 for a 100 ns resolution and then to the beginning of the address space for the first List entry to have a of 100 ns active high duration for the second List entry to have a 100 ns active low duration and to be designated as the Last Address to transmit the list continuous ly and finally to begin transmission of the last channel selected Verify a pulse durat
85. ront panel or the VXIbus TRIGGER command will have no effect if the channel has been programmed for internal triggering by the M command This command programs both Channel A and Channel B and 1s not dependent on which channel ts programmed by the S command The command string 93X selects the VXI bus TRIGGER command from the V XIbus commander of the 73A 270 for Channel A and VXIbus TTLTRG3 for Channel B as the sources for any external trigger programmed for the two channels 73A 270 41 OPERATION The 73A 270 Module will reset to its default condition at power up or for a VXIbus hard or soft reset condition A VXIbus hard reset occurs when another device such as the VXIbus Resource Manager asserts the backplane line SYSRST A VXIbus soft reset occurs when another device such as the 73A 270 s commander sets the Reset bit in the 73A 270 s Control register and the Halt Switch is ON The 73A 270 Module continuously monitors the 5V de 24V de 5 2V de 2V dc and its own internal 20 9V dc power supplies If all power supplies are valid on power up 1 The SYSFAIL VME system failure line will never be set active and the Failed LED will not be lit If any of the supplies fails either at power up or during operation the SYSFAIL line will be set active and the Failed LED will be lit and remain lit 2 The module enters the VXIbus PASSED state ready for normal operation on power up if all power suppl
86. s TTLTRG lines gt bipolar analog output programmable over the full 17 4V output range for both the active and inactive states The card is programmed with simple ASCII character strings consisting of numerical data combined with single letter commands The 73A 270 supports the VXI fast handshake mode and handles all characters on a Direct Memory Access DMA basis VXIbus handshake time is less than 500 nanoseconds per character Front panel BNC connectors are provided for TTL Pulse Pattern Outputs Analog Bipolar Pulse Pattern Outputs and External Trigger Inputs A 25 pin DB25S connector on the front panel provides duplicates of the above BNC signals plus additional Input Output signals for an external clock input a buffered internal clock and a transmission in progress signal See Appendix B for a complete description of these signals eg ns A E A A AA 73A 270 2 DESCRIPTION mT OW A BIPOLAR OUT A ExT TRIG A LS ALS e i gt MOAB fe SIFOLR OUE 8 i z C E ee E UTT T T e e ft poz e j p i FAILED mia 180 A 180 0 HALT STO LUN EXTERNAL CLO Y AN FUSE Figure 270 1 73A 270 Controls and Indicators LOGICAL ADDRESS malta ME BUS INTERLPT Evtl SELECT Av PUSE a 73A 270 DESCRIPTION The following controls and indicators are provided to select and display the functions of the 73A 270 Module s operating environment See Figure 270 1
87. se Pattern Generator Module Appendix D Performance Verification External Clock and This sequence verifies the high and low speed external clock inputs and the Transmission In Progress Transmission In Progress signal inputs on the front panel DB 25 connector Equipment Oscilloscope item 1 meguirements Oscilloscope Probe item 2 50 Q BNC Coaxial Cable two required item 5 Arbitrary Waveform or Pattern Generator clock source item 4 SMB to BNC Adapter Cable item 6 BNC Female to BNC Female item 7 BNC Male to Dual Binding Post Adapter item 8 DB 25 connector with wires soldered to pins 4 amp 5 item 9 Prerequisites All prerequisites listed on page 56 All previous Performance Verification Tests 1 Verify the Fast External Clock 250 kHz to 10 MHz with the following Steps a Turn the mainframe power off and remove the 73A 270 Change the FAST EXTERNAL CLOCK switch from the C1 internal to the C2 external position Return the 73A 270 to the mainframe and turn on the mainframe the power b Connect TTL OUT A to Ch 1 of the oscilloscope 2 V div 100 us 1 MQ2 input impedance c Connect the Arbitrary Waveform Generator AWG ARB OUT to the 73A 270 Fast External Clock pin 5 of S1 front panel DB25 Sth pin up from bottom right and pin 4 4th pin up from bottom right digital ground using the SMB to BNC cable the BNC barrel connector the BNC dual binding post adapter and two short pieces of 26 AWG jumper wir
88. the 500 Hz pulse pattern on TTL OUT B and then stop the pulse pattern IBWRT 1S3ROA0M101L104LOCOB Verify a square wave f Stop the pattern and again using the oscilloscope probe check that Transmission In Progress B active high pin 12 of S1 2nd down from top right is a TTL low level and that Transmission In Progress B active low pin 11 3rd down from top right is a TTL high level IBWRT Q Verify no pattern and pin 12 is high and pin 11 is low g Restart the 500 Hz pulse pattern and check that pin 12 of S1 is now a TTL high level and that pin 11 is a TTL low level IBWRT 1C0B Verify pin 12 is high and pin 11 is low This completes the 73A 270 verification procedure 73A 270 Arbitrary Pulse Pattern Generator Module 19 Appendix D Performance Verification 76 73A 270 Arbitrary Pulse Pattern Generator Module Appendix E User Service This appendix contains service related information that covers the following topics Preventive maintenance User replaceable Parts Preventive Maintenance You should perform inspection and cleaning as preventive maintenance Preventive main tenance when done regularly may prevent malfunction and enhance reliability inspect and clean the module as often as conditions require by following these steps 1 Turn off power and remove the module from the VXlbus mainframe 2 Remove loose dust on the outside of the instrument with a lint free cloth 3 Remove any re
89. tion range a 100 psec pulse may be delayed up to 150 000 seconds 41 hours Each location in memory can be identified as an active or inactive output Any location in the memory can be identified as the last address in order to provide a variable length data list Any number of locations in the memory can be identified as breakpoints for independent triggering of segments of memory Four cight channel multiplexers allow connection of the channel A and B pulse pattern output and external trigger input to any of the eight VXIbus TTLTRG lines There are two bipolar analog output amplifiers for each channel providing a programmable active and inactive level for each channel e Programming Sequence The typical programming sequence is One of two channels is selected with an S Select command All channel specific commands apply to that channel until another channel is selected An R Resolution command is used to specify one of four clock resolutions for the selected channel 73A 270 OPERATION A decimal address in the 1600 word memory is selected with an A Address command Memory data values consisting of a time duration value and polarity a last location identifier and breakpoint location identifiers are loaded into that address with an L List command The selected address automatically increments after each L List command or it may be reprogrammed at any time with the A command The s
90. uit Syntax zQ Purpose The Q command stops transmission of one or both channels Description z isa l digit decimal integer 0 or 1 that specifies the following Z Action 0 Stop transmission on the last selected channel l Stop transmission in both channels simultaneously Examples The command string 0S0Q stops transmission on Channel A but not on Channel B The command string ISOQ stops transmission on Channel B but not on Channel A The command string 0S1Q or ISIQ stops transmission on both channels within 20 nanoseconds of each other a a 73A 270 36 OPERATION Command Syntax Purpose Description Examples R Resolution ZR The R command specifies the time resolution range which will be used by the APPG Module for the selected channel z is a 1 digit decimal integer 0 1 2 or 3 that specifies the following resolution ranges Internal 10 MHz Clock External Clock IN 100 nanosecond 1 f second l microsecond 10 f second 10 microsecond 100 f second 100 microsecond 1000 f second w NY O f frequency of external clock The R command programs the time increment multiplier for the selected channel This multiplier isa time quantity equal to its associated resolution range That is for the 100 nanosecond resolution range the channel programs in 100 nanosecond increments For the microsecond resolution range the channel programs in microsecond increments and so on If an R
91. ular VME is under control of a commander in interrupt level The software the VXIbus system hierarchy A interrupt handler mav or may not be servant mav also be a commander er APPENDIX C tay GQ Soft Reset This state is entered unen the reset bitin the module s Control Register ts set to one 1 by the module s commander Whiie in this state a device 1s inactive interrupts which are pending are unasserted 21l pending bus requests are unasserted and any onboard processor is haited The device s VMEbus slave interface is active in this state however the device is incapable of responding to any commands other than RESET and SYSFAIL INHIBIT In the case of a CDS 73A IBX Card Cage for example a module soft reset occurs when the card cage s 73A 151 Resource Manager IEEE 488 Intertace Module receives a STOP command over the EEE 488 bus that is addressed to the 734 270 The 3A 270 does not reset for a Soft Reset unless the Halt switch is ON When reset the 3A 270 becomes inactive clears all pending interrupts and resets 1ts Operation to the power up state The 3A 270 does not generate VMEbus bus requests and does not have an on board processor SYSFAILL INHIBIT Bit in the Control register ol the module When set to a one 1 by the V XIbus Resource Manager the device is disabled from driving he SYSFAIL line CDS modules are designed so that the Sysfail Inhibit bit will work under ail conditions
92. ule to be the common clock source for a parallel module outputcontiguration each channel provides a TTL level output to the module s front connector indicating transmission is in progress This signal when indicating that transmission is not in progress may be used to indicate the need for another trigger to continue transmission Both TTL active high and TTL active low polarities of the signal are provided for both channels 73A 270 52 APPENDIX B APPENDIX C VXlbus GLOSSARY Certain terms used in this manual have very specific meanings in the context ot a VXIbus System A list of these terms is presented below Commander A YXIbus device that has bus master capability and has VXIbus servants under it in the system hierarchy A commander may be a servant as well on the same module as the hardware interrupt handler Inthe case of CDS instrument modules both the hardware and software interrupt handlers reside on the commander module of a given servant module Fast Handshake Compared to the Normal Transter Logical Address Mode ot the VXIbus the Fast A unique 8 bit number which Handshake Transter Mode reduces identifies cach VXIbus device ina the number of VMEbus data transfer system It defines the device s Al6 cycles bv 50 Upon receipt of a register addresses and indicates the request tor data a fast handshake device s commander servant module is able to return data in less relationship than 20
93. up instructions for the example equipment listed in Table A 1 You may use equipment other than the recommended examples if it meets the requirements listed The order of the test sequences has been chosen to minimize system setup Although not essential it is recommended that you follow the order presented as some tests rely on previously verified parameters Before starting the the test sequence verify that the SLOW EXTERNAL CLOCK is in the OFF position and that the FAST EXTERNAL CLOCK is in the C1 position Also ensure that the INT LEVEL is set to the same level as the Slot 0 Com mander module NOTE All ASCII character string commands enclosed in quotes which are sent to the 73A 270 must be in UPPER CASE You may wish to leave your keyboard in the CAP LOCK mode 73A 270 Arbitrary Pulse Pattern Generator Module 61 Appendix D Performance Verification VXibus Interface This sequence verifies that the 734 270 configures correctly and communicates properly with your system controller Equipment Oscilloscope item 1 Regui EAA ES 50 Q Coaxial Cable item 5 Prerequisites All prerequisites listed on page 56 1 Send the appropriate commands to the Slot O device to get the primary sec ondary GPIB address of the 73A 270 73A 54 1 and VX4790A Place these addresses into the IBCONF configurator for the VX270 VX541 amd VX4790A GPIB device 2 Verify that the 73A 270 responds to setup commands with the following steps a Connect th
94. upt Memory Busy A value of indicates that the data list memory is busy This bit is significant when trying to do in progress data updates when the data being transmitted on the pulse pattern output has several successive 100 nanosecond duration values To update in progress requires a free 100 nanosecond cycle when the memory is not being accessed by the transmitter a duration value of 200 nanoseconds or more is transmitted If an L command is issued while memory is busy previous data sent by an L command will be overwritten Memory Overwrite Interrupt A B A value of indicates that an interrupt has been generated in the selected channel as a result of issuing an L command while memory is busy Proper operation of the 73A 270 Module requires checking the memory busy status if more than ten consecutive 100 nanosecond durations have been previously programmed and are being transmitted Generation of this interrupt indicates improper use of the module and an error condition The Memory Overwrite Interrupt can not be disabled by the I command 73A 270 26 OPERATION Example The state of the four bits indicated by return of the values 00 through 15 1s as follows 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 XMIT in Progress no yes no yes no yes no yes no yes no yes no yes no yes XMIT Comp Memory Interrupt no no yes yes no no yes yes no no ves yes no no yes yes Busy
95. us so that the VXIbus fast handshake protocol can be used by Reset Bit Bit O in the Control register of the module When set toa one 1 by the module s commander or resource manager and the 73A 270 Halt switch is ON the 734 270 is forced into a reset state the module s commander Using tast handshake protocol data can be written and read without checking the Ready bits in the module s Response register Hard Reset This is the state of the module when the SYSRESET line is true While in this state the module is inactive and its Status and Control registers are cleared The SYSFAIL line is driver low and the Failed LED is lit In the case of a CDS 73A IBX Card Cage for example a module hard reset occurs when the card cage is powered up or the Reset switch on the front panel ot the 73A 15 1 Resource Manager IEEE 488 Interface Module is depressed Resource Manager A message based commander located at logical address 0 which provides configuration management services including commander servant mapping address map configuration self test and diagnostic management In CDS systems the Resource Manager function is co located with the VMEbus controller the slot O timing functions and the svstem controller interface Interrupt Handler Servant The module in the VXibus system A YX cus device that may or may that generates the hardware interrupt not have bus master capability that acknowledge tor a partic

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