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Renesas M16C/6NK Laptop User Manual

1. JEITA Package Code RENESAS Code Previous Code MASS Typ P LOFP100 14x14 0 50 PLOPO100KB A 100P6Q A FP 100U FP 100UV 0 69 NOTE 1 DIMENSIONS AND 2 DO NOT INCLUDE MOLD FLASH 2 DIMENSION 3 DOES NOT INCLUDE TRIM OFFSET bp by Reference Dimension in Milimeters Sj Symbol Min Nom Max D 199 140 141 E 199 140 141 Terminal cross section A Alda Ho 158 160 162 He 158 160 162 A 17 Ay 005 01 0 15 Index mark bp 0 15 0 20 0 25 by o18 c 009 0145 020 Ya LI lt 2 m oras n Ne A Wo i e o5 z Aly Sy z x 008 ox O y 008 Z 10 Detail F z 10 L 035 05 0 65 P 10 JEITA Package Code RENESAS Code Previous Code MASS Typ P LOFP128 14x20 0 50 PLOPO128KB A 128P6Q A 0 99 NOTE 1 DIMENSIONS rt AND DO NOT INCLUDE MOLD FLASH bp 2 DIMENSION 3 DOES NOT gt INCLUDE TRIM OFFSET M m NU o Reference Dimension in Milimeters Terminal cross section Symbol Min Nom Max D 199 200 201 E 139 140 141 Az 14 Ho 218 220 222 He 158 160 162 A 17 Index mark al A 005 0 125 02 lt o F i bp 017 022 027 i by o2 a m z c 009 0 145 0 20 i FREUE L a os A is m 8 o
2. 74 173 721171 69 68 67 66 65 P10_7 AN7 KT3 lt P10 6 ANG KI2 lt P10 5 ANS KTT lt lt P10 4 ANA KIO lt P10_3 AN3 P10 2 AN2 lt gt P10 1 AN1 lt lt AVSS P10 0 ANO NOTE O O M16C 6N Group M16C 6NM O glslsislslelalalsielelslelelelelelelalelelelelelale j 5 j BIO ee o J iN e2 ajo Nelles J i J 6 8 1 Overview P12 5 P12 6 P12 7 P5 0 P5 1 P5 2 P5 3 P13 0 P13 1 P13 2 P133 P5 4 P5 5 P5 6 P5 7 CLKOUT P13 4 P13 5 INT6 P13 6 INT7 P13 7 INT8 P6 O CTSO RTSO P6 1 CLKO Pe 2 RXDO SCLO P6 3 TXDO SDAO E o y 29 D N a El P9 7 ADTRG SINA co P9 6 ANEX1 CTXO SOUTA a gt F P9 5 ANEXO CRXO CLK4 lt a o P9 3 DAO TB3IN lt a P9 2 TB2IN SOUTS a gt 2 P9 4 DA1 TB4IN o 1 P9 1 TB1IN SINS lt lt P9 O TBOIN CLK3 gt 5 P14 0 gt 5 BYTE gt CNVSS
3. SDAi X D7 X De X D5 X D4 X D3 X D2 X D1 X DO X D8 ACK NACK A Receive interrupt Transmit interrupt DMA1 request A Transfer to UiRB register Transfer to UiRB register b15 b9 b8 b7 bo b15 b9 b8 b7 DO D7 D6 D5 D4 D3 D1 Uu D8 D7 D6 D5 D4 D3 D2 i Oto2 UiRB register UiRB register This diagram applies to the case where the following condition is met The CKDIR bit in the UiMR register O slave selected Figure 14 24 Transfer to UiRB Register and Interrupt Timing Rev 1 10 Jul01 2005 page 158 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O 14 1 3 1 Detection of Start and Stop Condition Whether a start or a stop condition has been detected is determined A start condition detected interrupt request is generated when the SDAi pin changes state from high to low while the SCLi pin is in the high state A stop condition detected interrupt request is generated when the SDAi pin changes state from low to high while the SCLi pin is in the high state Figure 14 25 shows the detection of start and stop condition Because the start and stop condition detected interrupts share the interrupt control register and vector check the BBS bit in the UiSMR register to dete
4. t Fass ndino eseug n ojsibou will peoj y J freisibeu VL 1 4066 al ind eqsued TV WIL 10 feuis jojju02 peojay ona UNIO JOJUOg indino seyd N vV Zy Ly saw GG O u 10 eubis 196611 ueis Jowl au peeq 196611 1966111 apo 1 w 1 zg Jou ss o u OLANI Ja siBay peojay 2g aut 0 jeuBis IUM SOANI INN ug 1s nb y 1dnueju SL O u 3S38 eg euin Jayuno9 call mo uapup zg JEW 38 O0ANI o eubis aM Aouanbai4 uoyesauasyy qA 0ANI 0 jdnueiu 19s oi YNO Ud aq 0 INEA G4 0 u Ja sib9y zglol RIAM 131 NESAS Figure 13 1 Three Phase Motor Control Timer Function Block Diagram Rev 1 10 Jul 01 2005 page 118 of 318 REJO9B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Three Phase Motor Control Timer Function Three Phase PWM Control Register 0 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset INVCO 01C8h 00h 0 The ICTB2 counter is incremented by one on the Interrupt Enable Output rising edge of the timer A1 reload control signal Polarity Select Bit P 1 The ICTB2 counter is incremented by one on the falling edge of the timer A1 reload control signal 2 0 ICTB2 counter is incremented by o
5. P10 4to P10 7 inside dotted line Data bus _ Port latch included Sisi a Pull up selection D A output enabled Direction register t lt Data bus Port latch 4 Input to respective peripheral functions lt P9 3 P9 4 Analog output D A output enabled Pull up selection Direction register t lt O Data bus Port latch n Pull up selection Analog input Direction register Output o Data bus Port latch adip m Input to respective peripheral functions lt 4 Analog input Qc Symbolizes a parasitic diode Make sure the input voltage on each port will not exceed VCC Figure19 4 1 O Ports 4 Rev 1 10 Jul01 2005 page 231 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 Programmable l O Ports Pull up selection Direction register f q Data bus Port latch i Pull up selection Direction register 4 q oe Output Data b
6. CANO Message Box 15 Data Field CANO Message Box 15 Time Stamp 0161h 0163h CANO Global Mask Register 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h CANO Local Mask A Register COLMAR CANO Local Mask B Register COLMBR Address otaon 0141h ota2n 0143h _ EL 0147h 0148h 0149h 014Ah ot4Bh _014Ch ot5th 0152h 0153h _ 0154h 0157h 0158h 0159h ot5Ah ot5Bh 015Ch_ ot6th O163h ot64n 0167h O168h ot69h 016Ah ot6Dh Ot6Eh Ot6Fh Ot70h X Undefined NOTE 1 The blank areas are reserved and cannot be accessed by users Rev 1 10 Jul01 2005 page 18 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 7 SFR Information 7 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh
7. esseeeeen 196 A A A 198 17 CRC Calculation ini lidia 200 18 CAN MOS cst tec ttn ia 202 18 1 CAN Module Related Registers oooococnocccinoccconococononcnnonncconnncn nono ncnano ca nann nn rana ra enne enne nnne nnns innen nnns 203 18 11 CAN Message BOX dm 203 18 1 2 Acceptance Mask Registers ooooocccinocccnocccconoccconocononocononnnnnnnnnnnnnn o nn nennen enne enn enne n nnne nnne 203 18 1 3 CAN SER Registers 2 eH aaa 203 18 2 CANI M6eSSage BOX edet li rar tando atada LB gan dtu aged erat utu pda cdam 204 18 3 Acceptance Mask ASUSTES scott lat n 206 18 4 GAN SE R BegiSterS ceo deett ee ro tte E neret entente dete dri e deep ots te UN a addu eek 207 18 5 Operational MOCSS ibarra 213 18 5 1 CAN Reset Initialization Mode sssaaa a ai aaia a a nnns aa aaa nnns 213 18 5 2 CAN Operation Mode rn rte a aaa da 214 18 5 3 CAN Sleep Mode comisi n is 214 18 5 4 CAN Interface Sleep MOEG aaa nnn ea aaaea aieeaa ani 214 185 5 Bus Off Oller ecos a e aaa a Ea Eaa 215 18 6 Configuration CAN Module System Clock 0ooooccccinccccnonccconocaconancnonoca nana corno nn nano conan n nc nan canann rn rann cnn 216 18 7 Bit Timing GonfIglEration s dese UA uade 216 18 8 BIETalO utili eth nennt iei initial ee etes 217 18 9 Acceptance Filtering Function and Masking Function e 218 18 10 Acceptance Filter Support Unit ASU sssssssssssssseeeeeeeneee nennen nennen enne 219 18 11 Basic CAN MOQ C teas Sat ort acide e
8. 1 Referenced to VCC AVCC VREF 3 3 to 5 5V VSS AVSS OV 40 to 85 C unless otherwise specified 2 This applies when using one D A converter with the DAI register i 0 1 for the unused D A converter set to 00h The resistor ladder of the A D converter is not included Also the current Ivrer always flows even though VREF may have been set to be unconnected by the ADCON1 register Rev 1 10 Jul01 2005 page 274 of 318 REJO9B0124 0110 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Electric Characteristics Table 21 8 Flash Memory Version Electrical Characteristics Parameter Word Program Time Standard Typ Block Erase Time Erase All Unlocked Blocks Time Lock Bit Program Time Flash Memory Circuit Stabilization Wait Time NOTES 1 Referenced to VCC 4 5 to 5 5V 3 0 to 3 6V Topr 0 to 60 C unless otherwise specified 2 n denotes the number of blocks to erase Table 21 9 Flash Memory Version Program Erase Voltage and Read Operation Voltage Characteristics at Topr 0 to 60 C Flash Program Erase Voltage Flash Read Operation Voltage VCC 3 3 0 3V or 5 0 0 5V VCC 3 0 to 5 5V Table 21 10 Power Supply Circuit Timing Characteristics Parameter Time for Internal Power Supply Stabilization During Powering On VCC 3 0 to 5 5V Measuring
9. This diagram applies to the case where the bits in the SiC register are set as follows SMi2 0 SOUTi output SMi5 0 LSB first Serial transmit reception starts SMi6 0 external clock NOTES 1 If the SMi6 bit 1 internal clock or if the SMi2 bit 1 SOUTi output disabled this output goes to the high impedance state 2 SOUTi can only be initialized when input on the CLKi pin is in the high state if the SMi4 bit in the SiC register 0 transmit data output at the falling edge of the transfer clock or in the low state if the SMi4 bit 1 transmit data output at the rising edge of the transfer clock Figure 14 41 SOUTi s Initial Value Setting Rev 1 10 Jul01 2005 page 180 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 A D Converter 15 A D Converter The microcomputer contains one A D converter circuit based on 10 bit successive approximation method configured with a capacitive coupling amplifier The analog inputs share the pins with P10_0 to P10 7 P9 5 P9 6 PO Oto PO 7 and P2 Oto P2 7 Similarly ADTRG input shares the pin with P9 7 Therefore when using these inputs make sure the corresponding port direction bits are set to 0 input mode When not using the A D converter set the VCUT bit to 0 VREF unconnected so that no current will flow from the VREF pin into the resisto
10. Clock Synchronous Disabled Bit Enabled Disabled SCL Wait Output Bit Enabled Disabl SDA Output Stop Bit ET UARTI Initialization Disabled Bit Enabled SCL Wait Output 0 Transfer clock Bit 2 1 L output SDA Output Disable 0 Enabled Bit 1 Disabled high impedance Nothing is assigned When write set to O When read its content is indeterminate UARTi Special Mode Register 3 i 0 to 2 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset UOSMRS to U2SMR3 01EDh 01F 1h 01F5h 000X0X0Xb Nothing is assigned When write set to 0 When read its content is indeterminate 0 Without clock delay 1 With clock delay Nothing is assigned When write set to 0 When read its content is indeterminate Clock Output Select 0 CLKi is CMOS output Bit 1 CLKi is N channel open drain output Nothing is assigned When write set to O When read its content is indeterminate Clock Phase Set Bit 5 0 Without delay 1 to 2 cycle s of UIBRG count source T 2 to 3 cycles of UIBRG count source SDAi Digital Delay 3 to 4 cycles of UIBRG count source Setup Bit 1 2 4 to 5 cycles of UIBRG count source 5 to 6 cycles of UIBRG count source 6 to 7 cycles of UIBRG count source 7 to 8 cycles of UIBRG count source 1 The DL2 to DLO bits are used to generate a delay in SDAi output by digital means during 12C mode In other than 12C mode set these bi
11. DMA Start Up Data transfer is initiated each time a DMA request is generated when the The DMAE bit in the DMAiCON register 1 enabled DMA Shutdown Single Transfer When the DMAE bit is set to 0 disabled After the DMAi transfer counter underflows Repeat Transfer When the DMAE bit is set to 0 disabled Reload Timing for Forward Address Pointer and Transfer Counter i20 1 NOTES When a data transfer is started after setting the DMAE bit to 1 enabled the forward address pointer is reloaded with the value of the SARi or the DARi pointer whichever is specified to be in the forward direction and the DMAi transfer counter is reloaded with the value of the DMAi transfer counter reload register 1 DMA transfer is not effective to any interrupt DMA transfer is affected neither by the I flag nor by the interrupt control register 2 The selectable causes of DMA requests differ with each channel 3 Make sure that no DMAC related registers addresses 0020h to 003Fh are accessed by the DMAC Rev 1 10 Jul 01 2005 page 83 of 318 REJO9B0124 0110 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM DMAO Request Cause Select Register b7 b6 b5 b4 b3 b2 bi bO 11 DMAC Symbol Address After Reset DMOSL 03B8h 00h Bit Symbol Bit Name Function Select Bit Request Bit DMA Req
12. Figure 15 5 ADCONO Register and ADCON1 Register in Repeat Mode Rev 1 10 Jul01 2005 page 188 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 1 3 Single Sweep Mode In single sweep mode analog voltage that is applied to selected pins is converted one by one to a digital code Table 15 4 lists the specifications of single sweep mode Figure 15 6 shows the ADCONO and ADCON1 registers in single sweep mode Table 15 4 Single Sweep Mode Specifications Specification Function The SCAN to SCANO bits in the ADCON1 register and the ADGSEL1 to ADGSELO bits in the ADCON register select pins Analog voltage applied to this pins is converted one by one to a digital code A D Conversion Start Condition When the TRG bit in the ADCONO register is 0 software trigger The ADST bit in the ADCONO register is set to 1 A D conversion starts When the TRG bit is 1 ADTRG trigger Input on the ADTRG pin changes state from high to low after the ADST bit is set to 1 A D conversion starts A D Conversion Stop Condition Completion of A D conversion If a software trigger is selected the ADST bit is set to 0 A D conversion halted e Set the ADST bit to 0 Interrupt Request Generation Timing Completion of A D conversion Analog Input Pin Select from ANO to AN1 2 pins
13. Address O2COh O2Cih O2C2h O2C3h EN O2C7h O2C8h O2Coh o2CAn 02CBh_ O2CCh o2Dth o2D3h_ oane O2D7h O2D8h o2Doh o2DAn o2DBh one 02Eth o2E2h o2E3h O2E4n O2E7h O2E8h o2Eon o2EBh o2ECh o2Fih o2Fen o2Fsh Eo 02F7h o2F8n o2ron 02FAN O2FBh Ka o2FFh Rev 1 10 Jul01 2005 page 24 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 13 SFR Information 13 Symbol AfterReset 0300h 0301h 0302n CAN1 Message Box 10 Identifier DLC 0304h 0305h 0306h 0307h 0308h osoon Message Box 10 Data Field 030Bh 030Ch 030Dh 030Eh M B i 030Fh essage Box 10 Time Stamp 0310h 0311h ETS Message Box 11 Identifier DLC 0314h 0315h 0316h 0317h 0318h 0319h M 031Ah essage Box 11 Data Field 031Bh 031Ch 031Dh 031Eh p 031Fh Message Box 11 Time Stamp 0320h 0321h 0322h M 0323h essage Box 12 Identifier DLC 0324h 0325h 0326h 0327h 0328h 0329h 032Ah Message Box 12 Data Field 032Bh 032Ch 032Dh 032Eh e
14. CANO Message Box 2 Time Stamp 008Fh 0090h e e co pri 2 CANO Message Box 3 Identifier DLC CANO Message Box 3 Data Field CANO Message Box 3 Time Stamp o Identifier DLC oo oo gt gt fo aha Co CANO Message Box 4 o o gt T E oo oo 2 OOo o o gt M gt olo oo gt gt a a gt CANO Message Box 4 Data Field oloojo ooo 22 Qu 2 2 o oo gt gt mo CANO Message Box 4 Time Stamp o ojojo oo w w gt o m sm o o UJ N E CANO Message Box 5 Identifier DLC o olojojojo ojojojo w Wy UJ W UJ NI BY 2 2 3 2 2 o ojo o EE BE CANO Message Box 5 Data Field o o UJ UJ zx o O UJ O ez o o UD s 3 OOBEh 00BFh CANO Message Box 5 Time Stamp Symbol CANO Message Box 6 Identifier DLC B 2 CANO Message Box 6 Data Field CANO Message Box 6 Time Stamp 00CFh 00DOh o o O zx e o N 2 CANO Message Box 7 Identifier DLC o ojojojojo ojojojo OJUJOJO O NI D G1 BY C2 z 2x o o g zx CANO Message Box 7 Data Field ojojo ojojo oojoo molo U2 o l 2 5 5 y CANO Message Box 7 Time Stamp ojo ojojojo mme S3 ojo o m m Co ho 2 CANO Message Box 8 Identifier DLC e e m A E ojo ojo m m ojo a hs y CANO Message Box 8 Data Field o ojojojojo
15. Nothing is assigned When write set to 0 To rewrite the interrupt control registers do so at a point that does not generate the interrupt request for that register For details refer to 22 7 Interrupt This bit can only be reset by writing 0 Do not write 1 If the IFSR10 to IFSR15 bits in the IFSR1 register and the IFSR23 to IFSR25 bits in the IFSR2 register are 1 both edges set the POL bit in the INTOIC to INT8IC register to O falling edge INT6IC to INT8IC registers are in the 128 pin version Set the POL bit in the S3IC register to 0 falling edge when the IFSROO bit in the IFSRO register 1 and the IFSR16 bit in the IFSR1 register 0 SI O3 selected Set the POL bit in the S4IC register to 0 falling edge when the IFSRO3 bit in the IFSRO register 1 and the IFSR17 bit in the IFSR1 register 0 SI O4 selected Use the IFSROG bit in the IFSRO register and the IFSR17 bit in the IFSR1 register to select Use the IFSROO bit in the IFSRO register and the IFSR16 bit in the IFSR1 register to select Use the IFSR20 bit in the IFSR2 register to select The INT7IC register is only in the 128 pin version In the 100 pin version set the IFSR20 bit to 0 Timer A2 Use the IFSR21 bit in the IFSR2 register to select The INT6IC register is only in the 128 pin version In the 100 pin version set the IFSR21 bit to 0 Timer A3 10 Use the IFSR22 bit in the IFSR2 register to select The INT8IC regis
16. Sub Clock Oscillating Sub Clock Turned Off No Divided Divided Divided Divided No Divided Divided Divided Divi Division by 2 by 4 by 8 Division by 2 by 4 by 8 No Division ivided by 2 Setting CM04 0 Sub clock turned off CM04 1 Sub clock oscillating CM06 0 CM17 0 CM16 0 CPU clock no division mode CM06 0 CM17 0 CM16 1 CPU clock division by 2 mode CM06 0 CM17 1 CM16 0 CPU clock division by 4 mode CM06 0 CM17 1 CM16 1 CPU clock division by 16 mode CM06 1 CPU clock division by 8 mode CM07 0 Main clock PLL clock or on chip oscillator clock selected CM07 21 Sub clock selected CM05 0 Main clock oscillating CMO05 1 Main clock turned off PLCO7 0 CM11 0 Main clock selected ivided by 4 ivided by 8 Divided by 16 PLCO7 1 CM11 1 PLL clock selected CM21 0 Main clock or PLL clock selected Sub Clock Turned Off Sub Clock Oscillating 9 Rev 1 10 Jul01 2005 page 56 of 318 REJO9B No Division ivided by 2 ivided by 4 D D D D D D ivided by 8 Divided by 16 setting method See right table 34 NE SAS 0124 0110 CM21 1 On chip oscillator clock selected CM10 1 Transition to stop mode 1 7 WAIT instruction Transition to wait mode Hardware interrupt Exit stop mod
17. 22 14 Programmable I O Ports If a low level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register 1 three phase output forcible cutoff by input on NMI pin enabled the P7_2 to P7_5 P8_0 and P8_1 pins go to a high impedance state Setting the SM32 bit in the S3C register to 1 causes the P9_2 pin to go to a high impedance state Setting the SM42 bit in the S4C register to 1 causes the P9 6 pin to go to a high impedance state Setting the SM52 bit in the S5C register to 1 causes the P11_2 pin to go to a high impedance state Setting the SM62 bit in the S6C register to 1 causes the P11 6 pin to go to a high impedance state NOTES 1 When using SI O4 set the SM43 bit in the S4C register to 1 SOUTA output CLK4 function and the port direction bit corresponding for SOUTA pin to 0 input mode 2 The S5C and S6C registers are only in the 128 pin version When using these registers set these registers after setting the PU37 bit in the PUR3 registger to 1 Pins P11 to P14 are usable The input threshold voltage of pins differs between programmable I O ports and peripheral functions Therefore if any pin is shared by a programmable l O port and a peripheral function and the input level at this pin is outside the range of recommended operating conditions VIH and VIL neither high nor low the input level may be determined differently depending on which side th
18. CANO Message Box 5 Data Field OOBEh OOBFh X Undefined CANO Message Box 5 Address 0080h oo8in oo82h 0083h onser 0087h 0088h 0089h 008Ah oo8Bh 008Ch_ oo9th oo92n 0093h E 0097h 0098h 0099h 009Ah oooBh Km 00Ath ooA2n 00ASh 00A4h 00A7h O0ASh OoAon Km 00Bth ooBen ooB3h ioo 0087h ooB8h ooBon ooBAh ooBBh ses ooBFh Time Stamp Rev 1 10 Jul 01 2005 page 15 of 318 REJO9B0124 0110 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 4 SFR Information 4 Address 00COh 00C1h 00C2h s ANO M 00C3h CANO Message Box 6 Identifier DLC 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h CANO M B Data Fiel O0CAh O Message Box 6 Data Field 00CBh 00CCh 00CDh OOCEh AN j O0CFh CANO Message Box 6 Time Stamp 00DOh 00D1h 00D2h a ANO M 1 00D3h CANO Message Box 7 Identifier DLC 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h O0DAh CANO Message Box 7 Data Field OODBh 00DCh 00DDh OODEh O0DFh CANO Message Box 7 Time Stamp OOEOh 00E1h 00E2h T 00E3h CANO Message Box 8 Identifier DLC 00E4h OOE5h OOE6h 00E7h 00E8h O0E9h CANO Message Box 8 Data Field OOEEh p OOEFh CANO Message B
19. Count Start Condition The TAIS bit in the TABSR register 1 start counting and one of the following triggers occurs External trigger input from the TAiIN pin Timer B2 overflow or underflow Timer Aj overflow or underflow Timer Ak overflow or underflow The TAiOS bit in the ONSF register is set to 1 timer starts Count Stop Condition When the counter is reloaded after reaching 0000h e TAIS bit is set to 0 stop counting Interrupt Request Generation Timing When the counter reaches 0000h TAiIN Pin Function I O port or trigger input TAiOUT Pin Function I O port or pulse output Read from Timer An indeterminate value is read by reading the TAi register Write to Timer When not counting and until the 1st count source is input after counting start Value written to the TAi register is written to both reload register and counter When counting after 1st count source input Value written to the TAi register is written to only reload register Transferred to counter when reloaded next Select Function i Oto4 j i 1 exceptj 4 ifi 2 O k i 1 except k 0ifi 4 Pulse output function The timer outputs a low when not counting and a high when counting Rev 1 10 Jul01 2005 page 104 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 Timers
20. Figure 18 21 Timing of Transmit Sequence 1 If the TrmReq bit in the CIMCTLj register i 0 1 j O to 15 is set to 1 Transmission slot in the bus idle state the TrmActive bit in the CiIMCTLj register and the TrmState bit in the CISTR register are set to 1 Transmitting Transmitter and CAN module starts the transmission 2 If the arbitration is lost after the CAN module starts the transmission the TrmActive and TrmState bits are set to 0 3 If the transmission has been successful without lost in arbitration the SentData bit in the CIMCTLj register is set to 1 Transmission is successfully completed and TrmActive bit is set to 0 Waiting for bus idle or completion of arbitration And when the interrupt enable bits in the CiICR register 1 Interrupt enabled CANi successful transmission interrupt request is generated and the MBOX the slot number which transmitted the message and TrmSucc bit in the CiSTR register are changed 4 When starting the next transmission set the SentData and TrmReq bits to 0 And set the TrmReq bit to 1 after checking that the SentData and TrmReq bits are set to 0 Rev 1 10 Jul01 2005 page 224 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 18 CAN Module 18 16 CAN Interrupt The CAN module provides the following CAN interrupts e CANi Suc
21. Reference M16C 60 M16C 20 Series Software Manual CANO 1 Wake up 9 4 to 7 0004h to 0007h CANO Successful Reception 8 to 11 0008h to 000Bh CANO Successful Transmission 12 to 15 000Ch to 000Fh 18 CAN Module INT3 16 to 19 0010h to 0013h 9 6 INT Interrupt Timer B5 SI O5 2 20 to 23 0014h to 0017h Timer B4 UART1 Bus Collision Detection 24 to 27 0018h to 001Bh Timer B3 UARTO Bus Collision Detection 9 28 to 31 001Ch to 001Fh 12 Timers 14 Serial I O CAN1 Successful Reception SIO4 INT5 32 to 35 0020h to 0023h CAN1 Successful Transmission S103 INT4 9 36 to 39 0024h to 0027h OO N OD O17 A Co Po 18 CAN Module 14 Serial I O 9 6 INT Interrupt UART2 Bus Collision Detection 9 40 to 43 0028h to 002Bh 14 Serial I O DMAO 44 to 47 002Ch to 002Fh DMA1 48 to 51 0030h to 0033h 11 DMAC CANO 1 Error t 452 to 455 0034h to 0037h 18 CAN Module A D Key Input M1 15 A D Convertor 9 8 Key Input Interrupt UART2 Transmission NACK2 60 to 63 003Ch to 003Fh UART2 Reception ACK2 64 to 67 0040h to 0043h UARTO Transmission NACKO 9 68 to 71 0044h to 0047h UARTO Reception ACKO 72 to 75 0048h to 004Bh UART1 Transmission NACK1 9 76 to 79 004Ch to 004Fh UART1 Reception
22. Reserved Bit Set to 1 Reserved Bit Set to 0 PLL Off Operation Enable Bit 3 a PLL zi 1 Write to this register after setting the PRCO bit in the PRCR register to 1 write enable 2 This bit can only be modified when the PLCO7 bit 0 PLL turned off The value once written to this bit cannot be modified 3 Before setting this bit to 1 set the CMO7 bit in the CMO register to 0 main clock set the CM17 to CM16 bits in the CM1 register to 00b main clock undivided mode and set the CMO6 bit in the CMO register to 0 CM16 and CM17 bits enable Figure 7 8 PLCO Register Rev 1 10 Jul01 2005 page 42 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Clock Generating Circuit The following describes the clocks generated by the clock generating circuit 7 1 1 Main Clock The main clock is generated by the main clock oscillation circuit This clock is used as the clock source for the CPU and peripheral function clocks The main clock oscillator circuit is configured by connecting a resonator between the XIN and XOUT pins The main clock oscillator circuit contains a feedback resistor which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip The main clock oscillator circuit may also be configured by feeding an externally gene
23. When operating in repeat mode or repeat sweep mode 0 or 1 Use the main clock for CPU clock directly without dividing it If A D conversion is forcibly terminated while in progress by setting the ADST bit in the ADCONO register to 0 A D conversion halted the conversion result of the A D converter is indeterminate The contents of ADi registers irrelevant to A D conversion may also become indeterminate If while A D conversion is underway the ADST bit is set to 0 in a program ignore the values of all ADi registers When setting the ADST bit to 0 in single sweep mode during A D conversion and A D conversion is aborted disable the interrupt before setting the ADST bit to 0 Rev 1 10 Jul01 2005 page 301 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 13 CAN Module 22 13 1 Reading CiSTR Register i 0 1 The CAN module on the M16C 6N Group M16C 6NK M16C 6NM updates the status of the CiSTR register in a certain period When the CPU and the CAN module access to the CiSTR register at the same time the CPU has the access priority the access from the CAN module is disabled Consequently when the updating period of the CAN module matches the access period from the CPU the status of the CAN module cannot be updated See Figure 22 5 When Updating Period of CAN Module Matches Access Perio
24. With no load applied LOWPOWER With no load applied LOW Output Voltage PO 0 to PO 7 P1 0 to P1 7 P2 0 to P2 P3 0 to P3 7 P4 0 to P4 7 P5 0 to P5 P6 0 to P6 7 P7 0 to P7 7 P8 0 to P8 P8 6 P8 7 P9 0 to P9 7 P10 0 to P10 P11 0toP11 7 P12 0toP12 7 P13 0to P13 P14 0 P14 1 lo 5mA LOW Output Voltage PO 0 to PO 7 P1 0 to P1 7 P2 0 to P2 P3 0 to P3 7 P4 0 to P4 7 P5 0 to P5 P6 0 to P6 7 P7 0 to P7 7 P8 0 to P8 P8 6 P8 7 P9 0 to P9 7 P10 0 to P10 P11 0toP11 7 P12 0toP12 7 P13 Oto P13 P14 0 P14 1 lo 2000A LOW Output Voltage XOUT HIGHPOWER lo 1mA LOWPOWER lo 0 5mA LOW Output Voltage XCOUT HIGHPOWER With no load applied LOWPOWER With no load applied Hysteresis TAOIN to TA4IN TBOIN to TBSIN INTO to INT8 NMI ADTRG CTSO to CTS2 SCLO to SCL2 SDAO to SDA2 CLKO to CLK6 TAOOUT to TA4OUT KIO to KI3 RXDO to RXD2 SIN3 to SIN6 Hysteresis RESET Hysteresis XIN HIGH Input Current PO 0 to PO 7 P1_0 to P1 7 P2_0 to P2 P3 0 to P3 7 P4 0 to P4 7 P5 O0 to P5 P6 0 to P6 7 P7 0 to P7 7 P8 O0 to P8 P9 0to P9 7 P10 Oto P10 7 P11 OtoP11 P12 0to P12 7 P13 0to P13 7 P14 0 P14 XIN RESET CNVSS BYTE LOW Input Current PO 0 to PO 7 P1 0 to P1 7 P2 0 to P2 P3 0 to P3 7 P4 0 to P4 7 P5_0 to P5 P6 0 to P6 7 P7 0 to P7 7 P8 O0 to P8 P9 0to P9 7 P10
25. X On chip On chip oscillator clock oscillator Oscillation stop re oscillation detection circuit CM10 1 stop mode PLL frequency synthesizer re clock Ms Main clock 1 Main clock oscillation circuit 0 OM CMO5 CM21 1 Soni 0 A moO CANO r 9 o Divider By CCLKO 1 and 2 A O CAN1 Oo By CCLK4 5 and 6 Divider o Peko f2 PCLKO 0 p o f32 gt PCLKO 1 PCLKO 0 ISI pciki 1 psi a gt PCLK1 0 f8SIO p gt 250 b jc jd Divider CM07 0 CPU clock M CO M X CM07 1 BCLK WAIT instruction RESET Software reset Interrupt request level judgment output PMOO PMO1 Bits in PMO register CMO0 CMO01 CM02 CM04 CM05 CM06 CMO7 Bits in CMO register CM10 CM11 CM16 CM17 Bits in CM1 register PCLKO PCLK1 Bits in PCLKR register CM21 CM27 Bits in CM2 register CCLKO to CCLK2 CCLK4 to CCLK6 Bits in CCLKR register Oscillation stop re oscillation detection circuit Pulse generating circuit for clock edge detection and charge discharge control Charge discharge circuit Main clock Programmable counter Phase comparator Main cloc
26. transmitting If it is rewritten an indeterminate data will be transmitted Rev 1 10 Jul01 2005 page 222 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 18 CAN Module 18 15 1 Reception Figure 18 20 shows the behavior of the module when receiving two consecutive CAN messages that fit into the slot of the shown CiMCTLj register i 0 1 j O to 15 and leads to losing overwriting of the first message CANbus RecReq bit InvalData bit NewData bit CiMCTLj register MsgLost bit CANI Successful Reception Interrupt RecState bit RecSucc bit CiSTR register MBOX bit Receive slot No 0 1 j2010 15 Figure 18 20 Timing of Receive Data Frame Sequence 1 On monitoring a SOF on the CAN bus the RecState bit in the CiSTR register becomes 1 CAN module is receiver immediately given the module has no transmission pending 2 After successful reception of the message the NewData bit in the CiMCTLj register of the receiving slot becomes 1 stored new data in slot The InvalData bit in the CIMCTLj register becomes 1 message is being updated at the same time and the InvalData bit becomes 0 message is valid again after the complete message was transferred t
27. z P8 7 XCIN P14 1 lt p P8_1 TA4IN U a VSS XIN S VCC1 E P8 5 NMI s S P8_4 INT2 ZP lt gt P8_3 INT1 lt lt P8 2 INTO lt gt XOUT 5 SIN4 lt lt RESET 3 P7 7 TASIN CRX1 5S P8 6 XCOUT o P8 O TA4OUT U I 1 P7 1 and P9 1 are N channel open drain pins Figure 1 4 Pin Configuration Top View 2 Rev 1 10 Jul 01 2005 page 7 of 318 REJO9B0124 0110 131 NESAS P7 6 TASOUT CTX1 lt gt 3 SOUT4 lt gt 8 P7_5 TA2IN WI P7 A TA2OUT W CLK4 lt gt P7 3 CTS2 RTSZ TAMN V lt lt 1 P7 1 RXD2 SCL2 TAOIN TBSIN F P7 2 CLK2 TA1OUTAV t 8 P7 0 TXD2 SDA2 TAOOUT 8 P6 7 TXD1 SDA1 gt 5 P6 6 RXD1 SCL1 El P6_4 CTS1 RTS1 CTSO CLKS1 P6_5 CLK1 4 vss Package PLQP0128KB A Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 1 6 Pin Description Tables 1 4 and 1 5 list the pin descriptions 1 Overview Table 1 4 Pin Description 100 pin and 128 pin Versions 1 Signal Name Power supply input Pin Name VCC1 VCC2 VSS WOTwe BDesplop Apply 3 0 to 5 5V to the VCC1 and VCC2 pins and OV to the VSS pin The VCC apply condition is that VCC2 VCC1 Analog power supply input AVCC AVSS Applies the power supply for the A D converter Connect t
28. 0357h 0358h 0359h 035Ah 035Bh_ E o36th_ 0363h 0364h 0367h 0368h 0369h 036Ah_ O36Dh 036Eh oseFh O370h X Undefined NOTE 1 The blank areas are reserved and cannot be accessed by users Rev 1 10 Jul01 2005 page 26 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 15 SFR Information 15 Count Start Flag 00h Clock Prescaler Reset Flag OXXXXXXXb One Shot Start Flag 00h Trigger Select Register 00h Up Down Flag 00h 1 Timer AO Register AE Timer A1 Register AE Timer A2 Register a Timer A3 Register EN Timer A4 Register E Timer BO Register E Timer B1 Register E 03941 Timer B2 Register oh XXh Timer AO Mode Register 00h Timer A1 Mode Register 00h Timer A2 Mode Register 00h Timer A3 Mode Register 00h Timer A4 Mode Register 00h Timer BO Mode Register 00XX0000b Timer B1 Mode Register 00XX0000b Timer B2 Mode Register 00XX0000b Timer B2 Special Mode Register XXXXXX00b UARTO Transmit Receive Mode Register 00h UARTO Bit Rate Generator XXh UARTO Transmit Buffer Register E UARTO Transmit Receive Control Register 0 00001000b UARTO Transmit Receive Control Register
29. 1 MSB first CLKi TDi NA STA D7 X DeX D5 X D4X pa X D2X Di X Do X P Y SP RXDi X X sT D7X DeX D5X D4X D3 X D2X p1 Y DOX P Y se i Oto2 ST Start bit P Parity bit SP Stop bit NOTE 1 This applies to the case where the register bits are set as follows e CKPOL bit in VICO register 0 transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock e UiLCH bit in UiC1 register O no reverse e STPS bit in UIMR register 0 1 stop bit e PRYE bit in UIMR register 1 parity enabled Figure 14 19 Transfer Format Rev 1 10 Jul01 2005 page 151 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O 14 1 2 4 Serial Data Logic Switching Function The data written to the UiTB register has its logic reversed before being transmitted Similarly the received data has its logic reversed when read from the UiRB register Figure 14 20 shows serial data logic 1 When the UiLCH bit in the UiC1 register 0 no reverse Transfer clock b mel ae ST Do X_D1 X pei D3 X D4 os De X D7 X P Y sP 2 When the UiLCH bit 2 1 reverse Transfer clock pal eO A Vsr Doy DT A bs f D4 y bs J be 07 EY sP i Oto2 ST Start bit P Parity bit SP Stop bit NOTE 1 T
30. Built in feedback resistor Built in feedback resistor Externally derived clock CCIN CCOUT vcc L L e EE NOTE 1 Place a damping resistor if required The resistance will vary depending on the oscillator and the oscillation drive capacity setting Use the value recommended by each oscillator the oscillator manufacturer When the oscillation drive capacity is set to low check that oscillation is stable Also place a feedback resistor between XCIN and XCOUT if the oscillator manufacturer recommends placing the resistor externally Figure 7 10 Examples of Sub Clock Connection Circuit Rev 1 10 Jul01 2005 page 44 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Clock Generating Circuit 7 1 3 On chip Oscillator Clock This clock approximately 1 MHz is supplied by a on chip oscillator This clock is used as the clock source for the CPU and peripheral function clocks In addition if the PM22 bit in the PM2 register is 1 on chip oscillator clock for the watchdog timer count source this clock is used as the count source for the watchdog timer refer to 10 1 Count Source Protective Mode After reset the on chip oscillator is turned off It is turned on by setting the CM21 bit in the CM2 register to 1 on chip oscillator clock and is used as the clock source for the CPU and peripheral function cloc
31. If the lock bit is set to 1 in 2 above that block cannot be used When a lock bit program operation is executed 1 Execute the clear status register command and set the SR4 bit to 0 2 Set the FMRO2 bit to 1 3 Execute the block erase command to erase the block where the error occurred 4 Execute the lock bit program command again NOTE If similar error occurs that block cannot be used Full status check completed FMRO06 FMRO7 Bits in FMRO register NOTE 1 When either FMRO6 or FMRO 7 bit is set to 1 terminated by error the program block erase erase all unlocked block lock bit program and read lock bit status commands cannot be accepted Execute the clear status register command before each command Figure 20 12 Full Status Check and Handling Procedure for Each Error Rev 1 10 Jul01 2005 page 258 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Flash Memory Version 20 4 Standard Serial I O Mode In standard serial I O mode the serial programmer supporting the M16C 6N Group M16C 6NK M16C 6NM can be used to rewrite the flash memory user ROM area in the microcomputer mounted on a board For more information about the serial programmer contact your serial programmer manufacturer Refer to the user s manual included with your serial programmer for instructions Table 20 7 lists pin
32. NOTE 1 When any INT instruction in software numbers 32 to 63 has been executed this is the SP indicated by the U flag Otherwise it is the ISP 1 SP contains even number 2 SP contains odd number Address Sequence in which order Address Sequence in which order registers are saved registers are saved SP 2 Saved simultaneously all 16 bits SP Saved 8 bits at a time 1 Saved simultaneously all 16 bits SP Finished saving registers Finished saving registers in two operations in four operations PCL 8 low order bit of PC PCM 8 middle order bits of PC PCH 4 high order bits of PC FLGL 8 low order bits of FLG FLGH 4 high order bits of FLG NOTE 1 SP denotes the initial value of the SP when interrupt request is acknowledged After registers are saved the SP content is SP minus 4 Figure 9 8 Operation of Saving Registers Rev 1 10 Jul01 2005 page 70 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 9 Interrupt 9 5 8 Returning from an Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine Thereafter the CPU returns to the program which was being executed before accepting the interrupt request Return the other
33. Not detected Detecting Flag 1 Detected No overrun error Overrun error found No framing error Framing error found No parity error Parity error found No error Error found o Overrun Error Flag 2 Framing Error Flag 2 Parity Error Flag 2 Error Sum Flag 2 aii a 0 0 J a 1 The ABT bit is set to 0 by writing 0 in a program Writing 1 has no effect 2 When the SMD2 to SMDO bits in the UiMR register 000b serial I O disabled or the RE bit in the UiC1 register 0 reception disabled all of the SUM PER FER and OER bits are set to 0 no error The SUM bit is set to O no error when all of the PER FER and OER bits are 0 no error Also the PER and FER bits are set to 0 by reading the lower byte of the UiRB register UARTI Bit Rate Generator Register i 0 to 2 0 9 Symbol Address After Reset UOBRG 03A1h Indeterminate U1BRG 03A9h Indeterminate U2BRG 01F9h Indeterminate bo Assuming that set value n UiBRG ivi FFh b7 b0 divides the count source by n 1 1 Write to this register while serial I O is neither transmitting nor receiving 2 Use the MOV instruction to write to this register Figure 14 5 UOTB to U2TB Registers UORB to U2RB Registers and UOBRG to U2BRG Registers Rev 1 10 Jul 01 2005 page 132 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to chan
34. Rev 1 10 Jul01 2005 page 202 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 18 CAN Module 18 1 CAN Module Related Registers The CANi i 0 1 module has the following registers 18 1 1 CAN Message Box A CAN module is equipped with 16 slots 16 bytes or 8 words each Slots 14 and 15 can be used as Basic CAN Priority of the slots The smaller the number of the slot the higher the priority in both transmission and reception A program can define whether a slot is defined as transmitter or receiver 18 1 2 Acceptance Mask Registers A CAN module is equipped with 3 masks for the acceptance filter CANI global mask register i 0 1 CiGMR register 6 bytes Configuration of the masking condition for acceptance filtering processing to slots O to 13 e CANI local mask A register CILMAR register 6 bytes Configuration of the masking condition for acceptance filtering processing to slot 14 CANi local mask B register CiLMBR register 6 bytes Configuration of the masking condition for acceptance filtering processing to slot 15 18 1 3 CAN SFR Registers CANi message control register j i 0 1 j O to 15 CIMCTLj register 8 bits X 16 Control of transmission and reception of a corresponding slot e CANI control register CICTLR register 16 bits Control of the CAN protocol e CANI status register CISTR regist
35. Set to 01b TB2 underflow before TA1TGH Select Bit using a V phase output control circuit RW TA2TGL Timer A2 Event Trigger Set to 01b TB2 underflow before TA2TGH TA2TGH Select Bit using a W phase output control circuit b5 b4 TASTGL 0 0 Selects an input to the TA3IN pin 1 Timer A3 Event Trigger 0 1 Selects TB2 2 Select Bit 3 1 0 Selects TA2 2 TASIGA 1 1 Selects TA4 2 TA4TGL Timer A4 Event T rigger Set to 01b TB2 underflow before TA4TGH Select Bit using a U phase output control circuit 1 Set the corresponding port direction bit to 0 input mode 2 Overflow or underflow Count Start Flag b7 b6 b5 b4 b3 b2 bi b0 Symbol Address a d TABSR 0380h e TAOS Timer A0 Count Start Flag 0 Stops counting 1 Starts counting Figure 13 7 TRGSR Register and TRBSR Register Rev 1 10 Jul01 2005 page 124 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Three Phase Motor Control Timer Function Timer Ai Mode Register i 1 2 4 b7 b6 b5 b4 b3 b2 bi BBDDEDUE Dd Address After Reset TA1MR TA2MR TA4MR 0397h 0398h 039Ah 00h a e A TMODO TMODO Set to 10b one shot timer mode Operation Mode with the three phase motor Mies TMOD1 Select Bit timer function RW MRO Pulse Output Function Set to 0 with the three phase motor Se
36. n value set to UIBRG CRD bit in UiCO register 0 CTS RTS enabled and CRS bit 0 CTS selected UIIRS bit 1 an interrupt request occurs when transmit completed i 0102 UOIRS bit is bit 0 in UCON register B U1IRS bit is bit 1 in UCON register U2IRS bit is bit 4 in U2C1 register 2 Example of Transmit Timing when Transfer Data is 9 bit Long parity disabled two stop bits Transfer clock TE bit in rt UiC1 register o 0 Write data to the UiTB register TI bit in UiC1 register an B x Transferred from UiTB register to UARTI transmit register Start Stop Stop _ bit bit bit m OATES LEADER TXEPT bit in n 1 UiCO register sns L IR bit in SiTIC register Z Set to 0 by an interrupt request acknowledgement or by program The above timing diagram applies to the case where the register bits are set TC 16 n 1 fj or 16 n 1 fEXT as follows fj frequency of UIBRG count source f1SIO f2SIO f8SIO f32SIO PRYE bit in UiMR register 0 parity disabled fEXT frequency of UiBRG count source external clock STPS bit in UIMR register 1 2 stop bits n value set to UBRG CRD bit in VICO register 1 CTS RTS disabled i201t02 UiIRS bit O an interrupt request occurs when transmit buffer becomes empty UOIRS bit is bit O in UCON register U1IRS bit is bit 1 in UCON register U2IRS bit is bit 4 in U2C1 register Figure 14 17 Transmit Operation Rev 1 10 Jul01 2005 page
37. the value of the ACKD bit in the UiSMR4 register is output from the SDAi pin If the IICM2 bit 0 a NACK interrupt request is generated if the SDAi pin remains high at the rising edge of the 9th bit of transmit clock pulse An ACK interrupt request is generated if the SDAi pin is low at the rising edge of the 9th bit of transmit clock pulse If ACKi is selected for the cause of DMA1 request a DMA transfer can be activated by detection of an acknowledge 14 1 3 8 Initialization of Transmission Reception If a start condition is detected while the STAC bit 1 UARTI initialization enabled the serial I O operates as described below e The transmit shift register is initialized and the content of the UiTB register is transferred to the trans mit shift register In this way the serial I O starts sending data synchronously with the next clock pulse applied However the UARTi output value does not change state and remains the same as when a start condition was detected until the first bit of data is output synchronously with the input clock The receive shift register is initialized and the serial I O starts receiving data synchronously with the next clock pulse applied The SWC bit is set to 1 SCL wait output enabled Consequently the SCLi pin is pulled low at the falling edge of the ninth clock pulse Note that when UARTi transmission reception is started using this function the TI bit does not change state Note also that whe
38. to the CLKi pin before receiving data is high CKDIR bit in VIMR register 1 external clock ES TE bit in UiC1 register 1 transmission enabled e CRD bit in VICO register 0 CTS RTS enabled CRS bit 1 RTS selected RE bit in UiC1 register 1 reception enabled e CKPOL bit in VICO register O transmit data output at the falling edge and receive Write dummy data to the UiTB register data taken in at the rising edge of the transfer clock fEXT frequency of external clock Figure 14 11 Transmit and Receive Operation Rev 1 10 Jul01 2005 page 141 of 318 RENESAS REJ09B0124 0110 14 Serial I O Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O 14 1 1 1 Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in clock synchronous serial I O mode follow the procedures below Resetting the UiRB register i 0 to 2 1 Set the RE bit in the UiC1 register to 0 reception disabled 2 Set the SMD2 to SMDO bits in the UiMR register to 000b serial I O disabled 3 Set the SMD2 to SMDO bits in the UiMR register to 001b clock synchronous serial I O mode 4 Set the RE bit in the UiC1 register to 1 reception enabled Resetting the UiTB register i O to 2 1 Set the SMD2 to SMDO bits in the UiMR register to 000b serial I O disabled 2 Set
39. 01AFh 01BOh 01B1h 01B2h 01B3h 01B4h 01B5h Flash Memory Control Register 1 1 OX00XX0Xb 01B6h 01B7h Flash Memory Control Register 0 1 00000001b 01B8h 00h Address Match Interrupt Register 2 00h 01BAh X0Oh 01BBh_ Address Match Interrupt Enable Register 2 XXXXXX00b 01BCh 00h Address Match Interrupt Register 3 00h 01BEh X0h 01BFh X Undefined NOTES 1 These registers are included in the flash memory version Cannot be accessed by users in the mask ROM version 2 The blank areas are reserved and cannot be accessed by users Rev 1 10 Jul01 2005 page 19 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 8 SFR Information 8 Address Symbol After Reset 01Coh_ Timer B3 B4 B5 Count Start Flag TBSR 000XXXXXb 01Cih 01C2h XXh imer A1 1 Register TA11 XXh 01C3h 01C4h XXh 01C5h imer A2 1 Register TA21 XXh 01C6h XXh imer A4 1 Register TA41 XXh Three Phase PWM Control Register 0 INVCO 00h Three Phase PWM Control Register 1 INVC1 00h Three Phase Output Buffer Register O IDBO 00h Three Phase Output Buffer Register 1 IDB1 00h Dead Time Timer D
40. 1 33h 4 22h 1Fh 9 19h 9 13h 33h 22h h 1F 19h 13h Rev 1 10 Jul01 2005 page 150 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O 14 1 2 2 Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in UART mode follow the procedures below Resetting the UiRB register i 0 to 2 1 Set the RE bit in the UiC1 register to 0 reception disabled 2 Set the RE bit in the UiC1 register to 1 reception enabled e Resetting the UiTB register i 0 to 2 1 Set the SMD2 to SMDO bits in the UiMR register to 000b Serial I O disabled 2 Set the SMD2 to SMDO bits in the UiMR register to 001b 101b 110b 3 1 transmission enabled is written to the TE bit in the UiC1 register regardless of the TE bit 14 1 2 3 LSB First MSB First Select Function As shown in Figure 14 19 use the UFORM bit in the UiCO register to select the transfer format This function is valid when transfer data is 8 bit long 1 When the UFORM bit in the UiCO register O LSB first CLKi TXDi st Do X D1 X D2 X pa X D4 X D5 X De X Dz X P Y SP RXDi st A Do X D1 X D2 X D3 X D4 X ps X pe X D7X P Y SP 2 When the UFORM bit
41. 11 DMAC Table 11 1 DMAC Specifications Item Specification No of Channels 2 cycle steal method Transfer Memory Space From any address in the 1 Mbyte space to a fixed address From a fixed address to any address in the 1 Mbyte space From a fixed address to a fixed address Maximum No of Bytes Transferred 128 Kbytes with 16 bit transfer or 64 Kbytes with 8 bit transfer DMA Request Factors Falling edge of INTO or INT1 Both edge of INTO or INT1 Timer AO to timer A4 interrupt requests Timer BO to timer B5 interrupt requests UARTO transfer UARTO reception interrupt requests UART1 transfer UART1 reception interrupt requests UART2 transfer UART2 reception interrupt requests SI 03 SI O4 interrupt requests A D conversion interrupt requests Software triggers Channel Priority DMAO gt DMA1 DMAO takes precedence Transfer Unit 8 bits or 16 bits Transfer Address Direction forward or fixed The source and destination addresses cannot both be in the forward direction Transfer Mode Single Transfer Transfer is completed when the DMAi transfer counter underflows after reaching the terminal count Repeat Transfer When the DMAi transfer counter underflows it is reloaded with the value of the DMAi transfer counter reload register and a DMA transfer is continued with it DMA Interrupt Request Generation Timing When the DMAi transfer counter underflowed
42. 4H a Input to respective peripheral functions lt words Symbolizes a parasitic diode Make sure the input voltage on each port will not exceed VCC 2 P11 to P14 are only in the 128 pin version Figure19 1 I O Ports 1 Rev 1 10 Jul01 2005 page 228 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 Programmable l O Ports Pull up selection Direction register 1 bis Output Data bus Port latch adim m i lt Switching gt NOTE 1 between ____ CMOS and Nch Input to respective peripheral functions Pull up selection Direction register lt Data bus Port latch P8 210 P8 4 4 NOTE 1 rir Input to respective peripheral functions Pull up selection Direction register P55 P7 7 P9 7 i lt P11_0 P11 1 P11 5 P11 72 P13 5to P13 7 Data bus Port latch NOTE 1 777 Input to respective peripheral functions f Symbolizes a parasitic diode Make sure the input voltage on each port will not exceed VCC 2 P11 to P13 are only in the 128 pin version Figure19 2 1 O Ports 2 R
43. 7 4 1 Normal Operation Mode Normal operation mode is further classified into seven sub modes In normal operation mode because the CPU clock and the peripheral function clocks both are on the CPU and the peripheral functions are operating Power control is exercised by controlling the CPU clock frequency The higher the CPU clock frequency the greater the processing capability The lower the CPU clock frequency the smaller the power consumption in the chip If the unnecessary oscillator circuits are turned off the power consumption is further reduced Before the clock sources for the CPU clock can be switched over the new clock source to which switched must be oscillating stably If the new clock source is the main clock sub clock or PLL clock allow a sufficient wait time in a program until it becomes oscillating stably Note that operation modes cannot be changed directly from low speed or low power dissipation mode to on chip oscillator or on chip oscillator low power dissipation mode Nor can operation modes be changed directly from on chip oscillator or on chip oscillator low power dissipation mode to low speed or low power dissipation mode Where the CPU clock source is changed from the on chip oscillator to the main clock change the operation mode to the medium speed mode divide by 8 mode after the clock was divided by 8 the CMO6 bit in the CMO register was set to 1 in the on chip oscillator mode 7 4 1 1 High speed Mode The main
44. AN 010Fh CANO Message Box 10 Time Stamp 0110h 0111h o112h ANO M Box 11 0113h CANO Message Box 11 Identifier DLC 0114h 0115h 0116h 0117h 0118h ono 011Ah CANO Message Box 11 Data Field 011Bh 011Ch 011Dh 011Eh p 011Fh CANO Message Box 11 Time Stamp 0120h 0121h o122h 0123h CANO Message Box 12 Identifier DLC 0124h 0125h 0126h 0127h 0128h 0129h 012Ah CANO Message Box 12 Data Field 012Bh 012Ch 012Dh 012Eh nm 012Fh CANO Message Box 12 Time Stamp 0130h 0131h 0132h T ANO M B t 0133h CANO Message Box 13 Identifier DLC 0134h 0135h 0136h 0137h 0138h 0139h 013Ah CANO Message Box 13 Data Field 013Bh 013Ch 013Dh 013Eh 013Fh CANO Message Box 13 Time Stamp X Undefined Rev 1 10 Jul01 2005 page 17 of 318 ENESAS REJO9B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 6 SFR Information 6 Address 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh CANO Message Box 14 Identifier DLC CANO Message Box 14 Data Field CANO Message Box 14 Time Stamp CANO Message Box 15 Identifier DLC
45. ANO to AN3 4 pins ANO to AN5 6 pins ANO to AN7 8 pins Reading of Result of A D Converter NOTE Read one of the ADO to AD7 registers that corresponds to the selected pin 1 ANO 0 to ANO 7 and AN2 0 to AN2 7 can be used in the same way as ANO to AN7 Rev 1 10 Jul01 2005 page 189 of 318 RENESAS REJ09B0124 0110 15 A D Converter Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 A D Converter A D Control Register 0 b7 b6 b5 b4 b3 b2 bi bO PTT ToT LL aooo fien ooo Analog Input Pin Select Bit Invalid in single sweep mode MDO A D Operation Mode DADOS ur Select Bit 0 1 0 Single sweep mode 0 Software trigger Trigger Select Bit 1 ADTRG trigger RW 0 A D conversion disabled ADST A D Conversion Start Flag 1 A D conversion started Refer to NOTE 2 for ADCON2 CKSO Frequency Select Bit 0 Register 1 If the ADCONO register is rewritten during A D conversion the conversion result will be indeterminate A D Control Register 1 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset LE aft fof ADCON1 03D7h 00h When single sweep mode is selected b1 bo RW 2 pi A D Sweep Pin Select Bit ANO NS bum 10 ANO to AN5 6 pins 11 ANO to AN7 8 pins 2 EN MD2 A D Operation Mode Set to 0 when single sweep mode RW Select Bit 1 is selected 1 0 8 bit mode BITS 8 10 Bit Mode Select Bi
46. CE input Input H level signal P5 1 to P5 4 P5 6 P5 7 Input port P5 Input H or L level signal or open P5 5 EPM input Input L level signal P6 Oto P6 4 P6 6 Input port P6 Input H or L level signal or open P6 5 CLK1 SCLK input Input L level signal Pe 7 TXD1 TXD output Input H level signal P7 0to P7 7 Input port P7 Input H or L level signal or open P8 Oto P8 4 P8 6 P8 7 Input port P8 Input H or L level signal or open P8 5 NMI NMI input Connect this pin to VCC1 P9 Oto P9 4 P9 7 Input port P9 Input H or L level signal or open P9 5 CRXO CRX input Connect to a CAN transceiver P9 6 CTXO CTX output Connect to a CAN transceiver P10 0 to P10 7 Input port P10 Input H or L level signal or open P11_0 to P11 7 Input port P11 Input H or L level signal or open P12 0 to P12 7 o Input port P12 Input H or L level signal or open P13 O to P13 7 1 Input port P13 Input H or L level signal or open P14 0 P14 1d NOTE Input port P14 Input H or L level signal or open 1 The pins P11 to P14 are only in the 128 pin version Rev 1 10 Jul01 2005 page 265 of 318 REJO9B0124 0110 RENESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK
47. FFFDChto FFFDFh M16C 60 M16C 20 Series Software Overflow INTO instruction FFFEOh to FFFE3h Manual BRK Instruction FFFE4h to FFFE7h Address Match FFFE8h to FFFEBh 9 10 Address Match Interrupt Single Step FFFEChto FFFEFh Oscillation Stop and Re oscillation Detection FFFFOh to FFFF3h 7 Clock Generating Circuit Watchdog Timer 10 Watchdog Timer DBC FFFF4h to FFFF7h NMI FFFF8h to FFFFBh 9 7 NMI Interrupt Reset FFFFCh to FFFFFh 5 Reset NOTES 1 Do not normally use this interrupt because it is provided exclusively for use by development support tools 2 If the contents of address FFFE7h is FFh program execution starts from the address shown by the vector in the relocatable vector table 9 4 2 Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB register comprise a relocatable vector table area Table 9 2 lists the relocatable vector tables Setting an even address in the INTB register results in the interrupt sequence being executed faster than in the case of odd addresses Rev 1 10 Jul01 2005 page 63 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Table 9 2 Relocatable Vector Tables Interrupt Source BRK Instruction Vector Address Address L to Address H 0 to 3 0000h to 0003h Software Interrupt Number o 9 Interrupt
48. Figure 11 6 DMA Transfer by External Factors Rev 1 10 Jul01 2005 page 91 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 Timers 12 Timers Eleven 16 bit timers each capable of operating independently of the others can be classified by function as either timer A five and timer B six The count source for each timer acts as a clock to control such timer operations as counting reloading etc Figures 12 1 and 12 2 show block diagrams of Timer A and Timer B configuration respectively f2 PCLKO 0 Main clock PLL clock On chip fl f1 or f2 PCLKO 1 oscillator clock DEE f8 1 4 132 f1 or f2 f8 f32 1032 TCK1 to TCKO 00r roi rol palo Clock prescaler XCINC 1 32 Set the CPSR bit in the CPSRF register to 1 prescaler reset TMOD1 to TMODO 00 Timer mode 10 10 One shot timer mode 11 Pulse width measuring mode oi ee s 2 gt Noise filter TCK1 to TCKO 00 Q 015 10 Q 11 TAOTGH to TAOTGL 11 00 01 Event counter mode TMOD 1 to TMODO 00 Timer mode 10 One shot timer mode 11 Pulse width measuring mode Noise 01 filter TCK1 to TCKO 00 Q 01 10 Boro 11 TA1TGH t0 TA1TGL
49. Figure 15 8 shows the ADCONO and ADCON1 registers in repeat sweep mode 1 Table 15 6 Repeat Sweep Mode 1 Specifications Specification Function The input voltages on all pins selected by the ADGSEL1 to ADGSELO bits in the ADCON register are A D converted repeatedly with priority given to pins selected by the SCAN1 to SCANO bits in the ADCON1 register and ADGSEL1 to ADGSELO bits Example If ANO selected input voltages are A D converted in order of ANO AN1 ANO gt AN2 gt ANO gt AN3 and so on A D Conversion Start Condition When the TRG bit in the ADCONO register is 0 software trigger The ADST bit in the ADCONO register is set to 1 A D conversion starts When the TRG bit is 1 ADTRG trigger Input on the ADTRG pin changes state from high to low after the ADST bit is set to 1 A D conversion starts A D Conversion Stop Condition Set the ADST bit to 0 A D conversion halted Interrupt Request Generation Timing None generated Analog Input Pins to be Given Priority when A D Converted Select from ANO 1 pin ANO to AN1 2 pins ANO to AN2 3 pins ANO to AN3 4 pins Reading of Result of A D Converter NOTE Read one of the ADO to AD7 registers that corresponds to the selected pin 1 ANO 0 to ANO 7 and AN2 0 to AN2 7 can be used in the same way as ANO to AN7 Rev 1 10 Jul01 2005 page 193 of 318 RENESAS REJ09B0124 0110 15 A D Conve
50. INT7 Interrupt Control Register INT7IC Timer A3 Interrupt Control Register TA3IC Processor Mode Register 2 INT6 Interrupt Control Register INT6IC Timer A4 Interrupt Control Register TA4IC Timer BO Interrupt Control Register TBOIC DMAO Source Pointer SI O6 Interrupt Control Register S6IC 0022h Timer B1 Interrupt Control Register TB11C 0023h INT8 Interrupt Control Register INT8IC 0024h Timer B2 Interrupt Control Register TB2IC ocn INTO Interrupt Control Register INTOIC DMAO Destination Pointer INT1 Interrupt Control Register INT1IC 0026h INT2 Interrupt Control Register INT2IC 0027h 0028h PLL Control Register 0 DMAO Transfer Counter CANO Message Box 0 Identifier DLC 002Ch DMAO Control Register DMOCON 0030h CANO Message Box 0 Data Field DMA1 Source Pointer 0032h 0033h 0034h CANO Message Box 0 Time Stamp DMA1 Destination Pointer 0036h Aum CANO Message Box 1 Identifier DLC 0039h DMA1 Transfer Counter TCR1 003Ah 003Ch DMA1 Control Register DM1CON 85 CANO Message Box 1 Data Field The blank areas are reserved CANO Message Box 1 Time Stamp Symbol CANO Message Box 2 Identifier DLC CANO Message Box 2 Data Field
51. M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O Table 14 7 lists the functions of the input output pins during UART mode Table 14 8 lists the P6_4 pin functions during UART mode Note that for a period from when the UARTi operation mode is selected to when transfer starts the TXDi pin outputs an H Figure 14 17 shows the typical transmit timings in UART mode Figure 14 18 shows the typical receive timing in UART mode Table 14 7 I O Pin Functions Function Method of Selection Outputs H when performing reception only TXDi P6 3 P6 7 P7 0 Serial Data Output RXDi P6 2 P6 6 P7 1 Serial Data Input PD6 2 and PD6 6 bits in PD6 register O PD7 1 bit in PD7 register 0 Can be used as an input port when performing transmission only CLKi I O Port CKDIR bit in UiMR register 0 P6 1 P6 5 P7 2 Transfer Clock Input CKDIR bit in UiMR register 1 PD6 1 and PD6 5 bits in PD6 register 0 PD7 2 bit in PD7 register 0 CTSI RTSi TS Input P6 0 P6 4 P7 3 CRD bit in UiCO register O CRS bit in VICO register 0 PD6_0 and PD6 4 bits in PD6 register O PD7_3 bit in PD7 register 0 CRD bit 0 CRS bit 1 i 0to2 Table 14 8 P6 4 Pin Functions CRD bit 1 Bit set Value Pin Function U1CO Register UCON Register PD6 Register CRD bit CRS bit RCSP bit CLKMD bit PD6 4 bit Input 0 Output 1 0 or 1 NOTE
52. M16C 6NM 14 Serial I O 14 1 1 Clock Synchronous Serial I O Mode The clock synchronous serial I O mode uses a transfer clock to transmit and receive data Table 14 1 lists the specifications of the clock synchronous serial I O mode Table 14 2 lists the registers used in clock synchronous serial I O mode and the register values set Table 14 1 Clock Synchronous Serial I O Mode Specifications Specification Transfer Data Format Transfer data length 8 bits Transfer Clock The CKDIR bit in the UiMR register 0 internal clock fj 2 n 1 e fj f181O f2SIO f8SIO f32SIO n Setting value of the UiBRG register 00h to FFh The CKDIR bit 1 external clock Input from CLKi pin Transmission Reception Control Selectable from CTS function RTS function or CTS RTS function disabled Transmission Start Condition Before transmission can start the following requirements must be met The TE bit in the UiC1 register 1 transmission enabled The TI bit in the UiC1 register O data present in the UiTB register e If CTS function is selected input on the CTSi pin L Reception Start Condition Before reception can start the following requirements must be met The RE bit in the UiC1 register 1 reception enabled The TE bit in the UiC1 register 1 transmission enabled The TI bit in the UiC1 register O data present in the UiTB register Interrupt Request Generation Timing For trans
53. OFFFEFh to OFFFECh ID4 Single step vector OFFFF3h to OFFFFOh ID5 Oscilation stop and re oscillation detection Watchdog timer vector OFFFF7h to OFFFF4h ID6 DBC vector OFFFFBh to OFFFF8h ID7 NMI vector OFFFFFh to OFFFFCh ROMCP Reset vector Figure 20 3 Address for ID Code Stored Rev 1 10 Jul01 2005 page 241 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 3 CPU Rewrite Mode In CPU rewrite mode the user ROM area can be rewritten when the CPU executes software commands The user ROM area can be rewritten with the microcomputer is mounted on a board without using a parallel serial or CAN programmer In CPU rewrite mode only the user ROM area shown in Figure 20 1 can be rewritten The boot ROM area cannot be rewritten Program and the block erase command are executed only in the user ROM area Erase write 0 EWO mode and erase write 1 EW1 mode are provided as CPU rewrite mode Table 20 3 lists the differences between EWO and EW1 modes Table 20 3 EWO Mode and EW1 Mode EWO Mode EWT Mode Operation Mode Single chip mode Boot mode 20 Flash Memory Version Single chip mode Space where Rewrite Control Program can be Placed User ROM area Boot ROM area User ROM area Space where Rewrite Control Program can be Executed The rewrite control program must be transferred to
54. P8 O TA4OUT U P7 5 TA2IN W I P9 2 TB2IN SOUT3 lt lt c P9 O TBOIN CLK3 lt lt 2 P9 4 DA1 TBAIN a gt P7 6 TA3OUT CTX 1 P9 1 TB1IN SIN3 lt lt F P7 AITA2OUT NI NOTE Package PLQP0100KB A 1 P7 1 and P9 1 are N channel open drain pins Figure 1 3 Pin Configuration Top View 1 Rev 1 10 Jul01 2005 page 6 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM PIN CONFIGURATION top view P1 0 lt gt PO 7 ANO 7 lt gt PO 6 ANO 6 lt gt PO 5 ANO 5 gt PO 4 ANO 4 PO S ANO 3 c PO 2 ANO 2 e PO 1 ANO 1 e PO O ANO 0 c P11_7 SING a P11 6 SOUT6 P11 5 CLK6 e P11 4 lt P11 3 p P11_2 SOUT5 lt a P11 1 SIN5 lt lt P11_0 CLK5 lt gt P12 INT3 INT4 MINTS gt P2 0 AN2_0 c p1_5 lt Pie E P1 gt p2 1 AN2 1 lt gt p2 A AN2 4 este sy T e o o gt 77 QN CO sf 10 XO T O QI OO TOON CO CO CO CO CO CO t b sb b t ttt amp n PL amp amp L 6 0 6 D aaa n AAA jar Pi 1 sir pi 3 Elan py 4 Fo E E o p2 2 AN2 2 S a P2 3 AN2_3 S o P2 5 AN2 5 E a 9 P2 6 AN2 6 Fo S a P2 7 AN2 7 3 4 vss Spl sala b 80 79 78 77 76 75
55. System Clock Control Register 0 01001000b System Clock Control Register 1 00100000b Address Match Interrupt Enable Register XXXXXX00b Protect Register XX000000b Oscillation Stop Detection Register 1 0X000000b Watchdog Timer Start Register XXh Watchdog Timer Control Register OOXXXXXXb 00h Address Match Interrupt Register 0 00h XOh 00h Address Match Interrupt Register 1 00h XOh PLL Control Register 0 0001X010b Processor Mode Register 2 XXX00000b XXh 0021h DMAO Source Pointer XXh 0022h XXh 0023h 0024h XXh 0025h DMAO Destination Pointer XXh 0026h XXh 0027h 0028h DMAO Transfer Counter XXh XXh DMAO Control Register DMOCON 00000X00b 0031h DMA1 Source Pointer 0032h 0033h 0034h 0035h DMA1 Destination Pointer 0036h 0037h 0038h DMA1 Transfer Counter DMA1 Control Register DM1CON 00000X00b X Undefined NOTES 1 The CM20 CM21 and CM27 bits in the CM2 register do not change at oscillation stop detection reset 2 The blank areas are reserved and cannot be accessed by users Rev 1 10 Jul01 2005 page 13 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 2 SFR Informatio
56. Timer Ai Mode Register i 0 to 4 b7 b6 b5 b4 b3 b2 bi b0 Jol 1fo Symbol Address After Reset TAOMR to TA4MR 0396h to 039Ah 00h E ETS Select Bit 1 Pulse is output TMODO IEE Operation Mode Select Bit 1 0 One shot timer mode TMOD1 RW 0 Pulse is not output TAiouT pin functions as a pulse output pin External Trigger Select O Falling edge of input signal to TAiIN pin 2 z Pulse Output Function TAiouT pin functions as I O port Bit 1 1 Rising edge of input signal to TAiIN pin 2 0 TAiOS bit is enabled MR2 Trigger Select Bit 1 Selected by TAITGH to TAITGL bits MR3 Set to 0 in one shot timer mode b7 b6 TCKO 00 f1 or f2 01 f8 Count Source Select Bit 10129 RW RW RW RW RW RW Ww 1 Effective when the TAITGH and TAiTGL bits in the ONSF or TRGSR register are 00b TAIIN pin input 2 The port direction bit for the TAiIN pin is set to 0 input mode Figure 12 11 TAiMR Register in One shot Timer Mode Rev 1 10 Jul01 2005 page 105 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 Timers 12 1 4 Pulse Width Modulation PWM Mode In pulse width modulation mode the timer outputs pulses of a given width in succession The counter functions as either 16 bit pulse width modulator or 8 bit pulse width modulator Table 12 5 lists specifications in pulse width modulati
57. Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O Table 14 3 lists the functions of the input output pins during clock synchronous serial I O mode Table 14 3 shows pin functions for the case where the multiple transfer clock output pin select function is deselected Table 14 4 lists the P6 4 pin functions during clock synchronous serial I O mode Note that for a period from when the UARTi operation mode is selected to when transfer starts the TXDi pin outputs an H Figure 14 11 shows the transmit receive timings during clock synchronous serial I O mode Table 14 3 Pin Functions When Not Select Multiple Transfer Clock Output Pin Function TXDi Serial Data Output Outputs dummy data when performing reception only P6_3 P6_7 P7_0 RXDi Serial Data Input PD6_2 and PD6 6 bits in PD6 register O P6_2 P6_6 P7_1 PD7_1 bit in PD7 register 0 Can be used as an input port when performing transmission only CLKi Transfer Clock Output CKDIR bit in UiMR register 0 P6 1 P6 5 P7 2 Transfer Clock Input CKDIR bit 1 PD6 1 and PD6 5 bits in PD6 register 0 PD7 2 bit in PD7 register 0 CTSi RTSi CTS Input CRD bit in UiCO register 0 P6_0 P6_4 P7_3 CRS bit in UiCO register 0 PD6_0 and PD6_4 bits in PD6 register 0 PD7_3 bit in PD7 register 0 RTS Output CRD bit 0 CRS bit 1 I O Port CRD bit 1 i
58. connect every pin to VSS via a resistor pull down P8 6 P8 7 P9 to P14 or after setting for output mode leave these pins open 9 XOUT Open NMI P8 5 Connect via resistor to VCC pull up AVCC Connect to VCC AVSS VREF BYTE Connect to VSS NOTES 1 When setting the port for output mode and leave it open be aware that the port remains in input mode until it is switched to output mode in a program after reset For this reason the voltage level on the pin becomes indeterminate causing the power supply current to increase while the port remains in input mode Furthermore by considering a possibility that the contents of the direction registers could be changed by noise or noise induced runaway it is recommended that the contents of the direction registers be periodically reset in software for the increased reliability of the program 2 Make sure the unused pins are processed with the shortest possible wiring from the microcomputer pins within 2 cm 3 When the ports P7 1 and P9 1 are set for output mode make sure a low level signal is output from the pins The ports P7 1 and P9 1 are N channel open drain outputs 4 With external clock input to XIN pin 5 The ports P11 to P14 are only in the 128 pin version When not using all of the P11 to p14 pins may be left open by setting the PU37 bit in the PUR register to 0 P11 to P14 unusable without causing any problem Microcomputer Port PO to
59. e a 3 x DetailF 88 dul x ot y 010 Z 05 z os L 0 35 05 0 65 Ly 10 Rev 1 10 Jul01 2005 page 315 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Appendix 1 Package Dimensions Memo Rev 1 10 Jul01 2005 page 316 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Register Index ADONOADT ie rens 184 ADCONO 183 186 188 190 192 194 ADCON 183 186 188 190 192 194 ADCON 2 3 ti ted 184 Dios 65 AER dada 79 AER O 5 tete rientra 79 C COTERRIG iier e iet 65 COTWNKIG er epe 65 COAFS CAAFS eessss 212 COCONR C1CONR s 211 COCTLR C1CTLR ss 208 COGMR C1GMR s 206 COICR C1ICR eeeeeesees 210 COIDR C1IDR eeeess 210 COLMAR C1LMAR 206 COLMBR C1LMBR 206 COMCTLO to COMCTL15 207 COREGIG serca 65 CORECR C1RECR un 212 COSSTR CASSTR iuris 210 COSTR CASTR sseesess 209 COTECR C1TECR 212 COTRMIC esseenm 65 COTSR C1TSR seseeeess 212 C1MCTLO
60. e SMi3 1 SOUTi output CLKi function SMi4 0 transmit data output at the falling edge and receive data input at the rising edge of the transfer clock SMi5 0 LSB first SMi6 1 internal clock NOTES 1 If the SMi6 bit 1 internal clock the serial I O starts sending or receiving data a maximum of 1 5 transfer clock cycles after writing to the SiTRR register 2 When the SMi6 bit 1 internal clock the SOUTI pin is placed in the high impedance state after the transfer finishes Figure 14 39 SI Oi Operation Timing 14 2 2 CLK Polarity Selection The SMi4 bit in the SiC register allows selection of the polarity of the transfer clock Figure 14 40 shows the polarity of the transfer clock 1 When SMi4 bit in SiC register 0 CLKi ii NOTE 1 SOUTI X po X D1 X p2 X D3 X D4 X Ds X De X D7 SINi X po X D1 X D2 X D3 X D4 X Ds X pe X D7 2 When SMi4 bit in SiC register 1 NOTE 2 CLKi N SOUTI Xs Ga D3 X D4 X Ds X De X D7 SINi X Do X D1 X D2 X D3 X D4 X D5 X pe X D7 i 3 to 6 5 and 6 are only in the 128 pin version This diagram applies to the case where the bits in the SiC register are set as follows SMi5 0 LSB first SMi6 1 internal clock NOTES 1 When the SMi6 bit 1 internal clock a high level is output from the CLKi pin if not transferring data 2 W
61. i 2 PM10 Data Block Enable Bit 2 4 Block A enable Reserved Bit Set to 0 PM12 Watchdog Timer Function 0 Watchdog timer interrupt RW Select Bit 1 Watchdog timer reset 3 Internal Reserved Area PM13 Expansion Bit 4 See NOTE 6 Reserved Bit Set to 0 ew 0 No wait state PM17 Wait Bit 1 With wait state 1 wait Mm Write to this register after setting the PRC1 bit in the PRCR register to 1 write enable Set the PM10 bit to 0 for Mask ROM version For the flash memory version when the PM10 bit is set to 1 addresses OF000h to OFFFFh can be used as internal ROM area In addition the PM10 bit is automatically set to 1 while the FMRO 1 bit in the FMRO register is set to 1 CPU rewrite mode The PM12 bit is set to 1 by writing a 1 in a program writing a 0 has no effect Be sure to set this bit to 0 except for products with internal ROM area over 192 Kbytes The PM13 bit is automatically set to 1 when the FMRO bit is 1 CPU rewrite mode When the PM17 bit is set to 1 with wait state one wait state is inserted when accessing the internal RAM or internal ROM The access area is changed by the PM13 bit as listed in the table below PM13 0 PM13 1 Up to addresses 00400h to O3FFFh 15 Kbytes The entire are is usable Internal ROM Up to addresses DOO00h to FFFFFh 192 Kbytes The entire are is usable Figure 6 2 PM1 Register Rev 1 10 Jul01 2005 page 33 of 318 RENESAS REJ09B
62. o ar o D gt gt o o gt z ojojojo alala o ooo m OO w S 5 5 3 o T ojojojojojojo apa iard iard Pard are 2 G9 D9 DO PO NY PO S 0 mM o O W TITS o ZR DM Ph a a gt ojojojojo aaa w Gd w N DIA Aj 3 5 5 5 o A ojo E 2 o A Co UJ zx o rd wo o zx CANO Message Box 12 Identifier DLC CANO Global Mask Register 206 CANO Local Mask A Register COLMAR 206 CANO Message Box 12 Data Field CANO Message Box 12 Time Stamp CANO Local Mask B Register COLMBR 206 CANO Message Box 13 Identifier DLC 0173h CANO Message Box 13 Data Field 013Dh 013Eh 013Fh CANO Message Box 13 Time Stamp The blank areas are reserved B 3 s Register_____ Symbol Symbol Timer B3 B4 B5 Count Start Flag Timer A1 1 Register Timer A2 1 Register Timer A4 1 Register Three Phase PWM Control Register 0 Three Phase PWM Control Register 1 Three Phase Output Buffer Register 0 IDBO Three Phase Output Buffer Register 1 IDB1 Dead Time Timer DTT Timer B2 Interrupt Occurrence Frequency Set Counter ICTB2 Interrupt Cause Select Register 2 IFSR2 Timer B3 Register TB3 Timer B4 Register TB4 Timer B5 Register TB5 SI O6 Transmit Receive Register S6TRR SI O6 Control Register Sec SI O6 Bit Rate Generator SeBRG SI O3 4 5 6 Transmit Re
63. reception enabled The TE bit in the UiC1 register 1 transmission enabled The TI bit in the UiC1 register O data present in the UiTB register Interrupt Request Generation Timing For transmission one of the following conditions can be selected The UiIRS bit 0 transmit buffer empty when transferring data from the UiTB register to the UARTi transmit register at start of transmission The UiIRS bit 21 transfer completed when the serial I O finished sending data from the UARTi transmit register For reception When transferring data from the UARTIi receive register to the UiRB register at completion of reception Error detection Overrun error This error occurs if the serial I O started receiving the next data before reading the UiRB register and received the 7th bit of the next data Select function i 0to2 NOTES Clock phase setting Selectable from four combinations of transfer clock polarities and phases 1 When an external clock is selected the conditions must be met while if the CKPOL bit in the UiCO register 0 transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock the external clock is in the high state if the CKPOL bit 1 transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock the external clock is in the low state 2 The UOIRS and U1IRS bits respective
64. the counter value can be read out at any time by reading the TAi register However if the counter is read at the same time it is reloaded the value FFFFh is read Also if the counter is read before it starts counting after a value is set in the TAi register while not counting the set value is read If a low level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register 1 three phase output forcible cutoff by input on NMI pin enabled the TA1OUT TA2OUT and TA4OUT pins go to a high impedance state Rev 1 10 Jul01 2005 page 290 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 9 1 2 Timer A Event Counter Mode The timer remains idle after reset Set the mode count source counter value etc using the TAIMR i 0 to 4 register the TAi register the UDF register the TAZIE TAOTGL and TAOTGH bits in the ONSF register and the TRGSR register before setting the TAIS bit in the TABSR register to 1 count starts Always make sure the TAiMR register the UDF register the TAZIE TAOTGL and TAOTGH bits in the ONSF register and the TRGSR register are modified while the TAIS bit remains 0 count stops regardless whether after reset or not While counting is in progress the counter value can be read out at any time by reading the TAi register However FFFFh can be read
65. 032Fh Message Box 12 Time Stamp 0330h 0331h 0332h 0333h Message Box 13 Identifier DLC 0334h 0335h 0336h 0337h 0338h 0339h M 033Ah essage Box 13 Data Field 033Bh 033Ch 033Dh 033Eh p 033Fh Message Box 13 Time Stamp X Undefined Rev 1 10 Jul 01 2005 page 25 of 318 2 NEC S AS REJO9B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 14 SFR Information 14 Address 0340h 0341h 0342h 0343h 0344h 0345h 0346h 0347h 0348h 0349h 034Ah 034Bh 034Ch 034Dh 034Eh 034Fh 0350h 0351h 0352h 0353h 0354h 0355h 0356h 0357h 0358h 0359h 035Ah 035Bh 035Ch 035Dh 035Eh 035Fh CAN1 Message Box 14 Identifier DLC Message Box 14 Data Field CAN1 Message Box 14 Time Stamp Message Box 15 Identifier DLC Message Box 15 Data Field CAN1 Message Box 15 Time Stamp 0361h 0363h Global Mask Register 0364h 0365h 0366h 0367h 0368h 0369h 036Ah 036Bh 036Ch 036Dh 036Eh 036Fh 0370h Local Mask A Register C1LMAR Local Mask B Register C1LMBR Address O340h o34tn O34 0343h_ O344n O347h o348h o3agh 034Ah os4Bh O34Ch o35th o352n 0353h E 8
66. 1 Set the FMR11 bit to 1 immediately after setting it to 0 while the FMRO1 bit is set to 1 Do not generate an interrupt or a DMA transfer between setting the FMR11 bit to 0 and setting it to 1 Set the FMRO1 and FMR11 bits while H is applied to the NMI pin Figure 20 6 Setting and Resetting of EW1 Mode Rev 1 10 Jul01 2005 page 246 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Flash Memory Version Low power dissipation mode program Transfer a low power dissipation mode program to a space other the flash memory Jump to the low power dissipation mode program transferred to a space other than the flash memory In the following steps use the low power dissipation mode in a space other than the flash memory NOTES Set the FMRO 1 bit to 1 after setting it to O CPU rewrite mode enabled Set the FMSTP bit to 1 the flash memory stops operating It is in a low power dissipation state 1 Switch the clock source of the CPU clock Turn main clock stops 2 Process in low power dissipation mode or on chip oscillator low power dissipation mode 4 Start Wait Switch main clock gt until oscillation gt clock source of oscillation stabilizes the CPU clock 2 Set the FMSTP bit to 0 flash memory operation Set the FMRO1 bit to O CPU rewrite mode disabled Wait
67. 1 SI O6 The SI O6 interrupt is only in the 128 pin version In the 100 pin version set the IFSRO5 bit to 0 Timer BO 7 Timer B3 and UARTO bus collision detection share the vector and interrupt control register When using the timer B3 interrupt set the IFSRO6 bit to 0 Tmer B3 When using UARTO bus collision detection set the IFSRO6 bit to 1 UARTO bus collision detection 8 Timer B4 and UART1 bus collision detection share the vector and interrupt control register When using the timer B4 interrupt set the IFSRO7 bit to 0 Timer B4 When using UART1 bus collision detection set the IFSRO7 bit to 1 UART1 bus collision detection Figure 9 11 IFSRO Register Rev 1 10 Jul 01 2005 page 74 of 318 REJO9B0124 0110 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 9 Interrupt Interrupt Request Cause Select Register 1 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset IFSR1 01DFh 00h orome ereman e ieaoo AAA EA e Switching Bit 1 Both edges 1 O E E A DES E A AE roms Mea DES E IFSR16 nem Cause vum rest transmission SI 03 8 RW IESR17__ Interrupt Request Cause O CAN successful reception SV04 1 Select Bit 4 1 INT5 RW RW RW RW RW RW W 1 When setting this bit to 1 both edges make sure the POL bit in the INTOIC to INT5IC register is set to 0 falling edge 2 CAN1 success
68. 1 10 Jul 01 2005 page 117 of 318 REJO9B0124 0110 131 NESAS 13 Three Phase Motor Control Timer Function This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Under development epoui uogenpow snem enBuel O 01 18S SI 1 90ANI Ou Ji Swojpiepun zg wW 1114 Sy pue S eie sJejsi6eJ gq pue OGG eui ueuw juo ye pejejeue si 166611 19Jsue1 LON 19151691 USQVL U SHE SYYL 0 SYL 0 sa sibas ul SH 1 41 40 01198 pen LOAN us i SLANI OLOLANI S 1euBIS 0 0 4q SZV eui Bumes ueuw WeiBeIp SIU ur UMOYS JOU si 974d 0127Zd PUE Bd 08d 01 uiuos 1a18i6a1 ODANI Ui Sig ZOANI 01 OOANI ECT m dz LLANI epo Jew 045 30 o a e oc jojjuo I le jndino eseuq M 1966111 o euis 1ndino aseyd M 191siboy ZYL Peojay ggz 0 u Jaw eui peaq 7 nOu O los si euBis 0 0 iia S Lv eui umes Yay YNO Jo4u02 euis 1ndino aseyd A po jndino eseuq A lt jeubis 1ndino aseyd A ry peojay reisen LVL GG 0 Jeu eui I e u 01188 S euBis 0 01119 Sp v eui Dunes ueuw jeubis ndino eseua n asind eseya n 10gg ouo epoy Jaw 1 10uS euO 19 sIDOy uus py Jou indino eseug eeiu TIUS YN TUAE ETA T
69. 1 In addition to this set the CRD bit in the UOCO register to 0 CTSO RTSO enabled and the CRS bit in the UOCO register to 1 RTSO selected Rev 1 10 Jul 01 2005 page 148 of 318 REJO9B0124 0110 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O 1 Example of Transmit Timing when Transfer Data is 8 bit Long parity enabled one stop bit The transfer clock stops momentarily as CTSi is H when the stop bit is checked The transfer clock starts as the transfer starts immediately CTSi changes to L TC Transfer clock l TE bit in UiC1 register Write data to the UiTB register TI bit in q Q UiC1 register Transferred from UiTB register to UARTi transmit register CTSi i Stopped pulsing Start Parity Stop because the TE bit i bit bit bit 0 TXDi fo MORROS Rs Aso Ys Na TXEPT bit in UiCO register IR bit in SiTIC register Set to 0 by an interrupt request acknowledgement or by program The above timing diagram applies to the case where the register bits are set TC 16 n 1 fj or 16 n 1 EXT as follows f fj frequency of UIBRG count source f1SIO f2SIO f8SIO f32SIO PRYE bit in UIMR register 1 parity enabled fEXT frequency of UiBRG count source external clock STPS bit in UIMR register 0 1 stop bit
70. 12 9 TA2MR to TA4MR Registers in Event Counter Mode when using two phase pulse signal processing with timer A2 A3 or A4 Rev 1 10 Jul01 2005 page 102 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 Timers 12 1 2 1 Counter Initialization by Two Phase Pulse Signal Processing This function initializes the timer count value to 0 by Z phase counter initialization input during two phase pulse signal processing This function can only be used in timer A3 event counter mode during two phase pulse signal processing free running type x4 processing with Z phase entered from the ZP pin Counter initialization by Z phase input is enabled by writing 0000h to the TA3 register and setting the TAZIE bit in the ONSF register to 1 Z phase input enabled Counter initialization is accomplished by detecting Z phase input edge The active edge can be selected to be the rising or falling edge by using the POL bit in the INT2IC register The Z phase pulse width applied to the INT2 pin must be equal to or greater than one clock cycle of the timer A3 count source The counter is initialized at the next count timing after recognizing Z phase input Figure 12 10 shows the relationship between the two phase pulse A phase and B phase and the Z phase If timer A3 overflow or underflow coincides with the counter initialization by Z phase input
71. 15 bit counter which counts down the clock derived by dividing the CPU clock using the prescaler Whether to generate a watchdog timer interrupt request or apply a watchdog timer reset as an operation to be performed when the watchdog timer underflows after reaching the terminal count can be selected using the PM12 bit in the PM1 register The PM12 bit can only be set to 1 watchdog timer reset Once this bit is set to 1 it cannot be set to 0 watchdog timer interrupt in a program Refer to 5 3 Watchdog Timer Reset for details about watchdog timer reset When the main clock on chip oscillator clock or PLL clock is selected for CPU clock the divide by n value for the prescaler can be selected to be 16 or 128 If a sub clock is selected for CPU clock the divide by n value for the prescaler is always 2 no matter how the WDCT7 bit is set The period of watchdog timer can be calculated as given below The period of watchdog timer is however subject to an error due to the prescaler With main clock on chip oscillator clock or PLL clock selected for CPU clock Prescaler dividing 16 or 128 X Watchdog timer count 32768 Watchdog timer period 2 lt lt CPU clock With sub clock selected for CPU clock Prescaler dividing 2 X Watchdog timer count 32768 Watchdog ti iod atchdog timer perio CPU clock For example when CPU clock 16 MHz and the divide by n value for the prescaler 16 the watchdog timer period is approx
72. 2 PCLK7 A D Clock Direct Input Bit a M mw 1 Write to this register after setting the PRCO bit in the PRCR register to 1 write enable 2 If this bit is set to 1 the software interrupt number and SFR location can bs changed as follows 1 Software interrupt number of the key input interrupt in the vector table can be changed from 14 to 13 No 13 is changed from the CANO 1 error interrupt to the CANO 1 error key input interrupt No 14 is changed from the A D key input interrupt to the A D interrupt 2 Address of the KUPIC register in the SFR can be changed from 004Eh to 004Dh Address 004Dh is changed from the CO1ERRIC register to the CO1ERRIC KUPIC register Address 004Eh is changed from the ADIC KUPIC register to the ADIC register 3 When this bit 1 the A D clock is set to divide by 1 of fAD mode regardless of whether the PCLKO bit is set 4 When the PCLK5 bit and the SM43 bit in the S4C register 1 the pin function of SI O4 can be changed as follows P8_0 TA40UT U SIN4 P7 5 TA2IN W SOUTA P7 A TA2OUT W CLK4 5 SI O5 and SI O6 are only in the 128 pin version Figure 7 5 PCLKR Register Rev 1 10 Jul01 2005 page 40 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Clock Generating Circuit CANO 1 Clock Select Register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset C
73. 2 Pi Register 100 pin Version i 0 to 10 128 pin Version i 0 to 13 PC14 Register Figure19 8 shows the Pi register Data input output to and from external devices are accomplished by reading and writing to the Pi register The Pi register consists of a port latch to hold the input output data and a circuit to read the pin status For ports set for input mode the input level of the pin can be read by reading the corresponding Pi register and data can be written to the port latch by writing to the Pi register For ports set for output mode the port latch can be read by reading the corresponding Pi register and data can be written to the port latch by writing to the Pi register The data written to the port latch is output from the pin The bits in the Pi register correspond one for one to each port About the port P14 128 pin version Figure19 8 shows the PC14 register 19 3 PURj Register 100 pin Version j 0 to 2 128 pin Version j 0 to 3 Figures 19 9 and 19 10 show the PURj register The PURj register bits can be used to select whether or not to pull the corresponding port high in 4 bit unit The port selected to be pulled high has a pull up resistor connected to it when the direction bit is set for input mode When using the ports P11 to P14 set the PUR37 bit in the PUR3 register to 1 P11 to P14 are usable 19 4 PCR Register Figure19 11 shows the PCR register When the P1 register is read after setting the PCRO bit
74. AN7 pins as analog inputs A key input interrupt request is generated when the A D input voltage goes low The oAD frequency must be 10 MHz or less Without sample and hold function limit the AD frequency to 250 kHz or more With the sample and hold function limit the AD frequency to 1 MHz or more When changing an A D operation mode select analog input pin again in the CH2 to CHO bits in the ADCONO register and the SCAN1 to SCANO bits in the ADCON1 register Microcomputer ANi ANi ANO i and AN i i 0 to 7 NOTES 1 C1 2 0 47 uF C2 gt 0 47 uF C3 gt 100 pF C4 gt 0 1 uF reference 2 Use thick and shortest possible wiring to connect capacitors Figure 22 4 Use of Capacitors to Reduce Noise Rev 1 10 Jul01 2005 page 300 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution If the CPU reads the ADi register at the same time the conversion result is stored in the ADi register after completion of A D conversion an incorrect value may be stored in the ADi register This problem occurs when a divide by n clock derived from the main clock or a sub clock is selected for CPU clock When operating in one shot or single sweep mode Check to see that A D conversion is completed before reading the target ADi register Check the IR bit in the ADIC register to see if A D conversion is completed
75. Bit Set to 0 0 Divided by 16 WDC7 Prescaler Select Bit 1 Divided by 128 Watchdog Timer Start Register Symbol Address After Reset po WDTS 000Eh Indeterminate Function The watchdog timer is initialized and starts counting after a write instruction to this register The watchdog timer value is always initialized to 7FFFh regardless of whatever value is written 1 Write to the WDTS register after the watchdog timer interrupt request is generated Figure 10 2 WDC Register and WDTS Register 10 1 Count Source Protective Mode In this mode a on chip oscillator clock is used for the watchdog timer count source The watchdog timer can be kept being clocked even when CPU clock stops as a result of runaway Before this mode can be used the following register settings are required 1 Set the PRC1 bit in the PRCR register to 1 enable writes to the PM1 and PM2 registers 2 Set the PM12 bit in the PM1 register to 1 reset when the watchdog timer underflows 3 Set the PM22 bit in the PM2 register to 1 on chip oscillator clock used for the watchdog timer count source 4 Set the PRC1 bit in the PRCR register to 0 disable writes to the PM1 and PM2 registers b Write to the WDTS register watchdog timer starts counting Setting the PM22 bit to 1 results in the following conditions The on chip oscillator starts oscillating and the on chip oscillator clock becomes the watchdog timer
76. CICTLR register 1 Loop back mode enabled Figure 18 13 shows sub modes of the CAN operation mode Module idle TrmState 0 RecState 0 Start Detect transmission an SOF Finish Finish transmission reception Module transmits Module receives TrmState 1 TrmState 0 RecState 0 RecState 1 Lost in arbitration TrmState RecState Bits in CiSTR register i 0 1 Figure 18 13 Sub Modes of CAN Operation Mode 18 5 3 CAN Sleep Mode The CAN sleep mode is activated by setting the Sleep bit to 1 and the Reset bit to 0 in the CICTLR register It should never be activated from the CAN operation mode but only via the CAN reset initialization mode Entering the CAN sleep mode instantly stops the clock supply to the module and thereby reduces power dissipation 18 5 4 CAN Interface Sleep Mode The CAN interface sleep mode is activated by setting the CCLK3 or CCLK7 bit in the CCLKR register to 1 It should never be activated but only via the CAN sleep mode Entering the CAN interface sleep mode instantly stops the clock supply to the CPU Interface in the module and thereby reduces power dissipation Rev 1 10 Jul01 2005 page 214 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 18 CAN Module 18 5 5 Bus Off State The bus off state is entered according to the fault confinement rules of the CAN specif
77. CTS2 These are send control input pins RTSO to RTS2 These are receive control output pins CLKO to CLK6 9 These are transfer clock I O pins RXDO to RXD2 These are serial data input pins SING to SIN6 9 These are serial data input pins TXDO to TXD2 These are serial data output pins SOUTS to SOUT6 9 These are serial data output pins CLKS1 This is output pin for transfer clock output from multiple pins function I Input O NOTES SDAO to SDA2 These are serial data I O pins SCLO to SCL2 Output These are transfer clock I O pins except SCL2 for the N channel open drain output I O Input Output 1 In this manual hereafter VCC refers to VCC1 unless otherwise noted 2 Ask the oscillator maker the oscillation characteristic 3 INT6 to INT8 CLK5 CLK6 SIN5 SIN6 SOUT5 SOUTS are only in the 128 pin version Rev 1 10 Jul 01 2005 page 8 of 318 REJO9B0124 0110 RENESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 1 Overview Table 1 5 Pin Description 100 pin and 128 pin Versions 2 Signal Name Reference voltage input Pin Name VREF Oty SSC TT Applies the reference voltage for the A D converter and D A converter A D converter ANO to AN7 ANO 0 to ANO 7 AN2_0 to AN2 7 Analog input pins for the A D converter ADTRG
78. Clock Select Bit 1 4 PLL clack fs CM15 XIN XOUT Dus Capacity PE LOW eu Bit 6 HIGH b7 b6 0 0 No division mode ome dus Clock Division 0 1 Division by 2 mode Select Bit 1 7 1 0 Division by 4 mode 1 Division by 16 mode 1 Write to this register after setting the PRCO bit in the PRCR register to 1 write enable 2 If the CM10 bit is 1 stop mode XOUT goes H and the internal feedback resistor is disconnected The XCIN and XCOUT pins are placed in the high impedance state When the CM11 bit is set to 1 PLL clock or the CM20 bit in the CM2 register is set to 1 oscillation stop re oscillation detection function enabled do not set the CM10 bit to 1 3 When the PM22 bit in the PM2 register is set to 1 watchdog timer count source is on chip oscillator clock writing to the CM10 bit has no effect 4 Effective when the CMO7 bit is 0 and the CM21 bit is O 5 After setting the PLCO7 bit in the PLCO register to 1 PLL operation wait until tsu PLL elapses before setting the CM11 bit to 1 PLL clock 6 When entering stop mode from high or medium speed mode or when the CMO5 bit is set to 1 main clock turned off in low speed mode the CM15 bit is set to 1 drive capability high 7 Effective when the CMOS6 bit is 0 CM16 and CM17 bits enabled Figure 7 3 CM1 Register Rev 1 10 Jul01 2005 page 38 of 318 RENESAS REJ09B0124 0110 Under development This document is under developm
79. D6 D5 D4 D3i D2 D1 DO UiTB register 9 bits PRYE ART Clock pan SMD2 to SMDO UART synchronous type enabled UART 1 1 Y Clock 0 UARTI transmit register synchronous UART 7 bits disabled type Error signal output disable IOPOL n reverse 0 Clock synchronous type UiERE 1 SP Stop bit Fror sige output Reverse PAR Parity bit SMD2 to SMDO STPS PRYE IOPOL CKDIR Bits in UiMR register CLK1 to CLKO CKPOL CRD CRS Bits in VICO register UiERE Bit in UiC1 register Figure 14 4 UARTi Transmit Receive Unit Rev 1 10 Jul01 2005 page 131 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O UARTi Transmit Buffer Register i 0 to 2 b15 Symbol Address After Reset zd UOTB 03A3h to 03A2h Indeterminate U1TB O3ABh to 03AAh Indeterminate U2TB 01FBh to 01FAh Indeterminate Nothing is assigned When write set to 0 When read their contents are indeterminate 1 Use the MOV instruction to write to this register UARTi Receive Buffer Register i 0 to 2 b15 b8 Address After Reset b7 20 b Bo 03A7h to 03A6h Indeterminate 03AFh to 03AEh Indeterminate 01FFh to 01FEh Indeterminate Receive data D7 to DO Receive data D8 Nothing is assigned When write set to O When read their contents are 0 Arbitration Lost
80. Figure 2 1 shows the CPU registers The CPU has 13 registers Of these RO R1 R2 R3 AO A1 and FB comprise a register bank There are two register banks Data Registers Address Registers 1 Frame Base Registers 1 Interrupt Table Register The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL b Program Counter User Stack Pointer Interrupt Stack Pointer Static Base Register Flag Register Carry Flag Debug Flag Zero Flag Sign Flag Register Bank Select Flag Overflow Flag Interrupt Enable Flag Stack Pointer Select Flag Reserved Area Processor Interrupt Priority Level Reserved Area NOTE 1 These registers comprise a register bank There are two register banks Figure 2 1 CPU Registers 2 1 Data Registers RO R1 R2 and R3 The RO register consists of 16 bits and is used mainly for transfers and arithmetic logic operations R1 to R3 are the same as RO The RO register can be separated between high ROH and low ROL for use as two 8 bit data registers R1H and R1L are the same as ROH and ROL Conversely R2 and RO can be combined for use as a 32 bit data register R2R0 R3R1 is the same as R2RO 2 2 Address Registers A0 and A1 The AO register consists of 16 bits and is used for address register indirect addressing and address register relative addressing They also are used for transfers and arithmetic logic operations A1 is the same as AO I
81. Lock bit protects each block 8 commands 100 times Parallel I O standard serial I O and CAN I O modes are supported Boot ROM Area Program Method Erase Method Program and Erase Control Method Protect Method Number of Commands Program and Erase Endurance ROM Code Protection NOTES 1 The boot ROM area contains a standard serial I O mode and CAN I O mode rewrite control program which is stored in it when shipped from the factory This area can only be rewritten in parallel I O mode 2 Can be programmed in byte units in only parallel I O mode 3 Definition of program and erase endurance The programming and erasure times are defined to be per block erasure times For example assume a case where a 4K byte block A is programmed in 2 048 operations by writing one word at a time and erased thereafter In this case the block is reckoned as having been programmed and erased once If a product is guaranteed of 100 times of programming and erasure each block in it can be erased up to 100 times 3 Table 20 2 Flash Memory Rewrite Modes Overview Flash Memory Rewrite Mode Function CPU Rewrite Mode Standard Serial I O Mode Parallel I O Mode CAN I O Mode The user ROM area is rewritten when the CPU executes software commands EWO mode Rewrite in areas other than flash memory EW1 mode Can be rewritten in the flash memory The user ROM area is rewritten using a dedicated serial progra
82. Oto P10 7 P11 OtoP11 P12 0to P12 7 P13 0to P13 7 P14 0 P14 XIN RESET CNVSS BYTE Pull up Resistance PO 0 to PO 7 P1 0 to P1 7 P2 0 to P2 P3 0 to P3 7 P4 0 to P4 7 P5 0 to P5 P6 Oto P6 7 P7 0 P7 210 P7 7 P8 0to P8 P8 6 P8 7 P9 0 P9 2to P9 7 P10 Oto P10 P11 0toP11 7 P12 0toP12 7 P13 OtoP13 7 P14 0 P14 1 7 7 4 7 Feedback Resistance XIN Feedback Resistance XCIN RAM Retention Voltage At stop mode NOTES 1 Referenced to VCC 3 0 to 5 5V VSS OV at Topr 40 to 85 C f BCLK 24MHz unless otherwise specified 2 P11 to P14 INT6 to INT8 CLK5 CLK6 SIN5 and SING are only in the 128 pin version Rev 1 10 Jul01 2005 page 272 of 318 REJO9B0124 0110 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Electric Characteristics Table 21 5 Electrical Characteristics 2 Standard Min Typ Max Parameter Measuring Condition Power Supply Output pins are open Mask ROM f BCLK 24MHz Current and other pins are VSS PLL operation VCC 3 0 to 5 5V No division On chip oscillation No division Flash Memory f BCLK 24MHz PLL operation No division On chip oscillation No division Flash Memory f BCLK 10MHz Program VCC 5V Flash Memory f BCLK 10MHz Erase VCC 5V Mask ROM f BCLK 32kHz Low
83. P14 Input mode except for P8 5 1 Input mode Output mode NMI XOUT AVCC BYTE NOTE 1 The ports P11 to P14 are only in the 128 pin version When not using all of the P11 to p14 pins may be left open by setting the PU37 bit in the PURS register to 0 P11 to P14 unusable without causing any problem Figure 19 12 Unassigned Pins Handling Rev 1 10 Jul01 2005 page 237 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Flash Memory Version 20 Flash Memory Version Aside from the built in flash memory the flash memory version microcomputer has the same functions as the masked ROM version In the flash memory version the flash memory can perform in four rewrite mode CPU rewrite mode standard serial I O mode parallel I O mode and CAN I O mode Table 20 1 lists the specifications of the flash memory version See Tables 1 1 and 1 2 Performance outline for the items not listed in Table 20 1 Table 20 2 shows the outline of flash memory rewrite mode Table 20 1 Flash Memory Version Specifications Flash Memory Operating Mode 4 modes CPU rewrite standard serial I O parallel I O CAN I O Erase Block User ROM Area See Figure 20 1 Flash Memory Block Diagram 1 block 4 Kbytes In units of word in units of byte Collective erase block erase Program and erase controlled by software command
84. Select the transfer clock polarity UFORM Select the LSB first or MSB first TE Set this bit to 1 to enable transmission reception TI Transmit buffer empty flag RE Set this bit to 1 to enable reception RI Reception complete flag U2IRS 2 Select the source of UART2 transmit interrupt U2RRM 2 Set this bit to 1 to use continuous receive mode UiLCH Set this bit to 1 to use inverted data logic UiERE Set to 0 0 to 7 Set to 0 0 to 7 Set to 0 0 to 2 Set to 0 NODC Select clock output mode 4 to7 Set to 0 0 to 7 Set to 0 UOIRS U1IRS Select the source of UARTO UART1 transmit interrupt UORRM U1RRM Set this bit to 1 to use continuous receive mode CLKMDO Select the transfer clock output pin when the CLKMD1 bit 1 CLKMD1 Set this bit to 1 to output UART1 transfer clock from two pins RCSP Set this bit to 1 to accept as input the UARTO CTSO signal from the P6_4 pin f i20to2 NOTES 1 Not all register bits are described above Set those bits to 0 when writing to the registers in clock Set to 0 synchronous serial I O mode 2 Set the bit 4 and bit 5 in the UOC1 and U1C1 registers to 0 The UOIRS U1IRS UORRM and U1RRM bits are in the UCON register Rev 1 10 Jul01 2005 page 139 of 318 RENESAS REJ09B0124 0110 14 Serial I O
85. Source Sgr d Direction ee Fixed Select Bit 2 Forward Nothing is assigned When write set to 0 b7 b6 When read their contents are O Destination dium n Fixed Direction Select Bit 2 Forward 1 The DMAS bit can be set to 0 by writing 0 in a program This bit remains unchanged even if 1 is written 2 At least one of the DAD and DSD bits must be 0 address direction fixed Figure 11 3 DM1SL Register DMOCON and DM1CON Registers Rev 1 10 Jul 01 2005 page 85 of 318 REJ09B0124 0110 7tENESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 11 DMAC DMAi Source Pointer i 0 1 i 5d b16 b15 b8 b0 b7 b0 b7 bo Symbol Address After Reset xo Xx MS a SARO 0022h to 0020h Indeterminate SAR1 0032h to 0030h Indeterminate Set the source address of transfer 00000h to FFFFFh Nothing is assigned When write set to 0 When read their contents are 0 1 If the DSD bit in the DMiCON register is 0 fixed this register can only be written to when the DMAE bit in the DMiCON register is 0 DMA disabled If the DSD bit is 1 forward direction this register can be written to at any time If the DSD bit is 1 and the DMAE bit is 1 DMA enabled the DMAi forward address pointer can be read from this register Otherwise the value written to it can be read DMAi Destination Pointer i 0 1 eu b
86. Standard Condition Min Typ Max STOP Release Time Low Power Dissipation Mode Wait Mode Release Time ta P R Time for Internal Power Supply Stabilization During Powering On ta R s STOP Release Time ta w s Low Power Dissipation Mode Wait Mode Release Time CPU clock ULIL Interrupt for a Stop mode release or b b Wait mode release CPU clock ULIL Figure 21 2 Power Supply Circuit Timing Diagram Rev 1 10 Jul01 2005 page 275 of 318 REJ09B0124 0110 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Electric Characteristics Timing Requirements Referenced to VCC 5V VSS OV at Topr 40 to 85 C unless otherwise specified Table 21 11 External Clock Input XIN Input Standard Min Max Parameter External Clock Input Cycle Time External Clock Input HIGH Pulse Width External Clock Input LOW Pulse Width External Clock Rise Time External Clock Fall Time Standard Min Max Parameter TAIIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Standard Min Max Parameter TAIIN Input Cycle Time TAIIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Standard Min Max Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pul
87. When SMi4 bit in SiC register 0 Generation Timing The rising edge of the last transfer clock pulse e When SMi4 bit 1 The falling edge of the last transfer clock pulse CLKi Pin Function I O port transfer clock input transfer clock output SOUTI Pin Function I O port transmit data output high impedance SINi Pin Function I O port receive data input Select Function LSB first or MSB first selection Whether to start sending receiving data beginning with bit O or beginning with bit 7 can be selected Function for setting an SOUTI initial value set function When the SMi6 bit in the SiC register 0 external clock the SOUTi pin output level while not transmitting can be selected CLK polarity selection Whether transmit data is output input timing at the rising edge or falling edge of transfer clock can be selected i 3 to 6 5 and 6 are only in the 128 pin version NOTES 1 To set the SMi6 bit in the SiC register to 0 external clock follow the procedure described below If the SMi4 bit in the SiC register 0 write transmit data to the SITRR register while input on the CLKi pin is high The same applies when rewriting the SMi7 bit in the SiC register If the SMi4 bit 1 write transmit data to the SiTRR register while input on the CLKi pin is low The same applies when rewriting the SMi7 bit Because shift operation continues as long as the transfer clock is supplied to the SI Oi circuit stop
88. a registered trademark of Koninklijke Philips Electronics N V 2 IEBus is a registered trademark of NEC Electronics Corporation option All options are on request basis Rev 1 10 Jul01 2005 page 3 of 318 REJ09B0124 0110 7tENESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 1 3 Block Diagram Figure 1 1 shows a block diagram of M16C 6N Group M16C 6NK M16C 6NM Port PO Port P1 Port P2 Port P3 Port P4 Port P5 1 Overview IT Port P o Internal peripheral functions Timer 16 bits Output timer A 5 Input timer B 6 Three phase motor control circuit A D converter 10 bits X 8 channels Expandable up to 26 channels UART or Clock synchronous serial I O 3 channels System clock generating circuit XIN XOUT XCIN XCOUT PLL frequency synthesizer On chip oscillator Clock synchronous serial I O 8 bits X 4 channels Zd uod 8d HOd CRC arithmetic circuit CCITT Polynomial X X X 1 CAN module 2 channels t Watchdog timer 15 bits M16C 60 series CPU core Memory ROH ROL R1H R1L SB ROM DMAC 2 channels D A converter 8 bits X 2 channels RAM Multiplier Ta 8 ord uod 6d voa S 84 uoa Port P14 1 ROM size depends on microcomputer
89. a registered trademark of Koninklijke Philips Electronics N V 2 IEBus is a registered trademark of NEC Electronics Corporation option All options are on request basis Rev 1 10 Jul01 2005 page 2 of 318 REJ09B0124 0110 100 pin plastic mold LQFP 134 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 1 Overview Table 1 2 Performance Outline of M16C 6N Group 128 pin Version M16C 6NM Number of Basic Instructions 91 instructions Performance Normal ver T V ver Minimum Instruction Execution Time 41 7ns f BCLK 24MHz 1 1 prescaler without software wait 50 0ns f BCLK 20MHz 1 1 prescaler without software wait Operation Mode Single chip mode Address Space 1 Mbyte Memory Capacity See Table 1 3 Product List Peripheral Function Port Input Output 113 pins Input 1 pin Multifunction Timer Timer A 16 bits X 5 channels Timer B 16 bits X 6 channels Three phase motor control circuit Serial I O 3 channels Clock synchronous UART I C bus IEBus 4 channels Clock synchronous A D Converter 10 bit A D converter 1 circuit 26 channels D A Converter 8 bits X 2 channels DMAC 2 channels CRC Calculation Circuit CRC CCITT CAN Module 2 channels with 2 0B specification Watchdog Timer 15 bits X 1 channel with p
90. a time stamp value is stored in a reception slot 18 14 Listen Only Mode When the RXOnly bit in the CiCTLR register i 0 1 is set to 1 the module enters listen only mode In listen only mode no transmission such as data frames error frames and ACK response is performed to bus When listen only mode is selected do not request the transmission Rev 1 10 Jul01 2005 page 221 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 18 CAN Module 18 15 Reception and Transmission Table 18 3 shows configuration of CAN reception and transmission mode Table 18 3 Configuration of CAN Reception and Transmission Mode Communication environment configuration mode configure the communication mode of the slot Configured as a reception slot for a data frame Configured as a transmission slot for a remote frame At this time the RemActive 1 After completion of transmission this functions as a reception slot for a data frame At this time the RemActive 0 However when an ID that matches on the CAN bus is detected before remote frame transmission this immediately functions as a reception slot for a data frame Configured as a transmission slot for a data frame Configured as a reception slot for a remote frame At this time the RemActive 1 After completion of reception this functions as a transmission slot
91. aee as el adu tenes ne 61 9 2 9 BRK Intertupt ei tee erred S 61 9 2 4 INT Instruction Interruptor ic 61 9 3 Hardware Interrupts urinaria 62 9 3 1 Special Itterf pts xum irc cere pe eene lets tobas 62 9 3 2 Peripheral Function Interr pts ii etnia nibhr letal Rede d 62 9 4 Interrupts and Interrupt Vector civic iris cate A c er sn add k deep eo onn etd eae naL on EE CAR 63 aaro Vector TablOS vitalicia 63 9 4 2 Relocatable Vector Tabl65 2 eee ia ea 63 9 5 interrupt Contr Olssen a a A ii 65 ea SET E DUE A 67 9 52 67 9 5 3 IEVIE2 to IEVEO BitS and P E ossi ld rd 67 9 54 Initerr pt Sequence ie testor ut a e repe a rer ti tie traia 68 9 5 5 Interrupt Response UNIS ias din 69 9 5 6 Variation of IPL when Interrupt Request is Accepted coooococonocccinocccconoccnoncaninncnonanacan cnn nannncnnna canon 69 9 5 7 SAVING Heglstels x naa 70 9 5 8 Returning from an Interrupt Routine sissisodan aiiai ai aiaia 71 9 5 9 Interrupt PriOnity iii A iii 71 9 5 10 Interrupt Priority Resolution Circuit sessesessseseseseseeeeeeeennee nnne rana 71 A IPTE 73 A auccm NORR Eee mete Ra uem uude pata he ayer ded Load deg emus 77 SEM valet aniio 77 9 9 CANO 1 Wakesup Intetr pt cootra aiia eiii 77 9 10 Address Match Interr pt imita A ae ideas 78 10 Watchdog TIMET NEM 80 10 1 Count So rce Protective MOC sess comio tror c
92. and 18 5 show the CiGMR register i 0 1 the CILMAR register and the CiLMBR register in which bit mapping in byte access and word access are shown Addresses CANO 0160h 0161h gt gt lt gt lt gt lt gt lt EID17 ElD16 EID15 EID14 016Eh i20 1 NOTES 1 E is undefined CAN1 0360h 0361h 0362h 0363h 0364h 0366h 0367h 0368h 0369h 036Ah 036Ch 036Dh 036Eh 036Fh 0370h 2 These registers can be written in CAN reset initialization mode of the CAN module Figure 18 4 Bit Mapping of Mask Registers in Byte Access b8 Sos so S07 sel lt lt sos sis sos soz s AA E A Eoen lt lt es ios E eoa eo lt lt TT T A E A EE c ev gt lt gt lt 805 e104 103 8102 e10 eroo gt lt gt gt LALA gt lt gt lt sutdsipe sing sib7 sips gt lt 7 SIbs SIb4 sa SID2 SID Lees eptz ert ero E09 eroe E107 eroe Lo pL ens ei4 eros ere E101 eoo gt lt gt lt gt lt gt lt gt lt LLL i2 0 1 NOTES 1 E is undefined 2 These registers can be written in CAN reset initialization mode of the CAN module Figure 18 5 Bit Mapping of Mask Registers in Word Access Rev 1 10 Jul01 2005 page 206 of 318 RENESAS REJ09B0124 0110 Addresses CANO 0160h 0162h 0164h 0166h 0168h 016Ah 016Ch 016Eh 0170h CAN1 0360h 0362h 0364h 0366h 0368h 036Ah 036Ch 036Eh 0370h gt CiGMR register gt Ci
93. and CMO7 bits all to 0 on chip oscillator turned off and the CMO5 bit 1 main clock turned off the CMO6 bit is fixed to 1 divide by 8 mode and the CM15 bit is fixed to 1 drive capability High During external clock input set the CMO5 bit to 0 oscillate When the CMO5 bit is set to 1 the XOUT pin goes H Furthermore because the internal feedback resistor remains connected the XIN pin is pulled H to the same level as XOUT via the feedback resistor When entering stop mode from high or medium speed mode on chip oscillator mode or on chip oscillator low power dissipation mode the CMO6 bit is set to 1 divide by 8 mode 11 After setting the CMO4 bit to 1 XCIN XCOUT oscillator function wait until the sub clock oscillates stably before switching the CMO7 bit from 0 to 1 sub clock 12 To return from on chip oscillator mode to high speed or medium speed mode set the CM06 and CM15 bits both to 1 Figure 7 2 CMO Register Rev 1 10 Jul 01 2005 page 37 of 318 REJO9B0124 0110 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Clock Generating Circuit System Clock Control Register 1 b7 b6 b5 b4 b3 b2 bi bO LT lololo Symbol Address After Reset CM1 0007h 00100000b T Br Symbol RW L CM10 All a Stop Control ut Clock on Bit 2 All clocks off stop mode de Main vut CM11 System
94. and P8 0 to P8 4 must be 40mA max The total lon peak for ports P8 6 P8 7 P9 P10 P11 P14 0 and P14 1 must be 40mA max 4 P11 to P14 are only in the 128 pin version Rev 1 10 Jul01 2005 page 270 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Table 21 3 Recommended Operating Conditions 2 f XIN 1 Parameter Main Clock Input Oscillation No Wait Mask ROM Version VCC 3 0 to 5 5V 3 4 Frequency Flash Memory Version 21 Electric Characteristics Standard Typ f XCIN Sub Clock Oscillation Frequency On chip Oscillation Frequency Ring PLL PLL Clock Oscillation Frequency f BCLK CPU Operation Clock VCC 3 0 to 5 5V tsu PLL PLL Frequency Synthesizer Stabilization Wait Time ftrippie Power Supply Ripple Allowable Frequency VCC V P P ripple Power Supply Ripple Allowable Amplitude Voltage VCC 5V VCC 3V V CC AV ATI NOTES Power Supply Ripple Rising Falling Gradient VCC 5V 1 Referenced to VCC 3 0 to 5 5V at Topr 40 to 85 C unless otherwise specified 2 Relationship between main clock oscillation frequency and supply voltage is shown right 3 Execute program erase of flash memory by VCC 3 3 0 3 V or VCC 5 0 0 5 V 4 When using 16MHz and over use PLL clock PLL
95. any space other than the flash memory e g RAM before being executed The rewrite control program can be executed in the user ROM area Space which can be Rewritten User ROM area User ROM area However this excludes blocks with the rewrite control program Software Command Restriction Program and block erase commands cannot be executed in a block having the rewrite control program Erase all unlocked block command cannot be executed when the lock bit in a block having the rewrite control program is set to 1 unlocked or when the FMRO 2 bit in the FMRO register is set to 1 lock bit disabled Read status register command cannot be used Modes after Program or Erasing Read status register mode Read array mode CPU Status during Auto Write and Auto Erase Operating Maintains hold state I O ports maintains the state before the command was executed Flash Memory Status Detection NOTES Read the FMROO FMRO6 and FMRO7 bits in the FMRO register by program Execute the read status register command to read the SR7 SR5 and SR4 bits in the status register Read the FMROO FMRO6 and FMRO7 bits in the FMRO register by program 1 Do not generate an interrupts except NMI and watchdog timer interrupts and DMA transfer 2 When in CPU rewrite mode the PM10 and PM13 bits in the PM1 register are set to 1 The rewrite control program can only be executed in
96. at the falling edge of the clock pulse of 9th bit If the ABT bit needs to be updated per byte set the ABT bit to O undetected after detecting acknowledge in the first byte before transferring the next byte Setting the ALS bit in the UISMR2 register to 1 SDA output stop enabled causes arbitration lost to occur in which case the SDAi pin is placed in the high impedance state at the same time the ABT bit is set to 1 unmatching detected Rev 1 10 Jul01 2005 page 160 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O 14 1 3 4 Transfer Clock Data is transmitted received using a transfer clock like the one shown in Figure 14 24 The CSC bit in the UiSMR2 register is used to synchronize the internally generated clock internal SCLi and an external clock supplied to the SCLi pin In cases when the CSC bit is set to 1 clock synchronization enabled if a falling edge on the SCLi pin is detected while the internal SCLi is high the internal SCLi goes low at which time the value of the UiBRG register is reloaded with and starts counting in the low level interval If the internal SCLi changes state from low to high while the SCLi pin is low counting stops and when the SCLi pin goes high counting restarts In this way the UARTi transfer clock is comprised of the logical product of the internal SCLi
97. bit to 0 falling edge of a one shot pulse of the timer A1 A2 A4 Figure 13 3 INVC1 Register Rev 1 10 Jul01 2005 page 120 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Three Phase Motor Control Timer Function Three Phase Output Buffer Register i i 0 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address E m IDBO IDB1 01CAh 01CBh EIE E MEM Dui u Phase U Phase Output Buffer i Buffer i Write output level DUBi U Phase Output Buffer i 9 Active level E i 1 Inactive level DVi V Phase Output Buffer i RW DVBi V Phase Output Buffer i When read the value of the three RW W Phase Output Buffer i phase shift register is read RW W Phase Output Buffer i RW Reserved Bit Set to 0 1 Values of the IDBO and IDB1 registers are transferred to the three phase output shift register by a transfer trigger After the transfer trigger occurs the values written in the IDBO register determine each phase output signal first Then the value written in the IDB1 register on the falling edge of timers A1 A2 and A4 one shot pulse determines each phase output signal Dead Time Timer 2 bo After Reset If setting value is n the timer stops when counting n times a count source selected by the INV12 bit in the INVC1 register after start trigger occurs 1 to 255 WO Positi
98. channel is set to 1 DMA requested at the same time In this case the DMA requests are arbitrated according to the channel priority DMAO gt DMA1 The following describes DMAC operation when DMAO and DMA1 requests are detected active in the same sampling period Figure 11 6 shows an example of DMA transfer effected by external factors In Figure 11 6 DMAO request having priority is received first to start a transfer when a DMAO request and DMA1 request are generated simultaneously After one DMAO transfer is completed a bus arbitration is returned to the CPU When the CPU has completed one bus access a DMA1 transfer starts After one DMA1 transfer is completed the bus arbitration is again returned to the CPU In addition DMA requests cannot be counted up since each channel has one DMAS bit Therefore when DMA requests as DMA1 in Figure 11 6 occurs more than one time the DMAS bit is set to 0 as soon as getting the bus arbitration The bus arbitration is returned to the CPU when one transfer is completed An example where DMA requests for external causes are detected active at the same time a DMA transfer is executed in the shortest cycle BCLK DMAO C ee I Bus arbitration INTO cu ZO Willis TZ DMAO EN request bit INT1 DMA1 request bit
99. clock XCINC De On chi oscllalor clock Set the CPSR bit in the Reset CPSRF register to 1 prescaler reset f1 or f2 f8 32 1032 Timer B2 overflow or underflow to a count source of theTimer A TCK1 to TCKO 00 xs 1 TMOD1 to TMODO 00 Timer mode 10 Pulse width period measuring mode Timer BO interrupt Timer BO Noise 5 filter TCKO TMOD1 to TMODO 00 Timer mode 10 Pulse width period measuring mode Timer B1 interrupt Noise filter TCKO TMOD to TMODO 00 Timer mode 10 Pulse width period measuring mode Timer B2 interrupt Timer B2 Noise 7 filter TCKO 01 Event counter mode TMOD1 to TMODO 00 Timer mode 10 Pulse width period measuring mode Timer B3 interrupt Noise filter TCKO TTMOD1 to TMODO 00 Timer mode 10 Pulse width period measuring mode Timer B4 interrupt filter TCKO TMOD1 to TMODO 00 Timer mode 10 Pulse width period measuring mode Timer B5 interrupt filter PCLKO Bit in PCLKR register TCK1 to TCKO TMOD1 to TMODO Bits in TBiMR register i 0 to 5 NOTE 1 Be aware that TB5IN shares the pin with RXD2 SCL2 and TAOIN Figure 12 2 Timer B Configuration Rev 1 10 Jul01 2005 page 93 of 318 RENESAS REJ09B0124 0110 Under development This document is under developm
100. clock oscillation frequency which can be used is 16MHz 20MHz or 24MHz f ripple Power Supply Ripple Allowable Frequency VCC VP P ripple Power Supply Ripple Allowable Amplitude Voltage f ripple VCC 3V f XIN operating maximum frequency MHz ak o o o o 3 0 5 5 VCC V main clock no division VCC wae e VP P ripple Figure 21 1 Timing of Voltage Fluctuation Rev 1 10 Jul01 2005 page 271 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Electric Characteristics Table 21 4 Electrical Characteristics 1 HIGH Output Voltage Parameter PO 0 to PO 7 P1 0 to P1 7 P2 0 to P2 7 P3 0 to P3 7 P4 0 to P4 7 P5 0 to P5 7 P6 0to P6 7 P7 0 P7 210 P7 7 PB Oto P8 4 P8 6 P8 7 P9 0 P9 2to P9 7 P10 Oto P10 7 P11 0toP11 7 P12 0toP12 7 P13 Oto P13 7 P14 0 P14 1 Measuring Condition Standard Min Typ Max HIGH Output Voltage PO 0 to PO 7 P1 0 to P1 7 P2 0 to P2 P3 0 to P3 7 P4 0 to P4 7 P5 0 to P5 P6 0to P6 7 P7 0 P7 210 P7 7 P8 Oto P8 P8 6 P8 7 P9 0 P9 2to P9 7 P10 Oto P10 P11 0toP11 7 P12 0toP12 7 P13 Oto P13 P14 0 P14 1 lon 200pA HIGH Output Voltage XOUT HIGHPOWER lou 1mA LOWPOWER lou 0 5mA HIGH Output Voltage XCOUT HIGHPOWER
101. combinations of transfer clock phases and polarities can be selected using the CKPH bit in the UISMR3 register and the CKPOL bit in the UiCO register Make sure the transfer clock polarity and phase are the same for the master and salves to be communicated Figure 14 28 shows the transmission and reception timing in master internal clock Figure 14 29 shows the transmission and reception timing CKPH 0 in slave external clock Figure 14 30 shows the transmission and reception timing CKPH 1 in slave external clock Clock output CKPOL 0 CKPH 0 Clock output CKPOL 1 CKPH 0 Clock output CKPOL 0 CKPH 1 Clock output CKPOL 1 CKPH 1 Data output timing il Do X Di X D2 X Da X n4 X ps X pe D7 Data input timing i i 1 1 f i 1 Figure 14 28 Transmission and Reception Timing in Master Mode Internal Clock Rev 1 10 Jul01 2005 page 166 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O Slave control input Clock input H CKPOL 0 CKPH 0 Clock input H CKPOL 1 CKPH 0 Data output timing Data input timing ES v A Ano A or A De ns X bs os A oo A br 1t1f10111 Figure 14 29 Transmission and Reception Timing CKPH z 0 in Slave Mode External Clock Slave control input Clock input H CKPOL 0 CKPH 1 Clock input H CK
102. control circuit Clock synchronous type 001 Clock synchronous type when internal clock is selected No 1 Clock synchronous type when external clock is selected CKDIR Clock synchronous type when internal clock is selected CLK2 O reversing circuit lt CTS RTS disabled CTS RTS selected CTS2 ATS2 O T CTS RTS disabled n2 Values set to the U2BRG register PCLK1 Bit in PCLKR register SMD2 to SMDO CKDIR Bits in U2MR register CLK1 to CLKO CKPOL CRD CRS Bits in U2CO register Figure 14 3 UART2 Block Diagram Rev 1 10 Jul 01 2005 page 130 of 318 REJ09B0124 0110 131 NESAS Transmit receive unit 14 Serial I O TXD polarity reversing circuit 1 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O IOPOL No reverse 0 RXD data d C reverse circuit qe Reverse Clock synchronous type UART 7 bits PRYE clock UART PAR synchronous 8 bits ART T bi disabled type H 7 bits UARTi receive register 0 ed UART mE Clock synchronous type SMD2 to SMDO 9 bits UART 8 bits UART 9 bits D7 D6 D5 D4 D3 D2 D1 DO UB register Data bus high order bits 4 Data bus low order bits V D7
103. count source Watchdog timer count 32768 Watchdog timer period on chip oscillator clock The CM10 bit in the CM1 register is disabled against write Writing a 1 has no effect nor is stop mode entered The watchdog timer does not stop when in wait mode or hold state Rev 1 10 Jul01 2005 page 81 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 11 DMAC 11 DMAC The DMAC Direct Memory Access Controller allows data to be transferred without the CPU intervention Two DMAC channels are included Each time a DMA request occurs the DMAC transfers one 8 or 16 bit data from the source address to the destination address The DMAC uses the same data bus as used by the CPU Because the DMAC has higher priority of bus control than the CPU and because it makes use of a cycle steal method it can transfer one word 16 bits or one byte 8 bits of data within a very short time after a DMA request is generated Figure 11 1 shows the block diagram of the DMAC Table 11 1 shows the DMAC specifications Figures 11 2 to 11 4 show the DMAC related registers Address bus DMAO source pointer SARO Lo DMAO destination pointer DARO DMAO forward address pointer 1 El DMAO transfer counter reload register TCRO i DMA1 source pointer SAR1 gt DMA1 destination pointer DAR1 C o U y DMA1 transfer counter reloa
104. document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Clock Generating Circuit Figure 7 12 shows the state transition from normal operation mode to stop mode and wait mode Figure 7 13 shows the state transition in normal operation mode Table 7 7 shows a state transition matrix describing allowed transition and setting The vertical line shows current state and horizontal line show state after transition All oscillators stopped Stop Mode Interrupt Stop Mode CM10 2 109 Interrupt CM10 1 3 CM10 1 5 Stop Mode Interrupt CM10 1 65 Stop Mode Interrupt 4 CMO05 CM06 CMO7 Bits in CMO register CM10 CM11 Bits in CM1 register NOTES Medium Speed Mode divided by 8 mode High Speed Mode Medium Speed Mode PLL Operation Mode Low Speed Mode Low Power Dissipation Mode On chip Oscillator Mode On chip Oscillator Dissipation Mode Normal Mode 1 Do not go directly from PLL operation mode to wait or stop mode 2 PLL operation mode can be entered from high speed mode Similarly PLL operation mode can be changed back to high speed mode 3 Write to the CMO and CM1 registers per 16 bits with the CM21 bit in the CM2 register 0 on chip oscillator stops Since the operation starts from the main clock after exiting stop mode the time until the CPU operates can be reduced 4 The on chip oscillator clock divided by 8 provides the CPU cl
105. document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 18 CAN Module 18 12 Return from Bus Off Function When the protocol controller enters bus off state it is possible to make it forced return from bus off state by setting the RetBusOff bit in the CiCTLR register i 0 1 to 1 Force return from bus off At this time the error state changes from bus off state to error active state If the RetBusOff bit is set to 1 the CIRECR and CiTECR registers are initialized and the State BusOff bit in the CISTR register is set to 0 CAN module is not in error bus off state However registers of the CAN module such as CiCONR register and the content of each slot are not initialized 18 13 Time Stamp Counter and Time Stamp Function When the CiTSR register i 0 1 is read the value of the time stamp counter at the moment is read The period of the time stamp counter reference clock is the same as that of 1 bit time that is configured by the CiCONR register The time stamp counter functions as a free run counter The 1 bit time period can be divided by 1 undivided 2 4 or 8 to produce the time stamp counter reference clock Use the TSPreScale bit in the CiCTLR register to select the divide by n value The time stamp counter is equipped with a register that captures the counter value when the protocol controller regards it as a successful reception The captured value is stored when
106. each mode for register setting Rev 1 10 Jul01 2005 page 128 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Main clock PLL clock or on chip oscillator clock UARTO RXD polarity RXDO O hs PCLK1 f2SIO f1SIO ey gt Nol nisio orf2SIO Lo f8SIO f32SIO 14 Serial I O Clock source selection CLK1 00h f1SIO or f2SIO 4 Oth t8sio 1h fa2sio 10h toCLKO ckpin Internal UOBRG register H 1 n0 1 UART reception SMD2 to SMDO 010 100 101 110 Clock synchronous type 001 p Reception control circuit UART transmission d AA 010 100 101 110 Transmission ro External lock synchronous type control circuit 001 Clock synchronous type when internal clock 5 selected T o 4 CKPOL Clock synchronous type cLKo Q4 CLK when internal clock is selected polarity Clock synchronous type when external clock is selected CKDIR 4 reversing circuit CTS RTS selected CTS RTS disabled CTS O Lot RTSO VSS 0 1 CRS 0 TS RTS disabled 5 Receive clock Transmit clock Transmit receive unit TX
107. erase operation is completed the FMRO6 FMRO7 bits in the FMRO register are set to 1 indicating a specific error Therefore execution results can be confirmed by check ing these bits full status check Table 20 6 lists errors and FMRO register state Figure 20 12 shows a flow chart of the full status check and handling procedure for each error 20 Flash Memory Version Table 20 6 Errors and FMRO Register Status FRMOO Register Status Register Status FMRO7 bit FMRO6 bit SR5 SR4 Command Sequence error Error Occurrence Conditions Command is written incorrectly A value other than xxDOh or xxFFh is written in the second bus cycle of the lock bit program block erase or erase all unlocked block command Erase error e The block erase command is executed on a locked block The block erase or erase all unlocked block command is executed on an unlock block and auto erase operation is not completed as expected NOTES Program error e The program command is executed on locked blocks The program command is executed on unlocked blocks but program operation is not completed as expected The lock bit program command is executed but program operation is not completed as expected 1 The flash memory enters read array mode by writing command code xxFFh in the second bus cycle of these commands The command code written in the first bus cycle becomes invalid 2 When
108. fed to the CLKi input pin When successively receiving data if all bits of the next receive data are prepared in the UARTI receive register while the RI bit in the UiC1 register 1 data present in the UiRB register an overrun error occurs and the OER bit in the UiRB register is set to 1 overrun error occurred In this case because the content of the UiRB register is indeterminate a corrective measure must be taken by programs on the transmit and receive sides so that the valid data before the overrun error occurred will be retransmitted Note that when an overrun error occurred the IR bit in the SiRIC register does not change state To receive data in succession set dummy data in the lower order byte of the UiTB register every time reception is made When an external clock is selected the conditions must be met while if the CKPOL bit 0 the external clock is in the high state if the CKPOL bit 1 the external clock is in the low state The RE bit in the UiC1 register 1 reception enabled The TE bit in the UiC1 register 1 transmission enabled The TI bit in the UiC1 register O data present in the UiTB register Rev 1 10 Jul01 2005 page 297 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 11 2 Special Modes 22 11 2 1 Special Mode 1 C Mode When generating start stop an
109. from address 004Eh to address 004Dh Use the IFSROS5 bit in the IFSRO register to select The S6IC register is only in the 128 pin version In the 100 pin version set the IFSRO5 bit to 0 Timer BO When the IFSRO bit in the IFSRO register 0 CANO 1 wake up or error CANO 1 wake up is selected When the IFSRO2 bit 1 CANO wake up error or CAN1 wake up error CANO wake up error is selected 9 When the IFSRO 2 bit 0 CANO 1 error is selected When the IFSRO2 bit 1 CAN1 wake up error is selected Figure 9 3 Interrupt Control Registers 1 Rev 1 10 Jul 01 2005 page 65 of 318 REJ09B0124 0110 7tENESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 9 Interrupt Interrupt Control Register Symbol Address After Reset INT3IC 0044h XX00X000b C1RECIC S4IC INT5IC 6 0048h XX00X000b C1TRMIC S3IC INT4IC 7 0049h XX00X000b b7 b6 b5 b4 b3 b2 bi b0 INTOIC to INT2IC 005Dh to 005Fh XX00X000b X NZ TA2IC INT7IC 8 0057h XX00X000b bol lll TA3IC INT6IC 9 0058h XX00X000b TB1IC INT8IC 10 XX00X000b Bit Symbol Level 0 interrupt disabled Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Interrupt Priority Level Select Bit Interrupt not requested Interrupt requested a Selects falling edge ER Polarity Select Bit Selects EA pesar e Interrupt Request Bit 65 ReewedBt Bit Seto to 0
110. function which gets the microcomputer out of wait or stop mode However if you intend to use the key input interrupt do not use P10 4 to P10 7 as analog input ports Figure 9 14 shows the block diagram of the key input interrupt Note however that while input on any pin which has had the PD10 4 to PD10 7 bits set to 0 input mode is pulled low inputs on all other pins of the port are not detected as interrupts L PU25 bit in PUR register PD10 7 bit in PD10 register PD10 7 bit in PD10 register Pull up transistor O Pull up PD10 6 bit in transistor PD10 register Key input interrupt request O Y Interrupt control circuit gt Pull up PD10_5 bit in transistor PD10 register o PD10 4 bit in Pul up PD10 register transistor Figure 9 14 Key Input Interrupt Block Diagram 9 9 CANO 1 Wake up Interrupt CANO 1 wake up interrupt request is generated when a falling edge is input to CRXO or CRX1 One interrupt is allocated to CANO 1 The CANO 1 wake up interrupt is enabled only when the PortEn bit 1 CTX CRX function and Sleep bit 1 Sleep mode enabled in the CiCTLR register i 0 1 Figure 9 15 shows the block diagram of the CANO 1 wake up interrupt Please note that the wake up message will be lost Sleep bit in COCTLR register PortEn bit in COCTLR register C01WKIC register CRX0 O Sleep bit in C1CTLR register Interrupt control CANO 1 wake up circuit interrupt
111. functions for standard serial l O mode Figures 20 13 and 20 14 show pin connections for standard serial l O mode 20 4 1 ID Code Check Function The ID code check function determines whether the ID codes sent from the serial programmer matches those written in the flash memory Refer to 20 2 Functions to Prevent Flash Memory from Rewriting Rev 1 10 Jul01 2005 page 259 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Flash Memory Version Table 20 7 Pin Functions for Standard Serial I O Mode Pin VCC1 VCC2 VSS Name Power supply input Description Apply the voltage guaranteed for Program and Erase to VCC1 pin and VCC2 to VCC2 pin The VCC apply condition is that VCC2 VCC1 Apply 0 V to VSS pin CNVSS CNVSS Connect to VCC1 pin HESET Reset input Reset input pin While RESET pin is L level input 20 cycles or longer clock to XIN pin XIN Clock input XOUT Clock output Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins To input an externally generated clock input it to XIN pin and open XOUT pin BYTE BYTE Connect this pin to VCC1 or VSS AVCC AVSS Analog power supply input Connect AVCC to VCC1 and AVSS to VSS respectively VREF Reference voltage input Enter the reference voltage for A D and D A converters from thi
112. in underflow while reloading and 0000h in overflow When setting the TAi register to a value during a counter stop the setting value can be read before a counter starts counting Also if the counter is read before it starts counting after a value is set in the TAi register while not counting the set value is read If a low level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register 1 three phase output forcible cutoff by input on NMI pin enabled the TA1OUT TA2OUT and TA4OUT pins go to a high impedance state Rev 1 10 Jul01 2005 page 291 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 9 1 3 Timer A One shot Timer Mode The timer remains idle after reset Set the mode count source counter value etc using the TAIMR i 0 to 4 register the TAi register the TAOTGL and TAOTGH bits in the ONSF register and the TRGSR register before setting the TAIS bit in the TABSR register to 1 count starts Always make sure the TAiMR register the TAOTGL and TAOTGH bits and the TRGSR register are modified while the TAiS bit remains 0 count stops regardless whether after reset or not When setting the TAiS bit to 0 count stop the followings occur A counter stops counting and a content of reload register is reloaded e TAIOUT pin outputs L After one
113. input X During event counter mode TAIIN input When count on falling edge Th TIN UP TsuUP TIN is selected TAIIN input When count on rising edge is selected Two phase pulse input in event counter mode tci lt TAIIN input tsu TAIN TAOUT tsu TAIN TAOUT gt gt tsu TAOUT TAIN TAiOUT input tsu TAOUT TAIN tc TB TBIIN input ADTRG input TXDi RXDi INTI input Figure 21 3 Timing Diagram Rev 1 10 Jul01 2005 page 278 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 Usage Precaution 22 1 SFR There is the SFR which can not be read containg bits that will result in unknown data when read Please set these registers to their previous values with the instructions other than the read modify write instructions Table 22 1 lists the registers contain bits that will result in unknown data when read and Table 22 2 lists the instruction table for read modify write Table 22 1 Registers Contain Bits that Will Result in Unknown Data When Read Address Timer A1 1 Register 01C3h 01C2h Timer A2 1 Register 01C5h 01C4h Timer A4 1 Register 01C7h 01C6h Dead Time Timer 01CCh Timer B2 Interrupt Occurrences Frequency Set Counter 01CDh SI O6 Bit Rate Generator
114. interrupt This bit is set to 0 by writing 0 in a program Writing 1 has no effect Nor is it set to 0 by an oscillation stop and re oscillation detection interrupt request acknowledged If an oscillation stop or a re oscillation is detected when the CM22 bit 1 no oscillation stop and re oscillation detection interrupt requests are generated 10 Read the CM23 bit in an oscillation stop and re oscillation detection interrupt handling routine to determine the main clock status 11 When the CM21 bit 0 on chip oscillator turned off and the CMO5 bit 1 main clock turned off the CM06 bit is fixed to 1 divide by 8 mode and the CM15 bit is fixed to 1 drive capability High Figure 7 4 CM2 Register Rev 1 10 Jul01 2005 page 39 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Peripheral Clock Select Register b7 b6 b5 b4 b3 b2 bi bO POLKA sen cQ 7 Clock Generating Circuit Timers A B and A D Clock 0 Divide by 2 of fAD f2 Select Bit 1 fAD f1 Clock source for the timers A B the dead time timer and A D SI O Clock Select Bit 0 f2SIO Clock source for ur to UART2 4 4SIO SI O3 to SI O6 5 Reserved Bt Bit Reserved Bt Seto to Settoror PCLK5 Pin Function Swirch Bit Scar easi E Software Interrupt Number SFR 0 Normal mode PCLK6 Location Switch Bit 1 Swiching mode
115. interrupt set the IFSR22 bit to 0 Timer B1 When using INT8 interrupt set the IFSR22 bit to 1 INT8 The INT8 interrupt is only in the 128 pin version In the 100 pin version set the IFSR22 bit to 0 Timer B1 5 When the PCLK6 bit in the PCLKR register 1 CANO 1 error and key input share the vector and interrupt control register When using the CANO 1 error interrupt set the IFSR26 bit to 0 CANO 1 error When using the key input interrupt set the IFSR26 bit to 1 key input 6 When using the INT6 to INT8 interrupts set these bits after settig the PU37 bit in the PUR3 register to 1 Figure 9 13 IFSR2 Register Rev 1 10 Jul 01 2005 page 76 of 318 REJO9B0124 0110 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 9 Interrupt 9 7 NMI Interrupt An NMI interrupt request is generated when input on the NMI pin changes state from high to low The NMI interrupt is a non maskable interrupt The input level of this NMI interrupt input pin can be read by accessing the P8 5 bit in the P8 register This pin cannot be used as an input port 9 8 Key Input Interrupt Of P10 4 to P10 7 a key input interrupt request is generated when input on any of the P10 4 to P10 7 pins which has had the PD10 4 to PD10 7 bits in the PD10 register set to 0 input goes low Key input interrupts can be used as a key on wake up function the
116. is assigned When write set to 0 When read its content turns out to be indeterminate Timer Bi Overflow 0 Timer did not overflow Flag 1 1 Timer has overflown b7 b6 00 f1 orf2 01 f8 10 f32 11 fC32 Count Source Select Bit 1 This flag is indeterminate after reset When the TBiS bit 1 start counting the MR3 bit is set to 0 no overflow by writing to the TBiMR register at the next count timing or later after the MRS bit was set to 1 overflow The MR3 bit cannot be set to 1 ina program The TBOS to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register and the TB3S to TB5S bits are assigned to the bit 5 to bit 7 in the TBSR register Figure 12 20 TBOMR to TB5MR Registers in Pulse Period and Pulse Width Measurement Mode Rev 1 10 Jul01 2005 page 115 of 318 REJO9B0124 0110 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 Timers Count source Measurement pulse Transfer Transfer P2 indeterminate value Pa measured value Reload register counter transfer timing NOTE 1 NOTE 1 NOTE 2 Timing at which counter reaches 0000h sux TBiS bit IR bit in TBIIC register Set to 0 upon accepting an interrupt request or by writing in program MRS bit in 1 mooo TBiMR register 5D E The TBOS to TB2S bits are assigned to bit 5 to bit 7 in the TABSR register and the TB
117. israel e 311 22 18 8 Operation SDOe6d iit eerte ret espe tee e a tus sert rs aaa t aaee 312 22 18 9 Prohibited Instructions essssssssssssessseeen eene nennen eaaa aiae 312 zm IgE 312 22 18 11 OW 10A CCOSS oin a 312 22 18 12 Rewriting in User ROM Area sisirain aana eene nennen nn nan nn aran rra nennen en rne 312 22 18 13 DMA Transfer tei EHE LOIRE Led Ed ae 312 22 19 Flash Memory Programming Using Boot Program ssssssssssseeeeeeeeeneeennenen nnne 313 22 19 1 Programming Using Serial VO Mode oooonoccconoccconocccononccnonaccnononononono in anniina anakaa kadakas enne nns 313 22 19 2 Programming Using CAN VO Mode eusen aa a ae aaa aoaaa ea nnne 313 22 20 SUI mmc SUM 314 Appendix 1 Package DIM SOS assunti aa 315 Regist r Ndek essa ado il P 317 Specifications written in this manual are believed to be accurate but are not guaranteed to be entirely free of error Specifications in this manual may be changed for functional or performance improvements Please make sure your manual is the latest edition A 6 SFR Page Reference CANO 1 Wake up Interrupt Control Register CO1WKIC CANO Successful Reception Interrupt Control Register CORECIC CANO Successful Transmission Interrupt Control Register COTRMIC Processor Modo Register 0 INT3 Interrupt Control Register INT3IC El Timer B5 Interrupt Control Register TB5IC Processor Mode Register 1 S1 O5 Interrupt Control Register S5IC System Clock Control Reg
118. keep the FSET instruction waiting INT SWITCH2 FCLR Disable interrupt AND B 00h 0055h Set the TAOIC register to 00h MOV W MEM RO Dummy read FSET Enable interrupt Example 3 Using the POPC instruction to changing the flag INT SWITCH3 PUSHC FLG FCLR Disable interrupt AND B 00h 0055h Set the TAOIC register to 00h POPC FLG Enable interrupt 22 7 7 Watchdog Timer Interrupt Initialize the watchdog timer after the watchdog timer interrupt request is generated Rev 1 10 Jul01 2005 page 288 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 8 DMAC 22 8 1 Write to DMAE Bit in DMiCON Register i 0 1 When both of the conditions below are met follow the steps below Conditions The DMAE bit is set to 1 again while it remains set DMAi is in an active state ADMA request may occur simultaneously when the DMAE bit is being written Step 1 Write 1 to the DMAE bit and DMAS bit in the DMiCON register simultaneously Step 2 Make sure that the DMAi is in an initial state in a program If the DMAi is not in an initial state the above steps should be repeated NOTES 1 The DMAS bit remains unchanged even if 1 is written However if 0 is written to this bit it is set to 0 DMA not requested In order to prevent the DMAS bit
119. lock bit function is disabled by setting the FMRO2 bit to 1 All blocks are unlocked However individual lock bit status remains unchanged The lock bit function is enabled by setting the FMRO2 bit to 0 Lock bit status is retained If the block erase or erase all unlocked block command is executed while the FMRO 2 bit is set to 1 the target block or all blocks are erased regardless of lock bit status The lock bit status of each block are set to 1 after an erase operation is completed Refer to 20 3 5 Software Commands for details on each command 20 3 7 Status Register SRD Register The status register indicates the flash memory operation state and whether or not an erase or program operation is completed as expected The FMROO FMRO06 and FMRO7 bits in the FMRO register indicate status register states Table 20 5 shows the status register In EWO mode the status register can be read when the followings occur Any even address in the user ROM area is read after writing the read status register command Any even address in the user ROM area is read from when the program block erase erase all unlocked block or lock bit program command is executed until when the read array command is executed 20 3 7 1 Sequencer Status SR7 and FMROO Bits The sequence status indicates the flash memory operation state It is set to 0 while the program block erase erase all unlocked block lock bit program or read lock bit status c
120. not change Rev 1 10 Jul01 2005 page 154 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Start and stop condition generation block STSPSEL 1 lt 9 SDA STSP circuit 0 STSPSEL 0 SCL STSP Transmission ACKC 1 ACKC 0 register 1ICM2 1 IICM 1 and IICM2 0 Noise Filter IICM2 1 Lbs IICM 1 and Start condition 1ICM2 0 detection Stop condition detection by detectan E detection dp _ T B ACK 9th bit ox Noise Filter UARTi 9th bit falling edge SWC 14 Serial I O DMAO DMA1 request UART1 DMAO only UARTI transmit NACK interrupt request DMAO UARTO UART2 UARTI receive ACK interrupt request DMA1 request Start stop condition detection interrupt request This diagram applies to the case where the SMD2 to SMDO bits in the UiIMR register 010b and the IICM bit in the UISMR register 1 i Oto2 IICM Bit in UISMR register IICM2 SWC ALS SWC2 SDHI Bits in UiSMR2 register STSPSEL ACKD ACKC Bits in UISMR4 register NOTE 1 If the IICM bit 1 the pins can be read even when the PD6 2 PD6 6 or PD7 1 bit 1 output mode Figure 14 23 1 C Mode Block Diagram Rev 1 10 Jul01 2005 page 155 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16
121. of Interrupts Figure 9 1 shows the types of interrupts Undefined instruction UND instruction Overflow INTO instruction BRK instruction INT instruction Software Non maskable interrupt Interrupt NMI DBC 9 Oscillation stop and re oscillation detection Watchdog timer Hardware Single step 2 Special Non maskable interrupt Address match Peripheral function Maskable interrupt NOTES 1 The peripheral functions in the microcomputer are used to generate the peripheral interrupt 2 Do not normally use this interrupt because it is provided exclusively for use by development support tools Figure 9 1 Interrupts Maskable Interrupt An interrupt which can be enabled disabled by the interrupt enable flag I flag or whose interrupt priority can be changed by priority level Non Maskable Interrupt An interrupt which cannot be enabled disabled by the interrupt enable flag I flag or whose interrupt priority cannot be changed by priority level Rev 1 10 Jul01 2005 page 60 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 9 Interrupt 9 2 Software Interrupts A software interrupt occurs when executing certain instructions Software interrupts are non maskable interrupts 9 2 1 Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the
122. or L level signal or connect to a CAN transceiver P9 6 CTXO CTX output Input H level signal open or connect to a CAN transceiver P10 0 to P10 7 Input port P10 P11 Oto P11 7 Input port P11 P12 0to P12 7 Input port P12 P13 Oto P13 7 Input port P13 P14 0 P14 1 Input port P14 NOTES 1 When using standard serial I O mode 1 the TXD pin must be held high while the RESET pin is pulled low Therefore connect this pin to VCC1 via a resistor Because this pin is directed for data output after reset adjust the pull up resistance value in the system so that data transfers will not be affected 2 The pins P11 to P14 are only in the 128 pin version Input H or L level signal or open Input H or L level signal or open Input H or L level signal or open Input H or L level signal or open Input H or L level signal or open Rev 1 10 Jul01 2005 page 260 of 318 REJO9B0124 0110 7tENESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Flash Memory Version M16C 6N Group M16C 6NK Flash memory version Connect oscillator Mode setup method circuit VSS VSS to VCC1 Package PLQP0100KB A Figure 20 13 Pin Connections for Standard Serial I O Mode 1 Rev 1 10 Jul01 2005 pag
123. pins Figure 14 15 shows the transfer clock output from the multiple pins function usage This function can be used when the selected transfer clock for UART1 is an internal clock Microcomputer TXD1 P6 7 CLKS1 P6 4 CLK1 P6_5 IN CLK Transfer enabled when Transfer enabled when the CLKMDO bit in the the CLKMDO bit 1 UCON register O This applies to the case where the CKDIR bit in the U1MR register 0 internal clock and the CLKMD1 bit in the UCON register 1 transfer clock output from multiple pins Figure 14 15 Transfer Clock Output From Multiple Pins Rev 1 10 Jul01 2005 page 144 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O 14 1 1 7 CTS RTS Function When the CTS function is used transmit and receive operation start when L is applied to the CTSi RTSi i 0 to 2 pin Transmit and receive operation begins when the CTSi RTSi pin is held L If the L signal is switched to H during a transmit or receive operation the operation stops before the next data When the RTS function is used the CTSi RTSi pin outputs on L signal when the microcomputer is ready to receive The output level becomes H on the first falling edge of the CLKi pin e CRD bit in UiCO register 1 CTS RTS function disabled CTSi RTSi pin is programmable I O function
124. power dissipation mode ROM Flash Memory f BCLK 32kHz Low power dissipation mode RAM f BCLK 32kHz Low power dissipation mode Flash memory Mask ROM On chip oscillation Flash Memory Wait mode f BCLK 32kHz Wait mode 3 Oscillation capacity High f BCLK 32kHz Wait mode 3 Oscillation capacity Low Stop mode Topr 25 C NOTES 1 Referenced to VCC 3 0 to 5 5V VSS OV at Topr 40 to 85 C f BCLK 24MHz unless otherwise specified 2 This indicates the memory in which the program to be executed exists 3 With one timer operated using fC32 Rev 1 10 Jul01 2005 page 273 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Table 21 6 A D Conversion Characteristics Parameter Resolution VREF 1 Measuring Condition VCC 21 Electric Characteristics Standard Min Typ 10 bits VREF VCC 5V Integral Nonlinearity Error ANEXO ANEX1 input ANO to AN7 input ANO 0to ANO 7 input AN2_0 to AN2 7 input External operation amp connection mode VREF VCC 3 3V ANEXO ANEX1 input ANO to AN7 input ANO 0to ANO 7 input AN2_0 to AN2 7 input External operation amp connection mode N 8 bits VREF AVCC VCC 3 3V Absolute 10 bits Accuracy VREF VCC
125. pulse width of an external signal Table 12 8 lists specifications in pulse period and pulse width measurement mode Figure 12 20 shows TBiMR register in pulse period and pulse width measurement mode Figure 12 21 shows the operation timing when measuring a pulse period Figure 12 22 shows the operation timing when measuring a pulse width Table 12 8 Specifications in Pulse Period and Pulse Width Measurement Mode Count Source f1 f2 f8 f32 fC32 Count Operation Up count Counter value is transferred to reload register at an effective edge of measurement pulse The counter value is set to 0000h to continue counting Count Start Condition Set the TBiS bit to 1 start counting Count Stop Condition Set the TBiS bit to 0 stop counting Interrupt Request Generation Timing When an effective edge of measurement pulse is input e Timer overflow When an overflow occurs the MR3 bit in the TBiMR register is set to 1 overflow simultaneously The MR3 bit is set to 0 no overflow by writing to the TBiMR register at the next count timing or later after the MR3 bit was set to 1 At this time make sure the TBiS bit is set to 1 start counting TBilN Pin Function Measurement pulse input Read from Timer Contents of the reload register measurement result can be read by reading TBi register Write to Timer Value written to the TBi register is written to neither reload register nor coun
126. ready Low power dissipation mode or on chip oscillator low power dissipation mode is entered Figure 20 7 shows a flow chart illustrating how to start and stop the flash memory before and after entering low power dissipation mode Follow the procedure on this flow chart When entering stop or wait mode the flash memory is automatically turned off When exiting stop or wait mode the flash memory is turned back on The FMRO register does not need to be set 20 3 3 5 FMRO5 Bit This bit selects the boot ROM or user ROM area in boot mode Set to 0 to access read the boot ROM area or to 1 user ROM access to access read write or erase the user ROM area 20 3 3 6 FMRO6 Bit This is a read only bit indicating an auto program operation state The FMRO6 bit is set to 1 when a program error occurs otherwise it is set to 0 Refer to 20 3 8 Full Status Check 20 3 3 7 FMRO7 Bit This is a read only bit indicating the auto erase operation status The FMRO7 bit is set to 1 when an erase error occurs otherwise it is set to 0 For details refer to 20 3 8 Full Status Check 20 3 3 8 FMR11 Bit EWO mode is entered by setting the FMR11 bit to 0 EWO mode EW1 mode is entered by setting the FMR11 bit to 1 EW1 mode 20 3 3 9 FMR16 Bit This is a read only bit indicating the execution result of the read lock bit status command When the block where the read lock bit status command is executed is locked the FMR
127. registers saved by a program within the interrupt routine using the POPM or similar instruction before executing the REIT instruction 9 5 9 Interrupt Priority If two or more interrupt requests are generated while executing one instruction the interrupt request that has the highest priority is accepted For maskable interrupts peripheral functions any desired priority level can be selected using the ILVL2 to ILVLO bits However if two or more maskable interrupts have the same priority level their interrupt priority is resolved by hardware with the highest priority interrupt accepted The watchdog timer and other special interrupts have their priority levels set in hardware Figure 9 9 shows the priorities of hardware interrupts Software interrupts are not affected by the interrupt priority If an instruction is executed control branches invariably to the interrupt routine NMI DBC Oscillation Stop and Re oscillation Detection Watchdog Timer Peripheral Function Single Step Address Match Figure 9 9 Hardware Interrupt Priority 9 5 10 Interrupt Priority Resolution Circuit The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those requested Figure 9 10 shows the circuit that judges the interrupt priority level Rev 1 10 Jul01 2005 page 71 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to ch
128. remain unchanged If a low level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register 1 three phase output forcible cutoff by input on NMI pin enabled the TA1OUT TA2OUT and TA4OUT pins go to a high impedance state Rev 1 10 Jul01 2005 page 293 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 9 2 Timer B 22 9 2 1 Timer B Timer Mode The timer remains idle after reset Set the mode count source counter value etc using the TBIMR i 0 to 5 register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to 1 count starts Always make sure the TBiMR register is modified while the TBiS bit remains 0 count stops regardless whether after reset or not NOTE 1 The TBOS to TB2S bits are the bits 5 to 7 in the TABSR register the TB3S to TB5S bits are the bits 5 to 7 in the TBSR register A value of a counter while counting can be read in the TBi register at any time FFFFh is read while reloading Setting value is read between setting values in the TBi register at count stop and starting a counter 22 9 2 2 Timer B Event Counter Mode The timer remains idle after reset Set the mode count source counter value etc using the TBIMR i 0 to 5 register and TBi register before setting the TBiS bit in the TABSR or the TBS
129. ren iaito Eriak 66 S3TRR to S6TRR 176 131 NE SAS Register Index AR 65 SARO SART eres 86 T TAO cuente 95 VADO Eco 65 TAOMR 95 98 100 105 107 TAA assente 95 122 TAG iiec teer inuito 122 uere 65 TAIMR 95 98 100 105 107 125 TA in iniecit O 95 122 TAZ Tis sese Peste sioe treo ri A bert 122 A tette 66 TA2MR 95 98 100 102 105 107 125 A 95 TASIC essed esa pise 66 TA3MR 95 98 100 102 105 107 E rm 95 122 TAA T ete ih ncn 122 TAC a SN 65 TAAMR 95 98 100 102 105 107 125 TABSRL ciis 96 111 124 TB ia 110 A e aac 65 TBOMR iine 110 112 113 115 TB an 110 A Ader ete 66 TBIMR srera ispanas 110 112 113 115 TBZ sitiada sica 110 122 A A n 65 TB2MR 110 112 113 115 125 BAS G a i eoe 123 B ihe Ree 110 TBSIO ioco ER ener 65 TBSMR em 110 112 113 115 ji H 110 TBAIG stir steht nace 65 TBAMR siidine 110 112 113 115 WBS iouis etii iei edi 110 TDi di 65 PBSMR irste 110 112 113 115 TBS Revia crearla 111 Nei stteasateas 86 TORT a teet dida 86 TROSA uan tern 97 124 U UOBCNIC to U2BONIC 65 UOBRG to U2BRG 132 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Register Index UOCO to U2CO cse ttis 133 UCA to UZC MT 134 UOMR to U2MR ococcocccocicnocin
130. request Figure 9 15 CANO 1 Wake up Interrupt Block Diagram Rev 1 10 Jul01 2005 page 77 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 9 Interrupt 9 10 Address Match Interrupt An address match interrupt request is generated immediately before executing the instruction at the ad dress indicated by the RMADi register i 0 to 3 Set the start address of any instruction in the RMADi register Use the AIERO and AIER 1 bits in the AIER register and the AIER20 and AIER21 bits in the AIER2 register to enable or disable the interrupt Note that the address match interrupt is unaffected by the flag and IPL For address match interrupts the value of the PC that is saved to the stack area varies depending on the instruction being executed refer to 9 5 7 Saving Registers The value of the PC that is saved to the stack area is not the correct return address Therefore follow one of the methods described below to return from the address match interrupt Rewrite the content of the stack and then use the REIT instruction to return Restore the stack to its previous state before the interrupt request was accepted by using the POP or similar other instruction and then use a jump instruction to return Table 9 6 shows the value of the PC that is saved to the stack area when an address match interrupt request is accepted Table
131. selected GTS RTS disabled RTS1 CLKMD1 kar CRS MM VSS n1 Values set to the U1BRG register PCLK1 Bit in PCLKR register SMD2 to SMDO CKDIR Bits in U1MR register 2 1 CTS RTS disabled o CTS1 A CRD CLK1 to CLKO CKPOL CRD CRS Bits in U1CO register CLKMDO CLKMD1 RCSP Bits in UCON register CTSO from UARTO Transmit receive unit polarity reversing circuit TXD polarity Figure 14 2 UART1 Block Diagram Rev 1 10 Jul 01 2005 page 129 of 318 REJO9B0124 0110 134 NESAS reversing circuit Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M1 Main clock PLL clock or on chip oscillator clock 4 0 UART2 Clock source selection RXD polarity reversing RXD2 O circuit 6C 6NM tsi 9 POLKI So 1 8 1 4 1 2 ol f1SIO or f2SIO gt f8SIO f32SIO CLK1 to CLKO ckpin f1SIO or fzSio 90 tso Ho N 0 Internal U2BRG register fe2sio 01 5 472 CKPOL CLK polarity Nol 17 n2 1 External UART reception SMD2 to SMDO Reception Receive clock control circuit UART transmission 1 010 100 101 110 Transmission Transmit clock
132. set to 0 A D conversion halted Set the ADST bit to 0 Interrupt Request Generation Timing Completion of A D conversion Analog Input Pin Select one pin from ANO to AN7 ANO 0 to ANO 7 AN2 0 to AN2 7 ANEXO to ANEX1 Reading of Result of A D Converter Read one of the ADO to AD7 registers that corresponds to the selected pin Rev 1 10 Jul01 2005 page 185 of 318 RENESAS REJ09B0124 0110 15 A D Converter Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 A D Converter A D Control Register 0 Mp Symbol Address After Reset dejo ADCONO 03D6h 00000XXXb Bit Symbol b2 b1 b0 0 0 0 ANO is selected 00 1 AN1 is selected 0 1 0 AN2 is selected Analog Input Pin Select Bit 0 1 1 AN3 is selected ANA is selected AN5 is selected AN6 is selected AN7 is selected 2 3 mD A D Operation Mode b4 b3 a Select Ei 0 0 0 One shot mode 3 0 Software trigger 0 A D conversion disabled ADST A D Conversion Start Flag AD conversi n started 1 Refer to NOTE 2 for ADCON2 CKSO Frequency Select Bit 0 Register 1 If the ADCONO register is rewritten during A D conversion the conversion result will be indeterminate 2 ANO 0 to AN 7 and AN2 0 to AN2 7 can be used in same way as ANO to AN7 Use the ADGSEL1 to ADGSELO bits in the ADCON2 register to select the desired pin 3 After rewriti
133. set to 0 When read its content is indeterminate RXOnI Listen AA Mode 0 Listen only mode NEU Y Select Bit 3 1 Listen only mode enabled 4 Time Stamp TSPreScale Prescaler 3 Nothing is assigned When write set to 0 When read their contents are indeterminate de When the TSReset bit 1 the CiTSR register is set to 0000h After this the bit is automatically set to 0 2 When the RetBusOff bit 1 the CIRECR and CiTECR registers are set to 00h After this this bit is automatically set to 0 3 Change this bit only in the CAN reset initialization mode 4 When the listen only mode is selected do not request the transmission Figure 18 7 COCTLR and C1CTLR Registers Rev 1 10 Jul01 2005 page 208 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM CANi Status Register i 0 1 b7 b6 b5 b4 b3 b2 bi b0 Address 0212h 0232h Symbol COSTR C1STR 18 CAN Module After Reset 00h 00h Bit Symbol Bit Name Function Active Slot Bits 1 Successful Transmission Flag 1 Successful Reception Flag 1 Transmission Flag Transmitter Reception Flag Receiver Slot 0 Slot 1 Slot 2 f 1 0 Slot14 1 Slot 15 No successful transmission The CAN module has transmitted a message successfully 0 No successful reception 1 CAN module received a message
134. set to 000b interrupt disable 2 Set the I flag to 1 3 Start operating the peripheral functions used to exit wait mode When the peripheral function interrupt is used an interrupt routine is performed as soon as an interrupt request is acknowledged and the CPU clock is supplied again When the microcomputer exits wait mode by the peripheral function interrupt the CPU clock is the same clock as the CPU clock executing the WAIT instruction Rev 1 10 Jul01 2005 page 51 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Clock Generating Circuit 7 4 3 Stop Mode In stop mode all oscillator circuits are turned off so are the CPU clock and the peripheral function clocks Therefore the CPU and the peripheral functions clocked by these clocks stop operating The least amount of power is consumed in this mode If the voltage applied to VCC is VRAM or more the internal RAM is retained However the peripheral functions clocked by external signals keep operating The following interrupts can be used to exit stop mode NMI interrupt Key interrupt INT interrupt Timer A Timer B interrupt when counting external pulses in event counter mode Serial 1 O interrupt when external clock is selected CANO 1 Wake up interrupt when CAN sleep mode is selected 7 4 3 1 Entering Stop Mode The microcomputer is p
135. successful transmission Use the IFSRO 1 bit in the IFSRO register to select During lC mode NACK and ACK interrupts comprise the interrupt source Bus collision detection During IE mode this bus collision detection constitutes the cause of an interrupt M16C 60 M16C 20 Series Software Manual During C mode a start condition or a stop condition detection constitutes the cause of an interrupt o 1 CANO wake up error is selected a CAN1 wake up error is selected n Use the IFSRO4 bit in the IFSRO register to select Use the IFSRO bit in the IFSRO register to select When the IFSRO2 bit 0 CANO 1 wake up is selected When the IFSRO2 bit Use the IFSRO2 bit in the IFSRO register to select When the IFSRO2 bit 0 CANO 1 error is selected When the IFSRO 2 bit 1 SI O5 is only in the 128 pin version In the 100 pin version set the IFSR04 bit to 0 Timer B5 13 Use the IFSR20 bit in the IFSR2 register to select INT is only in the 128 pin version In the 100 pin version set the IFSR20 bit to 0 Timer A2 14 Use the IFSR21 bit in the IFSR2 register to select INT6 is only in the 128 pin version In the 100 pin version set the IFSR21 bit to 0 Timer A3 15 Use the IFSRO5 bit in the IFSRO register to select SI O6 is only in the 128 pin version In the 100 pin version set the IFSRO5 bit to 0 Timer BO 16 Use the IFSR22 bit in the IFSR2 reg
136. the FMRO2 bit in the FMRO register is set to 1 lock bit disabled no error occurs even under the conditions above Rev 1 10 Jul 01 2005 page 257 of 318 REJ09B0124 0110 34 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Flash Memory Version Full status check FMRO6 1 and Command 1 Execute the clear status register command and set the SR4 and SR5 FMRO7 1 sequence error bits to 0 completed as expected 2 Rewrite command and execute again Erase error 1 Execute the clear status register command and set the SR5 bit to 0 2 Execute the lock bit read status command Set the FMRO2 bit in the FMRO register to 1 lock bit disabled if the lock bit in the block where the error occurred is set to 0 locked 3 Execute the block erase or erase all unlocked block command again NOTE If similar error occurs that block cannot be used If the lock bit is set to 1 unlocked in 2 above that block cannot be used FMRO6 0 When a program operation is executed 1 Execute the clear status register command and set the SR4 bit to 0 completed as expected 2 Execute the read lock bit status command and set the FMRO bit to 1 if the lock bit in the block where the error occurred is set to 0 3 Execute the program command again NOTE When a similar error occurs that block cannot be used
137. the falling edge 1 of RXDi i Oto2 This diagram applies to the case where IOPOL bit 1 reversed Figure 14 31 Bus Collision Detect Function Related Bits Rev 1 10 Jul01 2005 page 169 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O 14 1 6 Special Mode 4 SIM Mode UART2 Based on UART mode this is an SIM interface compatible mode Direct and inverse formats can be implemented and this mode allows to output a low from the TXD2 pin when a parity error is detected Table 14 17 lists the specifications of SIM mode Table 14 18 lists the registers used in the SIM mode and the register values set Figure 14 32 shows the typical transmit receive timing in SIM mode Table 14 17 SIM Mode Specifications Specification Transfer data format Direct format Inverse format Transfer clock The CKDIR bit in the U2MR register 0 internal clock fi 16 n 1 fi f1SIO f2SIO f8SIO f32SIO n Setting value of the U2BRG register 00h to FFh The CKDIR bit 1 external clock fEXT 16 n 1 fEXT Input from CLK2 pin n Setting value of the U2BRG register 00h to FFh Transmission start condition Before transmission can start the following requirements must be met The TE bit in the U2C1 register 1 transmission enabled The TI bit in the U2C1 register O data present in the U2TB
138. to 0 b5 b4 When read their contents are O DMA Request Cause A Basic cause of request Expansion Select Bit Extended cause of request Software DMA Request Bit A DMA request is generated by setting this bit to 1 when the DMS bit is 0 basic cause and the DSEL3 to DSELO RW bits are 0001b software trigger The value of this bit when read is 0 1 The causes of DMA1 requests can be selected by a combination of the DMS bit and the DSEL3 to DSELO bits in the manner described below DSEL3 to DSELO Bits DMS 0 basic cause of request DMS 1 extended cause of request 0000b Falling edge of INT1 pin 0001b Software trigger 0010b Timer AO 0011b Timer A1 0100b Timer A2 0101b Timer A3 SI OS 0110b Timer A4 SI 04 0111b Timer BO Two edges of INT1 pin 1000b Timer B1 1001b Timer B2 1010b UARTO transmit 1011b UARTO receive ACKO 1100b UART2 transmit 1101b UART2 receive ACK2 1110b A D conversion 1111b UART1 transmit ACK1 DMAi Control Register i 0 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol DM1CON RATTO SR Address After Reset 002Ch 00000X00b 003Ch 00000X00b El Transfer Unit Bit i 16 bits Repeat Transfer Mode M transfer DMASL Select Bit Repeat transfer DMA Request Bit 0 DMA not requested 1 DMA requested DMA Enable Bit Disabled Enabled
139. to 1 on chip oscillator clock inside the interrupt routine Oscillation stop re oscillation detection interrupt request is generated CM22 bit 1 main clock stop detected CM23 bit 1 main clock stopped CM21 bit remains unchanged Where the CM20 bit is 1 the system is placed in the following state if the main clock re oscillates from the stop condition Oscillation stop re oscillation detection interrupt request is generated CM22 bit 1 main clock re oscillation detected CM23 bit 0 main clock oscillation CM21 bit remains unchanged Rev 1 10 Jul01 2005 page 57 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Clock Generating Circuit 7 5 3 How to Use Oscillation Stop and Re oscillation Detection Function The oscillation stop re oscillation detection interrupt shares the vector with the watchdog timer interrupt If the oscillation stop re oscillation detection and watchdog timer interrupts both are used read the CM22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt Where the main clock re oscillated after oscillation stop the clock source for CPU clock and peripheral function must be switched to the main clock in the program Figure 7 14 shows the procedure to switch the clock source from the on chip oscillator to the main clock
140. to C1MCTL15 207 CIREGIG itcm eio 66 CUT HMIG mencionada 66 CANO Slot 0 to 15 Time Stamp 204 205 Data Field 204 205 Message Box 204 205 OCLEKR ederet ence tc 41 CMO icit tr potter ta 37 CMT iet ehe pe reve ters 38 CM 39 CPSHBE chien 97 111 A Area tales ties 200 CROIN eor iue ete 200 D DAO DAT iius 199 DACON Nesce asoraire naia 199 DARO DART iint 86 DMOCON DM1 CON ssec 85 DMOIC DM11C oirisium 65 Rev 1 10 Jul 01 2005 page 317 of 318 REJO9B0124 0110 DMOSL iie tiec tests 84 DMI SL iain niece ient 85 BRENT 121 F FMR O ppt EE 244 EMRA eec aos 244 I ICTB2 nisse itte teta 123 IDBO DB reete 121 IP SRO ge lidia 74 IIS Eis int teet 75 ESA EMMERICH TE ici 76 INTOIC to INT8IC 66 INVOO E EERTE E 119 hide icm 120 K KUPIC e 65 O ONS F aieeaa eolica 97 P PO to PAS ica neren 234 PCT4 ic en Eee 234 POLA Ricca 40 PGR ici ist 236 PDO to PDTI eee 233 PUGO P I 42 PING ts a cdas cante 32 PM eco EE 33 ccc P 41 PRAGA denia tado 59 PURO to PUR suessss 235 A 236 R RMADO to RMADS e 79 RHOMGP no tica 241 S SORIG to S2RIC ces 65 SOTIG to S2TIG hs 65 S93456TBRR irissen 177 S3BRG to S6BRG 176 S3C to S6C sss 176 S3IC SAC ei eienen
141. to the TBi register is written to only reload register Transferred to counter when reloaded next 0to5 NOTE 1 The TBOS to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register and the TB3S to TB5S bits are assigned to the bit 5 to bit 7 in the TBSR register Timer Bi Mode Register i 2 O to 5 D7 be b5 b4 b3 b bt Ho Symbol Address After Reset I lolol TBOMR to TB2MR 039Bh to 039Dh 00XX0000b EAM ee a TB3MR to TB5MR 01DBh to 01DDh 00XX0000b pipi Bit Symbol TMODO RW TMODO operation Mode Select Bit 0 0 Timer mode RW RW MRO Has no effect in timer mode RW MR1 Can be set to 0 or 1 TBOMR TB3MR registers Set to 0 in timer mode TB1MR TB2MR TB4MR TB5MR register s Nothing is assigned When write set to 0 When read its content is indeterminate When write in timer mode set to O When read in timer mode its content is indeterminate b7 b6 00 f1 orf2 Count Source Select Bit O 1 f8 10 f32 11 fC32 Figure 12 18 TBOMR to TB5MR Registers in Timer Mode Rev 1 10 Jul01 2005 page 112 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 Timers 12 2 2 Event Counter Mode In event counter mode the timer counts pulses from an external device or overflows and underflows of other timers Table 12 7 lists specifications in event counter mo
142. tw TBH TBilN Input HIGH Pulse Width counted on both edges tw TBL TBilN Input LOW Pulse Width counted on both edges Table 21 19 Timer B Input Pulse Period Measurement Mode Standard Min Max Parameter TBiIN Input Cycle Time TBiIN Input HIGH Pulse Width TBiIN Input LOW Pulse Width Table 21 20 Timer B Input Pulse Width Measurement Mode Standard Min Max Parameter TBilN Input Cycle Time TBiIN Input HIGH Pulse Width TBiIN Input LOW Pulse Width Table 21 21 A D Trigger Input P Standard Symbol arameter Min Max tc AD ADTRG Input Cycle Time trigger able minimum 1000 tw ADL ADTRG Input LOW Pulse Width 125 Table 21 22 Serial I O Standard Min Max Parameter te ck CLKi Input Cycle Time tw CKH CLKi Input HIGH Pulse Width twiCkL CLKi Input LOW Pulse Width ta c a TXDi Output Delay Time th c a TXDi Hold Time tsu D c RXDi Input Setup Time tn c D RXDi Input Hold Time Table 21 23 External Interrupt INTi Input Standard Min Max 250 250 Parameter Rev 1 10 Jul01 2005 page 277 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM XIN input TAIIN input TAiOUT input 21 Electric Characteristics TAiOUT input Up down
143. type 2 RAM size depends on microcomputer type 3 Ports P11 to P14 are only in the 128 pin version 4 8 bits X 2 channels in the 100 pin version Figure 1 1 Block Diagram Rev 1 10 Jul 01 2005 page 4 of 318 REJO9B0124 0110 34 NESAS Port P13 Port P12 3 8 Port P11 L Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 1 4 Product List 1 Overview Table 1 3 lists the M16C 6N Group M16C 6NK M16C 6NM products and Figure 1 2 shows the type numbers memory sizes and packages Table 1 3 Product List M306NKFHGP M306NMFHGP 384 K 4 Kbytes 31 Kbytes PLQP0100KB A As of Jul 2005 Type No ROM Capacity RAM Capacity Package Type Remarks Flash PLQP0128KB A M306NKFJGP M306NMFJGP 512 K 4 Kbytes 31 Kbytes PLQP0100KB A memory version PLQP0128KB A M306NKFHTGP M306NMFHTGP 384 K 4 Kbytes 31 Kbytes PLQP0100KB A PLQP0128KB A M306NKFJTGP M306NMFJTGP 512 K 4 Kbytes 31 Kbytes PLQP0100KB A PLQP0128KB A M306NKFHVGP M306NMFHVGP 384 K 4 Kbytes 31 Kbytes PLQP0100KB A PLQP0128KB A M306NKFJVGP M306NMFJVGP 512 K 4 Kbytes 31 Kbytes PLQP0100KB A PLQP0128KB A Normal ver M306NKME XXXGP M306NMME XXXGP 192 Kbytes 16 Kbytes PLQP0100KB A Mask PLQP0128KB A M
144. used for timers A and B and fiSIO is used for serial I O The f8 and f32 clocks can be output from the CLKOUT pin The fAD clock is produced from the main clock PLL clock or on chip oscillator clock and is used for the A D converter The fCANi i 0 1 clock is derived from the main clock PLL clock or on chip oscillator clock by dividing them by 1 undivided 2 4 8 or 16 and is used for the CAN module When the WAIT instruction is executed after setting the CMO2 bit in the CMO register to 1 peripheral function clock turned off during wait mode or when the microcomputer is in low power dissipation mode the fi fiSIO fAD fCANO and fCAN1 clocks are turned off The fC32 clock is derived from the sub clock and is used for timers A and B This clock can be used when the sub clock is activated NOTE 1 fCANO and fCAN1 clocks stop at H in CANO 1 sleep mode 7 3 Clock Output Function The f8 f32 or fC clock can be output from the CLKOUT pin Use the CMO1 to CMOO bits in the CMO register to select Rev 1 10 Jul01 2005 page 47 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Clock Generating Circuit 7 4 Power Control Normal operation mode wait mode and stop mode are provided as the power consumption control All mode states except wait mode and stop mode are called normal operation mode in this document
145. vec J vec 2 J PC Interrupt 1 SP 2 SP 4 J vec METRE i Data bus MEA Indeterminate t Eon contents contents contents RD Indeterminate 1 WR 2 NOTES 1 The indeterminate state depends on the instruction queue buffer A read cycle occurs when the instruction queue buffer is ready to accept instructions 2 The WR signal timing shown here is for the case where the stack is located in the internal RAM Figure 9 5 Time Required for Executing Interrupt Sequence Rev 1 10 Jul01 2005 page 68 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 9 Interrupt 9 5 5 Interrupt Response Time Figure 9 6 shows the interrupt response time The interrupt response or interrupt acknowledge time denotes a time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed Specifically it consists of a time from when an interrupt request is generated till when the instruction then executing is completed a on Figure 9 6 and a time during which the interrupt sequence is executed b on Figure 9 6 Interrupt request generated Interrupt request acknowledged Instruction Interrupt sequence _ Instruction in interrupt routine b Interrupt response time a A time from when an interrupt request is generated till
146. when the instruction then executing is completed The length of this time varies with the instruction being executed The DIVX instruction requires the longest time which is equal to 30 cycles without wait state the divisor being a register b A time during which the interrupt sequence is executed For details see the table below Note however that the values in this table must be increased 2 cycles for the DBC interrupt and 1 cycle for the address match and single step interrupts Interrupt Vector Address SP Value 16 bit Bus without Wait 8 bit Bus without Wait 18 cycles 20 cycles 19 cycles 19 cycles 20 cycles Figure 9 6 Interrupt response time 9 5 6 Variation of IPL when Interrupt Request is Accepted When a maskable interrupt request is accepted the interrupt priority level of the accepted interrupt is set in the IPL When a software interrupt or special interrupt request is accepted one of the interrupt priority levels listed in Table 9 5 is set in the IPL Table 9 5 shows the IPL values of software and special interrupts when they are accepted Table 9 5 IPL Level that is Set to IPL When A Software or Special Interrupt is Accepted Interrupt Sources Value that is Set to IPL Oscillation Stop and Re oscillation Detection Watchdog Timer NMI 7 Software Address Match DBC Single Step Not changed Rev 1 10 Jul01 2005 page 69 of 318 RENESAS REJ09B0124 0110 Under development This document is
147. 0 o m 2 gt o Dv m gt oo DIN 2o QU 7 olo NIN mim OU aa o g mo Ej o DIN gt gt mc o Dv mm gt ojojo MININ Tam S Sm N ojojo MIN w w gt oj T sm o n2 UJ m o Nm m ne y N N olojojojo DO DO DO PO w W UJ W UJ NDIA Aj 2 2 3 2 2 N ojojojojo RO DO PO mm mn min NI OQ a BY So oS ojo RO PO PES 2s o nv UJ UJ EJ o Dv UJ Q eg o Dv T Q o N Ww g Ej CAN1 Message Box 10 Data Field 030Fh CAN1 Message Box 10 Time Stamp 0310h e do zu Ere zx e do erg 110 En y CAN1 Message Box 11 Identifier DLC ojojojojo w Gd GO GO CO pare cire har Par esr N DIAA 2 23 2 25 2 e do Ere co 2 oo w pari pari Ko zs CAN1 Message Box 11 Data Field e wo ere zx mojo w SIIS CAN1 Message Box 11 Time Stamp 031Fh 0320h ao Dv peri CAN1 Message Box 12 Identifier DLC C 99 ojo C2 NIN 110 5 o do N ES 5 ojo Go Co MIN o a a gt CAN1 Message Box 12 Data Field 99 N CAN1 Message Box 12 Time Stamp ao Co ojojojojojo o GO CO GD GO C5 LIS moo aI 5 5 a 5a 5 gt CAN1 Message Box 13 Identifier DLC CAN1 Message Box 13 Data Field 033Ch 033Dh gen CAN1 Message Box 13 Time Stamp 033Fh The blank areas are reserved B 7 Symbo
148. 0 upon accepting an interrupt request or by writing in program fj Frequency of count source f1 f2 f8 f32 C32 NOTES 1 The 8 bit prescaler counts the count source 2 The 8 bit pulse width modulator counts the output from the 8 bit prescaler underflow signal 3 m 00h to FFh n 00h to FEh 4 This timing diagram is the following case e TAI register 0202h e The TAITGH and TAITGL bits in the ONSF or TRGSR register 00b TAIIN pin input e The MR1 bit in the TAiMR register 0 falling edge e The MR2 bit in the TAiMR register 1 trigger selected by the TAITGH and TAITGL bits Figure 12 14 Example of 8 bit Pulse Width Modulator Operation Rev 1 10 Jul01 2005 page 108 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 Timers 12 2 Timer B Figure 12 15 shows a block diagram of the timer B Figures 12 16 and 12 17 show the timer B related registers Timer B supports the following three modes Use the TMOD1 and TMODO bits in the TBiMR register i 0 to 5 to select the desired mode Timer mode The timer counts an internal count source Event counter mode The timer counts pulses from an external device or over flows or underflows of other timers Pulse period pulse width measuring mode The timer measures pulse period or pulse width of an external signal High order Bits of Data Bus Select clock sourc
149. 000b interrupt disabled before setting the CM10 bit in the CM1 register to 1 When the peripheral function interrupt is used to exit stop mode set the CM10 bit to 1 after the following settings are completed 1 The ILVL2 to ILVLO bits in the interrupt control registers for the peripheral function interrupt used to exit stop mode must have larger value than that of the RLVL2 to RLVLO bits The ILVL2 to ILVLO bits in all other interrupt control registers for the peripheral function interrupts which are not used to exit stop mode must be set to 000b interrupt disabled 2 Set the I flag to 1 3 Start operation of peripheral function being used to exit wait mode When exiting stop mode by the peripheral function interrupt the interrupt routine is performed when an interrupt request is generated and the CPU clock is supplied again When stop mode is exited by the peripheral function interrupt or NMI interrupt the CPU clock source is as follows in accordance with the CPU clock source setting before the microcomputer had entered stop mode When the sub clock is the CPU clock before entering stop mode Sub clock When the main clock is the CPU clock source before entering stop mode Main clock divided by 8 When the on chip oscillator clock is the CPU clock source before entering stop mode On chip oscillator clock divided by 8 Rev 1 10 Jul01 2005 page 53 of 318 RENESAS REJ09B0124 0110 Under development This
150. 01 2005 page 96 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 Timers One Shot Start Flag b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset ONSF 0382h 00h Bit Symbol Bit Name Function TAOOS Timer AO One Shot Start Flag The timer starts counting by setting this bit to 1 while the TMOD1 to Timer A1 One Shot Start Flag TMODO bits in the TAIMR register i Timer A2 One Shot Start Flag 0 to 4 10b one shot timer mode and the MR2 bit in the TAiMR register Timer A3 One Shot Start Flag _ 0 TAIOS El enabled 9 TA4OS Timer A4 One Shot Start Flag When read its content is 0 0 Z phase input disabled 1 Z phase input enabled b7 b6 A 0 0 Input on TAOIN is selected 1 Timer AO Event Trigger 0 1 TB2 is selected 2 Select Bit TAOTGH 10 TA4 is selected 2 one 1 1 TA1 is selected 2 TAZIE Z phase Input Enable Bit TAOTGL 1 Make sure the PD7_1 bit in the PD7 register is set to 0 input mode 2 Over flow or under flow Trigger Select Register b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset TRGSR 0383h 00h Bit Symbol 4 TA1TGL Input on TA1IN is selected 1 Timer A1 Event Trigger TB2 is selected 2 Select Bit TAO is selected 2 TAITGH TA2 is selected 2 RW TA2TGL Input on TA2IN is selected 1 RW Timer A2 Event Trigger T
151. 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 18 CAN Module 18 8 Bit rate Bit rate depends on f1 the division value of the CAN module system clock the division value of the baud rate prescaler and the number of Tq of one bit Table 18 2 shows the examples of bit rate Table 18 2 Examples of Bit rate 1Mbps 500kbps 10Tq 1 125kbps 10Tq 4 20Tq 2 83 3kbps 10Tq 6 20Tq 3 33 3kbps 10Tq 15 NOTE 1 The number in indicates a value of CAN division value multiplied by baud rate prescaler division value E Calculation of Bit rate f1 2 X CAN division value X baud rate prescaler division value x number of Tq of one bit NOTES 1 fCAN division value 1 2 4 8 16 fCAN division value a value selected in the CCLKR register 2 Baud rate prescaler division value P 1 P 0 to 15 P a value selected in the BRP bit in the CICONR register i 0 1 Rev 1 10 Jul01 2005 page 217 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 18 CAN Module 18 9 Acceptance Filtering Function and Masking Function These functions serve the users to select and receive a facultative message The CiIGMR register i 0 1 the CiLMAR register and the CiLMBR register can perform mask
152. 0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 6 Processor Mode Single chip mode 00000h SFR 00400h PM13 bit in PM1 register 0 Internal RAM Internal RAM Internal ROM XXXXXh Capacity Address XXXXXh Capacity Address YYYYYh Can not use PM13 bit 1 Internal RAM Internal ROM Address XXXXXh Address YYYYYh 16 Kbytes 043FFh 192 Kbytes D0000h YYYYYh 20 Kbytes 053FFh 256 Kbytes C0000h Internal ROM 31 Kbytes 07FFFh 384 Kbytes A0000h 512 Kbytes 80000h FFFFFh NOTES 1 If the PM13 bit in the PM1 register is set to 0 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used 2 For the mask ROM version set the PM10 bit in the PM1 register to 0 block A disable Figure 6 3 Memory Map Rev 1 10 Jul01 2005 page 34 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Clock Generating Circuit 7 1 Types of Clock Generating Circuit Four circuits are incorporated to generate the system clock signal Main clock oscillation circuit Sub clock oscillation circuit On chip oscillator PLL frequency synthesizer 7 Clock Generating Circuit Table 7 1 lists the clock generating circuit specifications Figure 7 1 shows the clock generating circuit Figures 7 2 to 7 8 show the clock related re
153. 01D9h SI O3 Bit Rate Generator 01E3h SI O4 Bit Rate Generator 01E7h SI O5 Bit Rate Generator 01EBh UART2 Bit Rate Generator 01F9h UART2 Transmit Buffer Register 01FBh 01FAh Up Down Flag 0384h Timer AO Register 0387h 0386h Timer A1 Register 0389h 0388h Timer A2 Register 038Bh 038Ah Timer A3 Register 038Dh 038Ch Timer A4 Register 038Fh 038Eh UARTO Bit Rate Generator 03A1h UARTO Transmit Buffer Register 03A3h 03A2h UART1 Bit Rate Generator 03A9h UART1 Transmit Buffer Register 03ABh 03AAh NOTES 1 It is affected only in three phase motor control timer function 2 These registers are only in the 128 pin version 3 It is affected only in one shot timer mode and pulse width modulation mode Table 22 2 Instruction Table for Read Modify Write Bit Manipulation BCLR BNOT BSET BTSTC BTSTS Shift RCLC RORC ROT SHA SHL Arithmetic ABS ADC ADCF ADD DEC EXTS INC MUL MULU NEG SBB SUB Logical AND NOT OR XOR Jump ADJNZ SBJNZ Rev 1 10 Jul01 2005 page 279 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 2 External Clock Do not stop the external clock when it is connected to the XIN pin and the main clock is selected as the CPU clock Rev 1 10 Jul01 2005 page 280 of 318 RENE
154. 1 Data Field 023Fh CAN1 Time Stamp Register The blank areas are reserved B 5 CAN1 Message Box 1 Time Stamp Symbol CAN1 Message Box 6 Identifier DLC C CAN1 Message Box 2 Data Field CAN1 Message Box 6 Data Field 028Fh CAN1 Message Box 2 Time Stamp 02CFh CAN1 Message Box 6 Time Stamp 0290h 02D0h CAN1 Message Box 3 Identifier DLC CAN1 Message Box 7 Identifier DLC CAN1 Message Box 3 Data Field CAN1 Message Box 7 Data Field CAN1 Message Box 3 Time Stamp CAN1 Message Box 7 Time Stamp 204 205 CAN1 Message Box 4 Identifier DLC CAN1 Message Box 8 Identifier DLC CAN1 Message Box 4 Data Field CAN1 Message Box 8 Data Field CAN1 Message Box 4 Time Stamp CAN1 Message Box 8 Time Stamp CAN1 Message Box 5 Identifier DLC CAN1 Message Box 9 Identifier DLC CAN1 Message Box 5 Data Field CAN1 Message Box 9 Data Field 02BEh A 02FEh q 02BFh CAN1 Message Box 5 Time Stamp O2FFh CAN1 Message Box 9 Time Stamp B 6 o Nm 5 o N UO A z o N m 2 n2 wo ojojoljojo NO PMO OJUOo O O Mojo 2 3 3 5 N 99 BR Nm ER ojojojojo NOP PPP OO 0 0 co Ny D aja 5 5 gt ojo NIN mg za D Dv i oo mmm gt gt fo a Dv Co oo M m m Co ho 2 o N gt T 5 o N m A T oo DID gt gt Dla 2 oo mH m m oo o m gt N gt olo DIN gt gt Oo a a gt olo mm mim G
155. 1 00XX0010b UARTO Receive Buffer Register XXN UART1 Transmit Receive Mode Register 00h UART1 Bit Rate Generator XXh UART1 Transmit Buffer Register XE UART1 Transmit Receive Control Register 0 00001000b UART1 Transmit Receive Control Register 1 00XX0010b UART1 Receive Buffer Register XXh UART Transmit Receive Control Register 2 X0000000b DMAO Request Cause Select Register DMA1 Request Cause Select Register CRC Data Register CRC Input Register 03BFh X Undefined NOTES 1 The TA2P to TA4P bits in the UDF register are set to 0 after reset However the contents in these bits are indeterminate when read 2 The blank areas are reserved and cannot be accessed by users Rev 1 10 Jul01 2005 page 27 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 16 SFR Information 16 Symbol After Reset 03COh XX A D Register 0 A D Register 1 A D Register 2 A D Register 3 A D Register 4 A D Register 5 A D Register 6 03CEh A D Register 7 A D Control Register 2 ADCON2 00h A D Control Register 0 ADC
156. 1 1 0001 0000 0010 0001b e Setting procedure 1 Reverse the bit positions of the value 80C4h by program in 1 byte unit 80h gt 01h C4h gt 23h b15 b0 2 Write 0000h initial value CRCD register b7 bo 3 Write 01h e CRCIN register Two cycles later the CRC code for 80h i e 9188h has its bit positions reversed to become 1189h which is stored in the CRCD register b15 bO 1189h CRCD register 4 Write 23h CRCIN register Two cycles later the CRC code for 80C4h i e WM 8250h has its bit positions reversed to become bO 0A41h which is stored in the CRCD register b15 0A41h CRCD register e Details of CRC operation n the case of 3 above the value written to the CRCIN register 01h 00000001b has its bit positions reversed to become 10000000b The value 1000 0000 0000 0000 0000 0000b derived from that by adding 16 digits and the initial value of the CRCD register 0000h are added The result is divided by the generator polynomial using modulo 2 arithmetic Modulo 2 operation is 1000 1000 operation that complies 1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 Data with the law given below A 1000 1000 0001 0000 1 040 0 1000 0001 0000 1000 O nd zd 1000 1000 0001 0000 1 14021 1001 0001 1000 1000 K 4 1 1 0 1 1 CRC code Generator polynomial The value 0001 0001 1000 1001b 1189h derived from the remainder 1001 0001 1000 1000b 9188h by reve
157. 149 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O Example of Receive Timing when Transfer Data is 8 bit Long parity disabled one stop bit UiBRG count source RE bit in UiC1 register RXDi Receive data taken in Transfer clock CLO d Reception triggered when transfer clock Transferred from UARTi receive RI bit in 1 is generated by falling edge of start bit register to UIRB register a u UiC1 register 9 l RTSi IR bit in SiRIC register i Oto2 Set to 0 by an interrupt request acknowledgement or by program The above timing diagram applies to the case where the register bits are set as follows PRYE bit in UIMR register O parity disabled STPS bit in UIMR register 0 1 stop bit CRD bit in UiCO register 0 CTSI RTSI enabled and CRS bit 1 RTSi selected Figure 14 18 Receive Operation 14 1 2 1 Bit Rates In UART mode the frequency set by the UiBRG register i O to 2 divided by 16 become the bit rates Table 14 9 lists example of bit rates and settings Table 14 9 Example of Bit Rates and Settings Bit rate Count source Peripheral function clock 16MHz Peripheral function clock 24MHz bps of BRG Set value of BRG n Actual time bps Set value of BRG n Actual time bps a 67h 155 9Bh 1 33h 5 19h 103 67h 8 44h
158. 16 17 Dissipation Mode 10 16 17 PLL Operation 12 p i E Mode On chip Oscillator Mode P 14 9 NOTE 8 11 16 O 17 chip Oscillator L On c prosa ator OW a E 10 NOTES mejo Power Dissipation Mode Stop Mode s 18 9 18 18 18 9 18 Wait Mode 18 18 18 18 18 Cannot transit NOTES 1 Avoid making a transition when the CM20 bit 1 oscillation stop re oscillation detection function enabled Set the CM20 bit to 0 oscillation Stop re oscillation detection function disabled before transiting On chip oscillator clock oscillates and stops in low speed mode In this mode the on chip oscillator can be used as peripheral function clock Sub clock oscillates and stops in PLL operation mode In this mode sub clock can be used as peripheral function clock PLL operation mode can only be entered from and changed to high speed mode Set the CMO6 bit to 1 division by 8 mode before transiting from on chip oscillator mode to high or medium speed mode When exiting stop mode the CMO6 bit is set to 1 division by 8 mode If the CMO5 bitis set to 1 main clock stop then the CMO6 bit is set to 1 division by 8 mode Atransition can be made only when sub clock is oscillating State transitions within the same mode divide by n values changed or sub clock oscillation turned on or off are shown in the table below
159. 16 b15 b8 b0 b7 b0 b7 bo Symbol Address After Reset XXX 1 1 DARO 0026h to 0024h Indeterminate DAR1 0036h to 0034h Indeterminate Set the destination address of transfer 00000h to FFFFFh RW Nothing is assigned When write set to 0 When read their contents are 0 1 If the DAD bit in the DMiCON register is 0 fixed this register can only be written to when the DMAE bit in the DMiCON register is 0 DMA disabled If the DAD bit is 1 forward direction this register can be written to at any time If the DAD bit is 1 and the DMAE bit is 1 DMA enabled the DMAi forward address pointer can be read from this register Otherwise the value written to it can be read DMAi Transfer Counter i 0 1 b8 bO b7 bo Symbol Address After Reset TCR1 0039h 0038h Indeterminate Set the transfer count minus 1 The written value is stored in the DMAi transfer counter reload register and when the DMAE bit in the DMICON register is set to 1 DMA enabled or the DMAi transfer counter underflows when the DMASL bit in the DMiCON 0000h to FFFFh RW register is 1 repeat transfer the value of the DMAi transfer counter reload register is transferred to the DMAi transfer counter When read the DMAi transfer counter is read Figure 11 4 SARO and SAR1 Registers DARO and DAR1 Registers TCRO and TCR1 Registers Rev 1 10 Jul01 2005 page 86 of 318 RENESAS REJ09B0124 0110 Under development This documen
160. 16 bit is set to 0 When the block where the read lock bit status command is executed is unlocked the FMR16 bit is set to 1 Figure 20 5 shows how to enter and exit EWO mode Figure 20 6 show how to enter and exit EW1 mode Rev 1 10 Jul01 2005 page 245 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Flash Memory Version Procedure to enter EWO mode z Rewrite control program A In boot mode only glp mdde or baot made set the FMROS bit to 1 user ROM area access Transfer the rewrite control program in CPU rewrite Set the FMRO1 bit to 1 CPU rewrite mode mode to a space other than the flash memory 9 enabled after writing 0 2 Set CMO CM1 and PM1 registers 1 Execute software commands Jump to the rewrite control program transferred to Execute the read array command 9 a space other than the flash memory In the following steps use the rewrite control program in a space other than the flash memory Set the FMRO1 bit to 0 CPU rewrite mode disabled In boot mode only Set the FMRO5 bit to 0 Boot ROM area accessed 4 Jump to a desired address in the flash memory NOTES 1 In CPU rewrite mode set the CMO6 bit in the CMO register and CM17 to CM16 bits in the CM1 register to CPU clock frequency of 10 MHz or less Set the PM17 bit in the PM1 registe
161. 16C 6N Group M16C 6NK M16C 6NM UART Transmit Receive Control Register 2 b7 b6 b5 b4 b3 b2 bi bO Symbol UCON UARTO Transmit Interrupt anne Cause Select Bit 14 Serial I O Address After Reset O3BOh X0000000b Transmit buffer empty TI bit 1 Transmission completed TXEPT bit 1 UART1 Transmit Interrupt Cause Select Bit Transmit buffer empty TI bit 1 Transmission completed TXEPT bit 1 UARTO Continuous Receive Mode Enable Bit UART1 Continuous Receive Mode Enable Bit Continuous receive mode disabled Continuous receive mode enabled Continuous receive mode disabled Continuous receive mode enabled UART1 CLK CLKS Select Bit 0 ffective when the CLKMD1 bit 1 Clock output from CLK1 Clock output from CLKS1 UART1 CLK CLKS Select Bit 1 1 O O0Om O0 O 0O0 0O CLK output is only CLK1 Transfer clock output from multiple pins function selected Separate UARTO CTS RTS Bit o CTS RTS shared pin 1 CTS RTS separated CTSO supplied from the P6 4 pin Nothing is assigned When write set to 0 When read its content is indeterminate 1 When using multiple transfer clock output pins make sure the following conditions are met The CKDIR bit in the U1MR register 0 internal clock UARTi Special Mode Register i 0 to 2 b7 b6 b5 b4 b3 b2 bi Address After Reset S X LLBLLI vsu is 01EFh 01F3h 01F7h X0000000b 12C Mode Select
162. 16C 6N Group M16C 6NK M16C 6NM 20 Flash Memory Version 20 3 3 1 FMROO Bit This bit indicates the flash memory operating status It is set to 0 while the program block erase erase all unlocked block lock bit program or read lock bit status command is being executed otherwise it is set to 1 20 3 3 2 FMRO1 Bit The microcomputer can accept commands when the FMR01 bit is set to 1 CPU rewrite mode Set the FMROD bit to 1 user ROM area access as well if in boot mode 20 3 3 3 FMRO2 Bit The lock bit is disabled by setting the FMROZ2 bit to 1 lock bit disabled Refer to 20 3 6 Data Protect Function The lock bit is enabled by setting the FMRO2 bit to 0 lock bit enabled The FMRO2 bit does not change the lock bit status but disables the lock bit function If the block erase or erase all unlocked block command is executed when the FMROZ2 bit is set to 1 the lock bit status changes 0 locked to 1 unlocked after command execution is completed 20 3 3 4 FMSTP Bit This bit resets the flash memory control circuits and minimizes power consumption in the flash memory Access to the flash memory is disabled when the FMSTP bit is set to 1 Set the FMSTP bit by program in a space other than the flash memory Set the FMSTP bit to 1 if one of the followings occurs A flash memory access error occurs while erasing or programming in EWO mode FMROO bit does not switch back to 1
163. 1IC 004Bh 004Ch CO1ERRIC 6 9 004Dh ADIC KUPIC 6 004Eh SOTIC to S2TIC 0051h 0053h 004Fh SORIC to S2RIC 0052h 0054h 0050h TAOIC TA1IC 0055h 0056h TA4IC 0059h TBOIC S6IC 7 005Ah XXXXX000b TB2IC 005Ch XXXXX000b Bi Symbol ILVLO Level 0 interrupt disabled Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 0 Interrupt not requested Interrupt Request Bit 1 Interrupt requested Noting is assigned When write set to O b7 b4 When read their contents are indeterminate After Reset XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b Interrupt Priority Level Select Bit To rewrite the interrupt control registers do so at a point that does not generate the interrupt request for that register For details refer to 22 7 Interrupt Use the IFSRO7 bit in the IFSRO register to select Use the IFSRO6 bit in the IFSRO register to select This bit can only be reset by writing 0 Do not write 1 Use the IFSR04 bit in the IFSRO register to select The S5IC register is only in the 128 pin version In the 100 pin version set the IFSRO4 bit to 0 Timer B5 If the PCLK6 bit in the PCLKR register is set to 1 CO1ERRIC KUPIC register can be assigned in an address 004Dh and the ADIC register can be assigned in an address 004Eh SFR location of the KUPIC register is changed
164. 2 UART1 Special Mode Register U1SMR UART2 Special Mode Register 4 U2SMR4 UART2 Special Mode Register 3 U2SMR3 UART2 Special Mode Register 2 U2SMR2 UART2 Special Mode Register U2SMR UART2 Transmit Receive Mode Register U2MR UART2 Bit Rate Generator U2BRG UART2 Transmit Buffer Register U2TB UART2 Transmit Receive Control Register 0 U2C0 00001000b UART2 Transmit Receive Control Register 1 U2C1 00000010b UART2 Receive Buffer Register U2RB XE X Undefined NOTES 1 These registers exist only in the 128 pin version 2 The S5TRF and S6TRF bits in the S8456TRR register are used in the 128 pin version 3 The blank areas are reserved and cannot be accessed by users Rev 1 10 Jul 01 2005 page 20 of 318 REJO9B0124 0110 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 9 SFR Information 9 Symbol After Reset CANO Message Control Register 0 COMCTLO 00h CANO Message Control Register 1 COMCTL1 00h CANO Message Control Register 2 COMCTL2 00h CANO Message Control Register 3 COMCTL3 00h CANO Message Control Register 4 COMCTL4 00h CANO Message Control Register 5 COMCTL5 00
165. 23 bit is set to 0 main clock oscillates Set the CMO6 bit to 1 divide by 8 Set the CM22 bit to 0 main clock stop re oscillation not detected Set the CM21 bit to 0 main clock for the CPU clock source 1 CMO06 bit Bit in CMO register CM21 CM22 CM 23 bits Bits in CM2 register NOTE 1 If the clock source for CPU clock is to be changed to PLL clock set to PLL operation mode after set to high speed mode Figure 7 14 Procedure to Switch Clock Source from On chip Oscillator to Main Clock Rev 1 10 Jul01 2005 page 58 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 8 Protection 8 Protection In the event that a program runs out of control this function protects the important registers so that they will not be rewritten easily Figure 8 1 shows the PRCR register The following lists the registers protected by the PRCR register The PRCO bit protects the CMO CM1 CM2 PLCO PCLKR and CCLKR registers The PRC1 bit protects the PMO PM1 PM2 TB2SC INVCO and INVC1 registers The PRC2 bit protects the PD7 PD9 S3C S4C S5C and S6C registers NOTE 1 The S5C and S6C registers are only in the 128 pin version Set the PRC2 bit to 1 write enabled and then write to any address and the PRC2 bit will be set to O write protected The registers protected by the PRC2 bit should be ch
166. 306NKMG XXXGP M306NMMG XXXGP D Under development 256 Kbytes 20 Kbytes Type No M30 6N KM GT XXX GP ps PLQP0100KB A PLQP0128KB A Package type ROM version Normal ver GP Package PLQP0100KB A PLQP0128KB A ROM No Omitted on flash memory version Characteristics no Normal ver T V ROM capacity E 192 Kbytes G 256 Kbytes H 384 Kbytes J 512 Kbytes Memory type M Mask ROM version F Flash memory version T ver Automotive 85 C version V ver Automotive 125 C version Shows the number of CAN module pin count etc 6N Group M16C Family Figure 1 2 Type No Memory Size and Package Rev 1 10 Jul01 2005 page 5 of 318 REJO9B0124 0110 134 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 1 Overview 1 5 Pin Configuration Figures 1 3 and 1 4 show the pin configuration top view PIN CONFIGURATION top view P2 3 lt gt P2 4 4 vss lt gt P3 0 g gt p2 2 For Ed Poy D For a Poy N 2 7 56 55 54 53 52 51 P1 2 lt cbe Pid lt gt e P1_0 lt A PO 7 ANO 7 lt a lt gt P0_6 ANO_6 lt gt PO 5 ANO 5 PO 4 ANO 4 lt lt gt PO 3 AN
167. 32 8 ms The watchdog timer is initialized by writing to the WDTS register The prescaler is initialized after reset Note that the watchdog timer and the prescaler both are inactive after reset so that the watchdog timer is activated to start counting by writing to the WDTS register In stop mode wait mode and hold state the watchdog timer and prescaler are stopped Counting is resumed from the held value when the modes or state are released Figure 10 1 shows the block diagram of the watchdog timer Figure 10 2 shows the watchdog timer related registers i Prescaler iCM07 0 WDC7 0 116 H CMO7 0 CPU clock iWDC7 1 HOLD m 1128 A 2 Watchdog timer Interrupt request O CMO7 1 Watchdog timer PM12 1 Watchdog timer Reset PM2 On chip oscillator clock Write to WDTS register Internal RESET signal O L active CMO7 Bit in CMO register WDC7 Bit in WDC register PM12 Bit in PM1 register PM22 Bit in PM2 register Figure 10 1 Watchdog Timer Block Diagram Rev 1 10 Jul01 2005 page 80 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 10 Watchdog Timer Watchdog Timer Control Register b7 b6 b5 b4 b3 b2 bi bO efe LT LT Woe oom o0o00001 Bit Symbol Bit Name Function RW High order Bit of Watchdog Timer Ro Reserved
168. 3S to TB5S bits are assigned to bit 5 to bit 7 in the TBSR register 0to05 NOTES 1 Counter is initialized at completion of measurement 2 Timer has overflown 3 This timing diagram is for the case where the MR1 to MPO bits in the TBiMR register are 00b measure the interval from falling edge to falling edge of the measurement pulse Figure 12 21 Operation Timing When Measuring Pulse Period Count source Measurement pulse Transfer Transfer Transfer Transfer LE RS ak measured value measured y measured value 2t value 1 4 value Reload register counter transfer timing s NOTE 1 NOTE 1 NOTE 1 NOTE 1 LA r L yi Timing at which counter reaches 0000h TBiS bit IR bit in TBIIC register Set to 0 upon accepting an interrupt request or by MR3 bit in d writing in program TBiMR register The TBOS to TB2S bits are assigned to bit 5 to bit 7 in the TABSR register and the TB3S to TB5S bits are assigned to bit 5 to bit 7 in the TBSR register i20to5 NOTES 1 Counter is initialized at completion of measurement 2 Timer has overflown 3 This timing diagram is for the case where the MR1 to MRO bits in the TBiMR register are 10b measure the interval from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of the measurement pulse Figure 12 22 Operation Timing When Measuring Pulse Width Rev 1 10 Jul01 2005 page 116
169. 5 page 292 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 9 1 4 Timer A Pulse Width Modulation Mode The timer remains idle after reset Set the mode count source counter value etc using the TAIMR i 0 to 4 register the TAi register the TAOTGL and TAOTGH bits in the ONSF register and the TRGSR register before setting the TAIS bit in the TABSR register to 1 count starts Always make sure the TAiMR register the TAOTGL and TAOTGH bits in the ONSF register and the TRGSR register are modified while the TAiS bit remains 0 count stops regardless whether after reset or not The IR bit is set to 1 when setting a timer operation mode with any of the following procedures Select the pulse width modulation mode after reset Change an operation mode from timer mode to pulse width modulation mode Change an operation mode from event counter mode to pulse width modulation mode To use the Timer Ai interrupt the IR bit set the IR bit to 0 by program after the above listed changes have been made When setting TAiS bit to 0 count stop during PWM pulse output the following action occurs Stop counting When TAiOUT pin is output H output level is set to L and the IR bit is set to 1 e When TAiOUT pin is output L both output level and the IR bit
170. 5V ANEXO ANEX1 input ANO to AN7 input ANO_0 to ANO 7 input AN2_0 to AN2 7 input It He I wN External operation amp connection mode VREF VCC 3 3V ANEXO ANEX1 input ANO to AN7 input ANO 0to ANO 7 input AN2_0 to AN2 7 input External operation amp connection mode N 8 bits VREF AVCC VCC 3 3V N Differential Nonlinearity Error Offset Error Co Gain Error It n6 It A Co RLADDER Resistor Ladder VREF VCC S o tconv 10 bit Conversion Time Sample amp Hold function Available VREF VCC 5V AD 10MHz 8 bit Conversion time Sample amp Hold function Available VREF VCC 5V 9AD 10MHz Sampling Time Reference Voltage NOTES Analog Input Voltage 1 Referenced to VCC AVCC VREF 3 3 to 5 5V VSS AVSS OV 40 to 85 C unless otherwise specified 2 dAD frequency must be 10MHz or less 3 When sample amp hold function is disabled AD frequency must be 250kHz or more in addition to a limit of NOTE 2 When sample amp hold function is enabled AD frequency must be 1MHz or more in addition to a limit of NOTE 2 Table 21 7 D A conversion Characteristics Parameter Resolution 1 Measuring Condition Standard Min Typ Absolute Accuracy Setup Time Output Resistance NOTES Reference Power Supply Input Current
171. 6N Group M16C 6NK M16C 6NM 3 Memory 3 Memory Figure 3 1 shows a memory map of the M16C 6N Group M16C 6NK M16C 6NM The address space extends the 1 Mbyte from address 00000h to FFFFFh The internal ROM is allocated in a lower address direction beginning with address FFFFFh For example a 512 Kbyte internal ROM is allocated to the addresses from 80000h to FFFFFh As for the flash memory version 4 Kbyte space block A exists in OFOO00h to OFFFFh 4 Kbyte space is mainly for storing data In addition to storing data 4 Kbyte space also can store programs The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh Therefore store the start address of each interrupt routine here The internal RAM is allocated in an upper address direction beginning with address 00400h For example a 31 Kbyte internal RAM is allocated to the addresses from 00400h to 07FFFh In addition to storing data the internal RAM also stores the stack used when calling subroutines and when interrupts are generated The SFR is allocated to the addresses from 00000h to 003FFh Peripheral function control registers are located here Of the SFR any area which has no functions allocated is reserved for future use and cannot be used by users The special page vector table is allocated to the addresses from FFEOOh to FFFDBh This vector is used by the JMPS or JSRS instruction For details refer to M16C 60 and M16C 20 Series Software Manual 00000h SF
172. 7 5 INT Interrupt Either an L level of at least tW INH or an H level of at least tW INL width is necessary for the signal input to pins INTO to INT8 regardless of the CPU operation clock If the POL bit in the INTOIC to INT8IC registers the IFSR10 to IFSR15 bits in the IFSR1 register or the IFSR23 to IFSR25 bits in the IFSR2 register are changed the IR bit may inadvertently set to 1 interrupt requested Be sure to set the IR bit to 0 interrupt not requested after changing any of those register bits NOTES 1 The pins INT6 to INT8 are only in the 128 pin version 2 The INT6IC to INT8IC registers are only in the 128 pin version 3 The IFSR23 to IFSR25 bits are effective only in the128 pin version In the 100 pin version these bits are set to 0 one edge Rev 1 10 Jul01 2005 page 287 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 7 6 Rewrite Interrupt Control Register a The interrupt control register for any interrupt should be modified in places where no interrupt requests may be generated Otherwise disable the interrupt before rewriting the interrupt control register b To rewrite the interrupt control register for any interrupt after disabling that interrupt be careful with the instruction to be used Changing any bit other than IR bit If while exe
173. 7Dh XXh E CANO Message Box 1 Time Stamp a X Undefined NOTES 1 These registers exist only in the 128 pin version 2 The blank area is reserved and cannot be accessed by users Rev 1 10 Jul01 2005 page 14 of 318 REJ09B0124 0110 7tENESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Table 4 3 SFR Information 3 4 Special Function Register SFR Address Symbol After Reset 0080h 0081h 0082h 0083h 0084h 0085h CANO Message Box 2 Identifier DLC 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh CANO Message Box 2 Data Field 008Eh ANO M Box 2 008Fh CANO Message Box 2 Time Stamp 0090h 0091h 0092h 0093h 0094h 0095h CANO Message Box 3 Identifier DLC 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh CANO Message Box 3 Data Field 009Eh 009Fh CANO Message Box 3 Time Stamp 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h CANO Message Box 4 Identifier DLC 00A6h 00A7h 00A8h Busan CANO Message Box 4 00ACh 00ADh Data Field OOAEh O0AFh CANO Message Box 4 Time Stamp 00B1h 00B2h 00B3h 00B4h 00B5h CANO Message Box 5 Identifier DLC 00B6h 00B7h 00B8h 00B9h 00BAh OOBBh 00BCh 00BDh
174. 8 Kbytes Block 6 64 Kbytes DOOR Block 3 8 Kbytes OEFFFF ORBEEE OFOO00 OFCOO00 Block 2 8 Kbytes Block 5 to 0 32 8 8 8 4 4 Kbytes Block 1 4 Kbytes OFFFFF Block 0 4 Kbytes OFFFFFh 4 Kbytes User ROM area Boot ROM area 2 NOTES 1 Block A can be made usable by setting the PM10 bit in the PM1 register to 1 block A enabled Block A cannot be erased by the erase all unlocked block command Use the block erase command to erase it 2 The boot ROM area can only be rewritten in parallel I O mode 3 To specify a block use an even address in that block Figure 20 1 Flash Memory Block Diagram Rev 1 10 Jul01 2005 page 239 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Flash Memory Version 20 1 1 Boot Mode The microcomputer enters boot mode when a hardware reset occurs while an H signal is applied to the CNVSS and P5 0 pins and an L signal is applied to the P5 5 pin A program in the boot ROM area is executed In boot mode the FMROS bit in the FMRO register selects access to the boot ROM area or the user ROM area The rewrite control program for standard serial l O mode is stored in the boot ROM area before shipment The boot ROM area can be rewritten in parallel I O mode only If any rewrite control program using erase write mode EWO mode is written in the boot ROM area the flash memory can b
175. 9 7 shows the relationship between address match interrupt sources and associated registers Figure 9 16 shows the AIER AIER2 and RMADO to RMAD3 registers Table 9 6 Value of PC That is Saved to Stack Area When Address Match Interrupt Request is Accepted Instruction at Address Indicated by RMADi Register Value of PC that is Saved to Stack Area 16 bit operation code Address indicated by RMADi Instruction shown below among 8 bit operation code instructions register 2 ADD B S IMM8 dest SUB B S IMM8 dest AND B S FIMME8 dest OR B S IMM8 dest MOV B S IMM8 dest STZ B S IMM8 dest STNZ B S IMM8 dest STZX B S IMM81 IMM82 dest CMP B S IMM8 dest PUSHM src POPM dest JMPS IMM8 JSRS IMM8 MOV B S IMM dest However dest AO or A1 Instructions other than the above Address indicated by RMADi register 1 Value of PC that is saved to stack area Refer to 9 5 7 Saving Registers Table 9 7 Relationship Between Address Match Interrupt Sources and Associated Registers Address Match Interrupt O AIERO Address Match Interrupt 1 Address Match Interrupt 2 AIER20 Address Match Interrupt 3 AIER21 Rev 1 10 Jul01 2005 page 78 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 9 Interrupt Address Match Interrupt Enable Register b7 b6 b5 b4 b3 b2 bi NINA Y Symbol Address After Reset OOOO Y
176. 9B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O 14 1 2 6 CTS RTS Function When the CTS function is used transmit operation start when L is applied to the CTSi RTSi i 0 to 2 pin Transmit operation begins when the CTSi RTSi pin is held L If the L signal is switched to H during a transmit operation the operation stops before the next data When the RTS function is used the CTSi RTSi pin outputs on L signal when the microcomputer is ready to receive The output level becomes H on the first falling edge of the CLKi pin e CRD bit in UiCO register 1 disables UARTO CTS RTS function CTSi RTSi pin is programmable I O function e CRD bit 0 CRS bit in UiCO register 0 CTS function is selected CTSi RTSi pin is CTS function CRD bit 0 CRS bit 1 RTS function is selected CTSi RTSi pin is RTS function 14 1 2 7 CTS RTS Separate Function UARTO This function separates CTSO RTSO outputs RTSO from the P6_0 pin and accepts as input the CTSO from the P6_4 pin To use this function set the register bits as shown below CRD bit in UOCO register 0 enables UARTO CTS RTS CRS bit in UOCO register 1 outputs UARTO RTS CRD bit in U1CO register 0 enables UART1 CTS RTS CRS bit in U1CO register 0 inputs UART1 CTS RCSP bit in UCON register 1 inputs CTSO from the P6 4 pin CLKMD 1 bit
177. ACK1 9 80 to 83 0050h to 0053h 14 Serial I O Timer AO 84 to 87 0054h to 0057h Timer A1 88 to 91 0058h to 005Bh 12 Timers Timer A2 INT7 9 56 to 59 0038h to 003Bh 92 to 95 005Ch to 005Fh 12 Timers Timer A3 INT6 96 to 99 0060h to 0063h 9 6 INT Interrupt Timer A4 100 to 103 0064h to 0067h 12 Timers Timer BO SI O6 9 104 to 107 0068h to 006Bh 12 Timers 14 Serial I O Timer B1 INT8 9 108 to 111 006Ch to OO6Fh 12 Timers 9 6 INT Interrupt Timer B2 112 to 115 0070h to 0073h 12 Timers INTO 116 to 119 0074h to 0077h INT1 120 to 123 0078h to 007Bh INT2 124 to 127 007Ch to 007Fh 9 6 INT Interrupt INT Instruction Interrupt NOTES Address relative to address in INTB OPA 0o ANAL 128 to 131 0080h to 0083h to 252 to 255 OOFCh to OOFFh These interrupts cannot be disabled using the I flag Use the IFSRO7 bit in the IFSRO register to select Use the IFSRO6 bit in the IFSRO register to select Use the IFSR17 bit in the IFSR1 register to select Furthermore use the IFSRO3 bit in the IFSRO register to select when selecting SI O4 or CAN1 successful reception Use the IFSR16 bit in the IFSR1 register to select Furthermore use the IFSROO bit in the IFSRO register to select when selecting SI O3 or CAN1
178. AIER 0009h XXXXXX00b Address Match Interrupt O Interrupt disabled AIERO Enable Bit Interrupt enabled AIER1 Address Match Interrupt 1 Interrupt disabled Enable Bit Interrupt enabled Nothing is assigned When write set to 0 b7 b2 When read their contents are indeterminate Address Match Interrupt Enable Register 2 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset AIER2 01BBh XXXXXX00b E Nothing is assigned When write set to 0 b7 b2 When read their contents are indeterminate Address Match Interrupt Register i i 0 to 3 Address After Reset b23 b19 b16 b15 b8 0012h to 0010h X00000h ba pons pO bf 0016h to 0014h X00000h 01BAh to 01B8h X00000h 01BEh to 01BCh X00000h Bit Symbol Function Setting Range Address setting register for address h to FFFFFh match interrupt vindi Nothing is assigned When write set to 0 b23 b20 When read their contents are indeterminate potter eee eee Figure 9 16 AIER Register AIER2 Register and RMADO to RMAD3 Registers Rev 1 10 Jul01 2005 page 79 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 10 Watchdog Timer 10 Watchdog Timer The watchdog timer is the function of detecting when the program is out of control Therefore we recommend using the watchdog timer to improve reliability of a system The watchdog timer contains a
179. ATI CPU E Oscillation stop re oscillation operation Normal processing detection interrupt request Normal processing XIN stops NOTE 1 This clock is generated by the on chip oscillator It is not supplies after reset The operating clock can changes from on chip oscillator clock on chip oscillation oscillating to BCLK by using oscicllation stop re oscillation detection function or setting the CM21 bit in the CM2 register Figure 22 2 Operation Timing at Oscillation Stop Re oscillation Stop Detection at Normal Processing Rev 1 10 Jul01 2005 page 284 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 6 Protection Set the PRC2 bit to 1 write enabled and then write to any address and the PRC2 bit will be set to 0 write protected The registers protected by the PRC2 bit should be changed in the next instruction after setting the PRC2 bit to 1 Make sure no interrupts or no DMA transfers will occur between the instruction in which the PRC2 bit is set to 1 and the next instruction Rev 1 10 Jul01 2005 page 285 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 7 Interrupt 22 7 1 Reading Address 00000h Do not read the address 00000h i
180. B2 is selected 2 Select Bit TA1 is selected 2 TA2TGH TA3 is selected 2 TASTGL l Input on TA3IN is selected 1 Timer A3 Event Trigger TB2 is selected 2 Select Bit TA2 is selected 2 TASTGH TA4 is selected 2 TA4TGL Input on TA4IN is selected 1 Timer A4 Event Trigger TB2 is selected 2 Select Bit TA3 is selected 2 TAO is selected 2 TA4TGH 1 Make sure the port direction bits for the TA1IN to TA4IN pins are set to 0 input mode 2 Over flow or under flow Clock Prescaler Reset Flag b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset CPSRF 0381h OXXXXXXXb Nothing is assigned When write set to 0 When read their contents are indeterminate Setting this bit to 1 initializes the Clock Prescaler Reset Flag prescaler for the timekeeping clock When read its content is 0 Figure 12 6 ONSF Register TRGSR Register and CPSRF Register Rev 1 10 Jul01 2005 page 97 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 Timers 12 1 1 Timer Mode In timer mode the timer counts a count source generated internally Table 12 1 lists specifications in timer mode Figure 12 7 shows TAiMR register in timer mode Table 12 1 Specifications in Timer Mode Count Source f1 f2 f8 f32 C32 Count Operation Down count When the timer underflows it reloads t
181. Bit Other than 12C mode 12 mode Arbitration Lost Detecting Flag Control Bit Update per bit Update per byte Bus Busy Flag STOP condition detected START condition detected busy Reserved Bit S et to 0 Bus Collision Detect Sampling Clock Select Bit Rising edge of transfer clock Underflow signal of timer Aj 2 Auto Clear Function Select Bit of Transmit Enable Bit No auto clear function Auto clear at occurrence of bus collision Transmit Start Condition Select Bit Not synchronized to RXDi Synchronized to RXDi 3 Nothing is assigned When write set to 0 When read its content is indeterminate 1 The BBS bit is set to 0 by writing 0 in a program Writing 1 has no effect 2 Underflow signal of timer A3 in UARTO underflow signal of timer A4 in UART1 underflow signal of timer AO in UART2 3 When a transfer begins the SSS bit is set to 0 not synchronized to RXDi Figure 14 8 UCON Register and UOSMR to U2SMR Registers Rev 1 10 Jul01 2005 page 135 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O UARTi Special Mode Register 2 i 0 to 2 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset UOSMR to U2SMR2 01EEh 01F2h 01F6h X0000000b 12C Mode Select Bit 2 See Table 14 12 I C Mode Functions RW
182. C 6NM Table 14 11 Registers to Be Used and Settings in IPC Mode Register Bit 0 to 7 Set transmission data 14 Serial I O 0 to 7 Reception data can be read 8 ACK or NACK is set in this bit ABT Arbitration lost detection flag Invalid OER Overrun error flag 0 to 7 Set a transfer rate Invalid SMD2 to SMDO Set to 010b CKDIR Set to 0 Set to 1 IOPOL Set to 0 CLK1 CLKO Select the count source for the UIBRG register Invalid CRS Invalid because the CRD bit 1 TXEPT Transmit register empty flag CRD Set to 1 NCH Set to 1 CKPOL Set to 0 UFORM Set to 1 TE Set this bit to 1 to enable transmission TI Transmit buffer empty flag RE Set this bit to 1 to enable reception RI Reception complete flag U2IRS 2 Invalid U2RRM 2 UiLCH UiERE Set to 0 ICM Set to 1 ABC Select the timing at which arbitration lost is detected Invalid BBS Bus busy flag 3 to 7 Set to 0 IICM2 See Table 14 12 IC Mode Functions CSC Set this bit to 1 to enable clock synchronization Set to 0 SWC Set this bit to 1 to have SCLi output fixed to L at the falling edge of the 9th bit of clock ALS Set this bit to 1 to have SDAi output stopped when a
183. C card type NMI P8 5 CAN Programmer CNVSS RTS1 P6 4 RESET user reset signal Figure 22 10 Pin Connection for Programming Using CAN I O Mode Rev 1 10 Jul01 2005 page 313 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 20 Noise Connect a bypass capacitor approximately 0 1 uF across the VCC1 and VSS pins and VCC2 and VSS pins using the shortest and thicker possible wiring Figure 22 11 shows the bypass capacitor connection Bypass Capacitor Connecting Pattern Connecting Pattern M16C 6N Group M16C 6NK M16C 6NM Connecting Pattern N Connecting Pattern Bypass Capacitor Figure 22 11 Bypass Capacitor Connection Rev 1 10 Jul01 2005 page 314 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Appendix 1 Package Dimensions Appendix 1 Package Dimensions
184. CLKR 025Fh 00h Bit Symbol Function b2 b1 bO CCLKO 000 No division 0 0 1 Divide by 2 0 1 0 Divide by 4 CCLK1 CANO Clock Select Bits 2 O 1 1 Divide by 8 100 Divide by 16 10 11 11 1 O 15 CCLK2 0 p not set a value 1 CCLK3 CANO CPU Interface 0 CANO CPU interface operating Sleep Bit 3 1 CANO CPU interface in sleep b6 b5 b4 CCLK4 000 No division 0 0 1 Divide by 2 0 1 0 Divide by 4 CAN1 Clock Select Bits 2 0 1 1 Divide by 8 100 Divide by 16 101 110 p not set a value 111 CAN1 CPU Interface 0 CAN1 CPU interface operating Sleep Bit 3 1 CAN1 CPU interface in sleep 1 Write to this register after setting the PRCO bit in the PRCR register to 1 Write enabled 2 Set only when the Reset bit in the CiCTLR register i 0 1 1 Reset Initialization mode 3 Before setting this bit to 1 set the Sleep bit in the CiCTLR register to 1 Sleep mode enabled CCLK6 Figure 7 6 CCLKR Register Processor Mode Register 2 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset XIX Polo o ewe 001Eh XXX00000b Bit Symbol Bit Name Function Specifying Wait when 0 2 waits je PM20 Accessing SFR at PLL 1 1 wait Operation 2 b1 Reserved Bit Set to 0 0 CPU clock is used for the WDT Count Source watchdog timer count source Protective Bit 3 4 1 On chip oscillator clock is used for the watchdog timer count source b4 b3 Reserved Bit Set to 0 Not
185. CM27 Bit 0 Oscillation Stop Detection Reset Where main clock stop is detected when the CM20 bit is 1 oscillation stop re oscillation detection function enabled the microcomputer is initialized coming to a halt oscillation stop reset refer to 4 SFR 5 Reset This status is reset with hardware reset Also even when re oscillation is detected the microcomputer can be initialized and stopped it is however necessary to avoid such usage During main clock stop do not set the CM20 bit to 1 and the CM27 bit to 0 7 5 2 Operation When CM27 Bit 1 Oscillation Stop Re oscillation Detection Interrupt Where the main clock corresponds to the CPU clock source and the CM20 bit is 1 oscillation stop re oscillation detection function enabled the system is placed in the following state if the main clock comes to a halt Oscillation stop re oscillation detection interrupt request is generated The on chip oscillator starts oscillation and the on chip oscillator clock becomes the clock source for CPU clock and peripheral functions in place of the main clock CM21 bit 1 on chip oscillator clock is the clock source for CPU clock CM22 bit 1 main clock stop detected CM23 bit 1 main clock stopped Where the PLL clock corresponds to the CPU clock source and the CM20 bit is 1 the system is placed in the following state if the main clock comes to a halt Since the CM21 bit remains unchanged set it
186. CRD bit 0 CRS bit in VICO register 0 CTS function is selected CTSi RTSi pin is CTS function CRD bit 0 CRS bit 1 RTS function is selected CTSURTSi pin is RTS function 14 1 1 8 CTS RTS Separate Function UARTO This function separates CTSO RTSO outputs RTSO from the P6 0 pin and accepts as input the CTSO from the P6 4 pin To use this function set the register bits as shown below CRD bit in UOCO register 0 enables UARTO CTS RTS CRS bit in UOCO register 1 outputs UARTO RTS CRD bit in U1CO register O enables UART1 CTS RTS CRS bit in U1CO register 0 inputs UART1 CTS RCSP bit in UCON register 1 inputs CTSO from the P6 4 pin CLKMD 1 bit in UCON register 0 CLKS1 not used Note that when using the CTS RTS separate function UART1 CTS RTS separate function cannot be used Figure 14 16 shows CTS RTS separate function usage Microcomputer TXDO P6 3 RXDO P6 2 CLKO P6 1 RTSO P6 0 CTSO P6 4 Figure 14 16 CTS RTS Separate Function Rev 1 10 Jul01 2005 page 145 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O 14 1 2 Clock Asynchronous Serial I O UART Mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format Table 14 5 lists the specifications of the UART mode Table 14 6 l
187. Cause Timer A2 IFSRER Select Bit 2 6 LINT zs 6 rp INT7 Interrupt Polarity One edge IFSR24 Switching Bit 1 6 Both edges INT8 Interrupt Polarity One edge FERES Switching Bit 1 6 Both edges Interrupt Request Cause CANO error IFSR26 Select Bit 5 key input Nothing is assigned When write set to 0 b7 When read its content is indeterminate 9 Interrupt 1 When setting this bit to 1 both edges make sure the POL bit in the INT6IC to INT8IC registers are set to 0 falling edge The INT6IC to INT8IC registers are only in the 128 pin version In the 100 pin version make sure the INT6 to INT8 interrupt polarity switching bitis set to 0 falling edge 2 Timer A2 and INT7 share the vector and interrupt control register When using the timer A2 interrupt set the IFSR20 bit to 0 Timer A2 When using INT7 interrupt set the IFSR20 bit to 1 INT7 The INT7 interrupt is only in the 128 pin version In the 100 pin version set the IFSR20 bit to 0 Timer A2 3 Timer A3 and INT6 share the vector and interrupt control register When using the timer A3 interrupt set the IFSR21 bit to 0 Timer A3 When using INT6 interrupt set the IFSR21 bit to 1 INT The INT6 interrupt is only in the 128 pin version In the 100 pin version set the IFSR21 bit to 0 Timer A3 4 Timer B1 and INT8 share the vector and interrupt control register When using the timer B1
188. D CTSo from UART1 nO Values set to the UOBRG register PCLK1 Bit in PCLKR register SMD to SMDO CKDIR Bits in UOMR register CLK1 to CLKO CKPOL CRD CRS Bits in UOCO register RCSP Bit in UCON register Figure 14 1 UARTO Block Diagram PCLK1 Main clock PLL clock or on chip oscillator clock o UART1 gt f1SIO or f2SIO gt f8SIO La f32SIO RXD polarity reversing RXD1 O circuit Clock source selection CLK1 to CLKO 1810 or f2810__ resio 2H CKDIR Internal UART reception SMD2 to SMDO 010 100 101 110 1 16 L Clock synchronous type 001 Reception control circuit Receive clock U1BRG UART transmission register fa2sio CKPOL CLK CLK1 Q polarity Lo External Clock synchronous type when external clock is selected 1 n1 1 Transmission Transmit clock type Wig 910 100 101 110 Clock synchronous o i 001 control circuit Clock synchronous type when internal clock is selected 0 ae o CLKMDO Clock synchronous type when internal clock is selected o reversing circuit lt Clock output pin select CTS1 RTS1 CTS0 CLKS1 1 pO CTS RTS
189. DDh 00XX0000b Bit Symbol Bit Name Function TMODO __ bibo TMODI Operation Mode Select Bit 0 4 Event counter mode Counts falling edge of external signal Count Polarity Select Counts rising edge of external signal Bit 1 1 0 Counts falling and rising edges of external signal Do not set a value TBOMR TB3MR registers Set to 0 in event counter mode TB1MR TB2MR TBAMR TB5MR registers Nothing is assigned When write set to 0 When read its content is indeterminate When write in event counter mode set to O When read in event counter mode its content is indeterminate Has no effect in event counter mode Can be set to 0 or 1 O Input from TBiIN pin 2 Event Clock Select Bit 1 TB overflow or underflow jai 1 exceptj 2 ifi 0 j 51fi 3 1 Effective when the TCK1 bit 0 input from TBiIN pin If the TCK1 bit 1 TBj overflow or underflow these bits can be set to 0 or 1 2 The port direction bit for the TBilN pin must be set to 0 input mode Figure 12 19 TBOMR to TB5MR Registers in Event Counter Mode Rev 1 10 Jul01 2005 page 113 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 Timers 12 2 3 Pulse Period and Pulse Width Measurement Mode In pulse period and pulse width measurement mode the timer measures pulse period or
190. Dissipation Mode On chip divided by 1 Oscillatondivided by 2 Mode divided by 4 divided by 8 divided by 16 On chip Oscillator Low power Dissipation Mode 0 or 1 NOTES 1 When the CMO5 bit is set to 1 main clock turned off in low speed mode the mode goes to low power dissipation mode and the CMOG6 bit is set to 1 divide by 8 mode simultaneously 2 The divide by n value can be selected the same way as in on chip oscillator mode Rev 1 10 Jul01 2005 page 49 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Clock Generating Circuit 7 4 2 Wait Mode In wait mode the CPU clock is turned off so are the CPU because operated by the CPU clock and the watchdog timer However if the PM22 bit in the PM2 register is 1 on chip oscillator clock for the watchdog timer count source the watchdog timer remains active Because the main clock sub clock and on chip oscillator clock all are on the peripheral functions using these clocks keep operating 7 4 2 1 Peripheral Function Clock Stop Function If the CMO2 bit in the CMO register is 1 peripheral function clocks turned off during wait mode the f1 f2 f8 132 f181O f8SIO f32SIO fAD fCANO and fCAN1 clocks are turned off when in wait mode with the power consumption redu
191. EW1 Mode Avoid rewriting any block in which the rewrite control program is stored 22 18 13 DMA Transfer In EW1 mode do not perform a DMA transfer while the FMROO bit in the FMRO register is set to 0 auto programming or auto erasing Rev 1 10 Jul01 2005 page 312 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 19 Flash Memory Programming Using Boot Program When programming the internal flash memory using boot program be careful about the pins state and connection as follows 22 19 1 Programming Using Serial I O Mode CTXO pin This pin automatically outputs H level CRXO pin Connect to CAN transceiver or connect via resister to VCC pull up Figure 22 9 shows a pin connection example for programming using serial I O mode 10 pin conngctor M16C 6NK M16C 6NM VCC monitor input CLK1 P6_5 RXD1 P6_6 NMI P8_5 TXD1 P6_7 RTSi P6 4 PC card type Flash Programmer EPM P5 5 ear CE P5_0 user reset signal Figure 22 9 Pin Connection for Programming Using Serial I O Mode 22 19 2 Programming Using CAN I O Mode RTS1 pin This pin automatically outputs H and L level Figure 22 10 shows a pin connection example for programming using CAN I O mode 10 pinconnggtor M16C 6NK M16C 6NM VCC monitor input CAN_H ras CAN L 820250 CRXO P9 5 a NB CE P5 0 P
192. Group M16C 6NK M16C 6NM 22 Usage Precaution 22 10 Thee Phase Motor Control Timer Function If there is a possibility that you may write data to TAi 1 register i 1 2 4 near Timer B2 overflow read the value of TB2 register verify that there is sufficient time until Timer B2 overflows before doing an immediate write to TAi 1 register In order to shorten the period from reading TB2 register to writing data to TAi 1 register ensure that no interrupt will be processed during this period If there is not enough time till Timer B2 overflows only write to TAi 1 register after Timer B2 overflowed Rev 1 10 Jul01 2005 page 296 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 11 Serial I O 22 11 1 Clock Synchronous Serial I O Mode 22 11 1 1 Transmission reception With an external clock selected and choosing the RTS function the output level of the RTSi pin goes to L when the data receivable status becomes ready which informs the transmission side that the recep tion has become ready The output level of the RTSi pin goes to H when reception starts So if the RTSi pin is connected to the CTSi pin on the transmission side the circuit can transmission and reception data with consistent timing With the internal clock the RTS function has no effect If a low level signal is applied to the N
193. IM mode set the IR bit to 0 interrupt not requested after setting these bits 3 The timing at which the framing error flag and the parity error flag are set is detected when data is transferred from the UARTi receive register to the UiRB register Rev 1 10 Jul01 2005 page 170 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O Table 14 18 Registers to Be Used and Settings in SIM Mode Register i 0 to 7 Set transmission data 0 to 7 Reception data can be read OER FER PER SUM Error flag 0 to 7 Set a transfer rate SMD2 to SMDO Set to 101b CKDIR Select the internal clock or external clock STPS Set to 0 PRY Set this bit to 1 for direct format or 0 for inverse format PRYE Set to 1 IOPOL Set to 0 CLK1 CLKO Select the count source for the U2BRG register CRS Invalid because the CRD bit 1 TXEPT Transmit register empty flag CRD Set to 1 NCH Set to 0 CKPOL Set to 0 UFORM Set this bit to O for direct format or 1 for inverse format TE Set this bit to 1 to enable transmission TI Transmit buffer empty flag RE Set this bit to 1 to enable reception RI Reception complete flag Set to 1 Set to 0 Set this bit to O for direct format or 1 for inverse format Set to 1 Set to 0 Set to 0 Set to 0 Set t
194. IN pin effective edge can be selected in program Timer B2 overflows or underflows Timer Aj overflows or underflows Timer Ak overflows or underflows Count Operation Up count or down count can be selected by external signal or program When the timer overflows or underflows it reloads the reload register contents and continues counting When operating in free running mode the timer continues counting without reloading Divided Ratio 1 FFFFh n 1 for up count 1 n 1 for down count n set value of the TAi register 0000h to FFFFh Count Start Condition Set the TAIS bit in the TABSR register to 1 start counting Count Stop Condition Set the TAIS bit to 0 stop counting Interrupt Request Generation Timing Timer overflow or underflow TAiIN Pin Function 1 0 port or count source input TAiOUT Pin Function I O port pulse output or up down count select input Read from Timer Count value can be read by reading the TAi register Write to Timer When not counting and until the 1st count source is input after counting start Value written to the TAi register is written to both reload register and counter When counting after 1st count source input Value written to the TAi register is written to only reload register Transferred to counter when reloaded next Select Function Free run count function Even when the timer overflows or underflows the reload register content is not reloaded to it Pulse output function Whenever the timer
195. Input mode PD8 1 Port P8 1 Direction Bit Functions as an input port PD8 2 Port P8 2 Direction Bit Output mode Functions as an output port PD8 3 Port P8 3 Direction Bit PD8 4 Port P8 4 Direction Bit Nothing is assigned When write set to 0 When read its content is indeterminate PD8 6 Port P8 6 Direction Bit O Input mode Sano as an input port 1 Output mode PD8_7 Port P8_7 Direction Bit Functions as an output port Figure19 7 PDO to PD13 Registers Rev 1 10 Jul01 2005 page 233 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 Programmable 1 O Ports Port Pi Register i 0 to 7 9 to 13 0 Symbol Address After Reset PO to P3 03E0h 03E1h 03E4h O3E5h Indeterminate P4 to P7 03E8h 03E9h O3ECh 03EDh Indeterminate P9 to P12 9 03F1h 03F4h O3F5h 03F8h Indeterminate P13 9 03F9h Indeterminate Bit Symbol A po Port Pi 0 Bit The pin level on any l O port which is set Port Pi 1 Bit for input mode can be read by readind the corresponding bit in this register Port Pi_2 Bit The pin level on any I O port which is Port Pi 3 Bit set for output mode can be controlled by writing to the corresponding bit in Port Pi 4 Bit this register Port Pi 5 Bit 0 L level Pi 6 Port Pi 6 Bit TP devel Pi 7 Port Pi 7 Bit 1 Since P7 1 and P9 1 are N channel open drain ports the data
196. LMAR register gt CiLMBR register gt CiGMR register gt CiLMAR register gt CiLMBR register Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 18 4 CAN SFR Registers Figures 18 6 to 18 11 show the CAN SFR registers CANi Message Control Register j i 0 1 j O to 15 4 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset COMCTLO to COMCTL15 0200h to 020Fh 00h C1MCTLO to C1MCTL15 0220h to 022Fh 00h 18 CAN Module When set to reception slot Successful 0 The content of the slot is read or still under NeowpData Reception Flag processing by the CPU 1 The CAN module has stored new data in the slot When set to transmission slot Successful SentData Transmission Flag 1 Transmission is successfully completed When set to reception slot Under Reception 0 The message is valid 1 The message is invalid The message is being updated InvalData When set to transmission slot 0 Transmission is not started or completed yet TrmActive Transmission 0 Waiting for bus idle or completion of arbitration Flag 1 Transmitting When set to reception slot 0 No message has been overwritten in this slot MsgLost Overwrite Flag 1 This slot already contained a message but it has been overwritten by a new one Remote Frame 0 Data frame transmission reception status Transmission 1 Remote frame transmission re
197. M16C 6NM 20 Flash Memory Version M16C 6N Group M16C 6NK Flash memory version Connect oscilator Mode setup method VCC1 VSS VSS to VCC1 Package PLQP0100KB A Figure 20 17 Pin Connections for CAN I O Mode 1 Rev 1 10 Jul01 2005 page 266 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Flash Memory Version 102 01 1100 9091198 97 96 95 64 93 92 91 90 B9 88 8788 85 B4 83 B2 i81 80 79 78 7 7 76 75 74 73 721 7 1 70 69 68 167 66 6 M16C 6N Group M16C 6NM Flash memory version 1J 2 3 4 5 L6 L7 J 8 9 Jitoj t 1 12 r3 t 4 15 r6 1 7 18 1 9 20 P1 P2 P3 P4 P5 P6 P7 28 P9 80 31 B2 B3 B4 B5 B6 97 38 Connect oscillator circuit Mode setup method VCC1 VSS VSS to VCC1 VCC2 VSS VCC1 Package PLQP0128KB A Figure 20 18 Pin Connections for CAN l O Mode 2 Rev 1 10 Jul01 2005 page 267 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Flash Memory Version 20 6 2 Example of Circuit Application in CAN I O Mode Figure 20 19 shows example of circuit application in CAN I O mode Refe
198. MI pin when the IVPCR1 bit in the TB2SC register 1 three phase output forcible cutoff by input on NMI pin enabled the RTS2 and CLK2 pins go to a high imped ance state 22 11 1 2 Transmission When an external clock is selected the conditions must be met while if the CKPOL bit in the UiCO register 0 transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock the external clock is in the high state if the CKPOL bit 1 transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock the external clock is in the low state The TE bit in the UiC1 register 1 transmission enabled e The TI bit in the UiC1 register O data present in UiTB register e If CTS function is selected input on the CTSi pin L 22 11 1 3 Reception In operating the clock synchronous serial I O operating a transmitter generates a shift clock Fix settings for transmission even when using the device only for reception Dummy data is output to the outside from the TXDi i 0 to 2 pin when receiving data When an internal clock is selected set the TE bit in the UiC1 register to 1 transmission enabled and write dummy data to the UiTB register and the shift clock will thereby be generated When an external clock is selected set the TE bit to 1 and write dummy data to the UiTB register and the shift clock will be generated when the external clock is
199. Message Box 5 Identifier DLC 02B4h 02B5h 02B6h 02B7h 02B8h o2B9h l 02BAh Message Box 5 Data Field 02BBh 02BCh 02BDh O2BEh 02BFh Message Box 5 Time Stamp X Undefined Rev 1 10 Jul01 2005 page 23 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 12 SFR Information 12 Address 02C0h 02C1h cacan CAN1 Message Box 6 Identifier DLC 02C4h 02C5h 02C6h 02C7h 02C8h 02C9h M B Data Fiel 02CAh essage Box 6 Data Field 02CBh 02CCh 02CDh 02CEh me 02CFh Message Box 6 Time Stamp 02DOh 02D1h 02D3h Message Box 7 Identifier DLC 02D4h 02D5h 02D6h 02D7h 02D8h 02D9h 02DAh Message Box 7 Data Field 02DBh 02DCh 02DDh 02DEh q 02DFh Message Box 7 Time Stamp 02E0h 02E1h 02E2h 02E3h Message Box 8 Identifier DLC 02E4h 02E5h 02E6h 02E7h 02E8h 02E9h Message Box 8 Data Field 02EBh 02ECh 02EDh O2bEEh pur O2EFh Message Box 8 Time Stamp 02F1h 02F2h T 02F3h Message Box 9 Identifier DLC 02F4h 02F5h 02F6h 02F7h 02F8h 02F9h 2 O2FAh Message Box 9 Data Field 02FBh 02FCh 02FDh 02FEh coat O2FFh Message Box 9 Time Stamp X Undefined
200. Module 18 11 Basic CAN Mode When the BasicCAN bit in the CiCTLR register i 0 1 is set to 1 Basic CAN mode enabled slots 14 and 15 correspond to Basic CAN mode In normal operation mode each slot can handle only one type message at a time either a data frame or a remote frame by setting CIMCTLj regisrer j 2 O to 15 However in Basic CAN mode slots 14 and 15 can receive both types of message at the same time When slots 14 and 15 are defined as reception slots in Basic CAN mode received messages are stored in slots 14 and 15 alternately Which type of message has been received can be checked by the RemActive bit in the CiMCTLj register Figure 18 19 shows the operation of slots 14 and 15 in Basic CAN mode Shot 14 er 7 Slot 15 Locked empty Locked empty Locked Msg n 1 Msg n 1 Msg n 2 Figure 18 19 Operation of Slots 14 and 15 in Basic CAN Mode When using Basic CAN mode note the following points 1 Setting of Basic CAN mode has to be done in CAN reset initialization mode 2 Select the same ID for slots 14 and 15 Also setting of the CILMAR and CiLMBR register has to be the same 3 Define slots 14 and 15 as reception slot only 4 There is no protection available against message overwrite A message can be overwritten by a new message b Slots 0 to 18 can be used in the same way as in normal CAN operation mode Rev 1 10 Jul01 2005 page 220 of 318 RENESAS REJ09B0124 0110 Under development This
201. N7 is selected 2 3 MDO A D Operation Mode ERE Select Bit 0 Repeat mode 0 Software trigger 0 A D conversion disabled ADST A D Conversion Start Flag AD conversi n started 1 Refer to NOTE 2 for ADCON2 CKSO Frequency Select Bit 0 Register 1 If the ADCONO register is rewritten during A D conversion the conversion result will be indeterminate 2 ANO 0 to AN 7 and AN2 0 to AN2 7 can be used in same way as ANO to AN7 Use the ADGSEL1 to ADGSELO bits in the ADCON2 register to select the desired pin 3 After rewriting the MD1 to MDO bits set the CH2 to CHO bits over again using another instruction A D Control Register 1 b7 b6 b5 b4 b3 b2 bt bO Symbol Address After Reset at fo ADCON1 03D7h 00h CEA occupe CM A D Sweep Pin Select Bit Invalid in repeat mode A D Operation Mode Set to 0 when repeat mode is Select Bit 1 selected oe 8 bit mode BITS 8 10 Bit Mode Select Bit 10 bit mode Refer to NOTE 2 for ADCON2 VCUT VREF Connect Bit 2 1 VREF connected mw b7 b6 0 O ANEXO and ANEX1 are not used RW External Op Amp 0 1 ANEXO input is A D converted Connection Mode Bit 1 0 ANEX1 input is A D converted 1 1 External op amp connection mode 1 If the ADCON register is rewritten during A D conversion the conversion result will be indeterminate 2 f the VCUT bit is reset from 0 VREF unconnected to 1 VREF connected wait for 1 us or more before starting A D conversion
202. O o ulo 00 o 01 Event counter mode TMOD1 to TMODO 00 Timer mode 10 One shot timer mode 11 Pulse width measuring mode Noise Pi 01 filter TCK1 to TCKO O 11 TA2TGH to TA2TGL 00 01 Event counter mode Reset Timer AO interrupt Timer A1 interrupt Timer A2 interrupt E O lo TMOD1 to TMODO 00 Timer mode 10 E eo lo 10 One shot timer mode 11 Pulse width measuring mode Noise filter TCK1 to TCKO 00 01 11 TA3TGH to TA3TGL Noise filter PCLKO Bit in PCLKR register O 10 OG 00 11 TA4TGH to TA4TGL Timer B2 overflow or underflow 00 5 01 Event counter mode TMOD1 to TMODO 00 Timer mode 10 One shot timer mode 11 Pulse width measuring mode o 01 Event counter mode TCK1 to TCKO TMOD1 to TMODO Bits in TAiMR register i 0 to 4 TAiTGH to TAITGL Bits in ONSF register or TRGSR register NOTE 1 Be aware that TAOIN shares the pin with RXD2 SCL2 and TB5IN Figure 12 1 Timer A Configuration Rev 1 10 Jul 01 2005 page 92 of 318 REJO9B0124 0110 131 NESAS Timer A3 interrupt Timer A4 interrupt Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 Timers PCLKO 0 Clock prescaler Main clock n S eee ie f1 or f2 i PLL
203. O 3 p lt gt lt gt gt gt EE ap P N Pie wm A ES E on NI o PO 2 ANO 2 PO 1 ANO 1 PO O ANO 0 P10 7 AN7 KI gt M16C 6N Group P10 6 ANG KI2 lt P10 5 ANS KTI e M 16C 6N K a P10_4 AN4 KI0 lt gt P6_0 CTSO RTSO P10_3 AN3 a P6_1 CLKO P10_2 AN2 gt P6 2 RXDO SCLO P10 1 AN1 lt P6 3 TXDO SDAO AVSS gt P6_4 CTS1 RTS1 CTSO CLKS1 P10 0 ANO lt e P6 5 CLK1 VREF 3 P6 6 RXD1 SCL1 AVCC gt P6 7 TXD1 SDA1 P9 7 ADTRG SIN4 a P7 O TXD2 SDA2 TAOOUT P9 6 ANEX1 CTXO SOUTA a P7 1 RXD2 SCL2 TAOIN TBSIN 1 P9 5 ANEXO CRXO CLK4 gt P7 2 CLK2 TA1OUT V N vU PAAS wm LKOUT O i ES o Ss FI bz mo a lt P7_3 CTS2 RTS2 TA11N V SIN4 P7_7 TASIN CRX CLK4 P8_4 iINT2 ZP lt gt P8 2 INTO e P8 5 NMI P8_3 INT1 lt gt P8_1 TA4IN U a SOUTA P8_6 XCOUT o P8_7 XCIN gt o P9_3 DAO TB3IN lt s
204. O UO ANO 1O ANO 2O ANO 3O 010b 011b ANO_4 0 ANO 5O Port P10 group Decoder for channel selection ANO O ADGSEL1 to ADGSELO 00b ANO O ANO O OPA1 to OPAO 00b ot ANO O AN0 O ANO O ANO O AN0 O PMO1 to PMOO 00b ADGSEL1 to ADGSELO 10b OPA to OPAO 00b X ANO 6O ANO 7O Port P2 group AN2 0O PMO1 to PM00 00b ADGSEL1 to ADGSELO 10b OPA1 to OPAO 00b AN2_1 O AN2 20 AN2_30 AN2_40 AN2 50 AN2_6 O AN2_7 0 PMO1 to PMO0 00b r ADGSEL1 to ADGSELO 11b OPA1 to OPAO 11b OPAO 1 a ADGSEL1 to ADGSELO 10b ADGSEL1 to ADGSELO 00b OPA1 to OPAO 11b PMO1 to PM00 00b r4 OPA1 to OPAO 11b 01b OPA to OPAO ANEXO y ANEX1O OPA1 1 SS o 4 OPA1 1 E Figure 15 1 A D Converter Block Diagram Rev 1 10 Jul 01 2005 page 182 of 318 REJO9B0124 0110 ENESAS VIN Comparator Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 A D Converter A D Control Register 0 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset ADCONO 03D6h 00000XXXb Bit Symbol RW Function varies Analog Input Pin Select Bit with each operation mode One shot mode A D Operation Mode Repeat mode Select Bit 0 Single sweep mode Repe
205. ON register i 0 1 to 1 enabled the DMAC operates as follows 1 Reload the forward address pointer with the SARi register value when the DSD bit in the DMiCON register is 1 forward or the DARi register value when the DAD bit in the DMiCON register is 1 forward 2 Reload the DMAi transfer counter with the DMAi transfer counter reload register value If the DMAE bit is set to 1 again while it remains set the DMAC performs the above operation However if a DMA request may occur simultaneously when the DMAE bit is being written follow the steps below Step 1 Write 1 to the DMAE bit and DMAS bit in the DMiCON register simultaneously Step 2 Make sure that the DMAi is in an initial state as described above 1 and 2 in a program If the DMAi is not in an initial state the above steps should be repeated 11 4 DMA Request The DMAC can generate a DMA request as triggered by the cause of request that is selected with the DMS and DSEL3 to DSELO bits in the DMISL register i 0 1 on either channel Table 11 4 shows the timing at which the DMAS bit changes state Whenever a DMA request is generated the DMAS bit is set to 1 DMA requested regardless of whether or not the DMAE bit is set If the DMAE bit was set to 1 enabled when this occurred the DMAS bit is set to 0 DMA not requested immediately before a data transfer starts This bit cannot be set to 1 ina program it can onl
206. ONO 00000XXXb A D Control Register 1 ADCON1 00h D A Register O DAO 00h D A Register 1 00h D A Control Register 00h Port P14 Control Register 1 XX00XXXXb Pull Up Control Register 3 1 00h Port PO Register XXh Port P1 Register XXh Port PO Direction Register 00h Port P1 Direction Register 00h Port P2 Register XXh Port P3 Register XXh Port P2 Direction Register 00h Port P3 Direction Register 00h Port P4 Register XXh Port P5 Register XXh Port P4 Direction Register 00h Port P5 Direction Register 00h Port P6 Register XXh Port P7 Register XXh Port P6 Direction Register 00h Port P7 Direction Register 00h Port P8 Register XXh Port P9 Register XXh Port P8 Direction Register 00X00000b Port P9 Direction Register 00h Port P10 Register XXh Port P11 Register 1 XXh Port P10 Direction Register 00h Port P11 Direction Register 1 00h Port P12 Register 1 XXh Port P13 Register 1 XXh Port P12 Direction Register 1 00h Port P13 Direction Register 1 00h Pull up Control Register 0 00h Pull up Control Register 1 00h Pull up Control Register 2 00h Port Control Register 00h X Undefined NOTES 1 These registers exist only in the128 pin version 2 The blank areas are reserved and cannot be accessed by users Rev 1 10 Jul01 2005 page 28 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 5 Reset 5 Reset Hardware reset softw
207. Oto2 Table 14 4 P6_4 Pin Functions Bit set Value Pin Function U1CO Register UCON Register PD6 Register CRD bit CRS bit RCSP bit CLKMD1 bit CLKMDO bit PD6_4 bit Input 0 Output 1 0 or 1 NOTES 1 In addition to this set the CRD bit in the UOCO register to 0 CTSO RTSO enabled and the CRS bit in the UOCO register to 1 RTSO selected 2 When the CLKMD1 bit 1 and the CLKMDO bit 0 the following logic levels are output High if the CLKPOL bit in the U1CO register O Low if the CLKPOL bit 1 Rev 1 10 Jul01 2005 page 140 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 1 Example of Transmit Timing when internal clock is selected Transfer clock TE bit in UiC1 register TI bit in UiC1 register CTSi CLKi TXDi TXEPT bit in UiCO register IR bit in SITIC register TC e VUU UU nuu un Write data to the UiTB register Transferred from the UiTB register to the UARTI transmit register gt Stopped pulsing because CTSi H Stopped pulsing because the TE bit 0 COSOQBSELOAOQOSOOE_OO HOEO pr x i i i i Pd Set to 0 when interrupt request is accepted or set to 0 in a program TC TCLK 2 n 1 fj fj frequency of UIBRG count source f1SIO f2SIO f8SIO f32SIO n value set to t
208. P9 2 to P9 7 P10 Oto P10 7 P11 Oto P11 7 P12 Oto P12 7 P13 0 to P13 7 P14 0 P14 1 HIGH Average PO 0 to PO 7 P1 Oto P1 7 P2_0 to P2 7 P8 Oto P3 7 Output Current P4 0 to P4 7 P5 Oto P5 7 P6 Oto P6 7 P7 0 P7 2to P7 7 P8 0 to P8 4 P8 6 P8 7 P9 0 P9 2 to P9 7 P10_0 to P10 7 P11 Oto P11 7 P12 Oto P12 7 P13 0 to P13 7 P14 0 P14 1 loL peak LOW Peak PO 0to PO 7 P1 Oto P1 7 P2 Oto P2 7 P3 Oto P3 7 Output Current P4 0 to P4 7 P5_0 to P5 7 P6 Oto P6 7 P7 0to P7 7 P8_0 to P8 4 P8 6 P8 7 P9 Oto P9 7 P10 Oto P10 7 P11 Oto P11 7 P12 0 to P12 7 P13_0 to P13 7 P14 0 P14 1 loL avg NOTES 1 Referenced to VCC 3 0 to 5 5V at Topr 40 to 85 C unless otherwise specified LOW Average P0_0 to PO 7 P1_0 to P1 7 P2 Oto P2 7 P3 Oto P3 7 Output Current P4 0 to P4 7 P5_0 to P5 7 P6 Oto P6 7 P7_0 to P7 7 P8 0to P8 4 P8 6 P8 7 P9 Oto P9 7 P10 Oto P10 7 P11_0 to P11 7 P12 O0 to P12 7 P13 O to P13 7 P14 0 P14 1 2 The mean output current is the mean value within 100 ms 3 The total loL peax for ports PO P1 P2 P8 6 P8 7 P9 P10 P11 P14 0 and P14 1 must be 80mA max The total lot peak for ports P3 P4 P5 P6 P7 P8 0 to P8 4 P12 and P13 must be 80mA max The total lon peak for ports PO P1 and P2 must be 40mA max The total lon peak for ports P3 P4 P5 P12 and P13 must be 40mA max The total lon peak for ports P6 P7
209. POL 1 CKPH 1 Data output timing Data input timing w Ano Xm X oz X 09 os X os os or TT 111111 Figure 14 30 Transmission and Reception Timing CKPH z 1 in Slave Mode External Clock Rev 1 10 Jul01 2005 page 167 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O 14 1 5 Special Mode 3 IE Mode In this mode one bit of IEBus is approximated with one byte of UART mode waveform Table 14 16 lists the registers used in IE mode and the register values set Figure 14 31 shows the functions of bus collision detect function related bits If the TXDi pin i 0 to 2 output level and RXDi pin input level do not match a UARTi bus collision detect interrupt request is generated Use the IFSRO6 and IFSRO7 bits in the IFSRO register to enable the UARTO UARTI bus collision detect function Table 14 16 Registers to Be Used and Settings in IE Mode Register 0 to 8 Set transmission data 0 to 8 Reception data can be read OER FER PER SUM Error flag 0 to 7 Set a transfer rate SMD2 to SMDO Set to 110b CKDIR Select the internal clock or external clock STPS Set to 0 PRY Invalid because the PRYE bit 0 PRYE Set to 0 IOPOL Select the TXD RXD input output polarity CLK1 CLKO Select the count source for th
210. Power Dissipation Topr 25 C 700 Operating Ambient When the Microcomputer is Operating 40 to 85 Temperature Flash Program Erase 0 to 60 Storage Temperature 65 to 150 NOTE 1 Ports P11 to P14 are only in the 128 pin version Rev 1 10 Jul01 2005 page 269 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Table 21 2 Recommended Operating Conditions 1 Parameter Supply Voltage VCC1 VCC2 21 Electric Characteristics Standard Analog Supply Voltage Supply Voltage Analog Supply Voltage HIGH Input PO 0to PO 7 P1 Oto P1 7 P2 Oto P2 7 P3 0toP3 7 Voltage P4 0to P4 7 P5 Oto P5 7 P6 Oto P6 7 P7 0 P7 2toP7 7 P8 0 to P8 7 P9 0 P9 2to P9 7 P10_0 to P10 7 P11_0 to P11 7 P12 Oto P12 7 P13 0 to P13 7 P14 0 P14 1 XIN RESET CNVSS BYTE P7 1 P9 1 LOW Input P0_0 to PO 7 P1_0 to P1 7 P2_0 to P2 7 P3 0toP3 7 Voltage P4_0 to P4 7 P5 0to P5 7 P6 Oto P6 7 P7 Oto P7 7 P8 0to P8 7 P9_0 to P9 7 P10_0 to P10 7 P11_0 to P11 7 P12_0 to P12 7 P13 0 to P13 7 P14 0 P14 1 XIN RESET CNVSS BYTE HIGH Peak PO Oto PO 7 P1 Oto P1 7 P2 Oto P2 7 P3 Oto P3 7 Output Current P4 0 to P4 7 P5 Oto P5 7 P6 Oto P6 7 P7 0 P7 2to P7 7 P8 0 to P8 4 P8 6 P8 7 P9 0
211. R 00400h Internal RAM XXXXXh Reserved area E Special page Internal ROM H vector table data area r OF000h OFFFFh 10000h E Overflow 3 Internal RAM Internal ROM 1 Reserved area i BRK instruction Capacity Address XXXXXh Capacity Address YYYYYh H Address match 16 Kbytes 043FFh 192 Kbytes D0000h H Single step Oscillation stop and re oscillation 7 waichdo it g timer 20 Kbytes 053FFh e56Kbytes coooon YYYYYh i Internal ROM 31 Kbytes 07FFFh 384 Kbytes A0000h program area 512Kbytes 80000h REF NOTES 1 As for the flash memory version 4 Kbyte space block A exists 2 Shown here is a memory map for the case where the PM13 bit in the PM1 register is 1 If the PM13 bit is set to 0 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used 3 When using the masked ROM version write nothing to internal ROM area Figure 3 1 Memory Map Rev 1 10 Jul01 2005 page 12 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR 4 Special Function Register SFR SFR Special Function Register is the control register of peripheral functions Tables 4 1 to 4 16 list the SFR information Table 4 1 SFR Information 1 Processor Mode Register 0 00h Processor Mode Register 1 00001000b
212. R register to 1 count starts Always make sure the TBiMR register is modified while the TBiS bit remains 0 count stops regardless whether after reset or not The counter value can be read out on the fly at any time by reading the TBi register However if this register is read at the same time the counter is reloaded the read value is always FFFFh If the TBi register is read after setting a value in it while not counting but before the counter starts counting the read value is the one that has been set in the register Rev 1 10 Jul01 2005 page 294 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 9 2 3 Timer B Pulse Period pulse Width Measurement Mode The timer remains idle after reset Set the mode count source etc using the TBiMR i 0 to 5 register before setting the TBiS bit in the TABSR or TBSR register to 1 count starts Always make sure the TBiMR register is modified while the TBiS bit remains 0 count stops regardless whether after reset or not To set the MR3 bit to 0 by writing to the TBiMR register while the TBiS bit 1 count starts be sure to write the same value as previously written to the TMODO TMOD1 MRO MR1 TCKO and TCK1 bits and a O to the MR2 bit The IR bit in the TBilC register goes to 1 interrupt request when an effective edge
213. REJ09B0124 0110 Everywhere you imagine y q E N ESAS M16C 6N Group M16C 6NK M16C 6NM Hardware Manual RENESAS 16 BIT SINGLE CHIP MICROCOMPUTER M16C FAMILY M16C 60 SERIES Before using this material please visit our website to verify that this is the most updated document available Rev 1 10 Renesas Technology Revision date Jul 01 2005 WWW renesas com Keep safety first in your circuit designs e Renesas Technology Corporation puts the maximum effort into making semiconductor prod ucts better and more reliable but there is always the possibility that trouble may occur with them Trouble with semiconductors may lead to personal injury fire or property damage Remember to give due consideration to safety when making your circuit designs with ap propriate measures such as i placement of substitutive auxiliary circuits ii use of non flammable material or iii prevention against any malfunction or mishap Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer s application they do not convey any license under any intellectual property rights or any other rights belonging to Renesas Technology Corporation or a third party Renesas Technology Corporation assumes no responsibility for any damage or infringe ment of any third party s rights originating in the use of any
214. ROM and Boot ROM Areas An erase block operation in the boot ROM area is applied to only one 4 Kbyte block The rewrite control program in standard serial l O and CAN I O modes are written in the boot ROM area before shipment Do not rewrite the boot ROM area if using the serial programmer In parallel 1 O mode the boot ROM area is located in addresses OFFOOOh to OFFFFFh Rewrite this address range only if rewriting the boot ROM area Do not access addresses other than addresses OFFOOOh to OFFFFFh 20 5 2 ROM Code Protect Function The ROM code protect function prevents the flash memory from being read and rewritten in parallel I O mode Refer to 20 2 Functions to Prevent Flash Memory from Rewriting Rev 1 10 Jul01 2005 page 264 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 6 CAN I O Mode In CAN I O mode the CAN programmer supporting the M16C 6N Group M16C 6NK M16C 6NM can be used to rewrite the flash memory user ROM area in the microcomputer mounted on a board For more information about the CAN programmer contact your CAN programmer manufacturer Refer to the user s manual included with your CAN programmer for instructions Table 20 8 lists pin functions for CAN I O mode Figures 20 17 and 20 18 show pin connections for CAN I O mode 20 6 1 ID Code Check Function 20 Flash Memory Version The ID code check fun
215. RT2 Receive Buffer Register U2RB The blank areas are reserved B 4 Symbol CANO Message Control Register 0 COMCTLO CANO Message Control Register 1 COMCTL1 CANO Message Control Register 2 COMCTL2 CANO Message Control Register 3 COMCTL3 CANO Message Control Register 4 COMCTL4 CANO Message Control Register 5 COMCTL5 CANO Message Control Register 6 COMCTL6 CANO Message Control Register 7 COMCTL7 CANO Message Control Register 8 COMCTL8 CANO Message Control Register 9 CANO Message Control Register 10 COMCTL9 COMCTL10 CANO Message Control Register 11 COMCTL11 CANO Message Control Register 12 COMCTL12 CANO Message Control Register 13 COMCTL13 CANO Message Control Register 14 COMCTL14 CANO Message Control Register 15 COMCTL15 Symbol CANO Acceptance Filter Support Register COAFS CAN Acceptance Filter Support Register C1AFS 0211h CANO Control Register CANO Status Register COCTLR 0214h 0215h CANO Slot Status Register 0216h 0217h CANO Interrupt Control Register SET CANO Extended ID Register 021Bh CANO Configuration Register 021Ch CANO Receive Error Count Register 021Dh CANO Transmit Error Count Register COTECR 02 IEn CANO Time Stamp Register COTSR 212 212 PCLKR 40 Peripheral Clock Select Registe
216. Rising edge of SCLi 9th bit Falling edge of SCLi 9th bit Falling and rising edges of SCLi 9th bit UARTI Transmission Output Delay Not delayed Delayed Functions of P6_3 P6_7 and P7_0 Pins TXDi output SDAi input output Functions of P6_2 P6_6 and P7_1 Pins RXDi input SCLi input output Functions of P6_1 P6_5 and P7_2 Pins CLKi input or output selected Cannot be used in IC mode Noise Filter Width 15 ns 200 ns Read RXDi and SCLi Pins Levels Possible when the corresponding port direction bit 0 Always possible no matter how the corresponding port direction bit is set Initial Value of TXDi and SDAi Outputs CKPOL 0 H CKPOL 1 L The value set in the port register before setting 1 C mode Initial and End Value of SCLi H H L DMA1 Factor 9 UARTI reception Acknowledgment detection ACK UARTI reception Falling edge of SCLi 9th bit Store Received Data 1st to 8th bits of the received data are stored into bit 7 to bit O in the UIRB register 1stto 7th bits of the received data are stored into bit 6 to bit 0 in the UIRB register 8th bit is stored into bit 8 in the UIRB register 1st to 8th bits are stored into bit 7 to bit 0 in UiRB register Read Received Data i Oto2 NOTES The UIRB register status is read Bit 6 to bit 0 in the UIRB register are read as bit 7 to bit 1 B
217. SAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 3 PLL Frequency Synthesizer Stabilize supply voltage so that the standard of the power supply ripple is met Refer to 21 Electrical characteristics Rev 1 10 Jul01 2005 page 281 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 4 Power Control When exiting stop mode by hardware reset set RESET pin to L until a main clock oscillation is stabilized Set the MRO bit in the TAiMR register i 0 to 4 to 0 pulse is not output to use the timer A to exit stop mode Insert more than four NOP instructions after an WAIT instruction or a instruction to set the CM10 bit in the CM1 register to 1 all clock stopped When shifting to wait mode or stop mode an instruction queue reads ahead to the next instruction to halt a program by an WAIT instruction and an instruction to set the CM10 bit to 1 The next instruction may be executed before entering wait mode or stop mode depending on a combination of instruction and an execution timing In the main clock oscillation or low power dissipation mode set the CMO2 bit in the CMO register to 0 do not stop peripheral function clock in wait mode before shifting to stop mod
218. Simultaneously with oscillation stop re oscillation detection interrupt request occurrence the CM22 bit becomes 1 When the CM22 bit is set at 1 oscillation stop re oscillation detection interrupt are disabled By setting the CM22 bit to 0 in the program oscillation stop re oscillation detection interrupt are enabled If the main clock stops during low speed mode where the CM20 bit is 1 an oscillation stop re oscillation detection interrupt request is generated At the same time the on chip oscillator starts oscillating In this case although the CPU clock is derived from the sub clock as it was before the interrupt occurred the peripheral function clocks now are derived from the on chip oscillator clock To enter wait mode while using the oscillation stop and re oscillation detection function set the CMO2 bit to 0 peripheral function clocks not turned off during wait mode Since the oscillation stop and re oscillation detection function is provided in preparation for main clock stop due to external factors set the CM20 bit to 0 oscillation stop re oscillation detection function disabled where the main clock is stopped or oscillated in the program that is where the stop mode is selected or the CMO5 bit is altered This function cannot be used if the main clock frequency is 2 MHz or less In that case set the CM20 bit to 0 Switch the main clock Determine several times whether the CM
219. TT XXh Timer B2 Interrupt Occurrence Frequency Set Counter ICTB2 XXh nterrupt Cause Select Register 2 IFSR2 X0000000b XXh Ti i TB 01D1h imer B3 Register 3 XXh 01D2h A XXh 01D3h imer B4 Register TB4 XXh 01D4h TB5 XXh imer B5 Register XXh SI 06 Transmit Receive Register 1 S6TRR XXh SI O6 Control Register 1 S6C 01000000b SI O6 Bit Rate Generator 1 S6BRG XXh SI O3 4 5 6 Transmit Receive Register 2 S3456TRR XXXX0000b Timer B3 Mode Register TB3MR 00XX0000b Timer B4 Mode Register TB4MR 00XX0000b Timer B5 Mode Register TB5MR 00XX0000b Interrupt Cause Select Register 0 IFSRO 00h Interrupt Cause Select Register 1 IFSR1 00h SI O3 Transmit Receive Register S3TRR XXh SI 03 Control Register S3C 01000000b SI O3 Bit Rate Generator S3BRG XXh SI O4 Transmit Receive Register S4TRR XXh SI O4 Control Register S4C 01000000b SI O4 Bit Rate Generator SABRG XXh SI O5 Transmit Receive Register 1 S5TRR XXh SI O5 Control Register 1 S5C 01000000b SI O5 Bit Rate Generator 1 S5BRG UARTO Special Mode Register 4 UOSMR4 UARTO Special Mode Register 3 UOSMR3 UARTO Special Mode Register 2 UOSMR2 UARTO Special Mode Register UOSMR UART1 Special Mode Register 4 U1SMR4 UART1 Special Mode Register 3 U1SMR3 UART1 Special Mode Register 2 U1SMR
220. This is an A D trigger input pin ANEXO This is the extended analog input pin for the A D converter and is the output in external op amp connection mode ANEX1 This is the extended analog input pin for the A D converter D A converter DAO DA1 These are the output pins for the D A converter CAN module CRXO0 CRX1 These are the input pins for the CAN module CTXO CTX1 These are the output pins for the CAN module I O port PO 0to PO 7 P1 0toP1 7 P2 Oto P2 7 P3 0to P3 7 P4 Oto P4 7 P5 0to P5 7 P6 0 to P6 7 P7 0to P7 7 P8 Oto P8 4 P8 6 P8 7 P9 0to P9 7 P10 0 to P10 7 P11 Oto P11 7 P12 0to P12 7 P13_0 to P13 7 P14_0 P14 10 8 bit I O ports in CMOS having a direction register to select an input or output Each pin is set as an input port or output port An input port can be set for a pull up or for no pull up in 4 bit unit by program except P7 1 and P9 1 for the N channel open drain output I Input O NOTE P8 5 Output Input pin for the NMI interrupt Pin states can be read by the P8 5 bit in the P8 register I O Input Output 1 Ports P11 to P14 are only in the 128 pin version Rev 1 10 Jul01 2005 page 9 of 318 REJ09B0124 0110 7tENESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 2 Central Processing Unit CPU 2 Central Processing Unit CPU
221. Three Phase Motor Control Timer Functions Block Diagram The above applies to INVCO 01XX110Xb and INVC1 010XXX00b X varies depending on each system The examples of PWM output change are Default value of the IDBO and IDB1 registers DUO 0 DUBO 1 DU1 1 DUB1 1 They are changed to DUO 1 DUBO 0 DU1 1 DUB1 1 by the timer B2 interrupt Figure 13 10 Sawtooth Wave Modulation Operation Rev 1 10 Jul01 2005 page 127 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O 14 Serial I O Serial I O is configured with 7 channels UARTO to UART2 and SI O3 to SI O6 NOTE 1 100 pin version supports 5 channels UARTO to UART2 SI O3 SI O4 128 pin version supports 7 channels UARTO to UART2 SI O3 to SI O6 14 1 UARTI i 0 to 2 UARTi each have an exclusive timer to generate a transfer clock so they operate independently of each other Figures 14 1 to 14 3 show the block diagram of UARTI Figure 14 4 shows the block diagram of the UARTi transmit receive UARTI has the following modes Clock synchronous serial l O mode Clock asynchronous serial I O mode UART mode Special mode 1 1 C mode Special mode 2 Special mode 3 Bus collision detection function IE mode Special mode 4 SIM mode UART2 Figures 14 5 to 14 10 show the UARTi related registers Refer to tables listing
222. Timer 15 bits X 1 channel with prescaler Interrupt Internal 32 sources External 9 sources Software 4 sources Priority level 7 levels Clock Generating Circuit 4 circuits Main clock oscillation circuit Sub clock oscillation circuit On chip oscillator PLL frequency synthesizer Equipped with a built in feedback resistor Oscillation Stop Detection Function Main clock oscillation stop and re oscillation detection function Electrical Characteristics Supply Voltage VCC 3 0 to 5 5V f BCLK 24MHz 1 1 prescaler without software wait VCC 4 2 to 5 5V f BCLK 20MHz 1 1 prescaler without software wait Power Mask ROM Consumption 21mA f BCLK 24MHz PLL operation no division Flash Memory 23mA f BCLK 24MHz 21mA f BCLK 20MHz PLL operation no division _ PLL operation no division Mask ROM Flash Memory 3pA f BCLK 32kHz Wait mode Oscillation capacity Low 0 8pA Stop mode Topr 25 C Flash Memory Version Program Erase Supply Voltage 3 0 0 3V or 5 0 0 5V 5 0 0 5V Program and Erase Endurance 100 times 1 0 Characteristics I O Withstand Voltage 5 0V Output Current 5mA Operating Ambient Temperature 40 to 85 C T version 40 to 85 C V version 40 to 125 C option Device Configuration CMOS high performance silicon gate Package NOTES 1 PC bus is
223. U clock to operate the CPU and peripheral function clocks to operate the peripheral functions 7 2 1 CPU Clock and BCLK These are operating clocks for the CPU and watchdog timer The clock source for the CPU clock can be chosen to be the main clock sub clock on chip oscillator clock or the PLL clock If the main clock or on chip oscillator clock is selected as the clock source for the CPU clock the selected clock source can be divided by 1 undivided 2 4 8 or 16 to produce the CPU clock Use the CMO6 bit in the CMO register and the CM17 to CM16 bits in the CM1 register to select the divide by n value When the PLL clock is selected as the clock source for the CPU clock the CMO6 bit should be set to 0 and the CM17 to CM16 bits to 00b undivided After reset the main clock divided by 8 provides the CPU clock Note that when entering stop mode from high or medium speed mode on chip oscillator mode or on chip oscillator low power dissipation mode or when the CMO5 bit in the CMO register is set to 1 main clock turned off in low speed mode the CMO6 bit in the CMO register is set to 1 divide by 8 mode 7 2 2 Peripheral Function Clock f1 f2 f8 32 f1SIO f2SIO f8SIO f32SIO fAD fCANO fCAN1 1C32 These are operating clocks for the peripheral functions Two of these fi i 2 1 2 8 32 and fiSIO are derived from the main clock PLL clock or on chip oscillator clock by dividing them by i The clock fi is
224. UND instruction 9 2 2 Overflow Interrupt An overflow interrupt occurs when executing the INTO instruction with the O flag set to 1 the operation resulted in an overflow The following are instructions whose O flag changes by arithmetic ABS ADC ADCF ADD CMP DIV DIVU DIVX NEG RMPA SBB SHA SUB 9 2 3 BRK Interrupt A BRK interrupt occurs when executing the BRK instruction 9 2 4 INT Instruction Interrupt An INT instruction interrupt occurs when executing the INT instruction Software interrupt Nos 0 to 63 can be specified for the INT instruction Because software interrupt Nos 1 to 31 are assigned to peripheral function interrupts the same interrupt routine as for peripheral function interrupts can be executed by executing the INT instruction In software interrupt Nos O to 31 the U flag is saved to the stack during instruction execution and is set to 0 ISP selected before executing an interrupt sequence The U flag is restored from the stack when returning from the interrupt routine In software interrupt Nos 32 to 63 the U flag does not change state during instruction execution and the SP then selected is used Rev 1 10 Jul01 2005 page 61 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 9 Interrupt 9 3 Hardware Interrupts Hardware interrupts are classified into two types special interrupts and p
225. VO1 1 INVOO 1 and ICTB2 1h The timer B2 interruptis Default value of the timer TA4 m generated on the falling edge of the timer A reload control The TA4 register is changed whenever the timer B2 signal interrupt is generated Default value of the timer TA41 m TA4 m First time TA4 m Second time TA4 n The TA4 and TA41 registers are changed whenever the Third time TA4 n Fourth time TA p timer B2 interrupt is generated Fifth time TA4 p First time TA41 n TA4 n Default value of the IDBO and IDB1 registers Second time TA41 p TA4 p DUO 1 DUBO 0 DU1 0 DUB1 1 Default value of the IDBO and IDB1 registers They are changed to DUO 1 DUBO 0 DU1 1 DUB1 0 by DUO 1 DUBO 0 DU1 0 DUB1 1 the sixth timer B2 interrupt They are changed to DUO 1 DUBO 0 DU1 1 DUB1 0 by the third timer B2 interrupt Figure 13 9 Triangular Wave Modulation Operation Rev 1 10 Jul01 2005 page 126 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Three Phase Motor Control Timer Function Sawtooth Waveform as a Carrier Wave Sawtooth Wave _ Signal Wave gt i Timer B2 Timer A4 Start Trigger Signal Timer A4 One Shot Pulse 1 U Phase Output Signa U Phase Output Signal INV14 2 0 L active INV14 1 H active INV14 Bits in the INVC1 register NOTES 1 Internal signals See Figure 13 1
226. a timer A3 interrupt request is generated twice in succession Do not use the timer A3 interrupt when using this function T3OUT A phase TASIN B phase Count source ZP 1 E Input equal to or greater than one clock cycle of count source Timer A3 m XmiX 1X2 X 3 X 4 X5 NOTE 1 This timing diagram is for the case where the POL bit in the INT2IC register 1 rising edge Figure 12 10 Two phase Pulse A phase and B phase and Z Phase Rev 1 10 Jul01 2005 page 103 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 Timers 12 1 3 One shot Timer Mode In one shot timer mode the timer is activated only once by one trigger When the trigger occurs the timer starts up and continues operating for a given period Table 12 4 lists specifications in one shot timer mode Figure 12 11 shows the TAiMR register in the one shot timer mode Table 12 4 Specifications Count Source in One shot Timer Mode Specification f1 f2 f8 f32 fC32 Count Operation Down count When the counter reaches 0000h it stops counting after reloading a new value If a trigger occurs when counting the timer reloads a new count and restarts counting Divide Ratio 1 n n set value of the TAi register 0000h to FFFFh However the counter does not work if the divide by n value is set to 0000h
227. and SCLi pin signal The transfer clock works from a half period before the falling edge of the internal SCLi 1st bit to the rising edge of the 9th bit To use this function select an internal clock for the transfer clock The SWC bit in the UiSMR2 register allows to select whether the SCLi pin should be fixed to or freed from low level output at the falling edge of the 9th clock pulse If the SCLHI bit in the UISMR4 register is set to 1 enabled SCLi output is turned off placed in the high impedance state when a stop condition is detected Setting the SWC2 bit in the UISMR2 register 1 0 output makes it possible to forcibly output a low level signal from the SCLi pin even while sending or receiving data Setting the SWC2 bit to 0 transfer clock allows the transfer clock to be output from or supplied to the SCLi pin instead of outputting a low level signal If the SWC9 bit in the UISMR4 register is set to 1 SCL hold low enabled when the CKPH bit in the UiSMR3 register 1 the SCLi pin is fixed to low level output at the falling edge of the clock pulse next to the ninth Setting the SWC9 bit 0 SCL hold low disabled frees the SCLi pin from low level output 14 1 3 5 SDA Output The data written to bit 7 to bit O D7 to DO in the UiTB register is sequentially output beginning with D7 The ninth bit D8 is ACK or NACK The initial value of SDAi transmit output can only be set when IICM 1 IPC mode and the SMD2 to SMDO
228. ange M16C 6N Group M16C 6NK M16C 6NM 9 Interrupt Priority level of each interrupt intial value Highest Timer B2 Timer BO SI O6 2 Timer A3 INT6 2 Timer A1 _ UART1 Reception ACK1 UARTO Reception ACKO UART2 Reception ACK2 INT2 INTO o Timeras l Timer A2 INT7 2 Timer AO l UARTO Transmission NACKO l A D Conversion Key Input 1 DMA1 UART2 Bus Collision Detection CAN Successful Reception SI O4 INT5 Timer B4 UART1 Bus Collision Detection INT3 l CANO Successful Reception Priority of peripheral function interrupts if priority levels are same _UART2 Transmission NACK2 CANO 1 Error Key Input 1 DMAO CAN Successful Transmission SI O3 INT4 imer B3 UARTO Bus Collision Detection Timer B5 SI O5 2 CANO Successful Transmission CANO 1 Wake up Lowest ELE EEE EEE EEE EEE EE EEE EEE EEE Interrupt request level resolution output to clock generating circuit D Figure 7 1 Clock Generating Circuit Interrupt request accepted Address Match Oscillation Stop and Re oscillation Detection l Watchdog Timer DBC l NMI NOTES 1 If the PCLK6 bit in the PCLKR register is set to 1 the priority level of key input interrupt can be changed 2 The SI O5 SI O6 and INT6 to INT8 registers are only in the 128 pin versi
229. anged in the next instruction after setting the PRC2 bit to 1 Make sure no interrupts or DMA transfers will occur between the instruction in which the PRC2 bit is set to 1 and the next instruction The PRCO and PRC1 bits are not automatically set to 0 by writing to any address They can only be set to 0 in a program Protect Register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset Poloj LL PRCR 000Ah XX000000b Bit Symbol Enable write to CMO CM1 CM2 PLCO PCLKR CCLKR PRCO Protect Bit 0 registers RW 0 Write protected 1 Write enabled Enable write to PMO PM1 PM2 TB2SC INVCO INVC1 PRC1 Protect Bit 1 registers RW 0 Write protected 1 Write enabled 0 Write protected 1 Write enabled 1 b5 b3 Reserved Bit Set to 0 Nothing is assigned When write set to 0 b7 b6 When read their contents are indeterminate Enable write to PD7 PD9 S3C i 2 Protect Bit 2 S4C S5C S6C registers Su 1 The PRC2 bit is set to 0 by writing to any address after setting it to 1 Other bits are not set to 0 by writing to any address and must therefore be set in a program 2 The S5C and S6C registers are only in the 128 pin version Figure 8 1 PRCR Register Rev 1 10 Jul01 2005 page 59 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 9 Interrupt 9 Interrupt 9 1 Type
230. applied to the NMI pin 20 3 4 6 Rewriting in User ROM Area EWO Mode The supply voltage drops while rewriting the block where the rewrite control program is stored the flash memory cannot be rewritten because the rewrite control program is not correctly rewritten If this error occurs rewrite the user ROM area while in standard serial I O mode or parallel I O mode or CAN I O mode 20 3 4 7 Rewriting in User ROM Area EW1 Mode Avoid rewriting any block in which the rewrite control program is stored 20 3 4 8 DMA Transfer In EW1 mode do not perform a DMA transfer while the FMROO bit in the FMRO register is set to 0 auto programming or auto erasing Rev 1 10 Jul01 2005 page 248 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Flash Memory Version 20 3 4 9 Writing Command and Data Write commands and data to even addresses in the user ROM area 20 3 4 10 Wait Mode When entering wait mode set the FMRO1 bit in the FMRO register to 0 CPU rewrite mode disabled before executing the WAIT instruction 20 3 4 11 Stop Mode When entering stop mode the following settings are required Set the FMRO1 bit to 0 CPU rewrite mode disabled Disable DMA transfer before setting the CM10 bit to 1 stop mode Execute the instruction to set the CM10 bit to 1 stop mode and then the JMP B instruction Exa
231. are reset watchdog timer reset and oscillation stop detection reset are available to reset the microcomputer 5 1 Hardware Reset The microcomputer resets pins the CPU and SFR by setting the RESET pin If the supply voltage meets the recommended operating conditions the microcomputer resets all pins when an L signal is applied to the RESET pin see Table 5 1 Pin Status When RESET Pin Level is L The oscillation circuit is also reset and the main clock starts oscillation The microcomputer resets the CPU and SFR when the signal applied to the RESET pin changes low L to high H The microcomputer executes the program in an address indicated by the reset vector The internal RAM is not reset When an L signal is applied to the RESET pin while writing data to the internal RAM the internal RAM is in an indeterminate state Figure 5 1 shows an example of the reset circuit Figure 5 2 shows a reset sequence Table 5 1 lists pin states while the RESET pin is held low L Figure 5 3 shows CPU register states after reset Refer to 4 SFR for SFR states after reset 5 1 1 Reset on a Stable Supply Voltage 1 Apply L to the RESET pin 2 Apply 20 or more clock cycles to the XIN pin 3 Apply H to the RESET pin 5 1 2 Power on Reset 1 Apply L to the RESET pin 2 Raise the supply voltage to the recommended operating level 3 Insert td P R ms as wait time for the internal voltage to stabilize 4 Appl
232. at sweep mode 0 or Repeat sweep mode 1 T Software trigger 0 A D conversion disabled ADST A D Conversion Start Flag 1 A D conversion started Refer to NOTE 2 for ADCON2 CKSO Frequency Select Bit 0 Register 1 If the ADCONO register is rewritten during A D conversion the conversion result will be indeterminate A D Control Register 1 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset ADCON1 03D7h 00h Bisymba Function varies with each operation mode E A D Sweep Pin Select Bit A D Operation Mode 0 Any mode other than repeat sweep mode 1 pelea ers Repeat sweep mode 1 T 8 bit mode BITS 8 10 Bit Mode Select Bit 10 bit mode e Refer to NOTE 2 for ADCON2 CKS1 Frequency Select Bit 1 Register re VREF not connected VCUT VREF Connect Bit 2 VREF connected B External Op Amp Function varies Connection Mode Bit with each operation mode 1 If the ADCON register is rewritten during A D conversion the conversion result will be indeterminate 2 If the VCUT bit is reset from 0 VREF unconnected to 1 VREF connected wait for 1 us or more before starting A D conversion Figure 15 2 ADCONO Register and ADCON1 Register Rev 1 10 Jul01 2005 page 183 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 A D Converter A D Control Register 2 b7 b6 b5 b4 b3 b2 bi bO Symbol Address A
233. b8 0393h 0392h Indeterminate ae 0395h 0394h Indeterminate 01D1h 01DOh Indeterminate 01D3h 01D2h Indeterminate 01D5h 01D4h Indeterminate Function Setting Range RW 1e the count source by n 1 Event Counter Divide the count source by n 1 0000h to FFFFh Mode where n set value 2 Pulse Period Measures a pulse period or width Modulation Mode Pulse Width Modulation Mode NOTES 1 The register must be accessed in 16 bit unit 2 The timer counts pulses from an external device or overflows or underflows of other timers Figure 12 16 TBOMR to TB5MR Registers and TBO to TB5 Registers Rev 1 10 Jul01 2005 page 110 of 318 RENESAS REJ09B0124 0110 12 Timers Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 Timers Count Start Flag b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset 0380h 1 Starts counting Timer B3 B4 B5 Count Start Flag b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset TBSR 01C0h 000XXXXXb When read their contents are indeterminate TB3S Timer B3 Count Start Flag 0 Stops counting TB4S TimerB4 Count Start Flag 91879 counting TB5S Timer B5 Count Start Flag Nothing is assigned When write set to 0 m Clock Prescaler Reset Flag TOO Symbol Address After Reset CPSRF 0381h OXXXXXXXb Bit Symbol Bit Name Function Nothing is assigned When write set to 0 When read th
234. bit in the CICONR register i 0 1 P 0 to 15 fCANCLK CAN communication clock fCANCLK fCAN 2 P 1 Figure 18 14 Block Diagram of CAN Module System Clock Generating Circuit 18 7 Bit Timing Configuration The bit time consists of the following four segments Synchronization segment SS This serves for monitoring a falling edge for synchronization Propagation time segment PTS This segment absorbs physical delay on the CAN network which amounts to double the total sum of delay on the CAN bus the input comparator delay and the output driver delay Phase buffer segment 1 PBS1 This serves for compensating the phase error When the falling edge of the bit falls later than expected the segment can become longer by the maximum of the value defined in SJW Phase buffer segment 2 PBS2 This segment has the same function as the phase buffer segment 1 When the falling edge of the bit falls earlier than expected the segment can become shorter by the maximum of the value defined in SJW Figure 18 15 shows the bit timing Bit time lt gt PBS1 PBS2 SJW SJW Sampling point The range of each segment Bit time 8 to 25Tq Configuration of PBS1 and PBS2 PBS1 PBS2 SS 1Tq PBS1 gt SJW PTS 1Tq to 8Tq PBS2 gt 2 when SJW 1 PBS1 2Tq to 8Tq PBS2 gt SJW when 2 lt SJW x 4 PBS2 2Tq to 8Tq SJW 1Tq to 4Tq Figure 18 15 Bit Timing Rev 1 10 Jul01 2005 page 216 of 318 RENESAS REJ09B0124
235. bits in the UiMR register 000b serial I O disabled The DL2 to DLO bits in the UiSMR3 register allow to add no delays or a delay of 2 to 8 UiBRG count source clock cycles to SDAi output Setting the SDHI bit in the UiSMR2 register 1 SDA output disabled forcibly places the SDAi pin in the high impedance state Do not write to the SDHI bit synchronously with the rising edge of the UARTi transfer clock This is because the ABT bit may inadvertently be set to 1 detected 14 1 3 6 SDA Input When the IICM2 bit 0 the 1st to 8th bits D7 to DO of received data are stored in the bit 7 to bit O in the UiRB register The 9th bit D8 is ACK or NACK When the IICM2 bit 1 the 1st to 7th bits D7 to D1 of received data are stored in the bit 6 to bit O in the UiRB register and the 8th bit DO is stored in the bit 8 in the UiRB register Even when the IICM2 bit 1 providing the CKPH bit 1 the same data as when the IICM2 bit 0 can be read out by reading the UiRB register after the rising edge of the corresponding clock pulse of 9th bit Rev 1 10 Jul01 2005 page 161 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O 14 1 3 7 ACK and NACK If the STSPSEL bit in the UISMR4 register is set to 0 start and stop conditions not generated and the ACKC bit in the UiSMR4 register is set to 1 ACK data output
236. cation equipment which requires high speed arithmetic logic operations 1 1 Applications Car audio and industrial control systems other Rev 1 10 Jul01 2005 page 1 of 318 RENESAS REJO9B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 1 2 Performance Outline Tables 1 1 and 1 2 list a performance outline of M16C 6N Group M16C 6NK M16C 6NM 1 Overview Table 1 1 Performance Outline of M16C 6N Group 100 pin Version M16C 6NK Number of Basic Instructions 91 instructions Performance Normal ver T V ver Minimum Instruction Execution Time 41 7ns f BCLK 24MHz 1 1 prescaler without software wait 50 0ns f BCLK 20MHz 1 1 prescaler without software wait Operation Mode Single chip mode Address Space 1 Mbyte Memory Capacity See Table 1 3 Product List Peripheral Function Port Input Output 87 pins Input 1 pin Multifunction Timer Timer A 16 bits X 5 channels Timer B 16 bits X 6 channels Three phase motor control circuit Serial I O 3 channels Clock synchronous UART I C bus IEBus 2 channels Clock synchronous A D Converter 10 bit A D converter 1 circuit 26 channels D A Converter 8 bits X 2 channels DMAC 2 channels CRC Calculation Circuit CRC CCITT CAN Module 2 channels with 2 0B specification Watchdog
237. ced that much However fC32 remains on 7 4 2 2 Entering Wait Mode The microcomputer is placed into wait mode by executing the WAIT instruction When the CM11 bit 1 CPU clock source is the PLL clock be sure to set the CM11 bit in the CM1 register to 0 CPU clock source is the main clock before going to wait mode The power consumption of the chip can be reduced by setting the PLCO7 bit in the PLCO register to 0 PLL stops 7 4 2 3 Pin Status During Wait Mode Table 7 4 lists the pin status during wait mode Table 7 4 Pin Status During Wait Mode Single Chip Mode Retains status before wait mode When fC selected Does not stop When f8 f32 selected CMO2 bit 0 Does not stop CMO bit 1 Retains status before wait mode 7 4 2 4 Exiting Wait Mode The microcomputer is moved out of wait mode by a hardware reset NMI interrupt or peripheral function interrupt If the microcomputer is to be moved out of wait mode by a hardware reset or NMI interrupt set the peripheral function interrupt priority ILVL2 to ILVLO bits to 000b interrupt disabled before executing the WAIT instruction The peripheral function interrupts are affected by the CMO bit If the CMO2 bit is 0 peripheral function clocks not turned off during wait mode peripheral function interrupts can be used to exit wait mode If the CMO2 bit is 1 peripheral function clocks turned off during wait mode the peripheral functions using the pe
238. ceive Register S3456TRR Timer B3 Mode Register TB3MR Timer B4 Mode Register TB4MR Timer B5 Mode Register TB5MR Interrupt Cause Select Register 0 IFSRO Interrupt Cause Select Register 1 IFSR1 SI O3 Transmit Receive Register S3TRR SI O3 Control Register S3C SI O3 Bit Rate Generator S3BRG SI O4 Transmit Receive Register SATRR SI O4 Control Register S4C SI O4 Bit Rate Generator S4BRG SI O5 Transmit Receive Register S5TRR SI O5 Control Register S5C SI O5 Bit Rate Generator S5BRG UARTO Special Mode Register 4 UOSMR4 UARTO Special Mode Register 3 UOSMR3 UARTO Special Mode Register 2 UOSMR2 UARTO Special Mode Register UOSMR UART1 Special Mode Register 4 U1SMR4 UART1 Special Mode Register 3 U1SMR3 UART1 Special Mode Register 2 U1SMR2 UART1 Special Mode Register U1SMR UART2 Special Mode Register 4 U2SMR4 UART2 Special Mode Register 3 U2SMR3 UART2 Special Mode Register 2 U2SMR2 UART2 Special Mode Register U2SMR UART2 Transmit Receive Mode Register U2MR UART2 Bit Rate Generator U2BRG Flash Memory Control Register 1 2 Flash Memory Control Register 0 2 Address Match Interrupt Register 2 44 44 79 79 79 Address Match Interrupt Enable Register 2 AIER2 SARTA Transmit Over eater ai UART2 Transmit Receive Control Register 0 U2CO Address Match Interrupt Register 3 RMAD3 UART2 Transmit Receive Control Register 1 U2C1 UA
239. ception status RemActive Reception Status Flag 2 When set to reception remote frame slot 0 After a remote frame is received it will be answered automatically 1 After a remote frame is received no transmission will be started as long as this bit is set to 1 Not responding Auto Response RspLock Lock Mode Select Bit Remote Frame 0 Slot not corresponding to remote frame Corresponding 1 Slot corresponding to remote frame Slot Select Bit BecR Reception Slot 0 Not reception slot ecnieq Request Bit 3 1 Reception slot Transmission 0 Not transmission slot TrmRe Slot Request Bit 9 1 Transmission slot 1 As for write only writing 0 is possible The value of each bit is written when the CAN module enters the respective state 2 In Basic CAN mode slots 14 and 15 serve as data format identification flag The RemActive bit is set to 0 if the data frame is received and it is set to 1 if the remote frame is received 3 One slot cannot be defined as reception slot and transmission slot at the same time 4 This register can not be set in CAN reset initialization mode of the CAN module Figure 18 6 COMCTLj and C1MCTLj Registers Rev 1 10 Jul01 2005 page 207 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 18 CAN Module CANi Control Register i 0 1 b7 b b5 b4 b3 b2 bi bo Symbol Address Af
240. cessful Reception Interrupt i 0 1 CANi Successful Transmission Interrupt CANO 1 Error Interrupt Error Passive State Error BusOff State Bus Error this feature can be disabled separately CANO 1 Wake up Interrupt When the CPU detects the CANi successful reception transmission interrupt request the MBOX bit in the CiSTR register must be read to determine which slot has generated the interrupt request Rev 1 10 Jul01 2005 page 225 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 Programmable 1 O Ports 19 Programmable l O Ports The programmable input output ports hereafter referred to simply as l O ports consist of 87 lines PO to P10 in the 100 pin version and consist of 113 lines PO to P14 in the 128 pin version Each port can be set for input or output every line by using a direction register and can also be chosen to be or not be pulled high every 4 lines P8 5 is an input only port and does not have a pull up resistor Port P8 5 shares the pin with NMI so that the NMI input level can be read from the P8 5 bit in the P8 register Table 19 1 lists the number of pins of the I O ports of each package Figures 19 1 to 19 5 show the I O ports Figure19 6 shows the I O pins Each pin functions as an I O port or a peripheral function input output pin For details on how to set peripheral functions refer to each fun
241. ck And then the SOUTI pin is held high impedance If the level which is output from the SOUTi pin is a problem when changing the SMi3 bit from 0 to 1 set the default value of the SOUTI pin by the SMi7 bit NOTE 1 SI O5 and SI O6 are only in the 128 pin version Rev 1 10 Jul01 2005 page 299 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 12 A D Converter Set the ADCONO except bit 6 ADCON1 and ADCONe registers when A D conversion is stopped before a trigger occurs When the VCUT bit in the ADCON1 register is changed from 0 VREF not connected to 1 VREF connected start A D conversion after passing 1 us or longer To prevent noise induced device malfunction or latch up as well as to reduce conversion errors insert capacitors between the AVCC VREF and analog input pins ANI i 0 to 7 ANO i and AN2 i each and the AVSS pin Similarly insert a capacitor between the VCC pin and the VSS pin Figure 22 4 shows an example connection of each pin Make sure the port direction bits for those pins that are used as analog inputs are set to 0 input mode Also if the TGR bit in the ADCONO register 1 external trigger make sure the port direction bit for the ADTRG pin is set to 0 input mode When using key input interrupt do not use any of the four ANA to
242. clock U2LCH bit in U2C1 register 0 no reverse n value set to U2BRG U2IRS bit in U2C1 register 1 transmit is completed NOTE 1 Because TXD2 and RXD2 are connected a composite waveform consisting of the TXD2 output and the parity error signal sent back from receiving end is generated 2 Reception Transfer clock RE bit in U2C1 register Transmit waveform Start Pasty ig from transmitting end bit bit bit s1 EOS sP STAO KOKOKOKOKO AOA TXD2 An L level is output from TXD2 due A the occurrence of a parity error cd 999899999 MANERAS U2CO ids id IR bit in S2RIC register Read the U2RB register Read the U2RB register bs a The above timing diagram applies to the case where data is Set to 0 by an interrupt request acknowledgement or a program received in the direct format STPS bit in U2MR register 0 1 stop bit TC 16 n 1 fi or 16 n 1 fEXT PRY bit in U2MR register 1 even parity fi frequency of U2BRG count source f1SIO f2SIO f8SIO f32SIO UFORM bit in U2CO register 0 LSB first fEXT frequency of U2BRG count source external clock U2LCH bit in U2C1 register O no reverse n value set to U2BRG U2IRS bit in U2C1 register 1 transmit is completed NOTE 1 Because TXD2 and RXD2 are connected a composite waveform consisting of transmit waveform from the transmitting end and parity error signal from receiving end is generated Figure 14 32 Transmit a
243. clock divided by 1 provides the CPU clock If the sub clock is activated fC32 can be used as the count source for timers A and B 7 4 1 2 PLL Operation Mode The main clock multiplied by 2 4 or 6 provides the PLL clock and this PLL clock serves as the CPU clock If the sub clock is activated fC32 can be used as the count source for timers A and B PLL operation mode can be entered from high speed mode If PLL operation mode is to be changed to wait or stop mode first go to high speed mode before changing 7 4 1 3 Medium speed Mode The main clock divided by 2 4 8 or 16 provides the CPU clock If the sub clock is activated C32 can be used as the count source for timers A and B 7 4 1 4 Low speed Mode The sub clock provides the CPU clock The main clock is used as the clock source for the peripheral function clock when the CM21 bit in the CM2 register is set to 0 on chip oscillator turned off and the on chip oscillator clock is used when the CM21 bit is set to 1 on chip oscillator oscillating The fC32 clock can be used as the count source for timers A and B 7 4 1 5 Low Power Dissipation Mode In this mode the main clock is turned off after being placed in low speed mode The sub clock provides the CPU clock The fC32 clock can be used as the count source for timers A and B Simultaneously when this mode is selected the CMO6 bit in the CMO register becomes 1 divide by 8 mode In the low power dissipation mode do not c
244. converted to a digital code A D Conversion Start Condition When the TRG bit in the ADCONO register is 0 software trigger The ADST bit in the ADCONO register is set to 1 A D conversion starts When the TRG bit is 1 ADTRG trigger Input on the ADTRG pin changes state from high to low after the ADST bit is set to 1 A D conversion starts A D Conversion Stop Condition Set the ADST bit to 0 A D conversion halted Interrupt Request Generation Timing None generated Analog Input Pin Select from ANO to AN1 2 pins ANO to AN3 4 pins ANO to AN5 6 pins ANO to AN7 8 pins Reading of Result of A D Converter NOTE Read one of the ADO to AD7 registers that corresponds to the selected pin 1 ANO 0 to ANO 7 and AN2 0 to AN2 7 can be used in the same way as ANO to AN7 Rev 1 10 Jul01 2005 page 191 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 A D Converter A D Control Register 0 b7 b6 b5 b4 b3 b2 bi bO PTT EET TE aeoo fomen aooo Analog Input Pin Select Bit Invalid in repeat sweep mode 0 EA m m ME TAN MD1 Select Bit 0 repeats sweep mode 1 me remsen E aw 1 If the ADCONO register is rewritten during A D conversion the conversion result will be indeterminate A D Control Register 1 uer e ET Symbol Address After re
245. ction determines whether the ID codes sent from the CAN programmer matches those written in the flash memory Refer to 20 2 Functions to Prevent Flash Memory from Rewriting Table 20 8 Pin Functions for CAN I O Mode VCC1 VCC2 VSS Power supply input Description Apply the voltage guaranteed for Program and Erase to VCC1 pin and VCC2 to VCC2 pin The VCC apply condition is that VCC2 VCC1 Apply 0 V to VSS pin CNVSS CNVSS Connect to VCC1 pin HESET Reset input Reset input pin While RESET pin is L level input 20 cycles or longer clock to XIN pin XIN Clock input XOUT Clock output Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins To input an externally generated clock input it to XIN pin and open XOUT pin BYTE BYTE Connect this pin to VCC1 or VSS AVCC AVSS Analog power supply input Connect AVCC to VCC1 and AVSS to VSS respectively VREF Reference voltage input Enter the reference voltage for A D and D A converters from this pin PO Oto PO 7 Input port PO Input H or L level signal or open P1 0to P1 7 Input port P1 Input H or L level signal or open P2 Oto P2 7 Input port P2 Input H or L level signal or open P8 Oto P3 7 Input port P3 Input H or L level signal or open P4 0 to P4 7 Input port P4 Input H or L level signal or open P5 0
246. ctional description in this manual If any pin is used as a peripheral function input SI O4 output or D A converter output pin set the direction bit for that pin to 0 input mode Any pin used as an output pin for peripheral functions other than the SI O4 and D A converter is directed for output no matter how the corresponding direction bit is set Table 19 1 Number of Pins of I O Ports of Each Package Pe 128 pin Version 100 pin Version I O Ports PO 0to PO 7 P1 OtoP1 7 P2 0to P2 7 P3 0 to P3 7 P4 0to PA 7 P5 0 to P5 7 P6_0 to P6 7 P7 0to P7 7 PO Oto PO 7 P1 OtoP1 7 P2 0to P2 7 P3 0to P3 7 P4 Oto P4 7 P5 0to P5 7 P6_0 to P6 7 P7 0to P7 7 P8 0 to P8 4 P8 6 P8 7 P8 5 is an input port P9 0 to P9 7 P10 Oto P10 7 P11 Oto P11 7 P12 Oto P12 7 P13 Oto P13 7 P14 O0 P14 1 113 pins 87 pins P8 0 to P8 4 P8 6 P8 7 P8 5 is an input port P9 0 to P9 7 P10 Oto P10 7 Rev 1 10 Jul 01 2005 page 226 of 318 REJO9B0124 0110 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 Programmable 1 O Ports 19 1 PDi Register 100 pin Version i 0 to 10 128 pin Version i 0 to 13 Figure19 7 shows the PDi register This register selects whether the I O port is to be used for input or output The bits in this register correspond one for one to each port No direction register bit for P8_5 is available 19
247. cuting an instruction an interrupt request controlled by the register being modified is generated the IR bit of the register may not be set to 1 interrupt requested with the result that the interrupt request is ignored If such a situation presents a problem use the instructions shown below to modify the register Usable instructions AND OR BCLR BSET Changing IR bit Depending on the instruction used the IR bit may not always be set to 0 interrupt not requested Therefore be sure to use the MOV instruction to set the IR bit to 0 c When using the flag to disable an interrupt refer to the sample program fragments shown below as you set the flag Refer to b for details about rewrite the interrupt control registers in the sample program fragments Examples 1 through 3 show how to prevent the flag from being set to 1 interrupt enabled before the interrupt control register is rewritten owing to the effects of the internal bus and the instruction queue buffer Example 1 Using the NOP instruction to keep the program waiting until the interrupt control register is modified INT SWITCH1 FCLR Disable interrupt AND B 00h 0055h Set the TAOIC register to 00h NOP NOP FSET Enable interrupt The number of the NOP instruction is as follows The PM20 bit in the PM2 register 1 1 wait 2 The PM20 bit 0 2 waits 3 When using HOLD function 4 Example 2 Using the dummy read to
248. cycle of the CPU clock the IR bit in the TAiIC register is set to 1 interrupt request Output in one shot timer mode synchronizes with a count source internally generated When an external trigger has been selected one cycle delay of a count source as maximum occurs between a trigger input to TAiIN pin and output in one shot timer mode The IR bit is set to 1 when timer operation mode is set with any of the following procedures Select one shot timer mode after reset Change an operation mode from timer mode to one shot timer mode Change an operation mode from event counter mode to one shot timer mode To use the Timer Ai interrupt the IR bit set the IR bit to 0 after the changes listed above have been made When a trigger occurs while counting a counter reloads the reload register to continue counting after generating a re trigger and counting down once To generate a trigger while counting generate a second trigger between occurring the previous trigger and operating longer than one cycle of a timer count Source When the external trigger is selected as count start condition do not input again the external trigger between 300 ns before the counter reachs 0000h If a low level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register 1 three phase output forcible cutoff by input on NMI pin enabled the TA1OUT TA2OUT and TA4OUT pins go to a high impedance state Rev 1 10 Jul01 200
249. d from CPU Accordingly be careful about the following points so that the access period from the CPU should not match the updating period of the CAN module a There should be a wait time of 3fCAN or longer see Table 22 3 CAN Module Status Updating Period before the CPU reads the CiSTR register See Figure 22 6 With a Wait Time of 3BTCAN Before CPU Read b When the CPU polls the CiSTR register the polling period must be 3fCAN or longer See Figure 22 7 When Polling Period of CPU is 3fCAN or Longer Table 22 3 CAN Module Status Updating Period 3fCAN Period 3 x XIN Original Oscillation Period x Division Value of CAN Clock CCLK Example 1 Condition XIN 16 MHz CCLK Divided by 1 3fCAN period 3 x 62 5 ns x 1 187 5 ns Example 2 Condition XIN 16 MHz CCLK Divided by 2 3fCAN period 3 x 62 5 ns x 2 375 ns Example 3 Condition XIN 16 MHz CCLK Divided by 4 3fCAN period 3 x 62 5 ns x 4 750 ns Example 4 Condition XIN 16 MHz CCLK Divided by 8 3fCAN period 3 x 62 5 ns x 8 1 5 us Example 5 Condition XIN 16 MHz CCLK Divided by 16 3fCAN period 3 x 62 5 ns x 16 2 3 us Rev 1 10 Jul01 2005 page 302 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution fCAN CPU read signal Updating period of CAN module CPU reset signal CiSTR re
250. d mode or normal operation mode If the operation mode is controlled by the microcomputer CAN transceiver must be set the operation mode to high speed mode or normal operation mode before programming the flash memory by changing the switch etc Tables 22 6 and 22 7 show pin connections of CAN transceiver Table 22 6 Pin Connections of CAN Transceiver In case of PCA82C250 Philips product Standby Mode Rs Pin High speed Mode L CAN Communication impossible possible Connection M16C 6NK M16C 6NM PCA82C250 Switch OFF i 0 1 NOTES M16C 6NK M16C 6NM PCA82C250 Port 2 Switch ON 1 The pin which controls the operation mode of CAN transceiver 2 Connect to enabled port to control CAN transceiver Table 22 7 Pin Connections of CAN Transceiver In case of PCA82C252 Philips product Sleep Mode STB Pin Normal Operation Mode H EN Pin H CAN Communication impossible possible Connection M16C 6NK M16C 6NM PCA82C252 Switch OFF i 0 1 NOTES MT6C 6NK M16C 6NM POAB2C250 Switch ON 1 The pin which controls the operation mode of CAN transceiver 2 Connect to enabled port to control CAN transceiver Rev 1 10 Jul01 2005 page 306 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution
251. d register TCR1 ii DMA1 forward address pointer 1 5 DMA1 transfer counter TCR1 gt DMA latch high order bits DMA latch low order bits Data bus low order bits Data bus high order bits NOTE 1 Pointer is incremented by a DMA request Figure 11 1 DMAC Block Diagram A DMA request is generated by a write to the DSR bit in the DMIiSL register i O 1 as well as by an interrupt request which is generated by any function specified by the DMS and DSEL3 to DSELO bits in the DMiSL register However unlike in the case of interrupt requests DMA requests are not affected by the flag and the interrupt control register so that even when interrupt requests are disabled and no interrupt request can be accepted DMA requests are always accepted Furthermore because the DMAC does not affect interrupts the IR bit in the interrupt control register does not change state due to a DMA transfer A data transfer is initiated each time a DMA request is generated when the DMAE bit in the DMiCON register 1 DMA enabled However if the cycle in which a DMA request is generated is faster than the DMA transfer cycle the number of transfer requests generated and the number of times data is transferred may not match For details refer to 11 4 DMA Request Rev 1 10 Jul01 2005 page 82 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM
252. d restart conditions set the STSPSEL bit in the UiSMR4 register to 0 start and stop conditions not output and wait for more than half cycle of the transfer clock before setting each condition generate bit STAREQ RSTAREQ and STPREQ bits from 0 clear to 1 start 22 11 2 2 Special Mode 2 If a low level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register 1 three phase output forcible cutoff by input on NMI pin enabled the RTS2 and CLK pins go to a high impedance state 22 11 2 3 Special Mode 4 SIM Mode A transmit interrupt request is generated by setting the U2IRS bit in the U2C1 register to 1 transmission complete and U2ERE bit in the U2C1 register to 1 error signal output after reset Therefore when using SIM mode be sure to set the IR bit to 0 no interrupt request after setting these bits Rev 1 10 Jul01 2005 page 298 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 11 3 SI Oi i 3 to 6 The SOUTI default value which is set to the SOUTi pin by the SMi7 in the SiC register bit approximately 10ns may be output when changing the SMIi3 bit in the SiC register from 0 I O port to 1 SOUTIi output and CLKi function while the SMi2 bit in the SiC register to 0 SOUTi output and the SMi6 bit is set to 1 internal clo
253. de Figure 12 19 shows TBiMR register in event counter mode Table 12 7 Specifications in Event Counter Mode Specification Count Source e External signals input to TBiIN pin effective edge can be selected in program Timer Bj overflow or underflow Count Operation Down count When the timer underflows it reloads the reload register contents and continues counting Divide Ratio 1 n 1 n set value of the TBi register 0000h to FFFFh Count Start Condition Set TBiS bit to 1 start counting Count Stop Condition Set TBiS bit to 0 stop counting Interrupt Request Generation Timing Timer underflow TBilN Pin Function Count source input Read from Timer Count value can be read by reading the TBi register Write to Timer When not counting and until the 1st count source is input after counting start Value written to the TBi register is written to both reload register and counter When counting after 1st count source input Value written to the TBi register is written to only reload register Transferred to counter when reloaded next i 0to5 j i 1 exceptj 2ifi 0 j 5ifi 3 NOTE 1 The TBOS to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register and the TB3S to TB5S bits are assigned to the bit 5 to bit 7 in the TBSR register Timer Bi Mode Register i 0 to 5 Bi PG JUS ibe abe b ODIO Symbol Address After Reset 1 TBOMR to TB2MR 039Bh to 039Dh 00XX0000b TB3MR to TB53MR 01DBh to 01
254. de O Main clock PLL clock or on chip oscillator clock 1 Sub clock WAIT Mode Peripheral Function Clock Stop Bit XCIN XCOUT DON System Clock Select Bit 6 11 Write to this register after setting the PRCO bit in the PRCR register to 1 write enable The fC32 clock does not stop During low speed or low power dissipation mode do not set this bit to 1 peripheral clock turned off when in wait mode The CMO3 bit is set to 1 high while the CM04 bit is set to 0 I O port or when entered to stop mode To use a sub clock set this bit to 1 Also make sure ports P8 6 and P8 7 are directed for input with no pull ups This bit is provided to stop the main clock when the low power dissipation mode or on chip oscillator low power dissipation mode is selected This bit cannot be used for detection as to whether the main clock stopped or not To stop the main clock set bits in the following order 1 Set the CMO7 bit to 1 sub clock select or the CM21 bit in the CM2 register to 1 on chip oscillator select with the sub clock stably oscillating 2 Set the CM20 bit in the CM2 register to O oscillation stop re oscillation detection function disabled 3 Set the CMOS5 bit to 1 stop To use the main clock as the clock source for the CPU clock set bits in the following order 1 Set the CMO5 bit to 0 oscillate 2 Wait until the main clock oscillation stabilizes 3 Set the CM11 CM21
255. die ended eee 220 18 12 Return from Bus off Function ooooncccconcccinocccnnncnnonancnnnnann nono coran co narran rre 221 18 13 Time Stamp Counter and Time Stamp Function sionistaren iramana Eaa 221 18 14 Listen Only Mode oconccconnccconococononocononocononocononaca canon rra 221 18 15 Reception and MransMmissi N imc ida 222 18 151 ree tablilla 223 18 15 22 Transmis SON sinsa aaa E EEE EA ER AEE E E REREN ados 224 18 16 CAN Intert pt coc il de aaae aa EESE 225 19 Pr grammable VO PONS ecse enee K EEEO EEEE AEREE dante AE 226 A NO 227 19 2 Pl Register PO 14 ReGISter scout ii pre 227 19 3 PUR Regist ct tos 227 19 4 POR Register adosada ibid 227 20 Flash Memory Version miii cade inmii n 238 20 1 Memory Map zu i tei eere neces neat A A racc bern bu ahead outs 239 20 TL IBOOEMOGO oia iaa nio ideado daa 240 20 2 Functions to Prevent Flash Memory from Rewriting oooooccconnccccnnocccnnocanonacanonananonanc cono nnn nano ncnann nn nannccnnns 240 20 2 1 ROM Code Protect F nction eicere tr rire ret ces iupra utu nghe iae eina rd 240 20 2 2 4D Code Check FUNGUO eee eee toe niae te aede the detener tun bua cured ein a Reda deett 240 20 9 GPU Hewtite MOGG co tree rri eit ab eet eto sin ot teli a 242 20 31 EWO MODO p E 243 20 3 2 EW IU Mode EE 243 20 3 3 FMRO EME T REQISTETS sinan asao aia e aa eie beret ecce R a EE E adiu 244 20 3 4 Precautions on CPU Rewrite Mode sisssssigi conania tana
256. divide by 8 divide by 16 CPU clock Y PLCO7 1 CPU clock CPU clock CPU clock CPU clock CPU clock CPU clock PLL pun 21 XIN f XINy 2 f XIN 4 f XIN 8 f XIN 16 Ring CM07 0 CM07 0 CM07 0 CM07 0 CM07 0 CM07 0 f Ring 2 CM06 0 CM06 0 CM06 0 CM06 0 CM06 1 CM06 0 f Ring 4 CM17 0 PLCO7 0 CM17 0 CM17 0 CM17 1 CM17 1 Ring 8 CMi6 0_ CM11 0 CM16 0 CM16 1 CM16 0 CM16 1 f Ring 16 High Speed mode PLL operation mode On chip Oscillator On chip Oscillator CMO7 1 3 CM07 0 2 4 Mode Low Power Dissipation Mdde Low Speed Mode Low Speed Mode CPU clock f XCIN CPU clock f XCIN CM07 0 CMo7 0 CMO5 1 1 9 Low Power Dissipation Mode CPU clock f XCIN CM07 0 CM06 1 CM15 1 Sub clock oscillation CM04 CMO05 CMO06 CMO7 Bits in CMO register CM11 CM15 CM16 CM17 Bits in CM1 register CM20 CM21 Bits in CM2 register PLCO7 Bit in PLCO register NOTES 1 Avoid making a transition when the CM20 bit is set to 1 oscillation stop re oscillation detection function enabled Set the CM20 bit to O oscillation stop re oscillation detection function disabled before transiting Wait for the main clock oscillation stabilization time Switch clock after oscillation of sub clock is sufficiently stable Change the CM17 and CM16 bits before changing the CMO6 bit Transit in accordance with arro
257. e When entering wait mode by executing the WAIT instruction after writing to addresses O3FDh to OSFFh or internal RAM area execute the JMP B instruction between writing to corresponding area and the executing the WAIT instruction If DMA transfer may occur between executing the JMP B instruction and the WAIT instruction set the DMAE bit DMA enable bit in the DMiCOM register i 0 1 to 0 disabled before ececuting the WAIT instruction Example program MOV B 55H 0601H Write to internal RAM area JMP B L1 L1 FSET Enable interrupt WAIT Enter to wait mode When using the interrupt to exit stop mode the fifth instruction from the instruction to enter the stop mode may be executed before executing a program of the interrupt to exit stop mode If this execution causes no problem with the system there are no need for measures to be taken If such a situation presents a problem execute the JMP B instruction subsequent to the instruction which sets the CM10 bit to 1 stop mode Example program BSET 0 CM1 Stop mode JMP B L1 L1 Program after exiting stop mode NOTES 1 Insert more than four NOP instructions after the instruction shifting to wait mode or stop mode 2 In the flash memory version be sure to execute the measures For details refer to 22 18 2 Stop Mode Wait for main clock oscillation stabilization time before switching the clock source for CPU clock to the main clock Similarly wait until t
258. e in order to place the CAN module from CAN operation mode into CAN reset initializa tion mode always be sure to check that the State Reset bit in the CiSTR register is set to 1 reset mode Similarly if the Reset bit is changed from 1 to 0 in order to place the CAN module from CAN reset initialization mode into CAN operation mode always be sure to check that the State Reset bit is set to 0 operation mode The procedure is described below To place CAN Module from CAN Operation Mode into CAN Reset Initialization Mode Change the Reset bit from 0 to 1 e Check that the State Reset bit is set to 1 To place CAN Module from CAN Reset Initialization Mode into CAN Operation Mode Change the Reset bit from 1 to 0 Check that the State Reset bit is set to 0 Rev 1 10 Jul01 2005 page 304 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 13 3 Suggestions to Reduce Power Consumption When not performing CAN communication the operation mode of CAN transceiver should be set to standby mode or sleep mode When performing CAN communication the power consumption in CAN transceiver in not performing CAN communication can be substantially reduced by controlling the operation mode pins of CAN transceiver Tables 22 4 and 22 5 show recommended pin connec
259. e 261 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Flash Memory Version M16C 6N Group M16C 6NM Flash memory version E spa Edad ao oa doia zo Lalola Isso E SIE CE Akak s PR 80 8 68510 1A PS ES ET L8 ET EG UT bd E Connect oscillator circuit E Figure 20 14 Pin Connections for Standard Serial I O Mode 2 Rev 1 10 Jul 01 2005 page 262 of 318 REJO9B0124 0110 131 NESAS Mode setup method VCC1 VSS VSS to VCC1 VCC2 Package PLQP0128KB A Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Flash Memory Version 20 4 2 Example of Circuit Application in Standard Serial I O Mode Figures 20 15 and 20 16 show example of circuit application in standard serial I O mode 1 and mode 2 respectively Refer to the user s manual of your serial programmer to handle pins controlled by a serial programmer Note that when using the standard serial l O mode 2 make sure a main clock input oscillation frequency is set to 5 MHz 10 MHz or 16 MHz Microcomputer SCLK input P6_6 CLK1 TXD output P6_7 TXD1 BUSY output P6_4 RTS1 RXD input P6_6 RXD1 Reset input User reset signal NOTES 1 Control pins and external circuitry will vary according to p
260. e A TCKO oo Timer Low order Bits of Data Bus 10 Pulse period measurement mode TMOD1 to TMODO pulse width measurement mode L d High order ow oraer E 8 bits 8 bits 4 Reload Register 01 Event counter Counter Counter Reset Circuit TCK1 to TCKO TMOD1 to TMODO Bits in TBiMR register TBi Addresses TBj TBiS Bit in TABSR register or TBSR register Timer BO 0391h 0390h Timer B2 Timer B1 0393h 0392h Timer BO i20to5 Timer B2 0395h 0394h Timer B1 j i 1 exceptj 2wheni 0 j 5wheni 3 Timer B3 01D1h 01D0h Timer B5 Timer B4 01D3h 01D2h Timer B3 NOTE Timer B5 01D5h 01D4h Timer B4 1 Overflow or underflow Figure 12 15 Timer B Block Diagram Rev 1 10 Jul01 2005 page 109 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Timer Bi Mode Register i O to 5 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset TBOMR to TB2MR 039Bh to 039Dh 00XX0000b TB3MR to TB53MR 01DBh to 01DDh 00XX0000b EE RW 1 TMODO Timer mode Event counter mode Operation Mode Select Bit Pulse period measurement mode TMOD1 pulse width measurement mode Do not set a value MRO MR1 TCKO Count Source Select Bit Function varies with each operation TCK1 mode 1 Timer BO timer B3 2 Timer B1 timer B2 timer B4 timer B5 Timer Bi Register i 0 to 5 1 Address After Reset 0391h 0390h Indeterminate
261. e The UiIRS bit 1 transfer completed when the serial I O finished sending data from the UARTI transmit register For reception When transferring data from the UARTi receive register to the UiRB register at completion of reception Error Detection e Overrun error This error occurs if the serial I O started receiving the next data before reading the UiRB register and received the bit one before the last stop bit of the next data Framing error This error occurs when the number of stop bits set is not detected Parity error This error occurs when if parity is enabled the number of 1 s in parity and character bits does not match the number of 1 s set Error sum flag This flag is set to 1 when any of the overrun framing or parity errors occur Select Function i Oto2 NOTES LSB first MSB first selection Whether to start sending receiving data beginning with bit O or beginning with bit 7 can be selected Serial data logic switch This function reverses the logic of the transmit receive data The start and stop bits are not reversed TXD RXD I O polarity switch This function reverses the polarities of the TXD pin output and RXD pin input The logic levels of all I O data is reversed Separate CTS RTS pins UARTO CTSO and RTSO are input output from separate pins 1 The UOIRS and U1IRS bits are bits 0 and 1 in the UCON register The U2IRS bit is bit 4 in the U2C1 register 2 If an overrun
262. e UiBRG register CRS Invalid because the CRD bit 1 TXEPT Transmit register empty flag CRD Set to 1 NCH Select TXDi pin output mode CKPOL Set to 0 UFORM Set to 0 TE Set this bit to 1 to enable transmission TI Transmit buffer empty flag RE Set this bit to 1 to enable reception RI Reception complete flag U2IRS Y Select the source of UART2 transmit interrupt U2RRM UiLCH UiERE Set to 0 0 to 3 7 Set to 0 ABSCS Select the sampling timing at which to detect a bus collision ACSE Set this bit to 1 to use the auto clear function of transmit enable bit SSS Select the transmit start condition 0 to 7 Set to 0 0 to 7 Set to 0 0 to 7 Set to 0 IFSRO6 IFSRO7 Set to 1 i 0to2 NOTES UOIRS U1IRS Select the source of UARTO UART1 transmit interrupt UORRM U1RRM Set to 0 CLKMDO Invalid because the CLKMD1 bit 0 CLKMD1 RCSP 7 Set to 0 1 Not all register bits are described above Set those bits to 0 when writing to the registers in IE mode 2 Set the bit 4 and bit 5 in the UOC1 and U1C1 registers to 0 The UOIRS U1IRS UORRM and U1RRM bits are in the UCON register Rev 1 10 Jul01 2005 page 168 of 318 REJ09B0124 0110 7tENESAS Under development This document is under de
263. e if the CKPOL bit in the UiCO register O transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock the external clock is in the high state if the CKPOL bit in the UiCO register 1 transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock the external clock is in the low state 2 The UOIRS and U1IRS bits respectively are bits O and 1 in the UCON register the U2IRS bit is bit 4 in the U2C1 register 3 If an overrun error occurs the value of UiRB register will be indeterminate The IR bit in the SiRIC register does not change Rev 1 10 Jul01 2005 page 138 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Table 14 2 Registers to Be Used and Settings in Clock Synchronous Serial I O Mode Register 0 to 7 Function Set transmission data 0 to 7 Reception data can be read OER Overrun error flag 0 to 7 Set a transfer rate SMD2 to SMDO Set to 001b CKDIR Select the internal clock or external clock IOPOL Set to 0 CLK1 to CLKO Select the count source for the UiBRG register CRS Select CTS or RTS to use TXEPT Transmit register empty flag CRD Enable or disable the CTS or RTS function NCH Select TXDi pin output mode CKPOL
264. e or wait mode CM04 CMO05 CM06 CMO7 Bits in CMO register CM10 CM11 CM16 CM17 Bits in CM1 register CM20 CM21 PLCO7 Bits in CM2 register Bit in PLCO register Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Clock Generating Circuit 7 5 Oscillation Stop and Re oscillation Detection Function The oscillation stop and re oscillation detection function is such that main clock oscillation circuit stop and re oscillation are detected At oscillation stop re oscillation detection reset or oscillation stop re oscillation detection interrupt request are generated Which one is to be generated can be selected using the CM27 bit in the CM2 register The oscillation stop and re oscillation detection function can be enabled or disabled using the CM20 bit in the CM2 register Table 7 8 lists a specification overview of the oscillation stop and re oscillation detection function Table 7 8 Specification Overview of Oscillation Stop and Re oscillation Detection Function Oscillation Stop Detectable Clock and f XIN 2 2 MHz Frequency Bandwidth Enabling Condition for Oscillation Stop Set CM20 bit to 1 enable and Re oscillation Detection Function Operation at Oscillation Stop Reset occurs when CM27 bit 0 Re oscillation Detection Oscillation stop re oscillation detection interrupt occurs when the CM27 bit 1 7 5 1 Operation When
265. e programmable I O port or the peripheral function is currently selected When changing the PD14 i bit i 0 1 in the PC14 register from 0 input port to 1 output port follow the procedures below Setting Procedure 1 Set P14 i bit MOV B 00000001b PC14 P14 ibit setting 2 Change PD14 i bit to 1 by MOV instruction MOV B 00110001b PC14 Change to output port Rev 1 10 Jul01 2005 page 307 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 15 Dedicated Input Pin When dedicated input pin voltage is larger than VCC pin voltage latch up occurs When different power supplied to the system and input voltage of unused dedicated input pin is larger than voltage of VCC pin connect dedicated input pin to VCC via resistor approximately 1kQ Figure 22 8 shows the circuit connection This note is also applicable when VINPUT exceeds VCC during power up The resistor is not necessary when VCC pin voltage is same or larger than dedicated input pin voltage T i Different power supply N Dedicated input pin e g NMI M16C 6NK M16C 6NM Figure 22 8 Circuit Connection Rev 1 10 Jul01 2005 page 308 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Preca
266. e rewritten according to the System implemented 20 2 Functions to Prevent Flash Memory from Rewriting The flash memory has a built in ROM code protect function for parallel l O mode and a built in ID code check function for standard serial I O mode and CAN I O mode to prevent the flash memory from reading or rewriting 20 2 1 ROM Code Protect Function The ROM code protect function inhibits the flash memory from being read or rewritten during parallel I O mode Figure 20 2 shows the ROMCP register The ROMCP register is located in the user ROM area The ROM code protect function is enabled when the ROMCR bits are set to other than 11b In this case set the bit 5 to bit O to 111111b When exiting ROM code protect erase the block including the ROMCP register by the CPU rewrite mode or the standard serial l O mode or CAN l O mode 20 2 2 ID Code Check Function Use the ID code check function in standard serial l O mode and CAN I O mode The ID code sent from the serial programmer is compared with the ID code written in the flash memory for a match If the ID codes do not match commands sent from the serial programmer are not accepted However if the four bytes of the reset vector are FFFFFFFFP ID codes are not compared allowing all commands to be accepted The ID codes are 7 byte data stored consecutively starting with the first byte into addresses OFFFDFh OFFFESh OFFFEBh OFFFEFh OFFFF3h OFFFF7h and OFFFFBh The flash mem
267. e shot pulse of Dead Time Timer the timer A1 A2 A4 9 Trigger Select Bit 1 Rising edge of the three phase output shift register U V W phase Reserved Bit Set to 0 1 Rewrite the INVC1 register after the PRC1 bit in the PRCR register is set to 1 write enable The timers A1 A2 A4 and B2 must be stopped during rewrite 2 The following table lists how the INV11 bit works INV11 0 Three phase mode 0 Three phase mode 1 TA11 TA21 and TA41 Registers Not used Used Disabled The ICTB2 counter is INVOO and INVO1 Bit incremented whenever the timer B2 Enabled underflows INV13 Bit Disabled Enabled when INV11 1 and INVO6 0 When the INVO6 bit is set to 1 Sawtooth wave modulation mode set the INV11 bit to 0 three phase mode 0 Also when the INV11 bit is set to 0 set the PWCON bit in the TB2SC register to 0 timer B2 is reloaded when the timer B2 underflows The INV13 bit is enabled only when the INVO6 bit is set to 0 Triangular wave modulation mode and the INV11 bit to 1 three phase mode 1 If the following conditions are all met set the INV16 bit to 1 rising edge of the three phase output shift register The INV15 bit is set to 0 dead time timer enabled e The Dij bit iU V or W j 0 1 and DiBj bit always have different values when the INVO3 bit is set to 1 The positive phase and negative phase always output opposite level signals If above conditions are not met set the INV16
268. e subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Flash Memory Version 20 3 5 4 Program Command 40h The program command writes 2 byte data to the flash memory By writing xx40h in the first bus cycle and data to the write address in the second bus cycle an auto program operation data program and verify will start The address value specified in the first bus cycle must be the same even address as the write address specified in the second bus cycle The FMROO bit in the FMRO register indicates whether an auto program operation has been completed The FMROO bit is set to 0 busy during auto program and to 1 ready when an auto program operation is completed After the completion of an auto program operation the FMRO6 bit in the FMRO register indicates whether or not the auto program operation has been completed as expected Refer to 20 3 8 Full Status Check An address that is already written cannot be altered or rewritten Figure 20 8 shows a flow chart of the program command programming The lock bit protects each block from being programmed inadvertently Refer to 20 3 6 Data Protect Function In EW1 mode do not execute this command on the block where the rewrite control program is allocated In EWO mode the microcomputer enters read status register mode as soon as an auto program operation starts The status register can be read The SR7 bit in the status register is set to 0 at the same time an auto pr
269. eE 298 22 11 9 9l Ol etos cHu dE NIMM LIII MEI MMOL INIM IEE 299 22 12 A D CONVENE sco certet ada causes EL RRR EA a AA Eun Fee aeria Te dr OEE a ada 300 22 18 CAN Module itc o reete ci host ee adeant e rcd ven ted n Lett t A tied 302 22 19 1 Heading CIS TR Register iia iia 302 22 13 2 Performing CAN Configuration sess en nnn enne nennen 304 22 13 3 Suggestions to Reduce Power Consumption sssssssssssssseseeeeeenenee nennen 305 22 13 4 CAN Transceiver in Boot Mode sssssssssssseseeeeee nennen nennen nnne n nennen nennen 306 22 14 Programmable I O Ports 0ooooncoconoccconoccconncccnnnacnnonoconnnncc naar cc seen eene nennen ein rette nennen a a nennen 307 22 15 Dedicated Input Pirineo tecti iced edicit cuerda eren rede EL dera RL tie 308 22 16 Electrical Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers 309 22 17 Mask ROM Verso i secet altri lea 310 22 18 Flash Memory Versi mita A eren 311 22 18 1 Functions to Prevent Flash Memory from Rewriting ooonocccnnccconococonoccnonnnccnananananrnananara naar 311 22 182 Stop MOG Tr ess 311 2218 39 Walt MOOG imei latas 311 22 18 4 Low Power Dissipation Mode and On Chip Oscillator Low Power Dissipation Mode 311 22 18 5 Writing Command and Dato iia 311 22 18 6 Program Commana essasi dd deta dde 311 22 18 7 Lock Bit Program COMMA
270. eceive all IDs with Basic CAN mode slots 14 and 15 receive all IDs which are not stored into slots 0 to 13 Rev 1 10 Jul01 2005 page 218 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 18 CAN Module 18 10 Acceptance Filter Support Unit ASU The acceptance filter support unit has a function to judge valid invalid of a received ID through table search The IDs to receive are registered in the data table a received ID is stored in the CiAFS register i 0 1 and table search is performed with a decoded received ID The acceptance filter support unit can be used for the IDs of the standard frame only The acceptance filter support unit is valid in the following cases When the ID to receive cannot be masked by the acceptance filter Example IDs to receive 078h 087h 111h When there are too many IDs to receive it would take too much time to filter them by software Figure 18 18 shows the write and read of the CiAFS register in word access Addresses CANO CAN1 When wie E 0 E eeo E E A 3 8 Decoder AIT when ead T I I I TOTO oeo aen zan Figure 18 18 Write read of CiAFS Register in Word Access Rev 1 10 Jul01 2005 page 219 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 18 CAN
271. ecial Mode 9 IE MOJE cocina tort alehe ri daa ga aeree Rer d REO 168 14 1 6 Special Mode 4 SIM Mode UART2 ssssssssssssseeeeeeneenneenn nennen nennen rnnt nnne 170 TAZ o 175 14 2 1 SVO Operation Timing cicero dines cee A ocv acd euet eon 179 14 2 2 CLK Polarity Selection ssesssssssssssseseseeeene nennen eene nenne rens e nnne nn nn restes neret 179 14 2 3 Functions for Setting an SOUTi Initial Value sse 180 pA DOnV BEBE ai tmt MP Mesi MN M M EA 181 uem Bleue 185 15 1 1 One shot MOde reti ce ot tec Herc asa 185 15 1 2 Repeat Mode itin Dti eer ee qr Re epe anu uA do ege eren e Eae nuts edat a ead cua 187 15 1 35Mgle Sweep o 189 15 1 4 Repeat Sweep Mode Q miccional avd o Hd ua a 191 15 1 5 Bepeat Sweep MOde Wains ladies 193 15 2 FUNCION p 195 15 2 1 Resolution Select FUNCtON i ecd ia ci dde en 195 15 2 2 Sample and Hold rio e bsec anita ER Dn isst i reum SERRE 195 15 2 3 Extended Analog Input Pins eene nennen nennen iE E EATER 195 15 2 4 External Operation Amplifier Op Amp Connection Mode ssssseeeeeneee 195 15 2 5 Current Consumption Reducing Function sesenta 196 15 2 6 Output Impedance of Sensor under A D Conversion
272. egister by reading the UiRB register In this case i e UIRRM bit 1 do not write dummy data to the UiTB register in a program The UORRM and U1RRM bits are bit 2 and bit 3 in the UCON register respectively and the U2RRM bit is bit 5 in the U2C1 register Rev 1 10 Jul01 2005 page 143 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O 14 1 1 5 Serial Data Logic Switching Function When the UiLCH bit in the UiC1 register i 0 to 2 1 reverse the data written to the UiTB register has its logic reversed before being transmitted Similarly the received data has its logic reversed when read from the UiRB register Figure 14 14 shows serial data logic 1 When the UiLCH bit in the UiC1 register 0 no reverse trastero AAA AAA TXDi H Tros NE DO j D J D2 j 23 j D4 j D5 jJ D6 j D7 2 When the UiLCH bit in the UiC1 register 1 reverse rransterelosk Y1 L UUU UU ES oee i20to2 This applies to the case where the CKPOL bit in the UiCO register 0 transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock and the UFORM bit 0 LSB first Figure 14 14 Serial Data Logic Switching 14 1 1 6 Transfer Clock Output From Multiple Pins UART1 Use the CLKMD1 to CLKMDO bits in the UCON register to select one of the two transfer clock output
273. ehavior during the interrupt sequence is described below Figure 9 5 shows time required for executing the interrupt sequence 1 The CPU obtains interrupt information interrupt number and interrupt request level by reading address 000000h Then the IR bit applicable to the interrupt information is set to 0 interrupt requested 2 The FLG register prior to an interrupt sequence is saved to a temporary register within the CPU 3 The I D and U flags in the FLG register become as follows The flag is set to 0 interrupt disabled The D flag is set to 0 single step interrupt disabled The U flag is set to 0 ISP selected However the U flag does not change state if an INT instruction for software interrupt Nos 32 to 63 is executed The temporary register within the CPU is saved to the stack The PC is saved to the stack The interrupt priority level of the acknowledged interrupt in IPL is set The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC 4 5 6 7 a e AA After the interrupt sequence is completed an instruction is executed from the starting address of the interrupt routine NOTE 1 Temporary register cannot be modified by users CPU clock Address bus Address Indeterminate 1 SP 2 J SP 4 J
274. eir contents are indeterminate Setting this bit to 1 initializes the Clock Prescaler Reset Flag prescaler for the timekeeping clock RW When read the value of this bit is O Figure 12 17 TABSR Register TBSR Register and CPSRF Register Rev 1 10 Jul01 2005 page 111 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 Timers 12 2 1 Timer Mode In timer mode the timer counts a count source generated internally Table 12 6 lists specifications in timer mode Figure 12 18 shows TBiMR register in timer mode Table 12 6 Specifications in Timer Mode Specification Count Source f1 f2 f8 f32 fC32 Count Operation e Down count When the timer underflows it reloads the reload register contents and continues counting Divide Ratio 1 n 1 n set value of the TBi register 0000h to FFFFh Count Start Condition Set the TBiS bit to 1 start counting Count Stop Condition Set the TBiS bit to 0 stop counting Interrupt Request Generation Timing Timer underflow TBilN Pin Function I O port Read from Timer Count value can be read by reading the TBi register Write to Timer When not counting and until the 1st count source is input after counting start Value written to the TBi register is written to both reload register and counter When counting after 1st count source input Value written
275. enn nana nana enana eie eaoaai natnra nnns 11 28 Flag Register Flu ta a asieshee stat ener a ead 11 2 8 1 Carty Flag GC FlaG spot tio lid isos 11 2 8 2 Debug Flag D Flag oiim nter i 11 2 8 3 Zero Hag Z Flag ae LUE Reiter ld 11 2 8 4 Sign Flag S Flag seriei tile AAA cca bee 11 2 8 5 Register Bank Select Flag B Flag nennen nennen rennen eene 11 2 8 6 Overllow Flag Q Flag onto e errant rrt npa denen tob de etc iaa 11 2 8 7 Interrupt Enable Flag Flag sssssssssseseeneeeeneneneneen nennen enne en nennen nnne n nensi nnne 11 2 8 8 Stack Pointer Select Flag U Flag eren nnne nnne 11 2 8 9 Processor Interrupt Priority Level IPL ssssssssseseeeeeeneeeenenenne ennemis 11 2 8 10 RESONON Ar iria 11 3 UII Vias 12 4 Special Function Register SFR ooooocccccccccnoncccccncconononannnoncnnnnnnnnnnnnnnnnnnnnncnnnnnnnnnnnnnnnncnnnnnnes 13 UM i O nn A IO 29 5 1 Hardware Reset viii O A di 29 5 1 1 Reset on a Stable Supply Voltage sssrin idinaan aeaio rca rancia 29 9 1 2 Power orn ROSEN octo al iia 29 5 2 SoftWare RESET sumone ei ai 29 5 3 Watchdog Timer ReSOtiococonccconiccconoccccnonccnononcn non nconn cnn rca 29 5 4 Oscillation Stop Detection Reset oococinncccinociconoccccnncnconnnccnoncononnnnnon conan narran nennen tnnt inrer ranr rre na nnns 29 6 Processor AA TP T T 32 7e Clock Generating Cl Mee TITTEN 35 7 1 Types of Clock Generating C
276. ent and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 1 Timer A 12 Timers Figure 12 3 shows a block diagram of the timer A Figures 12 4 to 12 6 show the timer A related registers The timer A supports the following four modes Except in event counter mode timers AO to A4 all have the same function Use the TMOD1 to TMODO bits in the TAiMR register i 0 to 4 to select the desired mode Timer mode The timer counts an internal count source Event counter mode The timer counts pulses from an external device or overflows and underflows of other timers One shot timer mode The timer outputs a pulse only once before it reaches the minimum count 0000h Pulse width modulation mode The timer outputs pulses in a given width successively Select Clock source TCK1 to TCKO TMOD1 to TMODO 00 MR2 0 One shot TMODI to TMODO 10 Mead to TMODO e Pulse width modulation TMOD1 to TMODO 11 Timer gate function TMOD1 to TMODO 00 MR2 1 5 e Event counter TMOD1 to TMODO 01 n Polarity TAIINO selection bits TB2 overflow 1 TAj overflow 1 TAk overflow 1 To external trigger circuit Decrement Counter Increment Decrement ee counts down except in event counter mode O TMOD1 to TMODO Pulse output Toggle Flip Flop TCK1 to TCKO TMOD1 to TMODO MR2 to MR1 Bits in TAiMR register TAI TAITGH to TAiTGL Bits
277. ent and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Clock Generating Circuit Oscillation Stop Detection Register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset SZ ell CM2 000Ch 0X000000b 2 Oscillation stop re oscillation detection function disabled Oscillation stop re oscillation detection function enabled Main clock or PLL clock System Clock Select E 2 2 5 6 7 8 11 E On chip oscillator clock On chip oscillator oscillating Main clock stop re oscillation not detected Main clock stop re oscillation detected Main clock oscillating cues XIN Monitor Flag 10 Main clock turned off RO Eu Sn Oscillation Stop Re Oscillation Detection Enable Bit 2 3 4 Oscillation Stop Re Oscillation Detection Flag 9 Nothing is assigned When write set to 0 When read its content is indeterminate Operation Select Bit 0 Oscillation stop detection reset behavior if oscillation stop 1 Oscillation stop re oscillation re oscillation is detected 2 detection interrupt Write to this register after setting the PRCO bit in the PRCR register to 1 write enable The CM20 CM21 and CM27 bits do not change at oscillation stop detection reset Setthe CM20 bit to 0 disable before entering stop mode After exiting stop mode set the CM20 bit back to 1 enable Set the CM20 bit to 0 disable before setting the CMO5 bit in
278. er 16 bits Indication of the protocol status CANI slot status register CISSTR register 16 bits Indication of the status of contents of each slot CANI interrupt control register CilCR register 16 bits Selection of interrupt enabled or disabled for each slot CANI extended ID register CilDR register 16 bits Selection of ID format standard or extended for each slot e CANI configuration register CICONR register 16 bits Configuration of the bus timing e CANI receive error count register CIRECR register 8 bits Indication of the error status of the CAN module in reception the counter value is incremented or decremented according to the error occurrence CANI transmit error count register CITECR register 8 bits Indication of the error status of the CAN module in transmission the counter value is incremented or decremented according to the error occurrence e CANI time stamp register CiTSR register 16 bits Indication of the value of the time stamp counter CANI acceptance filter support register CiAFS register 16 bits Decoding the received ID for use by the acceptance filter support unit Explanation of each register is given below Rev 1 10 Jul01 2005 page 203 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 18 CAN Module 18 2 CANi Message Box i 0 1 Table 18 1 shows the memory mapping o
279. er When separated no current will flow from the VREF pin into the resistor ladder helping to reduce the power consumption of the chip To use the A D converter set the VCUT bit to 1 VREF connected and then set the ADST bit in the ADCONO register to 1 A D conversion start The VCUT and ADST bits cannot be set to 1 at the same time Nor can the VCUT bit be set to 0 VREF unconnected during A D conversion Note that this does not affect VREF for the D A converter irrelevant 15 2 6 Output Impedance of Sensor under A D Conversion To carry out A D conversion properly charging the internal capacitor C shown in Figure 15 10 has to be completed within a specified period of time T sampling time as the specified time Let output impedance of sensor equivalent circuit be RO microcomputer s internal resistance be R precision error of the A D converter be X and the A D converter s resolution be Y Y is 1024 in the 10 bit mode and 256 in the 8 bit mode 1 t VC is generally VC VIN 1 e C RO R y X And whent T VC VIN VIN VIN 1 1 T C RO R X e pois Y 1 na C RO R Y Hence R0 EET eee R C In X Y Figure 15 10 shows analog input pin and external sensor equivalent circuit When the difference between VIN and VC becomes 0 1LSB we find impedance RO when voltage between pins VC changes from 0 to VIN 0 1 1024 VIN in time T 0 1 1024 means that A D precision drop due to insufficient capaci
280. erflow When the INVOO bit is set to 1 the first interrupt is generated when the timer B2 underflows n 1 times if n is the value set in the ICTB2 counter Subsequent interrupts are generated every n times the timer B2 underflows 3 Set the INVO1 bit to 1 after setting the ICTB2 register 4 Set the INVO2 bit to 1 to operate the dead time timer U V and W phase output control circuits and ICTB2 counter 5 When the INVO2 bit is set to 1 three phase control timer functions and the INVO3 bit to 0 three phase control timer output disabled U U V V W and W pins including pins shared with other output functions enter a high impedance state 6 The INVO3 bit is set to 0 when the followings occurs Reset A concurrent active state occurs while INV04 bit is set to 1 The INVO3 bit is set to 0 by program A signal applied to the NMI pin changes H to L 7 The INVO5 bit cannot be set to 1 by program Set the INVO4 bit to 0 as well when setting the INVO5 bit to 0 8 The following table describes how the INVO6 bit works INVO6 1 Mode Triangular wave modulation mode Sawtooth wave modulation mode Timing to Transfer from the IDBO Transferred once by generating a Transferred every time a transfer trigger and IDB1 Registers to Three transfer trigger after setting the IDBO is generated Phase Output Shift Register and IDB1 registers Timing to Trigger the Dead Time On the falling edge of a one shot p
281. eripheral function interrupts 9 3 1 Special Interrupts Special interrupts are non maskable interrupts 9 3 1 1 NMI Interrupt An NMI interrupt is generated when input on the NMI pin changes state from high to low For details refer to 9 7 NMI Interrupt 9 3 1 2 DBC Interrupt Do not normally use this interrupt because it is provided exclusively for use by development support tools 9 3 1 3 Watchdog Timer Interrupt Generated by the watchdog timer Once a watchdog timer interrupt is generated be sure to initialize the watchdog timer For details about the watchdog timer refer to 10 Watchdog Timer 9 3 1 4 Oscillation Stop and Re oscillation Detection Interrupt Generated by the oscillation stop and re oscillation detection function For details about the oscillation stop and re oscillation detection function refer to 7 Clock Generating Circuit 9 3 1 5 Single Step Interrupt Do not normally use this interrupt because it is provided exclusively for use by development support tools 9 3 1 6 Address Match Interrupt An address match interrupt is generated immediately before executing the instruction at the address indicated by the RMADO to RMAD3 registers that corresponds to one of the AIERO or AIER1 bit in the AIER register or the AIER20 or AIER21 bit in the AIER2 register which is 1 address match interrupt enabled For details refer to 9 10 Address Match Interrupt 9 3 2 Peripheral Function Interrupts The peripheral function int
282. eristics timing charts Software Manual Detailed description of assembly instructions and microcomputer performance of each instruction Application Note Application examples of peripheral functions Sample programs Introduction to the basic functions in the M16C family Programming method with Assembly and C languages RENESAS TECHNICAL UPDATE Preliminary report about the specification of a product a document etc NOTE 1 Before using this material please visit our website to verify that this is the most updated document available SFR Page Reference De a Cana B 1 A e e A E E E E A 1 AE e iia 1 1 2 PRertormance Outline srasni eie eaae a a a a e a aaa 2 1 9 Block DIagrarm ure r o st Ene gho rui Eg Do reng d ealunece Du dutu ed ecud uae xg utu bleed unu Eu 4 1 4 Product LISt qum 5 1 5 Pin Configuration E 6 1 6 Pin DescriPtiON caricia da A A een A E co E AA 8 2 Central Processing Unit CPU casona 10 2 1 Data Registers RO H1 R2 and RS iii ii ld ENN RAEES 10 2 2 Address Registers AO and A1 ieu a arias 10 2 3 Frame Base Register FB te on op ieu A daa 11 2 4 Interrupt Table Register INIT s intor prb ipee T 11 2 5 dresse Em 11 2 6 User Stack Pointer USP Interrupt Stack Pointer ISP oooooonnnccccnnicicinccccnnnccconnnnnnonancnano canon conan na nana nn 11 2 7 Static Base Register SB svansson eei annasa aeaa ia nana canon
283. error occurs the value of the UiRB register will be indeterminate The IR bit in the SiRIC register does not change 3 The timing at which the framing error flag and the parity error flag are set is detected when data is transferred from the UARTI receive register to the UiRB register Rev 1 10 Jul01 2005 page 146 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O Table 14 6 Registers to Be Used and Settings in UART Mode Register 0 to 8 Function Set transmission data 0 to 8 Reception data can be read OER FER PER SUM Error flag 0 to 7 Set a transfer rate SMD2 to SMDO Set these bits to 100b when transfer data is 7 bit long Set these bits to 101b when transfer data is 8 bit long Set these bits to 110b when transfer data is 9 bit long CKDIR Select the internal clock or external clock STPS Select the stop bit PRY PRYE Select whether parity is included and whether odd or even IOPOL Select the TXD RXD input output polarity CLKO CLK1 Select the count source for the UiBRG register CRS Select CTS or RTS to use TXEPT Transmit register empty flag CRD Enable or disable the CTS or RTS function NCH Select TXDi pin output mode CKPOL Set to 0 UFORM LSB first or MSB
284. errupt occurs when a request from the peripheral functions in the microcomputer is acknowledged The peripheral function interrupt is a maskable interrupt See Table 9 2 Relocatable Vector Tables about how the peripheral function interrupt occurs Refer to the descriptions of each function for details Rev 1 10 Jul01 2005 page 62 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 9 Interrupt 9 4 Interrupts and Interrupt Vector One interrupt vector consists of 4 bytes Set the start address of each interrupt routine in the respective interrupt vectors When an interrupt request is accepted the CPU branches to the address set in the corresponding interrupt vector Figure 9 2 shows the interrupt vector Vector address L Low order address Middle order address High order address Vector address H Figure 9 2 Interrupt Vector 9 4 1 Fixed Vector Tables The fixed vector tables are allocated to the addresses from FFFDCh to FFFFFh Table 9 1 lists the fixed vector tables In the flash memory version of microcomputer the vector addresses H of fixed vectors are used by the ID code check function For details refer to 20 2 Functions to Prevent Flash Memory from Rewriting Table 9 1 Fixed Vector Tables Vector table Addresses Ref Interrupt Source Address L to Address H eference Undefined Instruction UND instruction
285. esasTechnology Corp 2 6 2 Ote machi Chiyoda ku Tokyo 100 0004 Japan
286. et to 0 dead timer enabled phase switches from an inactive level to an active level when the dead time timer stops 5 When the INV11 bit in the INVC1 register is set to 0 three phase mode 0 the value of the TAi register is transferred to the reload register by a timer Ai start trigger When the INV11 bit is set to 1 three phase mode 1 the value of the TAi1 register is first transferred to the reload register by a timer Ai start trigger Then the value of the TAi register is transferred by the next trigger The values of the TAi1 and TAi registers are transferred alternately to the reload register with every timer Ai start trigger 6 Do not write to these registers when the timer B2 underflows 7 Follow the procedure below to set the TAi1 register a Write value to the TAi1 register b Wait one timer Ai count source cycle and c Write the same value as a to the TAi1 register Timer B2 Register b15 b8 b7 bo Address After Reset 0395h 0394h Indeterminate If setting value is n count source is divided by n 1 0000h to FFFFh RW The timers A1 A2 and A4 start every time an underflow occurs ia 1 Use a 16 bit data for read and write Figure 13 5 TA1 TA2 TA4 TA11 TA21 and TA41 Registers and TB2 Register Rev 1 10 Jul01 2005 page 122 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Three Pha
287. ev 1 10 Jul01 2005 page 229 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 Programmable 1 O Ports Pull up selection Direction register i lt Data bus Port latch 4 NOTE 1 777 Switching between 4 CMOS and Nch Input to respective peripheral functions f Pull up selection Direction register gt Ouput o Data bus Port latch m Switching between CMOS and Nch Data bus lt NMI interrupt input Direction register iis 1 e re Output i Data bus Port latch gt Input to respective peripheral functions f P7 1 P9 1 wove Symbolizes a parasitic diode Make sure the input voltage on each port will not exceed VCC 2 4 Symbolizes a parasitic diode Figure19 3 1 O Ports 3 Rev 1 10 Jul01 2005 page 230 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 Programmable l O Ports Pull up selection Direction register P10 Oto P10 3 inside dotted line not included E
288. f the CANi message box It is possible to access to the message box in byte or word Mapping of the message contents differs from byte access to word access Byte access or word access can be selected by the MsgOrder bit of the CICTLR register Table 18 1 Memory Mapping of CANi Message Box Address Message Content Memory mapping CANO Byte access 8 bits Word access 16 bits 0060h n 16 0 0260h n 16 0 SID10 to SID6 SID5 to SIDO 0060h n 16 1 0260h n 16 1 SID5 to SIDO SID10 to SID6 0060h n 16 2 0260h n 16 2 EID17 to EID14 EID13 to EID6 0060h n 16 3 0260h n 16 3 EID13 to EID6 EID17 to EID14 0060h n 16 4 0260h n 16 4 EID5 to EIDO Data Length Code DLC 0060h n 16 5 0260h n 16 5 Data Length Code DLC EID5 to EIDO 0060h n 16 6 0260h n 16 6 Data byte O Data byte 1 0060h n 16 7 0260h n 16 7 Data byte 1 Data byte 0 0060h n 16 13 0260h n 16 13 Data byte 7 Data byte 6 0060h n 16 14 0260h n 16 14 Time stamp high order byte Time stamp low order byte 0060h n 16 15 0260h n 16 15 Time stamp low order byte Time stamp high order byte i20 1 n 2 0 to 15 the number of the slot Rev 1 10 Jul01 2005 page 204 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 18 CAN Module Figures 18 2 and 18 3 show the bit mapping in each slot in by
289. f the UiBRG register 00h to FFh During slave The CKDIR bit 1 external clock Input from SCLi pin Transmission Start Condition Before transmission can start the following requirements must be met The TE bit in the UiC1 register 1 transmission enabled The TI bit in the UiC1 register O data present in the UiTB register Reception Start Condition Before reception can start the following requirements must be met The RE bit in the UiC1 register 1 reception enabled The TE bit in the UiC1 register 1 transmission enabled The TI bit in the UiC1 register O data present in the UiTB register Interrupt Request When start or stop condition is detected acknowledge undetected and acknowledge Generation Timing detected Error Detection Overrun error This error occurs if the serial I O started receiving the next data before reading the UiRB register and received the 8th bit of the next data Select Function Arbitration lost Timing at which the ABT bit in the UiRB register is updated can be selected SDAi digital delay No digital delay or a delay of 2 to 8 UiBRG count source clock cycles selectable Clock phase setting With or without clock delay selectable i Oto2 NOTES 1 When an external clock is selected the conditions must be met while the external clock is in the high state 2 If an overrun error occurs the value of UiRB register will be indeterminate The IR bit in the SiRIC register does
290. f the following conditions are all met the following restriction occur in operation of oscillation stop re oscillation stop detection interrupt Conditions CM20 bit in CM2 register 1 oscillation stop re oscillation stop detection function enabled CM27 bit in CM2 register 1 oscillation stop re oscillation stop detection interrupt e CMO 2 bit in CMO register 0 do not stop peripheral function clock in wait mode Enter wait mode from high speed or middle speed mode Restriction If the oscillation of XIN stops during wait mode the oscillation stop re oscillation stop detection interrupt request is generated after the microcomputer is moved out of wait mode without starting immediately Figures 22 1 and 22 2 show the operation timing at oscillation stop re oscillation stop detection XIN fRING 1 INTO input CPU l Oscillation stop re oscillation RI operation Waltmode c INTO interrupt request XIN stops Wait mode is released NOTE 1 This clock is generated by the on chip oscillator It is not supplies after reset The operating clock can changes from on chip oscillator clock on chip oscillation oscillating to BCLK by using oscicllation stop re oscillation detection function or setting the CM21 bit in the CM2 register Figure 22 1 Operation Timing at Oscillation Stop Re oscillation Stop Detection at Wait Mode when moving out of wait mode by using INTO interrupt fRING 1 FLU UTI MU L
291. fer data UART2 Transmit Receive Control Register 1 b7 b6 b5 b4 b3 b2 bi bO Symbol U2C1 Address 01FDh After Reset 00000010b a Sineme Foci A Transmission disabled ve Transmit nable Bit Transmission enabled El Transmit Buffer Empty Flag Data present in U2TB register No data present in U2TB register Receive Enable Bit Reception disabled Reception enabled Receive Complete Flag No data present in U2RB register Data present in U2RB register UART2 Transmit Interrupt Cause Select Bit Transmit buffer empty TI bit 1 Transmit is completed TXEPT bit 1 UART2 Continuous Receive Mode Enable Bit Continuous receive mode disabled Continuous receive mode enabled Data Logic Select Bit 1 No reverse Reverse Error ene Output Enable B FO Q Iii c O mi D Output disabled Output enabled 1 The U2LCH bit is enabled when the SMD2 to SMDO bits in the U2MR register are set to 001b clock synchronous serial I O mode 100b UART mode 7 bit transfer data or 101b UART mode 8 bit transfer data Set this bit to 0 when the SMD2 to SMDO bits are set to 010b I2C mode or 110b UART mode 9 bit transfer data Figure 14 7 UOC1 U1C1 Registers and U2C1 Register 131 NESAS Rev 1 10 Jul 01 2005 page 134 of 318 REJO9B0124 0110 Under development This document is under development and its contents are subject to change M
292. first can be selected when transfer data is 8 bit long Set this bit to 0 when transfer data is 7 or 9 bit long TE Set this bit to 1 to enable transmission TI Transmit buffer empty flag RE Set this bit to 1 to enable reception RI Reception complete flag U2IRS Y Select the source of UART2 transmit interrupt U2RRM Set to 0 UiLCH Set this bit to 1 to use inverted data logic UiERE Set to 0 0 to 7 Set to 0 0 to 7 Set to 0 0 to 7 Set to 0 0 to 7 Set to 0 i Oto2 NOTES UOIRS U1IRS Select the source of UARTO UART1 transmit interrupt UORRM U1RRM Set to 0 CLKMDO Invalid because the CLKMD1 bit 0 CLKMD1 Set to 0 RCSP Set this bit to 1 to accept as input the UARTO CTSO signal from the P6 4 pin 7 Set to 0 1 The bits used for transmit receive data are as follows e Bit O to bit 6 when transfer data is 7 bit long e Bit O to bit 7 when transfer data is 8 bit long e Bit O to bit 8 when transfer data is 9 bit long 2 Set bit 4 to bit 5 in the UOC1 and U1C1 registers to 0 The UOIRS U1IRS UORRM and U1RRM bits are included in the UCON register Rev 1 10 Jul 01 2005 page 147 of 318 REJO9B0124 0110 131 NESAS Under development This document is under development and its contents are subject to change
293. flag CRD Set to 1 NCH Select TXDi pin output format CKPOL Clock phases can be set in combination with the CKPH bit in the UiSMR3 register UFORM Set to 0 TE Set this bit to 1 to enable transmission Tl Transmit buffer empty flag RE Set this bit to 1 to enable reception RI Reception complete flag U2IRS Y Select UART2 transmit interrupt cause U2RRM Y UiLCH UiERE Set to 0 0 to 7 Set to 0 0 to 7 Set to 0 CKPH Clock phases can be set in combination with the CKPOL bit in the UiCO register NODC Set to 0 0 2 4 107 Set to 0 0 to 7 Set to 0 i Oto2 NOTES UOIRS U1IRS Select UARTO and UART1 transmit interrupt cause UORRM U1RRM Set to 0 CLKMDO Invalid because the CLKMD 1 bit 0 CLKMD1 RCSP 7 Set to 0 1 Not all register bits are described above Set those bits to 0 when writing to the registers in Special Mode 2 2 Set the bit 4 and bit 5 in the UOC1 and U1C1 registers to 0 The UOIRS U1IRS UORRM and U1RRM bits are in the UCON register Rev 1 10 Jul01 2005 page 165 of 318 REJO9B0124 0110 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O 14 1 4 1 Clock Phase Setting Function One of four
294. flash memory version of microcomputer these addresses are allocated to the vector addresses H of fixed vectors 22 18 2 Stop Mode When entering stop mode the following settings are required Set the FMRO1 bit to 0 CPU rewrite mode disabled Disable DMA transfer before setting the CM10 bit to 1 stop mode Execute the instruction to set the CM10 bit to 1 stop mode and then the JMP B instruction Example program BSET 0 CM1 Stop mode JMP B L1 L1 Program after exiting stop mode 22 18 3 Wait Mode When entering wait mode set the FMRO1 bit in the FMRO register to 0 CPU rewrite mode disabled before executing the WAIT instruction 22 18 4 Low Power Dissipation Mode and On Chip Oscillator Low Power Dissipation Mode If the CMO5 bit is set to 1 main clock stopped do not execute the following commands Program Block erase Erase all unlocked blocks Lock bit program software command Read lock bit status 22 18 5 Writing Command and Data Write commands and data to even addresses in the user ROM area 22 18 6 Program Command By writing xx40h in the first bus cycle and data to the write address in the second bus cycle an auto program operation data program and verify will start The address value specified in the first bus cycle must be the same even address as the write address specified in the second bus cycle 22 18 7 Lock Bit Program Command By writing xx77h in the first bus cyc
295. for a data frame At this time the RemActive 0 However transmission does not start as long as RspLock bit remains 1 thus no automatic response Response transmission starts when the RspLock bit is set to 0 TrmReq RecReq Remote RspLock RemActive RspLock Bits in CIMCTLj register i 0 1 j O to 15 When configuring a slot as a reception slot note the following points 1 Before configuring a slot as a reception slot be sure to set the CiIMCTLj register to 00h 2 A received message is stored in a slot that matches the condition first according to the result of reception mode configuration and acceptance filtering operation Upon deciding in which slot to store the smaller the number of the slot is the higher priority it has 3 In normal CAN operation mode when a CAN module transmits a message of which ID matches the CAN module never receives the transmitted data In loop back mode however the CAN module receives back the transmitted data In this case the module does not return ACK When configuring a slot as a transmission slot note the following points 1 Before configuring a slot as a transmission slot be sure to set the CiIMCTLj registers to 00h 2 Set the TrmReq bit in the CiMCTLj register to 0 not transmission slot before rewriting a transmission slot 3 A transmission slot should not be rewritten when the TrmActive bit in the CiMCTLj register is 1
296. from being modified to 0 1 should be written to the DMAS bit when 1 is written to the DMAE bit In this way the state of the DMAS bit immediately before being written can be maintained Similarly when writing to the DMAE bit with a read modify write instruction 1 should be written to the DMAS bit in order to maintain a DMA request which is generated during execution n2 Read the TCRi register to verify whether the DMAi is in an initial state If the read value is equal to a value which was written to the TCRi register before DMA transfer start the DMAi is in an initial state If a DMA request occurs after writing to the DMAE bit the value written to the TCRi register is 1 If the read value is a value in the middle of transfer the DMAi is not in an initial state Rev 1 10 Jul01 2005 page 289 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 9 Timers 22 9 1 Timer A 22 9 1 1 Timer A Timer Mode The timer remains idle after reset Set the mode count source counter value etc using the TAIMR i 0 to 4 register and the TAi register before setting the TAIS bit in the TABSR register to 1 count starts Always make sure the TAiMR register is modified while the TAIS bit remains 0 count stops regardless whether after reset or not While counting is in progress
297. fter Reset ADCON2 03D4h 00h Function b2 b1 ADGSELO 0 0 Port P10 group is selected A D Input Group Select Bit 0 1 Do not set a value 1 0 Port PO group is selected ADGSEL1 1 1 Port P2 group is selected b3 Reserved Bit Set to 0 0 Selects fAD divide by 2 of fAD or divide by 4 of fAD 1 Selects divide by 3 of fAD divide by 6 of fAD or divide by 12 of fAD Frequency Select Bit 2 2 Nothing is assigned When write set to O When read their contents are O 1 If the ADCON register is rewritten during A D conversion the conversion result will be indeterminate 2 The 9AD frequency must be 10 MHz or less The selected AD frequency is determined by a combination of the CKSO bit in the ADCONO register the CKS1 bit in the ADCON register and the CKS2 bit in the ADCONe register Divide by 4 of fAD Divide by 2 of fAD fAD Divide by 12 of fAD 1 1 1 Divide by 6 of fAD 1 o o 0 eee 0 1 0 I3 Divide by 3 of fAD Symbol Address After Reset ADO 03C1h to O3COh Indeterminate AD1 O3C3h to O3C2h Indeterminate AD2 03C5h to 03C4h Indeterminate A D Register i i 2 O to 7 AD3 03C7h to 03C6h Indeterminate iis AD4 03C9h to 03C8h Indeterminate bO b7 AD5 O3CBh to O3CAh Indeterminate AD6 03CDh to 03CCh Indeterminate AD7 O3CFh to 03CEh Indeterminate When BITS bit in ADCON1 When BITS bit is 0 register is 1 10 bit mode 8 bit mode Low order 8 bits of A D conversion res l
298. ful transmission When using SI O3 interrupt set the IFSROO bit to 1 SI OS 2 When the PCLK6 bit in the PCLKR register 0 A D conversion and key input share the vector and interrupt control register When using the A D conversion interrupt set the IFSRO1 bit to 0 A D conversion When using the key input interrupt set the IFSRO 1 bit to 1 key input 3 If this bit is set to 0 the software interrupt number 1 is selected CANO 1 wake up and the interrupt number 13 is selected CANO 1 error If this bit is set to 1 the interrupt number 1 is selected CANO wake up error and the interrupt number 13 is selected CAN1 wake up error 4 When the IFSR17 bit in the IFSR1 register 0 CAN1 successful reception and SI O4 share the vector and interrupt control register When using the CAN1 successful reception interrupt set the IFSRO3 bit to 0 CAN1 successful reception When using SI O4 interrupt set the IFSRO3 bit to 1 SI O4 5 Timer B5 and SI O5 share the vector and interrupt control register When using the timer B5 interrupt set the IFSRO4 bit to 0 Timer B5 When using SI O5 interrupt set the IFSRO4 bit to 1 SI O5 The SI O5 interrupt is only in the 128 pin version In the 100 pin version set the IFSRO4 bit to 0 Timer B5 6 Timer BO and SI O6 share the vector and interrupt control register When using the timer BO interrupt set the IFSRO5 bit to 0 Timer BO When using SI O6 interrupt set the IFSRO5 bit to
299. ful transmission SI O3 and INT4 share the vector and interrupt control register When using CAN1 successful transmission or SI O3 interrupt set the IFSR16 bit to 0 CAN1 successful transmission SI O3 When using INT4 interrupt set the IFSR16 bit to 1 INT4 3 When setting this bit to 0 CAN1 successful transmission SI O3 make sure the IFSROO bit in the IFSRO register is set to 0 CAN1 successful transmission or 1 SI O3 And make sure the POL bit in the C1TRMIC and S3IC registers are set to 0 falling edge 4 CAN1 successful recception SI O4 and INT5 share the vector and interrupt control register When using the CAN1 successful reception or SI O4 interrupt set the IFSR17 bit to 0 CAN1 successful reception SI O4 When using INT5 interrupt set the IFSR17 bit to 1 INT5 5 When setting this bit to 0 CAN1 successful reception SI O4 make sure the IFSRO3 bit in the IFSRO register is set to 0 CAN1 successful reception or 1 SI O4 And make sure the POL bit in the C1TRMIC and S4IC registers are set to 0 falling edge Figure 9 12 IFSR1 Register Rev 1 10 Jul01 2005 page 75 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Interrupt Request Cause Select Register 2 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset IFSR2 01CFh X0000000b Bit Symbol Function Interrupt Request
300. ge M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O UARTi Transmit Receive Mode Register i 0 to 2 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset UOMR to U2MR 03A0h 03A8h 01F8h 00h b2b1b0 000 Serial I O disabled 00 1 Clock synchronous serial I O mode Serial I O Mode 010 12C mode 2 Select Bit 1 1 00 UART mode transfer data 7 bit long 101 UART mode transfer data 8 bit long 110 UART mode transfer data 9 bit long pw Do not set a value except above Internal External Clock 0 Internal clock Select Bit 1 External clock 3 Stop Bit Length O 1 stop bit Select Bit 1 2 stop bits Odd Even Parity Effective when the PRYE bit 1 Select Bit 0 Odd parity 1 Even parity O Parity disabled 1 Parity enabled 0 1 Parity Enable Bit TXD RXD I O Polarity Reverse Bit No reverse Reverse 1 To receive data set the corresponding port direction bit for each RXDi pin to 0 input mode 2 Set the corresponding port direction bit for SCL and SDA pins to 0 input mode 3 Set the corresponding port direction bit for each CLKi pin to 0 input mode UARTIi Transmit Receive Control Register 0 i 0 to 2 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset UOCO to U2CO 03A4h 03ACh 01FCh 00001000b b1 b0 0 0 f1SIO or f2SIO is selected BRG Count Source 0 1 f8SIO is selected Select Bit 1 0 f32S10 is selected 1 1 Do not set a value CTS RTS y Effective when CRD 0
301. gister b8 State Reset bit 0 CAN operation 1 Hr atirina X When the CAN module s State_Reset bit updating period matches the CPU s read ization mode period it does not enter reset mode for the CPU read has the higher priority i 0 1 Figure 22 5 When Updating Period of CAN Module Matches Access Period from CPU Waittime CPU read signal CC Updating period of the CAN module CPU reset signal E a CiSTR register O b8 Reset state flag 0 CAN operation SON este O Updated without fail in period of SICAN ization mode i 0 1 Figure 22 6 With a Wait Time of 3fCAN Before CPU Read CPU read signal 4 CAN Updating period of the CAN module CPU reset signal CiSTR register b8 State Reset bit 0 CAN operation mode X When the CAN module s State Reset bit updating period matches the CPU s read 1 CAN reset initial period it does not enter reset mode for the CPU read has the higher priority ization mode O Updated without fail in period of 4fCAN 12 0 Figure 22 7 When Polling Period of CPU is 3fCAN or Longer Rev 1 10 Jul01 2005 page 303 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 13 2 Performing CAN Configuration If the Reset bit in the CiCTLR register i 0 1 is changed from 0 operation mode to 1 reset initialization mod
302. gisters Table 7 1 Clock Generating Circuit Specifications Use of Clock Main Clock Oscillation Circuit CPU clock source Peripheral function clock source Sub Clock Oscillation Circuit CPU clock source Clock source of Timer A B On chip Oscillator CPU clock source Peripheral function clock source CPU and peripheral function clock sources when the main clock stops oscillating PLL Frequency Synthesizer CPU clock source Peripheral function clock source Clock Frequency 0 to 16 MHz 32 768 kHz About 1 MHz 16 MHz 20 MHz 24 MHz Usable Oscillator Ceramic oscillator Crystal oscillator Crystal oscillator Pins to Connect Oscillator XIN XOUT XCIN XCOUT Oscillation Stop and Re Oscillation Detection Function Available Available Available Available Oscillation Status After Reset Oscillating Stopped Stopped Stopped Other Externally derived clock can be input Rev 1 10 Jul 01 2005 page 35 of 318 REJO9B0124 0110 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Sub clock oscillation circuit XCIN XCOUT O Sub clock 7 Clock Generating Circuit CM01 CM00 00b PM01 PM00 00b CM01 CM00 01b PM01 PM00 00b oo CLKOUT PMO1 PM00 00b CMO01 CMO0 11b 1 O ports 1C32
303. gnal Data l i l bus CPU use Source Source 1 Destination NOTE 1 The same timing changes occur with the respective conditions at the destination as at the source Figure 11 5 Transfer Cycles for Source Read Rev 1 10 Jul01 2005 page 88 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 11 2 DMA Transfer Cycles Any combination of even or odd transfer read and write addresses is possible 11 DMAC Table 11 2 shows the number of DMA transfer cycles Table 11 3 shows the coefficient j k The number of DMAC transfer cycles can be calculated as follows No of transfer cycles per transfer unit No of read cycles X j No of write cycles X k Table 11 2 DMA Transfer Cycles Transfer Unit Access Address No of Read Cycles 8 bit Transfer No of Write Cycles DMBIT 1 16 bit Transfer DMBIT 0 Table 11 3 Coefficient j k SFR Internal ROM RAM No Wait With Wait 1 Wait 2 Waits j 1 2 2 3 NOTE 1 Depends on the set value of the PM20 bit in the PM2 register Rev 1 10 Jul01 2005 page 89 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 11 DMAC 11 3 DMA Enable When a data transfer starts after setting the DMAE bit in the DMiC
304. h CANO Message Control Register 6 COMCTL6 00h CANO Message Control Register 7 COMCTL7 00h CANO Message Control Register 8 COMCTL8 00h CANO Message Control Register 9 COMCTL9 00h CANO Message Control Register 10 COMCTL10 00h CANO Message Control Register 11 COMCTL11 00h CANO Message Control Register 12 COMCTL12 00h CANO Message Control Register 13 COMCTL13 00h CANO Message Control Register 14 COMCTL14 00h CANO Message Control Register 15 COMCTL15 00h X0000001b 0211h CANO Control Register COCTLR XX0X0000b 0212h A 00h 0213h CANO Status Register COSTR X0000001b 0214h 00h 0215h CANO Slot Status Register COSSTR 00h 0216h 00h 0217h CANO Interrupt Control Register COICR 00h 0218h i 00h IDR 0219h CANO Extended ID Register CO 00h BS CANO Configuration Register COCONR XXh CANO Receive Error Count Register CORECR 00h CANO Transmit Error Count Register COTECR 00h CANO Time Stamp Register COTSR aon CAN1 Message Control Register 0 C1MCTLO 00h CAN1 Message Control Register 1 CAMCTL1 00h CAN1 Message Control Register 2 C1MCTL2 00h CAN1 Message Control Register 3 C1MCTL3 00h CAN1 Message Control Register 4 C1MCTL4 00h CAN1 Message Control Register 5 C1MCTL5 00h CAN1 Message Control Register 6 C1MCTL6 00h CAN1 Message Control Register 7 CAMCTL7 00h CAN1 Message Control Register 8 C1MCTL8 00h CAN1 Message Control Register 9 C1MCTL9 00h CAN1 Message Control Register 10 C1MCTL10 00h CAN1 Message Control Register 11 CAMCTL11 00h CAN1 Message Control Regis
305. h Memory Control Register O b7 b6 b5 b4 b3 b2 bi bO Symbol FMRO Address 01B7h RY BY Status Flag 20 Flash Memory Version After Reset 00000001b 0 Busy being written or erased 1 Ready CPU Rewrite Mode Select Bit 2 Disables CPU rewrite mode Enables CPU rewrite mode Lock Bit Disable Select Bit 3 Enables lock bit Disables lock bit Flash Memory Stop Bit 4 5 Enables flash memory operation Stops flash memory operation placed in low power dissipation mode flash memory initialized FMRO5 FMRO6 Reserved Bit User ROM Area Select Bit 4 Effective in only boot mode Program Status Flag 6 Erase Status Flag 6 Set to 0 0 Boot ROM area is accessed 1 User ROM area is accessed 0 Terminated normally 1 Terminated in error 0 Terminated normally 1 Terminated in error 1 This status includes writing or reading with the lock bit program or read lock bit status command 2 To set this bit to 1 write 0 and then 1 in succession Make sure no interrupts or no DMA transfers will occur before writing 1 after writing 0 Write to this bit when the NMI pin is in the high state Also while in EWO mode write to this bit from a program in other than the flash memory To set this bit to 0 in a read array m ode 3 To set this bit to 1 write 0 and then 1 in succession when the FMRO1 bit 1 Make sure no interrupts or no DMA t
306. hange the CMO6 bit Consequently the medium speed divide by 8 mode is to be selected when the main clock is operated next Rev 1 10 Jul01 2005 page 48 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Clock Generating Circuit 7 4 1 6 On chip Oscillator Mode The on chip oscillator clock divided by 1 undivided 2 4 8 or 16 provides the CPU clock The on chip oscillator clock is also the clock source for the peripheral function clocks If the sub clock is activated fC32 can be used as the count source for timers A and B 7 4 1 7 On chip Oscillator Low Power Dissipation Mode The main clock is turned off after being placed in on chip oscillator mode The CPU clock can be selected like in the on chip oscillator mode The on chip oscillator clock is the clock source for the peripheral function clocks If the sub clock is activated fC32 can be used as the count source for timers A and B When the operation mode is returned to the high and medium speed modes set the CMO6 bit in the CMO register to 1 divide by 8 mode Table 7 3 lists the setting clock related bit and modes Table 7 3 Setting Clock Related Bit and Modes CM2 Register CM1 Register CMO Register CM 1 CM11 CM17 CM16 CMO06 CM05 PLL Operation Mode High Speed Mode Medium divided by 2 divided by 4 divided by 8 divided by 16 Low Speed Mode Low Power
307. he AVCC pin to VCC1 Connect the AVSS pin to VSS Reset input RESET The microcomputer is in a reset state when applying L to the this pin CNVSS Connect this pin to VSS External data bus width select input Connect this pin to VSS Main clock input XIN Main clock output XOUT I O pins for the main clock oscillation circuit Connect a ceramic resonator or crystal oscillator between XIN and XOUT To use the external clock input the clock from XIN and leave XOUT open Sub clock input XCIN Sub clock output XCOUT 1 O pins for a sub clock oscillation circuit Connect a crystal oscillator between XCIN and XCOUT 9 To use the external clock input the clock from XCIN and leave XCOUT open Clock output CLKOUT The clock of the same cycle as fC f8 or f32 is output INT interrupt input INTO to INT8 9 Input pins for the INT interrupt NMI interrupt input NMI Input pin for the NMI interrupt Key input interrupt input 10 to KI3 Input pins for the key input interrupt TAOOUT to TA40UT These are timer AO to timer A4 I O pins TAOIN to TA4IN These are timer AO to timer A4 input pins ZP Input pin for the Z phase TBOIN to TB5IN These are timer BO to timer B5 input pins Three phase motor control output U U V V W W These are Three phase motor control output pins Serial l O CTSO to
308. he UiBRG register i20to2 The above timing diagram applies to the case where the register bits are set as follows CKDIR bit in UIMR register O internal clock CRD bit in VICO register 0 CTS RTS enabled CRS bit in VICO register 0 CTS selected e CKPOL bit in VICO register 0 transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock UiRS bit 0 an interrupt request occurs when the transmit buffer becomes empty UOIRS bit is bit O in UCON register U1IRS bit is bit 1 in UCON register U2IRS bit is bit 4 in U2C1 register 2 Example of Receive Timing when external clock is selected RE bit in UiC1 register TE bit in UiC1 register TI bit in UiC1 register RTSi CLKi RXDi RI bit in UiC1 register IR bit in SiRIC register n o y y Write dummy data to the UiTB register Transferred from the UiTB register to the UARTI transmit register Even if the reception is completed the RTS y does not change The RTS becomes L i 1 fEXT TA when the RI bit changes to 0 from 1 h Receive data is taken in Transferred from UARTi receive register Read out from the UiRB register to the UiRB register E rad Set to 0 when interrupt request is accepted or set to 0 in a program The above timing diagram applies to the case where the register bits are set Make sure the following conditions are met when input as follows
309. he reload register contents and continues counting Divide Ratio 1 n 1 n set value of the TAi register 0000h to FFFFh Count Start Condition Set the TAIS bit in the TABSR register to 1 start counting Count Stop Condition Set the TAIS bit to 0 stop counting Interrupt Request Generation Timing Timer underflow TAiIN Pin Function I O port or gate input TAiOUT Pin Function I O port or pulse output Read from Timer Count value can be read by reading the TAi register Write to Timer When not counting and until the 1st count source is input after counting start Value written to the TAi register is written to both reload register and counter When counting after 1st count source input Value written to the TAi register is written to only reload register Transferred to counter when reloaded next Select Function Gate function Counting can be started and stopped by an input signal to TAiIN pin Pulse output function Whenever the timer underflows the output polarity of TAiOUT pin is inverted When TAIS bit is set to 0 stop counting the pin outputs a low i 0to4 Timer Ai Mode Register i 0 to 4 b7 b6 b5 b4 b3 b2 bi bO HT Jo TJofo Symbol Address After Reset TAOMR to TA4MR 0396h to 039Ah 00h OE EE ET TMODO __ Operation Mode a TMODI Select Bit 00 Timer mode O Pulse is not output Pulse Output Function TA OUT pin is a normal port pin Select Bit 1 Pulse is o
310. he sub clock oscillates stably before switching the clock source for CPU clock to the sub clock Rev 1 10 Jul01 2005 page 282 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution Suggestions to reduce power consumption Ports The processor retains the state of each I O port even when it goes to wait mode or to stop mode A current flows in active I O ports A pass current flows in input ports that high impedance state When entering wait mode or stop mode set non used ports to input and stabilize the potential A D converter When A D conversion is not performed set the VCUT bit in the ADCON1 register to 0 VREF not connection When A D conversion is performed start the A D conversion at least 1 us or longer after setting the VCUT bit to 1 VREF connection D A converter When not performing D A conversion set the DAiE bit i O 1 in the DACON register to 0 input disabled and DAi register to 00h Switching the oscillation driving capacity Set the driving capacity to LOW when oscillation is stable Rev 1 10 Jul01 2005 page 283 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 5 Oscillation Stop Re oscillation Detection Function I
311. hen the SMi6 bit 1 internal clock a low level is output from the CLKi pin if not transferring data Figure 14 40 Polarity of Transfer Clock Rev 1 10 Jul01 2005 page 179 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O 14 2 3 Functions for Setting an SOUTI Initial Value If the SMi6 bit in the SiC register 0 external clock the SOUTI pin output can be fixed high or low when not transferring Figure 14 41 shows the timing chart for setting an SOUTI initial value and how to set it NOTE 1 When CANO function is selected P7 4 P7 5 and P8 O0 can be used as input output pins for SI O4 When CANO function is not selected P9 5 P9 6 and P9 7 can be used as input output pis for SI O4 Example When H selected for SOUTI initial value Setting of the initial value of SOUTI Signal written to output and starting of ia transmission reception SMi7 bit Set the SMi3 bit to 0 SOUTI pin functions as an I O port SMi3 bit Set the SMi7 bit to 1 SOUTI internal SOUTI initial value H SOUTI output Port output Set the SMi3 bit to 1 IE SOUTI pin functions as SOUTi output Setting the SOUTi Port selection switching H level is output initial value to H 2 I O port gt SOUTI from the SOUTi pin Write to the SiTRR register i 3 to 6 5 and 6 are only in the 128 pin version
312. hing is assigned When write set to O b7 b5 When read their contents are indeterminate 1 Write to this register after setting the PRC1 bit in the PRCR register to 1 write enable 2 The PM20 bit become effective when the PLCO7 bit in the PLCO register is set to 1 PLL on Change the PM20 bit when the PLCO7 bit is set to 0 PLL off Set the PM20 bit t 0 2 waits when PLL clock gt 16MHz 3 Once this bit is set to 1 it cannot be set to 0 in a program 4 Setting the PM22 bit to 1 results in the following conditions The on chip oscillator starts oscillating and the on chip oscillator clock becomes the watchdog timer count source The CM10 bit in the CM1 register is disabled against write Writing a 1 has no effect nor is stop mode entered The watchdog timer does not stop when in wait mode or hold state Figure 7 7 PM2 Register Rev 1 10 Jul01 2005 page 41 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Clock Generating Circuit PLL Control Register 0 b7 b6 b5 b4 b3 b2 bi b olonD TT Symbol Address After Reset ZN PLCO 001Ch 0001X010b Do not set a value RW Multiply by 2 Multiply by 4 PLL Multiplying Factor Multiply by 6 RW Select Bit 2 Do not set a value RW Nothing is assigned When write set to 0 When read its content is indeterminate
313. his applies to the case where the register bit are set as follows e CKPOL bit in VICO register O transmit data output at the falling edge of the transfer clock UFORM bit in UiCO register O LSB first STPS bit in UiMR register 0 1 stop bit PRYE bit in UIMR register 1 parity enabled Figure 14 20 Serial Data Logic Switching 14 1 2 5 TXD and RXD I O Polarity Inverse Function This function inverses the polarities of the TXDi pin output and RXDi pin input The logic levels of all input output data including the start stop and parity bits are inversed Figure 14 21 shows the TXD and RXD input output polarity inverse 1 When the IOPOL bit in the UiMR register 0 no reverse Transfer lock TLE LE LILILILILU UU UU LL horses sr Do y Dr y D2 9303 95 De J 07 y y SP pow _sT Doy DOLES Ds ppr E De ep RIS ieee BOY DT Y D2 YDS OF y v5 y De o7 P UE 2 When the IOPOL bit 2 1 reverse trece TELL LL LL LLL TXDi H reverse t E Ur D2 D3 D4 A D5 DS D7 A Py SP ST D0 DT 02 103 Dx A D5 A De D7 P ASP RXDi reverse i201t02 ST Start bit P Parity bit SP Stop bit NOTE 1 This applies to the case where the register bits are set as follows UFORM bit in VICO register O LSB first STPS bit in UIMR register 0 1 stop bit e PRYE bit in UiMR register 1 parity enabled Figure 14 21 TXD and RXD I O Polarity Inverse Rev 1 10 Jul01 2005 page 152 of 318 RENESAS REJ0
314. i IETS Function 0 CTS function is selected 2 Select Bit 1 RTS function is selected Data present in transmit register Transmit Register during transmission Empty Flag No data present in transmit register transmission completed CTS RTS function enabled CTS RTS Disable Bit 1 CTS RTS function disabled P6_0 P6_4 P7_3 can be used as I O ports TXDi SDAi and SCLi pins are CMOS output atin TXDi SDAi and SCLi pins are N channel open drain output Transmit data is output at falling edge of transfer clock and receive data is CLK Polarity input at rising edge Select Bit Transmit data is output at rising edge of transfer clock and receive data is input at falling edge Transfer Format LSB first Select Bit 4 MSB first 1 CTS1 RTS1 can be used when the CLKMD1 bit in the UCON register 0 only CLK1 output and the RCSP bit in the UCON register 0 CTSO RTSO not separated 2 Set the corresponding port direction bit for each CTSi pin to 0 input mode 3 SCL2 P7 1 is N channel open drain output The NCH bit in the U2CO register is N channel open drain output regardless of the NCH bit 4 The UFORM bit is enabled when the SMD2 to SMDO bits in the UiMR register are set to 001b clock synchronous serial I O mode or 101b UART mode 8 bit transfer data Set this bit to 1 when the SMD2 to SMDO bits are set to 010b 12 mode and to 0 when the SMD2 to SMDO bits are set to 100b UART m
315. ication When returning to the CAN operation mode from the bus off state the module has the following two cases In this time the value of any CAN registers except CISTR CIRECR and CiTECR registers does not change 1 When 11 consecutive recessive bits are detected 128 times The module enters instantly into error active state and the CAN communication becomes possible immediately 2 When the RetBusOff bit in the CiCTLR register 1 Force return from buss off The module enters instantly into error active state and the CAN communication becomes possible again after 11 consecutive recessive bits are detected Rev 1 10 Jul01 2005 page 215 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 18 CAN Module 18 6 Configuration CAN Module System Clock The M16C 6N Group M16C 6NK M16C 6NM has a CAN module system clock select circuit Configuration of the CAN module system clock can be done through manipulating the CCLKR register and the BRP bit in the CICONR register i 0 1 For the CCLKR register refer to 7 Clock Generating Circuit Figure 18 14 shows a block diagram of the clock generating circuit of the CAN module system CAN module ivide by E Prescaler system clock 1 2 Baud rate prescaler division value CCLKR register P 1 CAN module fCAN CAN module system clock P The value written in the BRP
316. ifier DLC 0274h 0275h 0276h 0277h 0278h an CAN1 Message Box 1 Data Field 027Bh 027Ch 027Dh 027Eh 027Fh CAN1 Message Box 1 Time Stamp X Undefined NOTE 1 The blank areas are reserved and cannot be accessed by users Rev 1 10 Jul01 2005 page 22 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 11 SFR Information 11 Address Register Symbol AferReset 0280h 0281h EN CAN1 Message Box 2 Identifier DLC 0284h 0285h 0286h 0287h 0288h Wr M Message Box 2 Data Field 028Bh 028Ch 028Dh 028Eh pz 028Fh Message Box 2 Time Stamp 0290h 0291h e Message Box 3 Identifier DLC 0294h 0295h 0296h 0297h 0298h 0299h M E 029Ah essage Box 3 Data Field 029Bh 029Ch 029Dh 029Eh P 029Fh Message Box 3 Time Stamp 02A0h 02A1h o2A2h 7 02A3h Message Box 4 Identifier DLC 02A4h 02A5h 02A6h 02A7h 02A8h o2A9h 02AAh Message Box 4 Data Field 02ABh 02ACh 02ADh 02AEh 02AFh Message Box 4 Time Stamp 02BOh 02B1h o2B2h 7 02B3h
317. in ONSF register If i 0 bits in TRGSR register if i 1 to 4 Timer AO TAIS Bit in TABSR register Timer A1 TAiUD Bit in UDF register Timer A2 Timer A3 i 0to4 Timer A4 j i except j 4 wheni 0 k i 1 except k 0 wheni 4 NOTE 1 Overflow or underflow Figure 12 3 Timer A Block Diagram Rev 1 10 Jul01 2005 page 94 of 318 RENESAS REJ09B0124 0110 Addresses 0387h 0386h 0389h 0388h 038Bh 038Ah 038Dh 038Ch 038Fh 038Eh TAj Timer A4 Timer AO Timer A1 Timer A2 Timer A3 TAk Timer A1 Timer A2 Timer A3 Timer A4 Timer AO h order Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 Timers Timer Ai Mode Register i 2 O to 4 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset TAOMR to TA4MR 0396h to 039Ah 00h Bit Symbol b1b0 00 Timer mode Operation Mode Select Bit O 1 Event counter mode 1 0 One shot timer mode 1 1 Pulse width modulation mode MR1 MR2 MR3 TCKO i i i Count Source Salect Bit Function varies with each TCK1 operation mode Timer Ai Register i 0 to 4 Address After Reset 5m bo 0387h to 0386h Indeterminate 0389h to 0388h Indeterminate po 038Bh to 038Ah Indeterminate 038Dh to 038Ch Indeterminate Function varies with each operation mode 038Fh to 038Eh Indeterminate Mois Funan Setting Range Timer Divide the count source by n 1 where n E
318. in UCON register 0 CLKS1 not used Note that when using the CTS RTS separate function UART1 CTS RTS separate function cannot be used Figure 14 22 shows CTS RTS separate function usage Microcomputer TXDO P6_3 RXDO P6_2 RTSO P6_0 CTSO P6_4 Figure 14 22 CTS RTS Separate Function Rev 1 10 Jul01 2005 page 153 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O 14 1 3 Special Mode 1 I C Mode FC mode is provided for use as a simplified I C interface compatible mode Table 14 10 lists the specifications of the IC mode Figure 14 23 shows the block diagram for I C mode Table 14 11 lists the registers used in the I C mode and the register values set Table 14 12 lists the functions in IC mode Figure 14 24 shows the transfer to the UiRB register and interrupt timing As shown in Table 14 12 the microcomputer is placed in IPC mode by setting the SMD2 to SMDO bits to 010b and the IICM bit to 1 Because SDAi transmit output has a delay circuit attached SDAi output does not change state until SCLi goes low and remains stably low Table 14 10 1 C Mode Specifications Specification Transfer Data Format Transfer data length 8 bits Transfer Clock During master The CKDIR bit in the UiMR register O internal clock fj 2 n 1 fj f181O f2SIO f8SIO f32SIO n Setting value o
319. in the PCR register to 1 the corresponding port latch can be read no matter how the PD1 register is set Table 19 2 lists an example connection of unused pins Figure19 12 shows an example connection of unused pins Rev 1 10 Jul01 2005 page 227 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 Programmable 1 O Ports Pull up selection Direction register gt inside dotted line included lt PO 0toPO 7 P2 0to P2 7 Data bus 4 Port latch P3 0to P3 7 P4 0to P4 7 P5 0to P5 4 P5 6 P11 2to P11 4 P11 6 2 gt inside dotted line P12 Oto P12 7 3 not included P13 0 toP13 4 2 P14 0 P14 12 Pull up selection Direction register P1 OtoP1 4 Port P1 control register Data bus t4 Port latch Pull up selection Direction register P1 5toP1 7 Port P1 control register Data bus Port latch Input to respective peripheral functions Pull up selection Direction register lt TS Data bus 4 Port latch xm
320. ing to the standard ID and the extended ID of 29 bits The CiGMR register corresponds to slots 0 to 13 the CiLMAR register corresponds to slot 14 and the CiLMBR register corresponds to slot 15 The masking function becomes valid to 11 bits or 29 bits of a received ID according to the value in the corresponding slot of the CiIDR register upon acceptance filtering operation When the masking function is employed it is possible to receive a certain range of IDs Figure 18 16 shows correspondence of the mask registers and slots Figure 18 17 shows the acceptance function ser S Slot 5 S ot 6 CiLMAR register Slot 14 CiLMBR register Slot 15 i 0 1 Figure 18 16 Correspondence of Mask Registers to Slots ID of the ID stored in The value of the Mask Bit Values received message _ the slot mask register 0 ID to which the received message corresponds match is handled as Don t care 1 ID to which the received message corresponds match is checked Acceptance Signal Acceptance judge signal 0 The CAN module ignores the current incoming message Not stored in any slot 1 The CAN module stores the current incoming message in a slot of which ID matches Figure 18 17 Acceptance Function When using the acceptance function note the following points 1 When one ID is defined in two slots the one with a smaller number alone is valid 2 When it is configured that slots 14 and 15 r
321. ing value of the TB2 register O to 65535 Count source f1 f2 f8 132 fC32 Three Phase PWM Output Width Triangular wave modulation count source X n X2 Sawtooth wave modulation count source X n n Setting value of the TA4 TA1 and TA2 registers of the TAA TA41 TA1 TA11 TA2 and TA21 registers when setting the INV11 bit to 1 1 to 65535 Count source f1 f2 f8 f32 fC32 Dead Time Count source X p or no dead time p Setting value of the DTT register 1 to 255 Count source f1 f2 f1 divided by 2 f2 divided by 2 Active Level Enable to select H or L Positive and Negative Phase Concurrent Active Disable Function Positive and negative phases concurrent active disable function Positive and negative phases concurrent active detect function Interrupt Frequency NOTE For Timer B2 interrupt select a carrier wave cycle to cycle basis through 15 times carrier wave cycle to cycle basis 1 Forced cutoff with NMI input is effective when the IVPCR1 bit in the TB2SC register is set to 1 three phase output forcible cutoff by NMI input enabled If an L signal is applied to the NMI pin when the IVPCR1 bit is 1 the related pins go to a high impedance state regardless of which functions of those pins are being used Related pins P7 2 CLK2 TA1OUT V P7 S CTS2 RTS2 TA1IN V P7_4 TA20UT W CLK4 e P7_5 TA2IN W SOUTA e P8 O TA4OUT U SIN4 e P8_1 TA4IN U Rev
322. ip tion of each peripheral function for details about the interrupts from peripheral functions Figure 22 3 shows the procedure for changing the interrupt generate factor Changing the interrupt source Disable interrupt 2 8 Change the interrupt generate factor including a mode change of peripheral function Use the MOV instruction to set the IR bit to 0 interrupt not requested 3 Enable interrupt 2 9 End of change IR bit A bit in the interrupt control register for the interrupt whose interrupt generate factor is to be changed NOTES 1 The above settings must be executed individually Do not execute two or more settings simultaneously using one instruction 2 Use the flag for the INTI interrupt i 0 to 8 6 to 8 are only in the 128 pin version For the interrupts from peripheral functions other than the INTi interrupt turn off the peripheral function that is the source of the interrupt in order not to generate an interrupt request before changing the interrupt generate factor In this case if the maskable interrupts can all be disabled without causing a problem use the flag Otherwise use the corresponding ILVL2 to ILVLO bit for the interrupt whose interrupt generate factor is to be changed 3 Refer to 22 7 6 Rewrite Interrupt Control Register for details about the instructions to use and the notes to be taken for instruction execution Figure 22 3 Procedure for Changing Interrupt Generate Factor 22
323. ircuit sereine ireren aaraa iad eoa aa rana 35 LAA Mal Clock unitario nd o ati 43 eM SUDUCIOCK 2 ooo lao eu IU 44 11 3 On chip Osclllator Clock au died AOR 45 AS A O tect eat eee fees 45 Table of Contents A 1 7 2 CPU Clock and Peripheral Function Clock oooooconcccnnnccccnocccconocanononononananoneno conca nonn cnn nan n cnn rra nan rc narran 47 72 1 CPU Clock and BOLK siia aaia a daa 47 12 2 Peripheral Function Clock titt A adi 47 8 Clock Output Function 0 cda ctae re place Rcs Rai 47 4 degere m E 48 741 Normal Operation MOGO c eed esee ede ta 48 1 4 2 WaIBMOOS cote enean A DIM UE uM DE o D cct eee eres 50 TA S tP MOE iii tbe redire vacated up ERIS datei dai LE 52 7 5 Oscillation Stop and Re oscillation Detection Function ssssssssseeeeeeneeennn 57 7 5 1 Operation When CM27 Bit 0 Oscillation Stop Detection Reset ssssesseeesss 57 7 5 2 Operation When CM27 Bit 1 Oscillation Stop Re oscillation Detection Interrupt 57 7 5 3 How to Use Oscillation Stop and Re oscillation Detection Function ssesssessssssss 58 8 Protectio d NNMERO TR 59 sm A c E 60 9 1 Type of Interrupis E A a 60 9 2 software Intetrr pls tt respete title 61 9 2 1 Undefined Instruction Interrupt 4 iiu ias betreten tesi expo tiere de leds een eo xu EE rase 61 9 2 2 Overllow Interrupt ioci ond a otros ae ecc cire e
324. irection Register DMAO Request Cause Select Register Port P12 Register Port P13 Register DMA1 Request Cause Select Register Port P12 Direction Register Port P13 Direction Register CRC Data Register Pull up Control Register 0 Pull up Control Register 1 CRC Input Register Pull up Control Register 2 The blank areas are reserved B 8 Port Control Register CENESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Rev 1 10 Jul 01 2005 1 Overview The M16C 6N Group M16C 6NK M16C 6NM of single chip microcomputers are built using the high performance silicon gate CMOS process using an M16C 60 Series CPU core and are packaged in 100 pin and 128 pin plastic molded LQFP These single chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency With 1 Mbyte of address space they are capable of executing instructions at high speed Being equipped with two CAN Controller Area Network modules in M16C 6N Group M16C 6NK M16C 6NM the microcomputer is suited to car audio and industrial control systems The CAN modules comply with the 2 0B specification In addition this microcomputer contains a multiplier and DMAC which combined with fast instruction processing capability makes it suitable for control of various OA and communi
325. is high impedance 2 When using the ports P11 to P13 set the PU37 bit in the PURS register to 1 usable If this bit is set to 0 unusable the P11 to P13 regisrers are set to 00h 3 The P11 to P13 registers are only in the 128 pin version b7 b6 b5 b4 b3 b2 bi bo Port P8 Register b7 b6 b5 b4 b3 b2 bi b0 Address After Reset 03FOh Indeterminate Bit symbol A Pao Port P8 O0 Bit The pin level on any l O port which is set P8 1 Port P8_1 Bit for input mode can be read by reading 5 the corresponding bit in this register Pi8 2 Port P8 _2 Bit The pin level on any I O port which is Port P8 3 Bit set for output mode can be controlled m ERN by writing to the corresponding bit in Port P8 4 Bit this register Except for P8 5 PortP8 5Bit 0 L level Port P8 6 Bit 1 H level Port P8 _7 Bit Port P14 Control Regisrer 128 pin version b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset PC14 03DEh XX00XXXXb Bit Symbol Bit Name Function The pin level on any l O port which is set for input mode can be read by reading the i PONTIA OBN corresponding bit in this register dd The pin level on any I O port which isset for output mode can be controlled by writing to the corresponding bit in this register Port P14 1 Bit 0 L level 1 H level Nothing is assigned When write set to 0 When read their contents are indeterminate Port P14 0 Direction O Input mode Bit Func
326. isi nahea nda aeaa aiiai aiana 248 20 3 5 Software GOMMANGS croata al ia aa DE aaea aa a E S 250 20 3 6 Data Protect Funcion titanio laa 255 20 3 7 Status Register SRD Register eui doce Lapi as 255 20 3 8 Full Status Check eno irlanda 257 A 4 20 4 Standard Serial l O Mode cccccccncnccccncccnnonoccnnnnnnnononcnnnonnnncnnnnnonnnnncnnnn nn nana nnnnnnnnnnn cnn n cnn nnnan EEEa annn rannen nenne 259 20 4 1 ID Code Check FUNCION isis sida il ciao einer va De e 259 20 4 2 Example of Circuit Application in Standard Serial l O Mode coooooocccnnnnoccccncnnooocnnconoonnnoncnnnoncnnnono 263 20 5 Parallel VO MOG repertae b exu e a ies 264 20 5 1 User ROM and Boot ROM Areas eiie ura neon ne dee Co Y RR e xe Rn cani 264 20 5 2 ROM Gode Protect Funci n uasa coto tos ctt ad 264 20 6 CAN VO Mode ias eni e Oe trad acta Pot Goce estas eae eii rada 265 20 6 1 ID Code Check FUNCION uec invi io Ee e edd dre eva duin cw E 265 20 6 2 Example of Circuit Application in CAN I O Mode ssssseeneeenmeenneeneennerennnnns 268 21 Electrical Characteristics ooooconococicicicoconococnnononnnnncnnnnnnnnnnnnnnnnnnnno nono nennen nnn nnne nnne 269 22 Usage Pre ueritate tener tuere otu a a HR ARMES EPUM EF UM EM EE ME 279 22 SRR case tan oes sen O ENIM MEIN ELEME INI MINMUIQINIEMLIEINGIM I I 279 22 2 INST Bo 280 22 9 PLL Frequency Syntlieslzer soto eee ebbe bes ero e t d tu o E P
327. ister 0 Timer B4 Interrupt Control Register TB4IC System Clock Control Register 1 UART Bus Collision Detection Interrupt Control Register U1 BCNIC Timer B3 Interrupt Control Register TB3IC Address Match Interrupt Enable Register es seson ceca nterrupt Soni id HORENIC AN1 Successful Reception Interrupt Control Register Protect Register SI O4 Interrupt Control Register S4IC INT5 Interrupt Control Register INT5IC Oscillation Stop Detection Register CAN Successful Transmission Interrupt Control Register C1 TRMIC SI O3 Interrupt Control Register S3IC Watchdog Timer Start Register INT4 Interrupt Control Register INT4IC Watchdog Timer Control Register UART2 Bus Collision Detection Interrupt Control Register U2BCNIC DMAO Interrupt Control Register DMOIC Address Match Interrupt Register 0 DMA1 Interrupt Control Register DM1IC 0012h CANO 1 Error Interrupt Control Register CO1 ERRIC 0013h A D Conversion Interrupt Control Register ADIC 0014h Key Input Interrupt Control Register KUPIC UART2 Transmit Interrupt Control Register S2TIC Address Match Interrupt Register 1 UART2 Receive Interrupt Control Register S2RIC UARTO Transmit Interrupt Control Register SOTIC UARTO Receive Interrupt Control Register SORIC UART1 Transmit Interrupt Control Register S1TIC UART1 Receive Interrupt Control Register S1RIC Timer AO Interrupt Control Register TAOIC Timer A1 Interrupt Control Register TA11C Timer A2 Interrupt Control Register TA2IC
328. ister to select INT8 is only in the 128 pin version In the 100 pin version set the IFSR22 bit to 0 Timer B1 17 Rev 1 10 If the PCLK6 bit in the PCLKR register is set to 1 software interrupt number 13 can be changed to CANO 1 error or key input interupt and software interrupt number 14 can be changed to A D interrupt The software interrupt number of key input is changed from 14 to 13 Use the IFSR26 bit in the IFSR2 register to select when selecting CANO 1 error or key input Jul 01 2005 page 64 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 9 5 Interrupt Control The following describes how to enable disable the maskable interrupts and how to set the priority in which order they are accepted What is explained here does not apply to non maskable interrupts Use the I flag in the FLG register IPL and the ILVL2 to ILVLO bits in the each interrupt control register to enable disable the maskable interrupts Whether an interrupt is requested is indicated by the IR bit in the each interrupt control register Figures 9 3 and 9 4 show the interrupt control registers Interrupt Control Register 9 Interrupt b7 b6 b5 b4 b3 b2 bi b0 Symbol Address C01WKIC 8 0041h CORECIC 0042h COTRMIC 0043h TB5IC S5IC 5 0045h TB4IC U1BCNIC 2 0046h TB3IC UOBCNIC 3 0047h U2BCNIC 004Ah DMOIC DM
329. ists the registers used in UART mode and the register values set Table 14 5 UART Mode Specifications Specification Transfer Data Format Character bit transfer data Selectable from 7 8 or 9 bits Start bit 1 bit Parity bit Selectable from odd even or none Stop bit Selectable from 1 or 2 bits Transfer Clock e CKDIR bit in UIMR register 0 internal clock fj 16 n 1 fj f1SIO f2SIO f8SIO f32SIO n Setting value of the UIBRG register 00h to FFh e The CKDIR bit 1 external clock fEXT 16 n 1 fEXT Input from CLKi pin n Setting value of the UIBRG register 00h to FFh Transmission Reception Control Selectable from CTS function RTS function or CTS RTS function disabled Transmission Start Condition Before transmission can start the following requirements must be met The TE bit in the UiC1 register 1 transmission enabled e The TI bit in the UiC1 register 0 data present in UiTB register If CTS function is selected input on the CTSi pin L Reception Start Condition Before reception can start the following requirements must be met The RE bit in the UiC1 register 1 reception enabled Start bit detection Interrupt Request Generation Timing For transmission one of the following conditions can be selected The UIIRS bit 0 transmit buffer empty when transferring data from the UiTB register to the UARTI transmit register at start of transmission
330. it After the initial value is set in the CRCD register the CRC code is set in that register each time one byte of data is written to the CRCIN register CRC code generation for one byte data is finished in two cycles Figure 17 1 shows the block diagram of the CRC circuit Figure 17 2 shows the CRC related registers Figure 17 3 shows the calculation example using the CRC operation Data bus high order CRC code generating circuit x16 4x12 4x5 44 CRCIN register Figure 17 1 CRC Circuit Block Diagram CRC Data Register b8 pope Symbol Address After Reset CRCD 03BDh to 03BCh Indeterminate Seting Range When data is written to the CRCIN register after setting the initial value in the CRCD register the CRC code can 0000h to FFFFh RW be read out from the CRCD register CRC Input Register i a Address After Reset O3BEh Indeterminate Seting Range Data input 00h to FFh RW Figure 17 2 CRCD Register and CRCIN Register Rev 1 10 Jul01 2005 page 200 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 17 CRC Calculation Setup procedure and CRC operation when generating CRC code 80C4h e CRC operation performed by the M16C CRC code Remainder of a division in which the value written to the CRCIN register with its bit positions reversed is divided by the generator polynomial Generator polynomial X X X
331. it 8 in the UIRB register is read as bit 0 1 If the source or cause of any interrupt is changed the IR bit in the interrupt control register for the changed interrupt may inadvertently be set to 1 interrupt requested Refer to 22 7 Interrupts If one of the bits shown below is changed the interrupt source the interrupt timing etc change Therefore always be sure to set the IR bit to O interrupt not requested after changing those bits e SMD2 to SMDO bits in UiIMR register IICM2 bit in UISMR2 register NOOB OP IICM bit in UiSMR register e CKPH bit in UISMR3 register Set the initial value of SDAi output while the SMD2 to SMDO bits in the UiMR register 000b serial I O disabled Second data transfer to the UiRB register rising edge of SCLi 9th bit First data transfer to the UiRB register falling edge of SCLi 9th bit See Figure 14 26 STSPSEL Bit Functions See Figure 14 24 Transfer to UiRB Register and Interrupt Timing When using UARTO be sure to set the IFSRO6 bit in the IFSRO register to 1 cause of interrupt UARTO bus collision detection When using UART1 be sure to set the IFSRO7 bit in the IFSRO register to 1 cause of interrupt UART1 bus collision detection Rev 1 10 Jul 01 2005 REJO9B0124 0110 page 157 of 318 ENESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Seria
332. jojo ojojojojo 22mm 2 2 5 s s s gt CANO Message Box 8 Time Stamp e ojo T m 2 CANO Message Box 9 Identifier DLC o ojojojojo ojojojo mm a TI UTI NoD an Aja 2 2 2 2 2 CANO Message Box 9 Data Field CANO Message Box 9 Time Stamp OOFFh Symbol Symbol CANO Message Box 10 Identifier DLC CANO Message Box 14 Identifier DLC CANO Message Box 10 Data Field CANO Message Box 14 Data Field 010Fh CANO Message Box 10 Time Stamp 014Fh CANO Message Box 14 Time Stamp 204 0110h 0150h 205 CANO Message Box 11 Identifier DLC CANO Message Box 15 Identifier DLC CANO Message Box 11 Data Field CANO Message Box 15 Data Field CANO Message Box 11 Time Stamp CANO Message Box 15 Time Stamp o A A A Ex o rt oa A zr A m y o pare al n ojojojojo apajaj ZA kp E mk NIDIA BR a gb a y ojojojojo pre ard Bere Bere ger o a oj aj a N DIAA 0 a ie a Ee a e e A m co zx o A a co 2 ojo ala ce zs ojo bord pare g g yF o A o a UJ SE mojo w S 5 5 o o o oj o ojal ajaja eoimim goc o 3 m xIm ojo al m om 3 o m a a o E o A zy ojo A A NIN PO i ojo pare eri oo WIN TT o Rz Nm AR gt o O R E ojo MIN o ojo bara r Q oO 2 o A N nd o Exi o A a ojo A A No no co oo 5 ojo k a D
333. k Figure 7 1 Clock Generating Circuit Rev 1 10 Jul 01 2005 page 36 of 318 REJO9B0124 0110 CM27 1 1 8 116 CM06 0 CM17 CM16 11b CM06 0 CM17 CM16 10b CMO06 0 CM17 CM16 01b CM17 CM16 00b Reset generating circuit Oscillation stop detection reset Oscillation stop re oscillation detection interrupt generating circuit Oscillation stop re oscillation detection interrupt signal CMe1 switch signal Voltage PLL clock control oscillator VCO Internal lowpass filter 31 NE SAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM System Clock Control Register 0 b7 b6 b5 b4 b3 b2 bi b0 7 Clock Generating Circuit When the CM21 bit 0 Address 0006h After Reset 01001000b Symbol CMO Bit Symbol Bit Name Function Clock Output Function Select Bit Valid only in single chip mode b1 b0 0 I O port P5 7 O 1 fC output 1 0 f8 output 1 1 f32 output 0 Do not stop peripheral function clock in wait mode 1 Stop papan function clock in wait mode 2 o LOW HIGH CMOS Capacity Select Bit 3 I O port P8 6 P8 7 XCIN ll generation CM04 Port XC Select Bit 3 function 4 0 On CMO05 Main Clock Stop Bit 5 4 Off 8 9 CMO06 Main Clock Division Select 0 CM16 and CM17 valid Bit O 7 10 12 1 Division by 8 mo
334. ks in place of the main clock If the main clock stops oscillating when the CM20 bit in the CM2 register is 1 oscillation stop re oscillation detection function enabled and the CM27 bit is 1 oscillation stop re oscillation detection interrupt the on chip oscillator automatically starts operating supplying the nec essary clock for the microcomputer 7 1 4 PLL Clock The PLL clock is generated by a PLL frequency synthesizer This clock is used as the clock source for the CPU and peripheral function clocks After reset the PLL clock is turned off The PLL frequency synthe sizer is activated by setting the PLCO7 bit to 1 PLL operation When the PLL clock is used as the clock source for the CPU clock wait a fixed period of tsu PLL for the PLL clock to be stable and then set the CM11 bit in the CM1 register to 1 Before entering wait mode or stop mode be sure to set the CM11 bit to 0 CPU clock source is the main clock Furthermore before entering stop mode be sure to set the PLCO7 bit in the PLCO register to 0 PLL stops Figure 7 11 shows the procedure for using the PLL clock as the clock source for the CPU The PLL clock frequency is determined by the equation below PLL clock frequency f XIN X multiplying factor set by the PLCO2 to PLCOO bits in the PLCO register However PLL clock frequency 16 MHz 20 MHz or 24 MHz The PLCO2 to PLCOO bits can be set only once after reset Table 7 2 shows the e
335. l CAN1 Message Box 14 Identifier DLC CAN1 Message Box 14 Data Field 034Fh CAN1 Message Box 14 Time Stamp 0350h C2 al o CAN1 Message Box 15 Identifier DLC C2 a ojo C2 So 2 CAN1 Message Box 15 Data Field ojo o a eim EM C2 o A ojo w oo Go PO a a CAN1 Message Box 15 Time Stamp CAN1 Global Mask Register 204 205 CAN1 Local Mask A Register C1LMAR CAN1 Local Mask B Register C1LMBR ojojojo 09 C5 NNN worm 23 25 25 206 206 206 Symbol Count Start Flag 96 111 124 Symbol Clock Prescaler Reset Flag 97 111 A D Register O One Shot Start Flag 97 Trigger Select Register 97 124 A D Register 1 Up Down Flag 96 A D Register 2 Timer AO Register 95 A D Register 3 0387h Timer A1 Register ve Timer A2 Register 03C7h A D Register 4 A D Register 5 038Bh 038Ch Timer A3 Register 03CBh 03CCh A D Register 6 038Dh 038Eh Timer A4 Register 03CDh 03CE A D Register 7 Timer BO Register Timer B1 Register 110 110 Timer B2 Register 122 A D Control Register 2 Timer AO Mode Register A D Control Register O 183 186 188 Timer A1 Mode Register 125 A D Control Register 1 190 192 194 Timer A2 Mode Register 102 125 D A Register O 199 Timer A3 Mode Register 102 Time
336. l I O 1 IICM2 0 ACK and NACK interrupts CKPH 0 no clock delay 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCLi sDai X D7 X D6 X D5 X D4 X D3 X D2 X D1 X DO X DB ACK NACK j ACK interrupt DMA1 request NACK interrupt Transfer to UiRB register b15 b9 b8 b7 Ds D7 De Ds Da Ds D2 UiRB register 2 IICM2 0 CKPH 1 clock delay 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCLi SDAi X D7 X D6 X D5 X D4 X D3 X D2 X D1 X Do X D8 ACK NACK ACK interrupt DMA1 request NACK interrupt 4 Transfer to UiRB register b15 b9 b8 b7 D8 D7 D6 D5 D4 D3 UiRB register 3 IICM2 1 UART transmit receive interrupt CKPH 0 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCLi SDAi X D7 X D6 X D5 X D4 X D3 X D2 X D1 X DO X D8 ACK NACK t f Receive interrupt Transmit interrupt DMA1 request Transfer to UiRB register b15 b9 b8 b7 4 IICM2 1 CKPH 1 UiRB register 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCLi
337. l Operation Amplifier Op Amp Connection Mode Multiple analog inputs can be amplified using a single external op amp via the ANXEO and ANEX1 pins Set the OPA1 to OPAO bits in the ADCON1 register to 11b external op amp connection mode The inputs from ANI i 0 to 7 are output from the ANEXO pin Amplify this output with an external op amp before sending it back to the ANEX1 pin The A D conversion result is stored in the corresponding ADi register The A D conversion speed depends on the response characteristics of the external op amp Figure 15 9 shows an example of how to connect the pins in external operation amp NOTE 1 ANO i and AN2 i can be used the same as ANI Microcomputer ADGSEL1 to ADGSELO bits in ADCON register 00b Resistor ladder re Successive conversion register to ADGSELO bits 10b so to ADGSELO bits 11b So gt z m X o ANEX1 Comparator External op amp Figure 15 9 External Op Amp Connection Rev 1 10 Jul01 2005 page 195 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 A D Converter 15 2 5 Current Consumption Reducing Function When not using the A D converter its resistor ladder and reference voltage input pin VREF can be separated using the VCUT bit in the ADCON 1 regist
338. laced into stop mode by setting the CM10 bit in the CM1 register to 1 all clocks turned off At the same time the CMO6 bit in the CMO register is set to 1 divide by 8 mode and the CM15 bit in the CM1 register is set to 1 main clock oscillator circuit drive capability high Before entering stop mode set the CM20 bit in the CM2 register to 0 oscillation stop re oscillation detection function disabled Also if the CM11 bit in the CM1 register is 1 PLL clock for the CPU clock source set the CM11 bit to 0 main clock for the CPU clock source and the PLCO7 bit in the PLCO register to 0 PLL turned off before entering stop mode 7 4 3 2 Pin Status in Stop Mode Table 7 6 lists the pin status in stop mode Table 7 6 Pin Status in Stop Mode i Single Chip Mode I O Ports Retains status before stop mode CLKOUT When fC selected H When f8 f32 selected Retains status before stop mode Rev 1 10 Jul01 2005 page 52 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Clock Generating Circuit 7 4 3 3 Exiting Stop Mode Stop mode is exited by a hardware reset NMI interrupt or peripheral function interrupt When the hardware reset or NMI interrupt is used to exit wait mode set all ILVL2 to ILVLO bits in the interrupt control registers for the peripheral function interrupt to
339. lag S Flag This flag is set to 1 when an arithmetic operation resulted in a negative value otherwise it is 0 2 8 5 Register Bank Select Flag B Flag Register bank 0 is selected when this flag is 0 register bank 1 is selected when this flag is 1 2 8 6 Overflow Flag O Flag This flag is set to 1 when the operation resulted in an overflow otherwise it is 0 2 8 7 Interrupt Enable Flag I Flag This flag enables a maskable interrupt Maskable interrupts are disabled when the flag is 0 and are enabled when the flag is 1 The flag is set to 0 when the interrupt request is accepted 2 8 8 Stack Pointer Select Flag U Flag ISP is selected when the U flag is 0 USP is selected when the U flag is 1 The U flag is set to 0 when a hardware interrupt request is accepted or an INT instruction for software interrupt Nos 0 to 31 is executed 2 8 9 Processor Interrupt Priority Level IPL IPL is configured with three bits for specification of up to eight processor interrupt priority levels from level 0 to level 7 If a requested interrupt has priority greater than IPL the interrupt request is enabled 2 8 10 Reserved Area When white to this bit write 0 When read its content is indeterminate Rev 1 10 Jul01 2005 page 11 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C
340. le and xxDOP to the highest order even address of a block in the second bus cycle the lock bit for the specified block is set to 0 The address value specified in the first bus cycle must be the same highest order even address of a block specified in the second bus cycle Rev 1 10 Jul01 2005 page 311 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 18 8 Operation Speed Set the CMO6 bit in the CMO register and the CM17 to CM16 bits in the CM1 register to clock frequency of 10 MHz or less before entering CPU rewrite mode EWO or EW1 mode Also set the PM17 bit in the PM1 register to 1 with wait state 22 18 9 Prohibited Instructions The following instructions cannot be used in EWO mode because the CPU tries to read data in flash memory UND instruction INTO instruction JMPS instruction JSRS instruction and BRK instruction 22 18 10 Interrupt EWO Mode To use interrupts having vectors in a relocatable vector table the vectors must be relocated to the RAM area e The NMI and watchdog timer interrupts are available since the FMRO and FMR1 registers are forcibly reset when either interrupt request is generated Allocate the jump addresses for each interrupt service routines to the fixed vector table Flash memory rewrite operation is aborted when the NMI or watchdog timer interrupt reques
341. le cutoff by NMI input high impedance Three Phase Output Port disabled NMI Control Bit 1 3 Three phase output forcible cutof by NMI input high impedance enabled Nothing is assigned When write set to O b7 b2 When read their contents are 0 1 Write to this register after setting the PRC1 bit in the PRCR register to 1 write enabled 2 If the INV11 bit in the INVC1 register is O three phase mode 0 or the INVO6 bit in the INVCO register is 1 sawtooth wave modulation mode set this bit to 0 timer B2 underflow 3 Related pins are U P8_0 TA40UT SIN4 U P8_1 TA4IN V P7_2 CLK2 TA10UT V P7_3 CTS2 RTS2 TAIIN W P7_4 TA20UT CLK4 W P7_5 TA2IN SOUTA If a low level signal is applied to the NMI pin when the IVPCR1 bit 1 the target pins go to a high impedance state regardless of which functions of those pins are being used MR After forced interrupt cutoff input H to the NMI pin and set the IVPCR 1 bit to 0 this forced cutoff will be reset IVPCR1 f RW Figure 13 6 ICTB2 Register and TB2SC Register Rev 1 10 Jul01 2005 page 123 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Three Phase Motor Control Timer Function Trigger Select Register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address i raa TRGSR 0383h RD 9e m T E TA1TGL TA1TGL rimer A1 Event Trigger
342. lect Bit control timer function External Trigger Set to 0 with the three phase motor RW Select Bit control timer function Set to 1 selected by the Trigger Select Bit TRGSR Bean with the three phase RW motor control timer function Set to 0 with the three phase motor control timer function b7 b6 0 0 f1 or f2 0 1 f8 10 132 1 fC32 Count Source Select Bit Timer B2 Mode Register b7 b6 b5 b4 b3 b2 bi LTT LTT Symbol Address After Reset TB2MR 039Dh 00XX0000b 0 ee IN mr T TMODO Set to 00b timer mode when using nw Es t Moge the three aa motor mn timer TMOD1 function RW MRo _ Disabled when using the three phase motor control timer function When write set to 0 MR1 When read its content is indeterminate MR2 Set to 0 when using three phase motor control timer function When write in three phase motor control timer function set to 0 MR3_ When read in three phase motor control timer function its content is indeterminate TCKO Count Source Select Bit TCK1 Figure 13 8 TA1MR TA2MR and TA4MR Registers and TB2MR Register Rev 1 10 Jul01 2005 page 125 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Three Phase Motor Control Timer Function The three phase motor control timer function is enabled by setting the INVO2 bit in the INVCO register to 1 When this function i
343. ls and descriptions used for bit function in each register are shown below 1 2 3 4 5 XXX Register b7 b6 b5 b4 b3 b2 bi bO 1 Address Afte Reset XXX Bit Name Function b1b0 0 0 XXX 2 0 1 XXX 1 0 Do not set a value 11 XXX Nothing is assigned When write set to O A When read its content is indeterminate 3 Reserved Bit 4 Function varies depending on mode of operation 0 XXX 1 XXX Blank Set to 0 or 1 according to the application 0 Setto 0 1 Setto 1 X Nothing is assigned RW Read and write RO Read only WO Write only Nothing is assigned Reserved bit Reserved bit Set to specified value Nothing is assigned Nothing is assigned to the bit concerned As the bit may be use for future functions set to 0 when writing to this bit Do not set to this value The operation is not guaranteed when a value is set Function varies depending on mode of operation Bit function varies depending on peripheral function mode Refer to respective register for each mode Follow the text in each manual for binary and hexadecimal notations 3 M16C Family Documents The following documents were prepared for the M16C family Short Sheet Hardware overview Data Sheet Hardware overview and electrical characteristics Hardware Manual Hardware specifications pin assignments memory maps peripheral specifications electrical charact
344. ly are bits O and 1 in the UCON register the U2IRS bit is bit 4 in the U2C1 register 3 If an overrun error occurs the value of UiRB register will be indeterminate The IR bit in SiRIC register does not change Rev 1 10 Jul01 2005 page 163 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM P7 2 CLK2 P7 1 RXD2 P7 O TXD2 Microcomputer Master 14 Serial I O P9 3 P7 2 CLK2 P7 1 RXD2 P7 O TXD2 Microcomputer Slave P9 3 P7 2 CLK2 P7 1 RXD2 P7 O TXD2 Microcomputer Slave Figure 14 27 Serial Bus Communication Control Example UART2 Rev 1 10 Jul01 2005 page 164 of 318 REJO9B0124 0110 ENESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O Table 14 15 Registers to Be Used and Settings in Special Mode 2 Register i 0 to 7 Function Set transmission data 0 to 7 Reception data can be read OER Overrun error flag 0 to 7 Set a transfer rate SMD2 to SMDO Set to 001b CKDIR Set this bit to 0 for master mode or 1 for slave mode IOPOL Set to 0 CLK1 CLKO Select the count source for the UiBRG register CRS Invalid because the CRD bit 1 TXEPT Transmit register empty
345. mance outline of T V ver is added Table 1 3 Product List is revised T V ver is added Figure 1 2 Type No Memory Size and Package Characteristics is added Flgure 4 1 SFR Information 1 The value of After Reset in CM2 Register is revised Figure 4 7 SFR Information 7 NOTE 1 is revised Figure 7 4 CM2 Register The value of After Reset is revised Figure 7 13 State Transition in Normal Operation Mode NOTE 7 is revised 9 10 Address Match Interrupt After of 13th line e Note that when using the external bus in 8 bit width no address match interrupts can be used for external areas is deleted Figure 14 37 upper SiC Register NOTE 4 is revised Figure 18 6 COMCTLj and C1MCTLj Registers e RemActive bit Function is revised RspLock bit Bit Name is revised NOTE2 is revised Figure 18 7 COCTLR and C1CTLR Registers upper LoopBack bit The expression of Function is revised BasicCAN bit The expression of Function is revised Figure 18 7 COCTLR and C1CTLR Registers lower e TSPreScale bit Bit Symbol is revised Bit1 BitO is deleted TSReset bit The expression of Function is revised RetBusOff bit The expression of Function is revised RXOnly bit The expression of Function is revised Figure 18 8 COSTR and C1STR Registers upper NOTE 1 is deleted Figure 18 8 COSTR and C1STR Registers lower State LoopBack bit The expression of Function is revised State BasicCAN bit The expression of Function is re
346. mission one of the following conditions can be selected The UiIRS bit 0 transmit buffer empty when transferring data from the UITB register to the UARTi transmit register at start of transmission e The UiIRS bit 21 transfer completed when the serial I O finished sending data from the UARTi transmit register For reception e When transferring data from the UARTi receive register to the UiRB register at completion of reception Error Detection Overrun error 9 This error occurs if the serial I O started receiving the next data before reading the UiRB register and received the 7th bit of the next data Select Function i Oto2 NOTES CLK polarity selection Transfer data input output can be selected to occur synchronously with the rising or the falling edge of the transfer clock LSB first MSB first selection Whether to start sending receiving data beginning with bit 0 or beginning with bit 7 can be selected Continuous receive mode selection Reception is enabled immediately by reading the UiRB register Switching serial data logic This function reverses the logic value of the transmit receive data Transfer clock output from multiple pins selection UART1 The output pin can be selected in a program from two UART1 transfer clock pins that have been set Separate CTS RTS pins UARTO CTSO and RTSO are input output from separate pins 1 When an external clock is selected the conditions must be met whil
347. mmer Standard serial I O mode 1 Clock synchronous serial I O Standard serial I O mode 2 UART The boot ROM and user ROM areas are rewritten using a dedicated parallel programmer The user ROM area is rewritten busing a dedicated CAN programmer Areas which can be Rewritten User ROM area User ROM area User ROM area Boot ROM area User ROM area Operation Mode Single chip mode Boot mode EWO mode Boot mode Parallel l O mode Boot mode ROM Programmer NOTES None Serial programmer Parallel programmer CAN programmer 1 The PM13 bit remains set to 1 while the FMRO1 bit in the FMRO register 1 CPU rewrite mode enabled The PM13 bit is reverted to its original value by setting the FMRO1 bit to 0 CPU rewrite mode disabled However if the PM13 bit is changed during CPU rewrite mode its changed value is not reflected until after the FMRO1 bit is set to 0 2 When in CPU rewrite mode the PM10 and PM13 bits in the PM1 register are set to 1 The rewrite control program can only be executed in the internal RAM area 3 When using the standard serial I O mode 2 make sure a main clock input oscillation frequency is set to 5 MHz 10 MHz or 16 MHz Rev 1 10 Jul 01 2005 page 238 of 318 REJO9B0124 0110 ENESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Fla
348. mple program BSET 0 CM1 Stop mode JMP B L1 L1 Program after exiting stop mode 20 3 4 12 Low Power Dissipation Mode and On chip Oscillator Low Power Dissipation Mode If the CMO5 bit is set to 1 main clock stopped do not execute the following commands Program Block erase Erase all unlocked blocks Lock bit program software command Read lock bit status Rev 1 10 Jul01 2005 page 249 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Flash Memory Version 20 3 5 Software Commands Software commands are described below The command code and data must be read and written in 16 bit unit to and from even addresses in the user ROM area When writing command code the high order 8 bits D15 to D8 are ignored Table 20 4 lists the software commands Table 20 4 Software Commands First Bus Cycle Second Bus Cycle Software Command Data Data Address D15 to DO Mode Address D15 to DO Read Array Read Status Register Clear Status Register Program Block Erase Erase All Unlocked Block Lock Bit Program Read Lock Bit Status SRD data in SRD register D7 to DO WA Address to be written The address specified in the first bus cycle is the same even address as the address specified in the second bus cycle WD 16 bit write data BA Highest order block address must be an even address X An
349. n 2 Symbol After Reset CANO 1 Wake up Interrupt Control Register CO1WKIC XXXXX000b CANO Successful Reception Interrupt Control Register CORECIC XXXXX000b CANO Successful Transmission Interrupt Control Register COTRMIC XXXXX000b INT3 Interrupt Control Register INT3IC XX00X000b Timer B5 Interrupt Control Register TB5IC SI O5 Interrupt Control Register 1 S5IC XXXXX000b Timer B4 Interrupt Control Register TB4IC UART1 Bus Collision Detection Interrupt Control Register U1BCNIC XXXXX000b Timer B3 Interrupt Control Register TB3IC UARTO Bus Collision Detection Interrupt Control Register UOBCNIC ue CAN1 Successful Reception Interrupt Control Register C1RECIC SI OA Interrupt Control Register S4IC XX00X000b INT5 Interrupt Control Register INTSIC CAN1 Successful Transmission Interrupt Control Register C1TRMIC SI O3 Interrupt Control Register S3IC XX00X000b INT4 Interrupt Control Register INT4IC UART2 Bus Collision Detection Interrupt Control Register U2BCNIC XXXXX000b DMAO Interrupt Control Register DMOIC XXXXX000b DMA1 Interrupt Control Register DM1IC XXXXX000b CANO 1 Error Interrupt Control Register CO1ERRIC XXXXX000b A D Conversion Interrupt Control Register ADIC Key Input Interrupt Control Register KUPIC XXXXX000b UART2 Transmit In
350. n a program When a maskable interrupt request is accepted the CPU reads interrupt information interrupt number and interrupt request priority level from the address 00000h during the interrupt sequence At this time the IR bit for the accepted interrupt is set to 0 If the address 00000h is read in a program the IR bit for the interrupt which has the highest priority among the enabled interrupts is set to 0 This causes a problem that the interrupt is canceled or an unexpected interrupt request is generated 22 7 2 Setting SP Set any value in the SP USP ISP before accepting an interrupt The SP USP ISP is set to 0000h after reset Therefore if an interrupt is accepted before setting any value in the SP USP ISP the program may go out of control Especially when using NMI interrupt set a value in the ISP at the beginning of the program For the first and only the first instruction after reset all interrupts including NMI interrupt are disabled 22 7 3 NMI Interrupt The NMI interrupt cannot be disabled If this interrupt is unused connect the NMI pin to VCC via a resistor pull up e The input level of the NMI pin can be read by accessing the P8 5 bit in the P8 register Note that the P8 5 bit can only be read when determining the pin level in NMI interrupt routine Stop mode cannot be entered into while input on the NMI pin is low This is because while input on the NMI pin is low the CM10 bit in the CM1 regi
351. n continuously in all blocks except the block A The FMROO bit in the FMRO register indicates whether an auto erase operation has been completed After the completion of an auto erase operation the FMRO7 bit in the FMRO register indicates whether or not the auto erase operation has been completed as expected The lock bit can protect each block from being programmed inadvertently Refer to 20 3 6 Data Protect Function In EW1 mode do not execute this command when the lock bit for any block storing the rewrite control program is set to 1 unlocked or when the FMRO2 bit in the FMRO register is set to 1 lock bit disabled In EWO mode the microcomputer enters read status register mode as soon as an auto erase operation starts The status register can be read The SR7 bit in the status register is set to 0 busy at the same time an auto erase operation starts It is set to 1 ready when an auto erase operation is completed The microcomputer remains in read status register mode until the read array command or read lock bit status command is written Only blocks 0 to 12 can be erased by the erase all unlocked block command The block A cannot be erased Use the block erase command to erase the block A 20 3 5 7 Lock Bit Program Command The lock bit program command sets the lock bit for a specified block to 0 locked By writing xx77h in the first bus cycle and xxDOP to the highest order even address of a block in
352. n some instructions A1 and AO can be combined for use as a 32 bit address register A1A0 Rev 1 10 Jul01 2005 page 10 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 2 Central Processing Unit CPU 2 3 Frame Base Register FB FB is configured with 16 bits and is used for FB relative addressing 2 4 Interrupt Table Register INTB INTB is configured with 20 bits indicating the start address of an interrupt vector table 2 5 Program Counter PC PC is configured with 20 bits indicating the address of an instruction to be executed 2 6 User Stack Pointer USP Interrupt Stack Pointer ISP Stack pointer SP comes in two types USP and ISP each configured with 16 bits Your desired type of stack pointer USP or ISP can be selected by the U flag of FLG 2 7 Static Base Register SB SB is configured with 16 bits and is used for SB relative addressing 2 8 Flag Register FLG FLG consists of 11 bits indicating the CPU status 2 8 1 Carry Flag C Flag This flag retains a carry borrow or shift out bit that has occurred in the arithmetic logic unit 2 8 2 Debug Flag D Flag This flag is used exclusively for debugging purpose During normal use it must be set to 0 2 8 3 Zero Flag Z Flag This flag is set to 1 when an arithmetic operation resulted in 0 otherwise it is 0 2 8 4 Sign F
353. n using this function the selected transfer clock should be an external clock Rev 1 10 Jul01 2005 page 162 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O 14 1 4 Special Mode 2 Multiple slaves can be serially communicated from one master Transfer clock polarity and phase are selectable Table 14 14 lists the specifications of Special Mode 2 Figure 14 27 shows communication control example for Special Mode 2 Table 14 15 lists the registers used in Special Mode 2 and the register values set Table 14 14 Special Mode 2 Specifications Specification Transfer data format Transfer data length 8 bits Transfer clock Master mode The CKDIR bit in the UIMR register 0 internal clock fj 2 n 1 fj f1SIO f2SIO f8SIO f32SIO n Setting value of the UiBRG register 00h to FFh Slave mode The CKDIR bit 1 external clock selected Input from CLKi pin Transmit receive control Controlled by input output ports Transmission start condition Before transmission can start the following requirements must be met The TE bit in the UiC1 register 1 transmission enabled The TI bit in the UiC1 register O data present in the UiTB register Reception start condition Before reception can start the following requirements must be met The RE bit in the UiC1 register 1
354. n version supports SI O3 and SI O4 128 pin version supports SI O3 SI O4 SI O5 and SI O6 Clock source select 5 f2SIO PCLK1 0 SMi1 to SMiO O Main clock x UD Data bus PLL clock O or on chip oscillator clock FU PCLK1 1 f8SIO 1 8 01b f32SIO Synchronous 6 SiBRG register SMi6 SI Ci CLK polarity T reversing SI O counter i interrupt circuit request 10b SMi2 SMi3 souti O id SMi5 LSB L MSB SINi OTT SiTRR register 8 i 3 to 6 5 and 6 are only in the 128 pin version n A value set in the SiBRG register Figure 14 36 SI Oi Block Diagram Rev 1 10 Jul01 2005 page 175 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM SI Oi Control Register i 3 to 6 b7 b6 b5 b4 b3 b2 bi b0 Address 01E2h 01E6h 01EAh 01D8h Symbol S3C S4C S5C 6 S6C 6 After Reset 01000000b 01000000b 01000000b 01000000b Bit Name Description b1 bO 0 0 Selecting f1SIO or f2SIO 0 1 Selecting f8SIO 1 0 Selecting f32SIO 1 1 Do not set a value SOUTi output SOUTi output disabled high impedance Internal Synchronous Clock Select Bit SOUTi Output Disable Bit 4 j Input output port S I Qi Port Select Bit 6 SOUTi output CLKi function Transmit data is output at falling edge of transfer clock and receive data is input at rising edge Transmi
355. nd Receive Timing in SIM Mode Rev 1 10 Jul01 2005 page 172 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O Figure 14 33 shows the example of connecting the SIM interface Connect TXD2 and RXD2 and apply pull up SIM card Figure 14 33 SIM Interface Connection 14 1 6 1 Parity Error Signal Output The parity error signal is enabled by setting the U2ERE bit in the U2C1 register to 1 The parity error signal is output when a parity error is detected while receiving data This is achieved by pulling the TXD2 output low with the timing shown in Figure 14 32 If the R2RB register is read while outputting a parity error signal the PER bit is set to O and at the same time the TXD2 output is returned high When transmitting a transmission finished interrupt request is generated at the falling edge of the transfer clock pulse that immediately follows the stop bit Therefore whether a parity signal has been returned can be determined by reading the port that shares the RXD2 pin in a transmission finished interrupt service routine Figure 14 34 shows the output timing of the parity error signal a Tf Oy i fat pe yO a clock e RXD2 n ST A DO f D1 D24 D3 D4 f D5 jf De D7 P SP TxD2 NOTE 1 pr RI bitin U2C1 register o L This timing diagram applies to the case where the direct forma
356. ne when timer B2 underflows Interrupt Enable Output Specification Bit Selected by the INVOO bit 2 No three phase control timer functions it 4 Mode Select Bit Three phase control timer function 5 Disables three phase control timer output 5 Output Control Bit Enables three phase control timer output 6 Positive and Negative Phases Concurrent Active Disable Function Enable Bit Enables concurrent active output 1 Disables concurrent active output Positive and Negative Phases Concurrent Active Output Detect Flag Not detected Detected 7 Modulation Mode Triangular wave modulation mode Select 8 Sawtooth wave modulation mode 9 Transfer trigger is generated when the INVO7 Software Trigger Select bitis set to 1 Trigger to the dead time timer Bit is also generated when setting the INVO6 bit to 1 Its value is 0 when read 1 Set the INVCO register after the PRC1 bit in the PRCR register is set to 1 write enable Rewrite the INVOO to INVO2 and INVO6 bits when the timers A1 A2 A4 and B2 stop 2 The INVOO and INVO1 bits are enabled only when the INV11 bit is set to 1 three phase mode 1 The ICTB2 counter is incremented by one every time the timer B2 underflows regardless of INVOO and INVO1 bit settings when the INV11 bit is set to 0 three phase mode 0 When setting the INVO1 bit to 1 set the timer A1 count start flag before the first timer B2 und
357. ng Range Assuming that set value n SIBRG divides the count 00h to FFh WO source by n 1 1 Write to this register while serial I O is neither transmitting nor receiving 2 Use the MOV instruction to write to this register 3 The S5BRG and S6BRG registers are only in the 128 pin version SI Oi Transmit Receive Register i 3 to 6 12 Address 01E0h 01E4h Symbol S3TRR S4TRR After Reset Indeterminate Indeterminate S5TRR 9 01E8h Indeterminate S6TRR 3 01D6h Indeterminate Transmission reception starts by writing transmit data to this register After transmission reception finishes reception data can be read by reading this register 1 Write to this register while serial I O is neither transmitting nor receiving 2 To receive data set the corresponding port direction bit for SINI to 0 input mode 3 The S5TRR and S6TRR registers are only in the 128 pin version 14 Serial I O Figure 14 37 S3C to S6C Registers S3BRG to S6BRG Registers and S3TRR to S6TRR Registers Rev 1 10 Jul01 2005 page 176 of 318 REJO9B0124 0110 7tENESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O SI 03 4 5 6 Transmit Receive Register 1 2 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset S3456TRR 01DAh XXXX0000b SI O3 Transmit Receive 0 During transmission reception RW Complete Flag 1 Transmission reception com
358. ng the MD1 to MDO bits set the CH2 to CHO bits over again using another instruction A D Control Register 1 1 b7 b6 b5 b4 b3 b2 bt b0 Symbol Address After Reset aft fo ADCON1 03D7h 00h A D Sweep Pin Select Bit Invalid in one shot mode A D Operation Mode Set to 0 when one shot mode Select Bit 1 is selected PR 8 bit mode BITS 8 10 Bit Mode Select Bit 10 bit mode Refer to NOTE 2 for ADCON2 VCUT VREF Connect Bit 2 1 VREF connected mw b7 b6 0 O ANEXO and ANEX1 are not used RW External Op Amp 0 1 ANEXO input is A D converted Connection Mode Bit 1 0 ANEX1 input is A D converted 1 1 External op amp connection mode 1 If the ADCON register is rewritten during A D conversion the conversion result will be indeterminate 2 f the VCUT bit is reset from 0 VREF unconnected to 1 VREF connected wait for 1 us or more before starting A D conversion Figure 15 4 ADCONO Register and ADCON1 Register in One shot Mode Rev 1 10 Jul01 2005 page 186 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 A D Converter 15 1 2 Repeat Mode In repeat mode analog voltage applied to a selected pin is repeatedly converted to a digital code Table 15 3 lists the specifications of repeat mode Figure 15 5 shows the ADCONO and ADCON1 registers in repeat mode Table 15 3 Repeat Mode Specifica
359. nitialization mode State Reset 1 UT 0 Sleep ed Hee 1 Pry Reset 1 CCLK3 1 or CCLK7 CAN interface sleep mode A CAN sleep mode ies 0 or CCLK7 0 CCLK3 CCLK7 Bits in CCLKR register Reset Sleep RetBusOff Bits in CICTLR register i 0 1 State Reset State_BusOff Bits in CiSTR register Figure 18 12 Transition Between Operational Modes 18 5 1 CAN Reset Initialization Mode 18 CAN Module CAN operation mode State_Reset 0 when 11 consecutive recessive bits are TEC gt 255 detected 128 times or RetBusOff 1 Bus off state State_BusOff 1 The CAN reset initialization mode is activated upon MCU reset or by setting the Reset bit in the CICTLR register i 0 1 to 1 If the Reset bit is set to 1 check that the State Reset bit in the CiSTR register is set to 1 Entering the CAN reset initialization mode initiates the following functions by the module CAN communication is impossible e When the CAN reset initialization mode is activated during an ongoing transmission in operation mode the module suspends the mode transition until completion of the transmission successful arbitration loss or error detection Then the State Reset bit is set to 1 and the CAN reset initialization mode is activated The CIMCTLj j 0 to 15 CISTR CilCR CilDR CIRECR CiTECR and CiTSR registers are initialized All these registers are locked to prevent CPU modificati
360. nly in the 128 pin version Figures 9 11 to 9 13 show the IFSRO IFSR1 and IFSR2 registers Rev 1 10 Jul01 2005 page 73 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Interrupt Request Cause Select Register 0 b7 b6 b5 b4 b3 b2 bi b0 Symbol IFSRO Bit Symbol IFSROO IFSRO1 IFSRO2 IFSRO3 IFSRO4 IFSRO5 IFSRO6 IFSRO7 Address 01DEh Bit Name Interrupt Request Cause Select Bit 1 Interrupt Request Cause Select Bit 2 Interrupt Request Cause Select Bit 3 Interrupt Request Cause Select Bit 4 Interrupt Request Cause Select Bit 5 Interrupt Request Cause Select Bit 6 Interrupt Request Cause Select Bit 7 Interrupt Request Cause Select Bit 8 After Reset 00h Function 0 CAN1 successful transission 1 SI O3 0 A D conversion 1 Key input 0 CANO 1 wake up or error 1 CANO wake up error or CAN1 wake up error 0 CAN1 successful reception 1 SI O4 0 Timer B5 1 SI O5 0 Timer BO 1 SI O6 0 Timer B3 1 UARTO bus collision detection 0 Timer B4 1 UART1 bus collision detection 9 Interrupt RW 1 When the IFSR16 bit in the IFSR1 register 0 CAN1 successful transmission and SI OS share the vector and interrupt control register When using the CAN1 successful transmission interrupt set the IFSROO bit to 0 CAN1 success
361. o 0 NOTE 1 Not all register bits are described above Set those bits to 0 when writing to the registers in SIM mode Rev 1 10 Jul01 2005 page 171 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O 1 Transmission Transfer clock TE bit in U2C1 register o Write data to U2TB register TI bit in U2C1 register Transferred from U2TB register to UART2 transmit register Parity Stop TXD2 Parity error signal sent back from receiving end An L level returns due to the occurrence of a parity error RXD2 pin level 1 The ievel i is detected by the intertupt routine E TXEPT bitin 1 i The level is U2C0 register o detected by the The IR bit is set to 1 at the idad IR bitin 1 falling edge of transfer clock S2TIC register ngs The above timing diagram applies to the case where data is Set to 0 by an interrupt request acknowledgement or a program transferred in the direct format Mm f TC 16 n 1 fi or 16 n 1 fEXT STPS bit in U2MR register 0 1 stop bit e PRY bit in U2MR register 1 even parity fi frequency of U2BRG count source f1SIO f2SIO f8SIO f32SIO UFORM bit in U2CO register 0 LSB first fEXT frequency of U2BRG count source external
362. o the slot 3 When the interrupt enable bit in the CilCR register of the receiving slot 1 interrupt enabled the CANI successful reception interrupt request is generated and the MBOX bit in the CiSTR register is changed It shows the slot number where the message was stored and the RecSucc bit in the CiSTR register is active 4 Read the message out of the slot after setting the New Data bit to 0 the content of the slot is read or still under processing by the CPU by a program 5 If the NewData bit is set to 0 by a program or the next CAN message is received successfully before the receive request for the slot is canceled the MsgLost bit in the CIMCTLj register is set to 1 message has been overwritten The new received message is transferred to the slot Generating of an interrupt request and change of the CiSTR register are same as in 3 Rev 1 10 Jul01 2005 page 223 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 18 CAN Module 18 15 2 Transmission Figure 18 21 shows the timing of the transmit sequence CTX TrmReq bit TrmActive bit CiMCTLj register SentData bit CANI Successful Transmission Interrupt TrmState bit TrmSucc bit CiSTR register MBOX bit Transmission slot No
363. ock 5 Before entering stop mode be sure to set the CM20 bit in the CM2 register to 0 oscillation stop re oscillation detection function disabled Figure 7 12 State Transition to Stop Mode and Wait Mode Rev 1 10 Jul 01 2005 page 54 of 318 REJO9B0124 0110 ENESAS WAIT CPU operation stopped instruction Wait Mode Interrupt WAIT instruction Wait Mode Interrupt WAIT instruction NA Interrupt WAIT instruction HA Interrupt Wait Mode Wait Mode Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Clock Generating Circuit Main Clock Oscillation On chip Oscillator Clock Oscillation PLL operation mode Hh Speed Made Mn Speed Mode edn Sesso edn Se Mode edn Sneed Mor ode Low Pouer Disspaten Mode CPU clock Y PLCO7 i CPU clock CPU clock CPU clock CPU clock CPU clock CPU clock CPU clock PLL OM11 1 XIN 1 AXINyZ XIN A f XIN 8 XIN 16 Ring f Ring cwo7 o cmo7 0 CM07 0 CM07 0 CMO07 0 CMO07 0 Ring 2 f Ring 1 1 1 1 y 2 CM06 0 9 CM06 0 CM06 0 CM06 0 CM06 1 CM06 0 Ring 4 Ring 4 CM17 0 PLCO7 0 CM17 0 CM17 0 CM17 1 CM17 1 f Ring 8 f Ring 8 CM16 0_ CM11 00 CM16 0 CM16 1 CM16 0 CM16 1 Ring 16 Ring 16 CM04 1 Medium Speed Mode Medium Speed Mode Medium Speed Mode Medium Speed Mode divide by 2 divide by 4
364. oconcooso 133 UORB to U2RB ausacicitaiicis 132 UOSMR to U2SMR s 135 UOSMR to U2SMR2 136 UOSMRS to U2SMR3 136 UOSMR4 to U2SMR4 137 UOTB to U2TB PAPA 132 CON auanacinsen nde niea 135 Jo MU E T 96 W WC dude 81 WDOTS noia 81 Rev 1 10 Jul01 2005 page 318 of 318 RENESAS REJ09B0124 0110 REVISION HISTORY M16C 6N Group M16C 6NK M16C 6NM Hardware Manual Description Rev Date Page Summary 1 00 Sep 30 2004 First edition issued Nov 01 2004 Revised edition issued Revised parts and revised contents are as follows except for expressional change Table 1 2 Performance Outline of M16C 6N Group 128 pin Version M16C 6NM Interrupt Internal interrupt source is revised from 32 sources to 34 sources Table 21 2 Recommended Operating Conditions 1 e lon peak Unit is revised from V to mA Table 21 3 Recommended Operating Conditions 2 NOTE 3 VCC 3 0 0 3 V is revised to VCC 3 3 0 3 V 22 9 1 2 Timer A Event Counter Mode is revised Jul 01 2005 Revised edition issued The contents of product are revised T V ver is added Revised parts and revised contents are as follows except for expressional change Table 1 1 Performance outline of M16C 6N Group 100 pin Version M16C 6NM Performance outline of T V ver is added Table 1 2 Performance outline of M16C 6N Group 128 pin Version M16C 6NN Perfor
365. ode 7 bit transfer data or 110b UART mode 9 bit transfer data Figure 14 6 UOMR to U2MR Registers and UOCO to U2CO Registers Rev 1 10 Jul01 2005 page 133 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM i 14 Serial I O UART j Transmit Receive Control Register 1 j 0 1 b7 b6 b5 b4 b3 b2 bi bO Symbol UOC1 U1C1 03A5h O3ADh Address After Reset 00XX0010b sia SNe Fonon faw 0 Transmission disabled ve Transmit Enable Bit Transmission enabled a Transmit Buffer Empty Flag Data present in the UjTB register No data present in the UjTB register Receive Enable Bit Reception disabled Reception enabled Receive Complete Flag No data present in the UjRB register Data present in the UjRB register Nothing is assigned When write set to O When read their contents are indeterminate Data Logic Select Bit 1 0 Reverse 1 No reverse Error Signal Output Enable Bit 0 Output disabled 1 Output enabled 1 The UjLCH bit is enabled when the SMD2 to SMDO bits in the UjMR register are set to 001b clock synchronous serial I O mode 100b UART mode 7 bit transfer data or 101b UART mode 8 bit transfer data Set this bit to 0 when the SMD2 to SMDO bits are set to 010b 12C mode or 110b UART mode 9 bit trans
366. ode is pulled high Figure19 9 PURO PUR1 and PUR2 Registers Rev 1 10 Jul01 2005 page 235 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 Programmable l O Ports Pull up Control Register 3 128 pin version b7 b6 b5 b4 b3 b2 bi bO Symbol After Reset PUR3 00h ae Unusable 2 1 The pin for which this bit is 1 pulled high and the direction bit is 0 input mode is pulled high 2 If the PU37 bit is set to 0 unusable the P11 to P14 regisrers are set to 00h Figure19 10 PUR3 Register Port Control Register b7 b6 b5 b4 b3 b2 bi bO Address After Reset 03FFh 00h Bit Symbol Operation performed when the P1 register is read 0 When the port is set for input the input levels of P1 0 to P1 7 pins Port P1 Control Bit are read When set for output the port latch is read The port latch is read regardless of whether the port is set for input or output Nothing is assigned When write set to O When read their contents are 0 Figure19 11 PCR Register Rev 1 10 Jul 01 2005 page 236 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 Programmable 1 O Ports Table 19 2 Unassigned Pin Handling Ports PO to P7 P8 0 to P8 4 After setting for input mode
367. of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Three Phase Motor Control Timer Function 13 Three Phase Motor Control Timer Function Timers A1 A2 A4 and B2 can be used to output three phase motor drive waveforms Table 13 1 lists the specifications of the three phase motor control timer function Figure 13 1 shows the block diagram for three phase motor control timer function Also the related registers are shown on Figures 13 2 to 13 8 Table 13 1 Three Phase Motor Control Timer Function Specifications Three Phase Waveform Output Pin Specification Six pins U U V V W W Forced Cutoff Input Input L to NMI pin Used Timers Timer A4 A1 A2 used in the one shot timer mode Timer A4 U and U phase waveform control Timer A1 V and V phase waveform control Timer A2 W and W phase waveform control Timer B2 used in the timer mode Carrier wave cycle control Dead time timer 3 eight bit timer and shared reload register Dead time control Output Waveform Triangular wave modulation Sawtooth wave modification Enable to output H or L for one cycle Enable to set positive phase level and negative phase level respectively Carrier Wave Cycle Triangular wave modulation count source X m1 X 2 Sawtooth wave modulation count source X m1 m Sett
368. of a measurement pulse is input or timer Bi is overflowed The factor of interrupt request can be determined by use of the MR3 bit in the TBiMR register within the interrupt routine If the source of interrupt cannot be identified by the MR3 bit such as when the measurement pulse input and a timer overflow occur at the same time use another timer to count the number of times Timer B has overflowed To set the MR3 bit to 0 no overflow set the TBiMR register with setting the TBiS bit to 1 and counting the next count source after setting the MR3 bit to 1 overflow Use the IR bit in the TBilC register to detect only overflows Use the MR3 bit only to determine the interrupt factor within the interrupt routine When a count is started and the first effective edge is input an indeterminate value is transferred to the reload register At this time Timer Bi interrupt request is not generated A value of the counter is indeterminate at the beginning of a count The MR3 bit may be set to 1 and Timer Bi interrupt request may be generated between a count start and an effective edge input For pulse width measurement pulse widths are successively measured Use program to check whether the measurement result is an H level width or an L level width Rev 1 10 Jul01 2005 page 295 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N
369. ogram operation starts It is set to 1 when auto program operation is completed The microcom puter remains in read status register mode until the read array command is written After completion of an auto program operation the status register indicates whether or not the auto program operation has been completed as expected Start Write the command code xx40h to an address to be the written Write data to an address to be written Full status check Program operation is completed NOTE 1 Write the command code and data to even addresses Figure 20 8 Program Command Rev 1 10 Jul01 2005 page 251 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Flash Memory Version 20 3 5 5 Block Erase Command The block erase command erases each block By writing xx20h in the first bus cycle and xxDOP to the highest order even address of a block in the second bus cycle an auto erase operation erase and verify will start in the specified block The FMROO bit in the FMRO register indicates whether an auto erase operation has been completed The FMROO bit is set to 0 busy during auto erase and to 1 ready when the auto erase operation is completed After the completion of an auto erase operation the FMRO7 bit in the FMRO register indicates whether or not the auto erase operation has been comple
370. ommand is being executed otherwise it is set to 1 20 3 7 2 Erase Status SR5 and FMRO7 Bits Refer to 20 3 8 Full Status Check 20 3 7 3 Program Status SR4 and FMRO6 Bits Refer to 20 3 8 Full Status Check Rev 1 10 Jul01 2005 page 255 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Table 20 5 Status Register Bits in Status Register Bits in FMRO Register Status Name Sequencer status 20 Flash Memory Version Contents Busy Ready Value after Reset Reserved Erase status Terminated normally Terminated in error Program status Terminated normally Terminated in error Reserved Reserved Reserved Reserved D7 to DO These data bus are read when the read status register command is executed NOTE 1 The FMRO7 bit SR5 and FMRO6 bit SR4 are set to 0 by executing the clear status register command When the FMRO7 bit SR5 or FMRO6 bit SR4 is set to 1 the program block erase erase all unlocked block and lock bit program commands are not accepted Rev 1 10 Jul01 2005 page 256 of 318 REJO9B0124 0110 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 3 8 Full Status Check If an error occurs when a program or
371. on Figure 9 10 Interrupts Priority Select Circuit Rev 1 10 Jul01 2005 page 72 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 9 Interrupt 9 6 INT Interrupt INTI interrupt i 0 to 8 is triggered by the edges of external inputs The edge polarity is selected using the IFSR10 to IFSR15 bits in the IFSR1 register and the IFSR23 to IFSR25 bits in the IFSR2 register INT4 share the interrupt vector and interrupt control register with CAN1 successful transmission and Sl O3 INT5 share with CAN1 successful reception and SI O4 INT6 share with Timer A3 INT7 share with Timer A2 INT8 share with Timer B1 To use the INT4 to INT8 interrupts set the each bits as follows To use the INT4 interrupt Set the IFSR16 bit in the IFSR1 register to 1 INT4 To use the INT5 interrupt Set the IFSR17 bit in the IFSR1 register to 1 INT5 To use the INT6 interrupt Set the IFSR21 bit in the IFSR2 register to 1 INT6 To use the INT7 interrupt Set the IFSR20 bit in the IFSR2 register to 1 INT7 To use the INT8 interrupt Set the IFSR22 bit in the IFSR2 register to 1 INT8 After modifying the IFSR16 IFSR17 IFSR20 IFSR21 and IFSR22 bits set the corresponding IR bit to 0 interrupt not requested before enabling the interrupt NOTE 1 INT6 to INT8 interrupts are o
372. on The CICTLR CiCONR CiGMR CiLMAR and CiLMBR registers and the CANi message box retain their contents and are available for CPU access Rev 1 10 Jul01 2005 page 213 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 18 CAN Module 18 5 2 CAN Operation Mode The CAN operation mode is activated by setting the Reset bit in the CICTLR register i 0 1 to 0 If the Reset bit is set to 0 check that the State Reset bit in the CiSTR register is set to 0 If 11 consecutive recessive bits are detected after entering the CAN operation mode the module initiates the following functions The module s communication functions are released and it becomes an active node on the network and may transmit and receive CAN messages Release the internal fault confinement logic including receive and transmit error counters The module may leave the CAN operation mode depending on the error counts Within the CAN operation mode the module may be in three different sub modes depending on which type of communication functions are performed Module idle The modules receive and transmit sections are inactive Module receives The module receives a CAN message sent by another node Module transmits The module transmits a CAN message The module may receive its own message simultaneously when the LoopBack bit in the
373. on mode Figure 12 12 shows TAiMR register in pulse width modulation mode Figures 12 13 and 12 14 show examples of how a 16 bit pulse width modulator operates and how an 8 bit pulse width modulator operates respectively Table 12 5 Specifications in Pulse Width Modulation Mode Specification Count Source f1 f2 f8 f32 fC32 Count Operation e Down count operating as an 8 bit or a 16 bit pulse width modulator The timer reloads a new value at a rising edge of PWM pulse and continues counting The timer is not affected by a trigger that occurs during counting 16 bit PWM High level width n fj n set value of the TAi register e Cycle time 279 1 fj fixed fj count source frequency f1 f2 f8 f32 C32 8 bit PWM e High level width n X m 1 fj n set value of the TAi register high order address e Cycle time 29 1 X m 1 fj m set value of the TAi register low order address Count Start Condition The TAIS bit in the TABSR register is set to 1 start counting e The TAIS bit 1 and external trigger input from the TAiIN pin The TAIS bit 1 and one of the following external triggers occurs Timer B2 overflow or underflow Timer Aj overflow or underflow Timer Ak overflow or underflow Count Stop Condition The TAIS bit is set to 0 stop counting Interrupt Request Generation Timing On the falling edge of the PWM pulse TAiIN Pin Function I O port or trigger inpu
374. ondition The ADST bit in the ADCONO register is set to 1 A D conversion starts External trigger retriggerable Input on the ADTRG pin changes state from high to low after the ADST bit is set to 1 A D conversion starts Conversion Speed Per Pin Without sample and hold function 8 bit resolution 49 6AD cycles 10 bit resolution 59 AD cycles With sample and hold function 8 bit resolution 28 AD cycles 10 bit resolution 33 AD cycles NOTES 1 Does not depend on use of sample and hold function 2 0AD frequency must be 10 MHz or less When sample amp hold function is disabled AD frequency must be 250 kHz or more When sample amp hold function is enabled AD frequency must be 1 MHz or more Rev 1 10 Jul01 2005 page 181 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM A D conversion rate selection ees o i T o AAA 1 3 il ADTRG O Software trigger VREFO Port PO group A D trigger y CKSi ckso 15 A D Converter Successive conversion register 5 cow register ADO register AD1 register AD2register AD register AD3 register Decoder ADA register AD5 register WA for A D register CH2 to CHO 000b ANO 0O 001b
375. or 1 us or more before starting A D conversion Figure 15 8 ADCONO Register and ADCON1 Register in Repeat Sweep Mode 1 Rev 1 10 Jul01 2005 page 194 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 A D Converter 15 2 Function 15 2 1 Resolution Select Function The desired resolution can be selected using the BITS bit in the ADCON 1 register If the BITS bit is set to 1 10 bit conversion accuracy the A D conversion result is stored in the bit 0 to bit 9 in the ADi register i 0 to 7 If the BITS bit is set to 0 8 bit conversion accuracy the A D conversion result is stored in the bit O to bit 7 in the ADi register 15 2 2 Sample and Hold If the SMP bit in the ADCON register is set to 1 with sample and hold the conversion speed per pin is increased to 28 oAD cycles for 8 bit resolution or 33 HAD cycles for 10 bit resolution Sample and hold is effective in all operation modes Select whether or not to use the sample and hold function before starting A D conversion 15 2 3 Extended Analog Input Pins In one shot and repeat modes the ANEXO and ANEX1 pins can be used as analog input pins Use the OPA1 to OPAO bits in the ADCON1 register to select whether or not use ANEXO and ANEX1 The A D conversion results of ANEXO and ANEX1 inputs are stored in the ADO and AD1 registers respectively 15 2 4 Externa
376. ory must have a program with the ID codes set in these addresses Figure 20 3 shows the ID code store addresses Rev 1 10 Jul01 2005 page 240 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Flash Memory Version ROM Code Protect Control Address b7 b6 b5 b4 b3 b2 bi bO LL Tall komee oem Ems LER 9o Reserved Bit Set to 1 RW b7 b6 00 ROMCP1 ROM Code Protect Level 1 041 Protect enabled RW Set Bit 1 2 3 4 10 1 1 Protect disabled RW 1 If a memory block that including ROMCP register is erased the ROMCP register is set to FFh 2 If the ROMCP1 bit is set to other than 11b ROM code protect enabled the flash memory is disabled against reading and rewriting in parallel l O mode 3 When the ROMCP 1 bit is set to other than 11b set the bit 5 to bit O to 111111b If the bit 5 to bit O are set to other than 111111b ROM code protect function may not become effective even if the RPMCP bit is set to other than 11b 4 When exiting ROM code protect erase the block including the ROMCP register by CPU rewrite mode or standard serial I O or CAN I O mode Figure 20 2 ROMCP Register Address OFFFDFh to OFFFDCh ID1 Undefined instruction vector OFFFESh to OFFFEOh ID2 Overflow vector OFFFE7h to OFFFE4h BRK instruction vector OFFFEBh to OFFFE8h ID3 Address match vector
377. otes re edt 281 22 4 PoWer Controlan reete et ea ey eene ve vi adeo ii 282 22 5 Oscillation Stop Re oscillation Detection Function oooooccccconoccccnccononcnononononnnnnonnno cnn cocoa nnnnnnnnnn rca nnns 284 zoe aAa 285 PANT 286 22 7 1 Reading Address 00000h ssssssssssssssssseeneeene enne neret entier nnne rnnt nnr nene nnn enne 286 ANS SP scettr edere iunc uber ean ved ende BAAD deett Breed aod ean eas 286 A A a 286 22 7 4 Changing Interrupt Generate Factor ooooocconnccccnnociconocaconancnnnnn ccoo cnn nano cnn ano ca nan rara cara rra nnns 287 AA A A 287 22 7 6 Rewrite Interrupt Control Register oooonccccnnncconocccononcccnoncconanncnnanocononn cc a aaa aaa ae aiiai 288 22 7 7 Watchdog Timer Interrupt sertis aaneen a eaea a nnns enne rr rara stets nnns 288 22 9 DMAG on ond LLLI DM 289 22 8 1 Write to DMAE Bit in DMiCON Registe oooooocccnccocccinccconcconcnconnnonncnnncnnnnncon cnn enne enne nnne 289 zr EJ see QN 290 22 9 TIME A Sears cccesecc anes sacccs esac cascacess NIU E MI 290 22 92 TIMO Binaria 294 22 10 Thee Phase Motor Control Timer Function ssssessssssssssese eene eene nnne nennen nnn 296 eed Vy SOMA io Pr E 297 22 11 1 Clock Synchronous Serial l O Mode ococonoccconoccccnocccononcccnnoccnonnnononnno canon nn nn n cnn nennen 297 22 112 Special MOG SS T
378. ox 8 Time Stamp OOF 1h 00F2h O0F3h CANO Message Box 9 Identifier DLC 00F4h OOF5h OOF6h 00F7h 00F8h OOF9h O0FAh CANO Message Box 9 Data Field OOFBh OOFCh OOFDh OOFEh T OOEFh CANO Message Box 9 Time Stamp X Undefined Address OOCOh 00Cih OOC2h O0C3h ee O0C7h OoC8h ooCoh ooCAn OOCBh 00CCh 00D1h 00D2h o0D3h ES 00D7h OoD8h 00D9h ooDAh OODBh ee 00Eth 00E2h O0ESh OoE4h O0E7h OOE8h ooE9h OoFih ooF2n O0F3h ET O0F7h OoFBh ooroh OoFAh O0FBh ES ooFFh Rev 1 10 Jul01 2005 page 16 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 5 SFR Information 5 Symbol AfterReset 0100h 0101h Loan CANO Message Box 10 Identifier DLC 0104h 0105h 0106h 0107h 0108h EIN CANO Message Box 10 Data Field 010Bh 010Ch 010Dh 010Eh
379. pleted SI O4 Transmit Receive 0 During transmission reception Complete Flag 1 Transmission reception completed RW SI O5 Transmit Receive 0 During transmission reception i Complete Flag 1 Transmission reception completed SI O6 Transmit Receive 0 During transmission reception S6TRF Complete Flag 1 Transmission reception completed Nothing is assigned When write set to 0 b7 b4 When read their contents are indeterminate 1 The S3TRF to S6TRF bits can only be reset by writing to 0 The S5TRF and S6TRF bits are only in the 128 pin version 2 When setting the S3TRF to S6TRF bits to 0 use the MOV instruction to write to the these bits after setting to 0 the bit set to 0 and setting other bits to 1 Figure 14 38 S3456TRR Register Rev 1 10 Jul01 2005 page 177 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O Table 14 19 SI Oi Specifications Transfer Data Format Transfer data length 8 bits Transfer clock e SMi6 bit in SiC register 1 internal clock fj 2 n 1 fj AISIO f8SIO f32SIO n Setting value of SiBRG register 00h to FFh e SMi6 bit 0 external clock Input from CLKi pin Transmission Reception Before transmission reception can start the following requirements must be met Start Condition Write transmit data to the SiTRR register Interrupt Request e
380. product data diagrams charts programs algorithms or circuit application examples contained in these materials All information contained in these materials including product data diagrams charts pro grams and algorithms represents information on products at the time of publication of these materials and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons It is therefore recommended that custom ers contact Renesas Technology Corporation or an authorized Renesas Technology Cor poration product distributor for the latest product information before purchasing a product listed herein The information described here may contain technical inaccuracies or typographical errors Renesas Technology Corporation assumes no responsibility for any damage liability or other loss rising from these inaccuracies or errors Please also pay attention to information published by Renesas Technology Corporation by various means including the Renesas Technology Corporation Semiconductor home page http www renesas com When using any or all of the information contained in these materials including product data diagrams charts programs and algorithms please be sure to evaluate all informa tion as a total system before making a final decision on the applicability of the information and products Renesas Technology Corporation assumes no responsibility for any dam age liability or other lo
381. r CANO 1 Clock Select Register CCLKR 41 CAN1 Message Control Register 0 C1MCTLO CAN1 Message Control Register 1 C1MCTL1 CAN1 Message Control Register 2 C1MCTL2 CAN1 Message Control Register 3 C1MCTL3 CAN1 Message Control Register 4 C1MCTL4 CAN1 Message Control Register 5 C1MCTL5 CAN1 Message Control Register 6 C1MCTL6 CAN1 Message Control Register 7 C1MCTL7 CAN1 Message Control Register 8 C1MCTL8 CAN1 Message Control Register 9 C1MCTL9 CAN1 Message Control Register 10 C1MCTL10 CAN1 Message Control Register 11 C1MCTL11 CAN1 Message Control Register 12 C1MCTL12 CAN1 Message Control Register 13 C1MCTL13 CAN1 Message Control Register 14 C1MCTL14 CAN1 Message Control Register 15 0230h CAN1 C1MCTL15 CAN1 Message Box O Identifier DLC 026Ch 026Dh CAN1 Message Box 0 Data Field 026Eh 026Fh CAN1 Message Box 0 Time Stamp 0270h 0271h 0231h Control Register Gesell CAN1 Status Register 0272h 0273h 0233h MESA CAN 1 Slot Status Register 0274h 0275h CAN1 Message Box 1 Identifier DLC 0235h 0236h 0276h 0277h 0237h CAN Interrupt Control Register 0238h 0278h 0279h 0239h CAN1 Extended ID Register En CAN1 Configuration Register 027Ah 027Bh 023Ch CAN1 Receive Error Count Register 023Dh CAN1 Transmit Error Count Register CAN1 Message Box
382. r PC bO b15 bO User Stack Pointer USP Interrupt Stack Pointer ISP Static Base Register SB Flag Register FLG Figure 5 3 CPU Register Status After Reset Rev 1 10 Jul01 2005 page 31 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 6 Processor Mode 6 Processor Mode Three processor mode is available single chip mode only Figures 6 1 and 6 2 show the processor mode related registers Figure 6 3 shows the memory map Processor Mode Register 0 b7 b6 b5 b4 b3 b2 bi bO o e o o o o o Sio o3 2 b1bO 0 0 Single chip mode Mm Processor Mode Bit aw 01 10 Do not set a value 11 Reserved Bit Set to 0 m Setting this bit to 1 resets the Software Reset Bit microcomputer When read its content is 0 hib Je ie NOTE 1 Write to this register after setting the PRC1 bit in the PRCR register to 1 write enable 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 J Figure 6 1 PMO Register Rev 1 10 Jul01 2005 page 32 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 6 Processor Mode Processor Mode PERIE 10 b7 b6 b5 b4 b3 b2 bi IEIEEUBNIE Symbol Address After Reset PM1 0005h 00001000b Bit Symbol 0 Block A disable
383. r A4 Mode Register 102 125 D A Register 1 199 Timer BO Mode Register 110 112 Timer B1 Mode Register Timer B2 Mode Register 113 115 D A Control Register 199 Timer B2 Special Mode Register 123 Port P14 Control Register 234 UARTO Transmit Receive Mode Register 133 Pull Up Control Register 3 Port PO Register 236 UARTO Bit Rate Generator 132 Port P1 Register UARTO Transmit Buffer Register 132 Port PO Direction Register Port P1 Direction Register UARTO Transmit Receive Control Register 0 133 Port P2 Register UARTO Transmit Receive Control Register 1 134 Port P3 Register UARTO Receive Buffer Register 132 Port P2 Direction Register Port P3 Direction Register UART1 Transmit Receive Mode Register 133 Port P4 Register UART1 Bit Rate Generator 132 Port P5 Register UART1 Transmit Buffer Register 132 Port P4 Direction Register Port P5 Direction Register UART1 Transmit Receive Control Register 0 133 Port P6 Register UART1 Transmit Receive Control Register 1 134 Port P7 Register UART1 Receive Buffer Register 132 UART Transmit Receive Control Register 2 Port P6 Direction Register Port P7 Direction Register Port P8 Register Port P9 Register Port P8 Direction Register Port P9 Direction Register Port P10 Register Port P11 Register Port P10 Direction Register Port P11 D
384. r are set to 00h while operating as an 8 bit pulse width modulator Figure 12 4 TAOMR to TA4MR Registers and TAO to TA4 Registers Rev 1 10 Jul01 2005 page 95 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 Timers Count Start Flag b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset TABSR 0380h 00h E a 1 Starts counting Up Down Flag b7 b6 b5 b4 b3 b2 bi Address After Reset 0384h 00h TAOUD Timer AO Up Down Flag 0 Down count TA1UD Timer A1 Up Down Flag UP count TA2UD Timer A2 Up Down Flag Enabled by setting the MR2 bit in the TAIMR register to 0 Tos Tuners Up Down Flag switching source in UDF register TA4UD Timer A4 Up Down Flag during event counter mode TA2P Timer A2 Two Phase Pulse 0 Two phase pulse signal Signal Processing Select Bit processing disabled 1 Two phase pulse signal TA3P Timer A3 Two Phase Pulse processing enabled 2 3 Signal Processing Select Bit Timer A4 Two Phase Pulse TA4P Signal Processing Select Bit 1 Use the MOV instruction to write to this register 2 Make sure the port direction bits for the TA2IN to TA4IN and TA20UT to TA4OUT pins are set to 0 input mode 3 When not using the two phase pulse signal processing function set the corresponding bit to timer A2 to timer A4 to 0 Figure 12 5 TABSR Register and UDF Register Rev 1 10 Jul
385. r externally Figure 7 9 Examples of Main Clock Connection Circuit Rev 1 10 Jul01 2005 page 43 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Clock Generating Circuit 7 1 2 Sub Clock The sub clock is generated by the sub clock oscillation circuit This clock is used as the clock source for the CPU clock as well as the timer A and timer B count sources In addition an fC clock with the same frequency as that of the sub clock can be output from the CLKOUT pin The sub clock oscillator circuit is configured by connecting a crystal resonator between the XCIN and XCOUT pins The sub clock oscillator circuit contains a feedback resistor which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip The sub clock oscillator circuit may also be configured by feeding an externally generated clock to the XCIN pin Figure 7 10 shows the examples of sub clock connection circuit After reset the sub clock is turned off At this time the feedback resistor is disconnected from the oscilla tor circuit To use the sub clock for the CPU clock set the CMO7 bit in the CMO register to 1 sub clock after the sub clock becomes oscillating stably During stop mode all clocks including the sub clock are turned off Refer to 7 4 Power Control Microcomputer Microcomputer
386. r ladder helping to reduce the power consumption of the chip The A D conversion result is stored in the ADi register s bits for ANi ANO i and AN2 i pins i 0 to 7 Table 15 1 shows the performance of the A D converter Figure 15 1 shows the block diagram of the A D converter and Figures 15 2 and 15 3 show the A D converter related registers Table 15 1 A D Converter Performance Method of A D Conversion Successive approximation capacitive coupling amplifier Analog Input Voltage OV to AVCC VCC Operating Clock AD fAD divide by 2 of fAD divide by 3 of fAD divide by 4 of fAD divide by 6 of fAD divide by 12 of fAD Resolution 8 bits or 10 bits selectable Integral Nonlinearity Error When AVCC VREF 5 V With 8 bit resolution 2LSB With 10 bit resolution ANO to AN7 input ANO 0 to ANO 7 input and AN2 0 to AN2 7 input 3LSB ANEXO and ANEX1 input including mode in which external operation amp is selected 7LSB When AVCC VREF 3 3 V With 8 bit resolution 2LSB With 10 bit resolution ANO to AN7 input ANO 0 to ANO 7 input and AN2 0 to AN2 7 input 5LSB ANEXO and ANEX1 input including mode in which external operation amp is selected 7LSB Operating Modes One shot mode repeat mode single sweep mode repeat sweep mode 0 and repeat sweep mode 1 Analog Input Pins 8 pins ANO to AN7 2 pins ANEXO and ANEX1 8 pins ANO 0 to ANO 7 4 8 pins AN2 0 to AN2 7 A D Conversion Software trigger Start C
387. r the FMROO bit in the FMRO register is set to 1 ready Figure 20 11 shows a flow chart of the read lock bit status command programming Write the command code xx71h Write xxDOh to the highest order block address YES Block is locked Block is not locked 1 Write the command code and data to even addresses Figure 20 11 Read Lock Bit Status Command Rev 1 10 Jul01 2005 page 254 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Flash Memory Version 20 3 6 Data Protect Function Each block in the flash memory has a nonvolatile lock bit The lock bit is enabled by setting the FMRO2 bit in the FMRO register to 0 lock bit enabled The lock bit allows each block to be individually protected locked against program and erase This helps prevent data from being inadvertently written to or erased from the flash memory When the lock bit status is set to 0 the block is locked block is protected against program and erase When the lock bit status is set to 1 the block is not locked block can be programmed or erased The lock bit status is set to 0 locked by executing the lock bit program command and to 1 unlocked by erasing the block The lock bit status cannot be set to 1 by any commands The lock bit status can be read by the read lock bit status command The
388. r to 1 with wait state 2 Set the FMRO1 bit to 1 immediately after setting it to 0 Do not generate an interrupts or DMA transfer between setting the bit to 0 and setting it to 1 Set the bit to 0 if setting to 0 Set this bit in a space other than the flash memory while the NMI pin is held H 3 Exit CPU rewrite mode after executing the read array command 4 When CPU rewrite mode is exited while the FMROS bit is set to 1 the user ROM area can be accessed 5 When in CPU rewrite mode the PM10 and PM13 bits in the PM1 register are set to 1 The rewrite control program can only be executed in the internal RAM area Figure 20 5 Setting and Resetting of EWO Mode Procedure to enter EW1 mode Program in the ROM Single chip mode 1 Set CMO CM1 and PM1 registers 2 Set the FMRO1 bit to 1 CPU rewrite mode enabled after writing O Set the FMR11 bit to 1 EW1 mode after writing 0 EW1 mode 3 Execute the software commands Set the FMRO1 bit to O CPU rewrite mode disabled NOTES 1 In EW1 mode do not enter the boot mode 2 In CPU rewrite mode set the CMO6 bit in the CMO register and the CM17 to CM16 bits in the CM1 register to CPU clock frequency of 10 0 MHz or less Set the PM17 bit in the PM1 register to 1 with wait state 3 Set the FMRO1 bit to 1 immediately after setting it to 0 Do not generate an interrupt or a DMA transfer between setting the bit to 0 and setting it to
389. r to the user s manual of your CAN programmer to handle pins controlled by a CAN programmer P6 7 TXD1 P6 5 CLK1 CAN transceiver P9 5 CRXO P9 6 CTXO NOTES 1 Control pins and external circuitry will vary according to programmer For more information refer to the programmer manual 2 In this example modes are switched between single chip mode and CAN I O mode by controlling the CNVSS input with a switch Figure 20 19 Circuit Application in CAN I O Mode Rev 1 10 Jul01 2005 page 268 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Electric Characteristics 21 Electrical Characteristics Table 21 1 Absolute Maximum Ratings Parameter Condition Rated Value Supply Voltage VCC1 VCC2 0 3 to 6 5 Analog Supply Voltage 0 3 to 6 5 Input RESET CNVSS BYTE 0 3 to VCC 0 3 Voltage PO Oto PO 7 P1 Oto P1 7 P2_0 to P2 7 P3_0 to P3 7 P4 O0 to P4 7 P5 Oto P5 7 P6 0to P6 7 P7 0 P7 2to P7 7 P8 OtoP8 7 P9 0 P9 2to P9 7 P10 0 to P10 7 P11 OtoP11 7 P12 Oto P12 7 P13 OtoP13 7 P14 0 P14 1 VREF XIN P7 1 P9 1 0 3 to 6 5 PO Oto PO 7 P1 Oto P1 7 P2 Oto P2 7 0 3 to VCC 0 3 P3_0 to P3 7 P4_0 to P4 7 P5 Oto P5 7 P6 0to P6 7 P7 0 P7 2to P7 7 P8 0 to P8 4 P8 6 P8 7 P9 0 P9 2to P9 7 P10 0toP10 7 P11 OtoP11 7 P12 OtoP12 7 P13 0 to P13 7 P14 O0 P14 1 XOUT P7 1 P9 1 0 3 to 6 5
390. ransfers will occur before writing 1 after writing 0 4 Write to this bit from a program in oth er than the flash memory 5 Effective when the FMRO1 bit 1 CPU rewrite mode If the FMRO1 bit 0 although the FMSTP bit can be set to 1 by writing 1 in a program the flash memory is neither placed in low power dissipation state nor initialized 6 This bit is set to 0 by executing the clear status command Flash Memory Control Register 1 b7 b6 b5 b4 b3 b2 bi bO Symbol FMR1 Bit Symbol b0 Address 01B5h After Reset 0X00XX0Xb Bit Name Function Reserved Bit EW1 Mode Select Bit 1 The value in this bit when read is indeterminate 0 EWO mode 1 EW1 mode Reserved Bit The value in this bit when read is indeterminate FMR16 b7 Write to this bit when the NMI pin is in Reserved Bit Lock Bit Status Flag Set to 0 0 Lock 1 Unlock Reserved Bit Set to 0 1 To set this bit to 1 write 0 and then 1 in succession when the FMRO1 bit in the FMRO register 1 Make sure no interrupts or no DMA transfers will occur before writing 1 after writing O the high state The FMRO1 and FMR11 bits both are set to 0 by setting the FMRO 1 bit to 0 Figure 20 4 FMRO Register and FMR Rev 1 10 Jul 01 2005 page 244 of 318 REJO9B0124 0110 1 Register 7tENESAS Under development This document is under development and its contents are subject to change M
391. rated clock to the XIN pin Figure 7 9 shows the examples of main clock connection circuit After reset the main clock divided by 8 is selected for the CPU clock The power consumption in the chip can be reduced by setting the CMO5 bit in the CMO register to 1 main clock oscillator circuit turned off after switching the clock source for the CPU clock to a sub clock or on chip oscillator clock In this case XOUT goes H Furthermore because the internal feedback resis tor remains on XIN is pulled H to XOUT via the feedback resistor Note that if an externally generated clock is fed into the XIN pin the main clock cannot be turned off by setting the CMO5 bit to 1 unless the sub clock is selected as a CPU clock If necessary use an external circuit to turn off the clock During stop mode all clocks including the main clock are turned off Refer to 7 4 Power Control Microcomputer Microcomputer Built in feedback resistor Built in feedback resistor XIN XOUT XIN XOUT Open Externally derived clock VSS NOTE 1 Place a damping resistor if required The resistance will vary depending on the oscillator and the oscillation drive capacity setting Use the value recommended by each oscillator the oscillator manufacturer When the oscillation drive capacity is set to low check that oscillation is stable Also place a feedback resistor between XIN and XOUT if the oscillator manufacturer recommends placing the resisto
392. rbitration lost is detected Set to 0 STAC Set to 0 Set this bit to 1 to initialize UARTI at start condition detection SWC2 Set this bit to 1 to have SCLi output forcibly pulled low SDHI Set this bit to 1 to disable SDAi output 7 Set to 0 0 2 4 and NODC Set to 0 CKPH See Table 14 12 IC Mode Functions DL2 to DLO Set the amount of SDAi digital delay STAREQ Set this bit to 1 to generate start condition Set to 0 RSTAREQ Set this bit to 1 to generate restart condition Set to 0 STPREQ Set this bit to 1 to generate stop condition Set to 0 STSPSEL Set this bit to 1 to output each condition Set to 0 ACKD Select ACK or NACK ACKC Set this bit to 1 to output ACK data SCLHI Set this bit to 1 to have SCLi output stopped when stop condition is detected Set to 0 SWC9 Set to 0 Set this bit to 1 to set the SCLi to L hold at the falling edge of the 9th bit of clock IFSRO6 ISFRO7 Set to 1 i Oto2 NOTES UOIRS U1IRS Invalid 2to7 Set to 0 1 Not all register bits are described above Set those bits to 0 when writing to the registers in IC mode 2 Set the bit 4 and bit 5 in the UOC1 and U1C1 registers to 0 The UOIRS U1IRS UORRM and U1RRM bi
393. rding to the STAREQ Output of start stop condition is RSTAREQ and STPREQ bits accomplished by a program using ports not automatically generated in hardware Start Stop Condition Interrupt Start stop condition detection Finish generating start stop condition Request Generation Timing 1 When slave CKDIR bit 1 external clock STSPSEL bit o SCLi ist 2nd 3rd 4th 5th 96th 7th 8th 9th bit SDAi t Start condition Stop condition detection interrupt detection interrupt 2 When master CKDIR bit 0 internal clock CKPH bit 1 clock delayed STSPSEL bit Set to 1 in Set to 0 in Set to 1 in Set to 0 in a program a program a program a program ist 2nd 3rd 4tlyp5th 6th 7th 8th Oth bit t Set STAREQ bit Set STPREQ bit 1 start Start condition 1 start detection interrupt Stop condition detection interrupt Figure 14 26 STSPSEL Bit Functions 14 1 3 3 Arbitration Unmatching of the transmit data and SDAi pin input data is checked synchronously with the rising edge of SCLi Use the ABC bit in the UiSMR register to select the timing at which the ABT bit in the UiRB register is updated If the ABC bit 0 updated per bit the ABT bit is set to 1 at the same time unmatching is detected during check and is set to O when not detected In cases when the ABC bit is set to 1 if unmatching is detected even once during check the ABT bit is set to 1 unmatching detected
394. register Reception start condition Before reception can start the following requirements must be met The RE bit in the U2C1 register 1 reception enabled Start bit detection Interrupt request generation timing For transmission When the serial I O finished sending data from the U2TB transfer register U2IRS bit 1 For reception When transferring data from the UART2 receive register to the U2RB register at completion of reception Error detection NOTES Overrun error This error occurs if the serial I O started receiving the next data before reading the U2RB register and received the bit one before the last stop bit of the next data Framing error 9 This error occurs when the number of stop bits set is not detected e Parity error During reception if a parity error is detected parity error signal is output from the TXD2 pin During transmission a parity error is detected by the level of input to the RXD2 pin when a transmission interrupt occurs Error sum flag This flag is set to 1 when any of the overrun framing and parity errors is encountered 1 If an overrun error occurs the value of the U2RB register will be indeterminate The IR bit in the S2RIC register does not change 2 A transmit interrupt request is generated by setting the U2IRS bit in the U2C1 register to 1 transmit is completed and U2ERE bit to 1 error signal output after reset Therefore when using S
395. rei eere oe ie rte tl ee 81 A 2 APS 82 SIE Ina e E 87 11 1 1 Effect of Source and Destination Addresses iseseisana inanasan aaa 87 11 1 2 Effect of Software Wall ii dde 87 EASIER 89 Tess DMA GIG cde Ec EPE 90 1TL 4DMA Bequest id Roe tahoe aed ii 90 11 5 Channel Priority and DMA Transfer Timing cooocccnoccconocccnnnocinononcnananononnncnnnnnnnnnn o conan cnc ennne tenen nnne 91 A A A 92 12 1 TIMET Actis A de aia 94 1201 Timer Modein li il iria e EREE 98 121 2 Event Counter Mode cuicos raid 99 121 3 Oneshot Timer Mode siii rai ia 104 12 1 4 Pulse Width Modulation PWM Mode oooococcoccconoccconoccnononccnoncconanononononanann conca nn none cnn nan nn nana nnnannnccns 106 LATINIS P 109 12 21 Timer Mode sisi da iaa 112 12 2 2 IA nennen nnns eaaa en tnt sen aana nennen inn 113 12 2 3 Pulse Period and Pulse Width Measurement Mode sssm ee 114 13 Three Phase Motor Control Timer Function ccccccccccccccnnnnnnnnnnnnnncnnnnnnnnononnnnnnnnnnnnnos 117 A TI PER E Uere t AN 128 EEUU 128 14 1 1 Clock Synchronous Serial VO Mode srine inon e entrare nne nennen nnne 138 14 1 2 Clock Asynchronous Serial I O UART Mode c oococonoccconoccconococonanccnonocononnno nono nonann nn non nc nnne 146 14 1 3 Special Mode T PO Mode ssirinriinin tia 154 iE cel M 163 14 1 5 Sp
396. remented 00h to FFh 1 according to the CAN module s error status 1 The value is indeterminate in bus off state CANI Transmit Error Count Register i 0 1 b7 b0 Symbol Address After Reset C1TECR 023Dh 00h Counter Value i Transmission error counting function The value is incremented or decremented 00h to FFh according to the CAN module s error status CANi Time Stamp Register i 0 1 b8 bo b7 50 Symbol Address After Reset COTSR 021Fh 021Eh 0000h C1TSR 023Fh 023Eh 0000h Time stamp function 0000h to FFFFh Es CANI Acceptance Filter Support Register i 0 1 b15 b8 b7 b0 b7 b0 Symbol Address After Reset C1AFS 0245h 0244h Indeterminate Function Setting Values Write the content equivalent to the standard frame ID of the received message The value is converted standard frame ID when read Standard frame ID Figure 18 11 CORECR C1RECR Registers COTECR C1TECR Registers COTSR C1TSR Registers and COAFS C1AFS Registers Rev 1 10 Jul01 2005 page 212 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 18 5 Operational Modes The CAN module has the following four operational modes e CAN Reset Initialization Mode CAN Operation Mode CAN Sleep Mode CAN Interface Sleep Mode Figure 18 12 shows transition between operational modes MCU Reset Reset 0 CAN reset i
397. rescaler Interrupt Internal 34 sources External 12 sources Software 4 sources Priority level 7 levels Clock Generating Circuit 4 circuits Main clock oscillation circuit Sub clock oscillation circuit On chip oscillator PLL frequency synthesizer Equipped with a built in feedback resistor Oscillation Stop Detection Function Main clock oscillation stop and re oscillation detection function Electrical Characteristics Supply Voltage VCC 3 0 to 5 5V f BCLK 24MHz VCC 4 2 to 5 5V f BCLK 20MHz 1 1 prescaler without software wait 1 1 prescaler without software wait Power Mask ROM Consumption 21mA f BCLK 24MHz PLL operation no division Flash Memory 23mA f BCLK 24MHz 21mA f BCLK 20MHz PLL operation no division PLL operation no division Mask ROM Flash Memory 3pA f BCLK 32kHz Wait mode Oscillation capacity Low 0 8pA Stop mode Topr 25 C Flash Memory Version Program Erase Supply Voltage 3 0 0 3V or 5 0 0 5V 5 0 0 5V Program and Erase Endurance 100 times 1 0 Characteristics I O Withstand Voltage 5 0V Output Current 5mA Operating Ambient Temperature 40 to 85 C T version 40 to 85 C V version 40 to 125 C option Device Configuration CMOS high performance silicon gate Package NOTES 128 pin plastic mold LQFP 1 PC bus is
398. ripheral function clocks stop operating so that only the peripheral functions clocked by external signals can be used to exit wait mode Table 7 5 lists the interrupts to exit wait mode Rev 1 10 Jul01 2005 page 50 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Clock Generating Circuit Table 7 5 Interrupts to Exit Wait Mode CMO2 Bit 0 CM02 Bit 1 NMI Interrupt Can be used Can be used Serial I O Interrupt Can be used when operating with Can be used when operating with internal or external clock external clock Key Input Interrupt Can be used Can be used A D Conversion Interrupt Can be used in one shot mode or Do not use single sweep mode Timer A Interrupt Can be used in all modes Can be used in event counter mode Timer B interrupt or when the count source is fc32 INT Interrupt Can be used Can be used CANO 1 Wake up Interrupt Can be used in CAN sleep mode Can be used in CAN sleep mode If the microcomputer is to be moved out of wait mode by a peripheral function interrupt set up the following before executing the WAIT instruction 1 Set the ILVL2 to ILVLO bits in the interrupt control register for peripheral function interrupts used to exit wait mode The ILVL2 to ILVLO bits in all other interrupt control registers for peripheral function interrupts not used to exit wait mode are
399. rmine which interrupt source is requesting the interrupt 3 to 6 cycles lt duration for setting up 1 3 to 6 cycles lt duration for holding 1 Duration for Duration for setting up holding SCLi SDAi Start condition SDAi Stop condition i Oto2 NOTE 1 When the PCLK1 bit in the PCLKR register 1 this is the cycle number of f1SIO and when the PCLK1 bit 0 this is the cycle number of f2SIO Figure 14 25 Detection of Start and Stop Condition 14 1 3 2 Output of Start and Stop Condition A start condition is generated by setting the STAREQ bit in the UISMR4 register i 0 to 2 to 1 start A restart condition is generated by setting the RSTAREQ bit in the UiSMRA register to 1 start A stop condition is generated by setting the STPREQ bit in the UISMR4 register to 1 start The output procedure is described below 1 Set the STAREQ bit RSTAREQ bit or STPREQ bit to 1 start 2 Set the STSPSEL bit in the UISMR4 register to 1 output Table 14 13 and Figure 14 26 show the functions of the STSPSEL bit Rev 1 10 Jul01 2005 page 159 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O Table 14 13 STSPSEL Bit Functions Function STSPSEL Bit 0 STSPSEL Bit 1 Output of SCLi and SDAi Pins Output of transfer clock and Output of a start stop condition data acco
400. rogrammer For more information refer to the programmer manual 2 In this example modes are switched between single chip mode and standard serial 1 0 mode by controlling the CNVSS input with a switch 3 If in standard standard serial I O mode 1 there is a possibility that the user reset signal will go low during standard serial I O mode break the connection between the user reset signal and RESET pin by using for example a jumper switch Figure 20 15 Circuit Application in Standard Serial I O Mode 1 Microcomputer P6_5 CLK1 TXD output t P6_7 TXD1 Monitor output P6_4 RTS1 RXD input P6 6 RXD1 Reset input User reset signal NOTES 1 In this example modes are switched between single chip mode and standard serial I O mode by controlling the CNVSS input with a switch Figure 20 16 Circuit Application in Standard Serial I O Mode 2 Rev 1 10 Jul01 2005 page 263 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Flash Memory Version 20 5 Parallel I O Mode In parallel I O mode the user ROM area and the boot ROM area can be rewritten by a parallel programmer supporting the M16C 6N Group M16C 6NK M16C 6NM Contact your parallel programmer manufacturer for more information on the parallel programmer Refer to the user s manual included with your parallel programmer for instructions 20 5 1 User
401. rsing its bit positions may be read from the CRCD register If operation 4 above is performed subsequently the value written to the CRCIN register 23h 00100011b has its bit positions reversed to become 11000100b The value 1100 0100 0000 0000 0000 0000b derived from that by adding 16 digits and the remainder in 3 1001 0001 1000 1000b which is left in the CRCD register are added the result of which is divided by the generator polynomial using modulo 2 arithmetic The value 0000 1010 0100 0001b 0A41h derived from the remainder by reversing its bit positions may be read from the CRCD register Figure 17 3 CRC Calculation Rev 1 10 Jul01 2005 page 201 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 18 CAN Module 18 CAN Module The CAN Controller Area Network module for the M16C 6N Group M16C 6NK M16C 6NM of microcomputers is a communication controller implementing the CAN 2 0B protocol The M16C 6N Group M16C 6NK M16C 6NM contains two CAN modules which can transmit and receive messages in both standard 11 bit ID and extended 29 bit ID formats Figure 18 1 shows a block diagram of the CAN module External CAN bus driver and receiver are required Data Bus CiCONR Register CiCTLR Register CiGMR Register CilDR Register CIMCTL Register CiLMBR Register A T 1 m M Message Box slot
402. rter Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 A D Converter A D Control Register 0 b7 b6 b5 b4 b3 b2 bi bO E Analog Input Pin Select Bit Invalid in repeat sweep mode 1 E mm AME EAN Mi Select Bit 0 repeats sweep mode 1 ee E qw 1 If the ADCONO register is rewritten during A D conversion the conversion result will be indeterminate A D Control Register 1 A AAA Symbol Address After Reset y HE E EHE P P ADCONI 03D7h oon Bit Symbol When repeat sweep mode 1 is selected b1b0 A D Sweep Pin Select Bit a A o A pins 10 ANO to AN2 3 pins 1 1 ANO to AN3 4 pins 2 A D Operation Mode Set to 1 when repeat sweep Select Bit 1 mode 1 is selected 8 bit mode BITS 8 10 Bit Mode Select Bit 10 bit mode ES Refer to NOTE 2 for ADCON2 VCUT VREF Connect Bit 3 1 VREF connected b7 b6 0 O ANEXO and ANEX1 are not used RW External Op Amp 0 1 D Connection Mode Bit Oniot Sota Va US 1 0 Do not set a value 1 1 External op amp connection mode 1 If the ADCON register is rewritten during A D conversion the conversion result will be indeterminate 2 ANO 0 to AN 7 and AN2 0 to AN2 7 can be used in same way as ANO to AN7 Use the ADGSEL1 to ADGSELO bits in the ADCONe register to select the desired pin 3 If the VCUT bit is reset from 0 VREF unconnected to 1 VREF connected wait f
403. s pin PO Oto PO 7 Input port PO Input H or L level signal or open P1 0to P1 7 Input port P1 Input H or L level signal or open P2 0to P2 7 Input port P2 Input H or L level signal or open P3 Oto P3 7 Input port P3 Input H or L level signal or open P4 0to P4 7 Input port P4 Input H or L level signal or open P5 0 CE input Input H level signal P5 1 to P5 4 P5 6 P5 7 Input port P5 Input H or L level signal or open P5 5 EPM input Input L level signal P6 Oto P6 3 Input port P6 Input H or L level signal or open P6 4 RTS1 BUSY output Standard serial I O mode 1 BUSY signal output pin Standard serial l O mode 2 Monitors the boot program operation check signal output pin P6 5 CLK1 SCLK input Standard serial I O mode 1 Serial clock input pin Standard serial I O mode 2 Input L Pe 6 RXD1 RXD input Serial data input pin Pe 7 TXD1 TXD output Serial data output pin P7_0 to P7_7 Input port P7 Input H or L level signal or open P8_0 to P8 4 P8 6 P8 7 Input port P8 Input H or L level signal or open P8 5 NMI NMI input Connect this pin to VCC1 P9 0 to P9 4 P9 7 Input port P9 Input H or L level signal or open P9 5 CRXO CRX input Input H
404. s 0 to 15 d Protocol Y Y y Controller Acceptance Filter slots 0 to 15 Message ID P 168i Timer DLC Message Data CiTSR Register Time Stamp AAA Interrupt 3H Generation S Function a CANI Successful Reception Int CiTECR Register CiSTR Register CiSSTR Register CilCR Register 4 CANI Successful Transmission Int CANO 1 Error Int CANO 1 Wake Up Int Data Bus Figure 18 1 CAN Module Block Diagram CTX CRX CAN I O pins Protocol controller This controller handles the bus arbitration and the CAN protocol services i e bit timing stuffing error status etc Message box This memory block consists of 16 slots that can be configured either as transmitter or receiver Each slot contains an individual ID data length code a data field 8 bytes and a time stamp Acceptance filter This block performs filtering operation for received messages For the filtering operation the CiIGMR register i O 1 the CiLMAR register or the CILMBR register is used 16 bit timer Used for the time stamp function When the received message is stored in the message memory the timer value is stored as a time stamp Wake up function CANO 1 wake up interrupt request is generated by a message from the CAN bus Interrupt generation function The interrupt requests are generated by the CAN module CANi successful reception interrupt CANi successful transmission interrupt CANO 1 error interrupt and CANO 1 wake up interrupt
405. s are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O 14 1 1 3 LSB First MSB First Select Function Use the UFORM bit in the UiCO register i 0 to 2 to select the transfer format Figure 14 13 shows the transfer format 1 When the UFORM bit in the UiCO register O LSB first CLKi TXDi X Do X D1 X D2 X D3 X D4 X Ds X De X D7 RXDi X Do X D1 X D2 X D3 X D4 X Ds X De X D7 2 When the UFORM bit in the UiCO register 1 MSB first CLKi TXDi X D7 X De X D5 X D4 X D3 X D2 X D1 X DO RXDi X D7 X De X D5 X D4 X D3 X D2 X D1 X DO i Oto2 This applies to the case where the CKPOL bit in the UiCO register 0 transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock and the UiLCH bit in the UiC1 register O no reverse Figure 14 13 Transfer Format 14 1 1 4 Continuous Receive Mode In continuous receive mode receive operation becomes enable when the receive buffer register is read It is not necessary to write dummy data into the transmit buffer register to enable receive operation in this mode However a dummy read of the receive buffer register is required when starting the operation mode When the UiRRM bit i 0 to 2 1 continuous receive mode the TI bit in the UiC1 register is set to 0 data present in UiTB r
406. s document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 5 Reset Recommended operation F voltage VCC OV E 2 0 2VCC or below gt i4 Supply a clock with td P R 20 So or more cycles to the XIN pin NOTE 1 Use the shortest possible wiring to connect external circuit Figure 5 1 Example Reset Circuit e a Me td P R More than 20 cycle are needed RESET BCLK 28cyc BCLK FFFFCh Content of reset vector Y Address FrrFrEh Y Figure 5 2 Reset Sequence Rev 1 10 Jul01 2005 page 30 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Table 5 1 Pin Status When RESET Pin Level is L Status CNVSS VSS PO P1 P2 P3 P4 P5 P6 P7 Input port P8 0 to P8 4 P8 6 P8 7 P9 P10 5 Reset P11 P12 P13 P14 0 P14 18 NOTE 1 P11 P12 P13 P14_0 and P14 1 pins are only in the 128 pin version b15 bO n f Data Register RO n f Data Register R1 n f Data Register R2 Data Register R3 0000h Address Register A0 0000h Address Register A1 0000h Frame Base Register FB b19 00000h Interrupt Table Register INTB Content of addresses FFFFEh to FFFFCh Program Counte
407. s must be relocated to the RAM area The NMI and watchdog timer interrupts are available since the FMRO and FMR1 registers are forcibly reset when either interrupt request is generated Allocate the jump addresses for each interrupt service routines to the fixed vector table Flash memory rewrite operation is aborted when the NMI or watchdog timer interrupt request is generated Execute the rewrite program again after exiting the interrupt routine The address match interrupt is not available since the CPU tries to read data in the flash memory 20 3 4 4 Interrupts EW1 Mode Do not acknowledge any interrupts with vectors in the relocatable vector table or address match interrupt during the auto program or auto erase period Do not use the watchdog timer interrupt e The NMI interrupt is available since the FMRO and FMR1 registers are forcibly reset when the interrupt request is generated Allocate the jump address for the interrupt service routine to the fixed vector table Flash memory rewrite operation is aborted when the NMI interrupt request is generated Execute the rewrite program again after exiting the interrupt service routine 20 3 4 5 How to Access To set the FMRO1 FMRO2 or FMR11 bit to 1 write 1 after first setting the bit to 0 Do not generate an interrupt or a DMA transfer between the instruction to set the bit to 0 and the instruction to set the bit to 1 Set the bit while an H signal is
408. s selected timer B2 is used to control the carrier wave and timers A4 A1 and A2 are used to control three phase PWM outputs U U V V W and W The dead time is controlled by a dedicated dead time timer Figure 13 9 shows the example of triangular modulation waveform and Figure 13 10 shows the example of sawtooth modulation waveform Triangular waveform as a Carrier Wave TB2S bit in TABSR register Timer B2 Timer A1 reload control signal 1 Timer A4 start trigger signal 0 TA4 register 2 TA4 iregisterO Q m XX PX gd Reload register 2 m X m X m X n XmxXxpX pP X T q Timer A4 one shot pulse U phase output Rewrite the IDBO and IDB1 registers signal U phase output signal INV14 0 L active U phase INV14 1 H active INVOO INVO1 Bits in the INVCO register INV11 INV14 Bits in the INVC1 register NOTES 1 Internal signals See Figure 13 1 Three Phase Motor Control Timer Functions Block Diagram 2 Applies only when the INV11 bit is set to 1 three phase mode The above applies to INVCO 00XX11XXb and INVC1 010XXXXOb X varies depending on each system Examples of PWM output change are a When INV11 1 three phase mode 1 b When INV11 0 three phase mode 0 INVO1 0 and ICTB2 2h The timer B2 interrupt is INVO1 0 ICTB2 1h The timer B2 interrupt is generated generated with every second timer B2 underflow or whenever the timer B2 underflows IN
409. se Motor Control Timer Function Timer B2 Interrupt Occurrence Frequency Set Counter 1 2 3 b0 Symbol Address After Reset ICTB2 01CDh Indeterminate When the INVO1 bit in the INVCO register is set to 0 the ICTB2 counter increments whenever the timer B2 underflows and the setting value is n the timer B2 interrupt is generated every nth time timer B2 underflow occurs When the INVO1 bit is set to 1 the INVOO bit selects count timing of the ICTB2 counter and setting value is n the timer B2 interrupt is generated every nth time timer B2 underflow meeting the condition selected in the INVOO bit occurs Nothing is assigned When write set to 0 1 Use the MOV instruction to set the ICTB2 register 2 If the INVO1 bit is set to 1 set the ICTB2 register when the TB2S bit is set to 0 timer B2 counter stopped If the INVO1 bit is set to 0 and the TB2S bit to 1 timer B2 counter start do not set the ICTB2 register when the timer B2 underflows 3 If the INVOO bit is set to 1 the first interrupt is generated when the timer B2 underflows n 1 times n being the value set in the ICTB2 counter Subsequent interrupts are generated every n times the timer B2 underflows Timer B2 Special Mode Register b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset TB2SC 039Eh XXXXXX00b 0 Timer B2 underflow Timer B2 megad Timing 1 Timer A output at odd numbered Switching Bit 2 occurrences Three phase output forcib
410. se Width Table 21 15 Timer A Input External Trigger Input in Pulse Width Modulation Mode Standard Min Max tw TAH TAiIN Input HIGH Pulse Width 100 tw TAL TAiIN Input LOW Pulse Width 100 Table 21 16 Timer A Input Counter Increment decrement Input in Event Counter Mode Standard Min Max Symbol Parameter Parameter ta up TAiOUT Input Cycle Time tw UPH TAiOUT Input HIGH Pulse Width tw UPL TAiOUT Input LOW Pulse Width tsu UP TIN TAiOUT Input Setup Time th TIN uP TAiOUT Input Hold Time Table 21 17 Timer A Input Two phase Pulse Input in Event Counter Mode Standard Min Max Parameter te TA TAiIN Input Cycle Time tsu TAIN Ta0UT TAIOUT Input Setup Time tsuTaouT TAIN TAIN Input Setup Time Rev 1 10 Jul01 2005 page 276 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 21 Electric Characteristics Timing Requirements Referenced to VCC 5V VSS OV at Topr 40 to 85 C unless otherwise specified Table 21 18 Timer B Input Counter Input in Event Counter Mode Standard Min Max Parameter tc TB TBilN Input Cycle Time counted on one edge tw TBH TBilN Input HIGH Pulse Width counted on one edge tw TBL TBilN Input LOW Pulse Width counted on one edge tc TB TBilN Input Cycle Time counted on both edges
411. set LL HEIL Ie ADCON1 03D7h 00h When repeat sweep mode 0 is selected b1b0 00 ANO AN1 2 pi A D Sweep Pin Select Bit p 4 ANO to p um 10 ANO to AN5 6 pins 11 ANO to AN7 8 pins 2 A D Operation Mode Set to 0 when repeat sweep Select Bit 1 mode 0 is selected BITS 8 10 Bit Mode Select Bit 0 Sb mode E Refer to NOTE 2 for ADCON2 VCUT VREF Connect Bit 3 1 VREF connected b7 b6 0 0 ANEXO and ANEX1 are not used RW External Op Amp 0 1 D Connection Mode Bit Onor seta vale 10 Do not set a value 1 1 External op amp connection mode 1 If the ADCON1 register is rewritten during A D conversion the conversion result will be indeterminate 2 ANO_0 to AN 7 and AN2_0 to AN2 7 can be used in same way as ANO to AN7 Use the ADGSEL1 to ADGSELO bits in the ADCON2 register to select the desired pin 3 If the VCUT bit is reset from 0 VREF unconnected to 1 VREF connected wait for 1 us or more before starting A D conversion Figure 15 7 ADCONO Register and ADCON 1 Register in Repeat Sweep Mode 0 Rev 1 10 Jul01 2005 page 192 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 1 5 Repeat Sweep Mode 1 In repeat sweep mode 1 analog voltage selectively applied to all pins is repeatedly converted to a digital code Table 15 6 lists the specifications of repeat sweep mode 1
412. sh Memory Version 20 1 Memory Map The flash memory contains the user ROM area and a boot ROM area The user ROM area has space to store the microcomputer operating program a separate 4 Kbyte space as the block A Figure 20 1 shows the block diagram of flash memory The user ROM area is divided into several blocks each of which can individually be protected locked against programming or erasure The user ROM area can be rewritten in all of CPU rewrite standard serial I O mode parallel I O mode and CAN I O mode Block A is enabled for use by setting the PM10 bit in the PM1 register to 1 block A enabled The boot ROM area is located at the same addresses as the user ROM area It can only be rewritten in parallel I O mode refer to 20 1 1 Boot Mode A program in the boot ROM area is executed after a hardware reset occurs while an H signal is applied to the CNVSS and P5 0 pins and an L signal is applied to the P5 5 pin refer to 20 1 1 Boot Mode A program in the user ROM area is executed after a hardware reset occurs while an L signal is applied to the CNVSS pin However the boot ROM area cannot be read OOFFFFh OOFFFFh Block A 4 Kbytes 080000 Block 12 64 Kbytes O8FFFF 090000 Block 11 64 Kbytes O9FFFF 0A0000 Block 10 64 Kbytes OAFFFF 0B0000 Block 9 64 Kbytes OBFFFF 0C0000 Block 8 64 Kbytes OCFFFF 0D0000 Block 7 64 Kbytes Block 5 32 Kbytes OF7FFFh BEBE ba OF8000h Block 4
413. ss resulting from the information contained herein Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is poten tially at stake Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product con tained herein for any specific purposes such as apparatus or systems for transportation vehicular medical aerospace nuclear or undersea repeater use The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials lf these products or technologies are subject to the Japanese export control restrictions they must be exported under a license from the Japanese government and cannot be im ported into a country other than the approved destination Any diversion or reexport contrary to the export control laws and regulations of Japan and or the country of destination is prohibited Please contact Renesas Technology Corporation for further details on these materials or the products contained therein How to Use This Manual 1 Introduction This hardware manual provides detailed information on the M16C 6N Group M16C 6NK M16C 6NM of microcomputers Users are expected to have basic knowledge of electric circuits logical circuits and microcomputers 2 Register Diagram The symbo
414. ssing operation Rev 1 10 Jul01 2005 page 101 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 Timers Timer Ai Mode Register i 2 to 4 When using two phase pulse signal processing PA Symbol Address After Reset fo 1 ofo TA2MR to TA4MR 0398h to 039Ah 00h ELLE i Tsim i odo v TMODO b1 bo EEN Operation Mode Select Bit TMOD1 O 1 Event counter mode W To use two phase pulse signal processing set this bit to 0 RW W MR2 To use two phase pulse signal processing set this bit to 1 To use two phase pulse signal processing set this bit to 0 R MR3 W Count Operation Type 0 Reload type odd Select Bit 1 Free run type RW Two Phase Pulse Signal N TCK1 Processing Operation 0 Normal processing operation RW Select Bit 1 2 1 Multiply by 4 processing operation 1 The TCK1 bit is valid for the TA3MR register No matter how this bit is set timers A2 and A4 always operate in normal processing mode and x4 processing mode respectively 2 If two phase pulse signal processing is desired following register settings are required Set the TAiP bit in the UDF register to 1 two phase pulse signal processing function enabled Set the TAITGH and TAiTGL bits in the TRGSR register to 00b TAIIN pin input Set the port direction bits for TAIIN and TAiOUT to 0 input mode Figure
415. ster is fixed to 0 Do not go to wait mode while input on the NMI pin is low This is because when input on the NMI pin goes low the CPU stops but CPU clock remains active therefore the current consumption in the chip does not drop In this case normal condition is restored by an interrupt generated thereafter The low and high level durations of the input signal to the NMI pin must each be 2 CPU clock cycles 300 ns or more Rev 1 10 Jul01 2005 page 286 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 7 4 Changing Interrupt Generate Factor If the interrupt generate factor is changed the IR bit of the interrupt control register for the changed interrupt may inadvertently be set to 1 interrupt requested If you changed the interrupt generate factor for an interrupt that needs to be used be sure to set the IR bit for that interrupt to 0 interrupt not requested Changing the interrupt generate factor referred to here means any act of changing the source polarity or timing of the interrupt assigned to each software interrupt number Therefore if a mode change of any peripheral function involves changing the generate factor polarity or timing of an interrupt be sure to set the IR bit for that interrupt to 0 interrupt not requested after making such changes Refer to the descr
416. successfully 0 CAN module is idle or receiver 1 CAN module is transmitter 0 CAN module is idle or transmitter 1 CAN module is receiver 1 These bits can be changed only when a slot which an interrupt is enabled by the CilCR register is transmitted or received successfully Address 0213h 0233h After Reset X0000001b X0000001b 0 Operation mode State Reset Reset State Flag 1 Reset mode HN State _ Loop Back 0 Not Loop back mode LoopBack State Flag 1 Loop back mode State _ Message Order 0 Word access MsgOrder State Flag 1 Byte access State _ Basic CAN Mode BasicCAN State Flag 0 Not Basic CAN mode 1 Basic CAN mode State _ Bus Error 0 No error has occurred BusError State Flag 1 A CAN bus error has occurred State Error Passive 0 CAN module is not in error passive state ErrPass State Flag 1 CAN module is in error passive state Nothing is assigned When read its content is indeterminate b7 Figure 18 8 COSTR and C1STR Registers Rev 1 10 Jul 01 2005 page 209 of 318 REJO9B0124 0110 131 NESAS When write set to 0 State _ Error Bus Off 0 CAN module is not in error bus off state BusOff State Flag 1 CAN module is in error bus off state Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 18 CAN Module CANi Slot Status Register i 0 1 b8 bo b7 b0 Symbol Address After Rese
417. sult of conversion set the DAIE bit in the DACON register to 1 output enabled Before D A conversion can be used the corresponding port direction bit must be set to 0 input mode Setting the DAIE bit to 1 removes a pull up from the corresponding port Output analog voltage V is determined by a set value n decimal in the DAi register V VREF X n 256 n 0 to 255 VREF reference voltage Table 16 1 lists the performance of the D A converter Figure 16 1 shows the block diagram of the D A converter Figure 16 2 shows the D A converter related registers Figure 16 3 shows the D A converter equivalent circuit Table 16 1 D A Converter Performance Performance D A conversion Method R 2R method Resolution 8 bits Analog Output Pin 2 DAO and DA1 Data bus low order DAO register R 2R resistor ladder gt DA1 register DAOE bit R 2R resistor ladder O O DA1 DATE bit Figure 16 1 D A Converter Block Diagram Rev 1 10 Jul01 2005 page 198 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 16 D A Converter D A Control Register b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset DACON 03DCh 00h Brsysbo iWame E A Output disabled DAQE D AO Output Enable Bit Output enabled nw DATE D A1 Output Enable Bit 9 a aren a Nothing is assigned When
418. t TAiOUT Pin Function Pulse output Read from Timer An indeterminate value is read by reading the TAi register Write to Timer i 0to4 j i 1 exceptj 4ifi 0 k i 1 exceptk O ifi 4 When not counting and until the 1st count source is input after counting start Value written to the TAi register is written to both reload register and counter When counting after 1st count source input Value written to the TAi register is written to only reload register Transferred to counter when reloaded next Rev 1 10 Jul01 2005 page 106 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 Timers Timer Ai Mode Register i 0 to 4 b7 b6 b5 b4 b3 b2 bi bO AAA TADMB lo TA4MR eden 6 o n ib un ae Bit Symbol boro TMODO __ Operation Mode A TMOD1 Select Bit 1 1 Pulse width modulation mode 0 Pulse is not output Pulse pid Function TAiOUT pin is a normal port pin Select Bit 3 Pulse is output TAI OUT pin is a pulse output pin s Trigger Select 0 Falling edge of input signal to TAiIN pin 2 Bit 1 1 Rising edge of input signal to TAiIN pin 2 0 Write 1 to TAIS bit in the TABSR register Trigger Select Bit 1 Selected by TAITGH to TAITGL bits 16 8 Bit Pulse Width O Functions as a 16 bit pulse width modulator Modulation Mode Select Bit 1 Functions as an 8 bit pulse width mod
419. t 3 Count down when input on TAiOUT pin is low or count up when input on that pin is high The port direction bit for TAiOUT pin is set to 0 input mode Figure 12 8 TAOMR to TA4MR Registers in Event Counter Mode when not using two phase pulse signal processing Rev 1 10 Jul01 2005 page 100 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 Timers Table 12 3 Specifications in Event Counter Mode when processing two phase pulse signal with timers A2 A3 and A4 Specification Count Source e Two phase pulse signals input to TAiIN or TAiOUT pins Count Operation Up count or down count can be selected by two phase pulse signal When the timer overflows or underflows it reloads the reload register contents and continues counting When operating in free running mode the timer continues counting without reloading Divide Ratio 1 FFFFh n 1 for up count 1 n 1 for down count n set value of the TAi register 0000h to FFFFh Count Start Condition Set the TAIS bit in the TABSR register to 1 start counting Count Stop Condition Set the TAIS bit to 0 stop counting Interrupt Request Generation Timing Timer overflow or underflow TAIIN Pin Function Two phase pulse input TAiOUT Pin Function Two phase pulse input Read from Timer Count value can be read by reading the TAi register Write to Timer When not co
420. t COSSTR 0215h 0214h 0000h C1SSTR 0235h 0234h 0000h 0 Reception slot The message has been read Transmission slot Transmission is not completed Reception slot The message has not been read Transmission slot Transmission is completed Slot status bits Each bit corresponds to the slot with the same number CANI Interrupt Control Register i 0 1 b8 b0 b7 bo Symbol Address After Reset COICR 0217h 0216h 0000h C1ICR 0237h 0236h 0000h Interrupt enable bits 0 Interrupt disabled Each bit corresponds with a slot with the same 1 Interrupt enabled number Enabled disabled of successful transmission interrupt or successful reception interrupt can be selected 1 This register can not be set in CAN reset initialization mode of the CAN module CANi Extended ID Register i 0 1 b8 bO b7 bo Symbol Address After Reset COIDR 0219h 0218h 0000h C1IDR 0239h 0238h 0000h Extended ID bits 0 Standard ID Each bit corresponds with a slot with the same 1 Extended ID number Selection of the ID format that each slot handles 1 This register can not be set in CAN reset initialization mode of the CAN module Figure 18 9 COSSTR C1SSTR Registers COICR C1ICR Registers and COIDR C1IDR Registers Rev 1 10 Jul01 2005 page 210 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 18 CAN Mod
421. t 1 10 bit mode Refer to NOTE 2 for ADCON2 VCUT VREF Connect Bit 3 1 VREF connected b7 b6 0 O ANEXO and ANEX1 are not used RW 0 1 Do not set a value 1 0 Do not set a value 1 1 External op amp connection mode External Op Amp Connection Mode Bit 1 If the ADCON register is rewritten during A D conversion the conversion result will be indeterminate 2 ANO 0 to AN 7 and AN2 0 to AN2 7 can be used in same way as ANO to AN7 Use the ADGSEL1 to ADGSELO bits in the ADCONe register to select the desired pin 3 If the VCUT bit is reset from 0 VREF unconnected to 1 VREF connected wait for 1 us or more before starting A D conversion Figure 15 6 ADCONO Register and ADCON1 Register in Single Sweep Mode Rev 1 10 Jul01 2005 page 190 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 A D Converter 15 1 4 Repeat Sweep Mode 0 In repeat sweep mode 0 analog voltage applied to selected pins is repeatedly converted to a digital code Table 15 5 lists the specifications of repeat sweep mode 0 Figure 15 7 shows the ADCONO and ADCON1 registers in repeat sweep mode 0 Table 15 5 Repeat Sweep Mode 0 Specifications Function Specification The SCAN1 to SCANO bits in the ADCON1 register and the ADGSEL1 to ADGSELO bits in the ADCON register select pins Analog voltage applied to the pins is repeatedly
422. t A D conversion result High order 2 bits of When read the content is A D conversion result indeterminate Nothing is assigned When write set to 0 When read their contents are 0 Figure 15 3 ADCON2 Register and ADO to AD7 Registers Rev 1 10 Jul01 2005 page 184 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 1 Mode Description 15 1 1 One shot Mode In one shot mode analog voltage applied to a selected pin is A D converted once Table 15 2 lists the specifications of one shot mode Figure 15 4 shows the ADCONO and ADCON1 registers in one shot mode Table 15 2 One shot Mode Specifications Specification Function The CH2 to CHO bits in the ADCONO register the ADGSEL1 to ADGSELO bits in the ADCON register and the OPA1 to OPAO bits in the ADCON1 register select a pin Analog voltage applied to the pin is converted to a digital code once A D Conversion Start Condition When the TRG bit in the ADCONO register is 0 software trigger The ADST bit in the ADCONO register is set to 1 A D conversion starts When the TRG bit is 1 ADTRG trigger Input on the ADTRG pin changes state from high to low after the ADST bit is set to 1 A D conversion starts A D Conversion Stop Condition Completion of A D conversion If a software trigger is selected the ADST bit is
423. t Priority Levels Enabled by IPL ILVL2 to ILVLO Bits Interrupt Priority Level Priority Order IPL Enabled Interrupt Priority Levels Level 0 Interrupt disabled Interrupt levels 1 and above are enabled Level 1 Interrupt levels 2 and above are enabled Level 2 Interrupt levels 3 and above are enabled Level 3 Interrupt levels 5 and above are enabled Level 4 Interrupt levels 5 and above are enabled Level 5 Interrupt levels 6 and above are enabled Level 6 Interrupt levels 7 and above are enabled Level 7 i All maskable interrupts are disabled Rev 1 10 Jul01 2005 page 67 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 9 Interrupt 9 5 4 Interrupt Sequence An interrupt sequence what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed is described here If an interrupt request is generated during execution of an instruction the processor determines its priority when the execution of the instruction is completed and transfers control to the interrupt sequence from the next cycle If an interrupt request is generated during execution of either the SMOVB SMOVF SSTR or RMPA instruction the processor temporarily suspends the instruction being executed and transfers control to the interrupt sequence The CPU b
424. t data is output at rising edge of transfer clock and receive data is input at falling edge CLK Polarity Select Bit Transfer Direction Select LSB first Bit MSB first Synchronous Clock Select Bit External clock 2 Internal clock 3 Effective when the SMi3 bit 0 0 L output 1 H output SOUTi Initial Value Set Bit Make sure this register is written to by the next instruction after setting the PRC2 bit in the PRCR register to 1 write enabled Set the SMi3 bit to 1 SOUTi output CLKi function and the corresponding port direction bit to 0 input mode Set the SMi3 bit to 1 SOUTi output CLKi function When the SM32 SM52 or SM62 bit 1 the corresponding pin is placed in the high impedance state regardless of which functions of those pins are being used SI O4 is effective only when the SM43 bit 1 SOUTA output CLK4 function When using SI O4 set the SM43 bit to 1 SOUTA output CLK4 function and the corresponding port direction bit for SOUTA pin to 0 input mode The S5C and S6C registers are only in the 128 pin version When using the S5C and S6C registers set these registers after setting the PU37 bit in the PURS register to 1 Pins P11 to P14 are usable SI Ci Bit Rate Generator i 3 to 6 19 Address 01E3h 01E7h Symbol S3BRG S4BRG After Reset Indeterminate Indeterminate S5BRG 3 01EBh Indeterminate S6BRG 3 01D9h Indeterminate Setti
425. t is ST Start bit implemented P Even Parity NOTE SP Stop bit 1 The output of microcomputer is in the high impedance state pulled up externally Figure 14 34 Parity Error Signal Output Timing Rev 1 10 Jul01 2005 page 173 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O 14 1 6 2 Format When direct format set the PRY bit in the U2MR register to 1 the UFORM bit in the U2CO register to 0 and the U2LCH bit in the U2C1 register to 0 When inverse format set the PRY bit to 0 UFORM bit to 1 and U2LCH bit to 1 Figure 14 35 shows the SIM interface format 1 Direct format clock L ee Do D1 j D2 D3 os 05 De 07 P P Even parity 2 Inverse format Transfer H clock MS s o7 De D5 os bs oz oi A Do P P Odd parity Figure 14 35 SIM Interface Format Rev 1 10 Jul01 2005 page 174 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O 14 2 SI Oi i 3 to 6 SI Oi is exclusive clock synchronous serial I Os Figure 14 36 shows the block diagram of SI Oi and Figures 14 37 and 14 38 show the Sl Oi related registers Table 14 19 lists the specifications of SI Oi NOTE 1 100 pi
426. t is generated Execute the rewrite program again after exiting the interrupt routine The address match interrupt is not available since the CPU tries to read data in the flash memory EW1 Mode Do not acknowledge any interrupts with vectors in the relocatable vector table or address match interrupt during the auto program or auto erase period Do not use the watchdog timer interrupt e The NMI interrupt is available since the FMRO and FMR1 registers are forcibly reset when the interrupt request is generated Allocate the jump address for the interrupt service routine to the fixed vector table Flash memory rewrite operation is aborted when the NMI interrupt request is generated Execute the rewrite program again after exiting the interrupt service routine 22 18 11 How to Access To set the FMRO1 FMRO2 or FMR11 bit to 1 write 1 after first setting the bit to 0 Do not generate an interrupt or a DMA transfer between the instruction to set the bit to 0 and the instruction to set the bit to 1 Set the bit while an H signal is applied to the NMI pin 22 18 12 Rewriting in User ROM Area EWO Mode The supply voltage drops while rewriting the block where the rewrite control program is stored the flash memory cannot be rewritten because the rewrite control program is not correctly rewritten If this error occurs rewrite the user ROM area while in standard serial I O mode or parallel I O mode or CAN I O mode
427. t is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 11 DMAC 11 1 Transfer Cycle The transfer cycle consists of a memory or SFR read source read bus cycle and a write destination write bus cycle The number of read and write bus cycles is affected by the source and destination addresses of transfer The bus cycle itself is extended by a software wait 11 1 1 Effect of Source and Destination Addresses If the transfer unit and data bus both are 16 bits and the source address of transfer begins with an odd address the source read cycle consists of one more bus cycle than when the source address of transfer begins with an even address Similarly if the transfer unit and data bus both are 16 bits and the destination address of transfer begins with an odd address the destination write cycle consists of one more bus cycle than when the destination address of transfer begins with an even address 11 1 2 Effect of Software Wait For memory or SFR accesses in which one or more software wait states are inserted the number of bus cycles required for that access increases by an amount equal to software wait states Figure 11 5 shows the example of the cycles for a source read For convenience the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown In reality the destination write cycle is subject to the same conditions as the source read cycle wi
428. te access and word access The content of each slot remains unchanged unless transmission or reception of a new message is performed m eT s p se ps lt se e p om see sor 99 TS eee pee sj T eT coe eos coe eo coo i ue no uo Data Byte 0 Data Byte 1 Data Byte 7 Time Stamp high order byte Time Stamp low order byte CAN Data Frame siDi0to6 siD5too EID171014 ElD13106 ElD5too DLC3to0 Data Byte o Data Byte 1 Data Byte 7 NOTE 1 When EX is read the value is the one written upon the transmission slot configuration The value is 0 when read on the reception slot configuration Figure 18 2 Bit Mapping in Byte Access Deseo Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7 Time Stamp high order byte Time Stamp low order byte CAN Data Frame SID10to6 SID5to0 EID17to14 EID13to6 EID5toO DLC3toO Data Byte O Data Byte 1 Data Byte7 NOTE 1 When 2 is read the value is the one written upon the transmission slot configuration The value is 0 when read on the reception slot configuration Figure 18 3 Bit Mapping in Word Access Rev 1 10 Jul01 2005 page 205 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 18 3 Acceptance Mask Registers 18 CAN Module Figures 18 4
429. ted as expected Refer to 20 3 8 Full Status Check Figure 20 9 shows a flow chart of the block erase command programming The lock bit protects each block from being programmed inadvertently Refer to 20 3 6 Data Protect Function In EW1 mode do not execute this command on the block where the rewrite control program is allocated In EWO mode the microcomputer enters read status register mode as soon as an auto erase operation starts The status register can be read The SR7 bit in the status register is set to 0 at the same time an auto erase operation starts It is set to 1 when an auto erase operation is completed The micro computer remains in read status register mode until the read array command or read lock bit status command is written Write the command code xx20h Write xxDOh to the EE order EE address Full status check Block erase operation is completed NOTE 1 Write the command code and data to even addresses Figure 20 9 Block Erase Command Rev 1 10 Jul01 2005 page 252 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Flash Memory Version 20 3 5 6 Erase All Unlocked Block The erase all unlocked block command erases all blocks except the block A By writing xxA7h in the first bus cycle and xxDOh in the second bus cycle an auto erase erase and verify operation will ru
430. ter i Oto5 NOTES 1 The TBOS to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register and the TB3S to TB5S bits are assigned to the bit 5 to bit 7 in the TBSR register 2 Interrupt request is not generated when the first effective edge is input after the timer started counting 3 Value read from the TBi register is indeterminate until the second valid edge is input after the timer starts counting Rev 1 10 Jul01 2005 page 114 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 Timers Timer Bi Mode Register i 0 to 5 Symbol TBOMR to TB2MR TB3MR to TB5MR Address 039Bh to 039Dh 01DBh to 01DDh After Reset 00XX0000b 00XX0000b Bit Name Function Operation Mode Pulse period pulse width Select Bit i E measurement mode Pulse period measurement Measurement between a falling edge and the next falling edge of measured pulse Pulse period measurement Measurement between a rising edge and the next rising edge of measured pulse Pulse width measurement Measurement between a falling edge and the next rising edge of measured pulse and between a rising edge and the next falling edge 1 1 Do not set a value Measurement Mode Select Bit TBOMR and TB3MR registers Set to 0 in pulse period and pulse width measurement mode TB1MR TB2MR TBAMR TB5MR registers Nothing
431. ter 12 C1MCTL12 00h CAN1 Message Control Register 13 C1MCTL13 00h CAN1 Message Control Register 14 C1MCTL14 00h CAN1 Message Control Register 15 C1MCTL15 00h 0230h X0000001b 0231h CAN1 Control Register C1CTLR XX0X0000b 0232h 00h 0233h CAN 1 Status Register C1STR X0000001b 0234h 00h 0235h CAN 1 Slot Status Register C1SSTR 00h 0236h 00h 0237h CAN1 Interrupt Control Register C1ICR 00h 0238h 00h 0239h CAN1 Extended ID Register C1IDR 00h Hess CAN1 Configuration Register C1CONR XE CAN1 Receive Error Count Register C1RECR 00h CAN1 Transmit Error Count Register C1TECR 00h CAN Time Stamp Register C1TSR ocn X Undefined Rev 1 10 Jul01 2005 page 21 of 318 ENESAS REJO9B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 4 Special Function Register SFR Table 4 10 SFR Information 10 0240h 0241h 0242h XXh 0243h CANO Acceptance Filter Support Register XXh 0244h XXh CAN1 Acceptance Filter Support Register XXh Peripheral Clock Select Register CANO 1 Clock Select Register 0260h 0261h CAN1 Message Box 0 Identifier DLC 0263h 0264h 0266h 0267h 0268h CAN1 Message Box 0 Data Field 026Ah 026Bh 026Ch 026Dh 026Eh Es O26Fh CAN1 Message Box 0 Time Stamp 0270h 0271h oaran _ CAN1 Message Box 1 Ident
432. ter Reset COCTLR 0210h X0000001b C1CTLR 0230h X0000001b CAN Module 0 Operation mode Reset Reset Bit 1 1 Reset initialization mode Loop Back Mode 0 Loop back mode disabled Select Bit 2 1 Loop back mode enabled Message Order 0 Word access Select Bit 2 1 Byte access BasicCAN Basic CAN o Basic CAN mode disabled asic Select Bit 2 Basic CAN mode enabled BusErrE Bus Error Vr 0 Bus error interrupt disabled USEMEN Enable Bit 2 1 Bus error interrupt enabled si Sleep Mode 0 Sleep mode disabled RW sep Select Bit 2 3 1 Sleep mode enabled clock supply stopped CAN Port Enable 0 I O port function LoopBack MsgOrder Nothing is assigned When write set to 0 b7 When read its content is indeterminate 1 When the Reset bit is set to 1 CAN reset initialization mode check that the State Reset bit in the CiSTR register is set to 1 Reset mode 2 Change this bit only in the CAN reset initialization mode 3 When using CANO 1 wake up interrupt set these bits to 1 b8 bo Symbol Address After Reset COCTLR 0211h XX0X0000b C1CTLR 0231h XX0X0000b b1 bO 0 0 Period of 1 bit time 0 1 Period of 1 2 bit time 1 0 Period of 1 4 bit time 1 1 Period of 1 8 bit time Time Samp Counter 0 Nothing is occurred Tope Reset Bit 1 1 Force reset of the time stamp counter E Return From WE Off 0 Nothing is occurred Fetbusem Command Bit 2 1 Force return from bus off Nothing is sod When write
433. ter is only in the 128 pin version In the 100 pin version set the IFSR22 bit to 0 Timer B1 Figure 9 4 Interrupt Control Registers 2 Rev 1 10 Jul01 2005 page 66 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 9 Interrupt 9 5 11 Flag The flag enables or disables the maskable interrupt Setting the flag to 1 enabled enables the maskable interrupt Setting the flag to 0 disabled disables all maskable interrupts 9 5 2 IR Bit The IR bit is set to 1 interrupt requested when an interrupt request is generated Then when the interrupt request is accepted and the CPU branches to the corresponding interrupt vector the IR bit is set to 0 interrupt not requested The IR bit can be set to 0 in a program Note that do not write 1 to this bit 9 5 3 ILVL2 to ILVLO Bits and IPL Interrupt priority levels can be set using the ILVL2 to ILVLO bits Table 9 3 shows the settings of interrupt priority levels and Table 9 4 shows the interrupt priority levels enabled by the IPL The following are conditions under which an interrupt is accepted flag 1 IR bit 1 interrupt priority level gt IPL The flag IR bit ILVL2 to ILVLO bits and IPL are independent of each other In no case do they affect one another Table 9 3 Settings of Interrupt Priority Levels Table 9 4 Interrup
434. terrupt Control Register S2TIC XXXXX000b UART2 Receive Interrupt Control Register S2RIC XXXXX000b UARTO Transmit Interrupt Control Register SOTIC XXXXX000b UARTO Receive Interrupt Control Register SORIC XXXXX000b UART1 Transmit Interrupt Control Register S1TIC XXXXX000b UART1 Receive Interrupt Control Register S1RIC XXXXX000b Timer AO Interrupt Control Register TAOIC XXXXX000b Timer A1 Interrupt Control Register TA11C XXXXX000b Timer A2 Interrupt Control Register TA2IC NT7 Interrupt Control Register 1 INT7IC XX00X000b Timer A3 Interrupt Control Register TA3IC NT6 Interrupt Control Register 1 INT6IC 2200X0009 Timer A4 Interrupt Control Register TA4IC XXXXX000b Timer BO Interrupt Control Register TBOIC SI O6 Interrupt Control Register 1 S6IC sind Timer B1 Interrupt Control Register TB1IC INT8 Interrupt Control Register INTSIC XX00X000b Timer B2 Interrupt Control Register TB2IC XXXXX000b INTO Interrupt Control Register INTOIC XX00X000b INT1 Interrupt Control Register INT1IC XX00X000b INT2 Interrupt Control Register INT2IC XX00X000b 0060h XXh 0061h XXh oean _ CANO Message Box 0 Identifier DLC 0064h XXh 0065h XXh 0066h XXh 0067h XXh 0068h XXh E CANO Message Box 0 Data Field XXh 006Bh XXh 006Ch XXh 006Dh XXh sb CANO Message Box 0 Time Stamp 0070h XXh 0071h XXh 0075h CANO Message Box 1 Identifier DLC XXh 0074h XXh 0075h XXh 0076h XXh 0077h XXh 0078h XXh a CANO Message Box 1 Data Field XXh 007Bh XXh 007Ch XXh 00
435. th the transfer cycle changing accordingly When calculating transfer cycles take into consideration each condition for the source read and the destination write cycle respectively For example when data is transferred in 16 bit unit using an 8 bit bus 2 on Figure 11 5 two source read bus cycles and two destination write bus cycles are required Rev 1 10 Jul01 2005 page 87 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 11 DMAC 1 When the transfer unit is 8 or 16 bits and the source of transfer is an even address s o Cue se o Dean 65 e RD signal WR signal Data bus CPU use Source Destination CPU use 2 When the transfer unit is 16 bits and the source address of transfer is an odd address or when the transfer unit is 16 bits and an 8 bit bus is used z AA LAA Address bus CPU use RD signal WR signal Data bus CPU use 3 When the source read cycle under condition 1 has one wait state inserted BCLK Address bus CPU use RD signal WR signal Data E i i i bus CPU use i Source Destination de CPU use 4 When the source read cycle under condition 2 has one wait state inserted e MIA E CPU use f Source 1 Destination cru use RD signal WR si
436. the second bus cycle the lock bit for the specified block is set to 0 The address value specified in the first bus cycle must be the same highest order even address of a block specified in the second bus cycle Figure 20 10 shows a flow chart of the lock bit program command programming Execute read lock bit status command to read lock bit state lock bit data The FMROO bit in the FMRO register indicates whether a lock bit program operation is completed Refer to 20 3 6 Data Protect Function for details on lock bit functions and how to set it to 1 unlocked Write command code xx77h to the highest order block address Write xxDOh to the highest order block address Full status check Lock bit program operation is completed NOTE 1 Write the command code and data to even addresses Figure 20 10 Lock Bit Program Command Rev 1 10 Jul01 2005 page 253 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Flash Memory Version 20 3 5 8 Read Lock Bit Status Command 71h The read lock bit status command reads the lock bit state of a specified block By writing xx71h in the first bus cycle and xxDOP to the highest order even address of a block in the second bus cycle the FMR16 bit in the FMR1 register stores information on whether or not the lock bit of a specified block is locked Read the FMR16 bit afte
437. the CMO register When the CM20 bit is 1 oscillation stop re oscillation detection function enabled the CM27 bit is 1 oscillation stop re oscillation detection interrupt and the CPU clock source is the main clock the CM21 bit is set to 1 on chip oscillator clock if the main clock stop is detected If the CM20 bit is 1 and the CM23 bit is 1 main clock turned off do not set the CM21 bit to 0 Effective when the CMO7 bit in the CMO register is 0 Where the CM20 bit is 1 oscillation stop re oscillation detection function enabled the CM27 bit is 1 oscillation stop re oscillation detection interrupt and the CM1 1 bit is 1 the CPU clock source is PLL clock the CM21 bit remains unchanged even when main clock stop is detected If the CM22 bit is O under these conditions an oscillation stop re oscillation detection interrupt request is generated at main clock stop detection it is therefore necessary to set the CM21 bit to 1 on chip oscillator clock inside the interrupt routine This bit is set to 1 when the main clock is detected to have stopped and when the main clock is detected to have restarted oscillating When this bit changes state from O to 1 an oscillation stop and re oscillation detection interrupt request is generated Use this bit in an interrupt routine to discriminate the causes of interrupts between the oscillation stop and re oscillation detection interrupt and the watchdog timer
438. the SMD2 to SMDO bits in the UiMR register to 001b clock synchronous serial I O mode 3 1 transmission enabled is written to the TE bit in the UiC1 register regardless of the TE bit 14 1 1 2 CLK Polarity Select Function Use the CKPOL bit in the UiCO register i 0 to 2 to select the transfer clock polarity Figure 14 12 shows the polarity of the transfer clock 1 When the CKPOL bit in the UiCO register 0 transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock CLKi NOTE 1 TXDi Ano A Dt X Dai Do A ba A Ds Xoe X o7 RXDi Y po Y pi X D2 X D3 X D4 X bs X pe X D7 2 When the CKPOL bit in the UiCO register 1 transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock CLKi l NOTE 2 TXDi OOOO RXDi Y po X D1 X D2 X pa X D4 X D5 X De X D7 i 0to2 This applies to the case where the UFORM bit in the UiCO register 0 LSB first and the UiLCH bit in the UiC1 register O no reverse NOTES 1 When not transferring the CLKi pin outputs a high signal 2 When not transferring the CLKi pin outputs a low signal Figure 14 12 Transfer Clock Polarity Rev 1 10 Jul01 2005 page 142 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its content
439. the internal RAM area Rev 1 10 Jul01 2005 page 242 of 318 REJO9B0124 0110 134 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Flash Memory Version 20 3 1 EWO Mode The microcomputer enters CPU rewrite mode by setting the FMRO1 bit in the FMRO register to 1 CPU rewrite mode enabled and is ready to accept commands EWO mode is selected by setting the FMR11 bit in the FMR1 register to 0 To set the FMRO1 bit to 1 set to 1 after first writing 0 The software commands control programming and erasing The FMRO register or the status register indicates whether a program or erase operation is completed as expected or not 20 3 2 EW1 Mode EW1 mode is selected by setting FMR11 bit to 1 by writing 0 and then 1 in succession after setting the FMRO1 bit to 1 by writing 0 and then 1 in succession Both bits must be set to 0 first before setting to 1 The FMRO register indicates whether or not a program or erase operation has been completed as expected The status register cannot be read in EW1 mode Rev 1 10 Jul01 2005 page 243 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 3 3 FMRO FMR1 Registers Figure 20 4 shows FMRO and FMR1 registers Flas
440. the transfer clock after supplying eight pulses If the SMi6 bit 1 internal clock the transfer clock automatically stops 2 Unlike UARTO to UART2 SI Oi is not separated between the transfer register and buffer Therefore do not write the next transmit data to the SiTRR register during transmission 3 When the SMIi6 bit 1 internal clock SOUTi retains the last data for a 1 2 transfer clock period after completion of transfer and thereafter goes to a high impedance state However if transmit data is written to the SiTRR register during this period SOUTi immediately goes to a high impedance state with the data hold time thereby reduced 4 When the SMi6 bit 1 internal clock the transfer clock stops in the high state if the SMi4 bit 0 or stops in the low state if the SMi4 bit 1 Rev 1 10 Jul01 2005 page 178 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O 14 2 1 SI Oi Operation Timing Figure 14 39 shows the SI Oi operation timing 1 5 cycle max 1 SI Oi internal clock CLKi output Signal written to the SiTRR register SOUTIi output SINi input IR bit in SilC register SiTRF bitin S3456TRR register o i 3 to 6 5 and 6 are only in the 128 pin version This diagram applies to the case where the bits in the SiC register are set as follows SMi2 0 SOUTi output
441. tions Table 22 4 Recommended Pin Connections In case of PCA82C250 Philips product High speed Mode Standby Mode Rs Pin up Power Consumption in less than 170 pA CAN Transceiver less than 70 mA CAN Communication impossible possible Connection M16C 6NK M16C 6NM PCA82C250 H output M16C 6NK M16C 6NM PCA82C250 L output i 0 1 NOTES 1 The pin which controls the operation mode of CAN transceiver 2 In case of Ta 25 C 3 Connect to enabled port to control CAN transceiver Table 22 5 Recommended Pin Connections In case of PCA82C252 Philips product Sleep Mode Normal Operation Mode STB Pin H EN Pin H Power Consumption in less than 50 uA less than 35 mA CAN Transceiver CAN Communication impossible possible Connection M16C 6NK M16C 6NM PCA82C252 M16C 6NK M16C 6NM PCA82C252 L output H output i 0 1 NOTES 1 The pin which controls the operation mode of CAN transceiver 2 Ta 25 C 3 Connect to enabled port to control CAN transceiver Rev 1 10 Jul01 2005 page 305 of 318 REJ09B0124 0110 131 NE SAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 13 4 CAN Transceiver in Boot Mode 22 Usage Precaution When programming the flash memory in boot mode via CAN bus the operation mode of CAN transceiver should be set to high spee
442. tions Function The CH2 to CHO bits in the ADCONO register the ADGSEL1 to ADGSELO bits in the ADCON2 register and the OPA1 to OPAO bits in the ADCON1 register select a pin Analog voltage applied to this pin is repeatedly converted to a digital code A D Conversion e When the TRG bit in the ADCONO register is 0 software trigger Start Condition The ADST bit in the ADCONO register is set to 1 A D conversion starts When the TRG bit is 1 ADTRG trigger Input on the ADTRG pin changes state from high to low after the ADST bit is set to 1 A D conversion starts A D Conversion Set the ADST bit to 0 A D conversion halted Stop Condition Interrupt Request None generated Generation Timing Analog Input Pin Select one pin from ANO to AN7 ANO 0 to ANO 7 AN2 0 to AN2 7 ANEXO to ANEX1 Reading of Result of Read one of the ADO to AD7 registers that corresponds to the selected pin A D Converter Rev 1 10 Jul01 2005 page 187 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 A D Converter A D Control Register 0 A A A AO Symbol Address After Reset deii ADCONO 03D6h 00000XXXb Bit Symbol b2 b1 b0 0 0 0 ANO is selected 00 1 AN1 is selected 0 1 0 AN2 is selected Analog Input Pin Select Bit 0 1 1 AN3 is selected AN4 is selected AN5 is selected AN6 is selected A
443. tions as an input port Port P14 1 Direction 1 Output mode Bit Functions as an output port Nothing is assigned When write set to 0 When read their contents are indeterminate 1 When using the port P14 set the PUS7 bit in the PUR3 register to 1 usable Figure19 8 PO to P13 Registers and PC14 Register Rev 1 10 Jul01 2005 page 234 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 Programmable l O Ports Pull up Control Register O b7 b6 b5 b4 b3 b2 bi bO Address After Reset 03FCh 00h 1 The pin for which this bit is 1 pulled high and the direction bit is 0 input mode is pulled high Pull up Control Register 1 b7 b6 b5 b4 b3 b2 bi bO Address After Reset 03FDh 00h umo eremo er 1 Puled high 1 The P7_1 pin does not have pull up 2 The pin for which this bit is 1 pulled high and the direction bit is 0 input mode is pulled high Pull up Control Register 2 b7 b6 b5 b4 b3 b2 bi bO Address After Reset 03FEh 00h L mus Pa Dira 3 Pulp 7 O Not pulled high PUzi P8 4 PB 6andPB 7 Pull Up 1 Pulled high 6 Nothing is assigned When write set to O When read their contents are 0 1 The P8 5 pin does not have pull up 2 The P9 1 pin does not have pull up 3 The pin for which this bit is 1 pulled high and the direction bit is 0 input m
444. tor charge is held to 0 1LSB at time of A D conversion in the 10 bit mode Actual error however is the value of absolute precision added to 0 1LSB When f XIN 10 MHz T 0 3 us in the A D conversion mode with sample amp hold Output impedance RO for sufficiently charging capacitor C within time T is determined as follows T 0 3 us R 7 8 KQ C 1 5 pF X 0 1 and Y 1024 Hence 0 3 X 105 RO 7 8 X103 5 13 9 x 10 1 5 X 10 e In 1024 Thus the allowable output impedance of the sensor circuit capable of thoroughly driving the A D converter turns out to be approximately 13 9 kQ Rev 1 10 Jul01 2005 page 196 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 15 A D Converter Microcomputer Sensor equivalent circuit Sampling time Sample and hold function enabled z Sample and hold function disabled Figure 15 10 Analog Input Pin and External Sensor Equivalent Circuit Rev 1 10 Jul01 2005 page 197 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 16 D A Converter 16 D A Converter This is an 8 bit R 2R type D A converter These are two independent D A converters D A conversion is performed by writing to the DAI register i 0 1 To output the re
445. ts are in the UCON register Rev 1 10 Jul01 2005 page 156 of 318 REJO9B0124 0110 ENESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O Table 14 12 1 C Mode Functions C Mode SMD2 to SMDO 010b IICM 1 IICM2 1 UART transmit receive interrupt Clock Synchronous Serial I O Mode IICM2 0 Function NACK ACK interrupt Factor of Interrupt Number 6 7 and 100610 SMD2 to SMDO 001b IICM 0 CKPH 0 CKPH 1 No clock delay Clock delay CKPH 0 No clock delay Start condition detection or stop condition detection See Table 14 13 STSPSEL Bit Functions CKPH 1 Clock delay Factor of Interrupt Number 15 17 and 19 1 6 UARTI transmission Transmission started or completed selected by VIlRS No acknowledgment detection NACK Rising edge of SCLi 9th bit UARTI transmission Rising edge of SCLi 9th bit UARTI transmission Falling edge of SCLi next to the 9th bit Factor of Interrupt Number 16 18 and 20 006 UARTI reception When 8th bit received CKPOL 0 rising edge CKPOL 1 falling edge Acknowledgment detection ACK Rising edge of SCLi 9th bit UARTI reception Falling edge of SCLi 9th bit Timing for Transferring Data from UART Reception Shift Register to UIRB Register CKPOL 0 rising edge CKPOL 1 falling edge
446. ts to 000b no delay 2 The amount of delay varies with the load on SCLi and SDAi pins Also when using an external clock the amount of delay increases by about 100 ns Figure 14 9 UOSMR2 to U2SMR2 Registers and UOSMR3 to U2SMR3 Registers Rev 1 10 Jul01 2005 page 136 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM UARTi Special Mode Registe b7 b6 b5 b4 b3 b2 bi bO Symbol UOSMR4 to U2SMR4 14 Serial I O r4 i 0 to 2 Address 01ECh 01FOh 01F4h After Reset 00h Start Condition Generate Bit 1 0 Clear 1 Start RSTAREQ 0 Clear 1 Start Restart Condition Generate Bit 1 0 Clear 1 Start Stop Condition Generate Bit 1 O Start and stop conditions not output SCL SDA Output i 1 Start and stop conditions output Select Bit 0 ACK ACK Data Bit 1 NACK ACK Data Output Enable Bit 0 Serial I O data output 1 ACK data output 1 Set to 0 when each condition is SCL Output Stop 0 Disabled Enable Bit 1 Enabled m 0 SCL L hold disabled SCL Wait Bit 3 1 SCL L hold enabled generated Figure 14 10 UOSMR4 to U2SMR4 Registers Rev 1 10 Jul 01 2005 page 137 of 318 REJO9B0124 0110 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK
447. uest Cause See NOTE 1 Nothing is assigned When write set to 0 When read their contents are 0 A DMA request is generated by setting Software DMA this bit to 1 when the DMS bit is 0 basic cause and the DSEL3 to DSELO bits are 0001b software trigger The value of this bit when read is 0 1 The causes of DMAO requests can be selected by a combination of the DMS bit and the DSEL3 to DSELO bits in the manner described below DSEL3 to DSELO Bits DMS 0 basic cause of request DMS 1 extended cause of request 0000b Falling edge of INTO pin 0001b Software trigger 0010b Timer AO 0011b Timer A1 0100b Timer A2 0101b Timer A3 0110b Timer A4 0111b Timer BO 1000b Timer B1 1001b Timer B2 1010b UARTO transmit 1011b UARTO receive 1100b UART2 transmit 1101b UART2 receive 1110b A D conversion 1111b UART1 transmit Figure 11 2 DMOSL Register Rev 1 10 Jul 01 2005 REJ09B0124 0110 page 84 of 318 34 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM DMA1 Request Cause Select Register b7 b6 b5 b4 b3 b2 bi b0 Symbol DM1SL 11 DMAC Address After Reset O3BAh 00h DSELO DSEL1 DMA Request Cause DSEL2 Select Bit DSEL3 See NOTE 1 Nothing is assigned When write set
448. ulator D all s E b7 b6 00 f1 or f2 Count Source Select Bit 0 1 f8 10 f32 1 fC32 D 22 8 1 Effective when the TAITGH and TAITGL bits in the ONSF or TRGSR register are 00b TAiIN pin input 2 The port direction bit for the TAiIN pin is set to 0 input mode 3 Set to 1 pulse is output PWM pulse is output Figure 12 12 TAOMR to TA4MR Registers in Pulse Width Modulation Mode Rev 1 10 Jul01 2005 page 107 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 Timers Count source Input signal to TAIIN pin PWM pulse output H from TAiOUT pin IR bit in TAiIC y register o i 0t04 Set to 0 upon accepting an interrupt request or by writing in program fj Frequency of count source f1 f2 f8 f32 fC32 NOTES 1 n 0000h to FFFEh 2 This timing diagram is the following case e TAI register 0003h e The TAITGH and TAiTGL bits in the ONSF or TRGSR register 00b TAIIN pin input e The MR1 bit in the TAiMR register 1 rising edge e The MR2 bit in the TAiMR register 1 trigger selected by the TAiITGH and TAITGL bits Figure 12 13 Example of 16 bit Pulse Width Modulator Operation Count source 1 Input signal to TAiIN pin Underflow signal of 8 bit prescaler 2 PWM pulse output from TAiOUT pin IR bit in TAiIC register 0to04 Set to
449. ule CANI Configuration Register i 0 1 pr D6 05 Re ibA Symbol Address After Reset COCONR 021Ah Indeterminate C1CONR 023Ah Indeterminate JE Divide by 1 of fCAN Divide by 2 of fCAN Divide by 3 of fCAN 1 0 Divide by 15 of f CAN 1 1 Divide by 16 of fCAN 1 n SAM Sampling Control One time sampling RW Bit Three times sampling 6 Propagation Time Segment Control Bits 2003 ooog Prescaler Division Ratio Select Bits oog 2o o o08 ooog 2o 2 00 zh EE o0 1 fCAN serves for the CAN clock The period is decided by configuration of the CCLKi bit i 0 to 2 4 to 6 in the CCLKR register b8 Symbol Address After Reset COCONR 021Bh Indeterminate C1CONR 023Bh Indeterminate b2 b1b0 000 Do not set a value Phase Buffer 001 2Tq Segment 1 010 3Tq Control Bits 110 7Tq 111 8Tq b5 b4 b3 000 Do not set a value Phase Buffer 001 2Tq Segment 2 010 3Tq Control Bits 110 7Tq 111 8Tq Resynchronization Jump Width Control Bits Figure 18 10 COCONR and C1CONR Registers Rev 1 10 Jul01 2005 page 211 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 18 CAN Module CANi Receive Error Count Register i 0 1 bz 50 Symbol Address After Reset T C1RECR 023Ch 00h Counter Value Reception error counting function D The value is incremented or dec
450. ulse By a transfer trigger or the falling edge of Timer when the INV16 Bit 0 of the timer A1 A2 or A4 a one shot pulse of the timer A1 A2 or A4 INV13 Bit Enabled when the INV11 bit 1 and the Disabled INVO6 bit 0 Transfer trigger Timer B2 underflows and write to the INVO7 bit or write to the TB2 register when INV10 1 9 When the INVO6 bit is set to 1 set the INV11 bit to 0 three phase mode 0 and the PWCON bit in the TB2SC register to 0 reload timer B2 with timer B2 underflow Figure 13 2 INVCO Register Rev 1 10 Jul01 2005 page 119 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Three Phase Motor Control Timer Function Three Phase PWM Control Register 1 b7 b6 b5 b4 b3 b2 bi BLLLLLLL rer ew e Be 0 Timer B2 underflow SU T Etape E 1 Timer B2 underflow and write to the timer B2 Timer A1 1 A2 1 A4 1 Three phase mode 0 9 Control Bit 2 Three phase mode 1 Dead Time Timer f1 or f2 Count Source Select Bit 1 f1 divided by 2 or f2 divided by 2 Carrier Wave Detect Timer A1 reload control signal is 0 Flag 4 Timer A1 reload control signal is 1 Output Polarity Control Active L of an output waveform Bit Active H of an output waveform Enables dead time Dead Time Disable Bit Disables dead time Falling edge of a on
451. under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 9 Interrupt 9 5 7 Saving Registers In the interrupt sequence the FLG register and PC are saved to the stack At this time the 4 high order bits of the PC and the 4 high order IPL and 8 low order bits in the FLG register 16 bits in total are saved to the stack first Next the 16 low order bits of the PC are saved Figure 9 7 shows the stack status before and after an interrupt request is accepted The other necessary registers must be saved in a program at the beginning of the interrupt routine Use the PUSHM instruction and all registers except SP can be saved with a single instruction SP New SP valu SP value before a is accepted Fa c Stack status before interrupt request is acknowledged Stack status after interrupt request is acknowledged PCL 8 low order bit of PC PCM 8 middle order bits of PC PCH 4 high order bits of PC FLGL 8 low order bits of FLG FLGH 4 high order bits of FLG Figure 9 7 Stack Status Before and After Acceptance of Interrupt Request The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP at the time of acceptance of an interrupt request is even or odd If the SP Note is even the FLG register and the PC are saved 16 bits at a time If odd they are saved in two steps 8 bits at a time Figure 9 8 shows the operation of the saving registers
452. underflows or underflows the output polarity of TAiOUT pin is inverted When TAIS bit is set to 0 stop counting the pin outputs a low i20to4 j i 1 exceptj 4ifi 0 k i 1 except k 0ifi 4 Rev 1 10 Jul01 2005 page 99 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 Timers Timer Ai Mode Register i O to 4 When not using two phase pulse signal processing b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset ol o TAOMR to TA4MR 0396h to 039Ah 00h TMODO TMODI Operation Mode Select Bit d Event couriter inede ti 0 Pulse is not output Pulse Output Function TAiOUT pin functions as I O port MRO Select Bit Pulse is output TA OUT pin functions as pulse output Mij E Counts falling edge of external signal M Count Polarity Select Bit 4 Counts rising edge of external signal RW Up Down Switching P UDF register EXE Select Bit Input signal to TAiOUT pin 3 MR3 set to 0 in event counter mode Count Operation Type 0 Reload type TCKO Select Bit 1 Free run type oe TCK1 Can be 0 or 1 when not using two phase pulse signal processing 1 During event counter mode the count source can be selected using the ONSF and TRGSR registers 2 Effective when the TAiTGH and TAITGL bits in the ONSF or TRGSR register are 00b TAiIN pin inpu
453. until the flash memory circuit stabilizes tps us Jump to a desired address in the flash memory 1 Set the FMSTP bit in the FMRO register to 1 after setting the FMRO1 bit in the FMRO register to 1 CPU rewrite mode 2 Wait until clock stabilizes to switch clock source of the CPU clock to the main clock or sub clock 3 Add tps us wait time by program Do not access the flash memory during this wait time 4 Before entering wait mode or stop mode be sure to set the FMRO 1 bit to 0 CPU rewrite disabled Figure 20 7 Processing Before and After Low Power Dissipation Mode Rev 1 10 Jul 01 2005 page 247 of 318 REJO9B0124 0110 131 NESAS Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 20 Flash Memory Version 20 3 4 Precautions on CPU Rewrite Mode 20 3 4 1 Operating Speed Set the CMO6 bit in the CMO register and the CM17 to CM16 bits in the CM1 register to clock frequency of 10 MHz or less before entering CPU rewrite mode EWO or EW1 mode Also set the PM17 bit in the PM1 register to 1 with wait state 20 3 4 2 Prohibited Instructions The following instructions cannot be used in EWO mode because the CPU tries to read data in flash memory UND instruction INTO instruction JMPS instruction JSRS instruction and BRK instruction 20 3 4 3 Interrupts EWO Mode To use interrupts having vectors in a relocatable vector table the vector
454. unting and until the 1st count source is input after counting start Value written to TAi register is written to both reload register and counter When counting after 1st count source input Value written to TAi register is written to reload register Transferred to counter when reloaded next Select Function Normal processing operation timer A2 and timer A3 The timer counts up rising edges or counts down falling edges on TAjIN pin when input signals on TAjOUT pin is H TAjOUT TAjIN i i i 1 Y 1 Up Up Up Down Down Down count count count count count count e Multiply by 4 processing operation timer A3 and timer A4 If the phase relationship is such that TAkIN pin goes H when the input signal on TAKOUT pin is H the timer counts up rising and falling edges on TAKOUT and TAKIN pins If the phase relationship is such that TAkIN pin goes L when the input signal on TAKOUT pin is H the timer counts down rising and falling edges on TAKOUT and TAKIN pins TAKOUT y A y 4 vAvAy WS ee Count up all edges Count down all edges TAkIN Er Mw Count up all edges Count down all edges Counter initialization by Z phase input timer A3 The timer count value is initialized to 0 by Z phase input i 2to4 j 2 3 k 3 4 NOTE 1 Only timer A3 is selectable Timer A2 is fixed to normal processing operation and timer A4 is fixed to multiply by 4 proce
455. us 34 Port latch ote ee a Symbolizes a parasitic diode Make sure the input voltage on each port will not exceed VCC Figure19 5 1 O Ports 5 BYTE signal input CNVSS CNVSS signal input RESET RESET signal input 4 QcEem Symbolizes a parasitic diode Make sure the input voltage on each port will not exceed VCC Figure19 6 I O Pins Rev 1 10 Jul01 2005 page 232 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 19 Programmable l O Ports Port Pi Direction Register i 0 to 7 9 to 13 0 Symbol Address After Reset PDO to PD3 03E2h 03E3h 03E6h 03E7h 00h PDA to PD7 03EAh 03EBh O3EEh 03EFh 00h PD9 to PD12 3 03F3h 03F6h 03F7h O3FAh 00h PD13 9 03FBh 00h OLE aras Functions as an input port E pope an output port PDi6 Porti 6 Direction Bit 1 Make sure the PD7 and PDO registers are written to by the next instruction after setting the PRC2 bit in the PRCR register to 1 write enabled 2 When using the ports P11 to P13 set the PU37 bit in the PURG register to 1 usable 3 The PD11 to PD13 registers are only in the 128 pin version b7 b6 b5 b4 b3 b2 bi bO Port P8 Direction Register b7 b6 b5 b4 b3 b2 bi b0 After Reset 00X00000b Bit Symbol PD8_0 Port P8 0 Direction Bit 0
456. ution 22 16 Electrical Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers Flash memory version and mask ROM version may have different characteristics operating margin noise tolerated dose noise width dose in electrical characteristics due to internal ROM different layout pattern etc When switching to the mask ROM version conduct equivalent tests as system evaluation tests conducted in the flash memory version Rev 1 10 Jul01 2005 page 309 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 17 Mask ROM Version When using the masked ROM version write nothing to internal ROM area Rev 1 10 Jul01 2005 page 310 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 22 Usage Precaution 22 18 Flash Memory Version 22 18 1 Functions to Prevent Flash Memory from Rewriting ID codes are stored in addresses OFFFDFh OFFFE3h OFFFEBh OFFFEFh OFFFF3h OFFFF7h and OFFFFBh If wrong data are written to theses addresses the flash memory cannot be read or written in standard serial I O mode and CAN I O mode The ROMCP register is mapped in address OFFFFFh If wrong data is written to this address the flash memory cannot be read or written in parallel I O mode In the
457. utput TAiOUT pin is a pulse output pin 00 1 Gate function not available 01 J TAIIN pin functions as I O port Gate Function Select Bit 1 0 Counts while input on the TAiIN pin is low 1 Counts while input on the TAiIN pin is high 1 Set to 0 in timer mode f1 or f2 Count Source Select Bit f8 f32 fC32 1 The port direction bit for the TAIIN pin is set to 0 input mode Figure 12 7 TAOMR to TA4MR Registers in Timer Mode Rev 1 10 Jul01 2005 page 98 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 12 Timers 12 1 2 Event Counter Mode In event counter mode the timer counts pulses from an external device or overflows and underflows of other timers Timers A2 A3 and A4 can count two phase external signals Table 12 2 lists specifications in event counter mode when not processing two phase pulse signal Figure 12 8 shows TAiMR register in event counter mode when not processing two phase pulse signal Table 12 3 lists specifications in event counter mode when processing two phase pulse signal with the timers A2 A3 and A4 Figure 12 9 shows TA2MR to TA4MR registers in event counter mode when processing two phase pulse signal with the timers A2 A3 and A4 Table 12 2 Specifications in Event Counter Mode when not processing two phase pulse signal Count Source External signals input to TAi
458. ve or negative phase which changes from inactive level to active level shifts when the dead time timer stops NOTES 1 Use the MOV instruction to set the DTT register 2 The DTT register is enabled when the INV15 bit in the INVC1 register is set to 0 dead time enabled No dead time can be set when the INV15 bit is set to 1 dead time disabled The INVO6 bit in the INVCO register determines start trigger of the DTT register Figure 13 4 IDBO and IDB1 Registers and DTT Register Rev 1 10 Jul01 2005 page 121 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 13 Three Phase Motor Control Timer Function Timer Ai Ai 1 Register i 1 2 4 0 9 0 9 6 b15 b8 b7 bO Symbol Address After Reset TA1 TA2 TA4 0389h 0388h 038Bh 038Ah 038Fh 038Eh Indeterminate TA11 TA21 TA41 7 01C3h 01C2h 01C5h 01C4h 01C7h 01C6h Indeterminate If setting value is n the timer stops when the nth count source is counted after a start trigger is generated Positive phase changes to negative phase and vice id ERREN MO versa when the timers A1 A2 and A4 stop 1 Use a 16 bit data for read and write 2 If the TAI or TAi1 register is set to 0000h no counters start and no timer Ai interrupt is generated 3 Use the MOV instruction to set the TAi and TAi1 registers 4 When the INV15 bit in the INVC1 register is s
459. velopment and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 14 Serial I O 1 ABSCS Bit in UiSMR Register bus collision detect sampling clock select If ABSCS bit 0 bus collision is determined at the rising edge of the transfer clock Transfer clock TXDi RXDi Timer Aj If ABSCS bit 1 bus collision is determined when timer Aj one shot timer mode underflows Timer Aj timer A3 when UARTO timer A4 when UART1 timer AO when UART2 2 ACSE Bit in UiSMR Register auto clear of transmit enable bit Transfer clock Lf VP Pe a de ee Le L a ST DO Di D2 D3 D4 DS D6 D7 D8 SP TXDi EN RXDi IR bit in If the ACSE bit 1 automatically UiBCNIC register clear when bus collision occurs the TE bit is set to 0 dect transmission disabled when TE bit in the IR bit in the UIBCNIC register 1 UiC1 register unmatching detected 3 SSS Bit in UiSMR Register transmit start condition select If SSS bit 0 the serial I O starts sending data one transfer clock cycle after the transmission enable condition is met Transfer clock 14 f f 1111 J f 1 n TLT LT D1 D2 D4 IS Transmission enable condition is met If SSS bit 1 the serial I O starts sending data at the rising edge 1 of RXDi CLKi TXDi RXDi NOTES 1 The falling edge of RXDi when IOPOL bit 0 the rising edge of RXDi when IOPOL bit 1 2 The transmit condition must be met before
460. vent Divide the count source by FFFFh n 1 Counter where n set value when O up or 0000h to FFFFh Mode by n 1 when counting down 2 One shot Divide the count source by n where n set 3 4 value and cause the timer to stop 0000h to FFFFh WO Pulse Width Modify the pulse width as follows Modulation PWM period 216 1 fj Mode High level PWM pulse width n fj 0000h to FFFEh 4 5 16 bit PWM where n set value fj count source frequency Pulse Width Modify the pulse width as follows Modulation PWM period 28 1 X m 1 fj 00h to FEh Mode High level PWM pulse width m 1 n fj High order address 8 bit PWM where n high order address set value 00h to FFh low order address set value fj Low order address count source frequency NOTES 1 The register must be accessed in 16 bit unit 2 The timer counts pulses from an external device or overflows or underflows in other timers 3 If the TAi register is set to 0000h the counter does not work and timer Ai interrupt requests are not generated either Furthermore if pulse output is selected no pulses are output from the TAiOUT pin 4 Use the MOV instruction to write to the TAi register 5 If the TAI register is set to 0000h the pulse width modulator does not work the output level on the TAiOUT pin remains low and timer Ai interrupt requests are not generated either The same applies when the 8 high order bits in the TAi registe
461. vised REVISION HISTORY M16C 6N Group M16C 6NK M16C 6NM Hardware Manual Date Summary Jul 01 2005 Figure 18 11 CORECR C1RECR Registers COTECR C1TECR Registers COTSR C1TSR Registers and COAFS C1AFS Registers CORECR C1RECR Registers NOTE 2 is deleted COTECR C1TECR Registers NOTE 1 is deleted COTSR C1TSR Registers NOTE 1 is deleted 18 15 1 Reception 1 refer to 18 15 2 Transmission is deleted Figure 19 1 I O Ports 1 P7 0 in 4th figure is deleted Figure 19 3 I O Ports 3 P7 0 is added to middle figure Figure 19 6 I O Pins NOTE 1 is deleted Table 21 4 Electrical Characteristics 1 e Measuring Condition of Vo is revised from Lo 200uA to Lo 200pA Table 21 5 Electrical Characteristics 2 Mask ROM 5th item f XCIN is changed to f BCLK Table 21 6 A D Conversion Characteristics Tolerance Level Impedance is deleted 22 14 Programmable I O Ports last 1 to 2 lines e 1 Setting Procedure is revised from 00010000b to 00000001b 2 Setting Procedure is revised from 00010011b to 00110001b M16C 6N Group M16C 6NK M16C 6NM Hardware Manual Publication Data Rev 1 00 Sep 30 2004 Rev 1 10 Jul 01 2005 Published by Sales Strategic Planning Div Renesas Technology Corp O 2005 Renesas Technology Corp All rights reserved Printed in Japan M16C 6N Group M16C 6NK M16C 6NM Hardware Manual 44 NESAS Ren
462. w The PM20 bit in the PM2 register become effective when the PLCO7 bit is set to 1 PLL on Change the PM20 bit when the PLCO7 bit is set to 0 PLL off Set the PM20 bit to O 2 waits when PLL clock gt 16 MHz PM20 bit to 0 SFR accessed with two wait states before setting the PLCO7 bit to 1 PLL operation PLL operation mode can only be changed to high speed mode Set the CMO6 bit to 1 division by 8 mode before changing back the operation mode from on chip oscillator mode to high or middle speed mode When the CM21 bit 0 on chip oscillator turned off and the CMO5 bit 1 main clock turned off the CMO6 bit is fixed to 1 divide by 8 mode and the CM15 bit is fixed to 1 drive capability High Figure 7 13 State Transition in Normal Operation Mode Rev 1 10 Jul01 2005 page 55 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM Table 7 7 Allowed Transition and Setting Current state State after transition 7 Clock Generating Circuit T Low Speed Low Power PLL Operation On chip Oscillator Mir eg Stop Wait Mois Mode Dissipation Mode Mode 2 Mode pissnaton ode Mode Mode High Speed Mode NOTE Y a 13 9 15 2 16 17 Medium Speed Mode AER deb 13 15 16 17 Low Speed Mode 2 8 abb 16 9 17 Low Power z 1
463. write set to 0 When read their contents are 0 1 When not using the D A converter set the DAIE bit i 0 1 to 0 output disabled to reduce the unnecessary current consumption in the chip and set the DAi register to 00h to prevent current from flowing into the R 2R resistor ladder D A Register i i 0 1 b7 bo Symbol Address After Reset DA1 03DAh 00h mm 8i Output value of D A conversion Mm 1 When not using the D A converter set the DAIE bit i 0 1 to 0 output disabled to reduce the unnecessary current consumption in the chip and set the DAi register to oon to prevent current from flowing into the R 2R resistor ladder Figure 16 2 DACON Register DAO and DA1 Registers DAIE bit DAi register q AVSS VREF i2 0 1 NOTE 1 The above diagram shows an instance in which the DAi register is assigned 2Ah Figure 16 3 D A Converter Equivalent Circuit Rev 1 10 Jul01 2005 page 199 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 17 CRC Calculation 17 CRC Calculation The Cyclic Redundancy Check CRC operation detects an error in data blocks The microcomputer uses a generator polynomial of CRC CCITT X6 X X 1 to generate CRC code The CRC code consists of 16 bits which are generated for each data block in given length separated in 8 bit un
464. xample for setting PLL clock frequencies Table 7 2 Example for Setting PLL Clock Frequencies XIN Multiply PLL Clock MHz PLCO2 PLCO1 PLCOO Eactor MHz O NOTE 1 PLL clock frequency 16 MHz 20 MHz or 24 MHz Rev 1 10 Jul01 2005 page 45 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Clock Generating Circuit Using the PLL clock as the clock source for the CPU Set the CMO7 bit to 0 main clock the CM17 to CM16 bits to 00b main clock undivided and the CMO6 bit to 0 CM16 and CM17 bits enabled 1 Set the PLC02 to PLCOO bits multiplying factor o SESIONES When PLL clock 16 MHz Set the PM20 bit to 0 2 wait state Set the PLCO7 bit to 1 PLL operation AA E Wait until the PLL clock becomes stable tsu PLL 2 Set the CM11 bit to 1 PLL clock for the CPU clock source NOTE 1 PLL operation mode can be entered from high speed mode Figure 7 11 Procedure to Use PLL Clock as CPU Clock Source Rev 1 10 Jul01 2005 page 46 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 7 Clock Generating Circuit 7 2 CPU Clock and Peripheral Function Clock Two type clocks CP
465. y 20 or more clock cycles to the XIN pin 5 Apply H to the RESET pin 5 2 Software Reset The microcomputer resets pins the CPU and SFR when the PMO3 bit in the PMO register is set to 1 microcomputer reset Then the microcomputer executes the program in an address determined by the reset vector Set the PMOS bit to 1 while the main clock is selected as the CPU clock and the main clock oscillation is stable In the software reset the microcomputer does not reset a part of the SFR Refer to 4 SFR for details 5 3 Watchdog Timer Reset The microcomputer resets pins the CPU and SFR when the PM12 bit in the PM1 register is set to 1 reset when watchdog timer underflows and the watchdog timer underflows Then the microcomputer executes the program in an address determined by the reset vector In the watchdog timer reset the microcomputer does not reset a part of the SFR Refer to 4 SFR for details 5 4 Oscillation Stop Detection Reset The microcomputer resets and stops pins the CPU and SFR when the CM27 bit in the CM2 register is 0 reset at oscillation stop re oscillation detection if it detects main clock oscillation circuit stop Refer to 7 5 Oscillation Stop and Re Oscillation Detection Function for details In the oscillation stop detection reset the microcomputer does not reset a part of the SFR Refer to 4 SFR for details Rev 1 10 Jul01 2005 page 29 of 318 RENESAS REJ09B0124 0110 Under development Thi
466. y be set to 0 The DMAS bit may be set to 1 when the DMS or the DSEL3 to DSELO bits change state Therefore always be sure to set the DMAS bit to 0 after changing the DMS or the DSEL3 to DSELO bits Because if the DMAE bit is 1 a data transfer starts immediately after a DMA request is generated the DMAS bit in almost all cases is 0 when read in a program Read the DMAE bit to determine whether the DMAC is enabled Table 11 4 Timing at Which DMAS bit Changes State DMA Fact DMAS Bit in DMiCON Register SS Timing at which the bit is set to 1 Timing at which the bit is set to 0 Software Trigger When the DSR bit in the DMISL register e Immediately before a data transfer starts is set to 1 When set by writing 0 in a program Peripheral Function When the interrupt control register for the peripheral function that is selected by the DSEL3 to DSELO and DMS bits in the DMISL register has its IR bit set to 1 i20 1 Rev 1 10 Jul01 2005 page 90 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents are subject to change M16C 6N Group M16C 6NK M16C 6NM 11 DMAC 11 5 Channel Priority and DMA Transfer Timing If both DMAO and DMA1 are enabled and DMA transfer request signals from DMAO and DMA1 are detected active in the same sampling period one period from a falling edge to the next falling edge of BCLK the DMAS bit on each
467. y even address in the user ROM area xx High order 8 bits of command code ignored NOTE 1 It is only blocks 0 to 12 that can be erased by the erase all unlocked block command Block A cannot be erased The block erase command must be used to erase the block A 20 3 5 1 Read Array Command FFh The read array command reads the flash memory By writing command code xxFFh in the first bus cycle read array mode is entered Content of a specified address can be read in 16 bit unit after the next bus cycle The microcomputer remains in read array mode until another command is written Therefore contents from multiple addresses can be read consecutively 20 3 5 2 Read Status Register Command 70h The read status register command reads the status register refer to 20 3 7 Status Register SRD Register for detail By writing command code xx70h in the first bus cycle the status register can be read in the second bus cycle Read an even address in the user ROM area Do not execute this command in EW1 mode 20 3 5 3 Clear Status Register Command 50h The clear status register command clears the status register By writing xx50h in the first bus cycle the FMRO7 FMRO6 bits in the FMRO register are set to 00b and the SR5 SR4 bits in the status register are set to 00b Rev 1 10 Jul01 2005 page 250 of 318 RENESAS REJ09B0124 0110 Under development This document is under development and its contents ar

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