Quatech ES-100 Network Card User Manual
Contents
1. RTS 5 5 CTS CTS 5 20 DTR DSR 20 20 DTR DTR 20 6 DSR DTR 6 6 DSR DSR 6 8 DCD DCD 8 8 DCD DCD 8 22 R RI 22 22 RI RI 22 7 GND GND 7 7 GND GND 7 Typical DTE to DCE cable Typical DTE to DTE null modem cable Figure 10 Cabling requirements for RS 232 C devices cables using 25 pin connectors shown Quatech ES 100D User s Manual 9 Channel Output Configuration The ES 100D connects to peripheral eguipment through a single female D 78 connector or using the adapter cable eight male D 25 connectors The standard serial port connections are listed in Figure 11 Unlisted pins are not used and not connected RS 232 Signal Serial 1 Serial 2 Serial 3 Serial 4 Description 578 D 25 p 78 p25 D 78 D 25 D 78 D 25 TxD a d2 EC EIERE 16 2 RxD 1 3 40 3 6 3 Jas 3 RTS 2 gelach a 7 4 4 4 CTS TANE NE el s l s5 DTR lr a anal a 2 DSR Al a Maier DCD 4 8 4 8 9 8 4 8 RI WIES lz Il Gon a 22 GND 5 SEET dee las 3 RS 232 Signal Serial 5 Serial 6 Serial 7 Serial 8 Description D78 D 25 D 78 D 25 D 78 D 25 D 78 D 25 TxD a eme ae ee res RxD u3 a ee a RTS 2I a Jost ca ae ae e A CTS 322. C GUATECH ES 100 EIGHT CHANNEL RS 232 ASYNCHRONOUS ADAPTER CARD for ISA compatible machines INTERFACE CARDS FOR IBM PC AT AND PS 2 User s Manual QUATECH INC TEL 330 655 9000 5675 Hudson Industrial Parkway FAX 330 655 9010 Hudson Ohio 44236 http www guatech com Warranty Information Quatech Inc warrants the ES 100 to be free of defects for one 1 year from the date of purchase Quatech Inc will repair or replace any adapter that fails to perform under normal operating conditions and in accordance with the procedures outlined in this document during the warranty period Any damage that results from improper installation operation or general misuse voids all warranty rights The authors have taken due care in the preparation of this document and any associated software program s In no event will Quatech Inc be liable for damages of any kind incidental or consequential in regard to or arising out of the performance or form of the materials presented herein and in the program s accompanying this document No representation is made regarding the suitability of this product for any particular purpose Quatech Inc reserves the right to edit or append to this document or the product s to which it refers at any time and without notice Please complete the following information and retain for your records Have this information available when requesting warranty service Date of purchase
3. 5 oz cs als 5 DTR 13 20 52 20 38 20 57 20 DSR 3 l e ee Mee l e v DCD 4 8 53 8 19 8 58 8 RI spe e 28h 8 15 GND 5 Me TRUE zer EU ES Figure 11 ES 100D connector definitions 10 Quatech ES 100D User s Manual OOODOOGOOODOOOO OOOOOOOOOOOOO D 25 connectors on the adapter cable 00000000000600000000 G90600900000000000000 0O0G000900000000600600009 D 78 connector Dashed lines delineate channels Pins 25 30 35 64 69 74 unused Figure 12 ES 100D output connectors 11 Quatech ES 100D User s Manual 6 SERIAL PORT FUNCTIONAL DESCRIPTION This section contains information intended for advanced users planning to do custom programming with the ES 100D The information presented here is a technical description of the interface to the 16450 or 16550 UART The 16450 UART is an improved functional equivalent of the 8250 UART performing serial to parallel conversion on received data and parallel to serial conversion on output data Designed to be compatible with the 16450 the 16550 UART enters character non FIFO mode on reset In this mode the 16550 appears as a 16450 to application software An additional mode FIFO mode can be invoked through software to reduce CPU overhead FIFO mode increases performance by providing two 16 byte hardware buffers one for transmit and one for receive This can reduce the frequency of interrupts is
4. To select a different IRQ move the jumper to the appropriate position on J2 IRQ3 IRQ4 RQ5 IRQ6 IRG7 IRQ10 IRQ11 IRQ12 IRQ14 wh Co AR wech Wu o bh N 00 co N o N Q OBR na O O O O O O O 20 OB pos J2 Default is IRQ 3 Figure 6 Interrupt level IRQ selection Interrupt Sharing All ports on the ES 100D share the same interrupt level In addition an interrupt sharing circuit allows the ES 100D to share its interrupt with another Quatech adapter supporting sharable interrupts In either case the software driving the serial ports must determine which port or ports are requesting service when an interrupt is generated The ES 100D signals a hardware interrupt when any port requires service The interrupt signal is maintained until no port requires service Because the ISA bus is edge sensitive this behavior forces the interrupt service routine to ensure that all ports are checked before exiting A way to do this is to poll each port until an interrupting port is found After servicing the port all ports should be checked again If any interrupting port is left unserviced the ES 100D will be unable to signal any further interrupts Interrupt Status register The ES 100D is equipped with an interrupt status register which can be used to simplify the servicing of shared interrupts If this feature is enabled the read only interrupt status register is accessed i
5. 100 Manual
6. 8 TROUBLESHOOTING Listed here are some common problems and freguent causes of those problems Suggestions for corrective action are given If the information here does not provide a solution contact Ouatech Customer Service for technical support Any unauthorized repairs or modifications will void the ES 100D s warranty Computer will not boot up 1 Is the ES 100D properly inserted Remove the card and try again Perhaps try a different expansion slot 2 Is the base address correctly set Check for address conflicts with other devices in the system Remember that the ES 100D requires 64 bytes of I O space Set a different address if necessary 3 The ES 100D may be defective Contact Quatech Customer Service for instructions Cannot communicate with other equipment 1 Are the cable connections correct Are the cables securely attached 2 Arethe base address and interrupt level IRQ correctly set Check for address and IRQ conflicts with other devices in the system Change the settings if necessary 3 If you are trying to communicate with a DTE a null modem cable may be required 4 If possible use a loopback connector to test the port This connector needs to connect the following sets of signals on a D 25 connector TxD and RxD pins 2 and 3 RTS and CTS pins 4 and 5 DCD DTR DSR and RI pins 8 20 6 and 22 Quatech ES 100D User s Manual 25 Version 1 01 March 2004 Part No 940 0099 101 Ouatech Inc ES
7. RxRDY and TxRDY change from mode 0 to mode 1 for DMA transfers DMA mode is not supported on the ES 100D 2 IXRST Transmit FIFO reset 16550 only When set logic 1 all bytes in the transmitter FIFO are cleared and the counter is reset The shift register is not cleared XRST is self clearing 1 RRST Receive FIFO reset 16550 only When set logic 1 all bytes in the receiver FIFO are cleared and the counter is reset The shift register is not cleared RRST is self clearing 0 FE FIFO enable 16550 only When set logic 1 enables transmitter and receiver FIFOs When cleared logic 0 all bytes in both FIFOs are cleared This bit must be set when other bits in the FIFO control register are written to or the bits will be ignored Figure 17 16550 FIFO Control Register bit definitions 16 Quatech ES 100D User s Manual LINE CONTROL REGISTER This register is located at UO address base 3 It is used for specifying the format of the asynchronous serial data to be processed by the UART and to set the Divisor Latch Access Bit DLAB allowing access to the baud rate divisor latches BIT DESCRIPTION 7 DLAB Divisor latch access bit DLAB must be set to logic 1 to access the baud rate divisor latches DLAB must be set to logic 0 to access the receiver buffer transmitting holding register and interrupt enable register 6 BKCN Break control When set log
8. current states of modem control signals to be sensed These signals include the DCD Data Carrier Detect RI Ring Indicator DSR Data Set Ready and CTS Clear To Send The Modem Status Register also provides change information for each of these signals When a modem control signal changes state the appropriate change bit is set to logic 1 The change bits 3 2 1 and 0 are reset to logic 0 whenever the Modem Status Register is read A modem status interrupt is generated whenever any of bits 3 2 1 or 0 is set by the UART to a logic 1 BIT DESCRIPTION 7 DCH Data carrier detect Complement of the DCD input 6 RI Ring indicator Complement of the RI input 23 DSR Data set ready Complement of the DSR input 4 CTS Clear to send Complement of the CTS input 3 DDCD Delta data carrier detect Indicates the Data Carrier Detect input has changed state Cleared when this register is read 2 TERI Trailing edge ring indicator Indicates the Ring Indicator input has changed from a low to a high state Cleared when this register is read 1 DDSR Delta data set ready Indicates the Data Set Ready input has changed state Cleared when this register is read 0 DCTS Delta clear to send Indicates the Clear to Send input has changed state Cleared when this register is read Figure 21 Modem Status Register bit definitions SCRATCHPAD REGISTER Th
9. in which the ES 100D is to be installed 3 Remove the system cover according to the instructions provided by the computer manufacturer 4 Install the ES 100D in any vacant expansion slot The board should be secured by installing the Option Retaining Bracket ORB screw 5 Replace the system cover according to the instructions provided by the computer manufacturer Attach and secure the cable connectors to the desired equipment 2 Quatech ES 100D User s Manual zr aJay 949 OHI 19S 20202020 0200 2270 001 S3 ONI Ho31vno OSS9L OSP9L OSS9L OSPOL ms LMS 0gg91 0S79 0SS9L 0Sv9 0SS9L 0Gv9l OSS9L OSPOL 0Sg91 0S79 0SS9L 0Sv9 ot EL LL y N 9 E y E N o zms LMS M I 9Jeu sesseJppe Joe JUUL JJ UL n I 1000 ejeos oj jou wespe Quatech ES 100D User s Manual 3 ADDRESSING PORTS Setting the address The base address of the ES 100D is set using the two DIP switch packs When setting the address selection switches a switch in the ON position specifies that the corresponding address line must be a logic 0 for the port to be selected Similarly a sw
10. Model Number ES 100 Product Description Eight Channel RS 232 Asynchronous Communication ISA Adapter Serial Number Quatech Inc ES 100 Manual The information contained in this document cannot be reproduced in any form without the written consent of Quatech Inc Likewise any software programs that might accompany this document can be used only in accordance with any license agreement s between the purchaser and Quatech Inc Quatech Inc reserves the right to change this documentation or the product to which it refers at any time and without notice The authors have taken due care in the preparation of this document and every attempt has been made to ensure its accuracy and completeness In no event will Quatech Inc be liable for damages of any kind incidental or consequential in regard to or arising out of the performance or form of the materials presented in this document or any software programs that might accompany this document Quatech Inc encourages feedback about this document Please send any written comments to the Technical Support department at the address listed on the cover page of this document Copyright 2004 by Quatech Inc 5675 Hudson Industrial Parkway Hudson Ohio 44236 AI rights reserved Printed in the U S A Quatech Inc ES 100 Manual Compliances Electromagnetic Emissions EC Council Directive 89 336 EEC This eguipment has been tested and found to comply with the limits of the f
11. d into the FIFO and transfers are disabled until the serial data input goes to the mark state logic 1 and a valid start bit is received 3 FE Framing error Indicates the received character had an invalid stop bit The stop bit following the last data or parity bit was a 0 bit spacing level 2 PE Parity error Indicates that the received data does not have the correct parity 1 OE Overrun error Indicates the receive buffer was not read before the next character was received and the character is destroyed In 16550 FIFO mode indicates the receive FIFO is full and another character has been shifted in The character in the shift register is destroyed but is not transferred to the FIFO 0 DR Data ready Indicates data is present in the receive buffer or FIFO 16550 DR is reset by reading the receive buffer register or receiver FIFO Figure 20 Line Status Register bit definitions Bits BI FE PE and OE are the sources of receiver line status interrupts The bits are reset by reading the line status register In 16550 FIFO mode these bits are associated with a specific character in the FIFO and the exception is revealed only when that character reaches the top of the FIFO Quatech ES 100D User s Manual 19 MODEM STATUS REGISTER This register is located at I O address base 6 It reports on the status of signals coming from the modem or equipment used in place of a modem It allows the
12. dicates FIFO mode enabled Always logic 0 for the 16450 6 FFE FIFO enable 16550 only When logic 1 indicates FIFO mode enabled Always logic 0 for the 16450 0 reserved TID2 Interrupt Identification 5 4 0 reserved 3 2 Jun Indicates highest priority interrupt pending if any See Figure 16 JjHDO NOTE IID2 is always a logic 0 on the 16450 or in non FIFO mode on the 16550 0 IP Interrupt pending When logic 0 indicates that an interrupt is pending and the contents of the interrupt identification register may be used to determine the interrupt source See Figure 16 Figure 15 Interrupt Identification Register bit definitions Figure 16 gives the detail of the IIDx bits in the Interrupt Identification Register These bits are examined to determine the source of an interrupt IIDx bits IP Priority Interrupt Type 1 N A None 0 1st Receiver Line Status Indicates overrun parity framing errors or break interrupts The interrupt is cleared by reading the line status register 0 2nd Received Data Ready 16450 or 16550 Indicates receive data available The interrupt is cleared by reading the receive buffer In 16550 FIFO mode indicates the receiver FIFO trigger level has been reached The interrupt is reset when the FIFO drops below the trigger level 0 2nd Character Timeout 16550 FIFO mode only Indicates no characters have been remo
13. eared when a character is written to the FIFO or when the Interrupt Identification Register is read Transmitter FIFO empty indications are delayed by one character time less the last stop bit time when the transmitter holding register is empty and there have not been at least two bytes together in the transmit FIFO since the last time the transmitter holding register was empty The first transmitter interrupt after enabling the FIFO mode will be immediate if that interrupt is enabled Quatech ES 100D User s Manual 21 FIFO polled mode operation 76550 UART only The receiver and transmitter are operated independently which would allow either or both to be used in a polled mode rather than using interrupts to determine when the UART needs to be serviced To use the UART in a polled mode the software is responsible for continuously checking for the conditions that normally cause interrupts to occur This would be done using the Line Status Register 1 The Data Ready bit will be set to logic 1 whenever there is at least one byte in the receive FIFO 2 Errors can be detected using the various error bits 3 The Transmitter Holding Register Empty bit can be used to determine when the transmit FIFO is empty 4 The Transmitter Empty bit indicates that the transmitter shift register is empty as well as the transmit FIFO being empty 5 Trigger levels and FIFO timeouts do not apply Both FIFOs are fully capable of holding multiple cha
14. ic 1 the serial output SOUT is forced to the spacing state logic 0 5 STKP Stick parity Forces parity to logic 1 or logic 0 if STKP EPS PEN PARITY parity is enabled X X 0 None 4 EPS Even parity select 0 e Odd eg NC 0 1 1 Even Selects even or odd parity if parity is enabled i o Logic 1 1 1 1 Logic 0 3 PEN Parity enable Enables parity on transmission and verification on reception 2 STB Number of stop bits Sets the number of stop bits STB WLS1 WLS0 WORD LEN STOP BITS transmitted 0 0 0 5 bits 1 0 0 1 6 bits 1 0 1 0 7 bits 1 0 1 1 8 bits 1 1 0 0 5 bits 1 5 1 0 1 6 bits 2 1 1 0 7 bits 2 1 1 1 8 bits 2 1 WLS1 Word length select Determines the number 0 e Mt of bits per transmitted word Figure 18 Line Control Register bit definitions Quatech ES 100D User s Manual 17 MODEM CONTROL REGISTER This register is located at I O address base 4 and is used to control the interface with the modem or device used in place of a modem This register allows the states of the modem control signals to be changed These are DTR Data Terminal Ready and RTS Reguest To Send It is also possible to place the UART in a loopback mode for testing Finally the user defined outputs OUTI and OUT2 are controlled from this register The ES 100D handles the OUTI and OUT2 signals in the manner appropriate for maintaining compatibility with standard PC serial ports The OUTI output is not c
15. is register is located at UO address base 7 It is not used by the 16450 or 16550 It may be used by the programmer for temporary data storage The Scratchpad Register is eight bits wide and can be read or written 20 Quatech ES 100D User s Manual FIFO INTERRUPT MODE OPERATION 76550 UART only When the receiver FIFO and receiver interrupts are enabled The receive data interrupt is issued when the receive FIFO reaches the trigger level The interrupt is cleared as soon as the receive FIFO falls below the trigger level The Interrupt Identification Register s receive data available indicator is set and cleared along with the receive data interrupt when the receive FIFO falls below the trigger level The data ready indicator is set as soon as a character is transferred into the receiver FIFO and is cleared when the FIFO is empty A FIFO timeout interrupt will occur if the receive FIFO contains at least one character at least four character times have passed since receipt of the last character and the last read of the FIFO by the CPU was done more than four character times ago Timeout interrupts are cleared when a read of the receive FIFO is done The receive FIFO timeout timer is reset whenever a new character is received into the FIFO or a read of the FIFO is done When the transmit FIFO and transmit interrupts are enabled l The transmitter holding register empty interrupt occurs when the transmit FIFO is empty and is cl
16. itch in the OFF position forces the corresponding address line to be a logic 1 for the port to be selected A full sixteen bit address decode is implemented to reduce the chance of address conflicts with other adapters in the system The base address of the ES 100D can be set anywhere in the range of 0000 hex to FFFF hex Each serial port on the ES 100D uses 8 consecutive I O locations The ports reside in a contiguous block of I O space in eight byte increments for a total of 64 contiguous bytes This is shown in Figure 3 PORT ADDRESS RANGE Serial 1 Base Address 0 to Base Address 7 Serial 2 Base Address 8 to Base Address 15 Serial 3 Base Address 16 mo Base Address 23 Serial 4 Base Address 24 to Base Address 31 Serial 5 Base Address 32 to Base Address 39 Serial 6 Base Address 40 to Base Address 47 Serial 7 Base Address 48 to Base Address 55 Serial 8 Base Address 56 to Base Address 63 Figure 3 Port address map Switch SW1 and the first four positions of switch SW2 select address lines A15 through A6 The fifth position of SW2 is not used The remaining address lines A5 AO are used by the UART to select the register being accessed The sixth position on SW2 is used to enable or disable the interrupt status register see page 7 Figure 4 shows how the switches on the ES 100D represent the address values for serial ports This figure can be used to explain the e
17. leared logic 0 the DTR output is forced inactive to a logic 1 Bv o yu Figure 19 Modem Control Register bit definitions 18 Quatech ES 100D User s Manual LINE STATUS REGISTER This register is located at I O address base 5 It is used to provide Various types of status information concerning the data transfer As Figure 20 shows the Line Status Register indicates several types of errors an empty transmit buffer a ready receive buffer or a break on the receive line BIT DESCRIPTION 7 FFRX Error in RCVR FIFO 16550 FIFO mode only Always logic 0 in 16450 or 16550 non FIFO mode Indicates one or more parity errors framing errors or break indications in the receiver FIFO FFRX is reset by reading the line status register 6 TEMT Transmitter empty Indicates the transmitter holding register or FIFO 76550 AND the transmitter shift register are empty and are ready to receive new data TEMT is reset by writing a character to the transmitter holding register 5 THRE Transmitter holding register empty Indicates the transmitter holding register or FIFO 76550 is empty and it is ready to accept new data THRE is reset by writing data to the transmitter holding register 4 BI Break interrupt Indicates the receive data input has been in the spacing state logic 0 for longer than one full word transmission time In 76550 FIFO mode only one zero character is loade
18. n place of the scratchpad of any given UART at base address 7 Virtually no commercially available software makes use of the scratchpad register The choice of using the interrupt status register or the UART scratchpads is made using position 6 of switch SW2 as shown in Figure 7 6 Quatech ES 100D User s Manual SW2 SW2 Interrupt Status Register Scratchpad Register Slide position 6 of SW2 toward the top of the ES 100D to enable the interrupt status register or toward the bottom of the ES 100D to disable it Figure 7 Enabling the Interrupt Status Register When a hardware interrupt occurs reading the interrupt status register will return the interrupt status of the entire ES 100D as shown in Figure 8 Individual bits are cleared as the interrupting ports are serviced The interrupt service routine must ensure that the interrupt status register reads zero before exiting or the ES 100D will be unable to signal subsequent interrupts An I O write to the interrupt status register will cause another hardware interrupt to be generated if the interrupt status register is non zero The value written is ignored and has no effect on the contents of the interrupt status register BIT DESCRIPTION 7 MSB 1 if interrupt pending on Serial 8 6 1 if interrupt pending on Serial 7 1 if interrupt pending on Serial 6 1 if inter
19. ny bit to a logic 1 enables that particular interrupt BIT DESCRIPTION 7 0 reserved 6 0 reserved 5 0 reserved 4 0 reserved 3 EDSSI MODEM Status Interrupt When set logic 1 enables interrupt on clear to send data set ready ring indicator and data carrier detect 2 ELSI Receiver Line Status Interrupt When set logic 1 enables interrupt on overrun parity framing errors and break indication ETBEI Transmitter Holding Register Empty Interrupt When set logic 1 enables interrupt on transmitter holding register empty 0 ETBEI Received Data Available Interrupt When set logic 1 enables interrupt on received data available For 16550 FIFO mode interrupts are also enabled for receive FIFO trigger level reached and for receive timeout Figure 14 Interrupt Enable Register bit definitions INTERRUPT IDENTIFICATION REGISTER This read only register is located at I O address base 2 When this register is read the UART freezes all interrupts and indicates the highest priority interrupt During this time new interrupts are detected by the UART but are not reported in this register until the access completes For the 76550 only this register can be used to indicate whether the FIFO mode is engaged by examining bits 6 and 7 14 Ouatech ES 100D User s Manual BIT DESCRIPTION 7 FFE FIFO enable 16550 only When logic 1 in
20. ollowing standards for a digital device EN50081 1 EN55022 EN60555 2 EN60555 3 ENS50082 1 IEC 801 2 IEC 801 3 IEC 801 4 Type of Eguipment Information Technology Eguipment Eguipment Class Commercial Residential amp Light Industrial FCC Class B This equipment has been tested and found to comply with the limits for a Class B digital device pursuant to part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one or more of the following measures e Reorient or relocate the receiving antenna Increase the separation between the equipment and receiver Connect the equipment into an outlet on a circuit different from that to which the receiver is connected Consult the dealer or an or an experienced radio TV technician for help This equipment has been certified to comply with the limits for a Class B computing device pursuant to FCC Rules In order
21. onnected The OUT2 output is used to globally enable interrupts to the computer It should be active at all times if interrupts are being used BIT DESCRIPTION 0 reserved 0 reserved 0 reserved LOOP Loopback enable When set logic 1 the transmitter shift register is connected directly to the receiver shift register The MODEM control inputs are internally connected to the MODEM control outputs and the outputs are forced to the inactive state All characters transmitted are immediately received to verify transmit and receive data paths Transmitter and receiver interrupts still operate normally MODEM control interrupts are available but are now controlled through the MODEM control register 3 OUT2 Output 2 When this bit is set logic 1 the OUT2 output is forced active to a logic 0 When cleared logic 0 the OUT2 output is forced inactive to a logic 1 Used for interrupt enable on the ES 100D 2 OUTI Output 1 When this bit is set logic 1 the OUTI output is forced active to a logic 0 When cleared logic 0 the OUTI output is forced inactive to a logic 1 Not connected on the ES 100D 1 RTS Request to send When this bit is set logic 1 the RTS output is forced active to a logic 0 When cleared logic 0 the RTS output is forced inactive to a logic 1 0 DTR Data terminal ready When this bit is set logic 1 the DTR output is forced active to a logic 0 When c
22. orts on the ES 100D share one interrupt level A special interrupt status register is provided to allow controlling software to manage the shared interrupt level The shared interrupt feature minimizes the system resources consumed by the adapter In order to support the use of the shared interrupt feature of the ES 100D Quatech has developed device drivers for several popular operating systems and environments The sales department can be contacted for details on current offerings Quatech ES 100D User s Manual 1 2 INSTALLATION If the default address and interrupt settings are sufficient the ES 100D can be guickly installed and put to use The factory defaults are listed in Figure 1 PORT ADDRESS IRO Serial 1 300 hex 3 Serial 2 308 hex 3 Serial 3 310 hex 3 Serial 4 318 hex 3 Serial 5 320 hex 3 Serial 6 328 hex 3 Serial 7 330 hex 3 Serial 8 338 hex 3 Figure 1 Default address and IRO settings for ES 100D The output of the ES 100D is a 78 pin D connector A cable is provided to convert the D 78 into eight standard male D 25 connectors with all control signals provided to each port RTS DTR CTS DSR DCD and RI See section V of this manual for connector details 1 Ifthe default settings are correct skip to step 2 otherwise refer to sections III and IV of this document for detailed information on how to set the address and IRQ level 2 Turn off the power of the computer system
23. racters at any time 22 Quatech ES 100D User s Manual BAUD RATE SELECTION The 16450 or 16550 UART determines the baud rate of the serial output using a combination of the clock input freguency and the value written to the divisor latches Standard personal computer serial interfaces use an input clock of 1 8432 MHz A table of baud rates available is given in Figure 22 DESIRED BAUD DIVISOR LATCH ERROR BETWEEN DESIRED AND ACTUAL RATE VALUE VALUES 50 2304 75 1536 110 1047 0 026 150 768 300 384 600 192 1200 96 1800 64 2000 58 0 69 2400 48 3600 32 4800 24 7200 16 9600 12 19200 6 38400 3 56000 2 2 86 Figure 22 Divisor Latch settings for common baud rates using 1 8432 MHz input clock Quatech ES 100D User s Manual 23 SPECIFICATIONS Bus interface Industry Standard Architecture ISA 16 bit bus IBM PC AT compatible Dimensions 13 4 x 4 2 Serial ports Number of ports eight Controllers 16450 16550 optional Interface Female high density D 78 connector or eight male D 25 connectors using optional adapter cables Transmit drivers MC1488 or compatible Receive buffers MC1489 or compatible I O Address range 0000H FFFFH Interrupt levels IRQ2 to IRQ7 IRO10 to IRQ12 IRO14 IRO15 Power reguirements 5 volts 450 mA 12 volts 90 mA 12 volts 90 mA Ouatech ES 100D User s Manual
24. rupt pending on Serial 5 1 if interrupt pending on Serial 3 1 if interrupt pending on Serial 2 5 4 3 1 if interrupt pending on Serial 4 2 1 0 1 if interrupt pending on Serial 1 Figure 8 Interrupt Status Register contents Quatech ES 100D User s Manual This page intentionally left blank Ouatech ES 100D User s Manual S EXTERNAL CONNECTIONS RS 232 C devices are classified by their function as either Data Terminal Eguipment DTE or Data Communication Eguipment DCE Generally data terminal eguipment is defined as the communication source and data communication eguipment is defined as the device that provides a communication channel between two DTE type devices Terminal Modem RS 232 C DTE DCE Telephone line Terminal Modem RS 232 C DTE DCE Figure 9 Use of DTEs and DCEs in a communications link DTE and DCE type devices have complementary pinouts to allow terminals and modems to be connected directly using a one to one cable as shown in Figure 10 In many applications DCEs are unnecessary and in these cases a cable called a null modem cable or modem eliminator cable is used to directly connect two DTE type devices A typical null modem cable is also shown in Figure 10 3 RxD TxD 3 3 RxD RxD 3 2 TxD RxD 2 2 TxD A TxD 2 4 RTS CTS 4 4 RTS RTS 4 5 CTS
25. sued to the CPU by the UART Other features of the 16450 and 16550 include Programmable baud rate character length parity and number of stop bits Automatic control of start stop and parity bits Independent and prioritized interrupts Transmit clock output receive clock input The ES 100D s serial ports are controlled by 16450 or 16550 UARTs The serial ports will generate interrupts in accordance with the bits set in the interrupt enable register of the UARTs In order to maintain compatibility with earlier personal computer systems the user defined output OUT2 is used as an external interrupt enable and must be set active for interrupts to be generated OUT2 is accessed through the UART s MODEM control register The following pages provide a brief summary of the internal registers available within the 16450 and 16550 UARTs Registers and functions specific to the 16550 will be indicated with boldface italic notations 12 Quatech ES 100D User s Manual Accessing the Serial Port registers Figure 13 lists the address map for the 16450 and 16550 UARTs Each register can be accessed by reading from or writing to the proper O address This I O address is determined by adding an offset to the base address set for the particular serial port The base address is set using DIP switches on the ES 100D see section III Notice that two locations access different registers depending on whether an I O read or VO write is at
26. tempted Address base 0 accesses the receive buffer on an I O read or the transmit buffer on an I O write Address base 2 accesses the Interrupt Identification register on an I O read or the FIFO control register 16550 only on an I O write Also notice that if address base 0 or base 1 is used with the DLAB bit from the Line Control Register set to 1 the baud rate divisor latches are accessed NOTE All figures displaying bitmapped registers are formatted such that bit 7 is the high order bit UART Addressing Register Description DLAB I O Address 0 Base 0 Receive buffer read Transmit holding register write 0 Base 1 Interrupt enable X Base 2 Interrupt identification read 16450 and 16550 FIFO control write 16550 only X Base 3 Line control X Base 4 MODEM control X Base 5 Line status X Base 6 MODEM status X Base 7 Scratchpad 1 Base 0 Baud rate divisor latch LSB 1 Base 1 Baud rate divisor latch MSB X don t care DLAB in Line Control Register must be set to access baud rate divisor latch Figure 13 Serial port register address map for 16450 16550 UART Quatech ES 100D User s Manual 13 INTERRUPT ENABLE REGISTER This register is located at UO address base 1 It enables the five types of UART interrupts Interrupts can be totally disabled by setting all of the enable bits in this register to a logic 0 Setting a
27. to maintain compliance with FCC regulations shielded cables must be used with this equipment Operation with non approved equipment or unshielded cables is likely to result in interference to radio and TV reception The user is cautioned that changes and modifications made to the equipment without the approval of the manufacturer could void the user s authority to operate this equipment ES 100 User s Manual Quatech Inc ES 100 Manual 1 GENERAL INFORMATION The Quatech Inc ES 100D provides eight RS 232 asynchronous serial communication interfaces for IBM compatible personal computer systems using the 16 bit ISA Industry Standard Architecture expansion bus The ES 100D s serial ports are implemented using 16450 Universal Asynchronous Receiver Transmitters UARTs For higher performance 16550 UARTS can be installed in place of the 16450 UARTs The 16550 contains a hardware buffer that reduces processing overhead Software must be aware of the 16550 UART for the device s extra capabilities to be used otherwise it will act as a 16450 UART The 16550 is suggested for multitasking environments and for applications involving high data rates The ES 100D is highly flexible with respect to addressing and interrupt level use The serial ports are addressed in a contiguous block that can be placed anywhere within the range of 0000 hex to FFFF hex and available interrupt levels include IRQ2 to IRQ7 IRQ10 to IRQ12 IRQ14 or IRQI15 AI p
28. ved from or input to the receiver FIFO for the last four character times and there is data present in the receiver FIFO The interrupt is cleared by reading the receiver FIFO 0 3rd Transmitter Holding Register Empty Indicates the transmitter holding register is empty The interrupt is cleared by reading the interrupt identification register or writing to the transmitter holding register Indicates transmit FIFO empty for 16550 0 4th MODEM Status Indicates clear to send data set ready ring indicator or data carrier detect have changed state The interrupt is cleared by reading the MODEM status register Figure 16 Interrupt Identification Register bit decoding Quatech ES 100D User s Manual 15 FIFO CONTROL REGISTER 76550 only This register which applies only to the 16550 UART is a write only register located at I O address base 2 It is used to enable the FIFO mode clear the FIFOs set the threshold level for the receive FIFO to generate interrupts and to set the mode under which the device uses DMA Note that DMA mode is NOT supported by the ES 100D BIT DESCRIPTION 7 RXT1 Receiver FIFO Trigger Level 16550 only 6 RXTO Determines the trigger level for the receiver FIFO interrupt RXTI RXTO Receiver FIFO trigger level bytes 0 0 1 0 1 4 1 0 8 1 1 14 5 0 reserved 4 0 reserved DMAM DMA mode select 16550 only When set logic 1
29. xamples shown in Figure 5 4 Quatech ES 100D User s Manual A serial port s address is a 16 bit quantity that is most often expressed in four hexadecimal base 16 digits A hex digit can hold a value from 0 to 15 decimal and is made up of four binary bits given weights of eight four two and one hence the maximum value of 8 4 2 1 15 A possible serial port address is 5240 hex The example below shows how the hex digits are broken down into binary bits Binary bits 0101 0010 0100 0000 Bit weight 8421 8421 8421 8421 Sum of bits 0 4 0 1 0 0 2 0 0 4 0 0 0 0 0 0 Hex digits 5 2 4 0 These address bits are set by the switches All other bits are considered to be zero 0101 0010 0100 0000 Switch on Switch off A5 A0 are zero for the base address bit 0 bit 1 Position 5 of SW2 is not used Position 6 of SW2 is used to enable or disable the interrupt status register Factory default setting 0300 hex SW1 SW2 Another Example 5ACO hex SW1 SW2 Quatech ES 100D User s Manual 5 4 INTERRUPT LEVEL IRO The ES 100D allows the use of any interrupt level in the range IRQ2 to IRQ7 IRQ10 to IRQ12 IRQ14 or IRQIS selected using jumper pack J2 In Figure 6 the factory default setting of IRQ3 is shown
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