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PMC-Sierra PM5349 Network Router User Manual

1. oe T DI M Al BALL CORNER D Al BALL 252119 17 15 I ll 9 7 8 3 1 CORNER EB 222018 1614 12 10 8 6 4 2 T o 30 S c A S B m NE o JA pi Al BALL 1 T b gt INK MARK E 9 L K E EI N R Al uy 5 AC t L 0 127 A ux e TOP VIEW F A A2 NM ZEE BOTTOM VIEW IUJUUUEUUUHUUUHUUUNSUUUNUU DIE SIDE iiic DAN MCA d olaaa EC SIDE VIE Tar SEATING PLANE Bie im Notes 1 ALL DIMENSIONS IN MILLIMETER 2 DIMENSION AAA DENOTES COPLANARITY 3 DIMENSION BBB DENOTES PARALLEL A A SECTION VIEW 4 DIMENSION ccc DENOTES FLATNESS PACKAGE TYPE 04 PIN THERMAL BALL GRID ARRAY BODY SIZE 31 x 31 x 1 45 MM Dim A Al A2 D DI E El MN b BBB CCC DDD MIN 1 41 0 56 0 85 50 90 27 84 50 90 27 84 0 60 0 15 0 20 Nom 1 54 0 63 0 91 151 00 27 94151 00 27 94425 25 1 27 0 75 0 33 0 50 1 67 0 70 0 97 51 10 28 04 51 10 28 04 0 90 0 15 0 15 0 20 0 50 0 55 Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 244 F2 MC PMC Serta NG PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD NOTES Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use
2. PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Alarm Description LOS Loss of signal LOF Loss of frame OOF Out of Frame LAIS Line Alarm Indication Signal LRDI Line Remote Defect Indication SDBER Signal Degrade Bit Error Rate SFBER Signal Fail Bit Error Rate LOP Loss of Pointer LCD Loss of cell delineation PAIS Path Alarm Indication Signal PRDI Path Remote Defect Indication PERDI Path Enhanced Remote Defect Indication PSLM Path Signal Label Mismatch Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 174 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register OxEO RASE Interrupt Enable Bit Type Function Default Bit 7 R W PSBFE 0 Bit 6 R W COAPSE Bit 5 R W 21 51 Bit 0 R W Unused SDBERE The SDBERE bit is the interrupt enable for the signal degrade threshold alarm When SDBERE is a logic one an interrupt is generated when the SD alarm is declared or removed SFBERE The SFBERE bit is the interrupt enable for the signal fail threshold alarm When SFBERE is a logic one an interrupt is generated when the SF alarm is declared or removed Z1 S1E The Z1 S1 interrupt enable is an interrupt mask for changes in the received synchronization status When Z1 S1E is a logic one an interrupt is generated when
3. 226 16 9 2 nove 227 17 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS 229 18 A C TIMING CHARACTERISTICS sse eene 233 18 1 SYSTEM 233 18 2 0 0 233 18 3 SYSTEM INTERFACE TIMING 2 234 18 4 TRANSMIT AND RECEIVE FRAME PULSES eee 238 18 5 239 19 ORDERING AND THERMAL 242 20 MECHANICAL 244 Proprietary and Confidential to PMC SIERRA Inc for its Customers Internal Use IV F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 1 FEATURES 1 1 General e Single chip QUAD ATM User Network Interface operating at 155 52 Mbit s e Implements the ATM Forum User Network Interface Specification and the ATM physical layer for Broadband ISDN according to CCITT Recommendation 1 432 e Processes duplex 155 52 Mbit s STS 3c STM 1 data streams with on chip clock and data recovery and clock synthesis e Exceeds Bellcore GR 253 CORE jitter tolerance and intrinsic jitter criteria e Fully implements the ATM Forum s Utopia Level 2 Specification with Multi PHY add
4. H O H O uonoes LOXH 2525 v LOXH 0 2 d M194H o 1943u N3O AHd 52 091 55 1041 pi 1088 201 10559204 10859204 10559204 _ 8N3l E 82 WLY H O H O H O uonoes 7 bax pass e 0 1 0 51 1 01 r v vo1a sseooy 1591 OVIT TRSTB TCK TMS TDI TDO Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 7 DESCRIPTION The PM5349 S UNI QUAD SATURN User Network Interface is a monolithic integrated circuit that implements four channel SONET SDH processing and ATM mapping functions at the STS 3c STM 1 155 52 Mbit s rate The S UNI QUAD receives SONET SDH streams using a bit serial interface recovers the clock and data and processes section line and path overhead It performs framing A1 A2 de scrambling detects alarm conditions and monitors section line and path bit interleaved parity B1 B2 B3 accumulating error counts at each level for performance monitoring purposes Line and path far end block error indications M1 G1 are also accumulated The S UNI QUAD interprets the received payload pointers H1 H2 and extracts the synchronous payload envelope which carries the received ATM cell
5. 2 1 i The test clock signal provides timing for test operations that are carried out using the IEEE P1149 1 test access port The test mode select TMS signal controls the test operations that are carried out using the IEEE P1149 1 test access port TMS is sampled on the rising edge of TCK TMS has an integral pull up resistor The test data input TDI signal carries test data into the S UNI QUAD via the IEEE P1149 1 test access port TDI is sampled on the rising edge of TCK TDI has an integral pull up resistor The test data output TDO signal carries test data out of the S UNI QUAD via the IEEE P1149 1 test access port TDO is updated on the falling edge of TCK TDO is a tristate output which is inactive except when scanning of data is in progress The active low test reset TRSTB signal provides an asynchronous S UNI QUAD test access port reset via the IEEE P1149 1 test access port TRSTB is a Schmitt triggered input with an integral pull up resistor Note that when not being used TRSTB must be connected to the RSTB input Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 25 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 9 5 Analog Signals The Analog Test Bus ATB These pins are used for manufacturing testing only and should be connected 9 6 Powe
6. 4 In non multiplexed address data bus architectures ALE should be held high so parameters tSacr tHaLnR tVL 151 and tH p are not applicable 5 Parameter tHar is not applicable if address latching is used 6 When a set up time is specified between an input and a clock the set up time is the time in nanoseconds from the 1 4 Volt point of the input to the 1 4 Volt point of the clock 7 When a hold time is specified between an input and a clock the hold time is the time in nanoseconds from the 1 4 Volt point of the input to the 1 4 Volt point of the clock Table 16 Microprocessor Interface Write Access Figure 25 Parameter Min Max Units Address to Valid Write Set up Time tSpw Data to Valid Write Set up Time tSALW Address to Latch Set up Time 10 Address to Latch Hold Time Valid Latch Pulse Width E Latch to Write Set up Latch to Write Hold tHpw Data to Valid Write Hold Time tHaw Address to Valid Write Hold Time Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 231 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Figure 25 Microprocessor Interface Write Timing A 10 0 Valid Address 1 wa tSuw ALE CSB WRB D 7 0 Valid Data Notes on Microprocessor Interface Write Timing 1 Avalid write c
7. Register 0x07 S UNI QUAD Channel Control Bit Type Function Default Bit 7 R W EN 0 Bit 6 R W Reserved 0 0 Bit 5 R W RXDINV This register controls the timing and high speed loopback features of the S UNI QUAD LOOPT The LOOPT bit selects the source of timing for the transmit section of the channel When LOOPT is a logic zero the transmitter timing is derived from input REFCLK Clock Synthesis Unit is used When LOOPT is a logic one the transmitter timing is derived from the recovered clock Clock Recovery Unit SDLE The SDLE bit enables the serial diagnostic loopback When SDLE is a logic one the transmit serial stream is connected to the receive stream The SDLE and the LLE bits should not be set high simultaneously LLE The LLE bit enables the S UNI QUAD line loopback When LLE is a logic one the value on RXD differential inputs is synchronously mapped to the TXD differential outputs after clock recovery The SDLE and the LLE bits should not be set high simultaneously PDLE The PDLE bit enables the parallel diagnostic loopback When PDLE is a logic one the transmit parallel stream is connected to the receive stream The loopback point is between the TPOP and the RPOP blocks Blocks upstream of the loopback point continue to operate normally For example line AIS may be inserted in the transmit stream upstream of the loopback point using the TSOP Control register Pro
8. Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 197 F2 MC PMC Serta ING PM5349 S UNI QUAD PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD S UNI QUAD DATASHEET NOTES 1 OENB is the active low output enable for D 7 0 2 RDATENB is the active low output enable for RSOC RDAT 15 0 and RXPRTYT 1 0 3 When set high INTB will be set to high impedance 4 HIZ is the active low output enable for all OUT CELL types except D 7 0 RXPRTY 1 0 RDAT 15 0 and INTB 5 A 7 is the first bit of the boundary scan chain 12 3 1 Boundary Scan Cells In the following diagrams CLOCK DR is equal to TCK when the current controller state is SHIFT DR or CAPTURE DR and unchanging otherwise The multiplexer in the center of the diagram selects one of four inputs depending on the status of select lines G1 and G2 The ID Code bit is as listed in the Boundary Scan Register table located above Figure 6 Input Observation Cell IN CELL IDCODE Scan Chain Out INPUT to internal logic SHIFT DR 1 0 Code bit CLOCK DR Scan Chain In Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 198 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Figure 7 Output Cell OUT CELL Scan Chain Out EXTEST Output or Enable
9. nennen nennen nns 32 10 1 RECEIVE LINE INTERFACE 32 10 1 1 CLOCK RECOVERY x 2 e rennen 32 10 1 2 SERIAL TO PARALLEL CONVERTER 33 10 2 RECEIVE SECTION OVERHEAD PROCESSOR RSOP 33 10 2 1 5 33 10 2 2 DESGRAMBBLE Bebe 34 10 2 3 ERROR MONITOR 2 dte tee nie innate 34 10 2 4 L SS OE SSIGNAL i tea Mes 34 10 2 5 LOSS OF FRAME eei Le ERE ete caet as 35 Proprietary and Confidential to PMC SIERRA Inc and for its Customers Internal Use 1 M di PMC Sierra Inc 5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 10 3 RECEIVE LINE OVERHEAD PROCESSOR 35 10 3 1 EINESBDEDETECI 2 odo 35 10 3 2 LINE AIS DETECT 35 10 3 3 ERROR MONITOR BLOCK eet 35 10 4 THE RECEIVE APS SYNCHRONIZATION EXTRACTOR AND BIT ERROR MONITOR xta eof nd Matt tate M iat 8 6 36 10 4 1 AUTOMATIC PROTECTION SWITCH 36 10 4 2 BIT ERROR RATE MONITOR ette 37 10 4 3 SYNCHRONIZATION STATUS
10. 37 10 5 RECEIVE PATH OVERHEAD PROCESSOR 38 10 5 1 POINTER INTERPRETER ettet 38 10 5 2 SPE TIMING tere pa Ep et An at weet 42 10 5 3 ERROR MONITOR er iere 42 10 6 RECEIVE ATM CELL PROCESSOR 22 24 4141 141040 43 10 6 1 CELL DELINEATION 42255 Sonne eh poner poe 43 10 6 2 DESCRAMBLER On senes caves cantata Mn 44 10 6 3 CELL FILTER AND HCS VERIFICATION ees 44 10 6 4 PERFORMANCE MONITOR etta 46 107 TRANSMIT LINE INTERFACE CSPI ttnnns 46 10 7 1 CLOCK SYNTHESIS cos Tee Posen eua idee 46 10 7 2 PARALLEL TO SERIAL CONVERTER ees 47 10 8 TRANSMIT SECTION OVERHEAD PROCESSOR 47 10 8 1 LINE AIS INSERT stttt ttt 47 10 8 2 1 8 INSERT esee ote Coots 47 10 8 3 FRAMING AND IDENTITY INSERT e 48 10 8 4 SORANBEBR 48 10 9 TRANSMIT LINE OVERHEAD PROCESSOR 48 10 9 1 APS INSERT 48 10 9 2 INIE BIP CADOBIJATE o ce section ha und 48 10 9 3 LINE RDPINSBET 48 10 9 4 LINE FEBE INSERT er 49 10 10 TRANSMIT PATH OVERHEAD PROCESSOR TPOP 49
11. Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 107 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x33 EXTD 0 RPOP Interrupt Enable Type Function Default R W PSLE Bit 6 R W Reserved NOTE To facilitate additional register mapping shadow registers have been added to registers 0x30 0x31 and 0x33 These shadow registers are accessed in the same way as the normal registers The EXTD extend register bit must be set in register 0x36 to allow switching between accessing the normal registers and the shadow registers This register allows interrupt generation to be enabled for path level alarm and error events FEBEE The FEBEE bit is the interrupt enable for path FEBEs When FEBEE is a logic one an interrupt is generated when a path FEBE is detected BIPEE The BIPEE bit is the interrupt enable for path BIP 8 errors When BIPEE is a logic one an interrupt is generated when a B3 error is detected PRDIE The PRDIE bit is the interrupt enable for path RDI When PRDIE is a logic one an interrupt is generated when the path RDI state changes PAISE The PAISE bit is the interrupt enable for path AIS When PAISE is a logic one an interrupt is generated when the path AIS state changes Proprietary and Confidential to PMC Sierra Inc and for its Customers
12. 2 lt lt lt DEEE EE TRSTB yyy v INTB TCK TMS TDI TDO Utopia System Interface JTAG Test Access Port VF Microprocessor ATM Cell Processor o o 9 3 2 P o o 8 8 Fe a n Line O H Processor Processor RCLK1 4 RFPO1 4 RALRM1 4 ction O H rocessor E 2 i ll ur E 59 Processor Section O H TXC1 4 TXC1 4 XD1 4 ATBO 3 REFCLK RXD1 4 RXD1 4 SD1 4 Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 211 ON AC scs MC PME Sera TR PM5349 S UNI QUAD PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD S UNI QUAD DATASHEET 13 6 JTAG Support The S UNI QUAD supports the IEEE Boundary Scan Specification as described in the IEEE 1149 1 standards The Test Access Port TAP consists of the five standard pins TRSTB TCK TMS TDI and TDO used to control the TAP controller and the boundary scan registers The TRSTB input is the active low reset signal used to reset the TAP controller TCK is the test clock used to sample data on input TDI and to output data on output TDO The TMS input is used to direct the TAP controller through its states The basic boundary scan architecture is shown below Figure 17 Boundary Scan Architecture Boundary Scan Register Device Identification Register Bypass Register Instruction Register and TDO Decode
13. AISDET The AISDET bit determines the Line AIS detection algorithm When AISDET is set to logic one Line AIS is declared when a 111 binary pattern is detected in bits 6 7 and 8 of the K2 byte for three consecutive frames When AISDET is set to logic zero Line AIS is declared when a 111 binary pattern is detected in bits 6 7 and 8 of the K2 byte for five consecutive frames ALLONES The ALLONES bit controls automatically forcing the SONET frame passed to downstream blocks to logical all ones whenever LAIS is detected When ALLONES is set to logic one the SONET frame is forced to logic one immediately when the LAIS alarm is declared When LAIS is removed the received byte is immediately returned to carrying data When ALLONES is set to logic zero the received byte carries the data regardless of the state of LAIS BIPWORD The BIPWORD bit controls the accumulation of B2 errors When BIPWORD is logic one the B2 error event counter is incremented only once per frame whenever one or more B2 bit errors occur during that frame When BIPWORD is logic zero the B2 error event counter is incremented for each B2 bit error that occurs during that frame the counter can be incremented up to 24 times per frame Reserved The reserved bits must be programmed to logic zero for proper operation Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 88 F2 MC PMC Serta ING PM5349 S UNI QUAD S U
14. a S I o i 5 De TCLK lt 8 RCLK1 4 1 4 TERO 98 RALRM1 4 o o 3 25 Y3 e ro aa Xx lt EE a TE Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 209 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Figure 15 Serial Diagnostic Loopback Mode z au 19 x gt Fr co oM 20 gt 2 lt lt lt DEEE EE i TRSTB vy v vvv INTB 2 Utopia 5 RSTB TMS o System Interface 2 RDB 92 Su WRB TDI ES amp CSB TDO gt lt 8 ALE gt 10 0 D 7 0 TAXI rr N IEEE 55 5 xo 2 cms DE 2 n o 5 5 x 8 cms 9 a n ro S a 59 9 o8 TCLK lt one 9 RCLK1 4 go o RFPO1 4 IS PES e RALRM1 4 o TXC1 4 TXC1 4 XD1 4 ATBO 3 REFCLK RXD1 4 RXD1 4 SD1 4 Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 210 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Figure 16 Parallel Diagnostic Loopback Mode z au 19 x gt Fr co oM 20 gt
15. PMC 971239 F2 MC PMC Serta ING PM5349 S UNI QUAD ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD H1 H2 H3 B2 K1 K2 S1 M1 The pointer value bytes locate the path overhead column in the SONET SDH frame The pointer action bytes contain synchronous payload envelope data when a negative stuff event occurs The all zeros pattern is inserted in the transmit direction This byte is ignored in the receive direction unless a negative stuff event is detected The line bit interleaved parity bytes provide a line error monitoring function The K1 and K2 bytes provide the automatic protection switching channel The K2 byte is also used to identify line layer maintenance signals Line RDI is indicated when bits 6 7 and 8 of the K2 byte are set to the pattern 110 Line AIS is indicated when bits 6 7 and 8 of the K2 byte are set to the pattern 111 The 51 byte provides the synchronization status byte Bits 5 through 8 of the synchronization status byte identifies the synchronization source of the STS 3c STM 1 signal Bits 1 through 4 are currently undefined The M1 byte is located in the third STS 1 locations of a STS 3c STM 1 and provides a line far end block error function for remote performance monitoring Path Overhead Bytes J1 B3 C2 G1 This byte is set to transmit continuous null characters Null is defined as the ASCII code 0x00 The path bit interleaved parity byt
16. PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Reserved These bits should be set to their default values for proper operation Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 156 ron Aa 5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x83 TXCP Interrupt Enable Status Bit 4 Unused Bit 3 Unused Bit 2 TPRTYI TSOCI The TSOCI bit is set high when the TSOC input is sampled high during any position other than the first word of the selected data structure The write address counter is reset to the first word of the data structure when TSOC is sampled high This bit is reset immediately after a read to this register FOVRI The FOVRI bit is set high when an attempt is made to write into the FIFO when it is already full This bit is reset immediately after a read to this register TPRTYI The TPRTYI bit indicates if a parity error was detected on the TDAT input bus When logic one the TPRTYI bit indicates a parity error over the active TDAT bus This bit is cleared when this register is read Odd or even parity is selected using the TPTYPE bit TSOCE The TSOCE bit enables the generation of an interrupt when the TSOC input is sampled high during any position other than the first word of the selected data structure When TSOCE is set to logic one the interrupt is enabled FOVR
17. Pass Cell DELTA consecutive correct HCS s From PRESYN state No Errors Detected Pass Cell Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 45 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD In normal operation the HCS verification state machine remains in the Correction Mode state Incoming cells containing no HCS errors are passed to the receive FIFO Incoming single bit errors are corrected and the resulting cell is passed to the FIFO Upon detection of a single bit error or a multi bit error the state machine transitions to the Detection Mode state In this state programmable HCS error filtering is provided The detection of any HCS error causes the corresponding cell to be dropped The state machine transitions back to the Correction Mode state when M where M 1 2 4 8 cells are received with correct HCSs The Mth cell is not discarded 10 6 4 Performance Monitor The Performance Monitor consists of two 12 bit saturating HCS error event counters and a 21 bit saturating receive cell counter One of the counters accumulates correctable HCS errors which are HCS single bit errors detected and corrected while the HCS Verification state machine is in the Correction Mode state The second counter accumulates uncorrectable HCS errors which are HCS bit errors detected whil
18. Proprietary and Confidential to PMC SIERRA Inc and for its Customers Internal Use F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 10 10 1 POINTER 49 10 10 2 8 00000 50 10 10 3 FEBE CALGULATE itte mee edet Gd 50 10 11 TRANSMIT ATM CELL PROCESSOR TXCP 50 10 11 1 IDLE UNASSIGNED CELL GENERATOR eene 50 10 11 2 SCRAMBLER a seit etu sad 50 10 11 3 HCS GENERATOR i nece d eie nes 51 10 12 UTOPIA LEVEL 2 SYSTEM INTERFACE eene 51 10 12 1 RECEIVE ATM INTERFACE esee 51 10 12 2 TRANSMIT ATM INTERFACE eene 51 10 13 JTAG TEST ACCESS 52 10 14 MICROPROCESSOR 52 11 NORMAL MODE REGISTER DESCRIPTION esee 59 12 TEST FEATURES DESCRIPTION esee nennen rennen 193 12 1 MASTER TEST REGISTER t e e eR 193 12 2 TEST MODE 0 DETAILS een te eee aped dec de one nn 195 12 3 TAG TEST PORT a ute t fie eas ieri ertet 196 12 3 1 BOUNDARY SCAN 5 198 13 OPERATION E ier etie che teg RR SERERE 201 13 1 SONET SDH FRAME MAPPINGS
19. R W GFC 2 Bitb R W GFC 1 Bit4 RW RW PTI 3 Bit2 R W PTI 2 GFC 3 0 The GFC 3 0 bits contain the pattern to match in the first second third and fourth bits of the first octet of the 53 octet cell in conjunction with the Idle Cell Header Mask Register The IDLEPASS bit in the Configuration 2 Register must be set to logic zero to enable dropping of cells matching this pattern Note that an all zeros pattern must be present in the VPI and VCI fields of the idle or unassigned cell PTI 2 0 The PTI 2 0 bits contain the pattern to match in the fifth sixth and seventh bits of the fourth octet of the 53 octet cell in conjunction with the Idle Cell Header Mask Register The IDLEPASS bit in the Configuration 2 Register must be set to logic zero to enable dropping of cells matching this pattern CLP The CLP bit contains the pattern to match in the eighth bit of the fourth octet of the 53 octet cell in conjunction with the Match Header Mask Register The IDLEPASS bit in the RXCP Configuration 2 Register must be set to logic zero to enable dropping of cells matching this pattern Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 143 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x68 RXCP Idle Cell Header Mask Type Function peur R W MGFC 3
20. an inv point indication Note 5 ss bits are unspecified in SONET and has bit pattern 10 in SDH Note 6 the use of ss bits in definition of indications may be optionally disabled Note 7 the requirement for previous NDF enable inc ind or dec ind be more than 3 frames ago may be optionally disabled Note 8 new point is also an inv point Note 9 LOP is not declared if all the following conditions exist the received pointer is out of range gt 782 the received pointer is static the received pointer can be interpreted according to majority voting on the and D bits as a positive or negative justification indication after making the requested justification the received pointer continues to be interpretable as a pointer justification Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 40 S UNI QUAD DATASHEET PMC 971239 F2 MC PMC Serta ING PM5349 S UNI QUAD ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Note 10 The transition When the received pointer returns to an in range value the S UNI QUAD will interpret it correctly LOP will exit at the third frame of a three frame sequence consisting of one frame with NDF enabled followed by two frames with NDF disabled if all three pointers have the same legal value s indicated in the state diagram are defined in the following table Table 2 Pointer Interpreter Transition Description Trans
21. and for its Customers Internal Use 85 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x15 TSOP Diagnostic Bit 4 Unused Bit 3 Unused Bit 2 R W DLOS DFP The DFP bit controls the insertion of a single bit error continuously in the most significant bit bit 1 of the A1 section overhead framing byte When DFP is set to logic one the A1 bytes are set to 0x76 instead of OxF6 DBIP8 The DBIP8 bit controls the insertion of bit errors continuously in the section BIP 8 byte B1 When 8 is set to logic one the B1 byte is inverted DLOS The DLOS bit controls the insertion of all zeros in the transmit stream When DLOS is set to logic one the transmit stream is forced to 0x00 Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 86 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x18 RLOP Control Status Bit Type Function Default Bit 7 R W BIPWORD 0 Bit 6 R W ALLONES Bit 5 R W AISDET LRDIV The LRDIV bit is read to determine the remote defect indication state of the RLOP When LRDIV is high the RLOP has declared line RDI LAISV The LAISV bit is read to determine the line AIS state of the RLOP When LAISV is high the RLOP has declared line AIS
22. from system logic OUTPUT or Enable IDOODE SHIFT DR I D code bit CLOCK DR UPDATE DR Scan Chain In Figure 8 Bidirectional Cell IO CELL Scan Chain Out EXTEST OUTPUT from internal logic IDCODE SHIFT DR INPUT from pin 1 0 code bit CLOCK DR UPDATE DR Scan Chain In Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 199 S UNI QUAD ron Aa MC BME siete ING 5349 S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Figure 9 Layout of Output Enable and Bidirectional Cells Scan Chain Out OUTPUT ENABLE from internal OUT_CELL logic 0 drive INPUT to internal logic OUTPUT from internal logic lO CELL NEL M Scan Chain In Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 200 F2 MC PMC Serta ING PM5349 S UNI QUAD PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD S UNI QUAD DATASHEET 13 OPERATION 13 1 SONET SDH Frame Mappings and Overhead Byte Usage 13 1 1 ATM Mapping The S UNI QUAD processes the ATM cell mapping for STS 3c STM 1 as shown below in Figure 10 The S UNI QUAD processes the transport and path overhead required to support ATM UNIs and NNIs In addition the S UNI QUAD provides support for the APS bytes In Figure 10 the STS 3c STM 1 mapping is shown In this mapping no stuff columns are included in th
23. BIPEI is a logic one when a B3 error is detected This bit is cleared when this register is read PRDII The PRDII bit is the path remote defect indication interrupt status bit PRDII is a logic one when a change in the path RDI state or the auxiliary path RDI state occurs This bit is cleared when this register is read PAISI The PAISI bit is the path alarm indication signal interrupt status bit PAISI is a logic one when a change in the path AIS state occurs This bit is cleared when this register is read Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 103 F2 MC PMC Serta ING PM5349 S UNI QUAD PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD S UNI QUAD DATASHEET LOPI The LOPI bit is the loss of pointer interrupt status bit LOPI is a logic one when a change in the LOP state occurs This bit is cleared when this register is read PSLI The PSLI bit is the change of path signal label interrupt status bit PSLI is a logic one when a change is detected in the path signal label register The current path signal label can be read from the RPOP Path Signal Label register This bit is cleared when this register is read Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 104 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Regist
24. F2 PMC Serta ING PM5349 S UNI QUAD ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD pattern for the first frame subsequent frames have the new data flag bit positions set to the normal pattern 0110 unless the NDF bit described above is set to a logic one This bit is automatically cleared after the new payload pointer is loaded Note When loading an out of range pointer that is a pointer with a value greater than 782 the TPOP continues to operate with timing based on the last valid pointer value The out of range pointer value is inserted in the transmit stream Although a valid SPE will continue to be generated it is unlikely to be extracted by downstream circuitry which should be in a loss of pointer state SOS The SOS bit controls the stuff opportunity spacing between consecutive SPE positive or negative stuff events When SOS is a logic zero stuff events may be generated every frame as controlled by the PSE and NSE register bits described above When SOS is a logic one stuff events may be generated at a maximum rate of once every four frames FTPTR The force transient pointer bit FTPTR enables the insertion of the pointer value contained in the Arbitrary Pointer Registers into the transmit stream for diagnostic purposes When FTPTR is a logic one the APTR 9 0 bits of the Arbitrary Pointer Registers are inserted into the H1 and H2 bytes of the transmit stream At least one corrupted pointer is guar
25. PMC 971239 M di PMC Sierra Inc PM5349 S UNI QUAD ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register OxE6 RASE SF Saturation Threshold Bit Type Function Default Bit 7 R W SFSTH 7 0 Bit6 R W SFSTH 6 Bitb R W SFSTH 5 Bit 0 R W SFSTH 0 Register OxE7 RASE SF Saturation Threshold SFSTH 1 1 0 The SFSTH 1 1 0 value represents the allowable number of B2 errors that can be accumulated during an evaluation window before an SF threshold event is declared Setting this threshold to OxFFF disables the saturation functionality Refer to the Operations section for the recommended settings Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 182 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register OxE8 RASE SF Declaring Threshold Bit Type Function Default Bit7 R W SFDTH 7 0 Bit6 R W SFDTH 6 Bit5 R W SFDTH 5 Bit RW SFDTH 0 Register OxE9 RASE SF Declaring Threshold R W SFDTHIS SFDTH 1 1 0 The SFDTH 11 0 value determines the threshold for the declaration of the SF alarm The SF alarm is declared when the number of B2 errors accumulated during an evaluation window is greater than or equal to the SFDTH 1 1 0 value Refer to the Operations section
26. R W C2 6 Bitb RW C2 5 BitoO RW C2 0 This register allows control over the path signal label Upon reset the register defaults to 0x01 which signifies an equipped but not specific payload This register should be reprogrammmed with the value 0x13 for Asynchronous Transfer Mode ATM mode C2 7 0 The C2 7 0 bits are inserted in the C2 byte position in the transmit stream Upon reset the register defaults to 0x01 which signifies an equipped but not specific payload This register should be reprogrammed with the value 0x13 when in Asynchronous Transfer Mode ATM mode Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 130 S UNI QUAD DATASHEET PMC 971239 F2 MC PMC Serta ING PM5349 S UNI QUAD ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x49 TPOP Path Status Bit Type Function Default Bit7 RW FEBE 3 0 This register allows control over the path status byte G 1 0 The G1 1 0 bits are inserted in bits 1 and 2 of the path status byte G1 These bits are ignored when EPRDIEN is logic zero or when EPRDIEN and EPRDISRC are both logic one See the description of EPRDIEN and EPRDISRC for more details on how G1 can be controlled APRDI The APRDI bit controls the insertion of the auxiliary path remote defect indication When APRDI is a logic one the APRDI bit position in the path status byte is set high When APR
27. Register 0x1C RLOP Line BIP 24 MSB LBE 19 0 Bits LBE 19 0 represent the number of line BIP 24 errors individual or block that have been detected since the last time the error count was polled The error count is polled by writing to any of the RLOP Line BIP Registers or Line FEBE Register addresses Such a write transfers the internally accumulated error count to the Line BIP Registers within approximately 7 us and simultaneously resets the internal counter to begin a new cycle of error accumulation The count can also be polled by writing to the S UNI QUAD Channel Reset and Monitoring Update register 0x05 Writing to register 0x05 simultaneously loads all the performance meter registers in the RSOP RLOP RPOP RXCP and TXCP blocks Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 92 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x1D RLOP Line FEBE LSB Register 0x1E RLOP Line FEBE D R DDD Bit Type Function Default 25 DI Bit 0 2 LFE 8 Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 93 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x1F RLOP Line FEBE
28. S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 10 11 3 HCS Generator The HCS Generator performs a CRC 8 calculation over the first four header octets A parallel implementation of the polynomial x8 x2 x 1 is used The coset polynomial x6 x4 x2 1 is added modulo 2 to the residue The HCS Generator optionally inserts the result into the fifth octet of the header 10 12 UTOPIA Level 2 System Interface The S UNI QUAD system interface provides a Utopia level 2 compliant bus to transfer ATM cells between the ATM layer device and the S UNI QUAD 10 12 1 Receive ATM Interface The Receive ATM FIFO RXCP provides FIFO management at the S UNI QUAD receive cell interface The receive FIFO contains four cells The FIFO provides the cell rate decoupling function between the transmission system physical layer and the ATM layer In general the management functions include filling the receive FIFO indicating when the receive FIFO contains cells maintaining the receive FIFO read and write pointers and detecting FIFO overrun and underrun conditions The FIFO interface is UTOPIA Level 2 compliant and accepts a read clock RFCLK and read enable signal RENB The receive FIFO output bus RDAT 15 0 is tri stated when RENB is logic one or if the PHY device address RADR 4 0 selected does not match this device s address The interface indicates the start of a cell RSOC and the receive cell availa
29. S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD intrinsic jitter is typically less than 0 01 UI RMS when measured using a high pass filter with a 12 kHz cutoff frequency The REFCLK reference should be within 20 ppm to meet the SONET free run accuracy requirements specified in GR 253 CORE 10 7 2 Parallel to Serial Converter The Parallel to Serial Converter PISO converts the transmit byte serial stream to a bit serial stream Every self timed channel a self timed channel is one that uses the CSU output clock share a common line rate clock and byte clock which can be output as TCLK Only self timed channels can be synchronized using the TFPI input When a channel is loop timed TCLK TFPI and TFPI are no more available and the receive signals shall be used instead to extract timing information 10 8 Transmit Section Overhead Processor TSOP The Transmit Section Overhead Processor TSOP provides frame pattern insertion A1 A2 scrambling section level alarm signal insertion and section BIP 8 B1 insertion 10 8 1 Line AIS Insert Line AIS insertion results in all bits of the SONET SDH frame being set to 1 before scrambling except for the section overhead The Line AIS Insert Block substitutes all ones as described when enabled through an internal register Reg 0x14 TSOP accessed through the microprocessor interface Activation or deactivation of line AIS insertion is synchronized
30. This block also extracts the line FEBE code from the third Z2 byte The FEBE code is contained in bits 2 to 8 of the Z2 byte and represents the number of line BIP 8 errors that were detected in the last frame by the far end The FEBE code value has 25 legal values 0 to 24 for an STS 3c STM 1 stream Illegal values are interpreted as zero errors The Error Monitor Block accumulates B2 error events and FEBE events in two 20 bit saturating counter that can be read via the microprocessor interface The contents of these counters may be transferred to internal holding registers by writing to any one of the counter addresses or by using the TIP register bit feature During a transfer the counter value is latched and the counter is reset to 0 or 1 if there is an outstanding event Note these counters should be polled at least once per second to avoid saturation The B2 error events counters optionally can be configured to accumulate only word errors A B2 word error is defined as the occurrence of one or more B2 bit error events during a frame The B2 error counter is incremented by one for each frame in which a B2 word error occurs In addition the FEBE events counters optionally can be configured to accumulate only word events In STS 3c STM 1 framing a FEBE word event is defined as the occurrence of one or more FEBE bit events during a frame The FEBE event counter is incremented by one for each frame in which a FEBE event occurs 10
31. cycle every 2430 RCLK cycles STS 3c STM 1 RFPO is updated on the rising edge of RCLK This pin is available independently for each channel RALRM 1 The Receive Alarm RALRM output indicates the RALRM2 state of the receive framing RALRM is low if no RALRMS receive alarms are active RALRM is high if line AIS RALRM4 LAIS path AIS PAIS line RDI LRDI path RDI PRDI enhanced path RDI PERDI loss of signal LOS loss of frame LOF out of frame OOF loss of pointer LOP loss of cell delineation LCD signal fail BER SFBER signal degrade BER SDBER or path signal label mismatch PSLM is detected in the associated channel Each alarm can be individually enabled using bits in the S UNI QUAD Channel Alarm Control registers 1 and 2 RALRM is updated on the rising edge of RCLK This pin is available independently for each channel The transmit differential data outputs TXD TXD contain the 155 52 Mbit s transmit stream This pin is available independently for each channel converted to PECL Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 13 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD men a TFPI Input The active high framing position TFPI signal is an 8 kHz timing marker for the transmitter TFPI is used to align the SONET SDH transport frame generated by
32. damages to the devices PHY ADR 2 0 Reserved The PHY ADR 2 0 is Device Identification Address PHY ADR 2 0 The PHY ADR 2 0 register bits are the most significant bits of the address space which this S UNI QUAD occupies When the PHY ADR 2 0 inputs match the TADR 4 2 or RADR 4 2 inputs then one of the four quadrants as determined by the TADR 1 0 or RADR 1 0 inputs in this S UNI QUAD is selected for transmit or receive operations Note that the null PHY address Ox1F is the null PHY address and cannot be assigned to any port on the S UNI QUAD Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 63 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x03 S UNI QUAD Master Clock Monitor Bit Type Function Default Bit 7 RCLK4A X Bit 6 RCLK3A Bit 5 RCLK2A D DD 29120 J This register provides activity monitoring on S UNI QUAD clocks When a monitored clock signal makes a low to high transition the corresponding register bit is set high The bit will remain high until this register is read at which point all the bits in this register are cleared A lack of transitions is indicated by the corresponding register bit reading low This register should be read at periodic intervals to detect clock failures REFCLKA The REFCLK active REFCLKA bit monit
33. parity bit TPRTY and the ATM device address TADR 4 0 when data is written to the transmit FIFO using the rising edges of TFCLK The interface provides the transmit cell available status TCA and DTCA 4 1 which can transition from available to unavailable when the transmit FIFO is near full when TCALEVELO is logic zero or when the FIFO is full when TCALEVELO is logic one and can accept no more writes To reduce FIFO latency the FIFO depth at which TCA and DTCA x indicates full can be set to one two three or four cells by the FIFODP 1 0 bits of TXCP Configuration 2 register If the programmed depth is less than four more than one cell may be written after TCA or DTCA x is asserted as the TXCP still allows four cells to be stored in its FIFO This interface also indicates FIFO overruns via a maskable interrupt and register bit but write accesses while TCA or DTCA x is logic zero are not processed The TXCP automatically transmits idle cells until a full cell is available to be transmitted 10 13 JTAG Test Access Port The JTAG Test Access Port block provides JTAG support for boundary scan The standard JTAG EXTEST SAMPLE BYPASS IDCODE and STCTEST instructions are supported The S UNI QUAD identification code is 053490CD hexadecimal 10 14 Microprocessor Interface The microprocessor interface block provides normal and test mode registers and the logic required to connect to the microprocessor interface The normal m
34. 15 0 bus A parity error is indicated by a status bit and a maskable interrupt Cells with parity errors are inserted in the transmit stream so the TPRTY input may be unused Odd or even parity selection is made independently for each channel using the RXPTYP register bit TPRTY is considered valid only when TENB is simultaneously asserted and the S UNI QUAD is selected via TADR 4 0 TPRTY is sampled on the rising edge of TFCLK TSOC Input J21 UTOPIA Transmit Start of Cell TSOC signal The transmit start of cell TSOC signal marks the start of cell on the TDAT bus When TSOC is high the first word of the cell structure is present on the TDAT bus It is not necessary for TSOC to be present for each cell An interrupt may be generated if TSOC is high during any word other than the first word of the cell structure TSOC is considered valid only when TENB is simultaneously asserted and the S UNI QUAD is selected via TADR 4 0 TSOC is sampled on the rising edge of TFCLK Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 16 S UNI QUAD DATASHEET PMC 971239 NAC scs MC PME Sera TR PM5349 S UNI QUAD ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Pin Name Type Pin No Function TENB Input J22 UTOPIA Transmit Multi PHY Write Enable TENB signal The TENB signal is an active low input which is used along with th
35. 245 F2 ra 5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD CONTACTING PMC SIERRA INC PMC Sierra Inc 105 8555 Baxter Place Burnaby BC Canada V5A 4V7 Tel 604 415 6000 Fax 604 415 6200 Document Information Corporate Information Application Information Web Site document pmc sierra com info pmc sierra com apps pmc sierra com http www pmc sierra com None of the information contained in this document constitutes an express or implied warranty by PMC Sierra Inc as to the sufficiency fitness or suitability for a particular purpose of any such information or the fitness or suitability for a particular purpose merchantability performance compatibility with other parts or systems of any of the products of PMC Sierra Inc or any portion thereof referred to in this document PMC Sierra Inc expressly disclaims all representations and warranties of any kind regarding the contents or use of the information including but not limited to express and implied warranties of accuracy completeness merchantability fitness for a particular use or non infringement In no event will PMC Sierra Inc be liable for any direct indirect special incidental or consequential damages including but not limited to lost profits lost business or lost data resulting from any use of or reliance upon the information whether or not PMC Sier
36. 4 The Receive APS Synchronization Extractor and Bit Error Monitor RASE 10 4 1 Automatic Protection Switch Control The Automatic Protection Switch APS control block filters and captures the receive automatic protection switch channel bytes K1 and K2 allowing them to be read via the RASE APS K1 Register and the RASE APS K2 Register The bytes are filtered for three frames before being written to these registers A protection switching byte failure alarm is declared when twelve successive frames have been received where no three consecutive frames contain identical K1 bytes The protection switching byte failure alarm is removed upon detection of three consecutive frames containing identical K1 bytes The detection of invalid APS codes is done in software by polling the RASE APS K1 Register and the RASE APS K2 Register Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 36 S UNI QUAD ron Aa MC BME siete ING 5349 S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 10 4 2 Bit Error Rate Monitor The Bit Error Monitor Block BERM calculates the received line BIP 24 error detection code B2 based on the line overhead and synchronous payload envelope of the receive data stream The line BIP 24 code is a bit interleaved parity calculation using even parity Details are provided in the references The calculated BIP code is compared with the BIP 24 code extr
37. Bit6 R W MGFC 2 Bit5 RW MGFCH Bit 0 R W MCLP MGFC 93 0 The MGFC 3 0 bits contain the mask pattern for the first second third and fourth bits of the first octet of the 53 octet cell This mask is applied to the Idle Cell Header Pattern Register to select the bits included in the cell filter A logic one in any bit position enables the corresponding bit in the pattern register to be compared A logic zero causes the masking of the corresponding bit MPTI 3 0 The 3 0 bits contain the mask pattern for the fifth sixth and seventh bits of the fourth octet of the 53 octet cell This mask is applied to the Idle Cell Header Pattern Register to select the bits included in the cell filter A logic one in any bit position enables the corresponding bit in the pattern register to be compared A logic zero causes the masking of the corresponding bit MCLP The CLP bit contains the mask pattern for the eighth bit of the fourth octet of the 53 octet cell This mask is applied to the Idle Cell Header Pattern Register to select the bits included in the cell filter A logic one in this bit position enables the MCLP bit in the pattern register to be compared A logic zero causes the masking of the MCLP bit Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 144 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK IN
38. Default Bit7 PBE X Bite X Bits PBE S 255 DDD Bit4 R 17 X Bits R X Bt2 R PBE IO X Biti X I Bit 0 PBE 15 0 PBE 15 0 represent the number of B3 errors individual or block that have been detected since the last time the error count was polled The error count is polled by writing to either of the RPOP Path BIP 8 Register addresses or to either of the RPOP Path FEBE Register addresses Such a write transfers the internally accumulated error count to the Path BIP 8 registers within a maximum of 7 us and simultaneously resets the internal counter to begin new cycle of error accumulation This transfer and reset is carried out in a manner that ensures that coincident events are not lost The count can also be polled by writing to the S UNI QUAD Channel Reset and Monitoring Update register 0x05 2 PBE 8 Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 117 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x3A RPOP Path FEBE LSB Register 0x3B RPOP Path FEBE MSB D R DDD Bit Type Function Default 25 DDD DD DI These registers allow path FEBEs to be accumulated PFE 15 0 PFE 15 0 represent the number
39. FEBEWORD The FEBEWORD bit controls the accumulation of FEBEs When FEBEWORD is logic one the FEBE event counter is incremented only once per frame whenever one or more FEBE bits occur during that frame When FEBEWORD is logic zero the FEBE event counter is incremented for each and every FEBE bit that occurs during that frame the counter can be incremented up to 24 BIPWORDO The BIPWORDO bit controls the indication of B2 errors reported to the TLOP block for insertion as FEBEs When BIPWORDO is logic one the BIP errors are indicated once per frame whenever one or more B2 bit errors occur during that frame When BIPWORDO is logic zero BIP errors are indicated once for every B2 bit error that occurs during that frame The accumulation of B2 error events functions independently and is controlled by the BIPWORD register bit Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 87 F2 MC PMC Serta ING PM5349 S UNI QUAD PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD S UNI QUAD DATASHEET LRDIDET The LRDIDET bit determines the Line LRDI detection algorithm When LRDIDET is set to logic one Line LRDI is declared when a 110 binary pattern is detected in bits 6 7 and 8 of the K2 byte for three consecutive frames When LRDIDET is set to logic zero Line LRDI is declared when a 110 binary pattern is detected in bits 6 7 and 8 of the K2 byte for five consecutive frames
40. FIFO is immediately emptied and ignores writes The FIFO remains empty and continues to ignore writes until a logic zero is written to FIFORST RCALEVELO Unused FIFORST The RCA and DRCA x level 0 bit RCALEVELO determines what output RCA and DRCA x indicates when it transitions low When RCALEVELO is set to logic one a high to low transition on output DRCA x and RCA indicates that the receive FIFO is empty DRCA x and RCA if polled will de assert on the rising RFCLK edge after Payload word 24 is output When RCALEVELO is set to logic zero a high to low transition on output DRCA x and RCA if polled indicates that the receive FIFO is near empty DRCA x and RCA if polled will de assert on the rising RFCLK edge after Payload byte 19 is output RCAINV The RCAINV bit inverts the polarity of the DRCA x and RCA output signal When RCAINV is a logic one the polarity of DRCA x and RCA is inverted DRCA x and RCA at logic zero means there is a receive cell available to be read When RCAINV is a logic zero the polarity of RCA and DRCA x is not inverted RXPTYP The RXPTYP bit selects even or odd parity for output RPRTY When set to logic one output RPRTY is the even parity bit for outputs RDAT 15 0 When Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 136 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NE
41. Internal Use 73 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD TXCPI The TXCPI bit is high when an interrupt request is active from the TXCP block The TXCP interrupt sources are enabled in the TXCP Interrupt Control Status Register CRUI The CRUI bit is high when an interrupt request is active from the Clock Recovery and SIPO block CRSI Clock Recovery Unit The CRUI interrupt sources are enabled in the Clock Recovery Interrupt Control Status Register RASEI The RASEI bit is high when an interrupt request is active from the RASE block The RASE interrupt sources are enabled in the RASE Interrupt Enable Register Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 74 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0 0 CSPI Clock Synthesis Control and Status Bit Type Function Default Bit 7 R W Reserved 0 Bit 6 R W Reserved Bit 5 R TROOLI Bit O R W Reserved This register controls the clock synthesis and reports the state of the transmit phase locked loop TROOLE The TROOLE bit is an interrupt enable for the transmit reference out of lock status When TROOLE is set to logic one an interrupt is generated when the TROOLV bit changes state TROOLV The transmi
42. Monitor The S UN QUAD provides two BERM blocks One can be dedicated to monitor at the Signal Degrade SD error rate and the other dedicated to monitor at the Signal Fail SF error rate The Bit Error Rate Monitor BERM block counts and monitor line BIP errors over programmable periods of time window size It can monitor to declare an alarm or to clear it if the alarm is already set A different threshold and accumulation period must be used to declare or clear the alarm whether or not those two operations are not performed at the same BER The following table list the recommended content of the BERM registers for different error rates BER Both BERMs in the TSB are equivalent and are programmed similarly a normal application they will be set to monitor different BER When the SF SD CMODE bit is 1 this indicates that the clearing monitoring is recommended to be performed using a window size that is 8 times longer than the declaration window size When the SF SD CMODE bit is 0 this indicates that the clearing monitoring is recommended to be performed using a window size equal to the declaration window size In all cases the clearing threshold is calculated for a BER that is 10 times lower than the declaration BER as required in the references The table indicates the declare BER and evaluation period only The Saturation threshold is not listed in the table and should be programmed with the value OxFFF by default deactivating satur
43. Operations section for the recommended settings Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 187 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register OxF1 RASE SD Declaring Threshold Bit Type Function Default Bit7 R W SDDTH 7 0 Bit R W SDDTHI6 Bitb SDDTH 5 Bit RW SDDTH 0 Register OxF2 RASE SD Declaring Threshold Bit RW SDDTHI8 SDDTH 11 0 The SDDTH 11 0 value determines the threshold for the declaration of the SD alarm The SD alarm is declared when the number of B2 errors accumulated during an evaluation window is greater than or equal to the SDDTH 11 0 value Refer to the Operations section for the recommended settings Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 188 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0xF3 RASE SD Clearing Threshold Bit Type Function Default Bit7 R W SDCTH 7 0 Bit SDCTHI6 Bitb SDCTH 5 BitO R W SDCTHIO Register 0xF4 RASE SD Clearing Threshold RW SDCTHIS SDCTH 1 1 0 The SDCTH 11 0 value determines the threshold for the removal of the SD alarm The SD a
44. PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Figure 30 JTAG Port Interface Timing TCK TMS TDI TCK tP TDO tVTRSTB TRSTB Notes on Input Timing 1 When a set up time is specified between an input and a clock the set up time is the time in nanoseconds from the 1 4 Volt point of the input to the 1 4 Volt point of the clock Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 240 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 2 When a hold time is specified between an input and a clock the hold time is the time in nanoseconds from the 1 4 Volt point of the clock to the 1 4 Volt point of the input Notes on Output Timing 1 Output propagation delay time is the time in nanoseconds from the 1 4 Volt point of the reference signal to the 1 4 Volt point of the output 2 Maximum output propagation delays are measured with a 50 pF load on the outputs with the exception of the RDAT 15 0 RPRTY RSOC RCA DRCA 4 1 TCA DTCA 4 1 for which propagation delays are measured with a 30 pF load Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 241 NA scs MC PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 19 ORDERING AND THERMAL INFORMATION Table 22 O
45. PME Sera TR PM5349 S UNI QUAD ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x60 RXCP Configuration 1 Bit Type Function Default Bit 7 R W DDSCR 0 Bit 6 R W Reserved Bit 5 Unused Bit 0 R W DISCOR The DISCOR bit controls the HCS error correction algorithm When DISCOR is a logic zero the error correction algorithm is enabled and single bit errors detected in the cell header are corrected When DISCOR is a logic one the error correction algorithm is disabled and any error detected in the cell header is treated as an uncorrectable HCS error HCSADD The HCSADD bit controls the addition of the coset polynomial x6 x4 x2 1 to the HCS octet prior to comparison When HCSADD is a logic one the polynomial is added and the resulting HCS is compared When HCSADD is a logic zero the polynomial is not added and the unmodified HCS is compared DDSCR DISCOR The DDSCR bit controls the de scrambling of the cell payload with the polynomial x43 1 When DDSCR is set to logic one cell payload de scrambling is disabled When DDSCR is set to logic zero payload de scrambling is enabled Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 133 S UNI QUAD DATASHEET PMC 971239 M di PMC Sierra Inc PM5349 S UNI QUAD ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x61 RXCP Configuration 2 Bit Type F
46. PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x11 RSOP Status Interrupt Status Bit Type Function Default Bit 7 Unused X OOFV The OOFV bit is read to determine the out of frame state of the RSOP When OOFV is high the RSOP is out of frame When OOFV is low the RSOP is in frame LOFV The LOFV bit is read to determine the loss of frame state of the RSOP When LOFV is high the RSOP has declared loss of frame LOSV The LOSV bit is read to determine the loss of signal state of the RSOP When LOSV is high the RSOP has declared loss of signal OOFI The bit is the out of frame interrupt status bit OOFI is set high when a change in the out of frame state occurs This bit is cleared when this register is read LOFI The LOFI bit is the loss of frame interrupt status bit LOFI is set high when a change in the loss of frame state occurs This bit is cleared when this register is read LOSI The LOSI bit is the loss of signal interrupt status bit LOSI is set high when a change in the loss of signal state occurs This bit is cleared when this register is read Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 82 NAC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD BIPEI The BIPEI bit is the
47. QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Table 19 Receive ATM System Interface Timing Figure 28 Symbol Description Min Max Units fRFCLK RFCLK Frequency 50 MHz DRFCLK RFCLK Duty Cycle 40 60 tSRENB RENB Set up time to RFCLK ns tSRADR RADR 4 0 Set up time to RFCLK ns RADR 4 0 Hold time to RFCLK ns tPRDAT RFCLK High to RDAT Valid 1 12 ns RFCLK High to RDAT Tri state 1 12 n S tZBepat RFCLK High to Driven S S n RFCLK High to RSOC Valid 1 12 n RFCLK High to RSOC Tri state RFCLK High to RSOC Driven ns RFCLK High to RPRTY Valid ns RFCLK High to RPRTY Tri state ns RFCLK High to RPRTY Driven 0 ns RFCLK High to RCA Valid 1 12 ns RFCLK High to RCA Tri state 1 12 ns tZBncA RFCLK High to RCA Driven 0 ns tPorca RFCLK High to DRCA 4 1 Valid 1 12 ns Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 236 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Figure 28 Receive ATM System Interface Timing Diagram RFCLK 5 RADR RADR RENB RENB RENB RDAT RSOC RPRTY RDAT 15 0 RXPRTY RSOC tZ RDAT RSOC RPRTY RDAT 15 0 RXPRTY RSOC ZB RSOC RDAT 15 0 RXPRTY RSOC ORCA DRCA 4 1 tP RCA tZaca RCA tZB RCA gt RCA Pr
48. Read Access Figure 24 Parameter Min Max Units Address to Valid Read Set up Time tHAR Address to Valid Read Hold Time Address to Latch Set up Time Address to Latch Hold Time 10 Valid Latch Pulse Width Latch to Read Set up Latch to Read Hold Valid Read to Valid Data Propagation Delay 70 ns tZRD Valid Read Negated to Output Tri state 20 ns tZINTH Valid Read Negated to Output Tri state 50 ns Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 229 S UNI QUAD ron Aa MC BME siete ING 5349 S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Figure 24 Microprocessor Interface Read Timing A 10 0 Valid ALE CSB RDB tZ INTH INTB ai tPrp tZ RD Valid Data Notes on Microprocessor Interface Read Timing 1 Output propagation delay time is the time in nanoseconds from the 1 4 Volt point of the reference signal to the 1 4 Volt point of the output 2 Maximum output propagation delays are measured with a 100 pF load on the Microprocessor Interface data bus D 7 0 3 A valid read cycle is defined as a logical OR of the CSB and the RDB signals Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 230 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD
49. S1 byte from the line overhead The SSE block can be configured to capture the S1 nibble after three or after eight frames with the same value filtering turned on or after any change in the value filtering turned off The S1 nibble can be read via the microprocessor interface Optionally the SSE can be configured to perform filtering based on the whole S1 byte Although this mode of operation is not standard it might become useful in the future Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 37 F2 PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 10 5 Receive Path Overhead Processor RPOP The Receive Path Overhead Processor RPOP provides pointer interpretation extraction of path overhead extraction of the synchronous payload envelope and path level alarm indication and performance monitoring 10 5 1 Pointer Interpreter The Pointer Interpreter interprets the incoming pointer H1 H2 as specified in the references The pointer value is used to determine the location of the path overhead the J1 byte in the incoming STS 3c STM 1 stream The algorithm can be modeled by a finite state machine Within the pointer interpretation algorithm three states are defined as shown below NORM state NORM 5 state AIS LOP state LOP The transition between states will be consecutive events ind
50. SONET Network Element free run accuracy specification the reference must be within 20ppm When not loop timed the REFCLK accuracy may be relaxed to 50ppm The loop filter transfer function is optimized to enable the PLL to track the jitter yet tolerate the minimum transition density expected in a received SONET SDH data signal The total loop dynamics of the clock recovery PLL yield a jitter tolerance that exceeds the minimum tolerance proposed for SONET equipment by GR 253 CORE Figure 3 Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 32 PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Figure 2 Typical STS 3c STM 1 Jitter Tolerance Tolerance 100 1000 10000 100000 1000000 10000000 J itter Freq Hz Note that for frequencies below 300 Hz the jitter tolerance is greater than 15 Ulpp 15 Ulpp is the maximum jitter tolerance of the test equipment Also note that the dip in the tolerance curve between 300 Hz and 10 kHz is due to the S UNI QUAD s internal clock difference detector if the recovered clock drifts beyond 488 ppm of the reference the PLL locks to the reference clock 10 1 2 Serial to Parallel Converter The Serial to Parallel Converter SIPO converts the received bit serial stream to a byte serial stream The SIPO searches for the SONET SDH framing pattern A1 A2
51. Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x10 RSOP Control Interrupt Enable Bit Type Function Default Bit 7 R W BIPWORD 0 Bit 6 R W DDS Bit 5 W FOOF Bit 0 R W OOFE OOFE The OOFE bit is an interrupt enable for the out of frame alarm When OOFE is set to logic one an interrupt is generated when the out of frame alarm changes state LOFE The LOFE bit is an interrupt enable for the loss of frame alarm When LOFE is set to logic one an interrupt is generated when the loss of frame alarm changes state LOSE The LOSE bit is an interrupt enable for the loss of signal alarm When LOSE is set to logic one an interrupt is generated when the loss of signal alarm changes state BIPEE The BIPEE bit is an interrupt enable for the section BIP 8 errors When BIPEE is set to logic one an interrupt is generated when a section BIP 8 error B1 is detected ALGO2 The 2 bit position selects the framing algorithm used to confirm and maintain the frame alignment When a logic one is written to the ALGO bit position the framer is enabled to use the second of the framing algorithms where only the first A1 framing byte and the first 4 bits of the last A2 framing byte 12 bits total are examined This algorithm examines only 12 bits of the framing pattern regardless of the STS mode all other framing bits are ignored When a
52. Z1 S1 byte contained in the receive stream is extracted into this register No interrupt is asserted on the change of this nibble In addition when the 21 51 CAP bit in the RASE Configuration Control register selects debouncing the upper nibble is only updated when eight of the same consecutive lower nibbles are received Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 192 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 12 TEST FEATURES DESCRIPTION Simultaneously asserting low the CSB RDB and WRB inputs causes all digital output pins and the data bus to be held in a high impedance state This test feature may be used for board testing Test mode registers are used to apply test vectors during production testing of the S UNI QUAD Test mode registers as opposed to normal mode registers are selected when TRS A 10 is high Test mode registers may also be used for board testing When all of the TSBs within the S UNI QUAD are placed in test mode 0 device inputs may be read and device outputs may be forced via the microprocessor interface refer to the section Test Mode O0 for details In addition the S UNI QUAD also supports a standard IEEE 1149 1 five signal JTAG boundary scan test port for use in board testing All digital device inputs may be read and all digital device outputs may be forced vi
53. and loads all the performance meter registers in the RSOP RLOP RPOP RXCP and TXCP blocks for channel 1 TIP remains high while the transfer is in progress and is set to a logic zero when the transfer is complete TIP can be polled by a microprocessor to determine when the accumulation interval transfer is complete CHRESET The CHRESET bit allows the Channel to be reset under software control If the CHRESET bit is a logic one the entire channel is held in reset This bit is not self clearing Therefore a logic zero must be written to bring the channel out of reset Holding a channel in a reset state places it into a low power stand by mode A hardware reset clears the CHRESET bit thus negating the software reset Otherwise the effect of a software reset is equivalent to that of a hardware reset Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 68 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x06 S UNI QUAD Channel Configuration Bit Type Function Default Bit 7 R W AUTOPFEBE 1 Bit 6 R W AUTOLFEBE Bit 5 R W AUTOLRDI Bit 4 R W AUTOPRDI Bit 3 R W Reserved Bit 2 R W Reserved Bit 1 R W Reserved Bit 0 R W Reserved AUTOPRDI The AUTOPRDI bit determines whether STS path remote defect indication RDI is sent immediately upon detection of an incoming alarm W
54. are valid a maximum of 67 RCLK periods after a transfer is triggered Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 147 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD by a write to one of RXCP s performance monitor counters or to the S UNI QUAD Channel Reset and Monitoring Update register Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 148 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register Ox6E RXCP Idle Cell Counter LSB Bit 4 ICELL 4 Bit 3 ICELL 3 Bit 2 ICELL 2 Bit 1 ICELL 1 Bit 0 R ICELL O0 Register Ox6F RXCP Idle Cell Counter Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 149 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x70 RXCP Idle Cell Counter MSB Bit Type Function Default Bt7 Bite Unused Bits Unused X Bt4 ___ Unused X Bits X Bt2 R ICELL 18 X Bt ICEL IZ R Bit 0 ICELL 16 ICELL 18 0 The ICELL 18 0 bits indicate the number of idle cells received during the l
55. bitg BLKFEBE causes path FEBE errors to be reported and accumulated on a block basis A single path FEBE error is accumulated for a block if the received FEBE code for that block is between 1 and 8 inclusive When BLKFEBE is set low path FEBE errors are accumulated on an error basis Reserved The reserved bits must be programmed to logic zero for proper operation Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 119 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register Ox3D RPOP Error Event Control Bit Type Function Default Bit 7 R W SOS 0 Bit 6 R W ENSS Bit 5 R W BLKBIP Bit 0 R W Reserved This register contains error event control bits BLKBIPO When BLKBIPO is a logic one path FEBE indications are generated on a block basis A single FEBE is transmitted if one or more path B3 error indications are detected per frame When BLKBIPO is a logic zero the transmitted FEBE indicates the number of B3 errors detected between 0 and 8 errors per frame BLKBIP When BLKBIP is a logic one B3 errors are reported and accumulated on a block basis A single B3 error is accumulated and reported to the TPOP if one or more B3 errors are detected per frame When BLKBIP is a logic zero each B3 error is accumulated and reported ENSS The ENSS bit controls whether the SS bits in th
56. bring the S UNI QUAD out of reset Holding the S UNI QUAD in a reset state places it into a low power stand by mode A hardware reset clears the RESET bit thus negating the software reset Otherwise the effect of a software reset is equivalent to that of a hardware reset Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 60 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x01 S UNI QUAD Master Configuration Bit Type Function Default Bit 7 R W PECLV 0 Bit 6 R W Reserved Bit 5 R W TFPO CH 1 Bit O R W Reserved TFPO CH 1 0 The transmit frame pulse channel select TFPO CH 1 0 bits selects which channel s transmit frame pulse is available on the TFPO output pin Since the RFPO1 4 output pins are providing transmit timing information for loop timed channels it is suggested but not mandatory that a self timed channel be selected Self timed channels all operate off the same clock synthesis unit and thus have a common timing reference their frequency will be identical although their frame pulses might not be aligned Table 5 TFPO Channel Selection TEPO 0 erected phannet 01 Channel 2 10 Channel 3 11 Channel 4 PECLV The PECL reveiver input voltage PECLV bit configures the PECL receiver level shifter When PECLV is set t
57. by byte Incorrect HCS cell by cell ALPHA consecutive incorrect HCS s cell by cell DELTA consecutive correct HCS s cell by cell The values of ALPHA and DELTA determine the robustness of the delineation process ALPHA determines the robustness against false misalignments due to bit errors DELTA determines the robustness against false delineation in the synchronization process ALPHA is chosen to be 7 and DELTA is chosen to be 6 These values result in an average time to delineation of 33 66 us for the STS 3c STM 1 rate 10 6 2 Descrambler The self synchronous descrambler operates on the 48 byte cell payload only The circuitry descrambles the information field using the x49 1 polynomial The descrambler is disabled for the duration of the header and HCS fields and may optionally be disabled for the payload 10 6 3 Cell Filter and HCS Verification Cells are filtered or dropped based on HCS errors and or a cell header pattern Cell filtering is optional and is enabled through the RXCP registers Cells are passed to the receive FIFO while the cell delineation state machine is in the SYNC state as described above When both filtering and HCS checking are Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 44 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD enabled cells are drop
58. cells are transmitted when the TXCP detects that no outstanding cells exist in the transmit FIFO GFC 3 0 The GFC 3 0 bits contain the first second third and fourth bit positions of the first octet of the idle unassigned cell pattern Idle unassigned cells are transmitted when the TXCP detects that no outstanding cells exist in the transmit FIFO The all zeros pattern is transmitted in the VCI and VPI fields of the idle cell Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 159 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x85 TXCP Idle Cell Payload Control Bit Type Function Default Bit7 R W PAYLD 7 0 Bit R W PAYLD 6 Bits R W 5 BitO R W PAYLDIO PAYLD 7 0 The PAYLD 7 0 bits contain the pattern inserted in the idle cell payload Idle cells are inserted when the TXCP detects that the transmit FIFO contains no outstanding cells PAYLD 7 is the most significant bit and is the first bit transmitted PAYLD O is the least significant bit Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 160 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x86 TXCP Transmit Cell Count LSB Bit Type Funct
59. counters or to the S UNI QUAD Channel Reset and Monitoring Update register Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 146 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0 6 RXCP Receive Cell Counter LSB Bit Type Function Default Bt7 R RCEL Z Bite X Bits R RCELL S X Bit 4 RCELL 4 Bit 3 RCELL 3 Bit 2 RCELL 2 Bit 1 RCELL 1 Bit 0 R RCELL O X Register 0 6 RXCP Receive Cell Counter Bit Function Default Bt7 R RCELL IS Bite R RCELL 14 x Bits R RCELL IS xX Bt4 R RCELL IZ X Bits R RCELL M Bit2 R RCELLIO X Bt RCELL X Bito R X Register 0 60 RXCP Receive Cell Counter MSB Bit Type Function Default Bt7 X Bite X Bt5 X Bt4 Unused Bits Unused Bt2 R RCELL IS Xx Bit R Bito R RCELL I6 X RCELL 20 0 The RCELL 18 0 bits indicate the number of cells received and written into the receive FIFO during the last accumulation interval Cells received and filtered due to HCS errors or Idle cell matches are not counted The counter should be polled every second to avoid saturation The contents of these registers
60. current instruction If the selected register does not allow parallel loads or no loading is required by the current instruction the test register maintains its value Loading occurs on the rising edge of TCK Shift DR The shift data register state is used to shift the selected test data registers by one stage Shifting is from MSB to LSB and occurs on the rising edge of TCK Update DR The update data register state is used to load a test register s parallel output latch In general the output latches are used to control the device For example for the EXTEST instruction the boundary scan test register s parallel output latches are used to control the device s outputs The parallel output latches are updated on the falling edge of TCK Capture IR The capture instruction register state is used to load the instruction register with a fixed instruction The load occurs on the rising edge of TCK Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 215 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Shift IR The shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage Shifting is from MSB to LSB and occurs on the rising edge of TCK Update IR The update instruction register state is used to load a new instruction into the instruc
61. device identification and boundary scan Using the TAP device input logic levels can be read device outputs can be forced the device can be identified and the device scan path can be bypassed For more details on the JTAG port please refer to the Operations section Table 9 Instruction Register Length 3 bits Instructions Selected Register Instruction Codes IR 2 0 EXTEST Boundary Scan 000 Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 196 di PMC Sierra Inc 5349 S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Instructions Selected Register Instruction Codes IR 2 0 IDCODE Identification 001 SAMPLE Boundary Scan 010 BYPASS Bypass 011 BYPASS Bypass 100 STCTEST Boundary Scan 101 BYPASS Bypass 110 BYPASS Bypass 111 Table 10 Identification Register Length 32 bits Version number OH Part Number 5349H Manufacturer s identification code OCDH Device identification 053490CDH Length 155 bits Table 11 Boundary Scan Register Pin Register Cell Type I D Bit Pin Enable Register Cell Type Bit Enable Bit Bit A 7 0 5 154 147 IN CELL 00000 101 ALE 146 IN CELL 0 CSB 145 IN CELL 0 WRB 144 IN CELL 1 RDB 143 IN CELL 1 RSTB 142 IN CELL 0 D 7 0 141 134 lO CELL 10101 010
62. features of the S UNI QUAD Reserved The reserved bits must be programmed to their default value proper operation Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 72 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x0A S UNI QUAD Channel Interrupt Status 1 This register allows the source of an active interrupt to be identified down to the block level within a given channel Further register accesses are required for the block in question to determine the cause of an active interrupt and to acknowledge the interrupt source RSOPI The RSOPI bit is high when an interrupt request is active from the RSOP block The RSOP interrupt sources are enabled in the RSOP Control Interrupt Enable Register RLOPI The RLOPI bit is high when an interrupt request is active from the RLOP block The RLOP interrupt sources are enabled in the RLOP Interrupt Enable Status Register RPOPI The RPOPI bit is high when an interrupt request is active from the RPOP block The RPOP interrupt sources are enabled in the RPOP Interrupt Enable Register RXCPI The RXCPI bit is high when an interrupt request is active from the RXCP block The RXCP interrupt sources are enabled in the RXCP Interrupt Enable Status Register Proprietary and Confidential to PMC Sierra Inc and for its Customers
63. for the recommended settings Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 183 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register OXEA RASE SF Clearing Threshold Bit4 RW SFCTHI4 Bit3 RW SFCTH 3 Bit2 RW SFCTH 2 SFCTH 0 Register OXEB RASE SF Clearing Threshold BitO RW SFCTH 8 SFCTH 1 1 0 The SFCTH 11 0 value determines the threshold for the removal of the SF alarm The SF alarm is removed when the number of B2 errors accumulated during an evaluation window is less than the SFCTH 11 0 value Refer to the Operations section for the recommended settings Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 184 S UNI QUAD DATASHEET PMC 971239 di PMC Sierra Inc PM5349 S UNI QUAD ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register OXEC RASE SD Accumulation Period Bit Type Function Default Bit7 RW SDSAP7Z 0 Bite RW SDSAPE 0 Bits RW SDSAP S 0 Bit4 RW SDSAP4 0 Bits RW SDSAPS 0 Bit2 RW SDSAP 2 0 Bit 7 Bit 6 Bit 5 Bit4 R W SDSAP 12 Bit 3 Bit 2 Bit RW SDSAP S Bit 0 R W R W R W R W SDSAP 15 SDSAP 14 SDSAP 13 SDSAP 11 SDSAP 10 SDSAP 8 0 P
64. in the receive stream and performs serial to parallel conversion on octet boundaries 10 2 Receive Section Overhead Processor RSOP The Receive Section Overhead Processor RSOP provides frame synchronization de scrambling section level alarm and performance monitoring 10 2 1 Framer The Framer Block determines the in frame out of frame status of the receive stream Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 33 F2 MC PMC Serta ING PM5349 S UNI QUAD PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD S UNI QUAD DATASHEET While in frame the framing bytes A1 A2 in each frame are compared against the expected pattern Out of frame is declared when four consecutive frames containing one or more framing pattern errors have been received While out of frame the SIPO block monitors the receive stream for an occurrence of the framing pattern When a framing pattern is recognized the Framer block verifies that an error free framing pattern is present in the next frame before declaring in frame 10 2 2 Descramble The Descramble Block utilizes a frame synchronous descrambler to process the receive stream The generating polynomial is x 6 1 and the sequence length is 127 Details of the de scrambling operation are provided in the references Note that the framing bytes A1 and A2 and the trace growth bytes J0 Z0 are not descrambled A registe
65. logic zero is written to the ALGO bit position the framer is Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 80 F2 PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD enabled to use the first of the framing algorithms where all the A1 framing bytes and all the A2 framing bytes are examined This algorithm examines all 48 bits of the STS 3c STM 1 AU3 AU4 framing pattern FOOF The FOOF bit controls the framing of the RSOP When a logic one is written to FOOF the RSOP is forced out of frame at the next frame boundary The FOOF bit is a write only bit register reads may yield a logic one or a logic zero DDS The DDS bit is set to logic one to disable the de scrambling of the STS 3c STM 1 stream When DDS is a logic zero de scrambling is enabled BIPWORD The BIPWORD bit position enables the accumulating of section block BIP errors When a logic one is written to the BIPWORD bit position one or more errors in the BIP 8 byte result in a single error accumulated in the B1 error counter When a logic zero is written to the BIPWORD bit position all errors in the B1 byte are accumulated in the B1 error counter Reserved The reserved bits must be programmed to logic zero for proper operation Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 81 ON AC scs MC
66. payload The S UNI QUAD frames to the ATM payload using cell delineation HCS error correction is provided Idle unassigned cells may be dropped according to a programmable filter Cells are also dropped upon detection of an uncorrectable header check sequence error The ATM cell payloads are descrambled The ATM cells that are passed are written to a four cell FIFO buffer The received cells are read from the FIFO using a 16 bit wide Utopia level 2 compliant datapath interface Counts of received ATM cell headers that are errored and uncorrectable and also those that are errored and correctable are accumulated independently for performance monitoring purposes The S UNI QUAD transmits SONET SDH streams using a bit serial interface and formats section line and path overhead appropriately It synthesizes the transmit clock from a lower frequency reference and performs framing pattern insertion A1 A2 scrambling alarm signal insertion and creates section line and path bit interleaved parity B1 B2 B3 as required to allow performance monitoring at the far end Line and path far end block error indications M1 G1 are also inserted The S UNI QUAD generates the payload pointer H1 H2 and inserts the synchronous payload envelope which carries the ATM cell payload The S UNI QUAD also supports the insertion of a large variety of errors into the transmit stream such as framing pattern errors bit interleaved parity errors and illegal pointer
67. positive pointer movements A logic zero to logic one transition on this bit enables the insertion of a single positive pointer justification in the transmit stream This register bit is automatically cleared when the pointer movement is inserted NSE The NSE bit controls the insertion of negative pointer movements A logic zero to logic one transition on this bit enables the insertion of a single negative pointer justification in the transmit stream This register bit is automatically cleared when the pointer movement is inserted NDF The NDF bit controls the insertion of new data flags in the inserted payload pointer When a logic one is written to this bit position the pattern contained in the NDF 3 0 bit positions in the TPOP Arbitrary Pointer MSB Register is inserted continuously in the payload pointer When a logic zero is written to this bit position the normal pattern 0110 is inserted in the payload pointer PLD The PLD bit controls the loading of the pointer value contained in the TPOP Arbitrary Pointer Registers Normally the TPOP Arbitrary Pointer Registers are written to set up the arbitrary new pointer value the S bit values and the NDF pattern A logic one is then written to this bit position to load the new pointer value The new data flag bit positions are set to the programmed NDF Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 124 S UNI QUAD DATASHEET PMC 971239
68. significant bit corresponding to the first bit bit 1 transmitted K1 0 is the least significant bit corresponding to the last bit bit 8 transmitted The bits in this register are double buffered so that register writes do not need to be synchronized to SONET SDH frame boundaries The insertion of a new APS code value is initiated by a write to this register The contents of this register and the TLOP Transmit K2 Register are inserted in the transmit stream starting at the next frame boundary Successive writes to this register must be spaced at least two frames 250 us apart Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 97 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x23 TLOP Transmit K2 Bit Type Function Default Bit7 R W K2 7 0 Bit6 R W K2 6 Bits R W K2 5 BitO R W K2 0 K2 7 0 The K2 7 0 bits contain the value inserted in the K2 byte when the APSREG bit in the TLOP Control Register is a logic one K2 7 is the most significant bit corresponding to the first bit bit 1 transmitted K2 0 is the least significant bit corresponding to the last bit bit 8 transmitted The bits in this register are double buffered so that register writes do not need to be synchronized to SONET SDH frame boundaries The insertion of a new APS code value is initiated by a wr
69. the EPRDI bits in the G1 byte are set according to the setting of the Channel Auto Enhanced Path RDI Control registers 0x92 and 0x93 Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 122 NAC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD EPRDIEN The enhanced path receive defect indication alarm enable bit EPRDIEN controls the use of 3 bit RDI mode When EPRDIEN is set to logic 0 the basic path RDI scheme is used and only G1 5 is used to indicate PRDI When EPRDIEN is set to logic 1 the enhanced path RDI scheme is used and the three G1 7 5 bits are used to indicate PRDI The actual three bit code will be controlled according to the EPRDISRC Reserved The reserved bits must be programmed to logic zero for proper operation Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 123 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x41 TPOP Pointer Control Bit Type Function Default Bit 7 R W Reserved 0 Bit 6 R W FTPTR Bit 5 R W SOS Bit 4 R W PLD Bit 3 R W NDF Bit 2 R W NSE Bit 1 R W PSE Bit O R W Reserved This register allows control over the transmitted payload pointer for diagnostic purposes PSE The PSE bit controls the insertion of
70. the S UNI QUAD Channel Enhanced Path RDI Control register controls the auto assertion of enhanced path RDI on the TPOP transmit stream Since the S UNI QUAD provides STS 3c STM 1 mapping this register controls the entire SONET SDH stream EPRDI EN The EPRDI EN bit enables the automatic insertion of enhanced RDI in the local transmitter When EPRDI EN is a logic one auto insertion is enabled using the event enable bits in this register When EPRDI EN is a logic zero enhanced path RDI is not automatically inserted in the transmit stream NOPAISCONEPRDI When set high the NOPAISCONEPRDI bit disables enhanced path RDI assertion when path AIS concatenation PAISCON events are detected in the receive stream If enabled when the event occurs bit 6 of the G1 byte is set low while bit 7 of the G1 byte is set high NOPAISCONEPRDI has precedence over PSLMERDI and UNEQERDI When NOPAISCONEPRDI is set low reporting of enhanced RDI is according to PSLMERDI and UNEQERDI and the associated alarm states PAISCONPRDI When set high the PAISCONPRDI bit enables path RDI assertion when path AIS concatenation PAISCON events are detected in the receive stream When PAISCONPRDI is set low path AIS concatenation events have no effect on path RDI Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 169 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6
71. the S UNI QUAD device to a system reference TFPI is internally used to align a master frame pulse counter When TFPI is not used this counter is free running TFPI should be brought high for a single TCLK period every 2430 STS 3c STM 1 TCLK cycles or a multiple thereof TFPI shall be tied low if such synchronization is not required cannot be used as an input to a loop timed channel For TFPI to operate correctly it is required that the TCLK TFPO output be configured to output the CSU byte clock The TFPI EN register bits allow to individually configure each channel to use the global framing pulse counter and TFPI for framing alignment TFPI is sampled on the rising edge of TCLK but only when the TTSEL register bit is set to logic zero When TTSEL is set to logic one TFPI is unused This pin is shared by all channels Output AC11 The transmit byte clock TCLK output provides a timing reference for the S UNI QUAD self timed channels TCLK always provide a divide by eight of the synthesized line rate clock and thus has a nominal frequency of 19 44 MHz TFPI is sampled on the rising edge of TCLK TCLK does not apply to internally loop timed channels in which case the channel s RCLK provides transmit timing information Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 14 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SA
72. the corresponding port DRCA can be configured to be de asserted when either zero or four bytes remain in the selected addressed FIFO DRCA will thus transition low on the rising edge of RFCLK after Payload word 24 RCALEVELO 1 or 19 RCALEVELO 0 is output if the PHY being polled is the same as the PHY in use DRCA x is updated on the rising edge of RFCLK PHY OEN Input A19 The PHY Output Enable PHY OEN signal controls the operation of the system interface When set to logic zero all System Interface outputs are held tristate When PHY OEN is set to logic one the interface is enabled PHY OEN can be overwritten by the PHY EN Master System Interface Configuration register bit PHY OEN and PHY EN are OR ed together to enable the interface When the S UNI QUAD is the only PHY layer device on the bus PHY OEN can safely be tied to logic one When the S UNI QUAD shares the bus with other devices then PHY OEN must be tied to logic zero and the PHY EN register bit used to enable the bus once its PHY ADR 2 0 is programmed in order to avoid conflicts Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 22 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 9 3 Microprocessor Interface Signals Input B11 The active low chip select CSB signal is low during S UNI QUAD Sr accesses Note th
73. to frame boundaries 10 8 2 BIP 8 Insert The BIP 8 Insert Block calculates and inserts the BIP 8 error detection code B1 into the transmit stream The BIP 8 calculation is based on the scrambled data of the complete STS 3c STM 1 frame The section BIP 8 code is based on a bit interleaved parity calculation using even parity Details are provided in the references The calculated BIP 8 code is then inserted into the B1 byte of the following frame before scrambling BIP 8 errors may be continuously inserted under register control for diagnostic purposes Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 47 F2 MC PMC Serta ING PM5349 S UNI QUAD PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD S UNI QUAD DATASHEET 10 8 3 Framing and Identity Insert The Framing and Identity Insert Block inserts the framing bytes A1 A2 into the STS 3c STM 1 frame Framing bit errors may be continuously inserted under register control for diagnostic purposes 10 8 4 Scrambler The Scrambler Block utilizes a frame synchronous scrambler to process the transmit stream when enabled through an internal register accessed via the microprocessor interface The generating polynomial is x7 x6 1 Precise details of the scrambling operation are provided in the references Note that the framing bytes and the identity bytes are not scrambled All zeros may be continuously inserted after s
74. transitions on the RCLK3 output RCLK3A is set high on a rising edge of RCLKS and is set low when this register is read RCLKAA The Channel 4 RCLK active RCLKAA bit monitors for low to high transitions on the RCLK4 output RCLKAA is set high on a rising edge of RCLK4 and is set low when this register is read Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 65 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x04 S UNI QUAD Master Interrupt Status When the interrupt output INTB goes low this register allows the source of an active interrupt to be identified down to the channel level Further register accesses are required for the channel in question to determine the cause of an active interrupt and to acknowledge the interrupt source CHNL 1I bit is high when an interrupt request is active from the channel 1 The Channel 1 Interrupt Status register should be read to identify the source of the interrupt CHNL2I The CHNL2I bit is high when an interrupt request is active from the channel 2 The Channel 2 Interrupt Status register should be read to identify the source of the interrupt CHNLSI The CHNLSI bit is high when an interrupt request is active from the channel 3 The Channel 3 Interrupt Status register should be read to identify the sour
75. value using the TPOP Arbitrary Pointer LSB and MSB Registers or by inserting positive and negative pointer movements using the PSE and NSE register bits It is recommended the CPTR 9 0 value be software de bounced to ensure a correct value is received Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 127 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x45 TPOP Arbitrary Pointer LSB Bit Type Function Default Bt7 R W APTR 7 0 Bit R W APTR 6 Bt5 R W APTRI5 Bit R W APTR 0 This register allows an arbitrary pointer to be inserted for diagnostic purposes APTR 7 0 The APTR 7 0 bits along with the APTR 9 8 bits in the TPOP Arbitrary Pointer MSB Register are used to set an arbitrary payload pointer value The arbitrary pointer value is inserted in the transmit stream by writing a logic one to the PLD bit in the TPOP Pointer Control Register If the FTPTR bit in the TPOP Pointer Control register is a logic one the current APTR 9 0 value is inserted into the payload pointer bytes H1 and H2 in the transmit stream Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 128 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Registe
76. with Word 1 containing the first two header octets Word 3 of this structure contains the HCS octet in bits 15 to 8 In the receive direction the lower 8 bits of Word 3 contain the HCS status octet An all zeros pattern in these 8 bits indicates that the associated header is error Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 204 F2 PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD free An all ones pattern indicates that the header contains an uncorrectable error if the HCSPASS bit in the RXCP Control Register is set to logic zero the all ones pattern will never be passed in this structure An alternating ones and zeros pattern 0xAA indicates that the header contained a correctable error In this case the header passed through the structure is the corrected header In the transmit direction the HCS bit in the TXCP Control register determines whether the HCS is calculated internally or is inserted directly from the upper 8 bits of Word 3 The lower 8 bits of Word 3 contain the HCS control octet The HCS control octet is an error mask that allows the insertion of one or more errors in the HCS octet A logic one in a given bit position causes the inversion of the corresponding HCS bit position for example a logic one in bit 7 causes the most significant bit of the HCS to be inverted 13 3 Bit Error Rate
77. 1 June 1995 e PMC 950820 SONET SDH Bit Error Threshold Monitoring Application Note Issue 2 September 1998 Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 5 S UNI QUAD DATASHEET PMC 971239 M di PMC Sierra Inc PM5349 S UNI QUAD ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 4 DEFINITIONS The following table defines the abbreviations for the S UNI QUAD CRSI CRU and SIPO CRU Clock Recovery Unit CSPI CSU and PISO CSU Clock Synthesis Unit RASE Receive APS Synchronization Extractor and Bit Error Monitor RLOP Receive Line Overhead Processor RPOP Receive Path Overhead Processor RSOP Receive Section Overhead Processor RXCP Receive ATM Cell Processor TLOP Transmit Line Overhead Processor TPOP Transmit Path Overhead Processor TSOP Transmit Section Overhead Processor TXCP Transmit ATM Cell Processor Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 6 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 5 APPLICATION EXAMPLES The PM5349 S UNI QUAD is intended for use in equipment implementing Asynchronous Transfer Mode ATM User Network Interfaces UNI The S UNI QUAD may find application at either end of switch to switch links or switch to terminal links The
78. 124 224 324 S UNI QUAD Channel Transmit Synchronization Message 51 Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 53 ON AC scs MC PME Siera E PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Address A 10 0 Description 326 Reserved 030 130 230 330 RPOP Status Control E D 336 RPOP Pointer MSB and RDI Filter Control 33E Reserved 343 T CD Current Pointer LSB Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 54 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Address A 10 0 Description 1 2 3 4 349 Path Status Reserved 356 Reserved 35E Reserved 60 060 160 260 360 RXCP Configuration 1 066 166 266 366 RXCP LCD Count Threshold EA 68 068 168 268 368 RXCP Idle Cell Header Mask 69 069 169 269 369 RXCP Corrected HCS Error Count 6B 06B 16B 26B 36B RXCP Received Cell Count LSB 6D 060 16D 26D 36D Received Cell Count MSB Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 55 PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSU
79. 2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD device inputs and outputs can be sampled by loading the boundary scan register using the Capture DR state The sampled values can then be viewed by shifting the boundary scan register using the Shift DR state IDCODE The identification instruction is used to connect the identification register between TDI and TDO The device s identification code can then be shifted out using the Shift DR state STCTEST The single transport chain instruction is used to test out the TAP controller and the boundary scan register during production test When this instruction is the current instruction the boundary scan register is connected between TDI and TDO During the Capture DR state the device identification code is loaded into the boundary scan register The code can then be shifted out output TDO using the Shift DR state 13 7 Board Design Recommendations The noise environment and signal integrity are often the limiting factors in system performance Therefore the following board design guidelines must be followed in order to ensure proper operation 1 Use a single plane for both digital and analog grounds 2 Provide separate 3 3 volt analog transmit 3 3 volt analog receive and 3 3 volt digital supplies but otherwise connect the supply voltages together at one point close to the connector where 3
80. 3 volts is brought to the card 3 Ferrite beads are not advisable in digital switching circuits because inductive spiking di dt noise is introduced into the power rail Simple RC filtering is probably the best approach provided care is taken to ensure the IR drop in the resistance does not lower the supply voltage below the recommended operating voltage 4 Separate high frequency decoupling capacitors are recommended for each analog power TAVD RAVD and QAVD pin as close to the package pin as possible Separate decoupling is required to prevent the transmitter from coupling noise into the receiver and to prevent transients from coupling into some reference circuitry Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 217 S UNI QUAD DATASHEET PMC 971239 F2 MC PMC Serta ING PM5349 S UNI QUAD ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 5 The high speed serial streams TXD and RXD must be routed with controlled impedance circuit board traces and must be terminated with a matched load Normal CMOS type design rules are not recommended and will reduce the performance of the device 13 8 Power Supply Sequencing Due to ESD protection structures in the pads it is necessary to exercise caution when powering a device up or down ESD protection devices behave as diodes between power supply pins and from I O pins to power supply pins Under extreme conditions it is po
81. 4 6V Bias Voltage Vss Va 3 to 5 5V Voltage on Any Pin 0 3V to V 4 10 3V Temperature Static Discharge Voltage 1000 V Latch Up Current 100 mA DC Input Current 20 mA Lead Temperature 230 C Absolute Maximum Junction 150 C Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 226 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 16 D C CHARACTERISTICS TA 40 C to 85 C Vpp 3 3V 10 Vpp lt BIAS lt 5 5V Typical Conditions TA 25 C Vpp 3 3V VBias 5V Table 14 D C Characteristics Symbol Parameter min Typ Max Units Conatons BM EN _ _ Low Voltage Volts n Input Low TTL Only voltage Input Low Voltage Volts Guaranteed Input Low PECL Only Input High Volts Guaranteed Input High Voltage voltage TTL Only VPIH Input Low Voltage Ayp Volts Guaranteed Input High PECL Only 1 0 0 8 voltage Output or Bi 0 4 Volts Guaranteed output Low directional Low voltage at VDD 2 97V and Voltage loL maximum rated for pad Note 4 Output or Bi Volts Guaranteed output High directional High voltage at VDD 2 97V and Voltage rated current for pad Note 4 Reset Input High Volts Applies to RSTB Voltage TRSTB only Reset Input Low Volts App
82. AC PMC Sierra Inc ISSUE 6 PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 SATURN USER NETWORK INTERFACE 155 QUAD 8 PIN DIAGRAM The S UNI QUAD is available in a 304 pin SBGA package having a body size of 31 mm by 31 mm and a ball pitch of 1 27 mm 23 22 21 20 19 18 7 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A TDAT 12 TDAT 15 PHY RAVS1_B B TDAT 13 6 VSS TDAT 10 TDAT 14 D TDAT 4 TDAT 6 9 TDAT 11 NIC D 7 E TDAT 0 TDAT 3 TDAT S TDAT S F TDAT 2 RAVS1_A G 0 TADR 2 TADRI4 TDAT 1 H TADR 1 TADRI3 RAVS2 A j TSOC K DICAM gus RAVS2 B L DTCA 1 DTCA 2 TAVD1_A M DRCAIAT TAVS1_B N DRCA 2 DRCA 1 RAVS3 B P RADR 3 R RADR 4 RADR 2 T RADR 0 v RDAT 15 RDAT 14 RDAT 12 RDAT 9 WF RDAT 10 RDAT 7 5 2 AC vss erou RAVS4 VSS BOTTOM VIEW Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 11 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 9 DESCRIPTION 9 1 Line Side Interface Signals me we Emm REFCLK Input The reference clock input REFCLK must provide a jitter free 19 44 MHz reference clock It
83. AND OVERHEAD BYTE USAGE 201 13 1 1 ATM MAPPING niiin iere ree Dee see eee 201 13 1 2 TRANSPORT AND PATH OVERHEAD 202 13 2 CELL DATA 204 13 8 BIT ERROR RATE 205 13 6 GLOGKING OPTIONS E de ERR Ea Pei RO 206 13 5 LOOPBACK 208 13 6 lt JTAG SUPPORT tabe et eter im e Pr 212 13 6 1 TAP GONTROLLER iae rettet 213 13 6 1 1 STATES otia twee tad ded a ON ntis 215 13 6 1 2 INSTRUCTIONS tdt etas 216 13 7 BOARD DESIGN RECOMMENDATIONS seen 217 13 8 POWER SUPPLY SEQUENCING eene 218 Proprietary and Confidential to PMC SIERRA Inc and for its Customers Internal Use M di PMC Sierra Inc PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 13 9 ANALOG POWER SUPPLY 219 13 10 INTERFACING TO ECL OR PECL DEVICES eee 220 13 11 INITIALIZING THE S UNI QUAD 1 00 eee ee teeter tenet mme enne 222 13 12 USING THE S UNI QUAD WITH A 5 VOLT 222 14 FUNGTIONAL TIMIING 2 Liceo einer Ee E de EROR 223 14 44 ATMUTOPIA LEVEL 2 SYSTEM INTERFACE 223 15 ABSOLUTE MAXIMUM 5
84. B is high RSOC is sampled on the rising edge of RFCLK RENB Input P22 UTOPIA Receive multi PHY Read Enable RENB The RENB signal is used to initiate reads from the receive FIFO s RENB works as follows When RENB is sampled high no read is performed and RDAT 15 0 RPRTY and RSOC are tristated and the address on RADR 4 0 is latched to select the device or port for the next FIFO access When RENB is sampled low the word on the RDAT bus is read from the selected receive FIFO RENB must operate in conjunction with RFCLK to access the FIFO s at a high enough rate to prevent FIFO overflows The system may de assert RENB at anytime it is unable to accept another byte RENB is sampled on the rising edge of RFCLK Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 20 S UNI QUAD DATASHEET PMC 971239 ISSUE 6 PMC Serta ING PM5349 S UNI QUAD SATURN USER NETWORK INTERFACE 155 QUAD Pin Name Type Pin No Function RADRI4 RADR 3 RADR 2 RADR 1 RADR O Input R23 P20 R22 R21 T22 UTOPIA Receive Read Address RADR 4 0 The RADR 4 signal is used to select the FIFO and hence port that is read from using the RENB signal and the FIFO whose cell available signal is visible on the RCA output Note that address Ox1F is the null PHY address and will not be identified to any port on the S UNI QUAD RAD
85. CA signal indicates when a cell is available in the transmit FIFO for the port polled by TADR 4 0 when TENB is asserted When high TCA indicates that the corresponding transmit FIFO is not full and a complete cell may be written When TCA goes low it can be configured to indicate either that the corresponding transmit FIFO is near full or that the corresponding transmit FIFO is full TCA will transition low on the rising edge of TFCLK after the Payload word 19 TCALEVELO 0 or 23 TCALEVELO 1 is sampled if the PHY being polled is the same as the PHY in use To reduce FIFO latency the FIFO depth at which TCA indicates full can be set to one two three or four cells Note that regardless of what fill level TCA is set to indicate full at the transmit cell processor can store 4 complete cells TCA is tri stated when either the null PHY address 0x1F or an address not matching the address space set by PHY ADR 2 0 is latched from the TADR 4 0 inputs when TENB is high TCA is updated on the rising edge of TFCLK TFCLK Input K20 UTOPIA Transmit FIFO Write Clock TFCLK This signal is used to write ATM cells to the four cell transmit FIFOs TFCLK cycles at a 50 MHz or lower instantaneous rate Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 18 S UNI QUAD DATASHEET PMC 971239 PMC Serta ING PM5349 S UNI QUAD ISSUE 6 SATURN USER NETW
86. D 10 9 4 Line FEBE Insert The Line FEBE Insert Block accumulates line BIP 24 errors B2 detected by the Receive Line Overhead Processor and encodes far end block error indications in the transmit M1 byte 10 10 Transmit Path Overhead Processor TPOP The Transmit Path Overhead Processor TPOP provides transport frame alignment generation pointer generation H1 H2 path overhead insertion and the insertion of path level alarm signals 10 10 1 Pointer Generator The Pointer Generator Block generates the outgoing payload pointer H1 H2 as specified in the references The concatenation indication the NDF field set to 1001 I bits and D bits set to all ones and unused bits set to all zeros is inserted in the second and third pointer byte locations in the transmit stream e 1 A normal pointer value locates the start of the SPE Note 0 lt normal pointer value lt 782 and the new data flag NDF field is set to 0110 Note that values greater than 782 may be inserted using internal registers to generate a loss of pointer alarm in downstream circuitry e 2 Arbitrary pointer values may be generated using internal registers These new values may optionally be accompanied by a programmable new data flag New data flags may also be generated independently using internal registers e 3 Positive pointer movements may be generated using a bit in an internal register A positive pointer movement is generated by inver
87. DI is a logic zero the APRDI bit position in the path status byte is set low PRDI The PRDI bit controls the insertion of the path remote defect indication When a logic one is written to this bit position the PRDI bit position in the path status byte is set high When a logic zero is written to this bit position the PRDI bit position in the path status byte is set low This bit is ignored when EPRDIEN is logic zero or when EPRDIEN and EPRDISRC are both logic one and the PRDI bit in the G1 byte bit 6 is set according to the setting of the Channel Auto Enhanced Path RDI Control registers 0x92 and 0x93 FEBE 3 0 The FEBE 3 0 bits are inserted in the FEBE bit positions in the path status byte The value contained in FEBE 3 0 is cleared after being inserted in the Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 131 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD path status byte Any non zero FEBE value overwrites the value that would normally have been inserted based on the number of receive B3 errors during the last frame When reading this register a non zero value in these bit positions indicates that the insertion of this value is still pending Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 132 S UNI QUAD DATASHEET PMC 971239 ON AC scs MC
88. E The FOVRE bit enables the generation of an interrupt due to an attempt to write the FIFO when it is already full When FOVRE is set to logic one the interrupt is enabled Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 157 NAC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD TPRTYE The TPRTYE bit enables transmit parity interrupts When set to logic one parity errors are indicated on INT and TPRTYI When set to logic zero parity errors are indicated using bit TPRTYI but are not indicated on output INT Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 158 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x84 TXCP Idle Cell Header Control Type Function Default R W GFC 3 Bit RW GFC 2 Bitb R W GFC 1 Bit4 R W GFC 0 Bits RW PTI 2 Bit2 RW PTI 1 CLP The CLP bit contains the eighth bit position of the fourth octet of the idle unassigned cell pattern Cell rate decoupling is accomplished by transmitting idle cells when the TXCP detects that no outstanding cells exist in the transmit FIFO PTI 3 0 The PTI 3 0 bits contains the fifth sixth and seventh bit positions of the fourth octet of the idle unassigned cell pattern Idle
89. E 6 SATURN USER NETWORK INTERFACE 155 QUAD Address A 10 0 Description 36F RXCP Idle Cell Count 377 Reserved 37C Reserved 80 080 180 280 380 Configuration 1 384 XCP Idle Cell Header Control 86 086 186 286 386 Transmit Cell Counter LSB 89 089 189 289 389 Reserved 002 38C Reserved Hap 18D 28D 38D Hesemed ENE NE EE NER EPRIELEEIPI m QUAD Channel Auto Enhanced Path RDI Control Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 56 PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Address A 10 0 Description RASE SF BERM Declaring Threshold MSB RASE SF BERM Clearing Threshold LSB RASE SF BERM Clearing Threshold MSB RASE SD BERM Accumulation Period LSB RASE SD BERM Declaring Threshold MSB RASE SD BERM Clearing Threshold LSB Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 57 PMC Serta ING PM5349 S UNI QUAD PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD S UNI QUAD DATASHEET Address A 10 0 Description Notes on Register Memory Map For all register accesses CSB must be low e Addr
90. E 6 SATURN USER NETWORK INTERFACE 155 QUAD BIPEE The BIPEE bit is an interrupt enable for the line BIP 24 errors When BIPEE is set to logic one an interrupt is generated when a line BIP 24 error B2 is detected FEBEE The FEBEE bit is an interrupt enable for the line far end block errors When FEBEE is set to logic one an interrupt is generated when FEBE M1 is detected Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 90 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x1A RLOP Line BIP 24 LSB Bit Type Function Default Bi7 R LBEZ Xx Bite R X Bits R LUBE X Bit4 R X Bits R 1 63 X Bt2 R Bey X Bt R LIBE X Bito R LBE X Register 0x1B RLOP Line BIP 24 D R DDD Bit Type Function Default Bit7 LBE I X Bit6 R LBE I Bits LBE I 25 Bit4 R X Bits R LIBET x Bt2 R LBEMO X Biti R LUBE X DI Bit 0 2 LBE 8 Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 91 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD
91. E and SDLE bits contained in the S UNI QUAD Channel Control Register The line loopback see Figure 14 connects the high speed receive data and clock to the high speed transmit data and clock and can be used for line side investigations including clock recovery and clock synthesis While in this mode the entire receive path is operating normally and cells can be received through the FIFO interface The serial diagnostic loopback see Figure 15 connects the high speed transmit data and clock to the high speed receive data and clock While in this mode the entire transmit path is operating normally and data is transmitted on the TXD outputs The parallel diagnostic loopback see Figure 16 connects the byte wide transmit data and clock to the byte wide receive data and clock While in this mode the entire transmit path is operating normally and data is transmitted on the TXD outputs Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 208 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Figure 14 Line Loopback Mode PHY_OEN RFCLK RENB RADB 4 0 RCA RSOC RPRTY DRCA 4 1 TRSTB fyvyivvyy INTB TCK 5 Utopia 5 RSTB TMS o System Interface RDB 9 S WRB TDI Eg CSB TDO 8 ALE gt 10 0 D 7 0 5 9 z 3 gt nu 5 6 8
92. FR ATM IP etc e Gibabit and terabit routers Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 4 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 3 REFERENCES e Bell Communications Research GR 253 CORE SONET Transport Systems Common Generic Criteria Issue 2 December 1995 e Bell Communications Research GR 436 CORE Digital Network Synchronization Plan Issue 1 Revision 1 June 1996 e TU T Recommendation G 703 Physical Electrical Characteristics of Hierarchical Digital Interfaces 1991 e ITU T Recommendation G 704 General Aspects of Digital Transmission Systems Terminal Equipment Synchronous Frame Structures Used At 1544 6312 2048 8488 and 44 736 kbit s Hierarchical Levels July 1995 ITU Recommendation G 707 Network Node Interface For The Synchronous Digital Hierarchy 1996 e Recommendation G781 Structure of Recommendations on Equipment for the Synchronous Design Hierarchy SDH January 1994 e ITU Recommendation G 783 Characteristics of Synchronous Digital Hierarchy SDH Equipment Functional Blocks 1996 ITU Recommendation 1 432 ISDN User Network Interfaces March 93 e ATM Forum ATM User Network Interface Specification V3 1 October 1995 e ATM Forum UTOPIA An ATM PHY Interface Specification Level 2 Version
93. Function A 10 TRS The test register select TRS signal selects between normal and test mode register accesses TRS is high during test mode register accesses and is low during normal mode register accesses The active low reset RSTB signal provides an asynchronous S UNI QUAD reset RSTB is a Schmitt triggered input with an integral pull up resistor The address latch enable ALE is active high and latches the address bus A 7 0 when low When ALE is high the internal address latches are transparent It allows the S UNI QUAD to interface to a multiplexed address data bus ALE has an integral pull up resistor The active low interrupt INTB signal goes low when a S UNI QUAD interrupt source is active and that source is unmasked The S UNI QUAD may be enabled to report many alarms or events via interrupts Examples of interrupt sources are loss of signal LOS loss of frame LOF line AIS line remote defect indication LRDI detect loss of pointer LOP path AIS path remote defect indication detect and others INTB is tristated when the interrupt is acknowledged via an appropriate register access INTB is an open drain output Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 24 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 9 4 JTAG Test Access Port Signals
94. IS line remote defect indication LRDI loss of pointer LOP path alarm indication signal PAIS path remote defect indication PRDI and path extended remote defect indicator PERDI Interprets the received payload pointer H1 H2 and extracts the STS 3c STM 1 synchronous payload envelope and path overhead Provides individual divide by 8 recovered clocks 19 44 MHz for each channel Provides individual 8KHz receive frame pulses for each channel 1 3 The Receive ATM Processor Extracts ATM cells from the received STS 3c STM 1 synchronous payload envelope using ATM cell delineation Provides ATM cell payload de scrambling Performs header check sequence HCS error detection and correction and idle unassigned cell filtering Detects Out of Cell Delineation OCD and Loss of Cell Delineation LCD Counts number of received cells idle cells errored cells and dropped cells Provides a synchronous 8 bit wide four cell FIFO buffer 1 4 The SONET Transmitter Synthesizes the 155 52 MHz transmit clock from a 19 44 MHz reference Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 2 F2 PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD e Provides a differential TTL serial interface can be adapted to PECL levels at 155 52 Mbit s e Provides a single transmit frame pulse input across the
95. Internal Use 108 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD LOPE The LOPE bit is the interrupt enable for LOP When LOPE is a logic one an interrupt is generated when the LOP state changes PSLE The PSLE bit is the interrupt enable for changes in the received path signal label When PSLE is a logic one an interrupt is generated when the received C2 byte changes Reserved The reserved bits must be programmed to logic zero for proper operation Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 109 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x33 EXTD 1 RPOP Interrupt Enable Bit 4 Unused Bit 3 Unused Bit 2 Unused NOTE To facilitate additional register mapping shadow registers have been added to registers 0x30 0x31 and 0x33 These shadow registers are accessed in the same way as the normal registers The EXTD extend register bit must be set in register 0x36 to allow switching between accessing the normal registers and the shadow registers This register allows interrupt generation to be enabled for path level alarm and error events ERDIE When EREDIE is a logic one an interrupt is generated when a path Enhanced RDI is detected Proprietary and Confidential to P
96. Loop timed RCLK Mode A is provided for all public user network interfaces UNIs and for private UNIs and private network node interfaces NNIs that are not synchronized to the recovered clock The transmit clock in a private UNI or a private NNI may be locked to an external reference or may free run The simplest implementation requires an oscillator free running at 19 44 MHz Mode A is selected by clearing the LOOPT bit of the Channel Control register REFCLK is multiplied by 8 to become the 155 52 MHz MHz transmit clock REFCLK must be jitter free The source REFCLK is also internally used as the clock recovery reference Mode B is provided for private UNIs and private NNIs that require synchronization to the recovered clock Mode B is selected by setting the LOOPT bit of the Master Control register Normally the transmit clock is locked to the receive data In the event of a loss of signal condition the transmit clock is synthesized from REFCLK Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 207 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 13 5 Loopback Operation The S UNI QUAD supports three loopback functions line loopback parallel diagnostic loopback and serial diagnostic loopback Each channel s loopback modes operate independently The loopback modes are activated by the PDLE LL
97. MC Sierra Inc and for its Customers Internal Use 110 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x34 RPOP Pointer Interrupt Enable Bit Type Function Default Bit 7 R W ILLJREQE 0 Bit 6 R W Reserved Bit 5 R W DISCOPAE Bit 0 R W NDFE This register is used to enable pointer event interrupts NDFE When a logic one is written to the NDFE interrupt enable bit position a change in active offset due to the reception of an enabled NDF NDF_enabled indication will activate the interrupt out INTB PSEE When a logic one is written to the PSEE interrupt enable bit position a positive pointer adjustment event will active the interrupt output INTB NSEE When a logic one is written to the NSEE interrupt enable bit position a negative pointer adjustment event will activate the interrupt output INTB ILLPTRE When a logic one is written to the ILLPTRE interrupt enable bit position an illegal pointer will activate the interrupt output INTB INVNDFE When a logic one is written to the INVNDFE interrupt enable bit position an invalid NDF code will activate the interrupt output INTB DISCOPAE When a logic one is written to the DISCOPAE interrupt enable bit position a change of pointer alignment event will activate the interrupt output INTB Proprietary and Confidential to PMC Sierra Inc and for its Customer
98. MSB LFE 19 0 Bits LFE 19 0 represent the number of line FEBE errors individual or block that have been detected since the last time the error count was polled The error count is polled by writing to any of the RLOP Line BIP Registers or Line FEBE Register addresses Such a write transfers the internally accumulated error count to the Line FEBE Registers within approximately 7 us and simultaneously resets the internal counter to begin a new cycle of error accumulation The count can also be polled by writing to the S UNI QUAD Channel Reset and Monitoring Update register 0x05 Writing to register 0x05 simultaneously loads all the performance meter registers in the RSOP RLOP RPOP RXCP and TXCP blocks Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 94 S UNI QUAD DATASHEET PMC 971239 F2 MC PMC Serta ING PM5349 S UNI QUAD ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x20 TLOP Control Bit Type Function Default Bit 7 Bit 6 Bit 5 R W R W R W Reserved Reserved APSREG 0 Bit 4 R W Reserved Bit 3 Bit 2 R W R W Reserved Reserved Bit 1 R W Reserved Bit 0 LRDI R W LRDI The LRDI bit controls the insertion of line far end receive failure LRDI When LRDI is set to logic one the TLOP inserts line RDI into the transmit SONET SDH stream Line RDI is inserted by transmitting the code 110 in bit
99. NA scs MC PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD PM5349 S UNI QUAD S UNI QUAD SATURN USER NETWORK INTERFACE 155 QUAD DATASHEET ISSUE 6 JULY 1999 PMC Sierra Inc 105 8555 Baxter Place Burnaby BC Canada V5A 4V7 604 415 6000 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD REVISION HISTORY Issue Issue Date Details of Change No 6 July 1999 General Update e Section 4 Augmented the DEFINITIONS table e Section 9 6 Changed TDO output drive from 2mA to 1mA changed other DC currents from 16mA to 4mA and 4mA to 2mA e Section 11 Added RPOP PAISCONV and LOPCONV status bits in Register 0x30 e Section 11 Clarified EPRDIEN register bit description in Register 0x40 e Section 11 Added H4INSB register bit to Register 0x82 e Section 11 Fixed logic level specification in Register 0x91 e Section 11 Changed 71 51 CAP bit description in Register OXE2 e Section 13 8 Enhanced Power Supply Sequencing information e Section 13 9 Analog Power Supply Filtering new recommendations e Section 16 DC Characteristics updated into include IDDOP values e Section 19 Maximum temperature changed from TC 85 C to TA 85 C Added Airflow versus Theta JA chart 5 January 1999 General update 4 September 1998 Genera
100. NI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x19 RLOP Interrupt Enable Interrupt Status Bit Type Function Default Bit 7 R W FEBEE 0 Bit 6 R W BIPEE Bit 5 R W LAISE LRDII The LRDII bit is the line far end receive failure interrupt status bit LRDII is set high when a change in the line RDI state occurs This bit is cleared when this register is read LAISI The LAISI bit is the line AIS interrupt status bit LAISI is set high when a change in the line AIS state occurs This bit is cleared when this register is read BIPEI The BIPEI bit is the line BIP interrupt status bit BIPEI is set high when a line layer B2 bit error is detected This bit is cleared when this register is read FEBEI The FEBEI bit is the line far end block error interrupt status bit FEBEI is set high when a line layer FEBE M1 is detected This bit is cleared when this register is read LRDIE The LRDIE bit is an interrupt enable for the line remote defect indication alarm When LRDIE is set to logic one an interrupt is generated when line RDI changes state LAISE The LAISE bit is an interrupt enable for line AIS When LAISE is set to logic one an interrupt is generated when line AIS changes state Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 89 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSU
101. ORK INTERFACE 155 QUAD Pin Name Type Pin Function No DTCA 4 Output K22 UTOPIA Direct Transmit Cell Available DTCA 4 1 EIC is These output signals provide direct status indication of when a cell is available in the transmit FIFO for DTOAL pel the corresponding port When high DTCA indicates that the corresponding transmit FIFO is not full and a complete cell may be written When DTCA goes low it can be configured to indicate either that the corresponding transmit FIFO is near full or that the corresponding transmit FIFO is full DTCA will transition low on the rising edge of TFCLK after the Payload word 19 TCALEVELO 0 or 23 TCALEVELO 1 is sampled if the PHY being polled is the same as the PHY in use To reduce FIFO latency the FIFO depth at which DTCA indicates full can be set to one two three or four cells Note that regardless of what fill level DTCA is set to indicate full at the transmit cell processor can store 4 complete cells DTCA 4 1 are updated on the rising edge of TFCLK RDAT 15 Output 023 UTOPIA Receive Cell Data Bus RDAT 15 0 RDAT 14 022 This data bus carries the cells that read ES from the receive FIFO selected by RADR A4 0 RDAT 11 V22 RDAT 15 0 is tri stated when RENB is high RDAT 10 W23 RDAT 15 0 is tristated when RENB is high RDAT 9 U20 RDAT 15 0 is also tristated when either the null RDAT 8 V21 PHY address 0x1F or an a
102. PMC Sierra Inc and for its Customers Internal Use 221 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 13 11 Initializing the S UNI QUAD The S UNI QUAD defaults to the Asynchronous Transfer Mode ATM operation but it is recommended to implement the following initialization sequence 1 Reset the device This can be done by asserting the RSTB pin or setting the RESET bit in the Master Reset and ID Register Register 00 2 Setthe TPOP Path Signal Label Register 0x48 to 0x13 which indicates an ATM payload For every channel reset all the Rx and Tx FIFO s by setting the FIFORST register bit in the TXCP and RXCP blocks Keep this bit set for at least 1 us then set the bit back to its inactive logic zero value 4 For every channel reset the performance monitoring counters in and RXCP blocks and preferably in all the blocks The easiest way to do this is to use the TIP register bit 13 12 Using the S UNI QUAD with a 5 Volt ODL The S UNI QUAD defaults to a 3 3V PECL optical data link ODL module interface It can also be used with a 5V ODL This is accomplished by setting to logic 1 the PECLV bit located in the Master Configuration Register Register 0x01 Notice that all four channels are reconfigured Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 222 F2 MC PMC
103. PSBFI The PSBFI bit is set high when the protection switching byte failure alarm is declared or removed This bit is cleared when the RASE Interrupt Status register is read Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 177 S UNI QUAD DATASHEET PMC 971239 ON AC scs MC PME Sera TR PM5349 S UNI QUAD ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register OxE2 RASE Configuration Control B Type Function Default B R W 41 51 CAP 0 B R W SFBERTEN Bit 5 R W SFSMODE Bit 4 R W SFCMODE Bit 3 R W SDBERTEN Bit 2 R W SDSMODE Bit 1 R W SDCMODE Bit 0 R W Unused it it 7 it 6 SDCMODE The SDCMODE alarm bit selects the RASE window size to use for clearing the SD alarm When SDCMODE is a logic zero the RASE clears the SD alarm using the same window size used for declaration When SDCMODE is a logic one the RASE clears the SD alarm using a window size that is 8 times longer than the alarm declaration window size The declaration window size is determined by the RASE SD Accumulation Period registers SDSMODE The SDSMODE bit selects the RASE saturation mode When SDSMODE is a logic zero the RASE limits the number of B2 errors accumulated in one frame period to the RASE SD Saturation Threshold register value When SDSMODE is a logic one the RASE limits the number of B2 errors accumulated in one window subtotal accumulation period to the RASE SD S
104. R 4 0 is sampled on the rising edge of RFCLK RCA Output N20 UTOPIA Receive multi PHY Cell Available RCA RCA indicates when a cell is available in the receive FIFO for the port selected by RADR 4 0 RCA can be configured to be de asserted when either zero or four bytes remain in the selected addressed FIFO RCA will thus transition low on the rising edge of RFCLK after Payload word 24 RCALEVELO 1 or 19 RCALEVELO 0 is output if the PHY being polled is the same as the PHY in use RCA is tristated when either the null PHY address 0x1F or an address not matching the address space is latched from the RADR 4 0 inputs when RENB is high RCA is updated on the rising edge of RFCLK RFCLK Input P21 UTOPIA Receive FIFO Read Clock RFCLK RFCLK is used to read ATM cells from the receive FIFO s RFCLK must cycle at a 50 MHz or lower instantaneous rate but at a high enough rate to avoid FIFO overflows Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 21 PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Pin Name Type Pin Function No DRCA 4 Output M21 UTOPIA Direct Receive Cell Available DRCA 4 1 DRCA 3 N23 DRCA 2 N22 DRCA 1 N21 These output signals provides direct status indication of when a cell is available in the receive FIFO for
105. R W Reserved Bit 2 R W Reserved Bit 1 R W DBIP8 Bit O R W Reserved This register allows insertion of path level alarms and diagnostic signals DBIP8 The DBIP8 bit controls the insertion of bit errors continuously in the byte When 8 is a logic one the byte is inverted PERSIST The path far end receive failure alarm persistence bit PERSIST controls the persistence of the RDI asserted into the transmit stream When PERSIST is a logic one the RDI code inserted into the transmit stream as a result of consequential actions is asserted for a minimum of 20 frames in non enhanced RDI mode or the last valid RDI code before an idle code idle codes are when bits 5 6 7 are 000 001 or 011 is asserted for 20 frames in enhanced RDI mode When PERSIST is logic zero the transmit RDI code changes immediately based on received alarm conditions EPRDISRC The enhanced path receive defect indication alarm source bit EPRDISRC controls the source of RDI input to be inserted onto the G1 byte When EPRDIEN is logic zero the extended RDI bits of the G1 byte not overwritten by the TPOP block regardless of EPRDISRC When EPRDIEN is logic one and EPRDISCR is logic zero the extended RDI bits of the G1 byte bits 6 and 7 are inserted according to the value in the G1 1 0 register bits register 0x49 When EPRDIEN is logic one and EPRDISCR is logic one the value register 0x49 G1 1 0 is ignored and
106. S UNI QUAD performs the mapping of ATM cells into the SONET SDH STS 3c STM 1 synchronous payload envelope SPE and processes applicable SONET SDH section line and path overhead In a typical STS 3c STM 1 ATM application the S UNI QUAD performs clock and data recovery for the receive direction and clock synthesis for the transmit direction of the line interface On the system side the S UNI QUAD interfaces directly with ATM layer processors and switching or adaptation functions using a Utopia Level 2 compliant synchronous FIFO style interface The initial configuration and ongoing control and monitoring of the S UNI QUAD are normally provided via a generic microprocessor interface This application is shown in Figure 1 Figure 1 Typical STS 3c STM 1 ATM Switch Port Application Utopia Level 2 ATM Layer Device Interface PM5349 S UNI 155 QUAD Optical Transceiver TxClk TFCLK TENB TADR 4 0 Optical Transceiver TPRTY TDAT 15 0 Optical Transceiver Optical Transceiver RxData lt 15 0 gt RDAT 15 0 Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 7 PM5349 S UNI QUAD SATURN USER NETWORK INTERFACE 155 QUAD P AC PMC Sierra Inc ISSUE 6 6 BLOCK DIAGRAM S UNI QUAD DATASHEET PMC 971239 INTB RCLK1 4 RFPO1 4 RALRM1 4 10SS 901d 019I W r y voua o silivau 10sseoojd 10ss8901d 108592024 105590024 v as AlHudH 189 WLY
107. SATURN USER NETWORK INTERFACE 155 QUAD Register 0x94 S UNI QUAD Channel Receive Line AIS Control Bit O R W Reserved LOSINS This bit is active only when the ALLONES bit in the RLOP Control Status register is set high it is ignored if the ALLONES bit is set low The LOSINS bit enables the insertion of line AIS in the receive direction upon the declaration of loss of signal LOS If LOSINS is a logic one line AIS is inserted into the SONET SDH frame when LOS is declared Line AIS is terminated when LOS is removed LOFINS This bit is active only when the ALLONES bit in the RLOP Control Status register is set high it is ignored if the ALLONES bit is set low The LOFINS bit enables the insertion of line AIS in the receive direction upon the declaration of loss of frame LOF If LOSINS is a logic one line AIS is inserted into the SONET SDH frame when LOS is declared Line AIS is terminated when LOS is removed SFINS This bit is active only when the ALLONES bit in the RLOP Control Status register is set high it is ignored if the ALLONES bit is set low The SFINS bit enables the insertion of line AIS in the receive direction upon the declaration of signal fail SF If SFINS is a logic one line AIS is inserted into the SONET SDH frame when SF is declared Line AIS is terminated when SF is removed SDINS This bit is active only when the ALLONES bit in the RLOP Control Status register is set high it is ignor
108. SD RXD and RXD inputs which operate at pseudo ECL PECL logic levels 2 The RDAT 7 0 RPRTY RSOC DRCA4 1 RCA DTCA4 1 TCA TCLK and RCLK1 4 outputs have a 4 mA DC drive capability The TDO output has a 1 mA drive capability All the other outputs have a 2 mA DC drive capability The TXD and TXD outputs are met to be terminated in a passive network and interface at PECL levels It is mandatory that every ground pin VSS be connected to the printed circuit board ground plane to ensure a reliable device operation 4 Itis mandatory that every power pin VDD be connected to the printed circuit board power plane to ensure a reliable device operation 5 All analog power and ground can be sensitive to noise They must be isolated from the digital power and ground Care must be taken to decouple these pins from each other and all other analog power and ground pins Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 30 S UNI QUAD DATASHEET PMC 971239 ON AC scs MC PME Sera TR PM5349 S UNI QUAD ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Power supply filtering recommendations are provided in the OPERATION section of this document Due to ESD protection structures in the pads it is necessary to exercise caution when powering a device up or down ESD protection devices behave as diodes between power supply pins and from I O pins to power supply pins Under extreme conditio
109. SER NETWORK INTERFACE 155 QUAD Register 0 RASE SF Accumulation Period Bit Function Default Bit7 RW SFSAP 7 0 Bite RW SFSAP 0 Bits RW SFSAPS 0 Bit4 RW SFSAP4jJ 0 Bits RW SFSAP 0 Bit2 RW SFSAP2 0 Bit 7 Bit 6 Bit 5 Bit4 R W SFSAP 12 Bit 3 Bit 2 Bit R W Bit 0 R W R W R W R W SFSAP 15 SFSAP 14 SFSAP 13 11 SFSAP 10 8 0 Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 180 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0 5 RASE SF Accumulation Period Bit Type Function Default Bit7 R W SFSAP 23 0 Bit6 R W SFSAP 22 5 R W SFSAP 21 Bit4 R W SFSAP 20 Bit3 R W SFSAP 19 Bit2 R W SFSAP 18 Bit R W SFSAPI17 BitO R W SFSAP 16 SFSAP 23 0 The SFSAP 23 0 bits represent the number of 8 KHz frames used to accumulate the B2 error subtotal The total evaluation window to declare the SF alarm is broken into 8 subtotals so this register value represents 1 8 of the total sliding window size Refer to the Operations section for recommended settings Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 181 S UNI QUAD DATASHEET
110. Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 14 FUNCTIONALTIMING All functional timing diagrams assume that polarity control is not being applied to input and output data and clock lines i e polarity control bits in the S UNI QUAD registers are set to their default states 14 1 ATM Utopia Level 2 System Interface Figure 22 Multi PHY Polling and Addressing Transmit Cell Interface sp ptm pp Sr es Tom es es TCA cats p onc XX feste SM cna RX ERY SE Re RATER X BEA TENG et Figure 66 is an example of the multi PHY polling and selection sequence supported by the S UNI QUAD A B and C represent any arbitrary address values of PHY devices which may be occupied by the S UNI QUAD The ATM Layer device is not restricted in its polling order The PHY associated with address A indicates it cannot accept a cell but PHY B indicates it is willing to accept a cell As a result the ATM Layer places address B on TADR 4 0 the cycle before TENB is asserted to select PHY B as the next cell destination In this example the PHY C status is ignored The ATM Layer device is not constrained to select the latest PHY polled As soon as the cell transfer is started the polling process may be restarted Proprietary and Confidential to PMC Sierra Inc and for its Cust
111. Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD EXTD The EXTD bit extends the registers to facilitate additional mapping If this bit is set to logic one the register mapping for registers 0x30 0x31 and 0x33 are extended Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 115 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x37 RPOP Path Signal Label DDD DDD J PSL 7 0 The PSL 7 0 bits contain the path signal label byte C2 The value in this register is updated to a new path signal label value if the same new value is observed for three or five consecutive frames depending on the status of the PSL5 bit Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 116 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x38 RPOP Path BIP 8 LSB Bit Type Function Default Bi7 R xX Bite R X Bits R X ee X Bits R X Bt2 PBE2 X Biti R Bito X Register 0x39 RPOP Path BIP 8 MSB D R DDD Bit Type Function
112. TDI Control Select Access Port Controller Tri state Enable Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 212 S UNI QUAD ron Aa MC BME siete ING 5349 S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD The boundary scan architecture consists of a TAP controller an instruction register with instruction decode a bypass register a device identification register and a boundary scan register The TAP controller interprets the TMS input and generates control signals to load the instruction and data registers The instruction register with instruction decode block is used to select the test to be executed and or the register to be accessed The bypass register offers a single bit delay from primary input TDI to primary output TDO The device identification register contains the device identification code The boundary scan register allows testing of board inter connectivity The boundary scan register consists of a shift register place in series with device inputs and outputs Using the boundary scan register all digital inputs can be sampled and shifted out on primary output TDO In addition patterns can be shifted in on primary input TDI and forced onto all digital outputs 13 6 1 TAP Controller The TAP controller is a synchronous finite state machine clocked by the rising edge of primary input TCK All state transitions are
113. TERFACE 155 QUAD Register 0x69 RXCP Corrected HCS Error Count Bit Type Function Default Bt7 R X Bite R CHCS6 X Bits R CHCSS X Bt4 R xX Bits CHCSS X Bt2 R CHOS x Bt R X Bit 0 CHCSIO CHCS 7 0 The CHCS 7 0 bits indicate the number of corrected HCS error events that occurred during the last accumulation interval The contents of these registers are valid a maximum of 40 RCLK periods after a transfer is triggered by a write to one of RXCP s performance monitor counters or to the S UNI QUAD Channel Reset and Monitoring Update register Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 145 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x6A RXCP Uncorrected HCS Error Count Bit Type Function Default Bt7 R X Bite R UHCS6 X Bits R UHCSS X Bt4 R UHCS4 X Bits UHCSS X Bt2 R UHCS2 X Bt X Bit 0 UHCSIO UHCS 7 0 The UHCS 7 0 bits indicate the number of uncorrectable HCS error events that occurred during the last accumulation interval The contents of these registers are valid a maximum of 40 RCLK periods after a transfer is triggered by a write to one of RXCP s performance monitor
114. TURN USER NETWORK INTERFACE 155 QUAD TFPO Output AB11 The Transmit Frame Pulse Output TFPO pulses high for one TCLK cycle every 2430 e cycles and provides an 8 KHz timing reference TFPO can be assigned to any of the four channels using TFPO CH 1 0 configuration register bits with the restriction that the selected channel must be self timed not in loop timed or line loopback modes TFPO is updated on the rising edge of TCLK 9 2 UTOPIA Level 2 System Interface Pin Name Type Pin Function No TDAT 15 Input A20 UTOPIA Transmit Cell Data Bus TDAT 15 0 E This data bus carries the ATM cell octets that are written to the selected transmit FIFO TDAT 15 0 is DAN e considered valid only when TENB is simultaneously TDAT 10 C20 asserted and the S UNI QUAD is selected via TDAT 9 D21 TDAT 8 E20 TDAT 15 0 is sampled on the rising edge of TFCLK TDAT 7 C23 TDAT 6 D22 TDAT 5 E21 TDAT 4 D23 TDAT 3 E22 TDAT 2 F21 TDATT 1 G20 TDAT O E23 Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 15 S UNI QUAD DATASHEET PMC 971239 PMC Serta ING PM5349 S UNI QUAD ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Pin Name Type Pin No Function TPRTY Input H22 UTOPIA Transmit bus parity TPRTY signal The transmit parity TPRTY signal indicates the parity of the TDAT
115. TWORK INTERFACE 155 QUAD RXPTYP is set to logic zero RPRTY is the odd parity bit for outputs RDAT 15 0 Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 137 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x63 RXCP Interrupt Enables and Counter Status Bit Function Default BitO RW LCDE 0 LCDE The LCDE bit enables the generation of an interrupt due to a change in the LCD state When LCDE is set to logic one the interrupt is enabled FOVRE The FOVRE bit enables the generation of an interrupt due to a FIFO overrun error condition When FOVRE is set to logic one the interrupt is enabled HCSE The HCSE bit enables the generation of an interrupt due to the detection of a corrected or an uncorrected HCS error When HCSE is set to logic one the interrupt is enabled OOCDE The OOCDE bit enables the generation of an interrupt due to a change in cell delineation state When OOCDE is set to logic one the interrupt is enabled XFERE The XFERE bit enables the generation of an interrupt when an accumulation interval is completed and new values are stored in the RXCP Count registers When XFERE is set to logic one the interrupt is enabled OVR The OVR bit is the overrun status of the RXCP Performance Monitoring Count registers A logic one in this bit position in
116. The LRDI signal is optionally reported on the RALRM output pin when enabled by the LRDIEN Receive Alarm Control Register bit 10 3 2 Line AIS Detect The Line AIS Block detects the presence of a Line Alarm Indication Signal LAIS in the receive stream Line AIS is declared when a 111 binary pattern is detected in bits 6 7 and 8 of the K2 byte for three or five consecutive frames Line AIS is removed when any pattern other than 111 is detected in bits 6 7 and 8 of the K2 byte for three or five consecutive frames The LAIS signal is optionally reported on the RALRM output pin when enabled by the LAISEN Receive Alarm Control Register bit 10 3 3 Error Monitor Block The Error Monitor Block calculates the received line BIP 8 error detection codes based on the Line Overhead bytes and synchronous payload envelopes of the STS 3c STM 1 stream The line BIP 8 code is a bit interleaved parity calculation using even parity Details are provided in the references The calculated BIP 8 Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 35 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD codes are compared with the BIP 8 codes extracted from the following frame Any differences indicate that a line layer bit error has occurred Optionally the RLOP can be configured to count a maximum of only one BIP error per frame
117. a new synchronization status message is extracted into the Receive Z1 S1 register COAPSE The COAPS interrupt enable is an interrupt mask for changes in the received APS code When COAPSE is a logic one an interrupt is generated when a new K1 K2 code value is extracted into the RASE Receive K1 and RASE Receive K2 registers PSBFE The PSBF interrupt enable is an interrupt mask for protection switch byte failure alarms When PSBFE is a logic one an interrupt is generated when PSBF is declared or removed Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 175 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register OxE1 RASE Interrupt Status Bit 4 SFBERI PSBFV The PSBFV bit indicates the protection switching byte failure alarm state The alarm is declared PSBFV is set high when twelve successive frames have been received without three consecutive frames containing identical K1 bytes The alarm is removed PSBFV is set low when three consecutive frames containing identical K1 bytes have been received SDBERV The SDBERV bit indicates the signal degrade threshold crossing alarm state The alarm is declared SDBERV is set high when the bit error rate exceeds the threshold programmed in the RASE SD Declaring Threshold registers The alarm is removed SDBERV is set low when the bit e
118. a the JTAG test port Table 6 Test Mode Register Memory Map Address Register 0x000 0x3FF Normal Mode Registers 0x400 Master Test Register 0x401 0x7FF Reserved For Test 12 1 Master Test Register Notes on Test Mode Register Bits 1 Writing values into unused register bits has no effect However to ensure software compatibility with future feature enhanced versions of the product unused register bits must be written with logic zero Reading back unused bits can produce either a logic one or a logic zero hence unused register bits should be masked off by software when read 2 Writable test mode register bits are not initialized upon reset unless otherwise noted Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 193 S UNI QUAD DATASHEET PMC 971239 F2 MC PMC Serta ING PM5349 S UNI QUAD ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x400 Master Test Bit Type Function Default Bit 7 Unused X Bit 6 W Reserved X Bit 5 W PMCATST X Bit 4 W PMCTST X Bit 3 W DBCTRL 0 Bit 2 R W IOTST 0 Bit 1 W HIZDATA 0 Bit 0 R W HIZIO 0 This register is used to enable S UNI QUAD test features All bits except PMCTST PMCATST and BYPASS are reset to zero by a reset of the S UNI QUAD using either the RSTB input or the Master Reset register PMCTST and BYPASS are reset when CSB is logic one PMCATST is reset
119. able H4INSB determines the contents of the H4 byte in the outgoing path overhead If HAINSB is set to logic one the H4 byte is set to the value of 00 hexadecimal If HAINSB is set to logic zero the H4 byte is set to the cell indicator offset value XFERI The XFERI bit indicates that a transfer of Transmit Cell Count data has occurred A logic one in this bit position indicates that the Transmit Cell Count registers have been updated This update is initiated by writing to one of the Transmit Cell Count register locations or to the S UNI QUAD Identification Master Reset and Global Monitor Update register XFERI is set to logic zero when this register is read OVR The OVR bit is the overrun status of the Transmit Cell Count registers A logic one in this bit position indicates that a previous transfer indicated by XFERI being logic one has not been acknowledged before the next accumulation interval has occurred and that the contents of the Transmit Cell Count registers have been overwritten OVR is set to logic zero when this register is read XFERE The XFERE bit enables the generation of an interrupt when an accumulation interval is completed and new values are stored in the Transmit Cell Count registers When XFERE is set to logic one the interrupt is enabled Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 155 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET
120. abled when the event occurs bit 6 of the G1 byte is set low while bit 7 of the G1 byte is set high NOLOPEPRDI has precedence over PSLMERDI and UNEQERDI When NOLOPEPRDI is set low reporting of enhanced RDI is according to PSLMERDI and UNEQERDI and the associated alarm states PSLMEPRDI When set high the PSLMEPRDI bit enables enhanced path RDI assertion when path signal label mismatch PSLM events are detected in the receive Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 167 F2 MC PMC Serta ING PM5349 S UNI QUAD PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD S UNI QUAD DATASHEET stream If enabled when the event occurs bit 6 of the G1 byte is set high while bit 7 of the G1 byte is set low When PSLMEPRDI is set low path signal label mismatch events have no effect on path RDI In addition this bit has no effect when EPRDI EN is set low NOPAISEPRDI When set high the NOPAISEPRDI bit disables enhanced path RDI assertion when the path alarm indication signal state PAIS is detected in the receive stream If enabled when the event occurs bit 6 of the G1 byte is set low while bit 7 of the G1 byte is set high NOPAISEPRDI has precedence over PSLMERDI and UNEQERDI When NOPAISEPRDI is set low reporting of enhanced RDI is according to PSLMERDI and UNEQERDI and the associated alarm states NOALMEPRDI When set high the NOALMEPRDI bit disab
121. acted from the B2 byte s of the following frame Any differences indicate that a line layer bit error has occurred Up to 192000 24 BIP frame x 8000 frames second bit errors can be detected per second for STS 3c STM 1 rate The BERM accumulates these line layer bit errors in a 20 bit saturating counter that can be read via the microprocessor interface During a read the counter value is latched and the counter is reset to 0 or 1 if there is an outstanding event Note this counter should be polled at least once per second to avoid saturation which in turn may result in missed bit error events The BERM block is able to simultaneously monitor for signal fail SF or signal degrade SD threshold crossing and provide alarms through software interrupts The bit error rates associated with the SF or SD alarms are programmable over a range of 10 3 to 109 Details are provided in the Operations section In both declaring and clearing detection states the accumulated BIP count is continuously compared against the threshold This allows to rapidly declare in the presence of error bursts or error rates that significantly exceed the monitored BER This behavior allows meeting the ITU T G 783 detection requirements at various error rates where the detection time is a function of the actual BER fora given monitored BER 10 4 3 Synchronization Status Extraction The Synchronization Status Extraction SSE Block extracts the synchronization status
122. alarm condition When LOPPRDI is set to logic one the transmit line RDI will be inserted When LOPPRDI is set to logic zero no action is taken This register bit has effect only if the AUTOPRDI register bit is also set to logic one PAISPRDI The Path Alarm Indication Signal PRDI PAISPRDI controls the insertion of a Path RDI in the transmit data stream upon detection of this alarm condition When PAISPRDI is set to logic one the transmit line RDI will be inserted When PAISPRDI is set to logic zero no action is taken This register bit has effect only if the AUTOPRDI register bit is also set to logic one Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 165 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD ALRMPRDI The Line Alarm Indication Signal PRDI ALRMPRDI controls the insertion of a Path RDI in the transmit data stream upon detection of one of the following alarm conditions Loss of Signal LOS Loss of Frame LOF and Line Alarm Indication Signal LAIS When ALRMPRDI is set to logic one the transmit line RDI will be inserted When ALRMPRDI is set to logic zero no action is taken This register bit has effect only if the AUTOPRDI register bit is also set to logic one LCDPRDI The Loss of ATM Cell Delineation Signal LCDPRDI controls the insertion of Path RDI in the transmit data stre
123. alculation over the first 4 octets of the ATM cell header When performing delineation correct HCS calculations are assumed to indicate cell boundaries Cells are assumed to be byte aligned to the synchronous payload envelope The cell delineation algorithm searches the 53 possible cell boundary candidates individually to determine the valid cell boundary location While searching for the cell boundary location the cell delineation circuit is in the HUNT state When a correct HCS is found the cell delineation state machine locks on the particular cell boundary corresponding to the correct HCS and enters the PRESYNC state The PRESYNC state validates the cell boundary location If the cell boundary is invalid an incorrect HCS will be received within the next DELTA cells at which time a transition back to the HUNT state is executed If no HCS errors are detected in this PRESYNC period the SYNC state is entered While in the SYNC state synchronization is maintained until ALPHA consecutive incorrect HCS patterns are detected In such an event a transition is made back to the HUNT state The state diagram of the delineation process is shown in Figure 4 Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 43 MC PMC Serta ING PM5349 S UNI QUAD PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD S UNI QUAD DATASHEET Figure 4 Cell Delineation State Diagram correct HCS byte
124. am upon detection of this alarm When LCDPRDI is set to logic zero no action is taken This register bit is used only if the AUTOPRDI register bit is also set to logic one Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 166 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x92 S UNI QUAD Channel Auto Enhanced Path RDI Control Bit O R W Reserved This register and the S UNI QUAD Channel Auto Path RDI Control register controls the auto assertion of enhanced path RDI G1 bits 5 6 7 in the local TPOP Since the S UNI QUAD provides a STS 3c STM 1 mapping this register with its companion register controls auto enhanced path RDI assertion on the entire transmit stream NOLOPCONEPRDI When set high the NOLOPCONEPRDI bit disables enhanced path RDI assertion when loss of pointer concatenation LOPCON events are detected in the receive stream If enabled when the event occurs bit 6 of the G1 byte is set low while bit 7 of the G1 byte is set high NOLOPCONEPRDI has precedence over PSLMERDI and UNEQERDI When NOLOPCONEPRDI is set low reporting of enhanced RDI is according to PSLMERDI and UNEQERDI and the associated alarm states NOLOPEPRDI When set high the NOLOPEPRDI bit disables enhanced path RDI assertion when loss of pointer LOP events are detected in the receive stream If en
125. anteed to be sent When FTPTR is a logic zero the pointer value in the Current Pointer registers is inserted in the transmit stream Reserved The reserved bits must be programmed to logic zero for proper operation Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 125 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x43 TPOP Current Pointer LSB DO DDD J CPTR 7 0 The CPTR 7 0 bits along with the CPTR 9 8 bits in the TPOP Current Pointer MSB Register reflect the value of the current payload pointer being inserted in the transmit stream The value may be changed by loading a new pointer value using the TPOP Arbitrary Pointer LSB and MSB Registers or by inserting positive and negative pointer movements using the PSE and NSE register bits Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 126 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x44 TPOP Current Pointer MSB CPTR 9 8 The CPTR 9 8 bits along with the CPTR 7 0 bits in the TPOP Current Pointer LSB Register reflect the value of the current payload pointer being inserted in the transmit stream The value may be changed by loading a new pointer
126. arried out in a manner that ensures that coincident events are not lost 2 SBEI8 The count can also be polled by writing to the Master Reset and Identity Load Performance Meters register 0x05 Writing to register 0x05 simultaneously loads all the performance meter registers in the RSOP RLOP RPOP RXCP and TXCP blocks Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 84 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x14 TSOP Control Bit Type Function Default Bit 7 Unused X Bit 6 R W DS Bit 5 R W Reserved Bit 4 R W Reserved Bit 3 R W Reserved Bit 2 R W Reserved Bit 1 R W Reserved Bit 0 R W LAIS LAIS The LAIS bit controls the insertion of line alarm indication signal AIS When LAIS is set to logic one the TSOP inserts AIS into the transmit SONET SDH stream Activation or deactivation of line AIS insertion is synchronized to frame boundaries Line AIS insertion results in all bits of the SONET SDH frame being set to one prior to scrambling except for the section overhead DS The DS bit is set to logic one to disable the scrambling of the STS 3c STM 1 stream When DS is a logic zero scrambling is enabled Reserved The reserved bits must be programmed to logic zero for proper operation Proprietary and Confidential to PMC Sierra Inc
127. ast accumulation interval The counter should be polled every second to avoid saturation The contents of these registers are valid a maximum of 67 RCLK periods after a transfer is triggered by a write to one of RXCP s performance monitor counters or to the S UNI QUAD s Channel Reset and Monitoring Update register Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 150 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x80 TXCP Configuration 1 Type Function Default R W TPTYP Bit 6 R W TCALEVELO Bit 5 R W Reserved Bit 4 R W Reserved Bit 3 R W HCSB Bit 2 R W HCSADD Bit 1 R W DSCR Bit 0 R W FIFORST FIFORST The FIFORST bit is used to reset the four cell transmit FIFO When FIFORST is set to logic zero the FIFO operates normally When FIFORST is set to logic one the FIFO is immediately emptied and ignores writes The FIFO remains empty and continues to ignore writes until a logic zero is written to FIFORST Null unassigned cells are transmitted until a subsequent cell is written to the FIFO DSCR The DSCR bit controls the scrambling of the cell payload When DSCR is a logic one cell payload scrambling is disabled When DSCR is a logic zero payload scrambling is enabled HCSADD The HCSADD bit controls the addition of the coset polynomial x6 x4 x2 1 to the HCS
128. at when not being used CSB must be tied high If CSB is not required i e registers accesses are controlled using the RDB and WRB signals only CSB must be connected to an inverted version of the RSTB input Input The active low read enable RDB signal is low during S UNI QUAD register read accesses The S UNI QUAD drives the D 7 0 bus with the contents of the addressed register while RDB and CSB are low The active low write strobe WRB signal is low during a S UNI QUAD register write accesses The D 7 0 bus contents are clocked into the addressed register on the rising WRB edge while CSB is low D 0 D16 The bi directional data bus D 7 0 is used during D 1 B17 S UNI QUAD register read and write accesses D 2 A17 D 3 C16 D 4 B16 D 5 C15 D 6 B15 D 7 D14 A 0 Input A15 The address bus A 9 0 selects specific registers A 1 C14 during S UNI QUAD register accesses 45 2 for S UNI QUAD global registers the A 9 8 AH D13 bits allow to select which channel is being 5 C13 accessed The A 7 0 bits allow to select which B13 register is being access within a given channel A13 address space A 8 C12 A 9 B12 Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 23 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Pin Name i
129. atenation path AIS PLOPV The PLOPV bit is read to determine the loss of pointer state When PLOPV is a logic one the S UNI QUAD has declared LOP LOPCONV The LOPCONYV bit is read to determine the loss of pointer concatenation state When LOPCONV is a logic one the S UNI QUAD has declared loss of pointer concatenation Reserved The reserved bits must be programmed to logic zero for proper operation Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 101 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x30 EXTD 1 RPOP Status Control Bit Type Function Default Bit 7 R W Reserved 0 Bit 6 R W IINVCNT Bit 5 R W PSL5 R Bit 0 ERDIV 0 NOTE To facilitate additional register mapping shadow registers have been added to registers 0x30 0x31 and 0x33 These shadow registers are accessed in the same way as the normal registers The EXTD extend register bit must be set in register 0x36 to allow switching between accessing the normal registers and the shadow registers The Status Register is provided at RPOP read address 0 if the extend register EXTD bit is set in register 0x36 ERDIV 2 0 The ERDIV 2 0 bits reflect the current state of the detected enhanced RDI filtered G1 bits 5 6 and 7 IINVONT When a logic one is written to the IINVCNT Intuitive Invalid Poin
130. ation Saturation capabilities are provided to allow the user to address issues associated with error bursts Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 205 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Table 12 Recommended BERM settings F SD SF SD SF SD SAP DTH CTH 0x S 0 000064 0x084 0x08E Ox0003E8 0x085 0 08 0 002710 0x085 0x014438 0x06D 0x077 0x055 0x061 It is important to notice that the Table 12 was designed around the Bellcore GR 253 specification Please refer to the SONET SDH SDH Bit error Threshold Monitoring application note for more details as well as a recommended programming meeting the ITU G 783 specification 13 4 Clocking Options The S UNI QUAD supports several clocking modes Figure 13 is an abstraction of the clocking topology Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 206 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Figure 13 Conceptual Clocking Structure Conceptual Clocking Structure REFCLK Internal LL Tx Clock Clock Synthesizer Source Mode A Source timed Internal Rx Clock Ee SN RXD Clock Recovery EN Mode B Internally
131. aturation Threshold register value Note that the number of frames in a window subtotal accumulation period is determined by the RASE SD Accumulation Period register value SDBERTEN The SDBERTEN bit selects automatic monitoring of line bit error rate threshold events by the RASE When SDBERTEN is a logic one the RASE continuously monitors line BIP errors over a period defined in the RASE configuration registers When SDBERTEN is a logic zero the RASE BIP accumulation logic is disabled and the RASE logic is reset to the declaration monitoring state All RASE accumulation period and threshold registers should be set up before SDBERTEN is written Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 178 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD SFCMODE The SFCMODE alarm bit selects the RASE window size to use for clearing the SF alarm When SFCMODE is a logic zero the RASE clears the SF alarm using the same window size used for declaration When SFCMODE is a logic one the RASE clears the SF alarm using a window size that is 8 times longer than the alarm declaration window size The declaration window size is determined by the RASE SF Accumulation Period registers SFSMODE The SFSMODE bit selects the RASE saturation mode When SFSMODE is a logic zero the RASE limits the number of B2 errors accumulate
132. bit counter to 1 or 0 The counter reset value is dependent on if there was a count event during the transfer of the count to the Transmit Cell Counter registers The counter should be polled every second to avoid saturating The contents of these registers are valid after a maximum of 5 us after a transfer is triggered by a write to a TXCP_50 Transmit Cell count Register or the S UNI QUAD Channel Reset and Monitoring Update register Register 0x05 Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 162 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x90 S UNI QUAD Channel Auto Line RDI Control Bit Type Function Default Bit 7 R W SDLRDI 0 Bit 6 R W SFLRDI Bit 5 R W LOFLRDI Bit 4 R W LOSLRDI Bit 3 R W Reserved Bit 2 R W Reserved Bit 1 R W LAISLRDI Bit O Unused This register controls the auto assertion of line RDI in the local TLOP Since the S UNI QUAD provides STS 3c STM 1 AU4 mappings this register controls the assertion of line RDI for the entire SONET SDH stream LAISLRDI The Line Alarm Indication Signal LRDI LAISLRDI controls the insertion of a Line RDI in the transmit data stream upon detection of this alarm condition When LAISLRDI is set to logic one the transmit line RDI will be inserted When LAISLRDI is set to logic zero no action is taken This register bi
133. ble status RCA and DRCA 4 1 when data is read from the receive FIFO using the rising edges of RFCLK The RCA DRCA x status changes from available to unavailable when the FIFO is either empty RCALEVELO 1 or near empty RCALEVELO is logic zero This interface also indicates FIFO overruns via a maskable interrupt and register bits Read accesses while RCA or DRCA x is a logic zero will output invalid data The FIFO is reset on FIFO overrun causing up to 4 cells to be lost 10 12 2 Transmit ATM Interface The ATM Transmit FIFO TXCP provides FIFO management at the S UNI QUAD transmit cell interface The transmit FIFO contains four cells The FIFO depth may be programmed to four three two or one cells The FIFO provides the cell Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 51 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD rate decoupling function between the transmission system physical layer and the ATM layer In general the management functions include emptying cells from the transmit FIFO indicating when the transmit FIFO is full maintaining the transmit FIFO read and write pointers and detecting a FIFO overrun condition The FIFO interface is UTOPIA Level 2 compliant and accepts a write clock TFCLK a write enable signal TENB the start of a cell TSOC indication the
134. cated inputs Table 7 Test Mode 0 Read Locations Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 08H OFH Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 195 PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 8BH 8CH The following inputs cannot be read using the IOTST feature D 7 0 A 7 0 ALE CSB WRB RDB RSTB TRSTB TMS TCK and TDI Writing the following address locations forces the outputs to the value in the corresponding bit position zeros should be written to all unused test register locations Table 8 Test Mode 0 Write Locations Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 06H 8BH 8CH 90H The following outputs can not be controlled using the IOTST feature D 7 0 and TDO 1 INT corresponds to output INTB INTB is an open drain output and should be pulled high for proper operation Writing a logic one to the INT bit allows the S UNI QUAD to drive INTB low Writing a logic zero to the INT bit tristates the INTB output 12 3 JTAG Test Port The S UNI QUAD JTAG Test Access Port TAP allows access to the TAP controller and the 4 TAP registers instruction bypass
135. ce of the interrupt CHNLAI The CHNLAI bit is high when an interrupt request is active from the channel 4 The Channel 4 Interrupt Status register should be read to identify the source of the interrupt Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 66 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD CSUI The CSUI bit is high when an interrupt request is active from the Clock Synthesis and PISO block CSPI Clock Synthesis Unit The CSUI interrupt sources are enabled in the Clock Synthesis Interrupt Control Status Register Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 67 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x05 S UNI QUAD Channel Reset and Monitoring Update Bit Type Function Default Bit 7 R W CHRESET 0 Bit 6 Unused Bit 5 Unused This register provides software reset capability on a per channel basis It also loads by writing this register without setting the CHRESET bit all the error counters in the RSOP RLOP RPOP RXCP and TXCP blocks TIP The TIP bit is set to a logic one when any value with the CHRESET bit set to logic zero is written to this register Such a write initiates an accumulation interval transfer
136. controlled using primary input TMS The finite state machine is described below Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 213 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Figure 18 TAP Controller Finite State Machine TRSTB 0 dp Test Logic Reset 1 0 1 1 Run Test Idle Select DR Scan Select IR Scan 0 0 0 1 Capture IR 0 Shift IR 1 1 Exit1 IR Pause IR Exit2 IR Update DR Update IR All transitions dependent on input TMS Proprietary and Confidential to PMC Sierra Inc for its Customers Internal Use 214 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 13 6 1 1 States Test Logic Reset The test logic reset state is used to disable the TAP logic when the device is in normal mode operation The state is entered asynchronously by asserting input TRSTB The state is entered synchronously regardless of the current TAP controller state by forcing input TMS high for 5 TCK clock cycles While in this state the instruction register is set to the IDCODE instruction Run Test Idle The run test idle state is used to execute tests Capture DR The capture data register state is used to load parallel data into the test data registers selected by the
137. crambling under register control for diagnostic purposes 10 9 Transmit Line Overhead Processor TLOP The Transmit Line Overhead Processor TLOP provides line level alarm signal insertion and line BIP 24 insertion B2 10 9 1 APS Insert The APS Insert Block inserts the two automatic protection switch APS channel bytes in the Line Overhead K1 and K2 into the transmit stream when enabled by an internal register 10 9 2 Line BIP Calculate The Line BIP Calculate Block calculates the line BIP 24 error detection code B2 based on the line overhead and synchronous payload envelope of the transmit stream The line BIP 24 code is a bit interleaved parity calculation using even parity Details are provided in the references The calculated BIP 24 code is inserted into the B2 byte positions of the following frame BIP 24 errors may be continuously inserted under register control for diagnostic purposes 10 9 3 Line RDI Insert The Line RDI Insert Block controls the insertion of line remote defect indication Line RDI insertion is enabled using the TLRDI input or register control Line RDI is inserted by transmitting the code 110 binary in bit positions 6 7 and 8 of the K2 byte contained in the transmit stream Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 48 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUA
138. d in one frame period to the RASE SF Saturation Threshold register value When SFSMODE is a logic one the RASE limits the number of B2 errors accumulated in one window subtotal accumulation period to the RASE SF Saturation Threshold register value Note that the number of frames in a window subtotal accumulation period is determined by the RASE SF Accumulation Period register value SFBERTEN The SFBERTEN bit enables automatic monitoring of line bit error rate threshold events by the RASE When SFBERTEN is a logic one the RASE continuously monitors line BIP errors over a period defined in the RASE configuration registers When SFBERTEN is a logic zero the RASE BIP accumulation logic is disabled and the RASE logic is reset to the declaration monitoring state All RASE accumulation period and threshold registers should be set up before SFBERTEN is written Z1 S1 CAP The 21 51 CAP bit enables the 21 51 Capture algorithm When 21 51 CAP is a logic one the 21 51 clock synchronization status message nibble must have the same value for eight consecutive frames before writing the new value into the RASE Receive 21 51 register When Z1 S1 is logic zero the Z1 S1 nibble value is written directly into the RASE Receive Z1 S1 register Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 179 S UNI QUAD DATASHEET PMC 971239 di PMC Sierra Inc PM5349 S UNI QUAD ISSUE 6 SATURN U
139. ddress not matching RDAT 7 W22 the address space is latched from the RADR 4 0 RDAT 6 Y23 inputs when RENB is high RDAT S W21 RDAT 15 0 is updated on the rising edge of RDAT 4 Y22 RFCLK RDAT 3 AA23 RDAT 2 W20 RDAT 1 Y21 RDAT 0 AA20 Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 19 S UNI QUAD DATASHEET PMC 971239 NAC scs MC PME Sera TR PM5349 S UNI QUAD ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Pin Name Type Pin Function No RPRTY Output T21 UTOPIA Receive Parity RPRTY The receive parity RPRTY signal indicates the parity of the RDAT bus RPRTY reflects the parity of RDAT 15 0 Odd or even parity selection is made independently for every channel by using the RXPTYP register bit in ATM cell processors the four RXCP shall be programmed with the same parity setting RPRTY is tristated when RENB is high RPRTY is also tristated when either the null PHY address 0x1F or an address not matching the address space is latched from the RADR 4 0 inputs when RENB is high RPRTY is updated on the rising edge of RFCLK RSOC Output P23 UTOPIA Receive Start of Cell RSOC RSOC marks the start of cell on the RDAT bus RSOC is tristated when RENB is deasserted RSOC is also tristated when either the null PHY address 0x1F or an address not matching the address space is latched from the RADR 4 0 inputs when REN
140. dicates that a previous transfer indicated by XFERI being logic one has not been acknowledged before the next accumulation interval has occurred and that the contents of the RXCP Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 138 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Count registers have been overwritten OVR is set to logic zero when this register is read XFERI The XFERI bit indicates that a transfer of RXCP Performance Monitoring Count data has occurred A logic one in this bit position indicates that the RXCP Count registers have been updated This update is initiated by writing to one of the RXCP Count register locations or to the S UNI QUAD Identification Master Reset and Global Monitor Update register XFERI is set to logic zero when this register is read Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 139 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x64 RXCP Status Interrupt Status Function Default LCDI The LCDI bit is set high when there is a change in the loss of cell delineation LCD state This bit is reset immediately after a read to this register FOVRI The FOVRI bit is set to logic one when a FIFO overrun occurs Thi
141. e SPE The entire SPE is used for ATM cells Figure 10 ATM Mapping into the STS 3c STM 1 SPE 270 bytes 9 261 bytes bytes Section Overhead ATM Cell Regen Section NL byt ATM Cell vies Line Overhead Section ATM cel Section ATM Cell Cell STS 3c Transport Overhead STM 1 Section Overhead CONN Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 201 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 13 1 2 Transport and Path Overhead Bytes Under normal operating conditions the S UNI QUAD processes a subset of the complete transport overhead present in an STS 3c STM 1 stream The byte positions processed by the S UNI QUAD are indicated in Figure 11 Figure 11 STS 3c STM 1 Overhead TRANSPORT OVERHEAD PATH OVERHEAD SOH POH Transport Overhead Bytes A1 A2 The frame alignment bytes A1 A2 locate the SONET SDH frame in the STS 3c STM 1 serial stream Z0 The ZO bytes are currently defined as the STS 3c STM 1 section growth bytes for SONET SDH ZO bytes are not scrambled by the frame synchronous scrambler B1 The section bit interleaved parity byte provides a section error monitoring function Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 202 S UNI QUAD DATASHEET
142. e TADR 4 0 inputs to initiate writes to the transmit FIFO s TENB works as follows When sampled high no write is performed but the TADR 4 0 address is latched to identify the transmit FIFO to be accessed When TENB is sampled low the word on the TDAT bus is written into the transmit FIFO that is selected by the TADR 4 0 address bus A complete 53 octet cell must be written to the transmit FIFO before it is inserted into the transmit stream Idle cells are inserted when a complete cell is not available While TENB is deasserted TADR 4 0 can be used for polling TCA TENB is sampled on the rising edge of TFCLK TADRI4 TADR 3 TADR 2 TADR 1 TADR O Input G21 H20 G22 H21 G23 UTOPIA Transmit Write Address TADR 4 0 signals The TADR 4 0 bus is used to select the FIFO and hence port that is written to using the TENB signal and the FIFO s whose cell available signal is visible on the TCA polling output Note that address Ox1F is the null PHY address and cannot be assigned to any port on the S UNI QUAD TADR 4 0 is sampled on the rising edge of TFCLK Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 17 NAC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Pin Name Type Pin Function No TCA Output J23 UTOPIA Transmit multi PHY Cell Available TCA The T
143. e a common exception Certain register bits are reserved These bits are associated with megacell functions that are unused in this application To ensure that the S UNI QUAD operates as intended reserved register bits must be written with their default value as indicated by the register bit description Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 59 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x00 S UNI QUAD Master Reset and Identity Bit Type Function Default Bit 7 R W RESET 0 Bt6 R TYPE 3 Bit 5 TYPE 2 This register allows the revision of the S UNI QUAD to be read by software permitting graceful migration to support newer feature enhanced versions of the S UNI QUAD It also provides software reset capability In addition writing to this register simultaneously loads all the performance meter registers in the RSOP RLOP RPOP RXCP and TXCP blocks ID 2 0 The ID bits can be read to provide a binary S UNI QUAD revision number 3 0 The TYPE bits distinguish the S UNI QUAD from the other members of the S UNI family of devices RESET The RESET bit allows the S UNI QUAD to be reset under software control If the RESET bit is a logic one the entire S UNI QUAD is held in reset This bit is not self clearing Therefore a logic zero must be written to
144. e additional register mapping shadow registers have been added to registers 0x30 0x31 and 0x33 These shadow registers are accessed in the same way as the normal registers The EXTD extend register bit must be set in register 0x36 to allow switching between accessing the normal registers and the shadow registers This register allows the status of path level alarms to be monitored NEWPTRE The NEWPTRE bit is the interrupt enable for the receive new pointer status When NEWPTRE is a logic one an interrupt is generated when the pointer interpreter validates a new pointer NEWPTRI The NEWPTRI bit is the receive new pointer interrupt status bit NEWPTRI is a logic one when the pointer interpreter has validated a new pointer value H1 H2 NEWPTRI is cleared when this register is read PRDIV The PRDIV bit is read to determine the remote defect indication state When PRDIV is a logic one the S UNI QUAD has declared path RDI PAISV The PAISV bit is read to determine the path AIS state When PAISV is a logic one the S UNI QUAD has declared path AIS Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 100 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD PAISCONV The PAISCONV bit is read to determine the concatenation path AIS state When PAISCONV is a logic the S UNI QUAD has declared a conc
145. e as QAVD providing the 100ohm resistor in series with QAVD shown in Figure 29 and Figure 30 is in place The AVD supplies should also be current limited to the maximum latchup current specification 100 mA To prevent forward biasing the ESD protection diode between AVD supplies and QAVD the differential voltage measured between these power supplies must be less than 0 5 volt This recommended differential voltage is to include peak to peak noise on the QAVD and AVD power supplies as digital noise will Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 218 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD otherwise be coupled into the analog circuitry Current limiting can be accomplished by using an off chip three terminal voltage regulator supplied by a quiet high voltage supply If the VDD power supply is relatively quiet VDD can be filtered using a ferrite bead and a high frequency decoupling capacitor to supply AVD The relative power sequencing of the multiple AVD power supplies is not important 5 Power down the device in the reverse sequence Use the above current limiting technique for the analog power supplies Small offsets in VDD AVD discharge times will not damage the device Figure 19 illustrates a power sequencing circuit to avoid latch up or damage to 3 3V devices that are 5V tolerant This circu
146. e payload pointer are included in the pointer interpreter state machine When ENSS is a logic one an incorrect SS bit pattern causes the pointer interpreter to enter the LOP loss of pointer state and prevents a new pointer indication When ENSS is a logic zero the SS bits are ignored by the pointer interpreter SOS The SOS controls the spacing between consecutive pointer justification events in the receive stream When SOS is a logic one the definition of inc ind and dec ind indications includes the requirement that active offset changes have occurred at least three frames ago When SOS is a logic zero Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 120 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD pointer justification indications in the receive stream are followed without regard to the proximity of previous active offset changes Reserved The reserved bits must be programmed to logic zero for proper operation Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 121 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x40 TPOP Control Diagnostic Bit Type Function Default Bit 7 Unused X Bit 6 R W EPRDIEN Bit 5 R W EPRDISRC Bit 4 R W PERSIST Bit 3
147. e provides a path error monitoring function The path signal label indicator identifies the equipped payload type For ATM payloads the identification code is 0x13 The path status byte provides a path FEBE function and a path remote defect indication function Three bits are allocated for remote defect indications bit 5 the path RDI bit bit 6 the auxiliary path RDI bit and bit 7 Enhanced RDI bit Taken together these bits provide a eight state path RDI code that can be used to categorize path defect indications Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 203 F2 MC PMC Serta ING PM5349 S UNI QUAD PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD S UNI QUAD DATASHEET H4 The multiframe indicator byte is a payload specific byte and is not used for ATM payloads 13 2 ATM Cell Data Structure ATM cells may be passed to from the S UNI QUAD using a twenty seven word 16 bit Utopia level 2 compliant data structure This data structure is shown in Figure 12 Figure 12 16 bit Wide 27 Word ATM Cell Structure Bit 15 Bit8 Bit7 Bit 0 Word 1 Word 2 L Word 27 PAYLOAD47 PAYLOAD48 Word 6 Bit 15 of each word is the most significant bit which corresponds to the first bit transmitted or received The header check sequence octet HCS is passed through this structure The start of cell indication input and output TSOC and RSOC are coincident
148. e the HCS Verification state machine is in the Detection Mode state or HCS bit errors detected but not corrected while the state machine is in the Correction Mode state The 21 bit receive cell counter counts all cells written into the receive FIFO Filtered cells are not counted Each counter may be read through the microprocessor interface Circuitry is provided to latch these counters so that their values can be read while simultaneously resetting the internal counters to 0 or 1 if appropriate so that a new period of accumulation can begin without loss of any events It is intended that the counter be polled at least once per second so as not to miss HCS error events 10 7 Transmit Line Interface CSPI The Transmit Line Interface allows to directly interface the S UNI QUAD with optical modules ODLs or other medium interfaces This block performs clock synthesis and performs parallel to serial conversion of the incoming outgoing 155 52 Mbit s data stream 10 7 1 Clock Synthesis The transmit clock is synthesized from a 19 44 MHz reference The transfer function yields a typical low pass corner of 2 0 MHz above which reference jitter is attenuated at 12 dB per octave The design of the loop filter and PLL is optimized for minimum intrinsic jitter With a jitter free 19 44 MHz reference the Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 46 ON AC scs MC PME Sera TR PM5349 S UNI QUAD
149. ed if the ALLONES bit is set low The SDINS bit enables the insertion of line AIS in the receive direction upon the declaration of signal degrade SD If SDINS is a logic one line AIS is inserted into the Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 170 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD SONET SDH frame when SD is declared Line AIS is terminated when SD is removed Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 171 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x95 S UNI QUAD Channel Receive Path AIS Control Type Function peur R W PAISCONPAIS Bit 6 R W LOPCONPAIS Bit 5 R W Reserved Bit O R W Reserved This register controls the auto assertion of path AIS on the receive side of the system interface AIS forces a loss of cell delineation PAISPAIS When set high the PAISPAIS bit enables path AIS insertion when path AIS events are detected in the receive stream When PAISPAIS is set low path AIS events will not assert path AIS LOPPAIS When set high the LOPPAIS bit enables path AIS insertion when loss of pointer LOP events are detected in the receive stream When LOPPAIS is set low loss of pointer events will not as
150. ent pointer is not updated by an enabled NDF if the pointer is out of range AIS ind H1 hFE H2 hFF inc ind disabled NDF ss majority of bits inverted no majority of D bits inverted previous NDF enable inc ind or dec ind more than 3 frames ago dec ind disabled NDF ss majority of D bits inverted no Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 39 S UNI QUAD DATASHEET PMC Serta ING PM5349 S UNI QUAD PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD majority of bits inverted previous NDF enable inc ind or dec ind more than 3 frames ago inv point not any of above i e not norm point and not NDF enable and not AIS ind and not inc ind and not dec ind new point disabled ss offset value in range of 0 to 782 but not equal to active offset inc req majority of bits inverted no majority of D bits inverted dec req majority of D bits inverted no majority of bits inverted Note 1 active offset is defined as the accepted current phase of the SPE VC in the NORM state and is undefined in the other states Note 2 enabled NDF is defined as the following bit patterns 1001 0001 1101 1011 1000 Note 3 disabled NDF is defined as the following bit patterns 0110 1110 0010 0100 0111 Note 4 the remaining six NDF codes 0000 0011 0101 1010 1100 1111 result
151. er 0x31 EXTD 1 RPOP Interrupt Status Bit 0 H ERDII NOTE To facilitate additional register mapping shadow registers have been added to registers 0x30 0x31 and 0x33 These shadow registers are accessed in the same way as the normal registers The EXTD extend register bit must be set in register 0x36 to allow switching between accessing the normal registers and the shadow registers This register allows identification and acknowledgment of path level alarm and error event interrupts ERDII The ERDII bit is set to logic one when a change is detected in the received enhanced RDI state ERDII is cleared when the RPOP Interrupt Status register is read Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 105 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x32 RPOP Pointer Interrupt Status This register allows identification and acknowledgment of pointer event interrupts NDFI The NDFI bit is the new data flag interrupt status bit NDFI is set to a logic one when the NDF field is active in the received pointer H1 H2 This bit is cleared when this register is read PSEI The PSEI bit is the positive stuff event interrupt status bit PSEI is a logic one when a positive stuff event is detected in the received pointer H1 H2 This bit is cleared when this regis
152. esses that are not shown must be treated as Reserved A 10 is the test resister select TRS and should be set to logic zero for normal mode register access Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 58 S UNI QUAD DATASHEET PMC 971239 F2 MC PMC Serta ING PM5349 S UNI QUAD ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 11 NORMAL MODE REGISTER DESCRIPTION Normal mode registers are used to configure and monitor the operation of the S UNI QUAD Normal mode registers as opposed to test mode registers are selected when TRS A 10 is low Notes on Normal Mode Register Bits 1 Writing values into unused register bits has no effect However to ensure software compatibility with future feature enhanced versions of the product unused register bits must be written with logic zero Reading back unused bits can produce either a logic one or a logic zero hence unused register bits should be masked off by software when read All configuration bits that can be written into can also be read back This allows the processor controlling the S UNI QUAD to determine the programming state of the block Writable normal mode register bits are cleared to logic zero upon reset unless otherwise noted Writing into read only normal mode register bit locations does not affect S UNI QUAD operation unless otherwise noted Performance monitoring counters registers ar
153. f cells based on the detection of an uncorrectable HCS error When HCSPASS is a logic zero cells containing an uncorrectable HCS error are dropped When HCSPASS is a logic one cells are passed to the receive FIFO regardless of errors detected in the HCS Additionally the HCS verification finite state machine never exits the correction mode Regardless of the programming of this bit cells are always dropped while the cell delineation state machine is in the HUNT or PRESYNC states unless the CCDIS bit in this register is set to logic one CCDIS The CCDIS bit can be used to disable all cell filtering and cell delineation All payload data read from the RXCP is passed into its FIFO without the requirement of having to find cell delineation first Reserved The reserved bits must be programmed to logic zero for proper operation Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 135 S UNI QUAD DATASHEET PMC 971239 ON AC scs MC PME Sera TR PM5349 S UNI QUAD ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x62 RXCP FIFO UTOPIA Control amp Config Bit Type Function Default Bit 7 R W RXPTYP 0 Bit 6 Unused Bit 5 R W R W RCAINV RCALEVELO Unused Bit 2 Unused R W FIFORST The FIFORST bit is used to reset the four cell receive FIFO When FIFORST is set to logic zero the FIFO operates normally When FIFORST is set to logic one the
154. four channels to align the transport frames to a system reference e Provides a single transmit byte clock divide by eight of the synthesized line rate clock to provide a timing reference for the transmit outputs Optionally inserts register programmable APS K1 K2 and synchronization status S1 bytes Optionally inserts path alarm indication signal PAIS path remote defect indication PRDI line alarm indication signal LAIS and line remote defect indication LRDI e Inserts path BIP 8 codes path far end block error G1 indications line BIP 24 codes B2 line far end block error M1 indications and section BIP 8 codes B1 to allow performance monitoring at the far end Scrambles the transmitted STS 3c STM 1 stream and inserts the framing bytes A1 A2 Inserts ATM cells into the transmitted STS 3c STM 1 synchronous payload envelope 1 5 The Transmit ATM Processor e Provides idle unassigned cell insertion e Provides HCS generation insertion and ATM cell payload scrambling e Counts number of transmitted and idle cells e Provides a synchronous 8 bit wide four cell FIFO buffer Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 3 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 2 APPLICATIONS e LAN switches and hubs e Layer 3 switches e Multiservice switches
155. hen AUTOPRDI is set to logic one STS path RDI is inserted immediately upon declaration of several alarms Each alarm can individually be enabled and disabled using the S UNI QUAD Channel Path RDI Control Registers AUTOLRDI The AUTOLRDI bit determines if line remote defect indication RDI is sent immediately upon detection of an incoming alarm When AUTOLRDI is set to logic one line RDI is inserted immediately upon declaration of several alarms Each alarm can individually be enabled and disabled using the S UNI QUAD Channel Line RDI Control Registers AUTOPFEBE The AUTOPFEBE bit determines if the path far end block errors are sent upon detection of an incoming path BIP error events When AUTOPFEBE is set to logic one one path FEBE is inserted for each path BIP error event respectively When AUTOPFEBE is set to logic zero incoming path BIP error events do not generate FEBE events AUTOLFEBE The AUTOLFEBE bit determines if line far end block errors are sent upon detection of an incoming line BIP error events When AUTOLFEBE is set to logic one one line FEBE is inserted for each line BIP error event respectively When AUTOLFEBE is set to logic zero incoming line BIP error events do not generate FEBE events Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 69 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD
156. ications e g three consecutive AIS indications to go from the NORM state to the AIS state The kind and number of consecutive indications activating a transition is chosen such that the behavior is stable and insensitive to low BER The only transition on a single event is the one from the AIS state to the NORM state after receiving a NDF enabled with a valid pointer value It should be noted that since the algorithm only contains transitions based on consecutive indications this implies that for example non consecutively received invalid indications do not activate the transitions to the LOP state Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 38 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Figure 3 Pointer Interpretation State Diagram 3xeq new point inc ind dec ind NDF enable 3x eq new point 8x inv point 3x eq new point 3x AIS ind NDF enable 3xAIS ind 8xinv point The following table defines the events indications shown in the state diagram Table 1 Pointer Interpreter Event Indications Description Event Indication Description norm point disabled NDF ss offset value equal to active offset NDF enable enabled NDF ss offset value in range of 0 to 782 or enabled NDF ss if NDFPOR bit is set Note that the curr
157. iming information to the Error Monitor and the Extract blocks The block contains a free running timeslot counter that is initialized by a J1 byte identifier which identifies the first byte of the SPE Control signals are provided to the Error Monitor and the Extract blocks to identify the Path Overhead bytes and to downstream circuitry to extract the ATM cell payload 10 5 3 Error Monitor The Error Monitor Block contains two 16 bit counters that are used to accumulate path BIP 8 errors B3 and far end block errors FEBEs The contents of the two counters may be transferred to holding registers and the counters reset under microprocessor control Path BIP 8 errors are detected by comparing the path BIP 8 byte B3 extracted from the current frame to the path BIP 8 computed for the previous frame FEBEs are detected by extracting the 4 bit FEBE field from the path status byte G1 The legal range for the 4 bit field is between 0000 and 1000 representing zero to eight errors Any other value is interpreted as zero errors Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 42 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Path RDI alarm is detected by extracting bit 5 of the path status byte The PRDI signal is set high when bit 5 is set high for five ten consecutive frames PRDI is set low when bit 5 is lo
158. ing multi PHY operation several PHY layer devices share the RDAT 15 0 RSOC RPRTY and RCA signals As a result these signals must be tri stated in all PHY devices which have not been selected for reading or polling by the ATM Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 224 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Layer Selection of which PHY layer device is being read is made by the value on RADR 4 0 the cycle before RENB is asserted and affects the RDAT 15 0 RSOC and RPRTY signals The value of RADR 4 0 selects the PHY being polled for the RCA signal and all devices not corresponding to this address must tri state its RCA output These multi PHY operations are directly supported by the S UNI QUAD Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 225 M di PMC Sierra Inc S UNI QUAD DATASHEET PMC 971239 ISSUE 6 PM5349 S UNI QUAD SATURN USER NETWORK INTERFACE 155 QUAD 15 ABSOLUTE MAXIMUM RATINGS Maximum rating are the worst case limits that the device can withstand without sustaining permanent damage They are not indicative of normal mode operation conditions Table 13 Absolute Maximum Ratings Ambient Temperature under Bias 40 C to 85 C Storage Temperature 40 C to 125 C Supply Voltage 0 3V to
159. ins for the analog core QAVS should be connected to analog GND AVD Analog RAVD1_A Channel 1 PECL Input Buffer Power RAVD1_B Channel 1 CRU RAVD1_C Channel 1 CRU RAVD2 A Channel 2 PECL Input Buffer RAVD2_B Channel 2 CRU RAVD2_C Channel 2 CRU RAVD3_A Channel 3 PECL Input Buffer RAVDS B Channel CRU RAVDS3 C Channel CRU RAVDA A Channel 4 PECL Input Buffer RAVDA B Channel 4 CRU RAVDA C Channel 4 CRU TAVD1 A CSU TAVD1 B CSU The analog power AVD pins for the analog core AND should be connected to analog 3 3V Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 29 ra MC PMC Serta Ie PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD AVS Analog RAVS1_A Channel 1 PECL Input Buffer Ground RAVS1_B Channel 1 CRU RAVS1_C Channel 1 CRU RAVS2_A Channel 2 PECL Input Buffer RAVS2_B Channel 2 CRU RAVS2_C Channel 2 CRU RAVS3_A Channel 3 PECL Input Buffer RAVS3_B Channel 3 CRU RAVS3_C Channel 3 CRU RAVS4_A Channel 4 PECL Input Buffer RAVS4_B Channel 4 CRU RAVS4_C Channel 4 CRU TAVS1_A CSU TAVS1_B CSU The analog ground AVS pins for the analog core AVS should be connected to analog GND Notes on Pin Description 1 All S UNI QUAD inputs and bi directionals present minimum capacitive loading and operate at TTL logic levels except the
160. ion Default Bt7 R Bite TCELLO X Bits R TCELLS X Bit 4 TCELLI4 Bit 3 TCELL 3 Bit 2 TCELL 2 Bit 1 TCELL 1 Bit 0 R TCELL 0 X Register 0x87 TXCP Transmit Cell Count Bit Function Default Bt7 R TCELL X Bite R X Bits R TCELL IS X Bt4 R TCELL 2 x Bits X Bt2 R TCELL 0 X Bt X Bito R X Register 0x88 TXCP Transmit Cell Count MSB Bit Type Function Default Bt7 Unused X Bite X Bt5 Bt4 Unused Bits Unused Bt2 8 Bt X Bito R TCEL t6 X TCELL 18 0 The TCELL 18 0 bits indicate the number of cells read from the transmit FIFO and inserted into the transmission stream during the last accumulation interval Idle cells inserted into the transmission stream are not counted A write to any one of the TXCP 50 Transmit Cell Counter registers or to the S UNI QUAD Channel Reset and Monitoring Update register Register 0x05 Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 161 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD loads the registers with the current counter value and resets the internal 19
161. is used as the reference clock by both clock recovery and clock synthesis circuits This pin is shared by all channels The receive differential data inputs RXD RXD contain the NRZ bit serial receive stream The receive clock is recovered from the RXD bit stream Please refer to the Operation section for a discussion of PECL interfacing issues This pin is available independently for each channel The Signal Detect pin SD indicates the presence of valid receive signal power from the Optical Physical Medium Dependent Device A PECL high indicates the presence of valid data and a PECL low indicates a loss of signal It is mandatory that SD be terminated into the equivalent network that RXD is terminated into This pin is available independently for each channel The receive byte clock RCLK provides a timing reference for the S UNI QUAD receive outputs RCLK is a divide by eight of the recovered line rate clock 19 44 MHz This pin is available independently for each channel Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 12 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Output The Receive Frame Pulse Output RFPO when the framing alignment is found the OOF register bit is logic zero is an 8 kHz signal derived from the receive line clock RFPO pulses high for one RCLK
162. it will ensure V a is greater than V and protect against designs which require the 3 3V power supply appearing before the 5V supply Figure 19 Power Sequencing Circuit IKQ SV o T amp V bus 0 IMF Schottky Diode 3 3V o o Via 13 9 Analog Power Supply Filtering The noise environment and signal integrity are often the limiting factors of the system performance thus the following analog power filtering scheme is recommended Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 219 S UNI QUAD ron Aa MC BME siete ING 5349 S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Figure 20 LAN Mode Analog Power Filters with 3 3V Supply 270 3 3V TAVD1 A 4 7uF M fo a esse 0 1uF 27 Q 3 3V TAVD1 B 47uF 0 1uF 1002 3 3V QAVD1 Fe QAVD2 0 1uF NOTES NA 1 Use 0 1uF on all other analog and digital power pins 2 place 0 1uF as close to power pin as possible 3 47uF and resistors do not have to be very close to power pins Please note TAVD1 Ais pin L3 TAVD1 Bis pin L1 QAVD is pin AA6 QAVD2 is pin 13 10 Interfacing to ECL or PECL Devices Although the TXD outputs are TTL compatible only a few passive components are required to convert the signals to ECL or PECL logic levels Figure 21 illustrates the recommended configuration The capacitor
163. ite to the TLOP Transmit K1 Register A coherent APS code value is ensured by writing the desired K2 APS code value to this register before writing the TLOP Transmit K1 Register Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 98 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x24 S UNI QUAD Channel Transmit Sync Message S1 Bit Type Function Default Bit7 R W Reserved 0 Bit6 R W Reserved Bit5 R W Reserved Bito R W TS1 0 TS1 3 0 The value written to these bit positions is inserted in the first S1 byte position of the transmit stream The S1 byte is used to carry synchronization status messages between line terminating network elements TS1 3 is the most significant bit corresponding to the first bit transmitted TS1 0 is the least significant bit corresponding to the last bit transmitted Reserved The reserved bits must be programmed to logic zero for proper operation Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 99 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x30 EXTD 0 RPOP Status Control Bit Type Function Default Bit 7 R W Reserved 0 Bit 6 R LOPCONV Bit 5 LOPV NOTE To facilitat
164. ition Description inc_ind dec_ind offset adjustment increment or decrement indication 3xeq new point three consecutive equal new point indications NDF enable single enable indication 3 x AIS ind three consecutive AIS indications 8xinv point eight consecutive inv point indications 8x NDF enable eight consecutive NDF enable indications Note 1 Note 2 Note 3 Note 4 the transitions from NORM state to NORM state do not represent state changes but imply offset changes 3xnew point takes precedence over other events and if the IINVCNT bit is set resets the inv point count all three offset values received in 3 x eq new point must be identical consecutive event counters are reset to zero on a change of state except for consecutive NDF count The Pointer Interpreter detects loss of pointer LOP in the incoming STS 3c STM 1 stream LOP is declared on entry to the state as a result of eight consecutive invalid pointers or eight consecutive NDF enabled indications The alarm condition is reported in the receive alarm port and is optionally returned to the source no de by signaling the corresponding Transmit Path Overhead Processor in the local S UNI QUAD to insert a path RDI indication The Pointer Interpreter detects path AIS in the incoming STS 3c STM 1 stream PAIS is declared on entry to the 5 state after three consecutive AIS indications The ala
165. k performs clock and data recovery and performs serial to parallel conversion on the incoming 155 52 Mbit s data stream 10 1 1 Clock Recovery The clock recovery unit recovers the clock from the incoming bit serial data stream The clock recovery unit is fully compliant with SONET and SDH jitter tolerance requirements The clock recovery unit utilizes a low frequency reference clock to train and monitor its clock recovery PLL Under loss of signal conditions the clock recovery unit continues to output a line rate clock that is locked to this reference for keep alive purposes The clock recovery unit utilizes a reference clocks at 19 44 MHz The clock recovery unit provides status bits that indicate whether it is locked to data or the reference The clock recovery unit also supports diagnostic loopback and a loss of signal input that squelches normal input data Initially the PLL locks to the reference clock REFCLK When the frequency of the recovered clock is within 488 ppm of the reference clock the PLL attempts to lock to the data Once in data lock the PLL reverts to the reference clock if no data transitions occur in 80 bit periods or if the recovered clock drifts beyond 488 ppm of the reference clock When the transmit clock is derived from the recovered clock loop timing the accuracy of the transmit clock is directly related to the REFCLK reference accuracy in the case of a loss of signal condition To meet the Bellcore GR 253 CORE
166. l Update PMC Sierra Inc 105 8555 Baxter Place Burnaby BC Canada V5A 4V7 604 415 6000 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD CONTENTS 1 agis 1 1 1 atre nete tet edet ies 1 1 2 THE SONET REGEIMER reb ee Ree eot red 1 1 3 THE RECEIVE ATM 5 2 1 4 5 5 rene rennen nre 2 1 5 THE TRANSMIT ATM rennen 3 2 APPLICATIONS pe eee et be regret ett 4 3 REFERENCES f eed dee 5 4 DEFINITIONS 4er rediere eee eiat COP I Hee tenes 6 5 gt rp ER nna e e DRE ERR M e ein 7 6 BLOCK DIAGRAM ete dans 8 7 DESCRIPTION ton te tto dit an tra bett cond 9 8 PIN DIAGRAM eii peti e ur e ipn ea acini av aii ined 11 9 PIN DESCRIPTION i irre er Re pina te eere P EE Ser aude Aaa antes 12 9 1 LINE SIDE INTERFACE SIGNALS enne 12 9 2 UTOPIA LEVEL 2 SYSTEM INTERFACE eee 15 9 3 MICROPROCESSOR INTERFACE SIGNALS 23 9 4 JTAG TEST ACCESS PORT TAP SIGNALS eene 25 9 5 ANALOG SIGNALS du ir abe hun e ade DE ba oes 26 9 6 POWER AND rennen tnnt nennen 26 10 FUNCTIONAL
167. larm is removed when the number of B2 errors accumulated during an evaluation window is less than the SDCTH 11 0 value Refer to the Operations section for the recommended settings Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 189 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register OxF5 RASE Receive K1 Bit 0 K1 0 K1 7 0 The K1 7 0 bits contain the current K1 code value The contents of this register are updated when a new K1 code value different from the current K1 code value is received for three consecutive frames An interrupt may be generated when a new code value is received using the COAPSE bit in the RASE Interrupt Enable Register K1 7 is the most significant bit corresponding to bit 1 the first bit received K1 0 is the least significant bit corresponding to bit 8 the last bit received Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 190 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register OxF6 RASE Receive K2 Bit 0 2 0 2 7 0 K2 7 0 bits contain the current K2 code value The contents of this register are updated when a new K2 code value different from the current K2 code value is received f
168. latency through the TXCP must be minimized When the FIFO is filled to the specified depth the transmit cell available signal TCA and DTCA x is asserted Note that regardless of what fill level FIFODP 1 0 is set to the transmit cell processor can store 4 complete cells The selectable FIFO cell depths are shown below Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 153 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD FIFODP 1 FIFODP 0 FIFO DEPTH 09 7 70 0 1 3 ls fee ee 0l e TCAINV The TCAINV bit inverts the polarity of the TCA and DTCA x output signal When TCAINV is a logic one the polarity of TCA and DTCA x is inverted TCA and DTCA x at logic zero means there is transmit cell space available to be written to When TCAINV is a logic zero the polarity of TCA and DTCA x is not inverted Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 154 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x82 TXCP Cell Count Status Configuration Options Bit Type Function Default 0 Bit7 R W XFERE Bit 6 R XFERI Bit 5 R OVR BitO R W Reserved HAINSB The active low H4 insert en
169. les enhanced path RDI assertion when loss of signal LOS loss of frame LOF or line alarm indication signal LAIS events are detected in the receive stream If enabled when these events occurs bit 6 of the G1 byte is set low while bit 7 of the G1 byte is set high NOALMEPRDI has precedence over PSLMERDI and UNEQERDI When NOALMEPRDI is set low reporting of enhanced RDI is according to PSLMERDI and UNEQERDI and the associated alarm states LCDEPRDI When set high the LCDEPRDI bit enables enhanced path RDI assertion when loss of cell delineation LCD events are detected in the receive stream If enabled when the event occurs bit 6 of the G1 byte is set high while bit 7 of the G1 byte is set low When LCDEPRDI is set low loss of ATM cell delineation has no effect on path RDI In addition this bit has no effect when EPRDI EN is set low Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 168 S UNI QUAD DATASHEET PMC 971239 ON AC scs MC PME Sera TR PM5349 S UNI QUAD ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x93 S UNI QUAD Channel Receive RDI and Enhanced RDI Bit Control Extensions Type Function Default Bit 7 R W PAISCONPRDI 0 Bit 6 R W NOPAISCONEPRDI 0 Bit 5 Unused X This register along with the S UNI QUAD Channel Path RDI Control register controls the auto assertion of path RDI on the TPOP transmit stream This register along with
170. lies to RSTB and Voltage TRSTB only Reset Input TBD Volts Applies to RSTB and Hysteresis TRSTB only Voltage Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 227 PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Pu upu Input Low Current 100 50 4 pA GND Notes 1 and Input High Current SE e ViH Vpp Notes 1 and ee cee on macmeme s wemeriwe _ Output ta 25 C f 1 MHz Capacitance Cio Bi directional 5 pF tA 25 0 f21MHz Capacitance IDDOP Operating Current 320 530 mA Vpp 3 63V Outputs Unloaded Notes on D C Characteristics 1 Input pin or bi directional pin with internal pull up resistor 2 Input pin or bi directional pin without internal pull up resistor 3 Negative currents flow into the device sinking positive currents flow out of the device sourcing 4 Refer to the footnotes at the bottom of the PIN DESCRIPTION table for the DC current rating of each device output Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 228 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 17 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS TA 40 C to 85 Vpp 3 3V 10 Table 15 Microprocessor Interface
171. n the RALRM output pin when enabled by the LOSEN Receive Alarm Control Register bit Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 34 S UNI QUAD ron Aa MC BME siete ING 5349 S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 10 2 5 Loss of Frame The Loss of Frame Block monitors the in frame out of frame status of the Framer Block A loss of frame LOF is declared when an out of frame OOF condition persists for 3 ms The LOF is cleared when an in frame condition persists for a period of 3 ms To provide for intermittent out of frame or in frame conditions the 3 ms timer is not reset to zero until an in frame or out of frame condition persists for 3 ms The LOF and OOF signals are optionally reported on the RALRM output pin when enabled by the LOFEB and OOFEN Receive Alarm Control Register bits 10 3 Receive Line Overhead Processor RLOP The Receive Line Overhead Processor RLOP provides line level alarm and performance monitoring 10 3 1 Line RDI Detect The Line RDI Detect Block detects the presence of Line Remote Defect Indication LRDI in the receive stream Line RDI is declared when a 110 binary pattern is detected in bits 6 7 and 8 of the K2 byte for three or five consecutive frames Line RDI is removed when any pattern other than 110 is detected in bits 6 7 and 8 of the K2 byte for three or five consecutive frames
172. ns it is possible to blow these ESD protection devices or trigger latch up Please adhere to the recommended power supply sequencing as described in the OPERATION section of this document If it is intended to substitute a S UNI QUAD in a S UNI TETRA socket special attention must be given to the NC pins The requirement is that no S UNI QUAD input pin is left floating when used in a S UNI QUAD socket Please refer to the relevant PMC Sierra Inc application note Some device pins can be made 5V tolerant by connecting the BIAS pins to 5V power supply while some other pins are 3 3V only In summary the system interface is 3 3V only while the microprocessor interface SONET and line interfaces can be 5V tolerant 3 3V only l O s RDAT 15 0 RSOC RPRTY RENB TDAT 15 0 TSOC TPRTY TENB RCA DRCA4 1 TCA DTCA4 1 RADR 5 0 TADR 5 0 PHY_OEN 5V tolerant l O s REFCLK RXD RCLK4 1 RFPO4 1 RALRM4 1 TCLK TFPO TFPI D 7 0 A 10 0 WRB RDB CSB RSTB INTB ALE TRSTB TCK TMS TDI TDO Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 31 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 10 FUNCTIONAL DESCRIPTION 10 1 Receive Line Interface CRSI The Receive Line Interface allows to directly interface the S UNI QUAD with optical modules ODLs or other medium interfaces This bloc
173. o input TPRTY is the odd parity bit for the TDAT input bus Reserved The reserved bits must be programmed to logic zero for proper operation Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 152 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x81 TXCP Configuration 2 Bit4 RW TCAINV Bit3 R W FIFODP 1 Bit2 R W FIFODP O0 HCSCTLEB HCSCTLEB The active low HCS control enable HCSCTLEB bit enables the XORing of the HCS Control byte with the generated HCS When set to logic zero the HCS Control byte provided in the third word of the 27 word data structure is XORed with the generated HCS When set to logic one XORing is disabled and the HCS Control byte is ignored DHCS The DHCS bit controls the insertion of HCS errors for diagnostic purposes When DHCS is set to logic one the HCS octet is inverted prior to insertion in the synchronous payload envelope DHCS takes effect unconditionally regardless of whether a null unassigned cell is being transmitted or whether the HCS octet was read from the FIFO DHCS occurs after any error insertion caused by the Control Byte in the 27 word data structure FIFODPT 1 0 The FIFODP 1 0 bits determine the transmit FIFO cell depth at which TCA and DTCA x de assert FIFO depth control may be important in systems where the cell
174. o logic zero the PECL receivers are configured to operate with a 3 3V input voltage When PECLV is set to logic one the PECL receivers are configured to operate with a 5 0V input voltage Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 61 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Reserved The reserved bits must be programmed to their default value proper operation Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 62 S UNI QUAD DATASHEET PMC 971239 F2 MC PMC Serta ING PM5349 S UNI QUAD ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x02 S UNI QUAD Master System Interface Control Bit Type Function Default Bit 7 R W ADRI 2 0 Bit6 R W PHY ADR 1 Bitb R W PHY ADR 0 Bit 0 R W PHY EN The PHY EN enables the System Interface Utopia bus When set to logic zero all the output signals of the System Interface are held in high impedance When set to logic one the System Interface is driven This register bit must be set to logic one to start using the device If the System Interface is shared by several PHY layer devices they should all be configured with their own unique PHY ADR 2 0 see below value before enabling them otherwise conflicts could occur on the bus resulting in
175. octet prior to insertion in the synchronous payload envelope When HCSADD is a logic one the polynomial is added and the resulting HCS is inserted When HCSADD is a logic zero the polynomial is not added and the unmodified HCS is inserted HCSADD takes effect unconditionally regardless of whether a null unassigned cell is being transmitted or whether the HCS octet was read from the FIFO HCSB The active low HCSB bit enables the internal generation and insertion of the HCS octet into the transmit cell stream When HCSB is logic zero the HCS is generated and inserted internally If HCSB is logic one then no HCS octet is inserted in the transmit data stream Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 151 F2 MC PMC Serta ING PM5349 S UNI QUAD PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD S UNI QUAD DATASHEET TCALEVELO The active high TCA and DTCA x level 0 bit TCALEVELO determines what output TCA and DTCA x indicates when it transitions low When TCALEVELO is set to logic one output TCA and DTCA x indicates that the transmit FIFO is full and can accept no more writes When TCALEVELO is set to logic zero output TCA and DTCA x indicates that the transmit FIFO is near full TPTYP The TPTYP bit selects even or odd parity for input TPRTY When set to logic one input TPRTY is the even parity bit for the TDAT input bus When set to logic zer
176. ode registers are required for normal operation and test mode registers are used to enhance the testability of the S UNI QUAD The register set is accessed as shown in Table 3 In the following section every register is documented and identified using the register number REG The corresponding memory map address for every channel CH 1 2 3 4 is given in the table Addresses that are not shown are not used and must be treated as Reserved Table 3 Register Memory Map Address A 10 0 Description Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 52 PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD REG CH CH CH CH 000 S UNI QUAD Master Reset and Identit S UNI QUAD Master Configuration 002 S UNI QUAD Master System Interface Config S UNI QUAD Master Clock Monitor 004 IS UNI QUAD Master Interrupt Status sd Monitoring Update 006 106 206 206 EE QUAD Channel Configuration 08 008 108 208 308 S UNKQUAD Channel Control Extensions 09 009 109 209 309 Reseved OE OB 008 10B 20B 30B Reserved oC ooc CSPI Control and Status Clock Synthesis oD OD 313 ios Section BIP 8 MSB 31B RLOP Line BIP 24 23 023 123 223 323 TLOP Transmit K2 24 024
177. of path FEBE errors G1 that have been detected since the last time the error count was polled The error count is polled by writing to either of the RPOP Path BIP 8 Register addresses or to either of the RPOP Path FEBE Register addresses Such a write transfers the internally accumulated error count to the Path FEBE Registers within a maximum of 7 us and simultaneously resets the internal counter to begin new cycle of error accumulation This transfer and reset is carried out in a manner that ensures that coincident events are not lost The count can also be polled by writing to the S UNI QUAD Channel Reset and Monitoring Update register 0x05 Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 118 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register Ox3C RPOP Auxiliary RDI Bit Type Function Default Bit 7 Unused X Bit 6 Unused Bit 5 R W Reserved Bit 4 R W BLKFEBE Bit 3 Unused Bit 2 R W Reserved R W APRDIE APRDIV APRDIE The APRDIE bit is the interrupt enable for auxiliary path RDI When APRDIE is a logic one an interrupt is generated when the auxiliary path RDI state changes APRDIV The APRDIV bit is read to determine the auxiliary path RDI state When APRDIV is a logic one the S UNI QUAD has declared auxiliary path RDI BLKFEBE When set to logic one the block FEBE
178. omers Internal Use 223 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD During multi PHY operation several PHY layer devices share the TCA signal As a result this signals must be tri stated in all PHY devices which have not been selected for polling by the ATM Layer The value of TADR 4 0 selects the PHY being polled for the TCA signal and all devices not corresponding to this address must tri state its TCA output This multi PHY operation is directly supported by the S UNI QUAD Figure 23 Multi PHY Polling and Addressing Receive Cell Interface SLL RCA s y X 8 S 88 RADRIA0 XY RSOC SF XXX XX XXX Figure 67 shows an example of the multi PHY polling and selection sequence supported by the S UNI QUAD A B D and E represent any arbitrary address values which may be occupied by the S UNI QUAD The ATM Layer device is not restricted in its polling order The PHY associated with address A indicates it does not have a cell available but PHY B indicates that it does As a result the ATM Layer places address B on RADR 4 0 the cycle before RENB is asserted to select PHY B as the next cell source In this example PHY C s status is ignored The ATM Layer device is not constrained to select the latest PHY polled As soon as the cell transfer is started the polling process may be restarted Dur
179. omers Internal Use 77 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD hundred milliseconds after the removal of the power on reset as the CRU PLL locks to the receive reference clock RDOOLI The RDOOLI bit is the receive data out of lock interrupt status bit RDOOLI is set high when the RDOOLV bit of the S UNI QUAD Clock Recovery Control and Status register changes state RDOOLI is cleared when this register is read RROOLI The RROOLI bit is the receive reference out of lock interrupt status bit RROOLI is set high when the RROOLV bit of the Clock Synthesis Control and Status register changes state RROOLI is cleared when this register is read Reserved The reserved bits must be programmed to logic zero for proper operation Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 78 S UNI QUAD DATASHEET PMC 971239 di PMC Sierra Inc PM5349 S UNI QUAD ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register OxOF CRSI Clock Recovery Reserved Bit 4 Bit 3 Bit 2 Bit 1 R W Reserved Bit 0 R W R W R W R W Reserved Reserved Reserved Reserved Reserved The reserved bits must be programmed to logic zero for proper operation Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 79 ON AC scs MC PME
180. on a per frame basis and inserts the accumulated value up to maximum value of eight in the FEBE bit positions of the path status G1 byte The FEBE information is derived from path BIP 8 errors detected by the receive path overhead processor RPOP Far end block errors may be inserted under register control for diagnostic purposes 10 11 Transmit ATM Cell Processor TXCP The Transmit ATM Cell Processor TXCP provides rate adaptation via idle unassigned cell insertion provides HCS generation and insertion and performs ATM cell scrambling The TXCP contains a four cell transmit FIFO An idle or unassigned cell is transmitted if a complete ATM cell has not been written into the FIFO 10 11 1 Idle Unassigned Cell Generator The Idle Unassigned Cell Generator inserts idle or unassigned cells into the cell stream when enabled Registers are provided to program the GFC PTI and CLP fields of the idle cell header and the idle cell payload The idle cell HCS is automatically calculated and inserted 10 11 2 Scrambler The Scrambler scrambles the 48 octet information field Scrambling is performed using a parallel implementation of the self synchronous scrambler x43 1 polynomial described in the references The cell headers are transmitted unscrambled and the scrambler may optionally be disabled Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 50 F2 MC PMC Serta ING PM5349 S UNI QUAD
181. ontrol and Status Bit Type Function Default Bit 7 R W Reserved 0 Bit 6 R RROOLI Bit 5 R RDOOLI Bit O R W Reserved This register controls the clock recovery and reports the state of the receive phase locked loop RDOOLE The RDOOLE bit is an interrupt enable for the receive data out of lock status When RDOOLE is set to logic one an interrupt is generated when the RDOOLV bit changes state RROOLE The RROOLE bit is an interrupt enable for the reference out of lock status When RROOLE is set to logic one an interrupt is generated when the RROOLV bit changes state RDOOLV The receive data out of lock status indicates the clock recovery phase locked loop is unable to lock to the incoming data stream RDOOLV is a logic if the divided down recovered clock frequency is not within 488 ppm of the REFCLK frequency or if no transitions have occurred on the RXD inputs for more than 80 bit periods RROOLV The receive reference out of lock status indicates the clock recovery phase locked loop is unable to lock to the receive reference REFCLK RROOLV should be polled after a power up reset to determine when the CRU PLL is operational When RROOLV is a logic one the CRU is unable to lock to the receive reference When RROOLV is a logic zero the CRU is locked to the receive reference The RROOLV bit may remain set at logic one for several Proprietary and Confidential to PMC Sierra Inc and for its Cust
182. oprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 237 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 18 4 Transmit and Receive Frame Pulses Table 20 Transmit and Receive Frame Pulse Timing Figure 29 i 15 ns 0 ns 0 10 ns tSTFPI TFPI Set up Time to TCLK High Hold Time to High tPTEPO TCLK High to TFPO Valid tPREPO RCLK1 4 High to RFPO1 4 Valid 0 10 ns Figure 29 Transmit and Receive Frame Pulses TCLK TFPI TFPO RCLK1 4 RFPO RFPO1 4 Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 238 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 18 5 JTAG Test Port Timing Table 21 JTAG Port Interface Figure 30 Symbol Description Min Max Units TCK Frequency 1 MHz TCK Duty Cycle 40 60 96 tSTMS TMS Set up time to TCK 50 ns tHTMS TMS Hold time to TCK 50 ns tSTDI TDI Set up time to TCK 50 ns tHTDI TDI Hold time to TCK 50 ns tPTDO TCK Low to TDO Valid 2 50 ns tVTRSTB TRSTB Pulse Width 100 ns Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 239 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET
183. or three consecutive frames An interrupt may be generated when a new code value is received using the COAPSE bit in the RASE Interrupt Enable Register K2 7 is the most significant bit corresponding to bit 1 the first bit received K2 0 is the least significant bit corresponding to bit 8 the last bit received Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 191 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register OxF7 RASE Receive Z1 S1 Bit 0 Z1 S1 0 21 51 3 0 The lower nibble of the first 21 51 byte contained in the receive stream is extracted into this register The 21 51 byte is used to carry synchronization status messages between line terminating network elements Z1 S1 3 is the most significant bit corresponding to bit 5 the first bit received Z1 S1 0 is the least significant bit corresponding to bit 8 the last bit received An interrupt may be generated when a byte value is received that differs from the value extracted in the previous frame using the Z1 S1E bit in the RASE Interrupt Enable Register In addition debouncing can be performed where the register is not loaded until eight of the same consecutive nibbles are received Debouncing is controlled using the 21 51 bit in the RASE Configuration Control register Z1 S1 7 4 The upper nibble of the first
184. ors for low to high transitions on the REFCLK reference clock input REFCLKA is set high on a rising edge of REFCLK and is set low when this register is read TFCLKA The TFCLK active TFCLKA bit monitors for low to high transitions on the TFCLK transmit FIFO clock input TFCLKA is set high on a rising edge of TFCLK and is set low when this register is read RFCLKA The RFCLK active RFCLKA bit monitors for low to high transitions on the RFCLK receive FIFO clock input RFCLKA is set high on a rising edge of RFCLK and is set low when this register is read TCLKA The TCLK active TCLKA bit monitors for low to high transitions on the TCLK output TCLKA is set high on a rising edge of TCLK and is set low when this register is read Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 64 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD RCLK1A The Channel 1 active RCLK1A bit monitors for low to high transitions on the RCLK1 output RCLK1A is set high on a rising edge of RCLK1 and is set low when this register is read RCLK2A The Channel 2 RCLK active RCLK2A bit monitors for low to high transitions on the RCLK2 output RCLK2A is set high on a rising edge of RCLK2 and is set low when this register is read RCLKSA The Channel 3 RCLK active RCLK3A bit monitors for low to high
185. ped if uncorrectable HCS errors are detected or if the corrected header contents match the pattern contained in the RXCP Match Header Pattern and RXCP Match Header Mask registers Idle or unassigned cell filtering is accomplished by writing the appropriate cell header pattern into the RXCP Match Header Pattern and RXCP Match Header Mask registers Idle Unassigned cells are assumed to contain the all zeros pattern in the VCI and VPI fields The RXCP Match Header Pattern and RXCP Match Header Mask registers allow filtering control over the contents of the GFC PTI and CLP fields of the header The HCS is a CRC 8 calculation over the first 4 octets of the ATM cell header The RXCP block verifies the received HCS using the polynomial 8 2 x 1 The coset polynomial x4 2 1 is added modulo 2 to the received HCS octet before comparison with the calculated result While the cell delineation state machine described above is in the SYNC state the HCS verification circuit implements the state machine shown in Figure 5 Figure 5 HCS Verification State Diagram ATM DELINEATION SYNC STATE ALPHA consecutive incorrect HCS s To HUNT state Apparent Multi Bit Error Drop Cell No Errors Detected Pass Cell CORRECTION MODE Single Bit Error Correct Error and Pass Cell 7 Errors Detected Drop Cell DETECTION MODE No Errors Detected In M Cells
186. positions 6 7 and 8 of the K2 byte of the transmit stream APSREG The APSREG bit selects the source for the transmit APS channel When APSREG is a logic zero 0x0000 hexadecimal is inserted in the transmit APS channel When APSREG is a logic one the transmit APS channel is inserted from the TLOP Transmit K1 Register and the TLOP Transmit K2 Register Reserved The reserved bits must be programmed to logic zero for proper operation Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 95 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x21 TLOP Diagnostic Bit 0 R W DBIP DBIP The DBIP bit controls the insertion of bit errors continuously in the line BIP byte s B2 When DBIP is set to logic one the B2 byte s are inverted Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 96 S UNI QUAD DATASHEET PMC 971239 M di PMC Sierra Inc PM5349 S UNI QUAD ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x22 TLOP Transmit K1 Bit Type Function Default Bit 7 R W K1 7 0 Bit6 R W K1 6 Bitb R W K1 5 Bit 0 K1 7 0 R W K1 0 The K1 7 0 bits contain the value inserted in the K1 byte when the APSREG bit in the TLOP Control Register is a logic one K1 7 is the most
187. prietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 70 S UNI QUAD ron Aa MC BME siete ING 5349 S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD RXDINV The RXDINV bit selects the active polarity of the RXD signals The default configuration selects RXD to be active high and RXD to be active low When RXDINV is set to logic one RXD to be active low and RXD to be active high TFPI EN The TFPI EN bit controls the framing alignment in the transmit direction When EN is set to logic one the transmit SONET SDH framing is aligned to a master available to all four channels framing pulse counter which can also be aligned to the TFPI device input When TFPI EN is set to logic zero the transmit framing alignment is arbitrary External framing EN set to logic one shall only be used when the channel is in self timed mode EN should always be set to logic zero when the channel is loop timed LOOPT set to logic one or in line loopback LLE set to logic one Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 71 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x08 S UNI QUAD Channel Control Extension Bit O R W Reserved This register controls the timing and high speed loopback
188. r 0x46 TPOP Arbitrary Pointer MSB Bit Type Function Default Bit7 R W 1 APTR 8 This register allows an arbitrary pointer to be inserted for diagnostic purposes APTR 9 8 The APTR 9 8 bits along with the APTR 7 0 bits in the TPOP Arbitrary Pointer LSB Register are used to set an arbitrary payload pointer value The arbitrary pointer value is inserted in the transmit stream by writing a logic one to the PLD bit in the TPOP Pointer Control Register If the FTPTR bit in the TPOP Pointer Control register is a logic one the current APTR 9 0 value is inserted into the payload pointer bytes H1 and H2 in the transmit stream S 1 S 0 The S 1 0 bits contain the value inserted in the S 1 0 bit positions also referred to as the unused bits in the payload pointer NDFT 3 0 The NDF 3 0 bits contain the value inserted the NDF bit positions when an arbitrary new payload pointer value is inserted using the PLD bit in the TPOP Pointer Control Register or when new data flag generation is enabled using primary input NDF or the NDF bit in the TPOP Pointer Control Register Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 129 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x48 TPOP Path Signal Label Bit Type Function Default Bit7 R W C2 7 0 Bit
189. r and Ground BIAS Bias K21 I O Bias BIAS When tied to 5V via a 1 KQ Voltage C17 resistor he aks input is used to bias the wells in the input and I O pads so that the pads can tolerate 5V on their inputs without forward biasing internal ESD protection devices When BIAS is tied to 3 3V the inputs and bi directional inputs will only tolerate 3 3V level inputs Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 26 ON AC scs MC PME Siera E PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD The digital power VDD pins should be connected to a well decoupled 3 3 V DC supply Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 27 ra MC PMC Serta Ie PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD VSS Ground 2 The digital ground VSS pins should be connected to ground Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 28 ra MC PMC Serta Ie PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD wind Analog ru QAVD1 Power C6 QAVD2 The quiet analog power QAVD pins for the analog core QAVD should be connected to analog 3 3V QAVS Analog Be QAVS1 Ground QAVS2 The quiet analog ground QAVS p
190. r bit is provided to disable the de scrambling operation 10 2 3 Error Monitor The Error Monitor Block calculates the received section BIP 8 error detection code B1 based on the scrambled data of the complete STS 3c STM 1 frame The section BIP 8 code is based on a bit interleaved parity calculation using even parity Details are provided in the references The calculated BIP 8 code is compared with the BIP 8 code extracted from the B1 byte of the following frame Differences indicate that a section level bit error has occurred Up to 64000 8 x 8000 bit errors can be detected per second The Error Monitor Block accumulates these section level bit errors in a 16 bit saturating counter that can be read via the microprocessor interface Circuitry is provided to latch this counter so that its value can be read while simultaneously resetting the internal counter to O or 1 if appropriate so that a new period of accumulation can begin without loss of any events It is intended that this counter be polled at least once per second so as not to miss bit error events 10 2 4 Loss of Signal The Loss of Signal Block monitors the scrambled data of the receive stream for the absence of 1 s When 20 3 us of all zeros patterns is detected a loss of signal LOS is declared Loss of signal is cleared when two valid framing words are detected and during the intervening time no loss of signal condition is detected The LOS signal is optionally reported o
191. ra Inc has been advised of the possibility of such damage 1998 1999 PMC Sierra Inc PMC 971239 P6 ref PMC 971028 R5 Issue date July 1999 PMC Sierra Inc 105 8555 Baxter Place Burnaby BC Canada V5A 4V7 604
192. rdering Information PART NO DESCRIPTION 5349 304 pin Ball Grid Array SBGA Table 23 Thermal Information PART NO AMBIENT TEMPERATURE Theta Ja Theta Jc PM5349 BI 40 C to 85 C 22 C W 1 C W 30 CO 25 20 15 10 Conv 100 200 300 400 500 Dense Board JEDEC Board The junction temperature Tj is less than 105 C for a ambient temperature Ta of 60 C and a 300LFM of airflow The device must operate at Ta 70 C with 100LFM and must not be damaged with Ta 70 C and no airflow This assumes a dense board and a ThetaJA of 16 Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 242 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Loaded power at 3 63V with TXC pins enable mean 2 83W Loaded power at 3 63V with TXC pins enable mean 2 sigma 2 89W The junction temperature 105 C Therefore the package is approved for use without enhanced cooling Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 243 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 20 MECHANICAL INFORMATION Figure 31 Mechanical Drawing 304 Pin Super Ball Grid Array SBGA
193. ressing and parity support e Provides a standard 5 signal IEEE 1149 1 JTAG test port for boundary scan board test purposes e Provides a generic 8 bit microprocessor bus interface for configuration control and status monitoring e Low power 3 3V CMOS with PECL and TTL compatible inputs and CMOS TTL outputs with 5V tolerance inputs system side interface is 3 3V only e Industrial temperature range 40 C to 85 C e 304 pin Super BGA package 1 2 The SONET Receiver e Provides a serial interface at 155 52 Mbit s e Recovers the clock and data e Frames to and de scrambles the recovered stream e Detects signal degrade SD and signal fail SF threshold crossing alarms based on received B2 errors Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 1 S UNI QUAD DATASHEET PMC 971239 ON AC scs MC PME Sera TR PM5349 S UNI QUAD ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Captures and debounces the synchronization status S1 byte in a readable register Filters and captures the automatic protection switch channel K1 K2 bytes in readable registers and detects APS byte failure Counts received section BIP 8 B1 errors received line BIP 24 B2 errors line far end block errors FEBE received path BIP 8 B3 errors and path far end block errors FEBE Detects loss of signal LOS out of frame OOF loss of frame LOF line alarm indication signal LA
194. rm condition reported in the receive alarm port and is Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 41 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD optionally returned to the source node by signaling the corresponding Transmit Path Overhead Processor in the local SONET SDH equipment to insert a path RDI indication Invalid pointer indications inv_point invalid NDF codes new pointer indications new_point discontinuous change of pointer alignment and illegal pointer changes are also detected and reported by the Pointer Interpreter block via register bits An invalid NDF code is any NDF code that does not match the NDF enabled or NDF disabled definitions The third occurrence of equal new point indications 3 x eq new point is reported as a discontinuous change of pointer alignment event DISCOPA instead of a new pointer event and the active offset is updated with the receive pointer value An illegal pointer change is defined as ainc ind or dec ind indication that occurs within three frames of the previous inc ind dec ind or NDF enable indications lllegal pointer changes may be optionally disabled via register bits The active offset value is used to extract the path overhead from the incoming stream and can be read from an internal register 10 5 2 SPE Timing The SPE Timing Block provides SPE t
195. rols the output enable for the data bus While the DBCTRL bit is set holding the CSB pin high causes the S UNI QUAD to drive the data bus and holding the CSB pin low tri states the data bus The DBCTRL bit overrides the HIZDATA bit The DBCTRL bit is used to measure the drive capability of the data bus driver pads PMCTST The PMCTST bit is used to configure the S UNI QUAD for PMC s manufacturing tests When PMCTST is set to logic one the S UNI QUAD microprocessor port becomes the test access port used to run the PMC canned manufacturing test vectors The PMCTST bit is logically ORed with the IOTST bit and can be cleared by setting CSB to logic one or by writing logic zero to the bit PMCATST The PMCATST bit is used to configure the analog portion of the S UNI QUAD for PMC s manufacturing tests Reserved The reserved bit must be programmed to logic one for proper operation 12 2 Test Mode 0 Details In test mode 0 the S UNI QUAD allows the logic levels on the device inputs to be read through the microprocessor interface and allows the device outputs to be forced to either logic level through the microprocessor interface The IOTST bit in the Master Test register must be set to logic one to access the device 1 0 To enable test mode 0 the IOTST bit in the Master Test register is set to logic one and the following addresses must be written with 00H TBD Reading the following address locations returns the values on the indi
196. roprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 185 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register OXEE RASE SD Accumulation Period Bit Type Function Default Bit7 SDSAP 3 0 Bit6 R W SDSAP 22 Bit5 R W SDSAP 21 BitO R W SDSAP 16 SDSAP 23 0 The SDSAP 23 0 bits represent the number of 8 KHz frames used to accumulate the B2 error subtotal The total evaluation window to declare the SD alarm is broken into 8 subtotals so this register value represents 1 8 of the total sliding window size Refer to the Operations section for recommended settings Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 186 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register OXEF RASE SD Saturation Threshold Bit4 SDSTHI4 Bits R W SDSTH 3 Bit2 R W SDSTH 2 SDSTH 0 Register 0 0 RASE SD Saturation Threshold RW SDSTH 8 SDSTH 11 0 The SDSTH 11 0 value represents the allowable number of B2 errors that can be accumulated during an evaluation window before an SD threshold event is declared Setting this threshold to OXFFF disables the saturation functionality Refer to the
197. rror rate is below the threshold programmed in the RASE SD Clearing Threshold registers SFBERV The SFBERV bit indicates the signal failure threshold crossing alarm state The alarm is declared SFBERV is set high when the bit error rate exceeds the threshold programmed in the RASE SF Declaring Threshold registers The alarm is removed SFBERV is set low when the bit error rate is below the threshold programmed in the RASE SF Clearing Threshold registers SDBERI The SDBERI bit is set high when the signal degrade threshold crossing alarm is declared or removed This bit is cleared when the RASE Interrupt Status register is read Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 176 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD SFBERI The SFBERI bit is set high when the signal failure threshold crossing alarm is declared or removed This bit is cleared when the RASE Interrupt Status register is read 21 511 The 21 511 bit is set high when a new synchronization status message is extracted into the RASE Receive Z1 S1 register This bit is cleared when the RASE Interrupt Status register is read COAPSI The COAPSI bit is set high when a new APS code value is extracted into the RASE Receive K1 and RASE Receive K2 registers This bit is cleared when the RASE Interrupt Status register is read
198. s Internal Use 111 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD ILLJREQE When a logic one is written tot he ILLJREQE interrupt enable bit position an illegal pointer justification request will activate the interrupt output INTB Reserved The reserved bits must be programmed to logic zero for proper operation Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 112 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x35 RPOP Pointer LSB DDD DDD J PTR 7 0 The PTR 7 0 bits contain the eight LSBs of the current pointer value that is interpreted from the H1 and H2 bytes The NDFI NSEI and PSEI bits of the RPOP Pointer Interrupt Status register should be read before and after reading this register to ensure that the pointer value did not change during the register read Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 113 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x36 RPOP Pointer MSB and RDI Filter Control Bit Type Function Default Bit 7 R W NDFPOR 0 PTR 9 8 The PTR 9 8 bits contain the two MSBs of
199. s Internal Use 233 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 18 3 ATM System Interface Timing Table 18 Transmit ATM System Interface Timing Figure 27 Units MHz Symbol Description Min Max Frequency 50 40 60 tHrENB TENB Hold time to TFCLK 0 ns tSTADR TADR 4 0 Set up time to 3 ns tHtapR 4 0 Hold time to 0 ns tStpat TDAT 15 0 Set up time to TFCLK 3 ns 0 15 0 Hold time to ns TPRTY Set up time to TFCLK 3 ns TPRTY Hold time to TFCLK 0 ns TSOC Set up time to TFCLK 3 ns 0 ns TSOC Hold time to TFCLK TFCLK High to DTCA 4 1 Valid 1 12 ns TFCLK High to TCA Valid 1 12 ns 1 10 ns 0 ns tZTCA TFCLK High to TCA Tri state tZBTCA TFCLK High to TCA Driven Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 234 NAC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Figure 27 Transmit ATM System Interface Timing Diagram TFCLK tS tH TFCLK TFCL tS tH TEGE TFCLK tS tH TFCLK TFCLK tH TFCL prcA DTCA x TCA 2 Toa TCA Proprietary and Confidential to PMC Sierra Inc for its Customers Internal Use 235 F2 ra PMC Serta Ie PM5349 S UNI
200. s which are useful for system diagnostics and tester applications ATM cells are written to an internal four cell FIFO using a 16 bit wide Utopia Level 2 datapath interface Idle unassigned cells are automatically inserted when the internal FIFO contains less than one cell The S UNI QUAD provides generation of the header check sequence and scrambles the payload of the ATM cells Each of these transmit ATM cell processing functions can be enabled or bypassed Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 9 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD No line rate clocks are required directly by the S UNI QUAD as it synthesizes the transmit clock and recovers the receive clock using a 19 44 MHz reference clock The S UNI QUAD outputs a differential TTL externally coverted to PECL line data TXD The S UNI QUAD is configured controlled and monitored via a generic 8 bit microprocessor bus interface The S UNI QUAD also provides a standard 5 signal IEEE 1149 1 JTAG test port for boundary scan board test purposes The S UNI QUAD is implemented in low power 3 3 Volt CMOS technology It has TTL and pseudo ECL PECL compatible inputs and TTL CMOS compatible outputs and is packaged in a 304 pin SBGA package Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 10 P
201. s AC couple the outputs so that the ECL inputs are free to swing around the ECL bias voltage The combination of the RS RS1 and ZO resistors divide the voltage down to a nominally 800mV swing The ZO resistors also terminate the signals Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 220 S UNI QUAD ron Aa MC BME siete ING 5349 S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD The RXD inputs to the S UNI QUAD are DC coupled as shown The device has a true PECL receiver so only termination resistors are required Ceramic coupling capacitors are recommended Figure 21 Interfacing to ECL or PECL Optics S UNI QUAD PMD RxD RD C E RD C Zo RxD end Rd V7 Gnd RS1 0 1 uF TD C Zo TxD Zo S20 RS TD Zo TxD VDD VDD 0 01uF or R1 Vdd R2 R1 R2 Vbb R2 V Gnd SD SD Rd Gnd Notes Vpp is minimum input swing required by the optical PMD device Vbb is the switching threshold of the PMD device typically Vdd 1 3 volts Vpp is Voh Vol typically 800 mVolts Vpp Zo RS1 Rs Z0 Vdd Vdd S UNI QUAD s analog transmit power 3 3V Zo trace impedance typically 50Q Rs TxD source impedance typically 15 20Q RS1 1580 For interfacing to 5 0V ODL R1 2379 R2 698Q Rd 3300 For interfacing to 3 3V ODL R1 2200 R2 3300 Rd 1500 Proprietary and Confidential to
202. s bit is reset immediately after a read to this register UHCSI The UHCSI bit is set high when an uncorrected HCS error is detected This bit is reset immediately after a read to this register CHCSI The CHCSI bit is set high when a corrected HCS error is detected This bit is reset immediately after a read to this register OOCDI The OOCDI bit is set high when the RXCP enters or exits the SYNC state The OOCDV bit indicates whether the RXCP is in the SYNC state or The OOCDI bit is reset immediately after a read to this register LCDV The LCDV bit gives the Loss of Cell Delineation state When LCD is logic one an out of cell delineation OCD defect has persisted for the number of cells specified in the LCD Count Threshold register When LCD is logic zero no OCD has persisted for the number of cells specified in the LCD Count Threshold register The cell time period can be varied by using the LCDC 7 0 register bits in the RXCP LCD Count Threshold register Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 140 S UNI QUAD ron Aa MC BME siete ING 5349 S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD OOCDV The OOCDYV bit indicates the cell delineation state When OOCDY is high the cell delineation state machine is in the HUNT or PRESYNC states and is hunting for the cell boundaries When OOCDYV is low the cell delineation s
203. section BIP 8 interrupt status bit BIPEI is set high when a section layer B1 bit error is detected This bit is cleared when this register is read Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 83 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x12 RSOP Section BIP 8 LSB Bit Type Function Default Bi7 R SBEZ xX Bite R SBE X __ Bits R SBE X X 0 Bits R SBE X Bt2 R SBE X Biti R SBE X Bito R SBE X Register 0x13 RSOP Section BIP 8 MSB 265 20 2 R DA Bit Type Function Default Bit7 SBE X Bit6 R SBE 4 X Bits R SBE S 25 DDD Bit4 R SBE j2 X Bits R SBE I X Bt2 R SBE IO X Biti R SBE X D D I Bit 0 SBE 15 0 Bits SBE 15 0 represent the number of section BIP 8 errors individual or block that have been detected since the last time the error count was polled The error count is polled by writing to either of the RSOP Section BIP 8 Register addresses Such a write transfers the internally accumulated error count to the Section BIP 8 registers within approximately 7 us and simultaneously resets the internal counter to begin a new cycle of error accumulation This transfer and reset is c
204. sert path AIS LOPCONPAIS When set high the LOPCONPAIS bit enables path AIS insertion when loss of pointer concatenation LOPCON events are detected in the receive stream When LOPCONPAIS is set low loss of pointer concatenation events have will not assert path AIS PAISCONPAIS When set high the PAISCONPAIS bit enables path AIS insertion when Path AIS concatenation PAISCON events are detected in the receive stream When PAISCONPAIS is set low Path AIS concatenation events will not assert path AIS Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 172 ON AC scs MC PME Sera TR PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x96 S UNI QUAD Channel Receive Alarm Control 1 Function Default LOSEN LOFEN OOFEN LAISEN LRDIEN SDBEREN SFBEREN LOPEN LCDEN PAISEN PRDIEN PERDIEN The above enable bits allow the corresponding alarm indications to be reported Ored into the RALRM output When the enable bit is high the corresponding alarm indication is combined with other alarm indications and output on RALRM When the enable bit is low the corresponding alarm indication does not affect the RALRM output Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 173 rai MC PRE Sierra MMe PM5349 S UNI QUAD S UNI QUAD DATASHEET
205. ssible to blow these ESD protection devices or trigger latch up The recommended power supply sequencing follows 1 To prevent damage to the ESD protection on the device inputs the maximum DOC input current specification must be respected This is accomplished by either ensuring that the VDD power is applied before input pins are driven or by increasing the source impedance of the driver so that the maximum driver short circuit current is less than the maximum DC input current specification 20 mA QAVD power must be supplied either after VDD or simultaneously with VDD to prevent current flow through the ESD protection devices which exist between QAVD and VDD power supplies To prevent forward biasing the ESD protection diode between QAVD supplies and VDD the differential voltage measured between these power supplies must be less than 0 5 volt This recommended differential voltage is to include peak to peak noise on the VDD power supply as digital noise will otherwise be coupled into the analog circuitry Current limiting can be accomplished by using an off chip three terminal voltage regulator supplied by a quiet high voltage supply BIAS voltage must be supplied either before VDD or simultaneously with VDD to prevent current flow through the ESD protection devices which exist between BIAS and VDD power supplies Analog power supplies AVD includes RAVDs TAVDs but not QAVD should be applied after QAVD but can be applied at the same tim
206. t has effect only if the AUTOLRDI register bit is also set to logic one LOSLRDI The Loss of Signal LRDI LOSLRDI controls the insertion of a Line RDI in the transmit data stream upon detection of this alarm condition When LOSLRDI is set to logic one the transmit line RDI will be inserted When LOSLRDI is set to logic zero no action is taken This register bit has effect only if the AUTOLRDI register bit is also set to logic one LOFLRDI The Loss of Frame LRDI LOFLRDI controls the insertion of a Line RDI in the transmit data stream upon detection of this alarm condition When LOFLRDI is set to logic one the transmit line RDI will be inserted When LOFLRDI is set to logic zero no action is taken This register bit has effect only if the AUTOLRDI register bit is also set to logic one SFLRDI The Signal Fail BER LRDI SFLRDI controls the insertion of a Line RDI in the transmit data stream upon detection of this alarm condition When SFLRDI is set to logic one the transmit line RDI will be inserted When SFLRDI is set to Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 163 ON AC scs MC PME Sera TR PM5349 S UNI QUAD PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD S UNI QUAD DATASHEET logic zero no action is taken This register bit has effect only if the AUTOLRDI register bit is also set to logic one SDLRDI The Signal Degrade BER LRDI SDLRDI controls
207. t reference out of lock status indicates the clock synthesis phase locked loop is unable to lock to the reference on REFCLK TROOLV is a logic one if the divided down synthesized clock frequency is not within 488 ppm of the REFCLK frequency TROOLI The TROOLI bit is the transmit reference out of lock interrupt status bit TROOLI is set high when the TROOLV bit of the S UNI QUAD Clock Synthesis Control and Status register changes state TROOLV indicates the clock synthesis phase locked loop is unable to lock to the reference on REFCLK and is a logic one if the divided down synthesized clock frequency is not within 488 ppm of the REFCLK frequency TROOLI is cleared when this register is read Reserved The reserved bits must be programmed to logic zero for proper operation Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 75 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0 00 CSPI Clock Synthesis Reserved Bit O R W Reserved Reserved The reserved bits must be programmed to logic zero for proper operation Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 76 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register OxOE CRSI Clock Recovery C
208. tate machine is in the SYNC state and cells are passed through the receive FIFO Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 141 S UNI QUAD DATASHEET PMC 971239 M di PMC Sierra Inc PM5349 S UNI QUAD ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x65 RXCP LCD Count Threshold MSB Bit Type Function Default Bit7 Unused X Bite X Bits Unused X Bt4 X Bits X Bit2 RW LCDC10 0 Bit 7 Bit 6 5 R W LCDO 5 LCDC 10 0 LCDC 7 LCDC 6 LCDC O0 The LCDC 10 0 bits represent the number of consecutive cell periods the receive cell processor must be out of cell delineation before loss of cell delineation LCD is declared Likewise LCD is not de asserted until receive cell processor is in cell delineation for the number of cell periods specified by LCDC 10 0 The default value of LCD 10 0 is 360 which translates to an average cell period of 2 83 us and a default LCD integration period of 1 02 ms Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 142 S UNI QUAD DATASHEET PMC 971239 ON AC scs MC PME Sera TR PM5349 S UNI QUAD ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x67 RXCP Idle Cell Header Pattern Type R W Function GFC 3 Default Bit6
209. ter Counter bit if in the LOP state 3 x new point resets the inv point count If this bit is set to 0 the inv point count will not be reset if in the LOP state and x new pointers are detected PSL5 The PSL5 bit controls the filtering of the path signal label byte C2 When PSL5 is set high the PSL is updated when the same value is received for 5 consecutive frames When the PSL5 is set low the PSL is updated when the same value is received for 3 consecutive frames Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 102 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x31 EXTD 0 RPOP Interrupt Status Bit Type Function Default R NOTE To facilitate additional register mapping shadow registers have been added to registers 0x30 0x31 and 0x33 These shadow registers are accessed in the same way as the normal registers The EXTD extend register bit must be set in register 0x36 to allow switching between accessing the normal registers and the shadow registers This register allows identification and acknowledgment of path level alarm and error event interrupts FEBEI The FEBEI bit is the path FEBE interrupt status bit FEBEI is a logic one when a FEBE error is detected This bit is cleared when this register is read BIPEI The BIPEI bit is the path BIP 8 interrupt status bit
210. ter is read NSEI The NSEI bit is the negative stuff event interrupt status bit NSEI is a logic one when a negative stuff event is detected in the received pointer H1 H2 This bit is cleared when this register is read ILLPTRI The ILLPTRI bit is the illegal pointer interrupt status bit ILLPTRI is a logic one when an illegal pointer value is detected This bit is cleared when this register is read INVNDFI The INVNDFI bit is the illegal new data field value interrupt status bit INVNDFI is a logic one when an illegal NDF field value is detected in the receive payload pointer An illegal NDF field is any one of the following six values 0 0 0x3 0 5 OxC and OxF This bit is cleared when this register is read Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 106 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD DISCOPAI The DISCOPAI bit is the discontinuous change of pointer interrupt status bit DISCOPAI is a logic one when a new pointer value is validated without an accompanying NDF indication This bit is cleared when this register is read ILLJREQI The ILLJREQI bit is the illegal justification request interrupt status bit ILLUREQI is a logic one when the pointer interpreter detects an illegal pointer justification request event This bit is cleared when this register is read
211. the current pointer value that is interpreted from the H1 and H2 bytes The NDFI NSEI and PSEI bits of the RPOP Pointer Interrupt Status register should be read before and after reading this register to ensure that the pointer value did not change during the register read SO S1 The SO and S1 bits contain the two S bits received in the last H1 byte These bits should be software debounced by reading this register at least twice RDI10 The RDI10 bit controls the filtering of the remote defect indication and the auxiliary remote defect indication When RDI10 is a logic one the PRDI and APRDI status is updated when the same value is received in the corresponding bit of the G1 byte for ten consecutive frames When RDI10 is a logic zero the PRDI and APRDI status is updated when the same value is received for five consecutive frames NDFPOR The NDFPOR new data flag pointer outside range bit allows an NDF counter enable if the pointer value is outside the range 0 782 If this bit is set to logic one the definition for NDF counter enable is enabled NDF ss If this bit is set to logic zero the definition for NDF counter enable is enabled NDF ss offset in the range of 0 to 782 Note that this bit only allows the NDF counter to count towards LOP when the pointer is out of range no active offset change will occur Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 114 F2 MC PMC
212. the insertion of a Line RDI in the transmit data stream upon detection of this alarm condition When SDLRDI is set to logic one the transmit line RDI will be inserted When SDLRDI is set to logic zero no action is taken This register bit has effect only if the AUTOLRDI register bit is also set to logic one Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 164 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD Register 0x91 S UNI QUAD Channel Auto Path RDI Control Bit O R W Reserved This register controls the auto assertion of path RDI G1 bit 5 in the local TPOP Since the S UNI QUAD provides STS 3c STM 1 AU4 mappings this register controls the assertion of path RDI for the entire SONET SDH stream See also the S UNI QUAD Channel Auto Enhanced Path RDI register LOPCONPRDI The Loss of Pointer Concatenation Indication PRDI LOPCONPRDI controls the insertion of a Path RDI in the transmit data stream upon detection of this alarm condition When LOPCONPRDI is set to logic one the transmit line RDI will be inserted When LOPCONPRDI is set to logic zero no action is taken This register bit has effect only if the AUTOPRDI register bit is also set to logic one LOPPRDI The Loss of Pointer PRDI LOPPRDI controls the insertion of a Path RDI in the transmit data stream upon detection of this
213. ting the five I bits of the pointer word The SPE is not inserted during the positive stuff opportunity byte position and the pointer value is incremented by one Positive pointer movements may be inserted once per frame for diagnostic purposes e 4 Negative pointer movements may be generated using a bit in an internal register A negative pointer movement is generated by inverting the five D bits of the pointer word The SPE is inserted during the negative stuff opportunity byte position the H3 byte and the pointer value is decremented by one Negative pointer movements may be inserted once per frame for diagnostic purposes Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 49 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD The pointer value is used to insert the path overhead into the transmit stream The current pointer value may be read via internal registers 10 10 2 BIP 8 Calculate The BIP 8 Calculate Block performs a path bit interleaved parity calculation on the SPE of the transmit stream Details are provided in the references The resulting parity byte is inserted in the path BIP 8 B3 byte position of the subsequent frame BIP 8 errors may be continuously inserted under register control for diagnostic purposes 10 10 3 FEBE Calculate The FEBE Calculate Block accumulates far end block errors
214. tion register The new instruction must be scanned in using the Shift IR state The load occurs on the falling edge of TCK The Pause DR and Pause IR states are provided to allow shifting through the test data and or instruction registers to be momentarily paused Boundary Scan Instructions The following is an description of the standard instructions Each instruction selects an serial test data register path between input TDI and output TDO 13 6 1 2 Instructions BYPASS The bypass instruction shifts data from input TDI to output TDO with one TCK clock period delay The instruction is used to bypass the device EXTEST The external test instruction allows testing of the interconnection to other devices When the current instruction is the EXTEST instruction the boundary scan register is place between input TDI and output TDO Primary device inputs can be sampled by loading the boundary scan register using the Capture DR state The sampled values can then be viewed by shifting the boundary scan register using the Shift DR state Primary device outputs can be controlled by loading patterns shifted in through input TDI into the boundary scan register using the Update DR state SAMPLE The sample instruction samples all the device inputs and outputs For this instruction the boundary scan register is placed between TDI and TDO Primary Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 216 F
215. unction Default Bit 7 Bit 6 Bit 5 Bit 4 R W Reserved Bit 3 Bit 2 Bit 1 Bit 0 R W HCSFTR 0 HCSFTR 1 0 R W R W R W R W R W R W CCDIS HCSPASS IDLEPASS Reserved Reserved HCSFTR 1 0 The HCS filter bits HCSFTR 1 0 indicate the number of consecutive error free cells required while in detection mode before reverting back to correction mode HCSFTR 1 0 Cell Acceptance Threshold 0 One ATM cell with correct HCS before resumption of cell acceptance This cell is accepted 0 01 Two ATM cells with correct HCS before resumption of cell acceptance The last cell is accepted 0 acceptance The last cell is accepted acceptance The last cell is accepted IDLEPASS The IDLEPASS bit controls the function of the Idle Cell filter When IDLEPASS is written with a logic zero all cells that match the Idle Cell Header Pattern and Idle Cell Header Mask are filtered out When IDLEPASS is a logic one the Idle Cell Header Pattern and Mask registers are ignored The default state of this bit and the bits in the Idle Cell Header Mask and Idle Cell Header Pattern Registers enable the dropping of idle cells Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 134 ON AC scs MC PME Sera TR PM5349 S UNI QUAD PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD S UNI QUAD DATASHEET HCSPASS The HCSPASS bit controls the dropping o
216. w for five ten consecutive frames Auxiliary RDI alarm is detected by extracting bit 6 of the path status byte The Auxiliary RDI alarm is indicated when bit 6 is set high for five ten consecutive frames The Auxiliary RDI alarm is removed when bit 6 is low for five ten consecutive frames The Enhanced RDI alarm is detected when the enhanced RDI code in bits 5 6 7 of the path status byte indicates the same error codepoint for five ten consecutive frames The Enhanced RDI alarm is removed when the enhanced RDI code in bits 5 6 7 of the path status byte indicates the same non error codepoint for five ten consecutive frames The ERDII maskable interrupt is set high when bits 5 6 amp 7 of the path status byte G1 byte are set to a new codepoint for five or ten consecutive frames The ERDIV 2 0 signal reflects the state of the filtered ERDI value G1 byte bits 5 6 amp 7 10 6 Receive ATM Cell Processor RXCP The Receive ATM Cell Processor RXCP performs ATM cell delineation provides cell filtering based on idle unassigned cell detection and HCS error detection and performs ATM cell payload de scrambling The RXCP also provides a four cell deep receive FIFO This FIFO is used to separate the STS 3c STM 1 line timing from the higher layer ATM system timing 10 6 1 Cell Delineation Cell Delineation is the process of framing to ATM cell boundaries using the header check sequence HCS field found in the cell header The HCS is a CRC 8 c
217. when both CSB is high and RSTB is low PMCTST PMCATST and BYPASS can also be reset by writing a logic zero to the corresponding register bit HIZIO HIZDATA The HIZIO and HIZDATA bits control the tri state modes of the S UNI QUAD While the HIZIO bit is a logic one all output pins of the S UNI QUAD except the data bus and output TDO are held tri state The microprocessor interface is still active While the HIZDATA bit is a logic one the data bus is also held in a high impedance state which inhibits microprocessor read cycles The HIZDATA bit is overridden by the DBCTRL bit IOTST The IOTST bit is used to allow normal microprocessor access to the test registers and control the test mode in each TSB block in the S UNI QUAD for board level testing When IOTST is a logic one all blocks are held in test mode and the microprocessor may write to a block s test mode 0 registers to manipulate the outputs of the block and consequentially the device outputs refer to the Test Mode 0 Details in the Test Features section Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 194 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD DBCTRL The DBCTRL bit is used to pass control of the data bus drivers to the CSB pin When the DBCTRL bit is set to logic one and either IOTST or PMCTST are logic one the CSB pin cont
218. ycle is defined as a logical OR of the CSB and the WRB signals 2 n non multiplexed address data bus architectures ALE should be held high so parameters 15 tVL tS_w and tH w are not applicable 3 Parameter tHAw is not applicable if address latching is used 4 When a set up time is specified between an input and a clock the set up time is the time in nanoseconds from the 1 4 Volt point of the input to the 1 4 Volt point of the clock 5 When a hold time is specified between an input and a clock the hold time is the time in nanoseconds from the 1 4 Volt point of the input to the 1 4 Volt point of the clock Proprietary and Confidential to PMC Sierra Inc and for its Customers Internal Use 232 F2 MC PMC Serta ING PM5349 S UNI QUAD S UNI QUAD DATASHEET PMC 971239 ISSUE 6 SATURN USER NETWORK INTERFACE 155 QUAD 18 A C TIMING CHARACTERISTICS TA 40 C to 85 Vpp 3 3V 10 18 1 System Reset Timing Table 17 RSTB Timing Figure 26 Symbol Desciplon Mim Max Units Vase RSTBPuseWidh 7 30 mW Figure 26 RSTB Timing Diagram RSTB 18 2 Reference Timing Line Side Reference Clock Symbol Description Min Max Units REFCLK Nominal Frequency 19 44 19 44 MHz REFCLK Duty Cycle 30 70 96 REFCLK Frequency Tolerance 50 50 ppm Proprietary and Confidential to PMC Sierra Inc and for its Customer

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