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Intel 31154 Computer Hardware User Manual

1. Table 2 PCI to PCI Bridge Configurations Primary Bus Interface Secondary Bus Interface PCI 2 3 PCI 2 3 PCI 2 3 PCI X PCI X PCI 2 3 PCI X PCI X The 31154 is used on motherboards to provide additional I O expansion slots It is also used on PCI add in cards to mitigate the restrictive electrical loading constraints imposed on an expansion slot enabling multiple conventional PCI or multiple PCI X devices to reside on a single PCI I O adapter The 31154 block diagram in Figure 1 indicates potential 31154 applications for a range of PCI bus speeds Figure 1 Intel 31154 133 MHz PCI Bridge Applications Legacy Legacy Multi PCI X High End 33 MHz 66 MHz Devices Application CPU Host o 2 e o N x o o 5 m ite O n PCI X Bus 100 MHz Slots PCI X Bus 133 MHz Slot Intel 31154 PCI Bridge B3338 01 Host System Slot PCI X Bus 100 MHz Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Introduction ntel e The 31154 has additional hardware support for CompactPCI Hot Swap and Redundant System Slot via queue flush arbiter lock and clock output tristating The 31154 supports any combination of 32 bit and 64 bit data transfers on its primary and secondary bus interfaces The 31154 is 33 66 MHz capable in conventional PCI mode and can run at 66 MHz 100 MHz or 133 MHz when operating in PCI X mode depending upon its surrounding environment 2 2 Features List Table 3 Features List P
2. 2 The recommended value for pull up resistors for PCI X applications is 8 2 KQ For PCI X the minimum pull up resistor value is 5 KQ as per the PCI X Addendum to the PCI Local Bus Specification Revision 1 0b section 9 7 3 For plug in card implementations the pull up must be on the motherboard 4 Connect PVIO and SVIO pull up resistors to 5 V or 3 3 V power supply through an external resistor 25 Q 5 V or 0 Q 3 3 V depending on the signaling level of the primary secondary PCI bus Refer to the power sequencing guidelines in Section 8 2 on page 58 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 21 Terminations n Table 5 Pull Up Pull Down Terminations Sheet 4 of 9 Signal Pull Up Pull Down or Termination See Note 1 Comments When the internal clock of the 31154 is used pull high to VCC33 through an external 8 2 KQ resistor When an external clock source is used tie to GND through a 330 Q external resistor All secondary S_GCLKOEN clock outputs S CLKO 8 0 and S_BRGCLKO asynchronously tristate When an external clock source is used tie SG CLKOEN 3 0 to a stable value Refer to S CLKOEN 3 0 below These are strapping pins to enable or tristate NOTE This strapping is meaningful only when S CLKO 8 0 after reset S GCLKOEN is pulled high To enable all S CLKO 8 0 pull each When external clocks are used tie S GCLKOEN S CLKOEN 3 0 S CLKOEN 3 0 pin to 3 3 V through an low and tie
3. cc c 11 3 Package Orma NOT E 13 3 1 TASNA COUN ect te rese to eee ve Dette lease yan WAL w n te uu us Poema putt 17 4 Ru ele 19 5 aca sais ices n zz zzzzrzrrza 29 5 1 PCI PCI X Voltage Level S sree a harika n r RAWE NE aa wa HER w a RE k ARA WURA Aa Ewa b a 29 O22 D r E 29 59 IDSEL II e 30 5 9 4 Primary IDSEL De a gt uiri ieee eerie dela ka kun an nand xwr dehek deeded 30 5 89 2 Secondary IDSEL Li nes ince enda de l k aa ed n e a dni 30 5 3 3 Secondary IDSEL Masking 4 x x xxx aaadauadaaa nea elllan denn dk kanika kaza aka nnns 31 5 3 4 Secondary Clock Control 31 5 4 CompactPCl Hot Swap Mode Geet 31 5 5 Opaque Memory Region Enable llLL kk kk EKA kK KA KAKA A AA AK KAK AW ARA 31 5 6 PCI X Initialization Clocking Modes esee eene 32 5 6 1 Primary PCI Clocking Mode ii s llc aa allay n k lana ra aa ke kerda nennen k benn aran 32 5 6 2 Secondary PCI Clocking Mode A 32 5 6 3 Primary to Secondary Frequency Limite 34 6 Routing GUNES xis Tm 35 o Crossa sme c 36 6 2 EMI Considerations y i nan kalan cete ke e e kekan eine E eR d ne Vu h ee ERU nan eee 37 6 3 Power Distribution and Decouplmg eee cece cece ee eeeeeee eee eeeeeeeeeeeaeeeeeeseeeeeeeeseeeeeeeeeeeeeeeees 38 6 3 1 Decoupling Recommendations AA 38 6 4 Trace Impedatice
4. 4 Connect PVIO and SVIO pull up resistors to 5 V or 3 3 V power supply through an external resistor 25 Q 5 V or 0 Q 3 3 V depending on the signaling level of the primary secondary PCI bus Refer to the power sequencing guidelines in Section 8 2 on page 58 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 27 Terminations 28 THIS PAGE INTENTIONALLY LEFT BLANK Intel 31154 133 MHz PCI Bridge Design Guide Design Guide n I ntel amp PCI PCI X Interface PCI PCI X Interface 5 This chapter provides guidelines for designing with the Intel 31154 133 MHz PCI Bridge PCI PCI X bus interface in your application 5 1 PCI PCI X Voltage Levels The Intel 31154 133 MHz PCI Bridge supports the 5 V PCI signaling interface as well as 3 3 V Table 6 is provided as a reference for the PCI PCI X signaling levels A complete PCI X Addendum to the PCI Local Bus Specification Revision 1 0a can be found on the www pcisig com website Table 6 PCI PCI X Voltage Levels Symbol Parameter Minimum Maximum Units Vi 3 Input low voltage PCI X 0 5 0 35 x Vccaa Ving Input high voltage PCI X PCI 0 5 x Vccas Vccas 0 5 V Vita Input low voltage PCI 0 5 0 3 x Vccaa V Vois Output low voltage PCI X 0 1 x Vccaa V Vous Output high voltage PCI X 0 9 x Vccaa V 5 2 Interrupt Routing The 31154 does not use PCI INT lines INTA INTB INTC and INTD These pins are usually routed from the prim
5. Additional crosstalk guidelines include the following Avoid slots in the ground plane Slots increase mutual inductance and thus increase crosstalk Ensure that the ground plane surrounding the connector pin fields is not completely cleared out When the area around the connector pins is completely cleared out all the return current must flow together around the pin field increasing crosstalk The preferred method of laying out a connector in the GND layer is shown in Figure 7 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide intel Figure 7 6 2 Routing Guidelines PCB Ground Layout Around Connectors OQ O O O Lo Ze O lt Connector et G O O O Connector Pins Q O O GND PCB Layer A Incorrect method B Correct method A9260 01 EMI Considerations It is highly recommended that you follow good EMI design practices when designing with the 31154 To minimize EMI on your PCB a useful technique is not to extend the power planes to the edge of the board Another technique is to surround the perimeter of your PCB layers with a GND trace This helps to shield the PCB with grounds minimizing radiation The AP 711 EMI Design Techniques Application Note discusses how to identify and prevent many common EMI problems at the design stage Although the document addresses a range of solutions emphasis is on printed circuit board design methods This document is available at the following
6. Hardware strap 5 Miscellaneous 17 Total 254 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 17 Package Information THIS PAGE INTENTIONALLY LEFT BLANK Intel 31154 133 MHz PCI Bridge Design Guide Design Guide intel Terminations Terminations 4 This chapter details all the recommended Intel 31154 133 MHz PCI Bridge terminations required for the different operating modes The chapter provides the recommended pull up and pull down terminations for a 31154 layout Table 5 lists these 31154 termination values Note that for motherboards the PCI Local Bus Specification Revision 2 3 requires that the PCI signals provide the termination resistors Table 5 Pull Up Pull Down Terminations Sheet 1 of 9 Signal Pull Up Pull Down or Termination See Note 1 Comments PCI Reset P_RST Connect to bus RST signal on primary PCI bus S_RST J to bus RST signal on secondary PCI us Primary PCI Signals P_AD 81 0 Connect to primary PCI bus AD 31 0 For 64 bit primary PCI bus Connect to the AD 63 32 bits of the primary P AD 63 32 PCI bus 7 For 32 bit Primary PCI Bus Pull up through individual external resistors see Note 2 and Note 3 P_CBE 3 0 du to the CBE 3 0 bits of the primary PCI For 64 bit primary PCI bus Connect to the CBE 7 4 bits of the primary P_CBEI7 4 PCI bus 7 For 32 bit primary PCI Bus Pull up t
7. keep the distance between different segments of the same clock line a minimum of 25 mils apart When there are PCI devices and PCI slots in the design an extra 2 5 trace length from connector to PCI device must be considered in calculating clock lengths going to PCI slots When there are PCI slots in the design S BRGCLKO must be 3 longer to compensate for the 2 5 trace length from connector to PCI device and 0 5 for the connector skew on a PCI add in card Intel 31154 133 MHz PCI Bridge Design Guide Design Guide l n 6 PCI X Layout Guidelines R Figure 8 PCI Clock Distribution and Matching Requirements gt Device gt a j 8 Intel 31154 Device 133 MHz PCI Bridge 7 S_CLKO8 Device S CLKO7 33 2 Ohms 6 S_CLKO6 33 2 Ohms A Device 33 2 Ohms S_CLKO4 33 2 Ohms Device 33 2 Ohms 33 2 Ohms 3 S_CLKO1 33 2 Ohms 33 2 Ohms S_BRGCLKO ech 1 S_CLKIN 33 2 Ohms I Notes af oN 9 1 Distance a is the length of the connection from each output clock pin to the closest end of the corresponding series resistor This distance must always be less than 0 5 inch These wirelengths must be matched and must not vary more than 0 1 inch The distance d between two adjacent clock lines must be gt 25 mils The distance between any clock line segment and itself must be gt 25 mils All clock lengths from the series resistor to the device clock input must be matched to within 0 1 inch The clock line le
8. link http developer intel com design auto mcs96 appInots 272673 htm Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 37 Routing Guidelines In 6 3 6 3 1 Table 11 38 Power Distribution and Decoupling Ensure that there is ample decoupling to ground for the power planes to minimize the effects of the switching currents Inadequate high frequency decoupling results in intermittent and unreliable behavior As a general guideline it is recommended that you use the largest easily available capacitor in the lowest inductance package The high speed decoupling capacitor must be placed as close to the pin as possible with a short wide trace Three types of decoupling are described below Bulk capacitor Bulk capacitors consist of electrolytic or tantalum capacitors These capacitors supply large reservoirs of charge but they are useful only at lower frequencies due to lead inductance effects Bulk capacitors can be located anywhere on the board High frequency ceramic capacitor For fast switching currents high frequency low inductance capacitors are most effective Place these capacitors as close to the device being decoupled as possible This placement minimizes the parasitic resistance and inductance associated with board traces and vias Inter plane capacitor Use an inter plane capacitor between power and ground planes to reduce the effective plane impedance at high frequencies The general guideline
9. 1b is sampled after the trailing edge of P_RST the internal secondary bus arbiter of the 31154 locks and provide grant only to itself NOTE S_ARB_LOCK has an effect only when the internal arbiter is enabled S_MAX100 To limit secondary bus frequency to maximum of 100 MHz Pull high to 3 3 V through an external 8 2 KQ resistor Otherwise Pull low to GND through an external 330 Q resistor default S TRISTATE GND during normal operation NOTES 1 The recommended value for pull up resistors for PCI applications is 5 6 KQ note that the minimum value for PCI 3 3 V signaling Ryn 2 42 KO Rryp 8 2 KO as per the PCI Local Bus Specification Revision 2 3 section 4 3 3 2 The recommended value for pull up resistors for PCI X applications is 8 2 KQ For PCI X the minimum pull up resistor value is 5 KQ as per the PCI X Addendum to the PCI Local Bus Specification Revision 1 0b section 9 7 3 For plug in card implementations the pull up must be on the motherboard 4 Connect PVIO and SVIO pull up resistors to 5 V or 3 3 V power supply through an external resistor 25 Q 5 V or 0 Q 3 3 V depending on the signaling level of the primary secondary PCI bus Refer to the power sequencing guidelines in Section 8 2 on page 58 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Terminations Table 5 Pull Up Pull Down Terminations Sheet 6 of 9 Signal Pull Up Pull Down or Te
10. AD47 10 14 AD46 e 13 AD45 14 12 AD44 16 11 AD43 18 10 AD42 20 9 AD41 22 8 AD40 24 7 AD39 26 6 AD38 28 5 AD37 30 4 AD36 32 3 AD35 34 2 AD34 36 1 AD33 38 0 AD32 66 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide n Debug Connectors and Logic Analyzer Connectivity Table 28 Logic Analyzer Pod 6 Mictor 38 Pin Number Even Pod Logic Analyzer Channel Number PCI X Signal Name 5 CLK 16 Unused 7 15 AD63 9 14 AD62 11 13 AD60 13 12 AD59 15 11 AD58 17 10 AD57 19 9 AD56 21 8 AD55 23 7 AD54 25 6 AD53 27 5 AD52 29 4 AD51 31 3 AD50 33 2 AD49 35 1 AD48 37 0 AD48 The recommended placement of the Mictor connectors is at either end of the bus segment The Mictors are placed at the end of a stub that must be as short as possible and are then daisy chained off either end of the bus When there is not enough room to place the Mictors at least 0 5 from the target an alternate method can be used This alternate method is to place the logic analyzer termination circuitry on the target and then extend the etch from the end of the termination circuitry over to the Mictor connectors The connection from the Mictors to the logic analyzer must then be made with the E5351A The E5346A contains the logic analyzer termination circuitry and the E5351A does not Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 67 n Debug Connectors an
11. Handbook of Black Magic Prentice Hall Professional Technical Reference 1993 PCI Bus Power Management Interface Specification Revision 1 1 PCI Special Interest Group Steve Kaufer and Kelee Crisafulli Terminating Differential Signals on PCBs Printed Circuit Design magazine March 1999 Table 30 lists Intel documentation that is helpful for designing with the Intel 31154 133 MHz PCI Bridge This documentation can be found at the Intel website at http www ntel com design bridge docs 31154 documentation htm Table 31 Intel Related Documentation Document Title pee Intef Packaging Databook http www intel com design packtech packbook htm 240800 Inte 31154 133 MHz PCI Bridge Evaluation Board Schematics 278839 Inte 31154 133 MHz PCI Bridge Product Brief 252974 Inte 31154 133 MHz PCI Bridge Datasheet 278821 Inte 31154 133 MHz PCI Bridge Developer s Manual 278848 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 71 References 72 THIS PAGE INTENTIONALLY LEFT BLANK Intel 31154 133 MHz PCI Bridge Design Guide Design Guide
12. PCI Bus Power Management Interface Specification Revision 1 1 Compact PCI Hot Swap Specification Revision 2 1 R2 0 PCI X Addendum to the PCI Local Bus Specification Revision 1 1 Embedded PCI X Specification PICMG 1 2 R1 0 2 4 References This section lists references that can be useful with a 31154 application These documents are available on the Intel Developer website http developer intel com Intel 31154 133 MHz PCI Bridge Datasheet 278821 Intel 31154 133 MHz PCI Bridge Developer s Manual 278848 Intel 31154 133 MHz PCI Bridge Specification Update 300826 Intel 31154 133 MHz PCI Bridge Design Checklist 300959 Intel 31154 133 MHz PCI Bridge Evaluation Board Schematics 278839 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 11 Introduction THIS PAGE INTENTIONALLY LEFT BLANK Intel 31154 133 MHz PCI Bridge Design Guide Design Guide n I ntel Package Information Package Information 3 The Intel 31154 133 MHz PCI Bridge is offered in a 421 lead PBGA package The mechanical dimensions for this package are provided in Figure 2 on page 14 Figure 3 on page 15 and Figure 4 on page 16 show the 421 lead PBGA mapped by pin function These figures are helpful in placing components around the 31154 for the layout of a PCB To simplify routing and minimize the number of cross traces keep this layout in mind when placing components on your board The signals by design are lo
13. applications with the Intel 31154 133 MHz PCI Bridge This document is intended to be used as a guideline only Intel recommends that you employ best known design practices with board level simulation signal integrity testing and validation for a robust design Please note that this design guide focuses on specific design considerations for the 31154 Bridge and is not intended to be an all inclusive list of all good design practices Use this guide as a starting point and use empirical data to optimize your particular design 1 1 Terminology and Definitions Table 1 Terminology and Definition Sheet 1 of 2 Term Definition 31154 Intel 31154 133 MHz PCI Bridge Stripline in a PCB is composed of the conductor inserted in a dielectric with GND planes to the top and bottom as shown in the cross section diagram at left Stripline ER T NOTE An easy way to distinguish stripline from microstrip is that you need to strip away layers of the board to view the trace on stripline HA Microstrip in a PCB is composed of the conductor on the top layer above the Microstrip dielectric with a ground plane below as shown in the cross section diagram at left Prepreg is material used for the lamination process of manufacturing PCBs It consists of a Prepreg layer of epoxy material that is placed between two cores This layer melts into epoxy when heated and forms around adjacent traces Core material is used for
14. are met Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Intel 5 3 3 5 3 4 5 4 Table 7 5 5 PCI PCI X Interface Secondary IDSEL Masking The 31154 supports private devices through the use of IDSEL masking When the IDSEL_MASK pin is sampled as 1b on the trailing edge of P_RST the default value for the Secondary IDSEL Select Register SISR is 001Fh to mask devices 0 4 refer to the Intel 31154 133 MHz PCI Bridge Developer s Manual for more information Secondary Clock Control The 31154 can disable its secondary clock outputs individually or globally The straps S CLKOEN 3 0 determine the number of S CLKO 8 0 outputs that are enabled The S BRCLKO output is dedicated for the bridge feedback clock and cannot be individually disabled When the global clock output enable 5 GCLKOEN is sampled as Ob all secondary clock outputs are disabled and an external clock source is required The 31154 Bridge still drives the PCI X initialization pattern so any external clock source must be consistent with the clock generation scheme of the bridge as defined in Table 9 Secondary Bus Frequency Initialization on page 33 CompactPCI Hot Swap Mode Select Hot Swap Mode Select HS SM must be asserted 1b to enable hot swap functionality HS_FREQ 1 0 pins allow the bridge to determine the cPCI backplane operating frequency on its primary interface without needing to see a PCI X initialization pattern These
15. asserted NT MASK When forced retirement of the 31154 internal NT_MASK must not be reasserted until the request queues and data buffer is desired in QE pin is cleared the application this pin must be connected to Setting the New Transaction Mask bit to 1b in external logic or using the GPIO of the 31154 VCRO has the same effect as asserting that drives this pin low when masking new NT MASK amp t transactions is desired Connection depends on application This is an NOTE The state of this output is valid only when output signal that indicates the state of the 31154 the NT MASK t pin is asserted QE internal request and data queues When high this signal indicates that the 31154 internal queues are completely empty SCAN EN For normal operation tie low to GND For normal operation tie to 0000 or 0111 TMODEIJI3 0 0 Pull low to GND 3 0 1 Pull high to 3 3 V through an external 8 2 KO resistor NOTES 1 The recommended value for pull up resistors for PCI applications is 5 6 KQ note that the minimum value for PCI 3 3 V signaling Ryun 2 42 KO Rryp 8 2 KO as per the PCI Local Bus Specification Revision 2 3 section 4 3 3 2 The recommended value for pull up resistors for PCI X applications is 8 2 KO For PCI X the minimum pull up resistor value is 5 KQ as per the PCI X Addendum to the PCI Local Bus Specification Revision 1 0b section 9 7 3 For plug in card implementations the pull up must be on the motherboard
16. both backward and forward crosstalk components Backward crosstalk creates an induced signal on a victim network that propagates in the opposite direction of the aggressor signal Forward crosstalk creates a signal that propagates in the same direction as the aggressor signal Circuit board analysis software is used to analyze your board layout for crosstalk problems Examples of 2D analysis tools include Ansoft Parasitic Parameters and Quad Design XFS Crosstalk problems occur when circuit etch lines run in parallel When board analysis software is not available the layout must be designed to maintain at least the minimum recommended spacing for bus interfaces Asa general guideline the distance between adjacent signals must be a least 3 3 times the distance from signal trace to the nearest return plane The coupled noise between adjacent traces decreases by the square of the distance between the adjacent traces tis also recommended that you specify the height of the above referenced plane when laying out traces and that you provide this parameter to the PCB manufacturer By moving traces closer to the nearest reference plane the coupled noise decreases by the square of the distance to the reference plane These design guidelines are illustrated in Figure 5 Crosstalk Effects on Trace Distance and Height EREN EE Maximize P H aggressor victim Reduce Crosstalk Reference Plane Minimize H A9259 01
17. can be disabled by strapping the S_CLKOEN 3 0 during reset When the internal clock of the 31154 is used All S CLKO 8 0 and S BRGCLKO must connect to the PCI clock input of the secondary match in length S CLKO 8 0 PCI devices through a 33 2 Q series resistor For asynchronous mode there is no maximum Each clock can be connected to only one PCI skew between P CLK and S CLKI device NOTE These clocks can be disabled by strapping the S CLKOEN S 0 during reset When using the internal clock refer to S BRGCLKO above for additional information When the internal clock of the 31154 is used When using an external clock source all S CLKI connect to 5 BRGCLKO secondary clocks must have matching length When an external clock is used connect to external clock source When using PCI slots in the design S BRGCLKO must be 3 longer to compensate for the 2 5 trace length from the connector to the PCI device on a PCI add in card S CLKSTABLE When the internal clock of the 31154 is used S_CLKSTABLE must be tied high to VCC33 through an external 8 2 KQ resistor When an external clock source is used connect to logic that outputs high after the secondary clocks are stable NOTES 1 The recommended value for pull up resistors for PCI applications is 5 6 KQ note that the minimum value for PCI 3 3 V signaling Rym 2 42 KO Rryp 8 2 KQ as per the PCI Local Bus Specification Revision 2 3 section 4 3 3
18. eere ad eren eere ride Pe E ede ten 2x xm agggm 39 7 ae SE VOniee rccee c 41 7 1 PCI Clock Layout Guidelines eeseseisesesesseseeeeeeseeeene nennen nnne nnne nennen 42 7 2 PCI X Topology Layout Guidelines eese nnne 44 7 24 single Slotat 133 MHZ Ai eiecit kk behay ae n Ese sack a Eos pde k e PA sneer rent 45 7 2 1 1 Intel 31154 133 MHz PCI Bridge Embedded Application at 133 MHz 46 7 2 2 JBDualSlotat 100 MHZ crm ten sot cu c dne sov do se cL a EEN 47 7 2 2 1 Embedded Intel 31154 133 MHz PCI Bridge Application at 100 MHz 48 723 Quad Slots at 66 MHZ iue oe an na i Ene Gd oue onu E bn Kin n W n n ER ny E Vae 49 7 2 3 1 Embedded Intel 31154 133 MHz PCI Bridge Application at 66 MHz 51 724 Re bC Krg oed ommnmnmnanDnIuID WD m_ 52 7 2 4 1 Embedded PCI X Specification PICMG 1 2 Overview 52 Intel 31154 133 MHz PCI Bridge Design Guide 3 Contents ntel S 7 2 4 2 PICMG 1 2 System Overview seessssseene nennen 52 8 Power consid D te E 57 8 1 Analog Power PIS erret ete natn nea kan akan kuneke Le Pb n cua EX xendan ake 57 8 2 ee Ee DE 58 9 Customer Reference BO Id edere roc teo re e tute k anl kedi han te Hu nex Ra Habt Eu 59 10 Debug Connectors and Logic Analyzer Connectivity sseeeeeneen 61 10 1 Probing FOLA S
19. elo ki e kana a du R dece cns 44 Wiring Lengths for 133 MHZ lot 45 Wiring Lengths for Embedded 133 MHz Deson kk kk kk kk A KAK K AA 46 Wiring Lengths for 100 MHz Dual Slot EEE kaka kk kk kA AA AK nennen 47 Wiring Lengths for Embedded 100 MHZ Deson kk kk kk KEK kk AKA KAK KA 48 Wiring Lengths for 66 MHz Ouad lot 49 Wiring Lengths for Embedded 66 MHZ Design 51 Wiring Lengths for PICMG 1 2 Backplane iiiiE Ek eene nnnm 54 PCI X Clock Wiring Lengths for PICMG Backplane see 55 Customer Reference Board Stackup iiu Ek aka EKA Ak KAKA AK KAK AA AA AA AA kk AA 60 Logic Analyzer Pod NEE 62 Logic El e sr my 63 Logic Analyzer POQ S siy Aalnakiyy ansa derdan d kad x n r n NR Leetaru 64 Logic NENT Pod EE 65 Logic Analyzer Pod 5 cas yay da wila y ak K Y AE di yalla Weya asa see a a nea ed 66 Logit Analyzer Fod treten atl ened ae eee as eee ee 67 Operational Power iden lan WA i ka AM Be Leu De ue e p De e ERE eue Du dene 69 Design Reference Material ANEN 71 Intel Related Documentation AANEREN 71 Intel 31154 133 MHz PCI Bridge Design Guide 5 Contents Revision History Date Revision Description April 2004 001 Initial release Intel 31154 133 MHz PCI Bridge Design Guide n l ntel About This Document About This Document 1 This document provides layout information and guidelines for designing platform or add in board
20. iret pee tek kek Emir ERR ERE ER nn DEZ RM ne Duda 53 16 PCI X Data Bus PICMG 1 2 Style Backpolane nennen 54 17 PCI X Clock PICMG 1 2 Style Backplane sessi iranin anii nnna AKN 55 18 CR MES NulpmE mn 57 19S VOCA ll 57 20 PVIO Voltage Protection Diode nun 58 21 Intel 1Q31154 Customer Reference Board Block Diagram 59 Tables 1 Terminology and Definition ssssesesesssssseeseeeeseeeee ka a nnne dena ne dirbek nennen nen BER RA RA ENA 7 2 PCkto PCI Bridge Configurations sess eene nnne nnns 9 TAN J m 10 4 Total Signal e 17 5 Pull Up Pull Down Terminations enn eee kaya kan kana V K klan bin k se w WD n kan E V nA kaw na K RA 19 6 PCI PCI X Voltage Levels AANEREN 29 Z7 HS FREQ Encoding K xi 2l sinan 31 8 PCI X Clocking Modes ne rere ele hide eee aint ENEE wg wa w Ue dt A ane 33 4 Intel 31154 133 MHz PCI Bridge Design Guide ntel Contents Secondary Bus Frequency Iomttalzaton EEE kk kek kk nnns 33 PCI X Initialization PARE asninn ayan ka y Ee200k k M40 20knk Hata n ke v ca Z ka ARO VA A nnn trennen H e VAKA 34 Intel 31154 133 MHz PCI Bridge Decoupling Recommendations sssis11ssersiisereiiereerrees 38 Add in Card Routing Parameters EEE kk kk KAK enne nennen nene 41 PCI X Slot Guidelines 4440 44 2 idees ecc acd a Sk
21. length of P CLK for an add in card is 2 4 2 6 Total length of P CLK in non add in card design is less than 8 A typical PCI X application requires separate clock point to point connections distributed to each PCI device The 31154 clock buffer also provides secondary clock fanout of up to nine PCI X devices Figure 8 PCI Clock Distribution and Matching Requirements on page 43 shows the use of eight secondary clocks going to individual PCI X devices with S BRGCLKO fed back into S CLKIN The recommended clock buffer layout is specified as follows refer to Figure 8 1 The distance between each series resistor and S_CLKO output clock buffer must be less than 0 5 The segment length from secondary output clock buffer S_CLKO to the end of the series resistor must be matched less than 0 1 You must match the end of series resistor to the device clock input to less than 0 1 to help keep the timing within the 0 5 ns maximum budget You must match the length of S BRGCLKO to the series resistor to less than 0 1 to all the other resistor secondary clock segment lengths listed in item 2 above Match the length of the other end of the series resistor to S_CLKIN to all the other secondary clock segments lengths labelled in Figure 8 on page 43 as segment length b Keep the distance between the clock lines and other signals d at least 25 mils from each other When using a serpentine clock layout
22. pins are valid only when HS SM is sampled as 1b during P_RST HS FREQ Encoding HS FREQ 1 0 P M66EN Operating Mode Bus Frequency 00 0 PCI 33 MHz 00 1 PCI 66 MHz 01 PCI X 66 MHz 10 PCI X 100 MHz 11 _ PCI X 133 MHz Opaque Memory Region Enable The 31154 supports an opaque memory region to enable private memory space for secondary devices When OPAQUE_EN is sampled as 1b at the trailing edge of P_RST the Opaque Memory Enable bit in the VCR2 Bridge Control Register 2 is set The default base and limit reserve the upper half of memory AD 63 1 for the private memory region Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 31 n PCI PCI X Interface ntel 5 6 5 6 1 5 6 2 32 PCI X Initialization Clocking Modes Both of the PCI bus interfaces can operate at a variety of frequencies and in either conventional PCI mode or in PCI X mode Each interface establishes the bus mode and frequency when coming out of its corresponding bus segment reset sequence The resultant mode and frequency is dependent upon the device capabilities reported in addition to any system specific loading information Primary PCI Clocking Mode The 31154 reports its primary bus operating capabilities to the originating device typically the host bridge of the primary bus segments The 31154 indicates to the originating device of the primary bus segments that its primary interface is PCI X
23. reference Figure 14 Embedded Intel 31154 133 MHz PCI Bridge Wiring for 66 MHz gt lt lt PCI Agent 1 UO Buffer IDSEL gt PCI Agent 2 lt PCI Agent 3 we 4 PCI Agent 4 B3247 01 Table 19 Wiring Lengths for Embedded 66 MHz Design Lower AD Bus Upper AD Bus Segment Units Minimum Length Maximum Length Minimum Length Maximum Length Wi 5 7 5 7 inches W2 0 75 1 5 1 75 2 75 inches W3 0 1 0 1 inches WA 1 725 1 725 _ inches W5 1 1 1 1 inches W6 0 75 1 5 1 75 2 75 inches W7 1 1 1 1 inches W 0 75 1 5 1 75 2 75 inches wo 1 1 1 1 inches W10 0 75 1 5 1 75 2 75 inches Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 51 n PCI X Layout Guidelines ntel E 7 2 4 7 2 4 1 7 2 4 2 52 PCI X at 33 MHz The 31154 supports running in an eight slot PICMG 1 2 style passive backplane environment at 33 MHz To verify this simulations were run based on the trace impedance of 57 Q 10 Embedded PCI X Specification PICMG 1 2 Overview The Embedded PCI X ePCI X Specification PICMG 1 2 is a specification supported by the PCI Industrial Computer Manufacturers Group ePCI X system host boards SHBs are defined in two form factors full size and half size The full size SHB length is identical to the ISA long board length Half size SHB form factor is based on the popular half size ISA board PICMG 1 2 System Overview An ePCI X syst
24. the IDSEL signal of the PCI edge RUM IDSEL Linea on page S0 Tor connector for add in card applications Connect to the M66EN signal of the primary PCI E MB6EN bus of the PCI add in card finger P_PAR Connect to PAR of the primary PCI bus P PAR64 Connect to PERR of the primary PCI bus P_PERR Connect to PERR of the primary PCI bus Connect to one of the PCI bus request signals of DAREK the primary PCI bus P_SERR Connect to SERR of the primary PCI bus Secondary PCI Signals Pull up to VCC33 through external 8 2 KQ S_REQ0 BR_GNT S_GNT0 BR_REQ S_AD 63 32 resistors Pull up to VCC33 through external 8 2 KQ S_CBE 7 4 dela j Pull up to VCC33 through external 8 2 KQ S_REQ64 resistors Pull up to VCC33 through external 8 2 KQ S AUKDAE resistors S_FRAME S_IRDY SEA Pull up to VCC33 voltage through external 8 2 KO S DEVSEL resistors S_PERR S_SERR S REQ 8 1 Pull up to VCC33 voltage through external 8 2 KQ resistors Pull up for both internal and external arbiter mode Secondary GNT S_GNT1 S_GNT2 S_GNT3 S_GNT4 S_GNT5 S_GNT6 S_GNT7 S GNT8 Connect to GNT input of the PCI devices on the secondary PCI bus NC when not used NOTES 1 The recommended value for pull up resistors for PCI applications is 5 6 KO note that the minimum value for PCI 3 3 V signaling Rmn 2 42 KO Rryp 8 2 KO as per the PCI Local Bus Sp
25. the lamination process of manufacturing PCBs This material is two Core sided laminate with copper on each side The core is an internal layer that is etched Printed circuit board An example PCB ___ 4 beye 1 copper manufacturing process consists of the repreg Lauer 2 GND following steps l l A PCB consists of alternating layers of Core core and prepreg stacked The finished PCB is heated and cured PCB Layer 3 Voc Prepreg The via holes are drilled WENN siayer 4 copper Plating covers holes and outer surfaces Etching removes unwanted copper Example of a cross section of The PCB is tinned coated with solder a four layer stack mask and silk screened Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 7 About This Document Table 1 Intel Terminology and Definition Sheet 2 of 2 Term Definition An aggressor network is a network that transmits a coupled signal to another network Zo Zo Aggressor Victim Network Zo Zo Aggressor Network B3337 01 Victi A network that receives a coupled cross talk signal from another network is a called the victim ictim network Network A network is the trace of a PCB that completes an electrical connection between two or more components Stub A stub is a branch from a trunk terminating at the pad of an agent Inter Symbol Interference ISI occurs when a transition that ha
26. 0 0 10 22 10 REF 26 00 0 20 Y oza 3 X 1 00 THRU 22 10 REF 45 CHAMFER 4 PLACES GU ALES p Ee z Pd kk xf PIN 1 CORNER TOP VIEW NO RADIUS Au GATE 2 38 0 21 yt 1 17 0 05 PIN 1 LD SHINY 1 0 DIA X 0 15 DEPTH 30 0 15 C K T 9 0 X 9 0 FROM CENTER LINE EE Blots T Ka E un SIDE VIEW SEATING PLANE DETAIL NOT TO SCALE B1290 01 14 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide n Figure 3 Intel 31154 133 MHz PCI Bridge Ball Map Top View Left Side Package Information 2 3 4 5 6 7 8 9 10 P P CBE7 vow PAR GA ves P P ps E gt AD57 AD59 AD52 AD55 11 12 vss EV ES ES AD63 CBE6 lee Ne le le Cc ADS3 PERR AD58 AD61 CBES REQ64 D NEE vss Yeo ves P ru uS HS_ E LED isrAT ENUM VSS FREQO OUT F Ves e vss ENG G H K M N P R U v o EET ec Veo vss Y AD46 GNT24 AD56 ADS EK s EO s s s s s s s ls AA REQI 2 apss AD59 AD61 ACK64 ADOO PARG4 CBE5 ADO6 AB vss eee Se NEWE ae es amy REQ3 GNT4 REQ4 AD60 AD62 AD63 ADO1 CBE6 ADO4 CBEO S S S REQS GNT5 GNT3 1 2 3 4 5 6 7 8 9 S S ves CBE4 ADO2 VCCP VSS VSS AC 10 ca ADO3 Men 11 12 B2240
27. 01 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 15 Package Information n Figure 4 Intel 31154 133 MHz PCI Bridge Ball Map Top View Right Side 13 14 15 16 17 18 19 20 21 22 23 P_ g re le p ep ENS CBEO cl CBE IRDY FER ou ADO7 oe BAW A ele dle IRCH le Te Te Tes ADOO ADO2 TRDY ADOS ADos CBE1 IDSEL ADI5S REQ ee OO B P II JE WE JU E abot app AD06 AD09 PAR anio GNT ed 2 C Wess hl US SEI AD11 D E F G H a amp CLKOO CLKO2 J s Te ts ME CLKO1 odios s K vss vss 5 Vcc L CLKO3 S_ CLKOS iai M sU ER N s BRG s s P CLKO cLKo7 AD26 s Is M66EN CLKOs oe R vcc vcc D IT U vcc L V veo vss BSS REQ8 0 Ww Veo RB Vee vss 52 ioc veces vss TRDY AD11 Y aitaeatltaleale AD07 FRAME CBE3 AD10 PAR AA aleafleleafselseleales REQ644 CBE2 ADO9 CBE1 PERR AD12 SERR AB s_ S SH NETTE Se ooo vss ov AC 13 14 15 16 17 18 19 20 21 22 23 B2241 01 16 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide n I ntel Package Information 3 1 Total Signal Count Table 4 Total Signal Count Interface Signals PCI bus interface 112 PCI 64 bit extensions 78 Clock and reset 20 JTAG 12 Serial ROM interface 4 CompactPCI Hot Swap 6
28. 1 13 C BE2 13 12 C BE3 15 11 IDSEL 17 10 REQ 19 9 GNT 21 8 INTD 23 7 INTC 25 6 INTB 27 5 INTA 29 4 UNUSED 31 3 UNUSED 33 2 UNUSED 35 1 UNUSED 37 0 UNUSED Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 63 Debug Connectors and Logic Analyzer Connectivity n Table 25 Logic Analyzer Pod 3 Mictor 38 2 Pin Number Odd Pod Logic Analyzer Channel Number PCI X Signal Name 6 CLK 16 IRDY 8 15 AD15 10 14 AD14 12 13 AD13 14 12 AD12 16 11 AD11 18 10 AD10 20 9 ADO9 22 8 ADO8 24 7 ADO7 26 6 AD06 28 5 ADO05 30 4 AD04 32 3 ADO3 34 2 AD02 36 1 ADO01 38 0 ADOO 64 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide n Debug Connectors and Logic Analyzer Connectivity Table 26 Logic Analyzer Pod 4 Mictor 38 2 Pin Number Odd Pod Logic Analyzer Channel Number PCI X Signal Name 5 CLK 16 UNUSED 7 15 AD31 9 14 AD30 11 13 AD29 13 12 AD28 15 11 AD27 17 10 AD26 19 9 AD25 21 8 AD24 23 7 AD23 25 6 AD22 27 5 AD21 29 4 AD20 31 3 AD19 33 2 AD18 35 1 AD17 37 0 AD16 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 65 Debug Connectors and Logic Analyzer Connectivity n Table 27 Logic Analyzer Pod 5 Mictor 38 3 Pin Number Odd Pod Logic Analyzer Channel Number PCI X Signal Name 6 CLK 16 PAR64 8 15
29. 154 signals on its secondary bus when coming out of S_RST after having evaluated the above information PCI X Initialization Pattern Clock Period Clock Frequency DEVSEL STOP TRDY Mode Ns MHz Max Min Min Max PCI 33 62 5 30 62 5 33 Deasserted Deasserted Deasserted PCI 66 30 15 33 66 Deasserted Deasserted Asserted PCI X 20 15 50 66 Deasserted Asserted Deasserted PCI X 15 10 66 100 Deasserted Asserted Asserted PCI X 10 7 5 100 133 Asserted Deasserted Deasserted PCI X Asserted Deasserted Asserted PCI X Reserved Asserted Asserted Deasserted PCI X Asserted Asserted Asserted PCI X NOTE 1 When the internal PLLs are operational the minimum input frequency is 16 MHz See Section 5 6 3 Primary to Secondary Frequency Limits on page 34 for more information Primary to Secondary Frequency Limits When operating in PCI 33 MHz mode the bridge bypasses the PLL to allow the full range of 0 33 MHz operations defined in the PCI specifications However the PLL is used to generate the secondary clock outputs when the secondary side is operating at a frequency greater than 33 MHz PCI 66 MHz or PCI X The primary clock input must operate above 25 MHz to ensure that the secondary frequencies are within the ranges defined in the PCI specifications When both the primary and secondary sides are operating in PCI 33 MHz mode then the secondary cloc
30. CI Agent 1 2 UO Buffer e W16 CG n Ca Wen Ca Slot 1 gt v W23 CO GENE Gm Leesch 3 PCI Agent 2 QO S Slot 2 v W33 CG eha S PCI Agent 3 3 Q Q Slot 3 W43 a gt HH Q 3 PCI Agent 4 o 9 9 Slot 4 B3060 01 Wiring Lengths for 66 MHz Quad Slot Sheet 1 of 2 Lower AD Bus Upper AD Bus Segment Minimum Maximum Minimum Maximum ante Length Length Length Length WI 5 7 2 5 7 inches W13 0 75 1 5 1 75 2 75 inches W14 0 1 0 1 inches Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 49 PCI X Layout Guidelines n Table 18 Wiring Lengths for 66 MHz Quad Slot Sheet 2 of 2 Lower AD Bus Upper AD Bus Segment Minimum Maximum Minimum Maximum nite Length Length Length Length W15 0 6 0 6 inches W16 1 125 1 125 B inches w21 0 8 1 2 0 8 1 2 inches W22 0 1 0 5 0 1 0 5 inches W23 0 75 1 5 1 75 2 75 inches W32 0 1 0 5 0 1 0 5 inches W33 0 75 1 5 1 75 2 75 inches W42 0 1 0 5 0 1 0 5 inches W43 0 75 1 5 1 75 2 75 inches 50 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide n l ntel PCI X Layout Guidelines 7 2 3 1 Embedded Intel 31154 133 MHz PCI Bridge Application at 66 MHz Figure 14 shows an 31154 in a stand alone embedded application In this application the 31154 is shown driving four loads Additional loads might be possible with careful simulation Table 19 shows the corresponding wiring lengths to use as a
31. CI bus interfaces 2 Secondary bus arbitration PCI Local Bus Specification Internal arbiter supports nine agents in Revision 2 3 compliant addition to the 31154 PCI to PCI Bridge Architecture Internal arbiter can be disabled Specification Revision 1 2 compliant Optinized for PCLX mode PCI Bus Power Management Interface Specification Revision 1 1 Bus parking on bridge or last miaster compliant Improved buffer architecture PCI X Addendum to the PCI Local 8 KBytes data buffers in each Bus Specification Revision 1 0b direction compliant Improved level of concurrency External SROM support Up to nine outstanding transactions on Vital Products Data VPD support each bus simultaneously 64 bit initiator target capable Scalability and flexibility 64 bit addressing Conventional PCI 32 64 bit 33 66 MHz 3 3 V Hardware support for dual host cPCI configurations 5 V tolerant inputs Compact PCI Hot Swap Specification PCI X 32 64 bit 66 100 133 MHz Revision 2 1 R2 0 support 3 3 V Secondary clock generation with 10 clock JTAG interface ld GPIO interface Allows simple software controlled signaling protocols 10 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide ntel e Introduction 2 3 Related External Specifications PCI Local Bus Specification Revision 2 3 PCI to PCI Bridge Architecture Specification Revision 1 1
32. IQ EE 61 11 Thermal Solutions cT 69 DAMES Ic ze 71 12 1 Related Docurrents uiii yan a h ka c rea KAWA rada ner k anda pu ena ked k w Adak a da kade 71 Figures 1 Intel 31154 133 MHz PCI Bridge Applicatiors utto tete ket kelan Sana Pit edhe 9 2 Intel 31154 133 MHz PCI Bridge Package sesssseeiseeeeissrirsrriessritestresrrrsrrrerrrtssrressrressrrtas 14 3 Intel 31154 133 MHz PCI Bridge Ball Map Top View Left Side seesesssssss 15 4 Intel 31154 133 MHz PCI Bridge Ball Map Top View Right Gde 16 b ID SEL Mapping NEE 30 6 Crosstalk Effects on Trace Distance and Height seen 36 7 PCB Ground Layout Around Connectors essen enne kla kan Ana 37 8 PCI Clock Distribution and Matching Heourements 43 9 Single Slot Point to Point Topology x 44xx k1 kananka knanan lak nadan kk yek ak k kak k la ak yA kal dk kk Waw 45 10 Embedded Intel 31154 133 MHz PCI Bridge Design 133 MHz PCI X Layou 46 11 Dual Slot CODfIGUEallOF uccide rate iet etichette cnt d l An een put E kun a AA 47 12 Embedded Intel 31154 133 MHz PCI Bridge Design 100 MHz PCI X Layout 48 13 Quad Slots 66 MHz Topology 5 i4 a21aasyia an lan yab saa k na i ka ben klan arav Ann ian n WAA Wan L nsns 49 14 Embedded Intel 31154 133 MHz PCI Bridge Wiring for 66 MHz 51 15 An Example of am ePOI X System uoce
33. Intel 31154 133 MHz PCI Bridge Design Guide Design Guide April 2004 Order Number 278944 001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel Corporation may have patents or pending patent applications trademarks copyrights or other intellectual property rights that relate to the presented subject matter The furnishing of documents and other materials and information does not provide any license express or implied by estoppel or otherwise to any such patents trademarks copyrights or other intellectual property rights Intel products are not intended for use in medical life saving life sustaining critical control or safety systems or in nuclear facility applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilit
34. S CLKOEN S3 0 to some stable value E external 8 2 KQ resistor 0000b for example To selectively disable some of the S CLKO 8 0 refer to 31154 Control Register 2 bits 8 0 Hot Swap For Hot Swap Connect the interrupt input pin to the host HS_ENUM eene When not using Hot Swap NC there is a weak internal pull up For Hot Swap Connect to cPCI ejector switch HS LSTAT i When not using Hot Swap Tie low to GND For Hot Swap HS LED OUT Connect to cPCI blue LED When not using Hot Swap NC For Hot Swap 0 2 The 31154 retries any Type 0 configuration cycles addressed to it until serial ROM preload has completed default 0 Tie low to GND HS SM 1 The 31154 ignores causes master abort any 1 Pull high to 3 3 V through an external 8 2 KQ Type 0 configuration cycles addressed to it resistor until its serial ROM preload has completed When not using Hot Swap Tie low to GND NOTES 1 The recommended value for pull up resistors for PCI applications is 5 6 KQ note that the minimum value for PCI 3 3 V signaling Ryin 2 42 KO Rryp 8 2 KO as per the PCI Local Bus Specification Revision 2 3 section 4 3 3 2 The recommended value for pull up resistors for PCI X applications is 8 2 KQ For PCI X the minimum pull up resistor value is 5 KQ as per the PCI X Addendum to the PCI Local Bus Specification Revision 1 0b section 9 7 3 For plug in card implementations
35. ary to secondary PCI buses bypassing the bridge Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 29 n PCI PCI X Interface ntel 5 3 5 3 1 Figure 5 5 3 2 30 IDSEL Lines The IDSEL lines act as chip selects during the configuration cycles Configuration cycles allow read and write access to one of the device configuration space registers As in PCI the IDSEL lines can be mapped to upper address lines which are unused during the configuration cycles Primary IDSEL Line Figure 5 provides an example of the 31154 used as an embedded controller connected to four PCI devices Note that AD16 is typically reserved for a PCI PCI X bridge When the 31154 is used as the primary interface to a plug in card the primary IDSEL line must be routed from the PCI connector to the P IDSEL pin When the 31154 is used in an embedded application PCI AD16 is used for source bridges This line AD16 must be connected to the P IDSEL line through a 2 KQ resistor IDSEL Mapping P AD 31 0 Intel 31154 UO Processor P IDSEL S AD 81 0 PCI Connector 1 IDSEL PCI Connector 2 IDSEL PCI Connector 3 IDSEL 2KQ Note PCI Bus Interrupt Signals rotate on subsequent PCI Connectors B3329 01 Secondary IDSEL Lines The PCI specification recommends a specific resistor value of 2 KQ 5 A smaller value may be used as long as system analysis ensures that timing and noise budgets for the AD bit
36. capable at frequencies of up to 133 MHz It also indicates that the 31154 is capable of running at 66 MHz when operating in conventional PCI mode Secondary PCI Clocking Mode The 31154 is the originating device for its secondary bus and as such sets the bus mode and frequency when exiting out of the secondary bus reset sequence The two key components that factor into the resultant secondary bus mode and frequency are the PCI X standard sampling of downstream device capabilities and the system specific physical bus loading characteristics for which the PCI X Addendum to the PCI Local Bus Specification Revision 1 0b does not provide any standard means of reporting Downstream device capabilities are indicated by the values of S M66EN and S PCIXCAP during S RST assertion Knowledge of the device capabilities alone is insufficient information to robustly select the bus frequency In order to know with certainty at what frequency to set the bus knowledge of the bus layout for example the number of slots is also necessary The 31154 provides the S MAX100 strapping pin for reporting system specific secondary bus loading information that is used in determining the maximum operating frequency of the secondary bus The 31154 considers 5 MAX100 along with S_PCIXCAP and S M66EN to determine the secondary bus mode and frequency when emerging from S_RST For example when a card is plugged into a two slot secondary bus the S MAXI0OO strapping of Ib ens
37. cated on the PBGA package to simplify signal routing and system implementation Figure 3 shows the left side of the 31154 ball map and Figure 4 shows the right side of the ball map Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 13 Package Information n Figure 2 Intel 31154 133 MHz PCI Bridge Package Notes 1 All dimensions and tolerances conform to ANSI Y14 5M 1982 Dimension is measured at the maximum solder ball g 9 20 C ER diameter parallel to primary datum o A 0 60 22 20 18 16 14 12 10 8 4 2 Y 29 2 19 17 15 s 9 7 5 3 1 Primary datum O and seating plane are defined by the 1030 Q C AS BO T oooooooooooooooooooooo a spherical crowns of the solder balls 00000000000000000000000 1 27 A 00000000000000000000000 c i i i 00000000000000000000000 4 All dimensions unless otherwise specified are in millimeters 00000000000000000000000 E 0000000000 0000000000 F 999909090 000000 ls 9990909090 oooooo H 000000 000000 000000 00600 000000 x 00000 00000 00000 L ooooo T o ooooo w ooooo ooooo 00000 n 9990909090 00000 0900000 e gt am 383888 5 0 127 A 000000 U 600000 Y 31 00 0 10 F Feooooo w 9909090909 k 900000 AA 9990909090 AB SEE DETAIL A 26 00 0 20 1 53REF Nj 99990 As FB gt 1 53 REF Le 1 27 31 0
38. ch allows ease of viewing the PCI signals on an Agilent Technologies logic analyzer Refer to the following test equipment that is used for this analysis Two AMP 2 767004 2 surface mount connectors mounted on the target board and routed to the PCI X local bus Two Agilent Technologies E5346A or E5351A high density adapter cables from FuturePlus Systems or Agilent Technologies Fourlogic analyzer PODS FS1104 software from FuturePlus Systems Equivalent analyzers can be substituted A FuturePlus Systems configuration file with the FS1104 product that matches the pinout is listed in Table 23 through Table 28 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 61 Debug Connectors and Logic Analyzer Connectivity n Table 23 Logic Analyzer Pod 1 Mictor 38 1 Pin Number Odd Pod Logic Analyzer Channel Number PCI X Name 6 CLKC 16 CLK 8 15 C BE4 10 14 C BE5 12 13 C BE6 14 12 C BE7 16 11 ACK64 18 10 REQ64 20 9 UNUSED 22 8 PME 24 7 C BEO 26 6 M66EN 28 5 C BE1 30 4 SERR 32 3 PAR 34 2 PERR 36 1 LOCK 38 0 STOP 62 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide n Debug Connectors and Logic Analyzer Connectivity Table 24 Logic Analyzer Pod 2 Mictor 38 1 Pin Number Odd Pod Logic Analyzer Channel Number PCI X Signal Name 5 CLK 16 FRAME d 15 DEVSEL 9 14 TRDY 1
39. d Logic Analyzer Connectivity ntel 68 THIS PAGE INTENTIONALLY LEFT BLANK Intel 31154 133 MHz PCI Bridge Design Guide Design Guide intel Thermal Solutions Thermal Solutions 11 The Intel 31154 133 MHz PCI Bridge is packaged in a 421 lead PBGA package The mechanical dimensions for this package are provided in Figure 2 Intel 31154 133 MHz PCI Bridge Package on page 14 Table 29 gives the operational power specifications Table 29 Operational Power Voltage Maximum Power 3 3 V 2 5 W 1 3 V 0 7 W Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 69 Thermal Solutions 70 THIS PAGE INTENTIONALLY LEFT BLANK Intel 31154 133 MHz PCI Bridge Design Guide Design Guide j ntel e References References 12 12 1 Related Documents Table 30 lists several books and specifications that are helpful for designing with the Intel 31154 133 MHz PCI Bridge Table 30 Design Reference Material Design Reference Material Brian C Wadell Transmission Line Design Handbook Artech House 1991 K C Gupta et al Microstrip Lines and Slotlines Artech House 1996 Moises Cases Nam Pham and Dan Neal Design Modeling and Simulation Methodology for High Frequency PCI X Subsystems http www pcisig com PCI Local Bus Specification Revision 2 3 PCI Special Interest Group 800 433 5177 Howard W Johnson and Martin Graham High Speed Digital Design A
40. e 17 48 intel Embedded Intel 31154 133 MHz PCI Bridge Application at 100 MHz Figure 12 shows the PCI X layout for a embedded 133 MHz design In this application the 31154 is driving three loads Table 17 shows the corresponding wiring lengths to use as a reference Embedded Intel 31154 133 MHz PCI Bridge Design 100 MHz PCI X Layout gt gt eme lt UO Buffer IDSEL Agent 1 6 PCI Agent 2 7 AV LV V PCI Agent 3 B3062 02 Wiring Lengths for Embedded 100 MHz Design Lower AD Bus Upper AD Bus Segment Units Minimum Length Maximum Length Minimum Length Maximum Length W1 3 5 6 3 5 6 0 inches W2 2 5 5 0 1 5 4 0 inches W3 0 75 1 5 1 75 2 75 inches WA 0 1 0 1 inches W5 1 725 1 725 inches W6 3 25 6 5 3 25 6 75 inches W7 3 25 6 5 3 25 6 75 inches Intel 31154 133 MHz PCI Bridge Design Guide Design Guide intel 7 2 3 Figure 13 Table 18 Quad Slots at 66 MHz Figure 13 shows one of the bridge secondary AD lines branching to four segments with each segment connecting to a slot connector to a buffer on an add in card The first segment representing an upper address line branches to a series resistor to become the IDSEL line for slot 1 Table 18 shows the corresponding wiring lengths to use as a reference Quad Slots 66 MHz Topology PCI X Layout Guidelines W1 W13 gt gt z C lt 9 P
41. ecification Revision 2 3 section 4 3 3 2 The recommended value for pull up resistors for PCI X applications is 8 2 KQ For PCI X the minimum pull up resistor value is 5 KQ as per the PCI X Addendum to the PCI Local Bus Specification Revision 1 0b section 9 7 3 For plug in card implementations the pull up must be on the motherboard 4 Connect PVIO and SVIO pull up resistors to 5 V or 3 3 V power supply through an external resistor 25 Q 5 V or 0 Q 3 3 V depending on the signaling level of the primary secondary PCI bus Refer to the power sequencing guidelines in Section 8 2 on page 58 20 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide intel Terminations Table 5 Pull Up Pull Down Terminations Sheet 3 of 9 Signal Pull Up Pull Down or Termination See Note 1 Comments These signals can be used as IDSEL lines and are connected to IDSEL of the secondary PCI bus S AD 31 17 through an external series coupling resistor a resistor of 2 KO is used on the customer reference board PCI Clocks P_CLK Connect to the PCI clock on the primary PCI bus All S CLKO 8 0 and S_BRGCLKO must When the internal clock of the 31154 is used Wee connect to S CLKI through a 33 2 Q series When there are PCI slots in the design S BRGCLKO resistor S BRGCLKO must be 3 longer to i compensate for the 2 5 trace length from the EE EE U Sed connector to the PCI device on a PCI add in card These clocks
42. em is composed of one ePCI X system host board SHB and an ePCI X backplane The SHB provides arbitration clock distribution and reset functions for all expansion boards The SHB is responsible for performing system initialization by managing the IDSEL signal of each local board Physically the SHB slot can be located at any slot in the backplane Electrically it must be at the end of each of primary PCI PCI X bus Intel 31154 133 MHz PCI Bridge Design Guide Design Guide n l ntel PCI X Layout Guidelines Figure 15 shows an example of this system with dual 64 bit buses with four expansion slots on each bus The backplane example shows the SHB in an ISA chassis The SHB slot is in the center of the board Figure 16 shows the data bus segments for this eight slot topology and Table 20 lists the segment lengths for the wiring segments Figure 17 shows the clock segment lengths and Table 21 lists the clock segments lengths Figure 15 An Example of an ePCI X System Option Bracket Front Plate O 20 32 57 99 0 00 33 oe 0 00 2 283 950 Min Ful B3339 01 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 53 PCI X Layout Guidelines n Figure 16 PCI X Data Bus PICMG 1 2 Style Backplane Intel 31154 133 MHz PCI Bridge Slot1 Slot2 Slot3 Slot4 Slot5 Slot6 Slot7 Slot8 X KKK KKK X Edge Connector Backplane B3331 01 Table 20 Wiring L
43. engths for PICMG 1 2 Backplane AD Bus Segment Units Minimum Length Maximum Length WI 0 75 2 75 inches w2 0 75 2 75 inches W3 0 75 2 75 inches W4 0 75 2 75 inches W5 0 75 2 75 inches W6 0 75 2 75 inches W7 0 75 2 75 inches wa 0 75 2 75 inches W9 1 2 1 2 inches W10 0 8 0 8 inches W11 0 8 0 8 inches W12 0 8 0 8 inches W13 0 8 0 8 inches W14 0 8 0 8 inches W15 0 8 0 8 inches 54 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Figure 17 Table 21 PCI X Layout Guidelines PCI X Clock PICMG 1 2 Style Backplane Intel 31154133 MHz ZOU SlotN PCI Bridge Clock Buffer 39 Ohms Card Stub Edge Connector Jan Backplane B3332 01 PCI X Clock Wiring Lengths for PICMG Backplane Clock Point to Point Segment Units Minimum Length Maximum Length S1 0 0 3 inches S2 0 75 2 75 inches WN 0 75 2 75 inches BN 6 5 16 2 inches 8 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 55 PCI X Layout Guidelines 56 THIS PAGE INTENTIONALLY LEFT BLANK Intel 31154 133 MHz PCI Bridge Design Guide Design Guide n l ntel Power Considerations Power Considerations 8 8 1 Analog Power Pins The analog voltage pins S_VCCA and P_VCCA require a low pass filter This is implemented by connecting the P VCCA and S_VCCA pins to a 10 Q series resistor and 0 01 UF and 4 7 uF low ESR ca
44. for placing capacitors is to place high frequency ceramic capacitors as close as possible to the module Decoupling Recommendations This section describes the recommended high frequency and bulk decoupling for each of the 31154 power supplies based on our simulations The recommendations are listed in Table 11 Intel 31154 133 MHz PCI Bridge Decoupling Recommendations Pins ge i PRO hae iuda Mar 1 xwa VCC33 3 3 V 22 1210 3 2 3 4 VCC33 3 3 V 0 1 603 12 2 3 4 VCC33 3 3 V 150 7343 1 2 3 4 VCC 1 3 V 22 1210 3 2 3 4 VCC 1 3 V 0 1 603 12 2 3 4 P_VIO S_VIO 3 3 V 5 0 V 22 1210 1 2 3 4 P_VIO S_VIO 3 3 V 5 0 V 0 1 603 4 2 3 4 SE iav sectona t on EI page 57 NOTES 1 Separate capacitor required only when P_VIO and S_VIO are not connected to VCC33 2 Polymerized organic capacitors are recommended for bulk 3 X5R X7R or COG are recommended for ceramics 4 Place all capacitors as close as possible to associated pins to minimize inductance Intel 31154 133 MHz PCI Bridge Design Guide Design Guide Note Routing Guidelines Trace Impedance The PCI X Addendum to the PCI Local Bus Specification Revision 1 0b recommends that all signal layers have a controlled impedance of 57 10 for add in card applications The characteristic impedance of a signal trace is 60 100 Q for PCI add in card applications Selecting the appropriate board stack up to minimize
45. gn Guide Design Guide ntel 6 PCI X Layout Guidelines PCI X Layout Guidelines D For acceptable signal integrity with bus speeds up to 133 MHz it is important for the PCB design layout to have controlled impedance The list below provides general guidelines for routing your PCI bus signals Avoid routing signal traces longer than 8 All clock nets must be on the top layer All 32 bit interface signals from the PCI edge fingers must be no longer than 1 5 and no shorter than 0 75 All 64 bit extension signals from the PCI edge fingers must be no longer than 2 75 and no shorter than 1 75 P CLK from the PCI edge finger must be 2 5 0 1 P_RST from the PCI edge finger must be no longer than 3 0 and no shorter than 0 75 Table 12 provides information on maximum lengths for routing add on card signals Table 12 Add in Card Routing Parameters PCI X Parameter Minimum Maximum Length Length inches inches P CLK 2 40 2 60 P AD 31 0 0 75 1 50 P AD 63 32 1 75 2 75 P RST 0 75 3 00 Note Do not use more than one via for the primary PCI bus signals Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 41 n PCI X Layout Guidelines ntel E 7 1 42 PCI Clock Layout Guidelines The PCI X Addendum to the PCI Local Bus Specification Revision 1 0a allows a maximum of 0 5 ns clock skew timing for each of the PCI X frequencies 66 MHz 100 MHz and 133 MHz Total
46. hrough individual external resistors see Note 2 and Note 3 P_FRAME Connect to FRAME of the primary PCI bus P_DEVSEL Connect to DEVSEL of the primary PCI bus P_IRDY Connect to IRDY of the primary PCI bus P_TRDY Connect to TRDY of the primary PCI bus P STOP Z Connect to STOP of the primary PCI bus NOTES 1 The recommended value for pull up resistors for PCI applications is 5 6 KQ note that the minimum value for PCI 3 3 V signaling Ryun 2 42 KO Rryp 8 2 KO as per the PCI Local Bus Specification Revision 2 3 section 4 3 3 2 The recommended value for pull up resistors for PCI X applications is 8 2 KO For PCI X the minimum pull up resistor value is 5 KQ as per the PCI X Addendum to the PCI Local Bus Specification Revision 1 0b section 9 7 3 For plug in card implementations the pull up must be on the motherboard 4 Connect PVIO and SVIO pull up resistors to 5 V or 3 3 V power supply through an external resistor 25 Q 5 V or 0 Q 3 3 V depending on the signaling level of the primary secondary PCI bus Refer to the power sequencing guidelines in Section 8 2 on page 58 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 19 Terminations n Table 5 Pull Up Pull Down Terminations Sheet 2 of 9 Signal Pull Up Pull Down or Termination See Note 1 Comments P_GNT Connect to GNT of the primary PCI bus Connect to one of the AD lines of the primary PCI i S E P_IDSEL bus or to
47. i486 i960 iCOMP InstantlP Intel Intel Centrino Intel logo Intel386 Intel486 Intel740 IntelDX2 IntelDX4 IntelSX2 Intel Create amp Share Intel GigaBlade Intel InBusiness Intel Inside Intel Inside logo Intel NetBurst Intel NetMerge Intel NetStructure Intel Play Intel Play logo Intel SingleDriver Intel SpeedStep Intel StrataFlash Intel TeamStation Intel Xeon Intel XScale IPLink Itanium MCS MMX MMX logo Optimizer logo OverDrive Paragon PC Dads PC Parents PDCharm Pentium Pentium II Xeon Pentium IIl Xeon Performance at Your Command RemoteExpress SmartDie Solutions960 Sound Mark StorageExpress The Computer Inside The Journey Inside TokenExpress VoiceBrick VTune and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Other names and brands may be claimed as the property of others Copyright 2004 Intel Corporation 2 Intel 31154 133 MHz PCI Bridge Design Guide j ntel R Contents Contents 1 About This DOGCutrient a eee E ERE ENERE E doa EEAS AA 7 1 1 Terminology and Definitions lt k kud anal xal eset 2al yaaa anak aka aka keka TEENAAN EAA 7 2 aige eE e l rr rrr E 9 2 1 Product OVGIVIOW M 9 AB dT D YD eg ce n vm gggggggggggqaann 10 2 3 Related External Specifications x x ixa ya aki manan kala n n na kila yekla ay neka enne 11
48. ide intel 7 2 1 Figure 9 Note Table 14 PCI X Layout Guidelines Single Slot at 133 MHz Figure 9 shows one of the chipset PCI AD lines connected through the W1 and W12 line segments to a single slot connector through the W13 line segment to the 31154 This AD line is also used as an IDSEL line from line segment W 14 to a resistor through W15 to the PCI connector The other end of the PCI connector IDSEL line connects through W16 to the 31154 IDSEL line input buffer Single Slot Point to Point Topology UO Buffer J0120uu02 Od Slot 1 B3057 01 Stub lengths are represented by W s Wiring Lengths for 133 MHz Slot Lower AD Bus Upper AD Bus Segment Minimum Maximum Minimum Maximum rite Length Length Length Length W1 W12 5 5 10 5 4 5 9 5 inches W13 0 75 1 5 1 75 2 75 inches W14 0 1 0 1 inches W15 0 6 0 6 inches W16 1 125 1 125 inches Intel 31154 133 MHz PCI Bridge Design Guide Design Guide PCI X Layout Guidelines intel 7 2 1 1 Intel 31154 133 MHz PCI Bridge Embedded Application at 133 MHz Figure 10 shows the 31154 application in a stand alone embedded application In this application the 31154 is shown driving a single PCI device Table 15 shows the corresponding wiring lengths Figure 10 Embedded Intel 31154 133 MHz PCI Bridge Design 133 MHz PCI X Layout B3058 01 Table 15 Wiring Lengths for Embedded 133 MHz Design Lower AD B
49. ies arising from future changes to them The Intel 31154 133 MHz PCI Bridge may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request This Design Guide as well as the software described in it is furnished under license and may only be used or copied in accordance with the terms of the license The information in this manual is furnished for informational use only is subject to change without notice and should not be construed as a commitment by Intel Corporation Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this document or any software that may be provided in association with this document Except as permitted by such license no part of this document may be reproduced stored in a retrieval system or transmitted in any form or by any means without the express written consent of Intel Corporation Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s website at http www intel com AnyPoint AppChoice BoardWatch BunnyPeople CablePort Celeron Chips CT Media Dialogic DM3 EtherExpress ETOX FlashFile i386
50. impedance variations is very important When calculating flight times it is important to consider the minimum and maximum trace impedance based on the switching neighboring traces The PCI Local Bus Specification Revision 2 3 recommends a trace velocity of 150 ps in to 190 ps in Use wider spaces between traces since this can minimize trace to trace coupling and reduce crosstalk When a different stack up is used the trace widths must be adjusted appropriately When wider traces are used the trace spacing must be adjusted accordingly linearly It is highly recommended that a 2D field solver be used to design the high speed traces An impedance calculator available at http emclab umr edu pcbtlc provides approximations for the trace impedance of various topologies These approximations may be used to generate the starting point for a full 2D field solver The following website provides a useful basic guideline for calculating trace parameters http www ultracad com calc htm Using stripline transmission lines may give better results than microstrip This is due to the difficulty of precisely controlling the dielectric constant of the solder mask and the difficulty in limiting the plated thickness of microstrip conductors which can substantially increase crosstalk Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 39 Routing Guidelines 40 THIS PAGE INTENTIONALLY LEFT BLANK Intel 31154 133 MHz PCI Bridge Desi
51. ired in design Serial ROM data output NOTE When EEPROM is present but register Connect to the DO output of the EEPROM preload is not desired bits 7 6 of the first SR_DO E byte can be any value except the preload Tie high or pull to GND when EEPROM is not enable value 10b required in design Serial ROM chip select SR CS Connect to the chip select of the EEPROM NC when EEPROM is not required in design NOTES 1 The recommended value for pull up resistors for PCI applications is 5 6 KQ note that the minimum value for PCI 3 3 V signaling Ryin 2 42 KO Rryp 8 2 KO as per the PCI Local Bus Specification Revision 2 3 section 4 3 3 2 The recommended value for pull up resistors for PCI X applications is 8 2 KQ For PCI X the minimum pull up resistor value is 5 KQ as per the PCI X Addendum to the PCI Local Bus Specification Revision 1 0b section 9 7 3 For plug in card implementations the pull up must be on the motherboard 4 Connect PVIO and SVIO pull up resistors to 5 V or 3 3 V power supply through an external resistor 25 Q 5 V or 0 Q 3 3 V depending on the signaling level of the primary secondary PCI bus Refer to the power sequencing guidelines in Section 8 2 on page 58 24 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide intel Terminations Table 5 Pull Up Pull Down Terminations Sheet 7 of 9 Signal Pull Up Pull Down or Terminati
52. k equals the primary clock in frequency An external clock source can be used on the secondary interface to remove any dependencies on the primary clock input Intel 31154 133 MHz PCI Bridge Design Guide Design Guide n l ntel Routing Guidelines Routing Guidelines 6 This chapter provides some basic routing guidelines for layout and design of a printed circuit board PCB using the Intel 31154 133 MHz PCI Bridge The high speed clocking required when designing with the 31154 requires special attention to signal integrity In fact it is highly recommended that the board design be simulated to determine optimum layout for signal integrity The information in this chapter provides guidelines to aid the designer with board layout Several factors influence the signal integrity of a 31154 design including the following Power distribution Decoupling Minimizing crosstalk Layout considerations when routing the PCI X bus interfaces The order in which signals are routed varies from designer to designer Some designers prefer to route all clock signals first while others prefer to route all high speed bus signals first Either order can be used provided the guidelines listed here are followed Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 35 n Routing Guidelines ntel 6 1 Figure 6 36 Crosstalk Crosstalk is caused by capacitive and inductive coupling between signals Crosstalk is composed of
53. nd bounce effects These results for the slot configurations met the required PCI X timing characteristics and were within appropriate noise margins 133 MBz Single Slot Included a single connection from the bridge to a single slot e 133 MHz Embedded Included a single connection from the bridge to one additional device on the system board Note that this topology was interpolated from the above 133 MHz One Slot not based on actual simulation results 100 MHz Two Slot Non Hot Plug Balance Star Included a single connection from the bridge to two slots without hot plug devices The connections to the bridge and to each slot came together such that each of the three branches is approximately the same length 100 MHz Embedded Non Hot Plug Balance Star Included a single connection from the bridge to three devices The connections to the bridge and to each device came together such that each of the three branches was approximately the same length Note that this topology was interpolated from the above 100 MHz Two Slot not based on actual simulation results 66 MHz Four Slot Non Hot Plug Included a single connection from the bridge to four hot plug slots e 66 MHz Embedded Non Hot Plug Included a single connection from the bridge to four hot plug slots Note that this topology was interpolated from the above 66 MHz Four Slot not based on actual simulation results Intel 31154 133 MHz PCI Bridge Design Guide Design Gu
54. ngth from S_BRGCLKO to the series resistor must be matched to the other clock line lengths to within 0 1 inch The clock line length from the series resistor to S_CLKIN must be matched to the other clock line lengths to within 0 1 inch B3330 01 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 43 n PCI X Layout Guidelines ntel E 7 2 Table 13 44 PCI X Topology Layout Guidelines The PCI X Addendum to the PCI Local Bus Specification Revision 1 0a recommends the following guidelines for the number of loads for your PCI X designs Table 13 Any deviation from these maximum values requires close attention to layout with regard to loading and trace lengths PCI X Slot Guidelines Frequency Maximum Loads EL 66 MHz 8 4 100 MHz 4 2 133 MHz 2 1 The following PCI X design layout considerations are compiled from the white paper Design Modeling and Simulation Methodology for High Frequency PCI X Subsystems available on the http www pcisig com website The following results are compiled from the simulation of system models that included system board and add in cards for different slot configurations and bus speeds discussed in the white paper mentioned above This simulation addressed signal integrity issues including reflective noise crosstalk noise overshoot undershoot voltage ring back voltage settling time inter symbol interference input reference voltage offset and grou
55. o GND through a 0 Q external resistor RSRV1 CRSTEN Tie to GND through a 0 Q external resistor S M66EN is meaningful only when S PCIXCAP is connected to GND that is when the secondary PCI bus is in legacy PCI mode For designs without secondary PCI slot When the secondary PCI devices and loading support 66 MHz PCI bus pull up to 3 3 V through an 8 2 KQ series resistor S M66EN When the secondary PCI devices and Refer to PCI X Addendum to the PCI Local Bus z loading do not supports 66 MHz PCI bus Specification Revision 1 0b Table 6 1 GND this pin For designs with secondary PCI slot When the on board PCI device does not support 66 MHz PCI bus GND this pin When the on board PCI device does support 66 MHz PCI bus connect this pin to M66EN pin 49B of the PCI connector For designs without secondary PCI slot When there is at least one legacy PCI device on the secondary PCI bus tie this pin directly to GND When there is at least one PCI X device that supports maximum PCI X of only 66 MHz on the secondary PCI bus pull down to GND through a 10 KQ series resistor When all secondary PCI X devices and the S PCIXCAP bus loading support PCI X 133 MHz leave Refer to PCI X Addendum to the PCI Local Bus this pin unconnected except for decoupling Specification Revision 1 0b Table 6 1 capacitor For designs with secondary PCI slot When there is at least one on board legacy PCI device on the secondary PCI bus
56. omer Reference Board ntel The IQ31154 CRB is implemented on eight layers These layers are detailed in Table 22 This example is provided as a reference each individual 31154 application may vary Table 22 Customer Reference Board Stackup Layers Signal Top layer Signal layer critical nets clocks S P AD buses 2nd layer Ground plane 3rd layer Signal layer 4th layer Power plane split voltage plane 3 3 and 1 3 for I O and core 5th layer Power plane also a split voltage plane 5 and 12 V 6th layer Signal some minor 25 mil wide power runs included 7th layer Ground plane 8th layer Signal layer critical nets FR 4 0 062 in 0 008 1 0 oz copper power GND oz copper signal 60 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide n ntel R Debug Connectors and Logic Analyzer Connectivity Debug Connectors and Logic Analyzer Connectivity 10 10 1 Probing PCI X Signals To ease the probing and debugging of the PCI X signals you are recommended to passively probe the PCI X bus signals with a logic analyzer This can be done by placing six AMP Mictor 38 connectors on the board or by probing the bus with an interposer card such as the FuturePlus Systems FS2007 that works with an Agilent Technologies logic analyzer For ease of debugging the pinout of the AMP Mictor 38 connectors the recommended pin out matches the FuturePlus Systems configuration setup whi
57. on See Note 1 Comments JTAG TCK Pull low when not used TDI When not used pull up to 3 3 V through an external 8 2 KQ resistor TDO NC when not used When not used pull low to GND through an TRST external 1 KQ resistor TMS When not used pull up to 3 3 V through an external 8 2 KQ resistor SCAN_EN For normal operation tie low to GND For normal operation tie to 0000 or 0111 TMODE 3 0 0 Pull low to GND 3 0 1 Pull high to 3 3 V through an external 8 2 KO resistor Voltages Connect to 1 3 V supply through a low pass filter to Ensure that the voltage at the input pin is reduce noise induced jitter The 4 7 uF capacitor within the min max range for S_VCCA S_VCCA must be low ESR solid tantalum the 0 01 uF 1 235 V and 1 365 V capacitor must be of type X7R and the node For power sequencing see Section 8 2 connecting VCCPLL must be as short as possible Power Sequencing on page 58 Connect to 1 3 V supply through a low pass filter to Ensure that the voltage at the input pin is reduce noise induced jitter The 4 7 uF capacitor within the min max range for P VCCA P VCCA must be low ESR solid tantalum the 0 01 uF 1 235 V and 1 365 V capacitor must be of type X7R and the node For power sequencing see Section 8 2 connecting VCCPLL must be as short as possible Power Sequencing on page 58 VCC Connect to 1 3 V supply VCCP Connect to 3 3 V supply Connect to 5 V or 3 3 V power supply through an PVIO ex
58. pacitors in parallel going to ground The opposite end of the 10 resistor is connected to the 1 3 V supply This arrangement is shown in Figure 18 and Figure 19 When implementing these circuits use the following filter circuit layout and component recommendations 1 Low ESR polymerized organic capacitors are recommended for 4 7 UF 2 The 0 01 uF capacitor must be a X5R X7R or COG 3 The capacitors must be placed as close as possible to associated pins to minimize inductance 4 The connections from the P VCCA and S_VCCA must be kept as short as possible Figure 18 P_VCCA Filter 10 Ohms P_VCCA 0 01 T 4 7 T B3333 01 Figure 19 S VCCAFilter 10 Ohms S VCCA 0 01 T 4 7 T B3334 01 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 57 n Power Considerations ntel S 8 2 Figure 20 58 Power Sequencing When either P VIO or S VIO is connected to a power supply other than Voc you must perform one of the following steps listed in order from most favorably recommended to least favorably recommended 1 Ensure that the P VIO or S VIO power comes up before or simultaneously with V ccp and ensure that the P VIO or S VIO power goes down after or simultaneously with V ccp 2 Alternatively when the recommendation in item 1 is not followed install a Schottky diode as shown in Figure 20 between Vc and the VIO pin s as appropriate The diode must be sized a
59. ppropriately for the power environment of the system 3 Alternatively when the recommendations in item 1 and item 2 are not followed connect a 25 Q current limiting resistor in series with the P VIO and S VIO supply P VIO and S VIO must never be at a voltage lower than Vc except in the case of a 25 Q current limiting resistor in series with the P VIO and S VIO supply PVIO Voltage Protection Diode Shottky Diode Intel 31154 133 MHz PCI Bridge B3335 01 8 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide intel Customer Reference Board Customer Reference Board 9 Figure 21 This chapter provides information on the customer reference board based on the Intel 31154 133 MHz PCI Bridge the Intel IQ31154 Customer Reference Board CRB Figure 21 shows the block diagram for this CRB The schematics for this board are provided on the Intel Developer s website document number 278839 Intel 1Q31154 Customer Reference Board Block Diagram Logic Analyzer Mictors Quick Switches Quick Switch O Enable Serial X a EEPROM Strapping Intel 31154 Options 133 MHz PCI Bridge PCI Primary Bus B3336 01 1 The schematics are included in the download at http downloadfinder intel com scripts df license_agr asp url 68 10 eng 31154_eval zip amp sType amp ProductID amp PrdMap Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 59 n Cust
60. rmination See Note 1 Comments OPAQUE_EN To enable Opaque Memory Base Limit Registers to establish a private memory space for secondary bus usage Pull high to 3 3 V through an external 8 2 KQ resistor To disable Opaque Memory Base Limit Registers Pull low to GND through an external 220 Q resistor default IDSEL MASK To enable device hiding after reset in other words to hide device numbers 16 21 from the host Pull high to 3 3 V through an external resistor To disable device hiding after reset Pull low to GND through an external 220 Q resistor default After reset device hiding can be performed through software through the Secondary IDSEL Select Register Offset 5Ch DEV_64BIT This bit is used by the system management software to help the user identify the best slot for an add in card When the 31154 is installed on an add in card and the add in card implements a 64 bit PCI connector pull up to 3 3 V through an external 8 2 KQ resistor When the 31154 is not installed on an add in card or the add in card implements only a 32 bit PCI connector pull low to GND through a 220 Q external resistor default Serial EEPROM Serial ROM clock input SR_CLK Connect to the clock input of the EEPROM NC when EEPROM is not required in design Serial ROM data input SR_DI Connect to the DI input of the EEPROM NC when EEPROM is not requ
61. s not been completely dissipated interferes with a signal being transmitted down a transmission line ISI can impact both timing and signal integrity It is dependent on frequency time delay of the line and the refection coefficient at the driver and receiver Examples of ISI patterns that can be used in ISI testing at the maximum allowable frequencies are the sequences shown below 0101 0101 0101 0101 0011 0011 0011 0011 000 1110 0011 1000 1111 Davies A device is a component of a PCI system that connects to a PCI bus As defined by PCI 2 3 a device can be a single function or a multi function device Downstream A transaction that targets the secondary side of the bridge is a downstream transaction Upstream A transaction that targets the primary side of the bridge is an upstream transaction SHB SHB is a system host board in a PICMIG 1 2 backplane The removable CPU board provides clocks and arbitration signals as well as an optional ATX power supply control ePCI X Embedded PCI X specification CRB Customer Reference Board Intel 31154 133 MHz PCI Bridge Design Guide Design Guide intel Introduction 2 1 Product Overview Introduction 2 The Intel 31154 133 MHz PCI Bridge called hereafter the 31154 is a PCI component that functions as a highly concurrent low latency transparent bridge between two PCI buses The 31154 can operate as a PCI to PCI bridge in the configurations shown in Table 2
62. ternal resistor depending on the signaling level of primary PCI bus see Note 4 Connect to 5 V or 3 3 V power supply through an SVIO external resistor depending on the signaling level of secondary PCI bus see Note 4 Miscellaneous R REF Pull down to GND through an external 30 Q 1 resistor MTO and MT1 Pull up to 3 3 V through an external 8 2 KQ series resistor NOTES 1 The recommended value for pull up resistors for PCI applications is 5 6 KQ note that the minimum value for PCI 3 3 V signaling Ryn 2 42 KO Rryp 8 2 KO as per the PCI Local Bus Specification Revision 2 3 section 4 3 3 2 The recommended value for pull up resistors for PCI X applications is 8 2 KQ For PCI X the minimum pull up resistor value is 5 KQ as per the PCI X Addendum to the PCI Local Bus Specification Revision 1 0b section 9 7 3 For plug in card implementations the pull up must be on the motherboard 4 Connect PVIO and SVIO pull up resistors to 5 V or 3 3 V power supply through an external resistor 25 Q 5 V or 0 Q 3 3 V depending on the signaling level of the primary secondary PCI bus Refer to the power sequencing guidelines in Section 8 2 on page 58 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 25 Terminations n amp Table 5 Pull Up Pull Down Terminations Sheet 8 of 9 Signal Pull Up Pull Down or Termination See Note 1 Comments RSTVO Tie t
63. the pull up must be on the motherboard 4 Connect PVIO and SVIO pull up resistors to 5 V or 3 3 V power supply through an external resistor 25 Q 5 V or 0 Q 3 3 V depending on the signaling level of the primary secondary PCI bus Refer to the power sequencing guidelines in Section 8 2 on page 58 22 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide intel Terminations Table 5 Pull Up Pull Down Terminations Sheet 5 of 9 Signal Pull Up Pull Down or Termination See Note 1 Comments For Hot Swap Depending on Primary PCI Bus frequency 00 PCI Mode 33 or 66 MHz default Only valid when HS SM 1 01 PCI X 66 MH 2T HS FREQ 0 Z 0 Tie low to GND 10 PCI X 100 MHz 11 PCI X 133 MHz When not using Hot Swap Tie low to GND 1 Pull high to 3 3 V through external 8 2 KO resistor Hardware Straps sampled at the edge of P_RST S_ARB_DISABLE S_ARB_LOCK To disable internal secondary arbiter Pull up to 3 3 V through an external 8 2 KQ resistor S GNTO becomes the secondary PCI bus request output of the 31154 and S REQO becomes the secondary PCI bus grant input of the 31154 To enable internal secondary arbiter Pull down to GND through an external 220 Q resistor default S ARB LOCK after trailing edge of P_RST Sampled as 1b the internal secondary bus arbiter of the 31154 locks and provides the grant only to itself When internal arbiter is used and
64. tie this pin directly to GND Otherwise connect this pin to PCIXCAP pin B38 of the PCI connector assuming that the bus loading supports up to PCI X 133 MHz NOTES 1 The recommended value for pull up resistors for PCI applications is 5 6 KQ note that the minimum value for PCI 3 3 V signaling Rmn 2 42 KO Rryp 8 2 KO as per the PCI Local Bus Specification Revision 2 3 section 4 3 3 2 The recommended value for pull up resistors for PCI X applications is 8 2 KQ For PCI X the minimum pull up resistor value is 5 KQ as per the PCI X Addendum to the PCI Local Bus Specification Revision 1 0b section 9 7 3 For plug in card implementations the pull up must be on the motherboard 4 Connect PVIO and SVIO pull up resistors to 5 V or 3 3 V power supply through an external resistor 25 Q 5 V or 0 Q 3 3 V depending on the signaling level of the primary secondary PCI bus Refer to the power sequencing guidelines in Section 8 2 on page 58 26 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide intel Terminations Table 5 Pull Up Pull Down Terminations Sheet 9 of 9 Signal Pull Up Pull Down or Termination See Note 1 Comments When forced retirement of the 31154 internal request queues and data buffer is not desired As soon as NT_MASK is asserted it must in the application this pin must be pulled up to not be de asserted until the QE pin is 3 3 V through an 8 2 KQ resistor
65. ures that the bus runs at no greater than 100 MHz regardless of the reported downstream device capabilities Intel 31154 133 MHz PCI Bridge Design Guide Design Guide PCI PCI X Interface Table 8 PCI X Clocking Modes PCIXCAP pin on PCI X Mode PCI Mode PCI connector P_M66EN Not capable 33 MHz GND GND Not capable 66 MHz GND Not connected PCI X 66 MHz 33 MHz Pull down GND PCI X 66 MHz 66 MHz Pull down Not connected PCI X 133 MHz 33 MHz Not connected Ground PCI X 133 MHz 66 MHz Not connected Not connected Table 9 Secondary Bus Frequency Initialization Conventional PCI Typical Slot S M66EN S PCIXCAP S MAX100 Frequency PCI X Frequency Loading Ground Ground 33 MHz Not capable Not connected Ground 66 MHz Not capable Typical setting for Ground Pull down _ 33 MHz PCI X 66 MHz four slots Not connected Pull down 66 MHz PCI X 66 MHz Ground Not connected 1 33 MHz PCI X 100 MHz Typical setting for Not Connected Not Connected 1 66 MHz PCI X 100 MHz two slots Ground Not Connected 0 33 MHz PCI X 133 MHz Not Connected Not Connected 0 66 MHz PCI X 133 MHz err for NOTE 1 Simulation is suggested for any deviation from typical slot loading recommendations Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 33 PCI PCI X Interface n Table 10 5 6 3 34 Table 10 describes the bus mode and frequency initialization pattern that the 31
66. us Upper AD Bus Segment Minimum Maximum Minimum Maximum Units Length Length Length Length W1 5 5 10 5 4 5 9 5 inches We 0 75 1 5 1 75 2 75 inches W3 0 1 0 1 inches W4 1 725 1 725 _ inches 46 Intel 31154 133 MHz PCI Bridge Design Guide Design Guide to use as a reference n l ntel PCI X Layout Guidelines 7 2 2 Dual Slot at 100 MHz Figure 11 shows one of the secondary bridge PCI AD lines branching into two segments with each going through slot connectors to a buffer on an add in card Table 16 shows the corresponding wiring lengths to use as a reference This two slot design uses a balanced star topology Figure 11 Dual Slot Configuration IO Buffer J012euu02 Dd W Q gt Kei 0 EI PCI Agent 2 J0 98UU09 Od Slot 2 B3059 01 Table 16 Wiring Lengths for 100 MHz Dual Slot Lower AD Bus Upper AD Bus Segment Minimum Maximum Minimum Maximum Unlts Length Length Length Length W1 3 5 6 3 5 6 inches W21 2 0 4 5 1 0 3 5 inches W11 W12 0 5 0 5 0 5 0 5 inches W13 0 75 1 5 1 75 2 75 inches W14 0 1 0 1 N A N A inches W15 0 6 0 6 N A N A inches W16 1 125 1 125 N A N A inches W21 2 0 4 5 1 0 3 5 inches W22 0 5 0 5 0 5 0 5 inches WW23 0 75 1 5 1 75 2 75 inches Intel 31154 133 MHz PCI Bridge Design Guide Design Guide 47 PCI X Layout Guidelines 7 2 2 1 Figure 12 Tabl

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