Home

Emerson NT5C06D Power Supply User Manual

1. 73 MPC860 Parallel Port configuration 3 5 Deadlocked Cycles 7 6 Optional BDM Header 3 6 Retries on Local Direct Master Cycles oot desees intus ps 7 6 Retries on Direct Slave Cycles 7 6 4 On Card Memory Assigning Priorities E T 7 6 Configu ration Controlling Access Latency 7 7 Socketed Flash 0 00eeeeeees 4 1 Avoiding the PCI9060ES Phantom I2CEEPROM ccceccccccuuce 4 1 R ad cit ccm week EU UD Uii edt 7 7 I2C EEPROM Operation 4 2 Managing Bandwidth 7 8 Emerson Memory Map 4 2 Bridge to Bridge Considerations 7 8 On card DRAM cccceccccecece 4 2 PCl Interrupts 0 ee eee 7 8 On card Memory Sizing and Type 4 3 PCI Bus Interface 4 7 8 DRAM Timing 4 3 PMC Connector Pin Assignments 7 8 PCI Bus Control Signals 7 10 10002367 02 PmT1 and PmE1 User s Manual ed 8 Monitor Power up Reset Sequence 8 1 Start up Display 06 8 4 Command line History 8 5 Command line Editor 8 5 Initializing Memory 8 6 Command Syntax 0 06s 8 6 Initializing Memory 8 7 Command Syntax 0 08s 8 7 Typographic Conventions 8 7 Boot Commands 2 04 8 7 bootbus 0 cece eee ee eee ee 8 7 booteprom e eee eee 8 8 DOOHOM so eorr p e
2. sss 8 34 interrupts CPM Si eo aaesu pde deis 5 3 PMC PCI 605 7 8 7 10 IRQZ 5 coe beevm rente 3 4 K keys dopo E 8 5 DNE 8 5 o OUR EE 8 5 L INTO enm ee E pus 3 4 LoadAddress field monitor 8 7 local bus speed 4 3 LOCK signal PCI 7 11 ISERR secessit 3 4 EH PmT1 and PmET User s Manual management data interface MDI 6 7 Manufacturing monitor group 8 3 mean time between failures MTBF 1 4 memory initializing from the monitor8 6 8 7 management 8 39 monitor commands 8 10 phe 4 3 memory controller 3 4 Memory Map e eee eee 1 2 EEPROM sii 0d thx tmi 4 2 memory test error 8 29 Misc monitor group 8 2 8 17 monitor command syntax 8 6 8 7 command line history 8 5 EEPROM 41th 8 13 Ee serm re rerer ene 8 10 NVRAM configuration defaults 8 2 operation l l ese 8 1 power up reset sequence 8 1 start up display 8 4 version number 2 7 monitor command Tae sede ere etes 8 27 bootbus ceste rr me 8 7 booteprom esses 8 8 bootrom eere rr rms 8 9 bootserial 004 8 9 cachetest 00 8 18 Call s arni nN a 8 19 checksummem 8 10 cearmem ess 8 10 EMPMEM ss 2s rrr pere 8 10 configboard 8 27 configboard 8 13 COPYMEM ee eee eee ee 8 11 displa
3. 5 4 transmit clock TCLK 6 4 transmit link TLINK 6 6 transmit link clock TLCLK 6 6 transmit serial TSER 6 4 transmit sync TSYNC 6 4 troubleshooting general 2 6 U UART s 31i ated Soo Ries 5 4 baud rate selection 5 6 10002367 02 UL certifications sss 1 5 user programmable machine UPM 4 3 utilities for the monitor 8 27 V vectors interrupt 8 34 vendorID ee ee eee eee 7 4 version mohitor iss rem nee wens 2 7 operating system 2 7 vi editing commands 8 5 WwW write cycle access time 4 3 Notes 10002367 02 PmT1 and PmE1 User s Manual P Bl AC Power Systems Bl Embedded Power ll Precision Cooling Emerson Network Power The global leader in enabling W Connectivity Wi integrated Cabinet Solutions H services Business Critical Continuity Wl pc Power Systems B Outside Plant H site Monitoring E Embedded Computing Bi Power Switching amp Controls Bi surge amp Signal Protection Emerson Network Power Embedded Computing Business Critical Continuity Emerson Network Power and the 8310 Excelsior Drive Madison WI 53717 1935 USA Emerson Network Power logo are trademarks andservice marks of US Toll Free 1 800 356 9602 Voice 1 608 831 5500 FAX 1 608 831 4249 Emerson Network Power Embedded Computing Inc Email info artesyncp com 2007 Emerson Network Powe
4. 8 40 EEPROMACC 0eee eee 8 30 enable dcache 8 33 enable icache 8 33 FindBitSet 0000 8 37 IR DTE EPOR 8 39 FromFifo ics e er e 8 38 Getcha eerte erre 8 30 getDC_CST 8 36 getDEC inier im nons 8 36 g tlC CST o roreper yes 8 36 getlCTRL ese cha re ren nen 8 36 getMSR cesechrrer rre 8 36 getSRRO oss eere rritehen 8 36 getSRRI cessere bre here 8 36 getTBL diu veeex och e res 8 36 Index continued getTBU Jue ee pore wie 8 36 XSDrintf e eu een er ree nes 8 45 overview lees 1 1 HexToBin 0 cee eee 8 37 read cycle access time 4 3 InitBoard cece eee eee 8 31 N receive clock RCLK 6 3 InitFIfO ener ea 8 38 receive link RLINK 6 6 Interact 8 44 non burst cycles 4s 4040400 0ees 4 4 receive link clock RLCLK 6 6 Sree Or D EO notation conventions 1 6 3 menon ld naa invalidate_dcache 8 33 receive serial RSER 6 4 invalidate icache 8 33 pc for monitor arguments receive sync RSYNC 6 4 legah eos erre Rene 8 38 umane LE 8 6 8 7 references and manuals 1 6 IsPowerUp sss 8 31 EO DAD M d register map for PCISO60ES 7 1 KBElE o is orent es 8 31 22 M default monitor configuration register monitor commands 8 10 LongAddrTest 8 44 registers Mallot cierre ee mene 8 39 BER c TERT 4 3 Masklnts lesse 8
5. 6 5 features general 1 1 figures listof 00 iii ix flags for monitor commands 8 10 flash eee ener een 4 1 overview eee eee ee eee 1 1 free memory 2000 8 39 front panel I O cable assembly 2 5 front panel TDM ports 2 1 function reference 8 29 G general purpose timers 5 4 grant signal PCl 7 10 grounding ee eee aee 2 1 group BootParams 8 2 Cache sus onere emet Eus 8 2 Console and Download 8 2 HardwareConfig 8 3 PmT1 and PmE1 User s Manual Manufacturing 8 3 MISC e eerie 8 2 8 17 H HardwareConfig monitor group 8 3 HOC os uetus aaa T 5 4 hex Intel fileexample 8 23 records 4 8 18 8 21 l IDMA channels suse 5 4 initialization device select signal PCI 7 10 error nonvolatile memory 8 28 of board to defaults 8 31 of CPM registers 5 2 of memory from the monitor 8 7 of memory monitor 8 6 of nonvolatile memory 8 14 of PCISOGOES 7 3 initiator ready signal PCI 7 10 installation of the board 2 5 INITAT cure xen 7 4 7 10 INTB sc siieca dece vex eem 7 10 INTE ecto Renita epe RR PR 7 10 INTOS core n tre cette 7 10 internal interrupt sources 3 4 interrupt vector register 1 4 3 4 interrupt vectors
6. HELP COMMANDS help Use the help command to view the description of the monitor command specified by name The full name of the command must be given help name For instructions on editing command lines type help editor For a list of command line functions type help functions For a detailed memory map type help memmap MEMORY REGISTER COMMANDS For some memory commands the data size is determined by the following flags The flag b is for data in 8 bit bytes The flag w is for data in 16 bit words The flag l is for data in 32 bit long words checksummem reads bytecount bytes starting at address source and computes the checksum for that region of memory The checksum is the 16 bit sum of the bytes in the memory block checksummem source bytecount clearmem clears bytecount bytes starting at address source clearmem source bytecount cmpmem compares bytecount bytes at the source address with those at the destination address Any differences are displayed cmpmem source destination bytecount copymem copies bytecount bytes from the source address to the destination address s0 PmT1 and PmE1 User s Manual 10002367 02 Monitor Memory Register Commands Description Description Description Description Description Description Description copymem source destination bytecount displaymem displays memory in 16 byte lines starting at address startaddr The number of lines dis pla
7. shown in Table 3 7 EH PmT1 and PmET User s Manual 10002367 02 Central Processing Unit Optional BDM Header Figure 3 1 Table 3 7 Processor BDM Header 10 1 Processor BDM Pin Assignments Pin Signal Number Name Description 1 VFLSO Visible History Buffer Flushes Status 0 output line reports how many instructions were flushed from the history buffer in the MPC860P internal core 2 SRESET Software Reset input signal may initiate a warm reset 3 GNDI Ground MEM m 4 CK Test Clock input scan data is latched at the rising edge of this signal 7 1K ohm pull up to 5 volts input to board JTAG bit clock 5 GND2 Ground 0 E 6 O VFLSI Visible History Buffer Flushes Status 1 output line reports how many instructions were flushed from the history buffer in the MPC860P internal core 7 HRESET Hardware Reset input signal is used at power up to reset the processor 8 TDI Test Data Input signal acts as the input port for scan instructions and data 1K ohm pull up to 5 volts input to board JTAG data in 9 2033V 33 Voltage i 5 7 10 TDO Test Data Output signal acts as the output port for scan JTAG instructions and data 10002367 02 PmT1 and PmE1 User s Manual Central Processing Unit Optional BDM Header PmT1 and PmE1 User s Manual 10002367 02 On Card Memory Configuration Note Caution A Table 4 1 The PmT1
8. Intel 1 for S records 2 for Emerson binary DevNumber Define device number 0 Whether you use this field depends on the application ClrMemOnBoot Clear memory on boot False True False HaltOnFailure Halt if a failure occurs False True False HardwareConfig DRAMSz 16MEG 16MEG NVMemSize 2K Bytes 2K Bytes FlashSize None None 4MB Mpulype MPC860 MPC860 MPC860P Mmulype MPC860 MPC860 MPC860P CacheType MPC860 MPC860 MPC860P FpuType None None None DmaType None None MemExp None None Eth Type None None ScsiType None None Manufacturing Test Services Mode i PmTlandPmEI ShipDate Unknown ManufPartNum Unknown WorkOrderNum Unknown SerNumber 0 RevLev 0 1 DoModConfig must be set to False in Solaris hosts 2 These values are set by software 3 These values are entered in the Test Services department 10002367 02 PmT1 and PmE1 User s Manual H Monitor Start up Display START UP DISPLAY At power up or after a reset the monitor runs diagnostics and reports the results in the start up display The PmT1 and PmE1 displays have identical diagnostic reports Figure 8 1 Monitor Start up Display Hardware initialization Hello World and power up MPC860 and SMC are initialized diagnostic Memory Size is 0x00400000 reports 860 Decrementer Test PASSED 860 Time Base Timer Test PASSED Print Hex Test should 89ABCDEF
9. the transmitter can only be accessed via the FDL transmit register The only exception is when the transmitter and receiver can be made multi frame synchronized The T1 FDL interface consists of three signals Receive data RXD Transmit data TXD Clock CLKx The following table indicates which QUICC pins are dedicated to the FDL FDL QUICC Port Assignments FDL for Port P2 FDL for Port P1 Pin Function Pin Function PA 15 RXD1 PA 13 RXD1 PA 14 TXD1 PA 12 TXD1 PA 6 CLK2 PA 4 CLK4 1 CLK2 is derived from the receive clock RCLK for TDMA Fig 6 1 and the following signal list indicate how the QUICC is connected to the DS2151Q T1 or DS2153Q E1 interface controller The module provides factory installed optional configuration resistors to address a variety of options The DS2151Q has two onboard two frame 386 bits elastic stores receive side and transmit side and the DS2153Q has one onboard two frame 512 bits elastic store These elastic store buffers are not available for use and should always be bypassed The transmit and receive link lines are the 4 KHz serial data lines of the FDL interface The QUICC must be initialized appropriately to utilize the appropriate RXDx and TXDx signals There are not enough resources in the QUICC to support the transmit link clock This means that TLINK line does not have a clock line to frame data and FDL data can only be read using the FDL transmit register The only
10. C100 00CC 4C Long Mailbox register 3 C100 00D0 DF 50 5C reserved C100 00E0 60 Long PCI to Local Doorbell register C100 00E4 64 Long Local to PCI Doorbell register C100 00E8 68 Long Interrupt Control Status C100 00EC 6C Long EEPROM Control PCI Command Codes User I O amp Init Control register C100 00F0 70 Long PCI Configuration ID register PCI9060ES INITIALIZATION The following tables describe how the PCI9060ES PCI Configuration Local Configuration and Shared Runtime registers are initialized to set up the PCI bridge and turn on the neces sary functions The PCI bridge is used to decode portions of the local address bus and the PCI address bus At reset the PCI9060ES reads a serial EEPROM to initialize the PCI bridge Five long words of data are stored in the 128 kilobyte EEPROM These long words sequentially program the PCI Configuration registers listed in Table 7 4 and two Shared Runtime registers Mailbox registers 0 and 1 listed in Table 7 6 10002367 02 PmT1 and PmE1 User s Manual PMC PCI Interface PCI9060ES Initialization The serial EEPROM may be reprogrammed to configure the PCI bridge in other ways Bits 27 24 of the PCI9060ES EEPROM control register C100 00EC are used for reading and writing the EEPROM Refer to the NS93CS46 data sheet listed in Table 1 5 for a description of the EEPROM s programming instructions and the PCI9060ES data sheet for the sequence in which the data is stored Table 7 4
11. FF00 0240 PISCR 0082 Clocks and Reset FF00 0280 SCCR 0200 0000 Input Output Por E PmT1 and PmE1 User s Manual 10002367 02 Description SIU module configuration System protection control Base register bank 0 Option register bank 0 Base register bank 1 Option register bank 1 Base register bank 2 Option register bank 2 Base register bank 3 Option register bank 3 Base register bank 4 Option register bank 4 Base register bank 6 Option register bank 6 Machine A mode Timebase status and control PIT status and control System clock control Central Processing Unit MPC860P Exception Handling Table 3 4 Physical Required Address hex Register Hex Format FF00 0950 PADIR 000A FF00 0952 PAPAR 0000 FF00 0954 PADDR 0000 BRGs FF00 09F0 BRGC1 10144 FF00 09FA4 BRGC2 10144 SMCs FF00 0A82 SMCMR1 4823 FF00 0A92 SMCMR2 4823 PIP FF00 0AB8 PBDIR 0030 FF00 0ABC PBPAR 00CO FF00 0AC2 PBODR 0010 SI FF00 0AEO SIMODE 1000 0000 FF00 0AEC SICR 0000 0000 MPC860P EXCEPTION HANDLING Description continued Port A data direction register Port A pin assignment register Port A open drain register BRG1 configuration register BRG2 configuration register SMC1 mode register SMC2 mode register Port B data direction register Port B pin assignment register Port B open drain register SI mode register SI clock route Each type of CPU exception transfers control to a different address in the vector table The ve
12. FPtr unsigned char c FromFifo FPtr Ptr struct Fifo FPtr unsigned char Ptr These functions provide the necessary interface to initialize read and write a software FIFO The FIFO is used for buffering serial I O when using transparent mode but could be used for a variety of applications All three functions accept a pointer FPtr as the first argu ment to a FIFO management structure This FIFO structure is described briefly below struct Fifo unsigned char Top unsigned char Bottom int Length unsigned char Front unsigned char Rear int Count Fifo The function InitFifo initializes the FIFO control structure specified by FPtrto use the unsigned character buffer starting at StartAddr that is of size Length The function ToFifo writes the byte c to the specified FIFO This function returns TRUE if there is room in the FIFO before adding cto the FIFO or FALSE if the FIFO is full The function FromFifo reads a byte from the specified FIFO If a character is available it is written to the address specified by the pointer Ptr and the function returns TRUE If no char acter is available the function returns FALSE IsLegal IsLegal Type Str unsigned char Type char Str This function is used to determine if the specified character string Str contains legal values to allow the string to be parsed as decimal hex uppercase or lowercase The function IsLe gal traverses the character string until a NULL
13. PCI9060ES PCI Configuration Register Initialization Hex Value Local Bus atthe byte swapped Address hex Register PCI9060ES atthe CPU Notes C100 0000 PCI Configuration ID 1223 2312 This read only register contains Emerson s vendor ID C100 0002 I PCI Configuration ID 0004 0400 This read only register contains the PmT1 device ID C100 0002 1 PCI Configuration ID 0005 0500 This read only register contains the PmE1 device ID C100 0004 PCI Command 0147 4701 Enable I O and memory space accesses Enable PCI9060ES to act as a bus master Enable parity checking and the SERR driver C1 00 0030 PCI Expansion ROM 00000000 00000000 Address decode enable and expansion ROM Base base address accesses C1 00 0008 PCI Revision ID 01 01 This read only register contains the PmT1 and PmE1 s revision number C1 00 0009 PCI Class Code 0B20000 00200B No interface is defined C100 001 82 PCI Base Address XXXXXXXX XXXXXXXX PCI to local base address is 0000 000046 for memory access to PCI host sets local address space C1 00 003cl PCI interrupt Line 00 00 C1 00 003D PCI Interrupt Pin 01 01 This read only register indicates that the PCI9060ES uses INTA as its interrupt pin C1 00 003E PCI Min_Gnt 00 00 This read only register specifies a burst period of 0 seconds C1 00 003F PCI Max Lat 00 00 This read only register specifies a maximum latency of 0 seconds 1 These registers are initialized by the serial EEPROM 2 These registers are not init
14. ations Repairs to certified equipment should be coordinated by a representative designated by the supplier Any repairs or alterations made by the user to this equipment or equipment malfunctions may give the telecommunications company cause to request the user to dis connect the equipment Users should ensure for their own protection that the electrical ground connections of the power utility telephone lines and internal metallic water pipe system if present are con nected together This precaution may be particularly important in rural areas Users should not attempt to make such connections themselves but should contact the appropriate electric inspection authority or electrician as appropriate The standard connecting arrangement code telephone jack type for this equipment is CA48C 10002367 02 PmT1 and PmE1 User s Manual mn Regulatory Agency Warnings amp Notices continued EC Declaration of Conformity According to EN 45014 1998 Manufacturer s Name Emerson Network Power Embedded Computing Manufacturer s Address 8310 Excelsior Drive Madison Wisconsin 53717 Declares that the following product in accordance with the requirements of 2004 108 EEC EMC Directive and 1999 5 EC RTTE Directive and their amending directives Product PMC Module Model Name Number PmT1 and PmE1 01439143 xx has been designed and manufactured to the following specifications EN55022 1998 Information Technology Equipment
15. 00004g The following table shows the register block map for the CPM portion of the MPC860P Please refer to the MPC860 Power QUICC User s Manual for descriptions of the registers in each register block MPC860P CPM Register Block Map Physical Address hex Acronym FF00 0930 FF00 0950 FF00 0980 FF00 09CO FF00 09F0 BRG FF00 0A00 SCC1 FF00 0A20 SCC2 FF00 0A40 SCC3 FF00 0A60 SCCA FF00 0A82 SMCI FF00 0A9 SMC2 FF00 0A82 eS FF00 0AEO SI 10002367 02 Register Block Name CPM Interrupt Control Input Output Port CPM Timers Communication Processor Baud Rate Generators Serial Communications Controller 1 Serial Communications Controller 2 Serial Communications Controller 3 Serial Communications Controller 4 Serial Management Controller 1 Serial Management Controller 2 reserved Serial Interface PmT1 and PmE1 User s Manual 5a Serial IO The Communications Processor Module CPM Register Initialization Format Some of the CPM registers must be initialized as described in Table 5 2 Table 5 2 CPM Initialization Values Physical Address Required hex Acronym Hex Format Description Input Output Port FF00 0950 PADIR 000A Port A Data Direction register FF00 0952 PAPAR 0000 Port A Pin Assignment register FF00 0954 PAODR 0000 Port A Open Drain register BRGs FF00 09F0 BRGC1 10144 BRG1 Configuration register FF00 09F4 BRGC2 10144 BRG2 Configuration register FF00 0AC2 PBODR 0010 Port B Open Dr
16. 23 Ke c12 lt TDM Rip 24 B8 A12 TDM Ring 25 A8 C13 RS422 TXD 26 E12 A13 RS422 TXD 27 o o I 28 C12 Al4 RS422 RXD 29 B12 C15 RS422 RXD 30 A12 A15 RS422 RTS 31 E13 Cl6 RS422 RXCLK 32 D13 A16 RS422 CTS 33 k 34 E 35 A13 c18 RS422 RTS 36 E14 A18 GND 37 38 an 39 40 A14 A20 RS422 RXCLK 41 E 42 43 44 B15 A22 RS422 TXCLK 45 A15 C23 RS422 TXCLK 46 E16 A23 RS422CTS 47 E E ps 48 E EL 49 50 51 52 53 54 55 56 57 E 58 59 E 60 m m 61 62 63 64 1 All xTIP and xRING signals are routed to P14 directly from the Dallas interface and do not provide circuit protection See Regulatory Agency Warnings and Notices in preface E PmT1 and PmET User s Manual 10002367 02 TDM Interface Table 6 1 The Time Division Multiplexor TDM processes channelized serial data such as T1 and E1 The data channels can be routed internally to the QUICC to any of the SCC or SMC control lers Each port can be configured to be either T1 or E1 at manufacturing The TDM interface consists of Three signals for the transmitter L1TXD L1TCLK L1TSYNC Three for the receiver LTRXD LTRCLK LTRSYNC Each direction has a data clock and sync signal The PmT1 supports two T1 TDM ports and the PmE1 supports two E1 TDM ports The TDM signals are
17. 5 5 jJ E 5 5 customer support See technical support cycle frame signal PCI 7 10 D data count records See S5 records datairecordi suisse etes 8 22 deadlocked cycle PCI 7 6 debugging applications monitor 8 17 decrementer counter 3 5 device ID 1er eens 7 4 device select signal PCl 7 10 diagnostics power up 8 4 DMAtransfers 2000 5 2 download configuring the port 8 20 from monitor 8 18 Download monitor group 8 2 DRAM ii i vehere ttr PC EEDHOS 4 2 memory size andtype 4 3 memorytype eese 4 3 MPC860 controller 4 2 10002367 02 dual port RAM ssssse 5 3 E E1 DS2153Q initialization sess 6 1 line impedance 6 4 overview eese eee eee 1 1 TDM interface 6 1 EEPROM ida stehe 4 1 memory map sseeee 4 2 nonvolatile memory commands 8 13 PCI bridge initialization 7 3 EEPROM control register 7 4 EIA 232 See serial I O end of filerecord 8 22 EPROM booting application programs 8 8 equipment for setup 2 5 errors parity 000 7 11 ESC key ree enn y eR mtn 8 5 ESD prevention 2 1 examples hex Intel file 0 8 23 S record file 04 8 26 exception handling 3 3 extended address record 8 21 F facility data link FDL
18. 7 9 Connector P11 and P12 Pin Assignments Pin P11 Signal P12 Signal Pin P11 Signal P12 Signal 1 no connect 12V 2 12V no connect 3 GND no connect 4 INTA no connect 5 no connect no connect 6 no connect GND 7 BUSMODE1 GND 8 no connect no connect 9 no connect no connect 10 no connect no connect 11 GND BUSMODE2 12 no connect no connect 13 CLK RST 14 GND BUSMODE3 15 GND no connect 16 GNT BUSMODE4 17 REQ no connect 18 no connect GND 19 5V AD30 20 AD31 AD29 21 AD28 GND 22 AD27 AD26 23 AD25 AD24 24 GND no connect 25 GND IDSEL 26 C BE3 AD23 27 AD22 no connect 28 AD21 AD20 29 AD19 AD18 30 no connect GND 31 5V AD16 32 AD17 C BE2 33 FRAME GND 34 GND no connect 35 GND TRDY 36 IRDY no connect 37 DEVSEL GND 38 5V STOP 39 GND PERR 40 LOCK GND 41 no connect no connect 42 no connect SERR 43 PAR C BE1 44 GND GND 45 5V AD14 46 AD15 AD13 47 AD12 GND 48 AD11 AD10 49 ADO9 AD08 50 5V no connect 10002367 02 PmT1 and PmE1 User s Manual PMC PCI Interface PMC Connector Pin Assignments Pin P11 Signal P12 Signal Pin P11 Signal P12 Signal 51 GND AD07 52 C BEO no connect 53 AD06 no connect 54 ADO5 no connect 55 AD04 no connect 56 GND GND 57 5V no connect 58 AD03 no connect 59 AD02 GND 60 AD01 no connect 61 ADOO no connect 62 5V no connect 63 GND GND 64 no connect no connect PCI Bus Control Signals The following signals for the PCI interface are available on connectors P11 and P12 Refer to the PCI speci
19. DS2151 Channel 0 1005 DS2153 DS2151 Channel 0 TDMA Register Write 1015 DS2153 DS2151 Channel 1 TDMB Register Write 1105 DS2153 DS2151 Channel 0 TDMA Register Read 1115 DS2153 DS2151 Channel 1 TDMB Register Read Address 8 Address of a T1 or E1 controller register determined by 2153 or 2151 interface controller For ID register and interrupt register cycles the address field is ignored Data 8 Register Read Write Data On read cycles the MDI protocol requires thatthe accessing application continue to clock the interface while waiting for the MDIO line to be driven low Once low the following 8 bits will be valid data 1 These are read only bits You must enable disable or clear interrupts at the DS2153 DS2151 framer chip itself The SR1 status register on each framer chip corresponds to bits 5 and 7 Similarly the SR2 status register on each framer chip corresponds to bits 4 and 6 FRONT PANEL I O Connectors P1 and P2 provide the TDM signals for the PmT1 and PmE1 front panel I O con figurations The manufacturer part number for this eight pin connector is Stewart Connec tor Systems SS 610808 NF P 5 Figure 6 3 Front Panel I O Connectors P1 and P2 P2 P1 TDMA Channel 0 TDMB Channel 1 Pin 1 H PmT1 and PmET User s Manual 10002367 02 TDM Interface Front Panel O The recommended cable assembly Emerson part number C308A009 05 for P1 and P2 is shown in Fig 6 4 The manufacture
20. L1TSYNCB PC7 ke 4 TSYNC LIRSYNCB PC6 kg RSYNC L1TXDB PAI 1 gt gt TSER L1RXDB PAT 0 3 RSER DS2151Q BRGO4 L1RCLKB PA2 amp 3 RCLK PmT1 6 L1TCLKB PAO TCLK or P1 CLK8 BRGO4 PAI DS2153Q I o PmE1 TXD2 PA12 gt HDI PA12 TLINK RXD2 PA13 M RLINK TLCLK CLK4 PA4 RLCLK Channel 1 The following list describes how these signals are used and how they are to be configured for the variety of options that can be supported The receive clock signal is always driven by the E1 or T1 controller The controller provides the ability to determine if the line interface has successfully synchronized to the line inter face The QUICC must always be configured to accept the receive clock on L1RCLKx If the appli cation requires the transmit clock TCLK to be derived from RCLK then RCLK can be routed to an internal baud rate generator and driven as TCLK 10002367 02 PmT1 and PmE1 User s Manual gH TDM Interface The T1 or 1 Line Interface TCLK TSYNC RSYNC TSER RSER Note The transmit clock must be driven to the T1 or E1 controller The clock will be driven by a baud rate generator In this case the baud rate generator is driven by the RCLK input or sys tem clock The TCLK line
21. Misc PowerUpMemcClr Clear memory on power up True True False ClrMemOnReset Clear memory on reset False True False PowerUpDiags Run diagnostics on power up On On Off ResetDiags Run diagnostics on reset Off On Off Bus Monitor Turn bus monitor on or off Off On Off NOTE Do not change this default setting CountValue Choose shortest 0 to longest 7 duration for 7 0 1 2 3 4 5 6 7 autoboot countdown DoModConfig Module configuration Sets the PxBReqTmr and True True False PlxPciRetTmr values PIxBReqTmr Select value of BReq timer in PLX register 0x94 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PlxPciRetTmr Select value of PCI target retry delay in PLX 15 0 1 2 3 4 5 6 7 8 9 10 11 register 0x98 12 13 14 15 BootParams BootDev Select boot device EPROM None Serial ROM Bus EPROM LoadAddress Define load address 0x40000 B PmT1 and PmET User s Manual 10002367 02 Monitor Power up Reset Sequence Factory Fields Purpose Default Optional Values RomBase Define ROM base Oxfff30000 This field is used only when BootDev is defined as ROM RomSize Define ROM size 0x40000 This field is used only when BootDev is defined as ROM DevType Define device type 0 Whether you use this field depends on the application When BootDev is defined as Bus or ROM DevType refers to a device type When BootDev is defined as Serial DevType selects a download format 0 for hex
22. NvMonSize NvMonAddr These functions allow the nonvolatile library functions to operate on the nonvolatile mem ory sections without actually compiling the board configuration files into the library The NvHkOffset and NvMonOffset functions describe where in the nonvolatile memory device the Emerson and monitor defined data sections begin In general the Emerson defined data section and the monitor data section reside in the user writeable section of the nonvolatile memory device The returned value is the offset in bytes from the begin ning of the device in which the section is loaded The functions NvMonSize and NvMonAddr return the size and location of the nonvolatile monitor configuration data structure This again allows other monitor facilities and applica tion programs to get at the monitor configuration structure without having to know too much about the monitor NvRamAcc unsigned char NVRamAcc Mode Cnt Val unsigned long Mode Cnt unsigned char Val NVRamAcc function provides access to the lower level utilities of the X24C16 device The Mode indicates one of four access types READ READ PROBE WRITE and WRITE PROBE If Modeis zero a byte is read from nonvolatile memory If Mode is one a byte is written to nonvolatile memory E PmT1 and PmE1 User s Manual 10002367 02 Monitor MPC860P Specific Functions Description Description The Cnt indicates the byte location to be modified and assumes the no
23. PCI to local remap address is 0000 0000 Enable PCI to local accesses Enable PCI direct slave locked sequences Little endian ordering Disable local expansion ROM Slave BREQo delay is 24 clocks Enable local bus BREQo Memory space local bus width is 32 bits There are no memory space internal wait states Enable memory space ready input Disable bterm input and bursting The slave PCI write mode is one Target retry delay is 120 clocks Local to PCl range is 512 MB PCI memory space is mapped at 4000 0000 PCI I O and configuration space is mapped at 6000 000046 Local to PCl remap address is 0000 0000 Enable master I O memory accesses and lock input Local to PCl accesses are not converted to PCI configuration cycles PmT1 and PmE1 User s Manual PMC PCI Interface PCI9060ES Initialization Table 7 6 PCI9060ES Shared Runtime Register Initialization Hex Value Local Bus atthe byte swapped Address hex Register PCI9060ES atthe CPU Notes C100 00CO0 Mailbox 0 00000000 00000000 These registers are initialized by the serial EEPROM C10000CO0 will be 35000000 upon successful completion of the Monitor power up diagnostics C100 00C4 Mailbox 1 00000000 00000000 These registers are initialized by the serial EEPROM Deadlocked Cycles When a local bus master attempts to access the PCI bus at the same time a PCI bus master attempts to access the local bus a deadlocked cycle results Neither master
24. PR and PC leads PC board traces carrying tip and ring leads shall have sufficient spacing to avoid surge breakdown E PmT1 and PmET User s Manual 10002367 02 Regulatory Agency Warnings amp Notices continued Caution A Information shall be provided as to the power source requirements See the PmT1 and PmE1 power requirements in the hardware manual If the device is enclosed in an assembly and not readily accessible a label shall be placed on the exterior of the cabinet listing the registration number of each PmT1 and PmE1 con tained therein The final assembler shall provide in the consumer instructions all applicable Network Con nection Information INDUSTRY CANADA RULES AND REGULATIONS CS03 NOTICE The Industry Canada label identifies certified equipment This certification means that the equipment meets certain telecommunications network protective operational and safety requirements as prescribed in the appropriate Terminal Equipment Technical Requirements document s The Department does not guarantee the equipment will oper ate to the user s satisfaction Before installing this equipment users should ensure that it is permissible to be connected to the facilities of the local telecommunications company The equipment must also be installed using an acceptable method of connection The customer should be aware that compliance with the above conditions may not prevent degradation of service in some situ
25. Radio disturbance characteristics Limits and methods of measurement EN55024 1998 Information Technology Equipment Immunity characteristics Limits and methods of measurement EN300386 V 1 3 1 Electromagnetic compatibility and radio spectrum matters ERM Telecommunication network equipment EMC requirements As manufacturer we hereby declare that the product named above has been designed to comply with the relevant sections of the above referenced specifications This product complies with the essential health and safety requirements of the EMC Directive and RTTE Directive We have an inter nal production control system that ensures compliance between the manufactured products and the technical documentation Bill Fleury Compliance Engineer Issue date December 14 2007 C EMERSON Network Power m PmT1 and PmE1 User s Manual 10002367 02 Contents 1 Overview 5 Serial 1 O Components and Features 1 1 The Communications Processor Module5 1 Functional Overview 1 1 CPM Register Initialization Format 5 2 Physical Memory Map 1 2 RISC Controller LL 5 2 Additional Information 1 4 CPM Interrupt Handling 5 3 Product Certification 1 4 Dual Port RAM eeeeee 5 3 RoHS Compliance 1 6 General Purpose Timers 5 4 Terminology and Notation 1 6 Independent DMA IDMA Channe
26. Remote Host Commands Where Example indicates that the start address segment value is one and the start address offset value is 2 so the absolute start address is 1216 gt 04003000902BB4FD60 loads byte 9046 to address 4016 loads byte 2B4g to address 4116 loads byte B44g to address 4216 loads byte FD1gto address 4346 gt 00000001FF terminates the file Motorola S record Format S records are named for the ASCII character S which is used for the first character in each record After the S character is another character that indicates the record type Valid types are 0 1 2 3 5 7 8 and 9 After the type character is a sequence of characters that represent the length of the record and possibly the address The rest of the record is filled out with data and a checksum The checksum is the one s complement of the 8 bit sum of the binary representation of all elements of the record except the S and the record type character In other words if you sum all the bytes of a record except for the S and the character immediately following it with the checksum itself you should get FF for a proper record SO records User Defined SO0nndid2d3 dncs so indicates the record type nn is the count of data and checksum bytes di dn are the data bytes cs is the checksum 0 records are optional and can contain any user defined data gt S008763330627567736D In this example the length of the fiel
27. Y rbv 8 9 bootserial lsuleeuuueu 8 9 Help Commands 8 10 lielpzcz esses setecepeeeecenp ihe 8 10 Memory Register Commands 8 10 checksummem ss 8 10 Cleaim mem 43st opns Ue UU ETE 8 10 CMPMEM cee eee eee eee 8 10 COPYMEM s s20 cdeccevserses as 8 10 displaymem esses 8 11 fillierm i i565 4S sese then 8 11 findmem ssesussuue 8 11 findnotmem uus 8 11 TIGER s see sccdsew RR RR RRREREER 8 11 teadmietm sooo ever eR YR 8 11 Setmeltls 22 eo verertu EE MUS 8 12 SWAPMEM eee eee ee eee 8 12 Tes tmielil s ove eer o rer SEEDS 8 12 a a e PROLES 8 12 WIILeImelTizecs coe nee x EP REEF 8 12 WIILeSLI i ceobneeecreet tK KR rS 8 13 NVRAM Commands 8 13 nvdisplay ee eee ee eee 8 13 AVIN ss cece cece cera awed es 8 14 DWODen vaste kn RE RE RS 8 14 DVset l c ned e RR RRRER RES 8 14 nvupdate eee eee 8 15 Configuring the Default Boot piu UM 8 15 Power up Diagnostic Test Commands 8 17 cachetest 2 cecorver yx nee 8 18 eepromtest 0000 8 18 Temtest 5 enececece ebrei 8 18 Remote Host Commands 8 18 n iess 8 19 10002367 02 Es PmT1 and PmE1 User s Manual download 0c cence 8 19 Binary Download Format 8 19 transmode suuue 8 20 Configuring the Download Port 8 20 Hex Intel Format 8 21 Extended Address Reco
28. and PmE1 User s Manual 8 33 Monitor MPC860P Specific Functions 8 34 Description Table 8 6 typedef struct HANDLER handler HANDLERPARM parameter JHANDLERSTRUCT HANDLERSTRUCT ConnectHandler unsigned long Vector HANDLER Handler ConnectHandler Vector Handler unsigned long Vector int Handler DisConnectHandler Vector unsigned long Vector probe DirFlag SizeFlag Address Data char DirFlag SizeFlag unsigned long Address unsigned long Data These functions are the MPC860P processor specific functions that provide interrupt and exception handling support The following table defines those exceptions which have interrupt vectors assigned to them by the monitor When connecting an interrupt handler to these exceptions the spec ified vectors must be used Assigned Exception Vectors Vector Cause of Exception 0x02 Machine check 0x06 Alignment error 0x09 Decrementer interrupt m mE Ox0c SYSCALL E 0x10 Software emulation 0x11 Instruction TLB miss 0x12 Data TLB miss 0x13 Instruction TLB error 0x14 _ Data TLB error 0x20 Hardware interrupt level 0 IRQO 0x21 Software Interrupt level 0 0x22 Hardware interrupt level 1 IRQ1 0x23 Software Interrupt level EN 0x24 Hardware interrupt level 2 IRQ2 0x25 Software Interrupt level 2 EN 0x26 Hardware interrupt level 3 IRQ3 PmT1 and PmE1 User s Manual 10002367 02 Monitor MPC860
29. as the base address of a shared memory communications structure described below gt struct BusComStruct unsigned long MagicLoc 10002367 02 PmT1 and PmE1 User s Manual Monitor Boot Commands Description unsigned long CallAddress The structure consists of two unsigned long locations The first is used for synchronization and the second is the entry address of the application The sequence of events used for loading an application is described below The host board waits for the target this board to write the value 0x496d4f6b character string ImOk to MagicLoc to show that the target is initialized and waiting for a download The host board downloads the application program over the bus writes the application start address to CallAddress and then writes 0x596f4f6b character string YoOk to MagicLoc to show that the application is ready for the target Target writes value 0x42796521 character string Bye to MagicLoc to show that the application was found The target then calls the application at CallAddress When the application is called four parameters are passed to the application from the non volatile memory boot configuration section The parameters are seen by the application as shown below Application Device Number RomSize RomBase unsigned char Device Number unsigned long RomSize RomBase These parameters allow multiple boards using the same facility to receive
30. board from a rack while power is applied at risk of damage to the board Power Requirements The Emerson PmT1 and PmE1 circuit board typically requires 6 7 watts maximum 10002367 02 PmT1 and PmE1 User s Manual EJ Setup Reset Methods Table 2 2 Table 2 3 Power Requirements Volts Range volts Maximum Current Sa rT O 5 596 1 16 A typical 1 Running on card memory test The exact power requirements for the PmT1 and PmE1 circuit board depend upon the spe cific configuration of the board including the CPU frequency and amount of memory installed on the board Please contact Emerson Technical Support at 1 800 327 1251 if you have specific questions regarding the board s power requirements Environmental Considerations As with any printed circuit board be sure that air flow to the board is adequate Chassis con straints and other factors greatly affect the air flow rate The environmental requirements are listed in Table 2 3 Environmental Requirements Environment Range Relative Humidity Operating Temperature 0 to 55 Centigrade ambient Not to exceed 95 non at board condensing Storage Temperature 40 to 70 Centigrade Not to exceed 95 non condensing Air Flow 50 linear feet minute n a RESET METHODS The entire board is reset on power up A baseboard PCI reset causes a PORESET of the PmT1 and PmE1 The PCI9060ES may be programmed to initiate a software controlled hard reset from the PCI
31. can complete its cycle because the other device already owns the required resource The PCI9060ES can quickly force one of the masters to relinquish ownership of its bus and try the cycle again later Consequently retrying one side favors the other Retries on Local Direct Master Cycles Local Direct Master cycles are transfers that originate from a local bus master and access the PCI bus The PCI9060ES programmable Direct Slave BREQo Delay Timer and BREQo retry pin control Local Direct Master cycle retries If enabled this timer counts down when a Local Direct Master cycle is pending and unable to access the PCI bus If the count expires a true condition on the BREQo pin signals the local master to relinquish the local bus and retry its cycle later Retries on Direct Slave Cycles Direct Slave cycles are transfers that originate from a PCI bus master and access the local bus The PCI9060ES programmable PCI Target Retry Delay Timer controls Direct Slave cycle retries This timer counts down while a Direct Slave cycle is pending If the count expires the PCI9060ES signals a target retry condition informing the PCI master to relinquish the PCI bus and retry its cycle later Assigning Priorities When assigning a bus priority for deadlocked cycles consider whether a series of transfers onone side ofthe bridge could starve access on the other side Also consider whether there may be other adverse effects of retrying Local Direct Master cycles
32. commands without problems but may have problems if text editing is attempted If the host is a UNIX system and you have a hex Intel file called foo hex in a directory foodir to download you can use the following sequence PmT1 or PmE1 2 x transmode UNIXprompt cd foodir UNIXprompt gt cat foo hex Press CTRL Return EEE Ue ALIE dots continue during download PmT1 or PmE1 2 x Configuring the Download Port In this example the NVRAM command nvdisplay changes fields in the Download group which contains fields for port selection baud rate parity number of data bits and number of stop bits A cable reverser might be necessary for the connection At the monitor prompt type gt nvdisplay Press lt cr gt until the Download group is displayed 2 PmT1 and PmE1 User s Manual 10002367 02 Monitor Remote Host Commands on Do A W Press E to edit the group Press lt cr gt until the Baud field is displayed Type a new value Change other fields in the same way cr over all fields whether you edit them or not until the monitor prompt reappears Type nvupdate to save the new value Hex Intel Format Hex Intel format supports addresses up to 20 bits one megabyte This format sends a 20 bit absolute address as two possibly overlapping 16 bit values The least significant 16 bits of the address constitute the offset and the most significant 16 bits constitute the seg ment Segments can
33. converted to T1 or E1 signaling by either the DS2151Q or DS2153Q transceivers and are routed to the front panel connectors P1 and P2 Table 6 1 and Table 6 3 indicate which QUICC pins are dedicated to the TDM and how the T1 or E1 signals from the trans ceiver are routed to the connectors Configurations that route T1 or E1 out the P14 connector bypass the protection circuitry The FCC Part 68 and UL1950 certification can be met by providing an external circuit pro tection card The DS2153Q on the PmE1 requires specific initialization reference Application Note 342 DS2151 DS2153 Initialization and Programming Dallas Semiconductor 102899 Set CCR2 to 0x04 This causes the framer to switch to RCLK if TCLK stops Wait for at least 10 ms Zero all of the framer registers except the LOTCMC bit that was set in step 1 This is important since the framer has no reset and cannot be guaranteed to be in an absolute known state after power up Configure the desired framer settings Set the LIRST bit in CCR3 Clearthe LIRST bit in CCR3 TDM to T1E1 Port Connections for TDMB P1 QUICC Pins to Transceiver Direction DS215xQ Function PA 11 L1TXDB P SER PA 0 LITCLKB gt TCK PC 7 LITSYNCB TSYNC PA 10 L1RXDB 8 RSER PA 2 LIRCLKB 8 RCIK PC 6 LIRSYNCB 8 RSYNC 10002367 02 PmT1 and PmE1 User s Manual 6a TDM Interface Table 6 2 Table
34. exception to this case is if the transmit and receive sec tions can be forced to be multi frame synchronized Then RLCLK input can be used for trans mitter as well The receive link clock is a 4 KHz clock used to frame data on the RLINK line H PmT1 and PmE1 User s Manual 10002367 02 TDM Interface The Management Data Interface MDI Table 6 6 Figure 6 2 THE MANAGEMENT DATA INTERFACE MDI The MDI or Management Data Interface is a 3 wire protocol which allows access to the mod ule resources registers and interrupts using the minimum resources necessary This inter face consists of Data MDIO Clock MDCLK and Interrupt MDINT lines The MDI uses control pins PCO PC2 which are not likely to conflict with any MPC860P dedi cated functions MDI Port Connections Pin Description Port MDINT MDI Interrupt Request PC 15 MDC MDI Clock PC 14 MDIO MDI I O Pin PC 13 The protocol used to communicate involves sequencing bit patterns to indicate the start command address data and close of a transaction Fig 6 2 shows how the interface is accessed This protocol is modeled after the existing standards for serial ROM and other micro wire type non volatile memory devices MDI Interface Protocol aec ng En i i pF Pi Fn Vs i Ka a iL a FE VT YF a dP HT Start Opcode 3 Register Address 8 Bits Register Data 8 Bits Note The MD interrupt line MDINT connects to the MPC860P at PC 15 which must se
35. features of the QUICC MC68360 communications processor module CPM This chapter is an overview of the processor logic on the PmT1 and PmE1 It includes information on the CPU excep tion handling and processor reset MPC860P Features Feature Description Instruction Set 32 bit System Clock Rate 80 MhZ Data Bus 32 bit Address Bus 32 bit Cache 16K instruction 8K data MMU 32 entr y instruction and data Translation Look aside Buffer TLB Dual port RAM 8K ATM 10 100 base T Ethernet QMC microcode for multichannel HDLC support Serial Channel four SCCs two SMCs one SPI and on IC interface System Interface Memory controller internal and external bus interface units real time clock Unit SIU PCMIA ATA interface and JTAG TAP DMA channels 16 virtual SDMA and 2 IDMA Dynamic bus sizing 8 16 or 32 bits Voltages 3 3V operation with 5V TTL compatibility Beyond the usual CPU functions the MPC860P provides ADRAM controller is contained in the system interface unit SIU The memory controller is described in the On card DRAM Section e Four high speed SCC serial ports are supported by the CPM The serial interface is described in Chapter 5 MPCS860P INITIALIZATION Some of the MPC860P registers must be initialized with Emerson specific values The val ues in the following tables assume a PmT1 and PmE1 configuration of 9600 baud 40 MHz and CPU speed The relevant special purpose registers on the MPC860P are acc
36. for TDM channel B is routed to BRG04 to support this option The data signals must always be driven by the T1 or E1 controller The receive sync signal is always an output of the T1 or E1 controller and the transmit sync must be programmed to be an output In both cases the QUICC must be programmed to accept the sync lines on LTTSYNCx and L1RSYNCx Additional factory installed optional configuration resistors can be provided which connect both sync and clock lines together This option is non standard and is only useful when the application requires the T1 or E1 controller transmit and receive sections be multi frame synchronized The transmit serial data is driven by the QUICC from the L1TXDx and the receive data is driven by the T1 or E1 controller The QUICC must be initialized appropriately to utilize the L1TXDx and L1RXDx signals THE T1 OR E1 LINE INTERFACE The PmT1 and PmE1 modules that route channels out the front panel provide protection circuitry which protects equipment from overvoltage and overcurrent stresses from light ning strikes power crosses and other noise impairments This circuitry is necessary in cases where the connections are outside the customers building and in some cases within the same building depending on the application The requirements for T1 equipment are specified by FCC Part 68 lightning UL1950 AC Hazards Bell Core TR TSY 000007 and AT amp T Publication 62411 Similar requirements are specified
37. hex Size Register Name C100 0080 00 Long Local Address Space 0 Range register PCI to local bus C100 0084 04 Long Local Space 0 Local Base Address register PCI to local bus C100 0088 08 Long Local Arbitration register C100 008C 0C Long Big Little Endian Descriptor register C100 0090 10 Long Local Expansion ROM Range register PCI to local bus C100 0094 14 Long BREQo Control register C100 0098 18 Long Local Bus Region Descriptor for PCI to Local Accesses register C100 009C 1C Long Local Range register Direct Master to PCI PmT1 and PmE1 User s Manual 10002367 02 PMC PCI Interface PCI9060ES Initialization Table 7 3 Local Bus PCI Offset Address hex Address hex Size Register Name continued C100 00A0 20 Long Local Bus Base Address register Direct Master to PCI memory C100 00A4 24 Long Local Base Address For Direct Master to PCI 1 O CFG register C100 00A8 28 Long PCI Base Address register Direct Master to PCI C100 00AC 2C Long PCI Configuration Address register Direct Master to PCI IO CFG Shared Runtime Registers The Shared Runtime registers are a collection of mailbox interrupt doorbell and configura tion registers that may be accessed from the local bus and the PCI bus Shared Runtime Registers Local Bus PCI Offset Address hex Address hex Size Register Name C100 00C0 40 Long Mailbox register 0 C100 00C4 44 Long Mailbox register 1 C100 00C8 48 Long Mailbox register 2
38. is reached Each character is verified accord ing to the Type argument The effects of specifying each type are described below PmT1 and PmE1 User s Manual 10002367 02 Monitor Standard Monitor Functions Table 8 7 Description IsLegal Function Types Type Value Legal Characters DECIMAL 0x8 0 9 HEX 0x4 0 9 A F a f UPPER 0x2 A Z LOWER Ox1 a z ALPHA 0x3 A Z a z If the character string contains legal characters this function returns TRUE otherwise it returns FALSE The string equivalent of the character functions isalpha isupper islower and isdigit can be constructed from this function which deals with the entire string instead of a single character MemMng void Malloc NumBytes unsigned long NumBytes void Calloc NumElements Size unsigned long NumElements Size Free MemLoc unsigned long MemLoc CFree Block unsigned long Block void ReAlloc Block NumBytes char Block unsigned long NumBytes MemReset MemAdd MemAddr MemSize unsigned long MemAddr MemBSize MemStats The memory management functions allocate and free memory from a memory pool The monitor initializes the memory pool to use all on card memory after the monitor s bss sec tion If any of the autoboot features are used the memory pool is not initialized and the application program is required to set up the memory pool for these functions The functions Malloc Calloc and ReAll
39. layer printed circuit board with the following dimensions Circuit Board Dimensions Width Depth Height 5 86 in 148 8 mm 2 913 in 74 0mm 39in 10 0 mm The following figures show the front panel and component maps for the PmT1 and PmE1 circuit board PmT1 and PmE1 Front Panel 10002367 02 PmT1 and PmE1 User s Manual EN 10002367 02 PmT1 and PmE1 Circuit Board e e Figure 2 2 Component Map Top rev 33 PmT1 and PmE1 User s Manual Setup Setup PmT1 and PmE1 Circuit Board Figure 2 3 Component Map Bottom rev 33 RT RTS mzz tds anaa a mr r el U25 U24 U23 U30 U29 3 Md i BB o001234 YYYYY 10002367 02 PmT1 and PmE1 User s Manual EI Setup Installation P1 P2 P3 P11 P12 P14 Connectors The PmT1 and PmE1 circuit board has various connectors see the figures beginning on page 2 2 summarized as follows These connectors are installed for the PmT1 front panel I O configurations See Chapter 6 for pin assignments This is the optional 10 pin BDM JTAG header for viewing processor functions See Table 3 7 for pin assignments These provide a 32 bit PCI interface between the module and the PMC baseboard Pin assignments are shown in Chapter 7 This is the I O connector for
40. number of wait states per cycle For burst cycles the number in the Total Clocks column of Table 4 3 is the total number of CPU clocks for the first access of the four long word burst plus the number of clocks for the second third and fourth cycles The number in the Wait States column is the number of wait states for each of the four accesses PmT1 and PmET User s Manual 10002367 02 Serial I O Table 5 1 The PmT1 and PmE1 module has six TTL serial ports that are supplied by the MPC860P Pow erQUICC The MPC860P supports the serial ports with the following features Communications Processor Module CPM which includes a RISC controller 224 buffer descriptors continuous mode transmission and reception on all serial channels dual port RAM fourteen serial DMA SDMA channels and NMSI mode each serial channel can have its own pins Four serial communication controllers SCCs e Two serial management controllers SMCs for the console and download serial ports Four baud rate generators that are independent i e can be connected to any SCC or SMC allow changes during operation and have autobaud support Protocols in firmware for asynchronous synchronous UARTs HDLC and SS7 For detailed descriptions of the MPC860P features and examples of how to implement them refer to the MPC860 PowerQUICC User s Manual THE COMMUNICATIONS PROCESSOR MODULE The physical base address of the MPC860P is FF00
41. of the test and summarizes the number of passes and failures The memory test can be interrupted by pressing any character um b w 1 base addr top addr Also refer to the functions MemBase and MemTop in Misc Section writemem writes value to a memory location specified by address writemem b w 1 address value e PmT1 and PmE1 User s Manual 10002367 02 Monitor NVRAM Commands Description Description Example 1 writestr writes the ASCII string specified by string to a memory location specified by address The string must be enclosed in double quotes writestr string address NVRAM COMMANDS The monitor uses the I C EEPROM for nonvolatile memory A memory map of the I C EEPROM is given in Table 4 2 earlier in this manual Portions of this nonvolatile memory are reserved for factory configuration and identification information and the monitor The nonvolatile memory support commands provide the interface to the I C EEPROM The nonvolatile commands deal only with the monitor and Emerson defined sections of the nonvolatile memory The monitor defined sections of nonvolatile memory are readable and writeable and can be modified by the monitor nvdisplay is used to display the Emerson defined and monitor defined nonvolatile sections The non volatile memory configuration information is used to completely configure the PmT1 and PmE1 modules at reset The utility command configboard can also be u
42. reconfigured on PCI by the baseboard MPC860 PARALLEL PORT CONFIGURATION The following values set up the MPC860 parallel ports to receive RCLK from the incoming T1 E1 stream route the clock to the respective Baud Rate Generator TDMA BRGO2 TDMB BRGO4 then output the clock from the Baud Rate Generator as TCLK padir Ox44F0 papr OxEFFF pcdir 0x0002 pcpar OxOF00 10002367 02 PmT1 and PmE1 User s Manual EI Central Processing Unit Optional BDM Header Table 3 6 lists the implementation of the MPC860 Port A and C signals used on the PmT1 and PmET module Table 3 6 MPC860P Ports A and C MPC860 Pin MPC860 Signal Use PA15 RXD1 Facility Data Link FDL A PA14 TXD1 FDL A PA13 RXD2 FDL B PA12 TXD2 FDL B PA11 LTTXDB TDMB PA10 L1RXDB TDMB PAS LTTXDA TDMA PA8 LIRXDA TDMA PA7 CLK1 L1RCLKA TDMA PA6 CLK2 TDMA PA5 BRGO2 TDMA PA4 CLK4 FDL PA3 reserved PA2 CLK6 L1RCLKB TDMB PA1 BRGO4 TDMB PAO CLK8 L1TCLKB TDMB PC15 Management Data Interface MDI PC14 MDI PC13 MDI PC12 reserved PC11 reserved PC10 reserved PC9 reserved PC8 reserved PC7 LTTSYNCB TDMB PC6 LIRSYNCB TDMB PC5 LITSYNCA TDMA PC4 LIRSYNCA TDMA PC3 reserved OPTIONAL BDM HEADER An optional 10 pin header P3 is available for examining processor functions The recom mended mating connector is AMP part number 746288 1 The standard pin assignment is
43. select during configuration read and write transactions INTA PMC INTERRUPT A input line is used by the PmT1 and PmE1 to interrupt the baseboard IRDY INITIATOR READY sustained tri state signal indicates that the bus master is ready to com plete the data phase of the transaction 7 10 PmT1 and PmE1 User s Manual 10002367 02 PMC PCI Interface PMC Connector Pin Assignments LOCK LOCK sustained tri state signal indicates that an atomic operation may require multiple transactions to complete PAR PARITY is even parity across AD00 AD31 and C BEO C BE3 Parity generation is required by all PCI agents This tri state signal is stable and valid one clock after the address phase and one clock after the bus master indicates that it is ready to complete the data phase either IRDY or TRDY is asserted Once PAR is asserted it remains valid until one clock after the completion of the current data phase PERR PARITY ERROR sustained tri state line is used to report parity errors during all PCI transac tions REQ REQUEST output pin indicates to the arbiter that a particular master wants to use the bus RST RESET assertion of this input line brings PCI registers sequencers and signals to a consis tent state SERR SYSTEMS ERROR open collector output signal is used to report any system error with cata strophic results STOP STOP sustained tri state signal is used by the current target to request that the bus master st
44. service It is recommended that the customer install an AC surge arrestor in the AC outlet to which this device is connected This is to avoid damaging the equipment caused by local lighten ing strikes and other electrical surges The following table lists each applicable Facility Interface Code FIC along with the Service Order Code SOC and connector jack type for the PmT1 and PmE1 Facility Interface FIC ServiceOrder Jack Code FIC Description Code SOC Type 04DU9 BN 1 54 Mbps AMI Superframe Format SF without 6 0N RJA8C line power 04DU9 DN 1 544 Mbps SF and B8ZF without line power 04DU9 1KN 1 544 Mbps AMI ESF without line power 04DU9 1SN 1 544 Mbps AMI ESF and B8ZS without line power a Combinations of equipment provide full protection to digital service Billing protection and encoded analog protection are provided either by including auxiliary equipment within the registration envelope or by use of a separately registered device Note Thefollowing information and instructions must be given to the final assembler end user The mounting of the PmT1 and PmE1 in the final assembly must be made so that the PmT1 and PmE1 is isolated from exposure to hazardous voltages within the assembly Adequate separation and restraint of cables and cords must be provided The circuitry from the PmT1 and PmE1 to the telephone line must be provided in wiring that carries no other circuitry that is specifically allowed in the rules such as
45. standards include EIA 422 and EIA 485 which offer fea tures such as longer line lengths and multidrop support The UART also supports synchronous mode where a clock is provided with each bit Syn chronous UART mode can provide faster data transfers because there is no need to over sample the data bits HDLC is one of the most common layer 2 protocols of the seven layer OSI model HDLC protocol consists of a framing structure which is synchronously transferred Therefore HDLC relies on the physical layer i e SI with TSA to provide a method of clocking and syn chronizing the transmitter receiver Each of the four SCCs can function as an HDLC control ler The SCC outputs can then be routed directly to the external pins or connected to one of two TDM channels via the TSA PmT1 and PmE1 User s Manual 10002367 02 Serial I O MPC860P Serial Interface Serial Communication Controllers SCC The MPC860P has four SCCs which may be configured independently to implement differ ent protocols Protocols such as UART HDLC and SS7 are supported to varying degrees in the MPC860P The choice of protocol is independent of the choice of physical interface The SCCs do not implement the physical interface They are connected to the outside world via the serial interface SI The SI can route the SCC SMC outputs directly to the MPC860P external pins orit can multiplex any combination of SCCs and SMCs together on one or two TDM chan nels u
46. the EIA 422 and EIA 232 serial ports See Chapter 5 for pin assignments INSTALLATION The PmT1 and PmE1 module may be installed in either expansion site on the baseboard To attach the module to your baseboard follow these steps Remove the loosely installed screws from the standoffs on the PmT1 and PmE1 module Line up the P11 P12 and P14 connectors and the 5V keying hole with the PMC connectors and the keying pin on the baseboard Press the module into place making sure that the connectors are firmly mated and the module front panel is fully seated in the baseboard front panel From the back of the baseboard insert and tighten the two screws in the standoffs closest to the PMC connectors PmT1 and PmE1 User s Manual 10002367 02 Setup PmT1 and PmE1 Setup Figure 2 4 4 Caution A PmT1 and PmE1 Installation Voltage key Tighten these two screws first Insert and tighten the two remaining screws PMT1 AND PME1 SETUP You need the following items to set up and check the operation of the Emerson PmT1 and PmE1 O Five volt compatible PMC baseboard Chassis and power supply O Serial interface cable for EIA 232 port Emerson part C0006322 xx0 Two Compu shield to RJ45 cable assemblies Emerson part number C308A009 xx for front panel I O configurations Computer terminal Save the antistatic bag and box for future shipping or storage Do not install the board in a rack or remove the
47. the framer device Error counters change every 500 frames about once per second The error count only pertains to the second before the register was polled THE T1 FDLINTERFACE The Facility Data Link FDL is the mechanism used by a T1 port to communicate operating statistics The FDL consists of one bit for every other frame of data or a 4 KHz serial data port For most applications the FDL remains inactive waiting for commands The DS2151Q uses the HDLC protocol to transfer information to and from the FDL The Facility Data Link is currently not available for use on the PmT1 due to latency of the MDI interface The PmT1 support for the FDL varies depending on the application requirements Normally the FDL can be accessed via the FDL transmit and receive registers inside the DS2151Q T1 controller The DS2151Q can be configured to generate interrupts when the receiver goes full transmitter goes empty and when a particular pattern is detected at the receiver Use the SI mode register to set up transmit and receive frame sync delays 0 3 clocks to mask the F bit in T1 applications RFSDA 1 for DS2151Q and 0 for DS2153Q 10002367 02 PmT1 and PmE1 User s Manual dH TDM Interface The T1 FDL Interface Table 6 5 Note TLINK RLINK TLCLK RLCLK Depending on the configuration of the board the FDL receiver can be connected to an SCC allowing the application to push the overhead of receive data on the QUICC chip However
48. to call this function before every call to MemAdd The function MemAdd initializes the free memory pool to use the memory starting at MemAdar of size specified by MemSize This function currently allows for only one contigu ous memory pool and must be preceded by a function call to MemReset The function MemStats monitors memory usage This function outputs a table showing how much memory is available and how much is used and lost as a result of overhead MemTop MemBase NVSupport SetNvDefaults Groups NumGroups NVGroupPtr Groups int NumGroups DispGroup Group EditFlag NVGroupPtr Group unsigned long EditFlag NVOp NVOpCmd Base Size Offset unsigned long NVOpCmd Size Offset unsigned char Base The support functions used for displaying initializing and modifying the nonvolatile mem ory data structures can also be used to manage other data structures that may or may not be stored in nonvolatile memory The method used to create a display of a data structure is to create a second structure that contains a description of every field of the first structure This description is done using the NVGroup structure Each entry in the NVGroup structure describes a field name pointer to the field size of the field indication of how the field is to be displayed and the initial value of the field An example data structure is shown below as well as the NVGroup data structure necessary to describe the data structure This
49. to comply with various safety immunity and emissions requirements as specified by the Federal Communications Commission FCC Underwriters Laboratories UL and others The following table summarizes this compliance PmT1 and PmE1 User s Manual 10002367 02 Overview Additional Information Table 1 3 Regulatory Agency Compliance T1 Table 1 4 Type Safety Telecom Specification UL60950 1 CSA C22 2 No 60950 1 03 1st Edition Safety of Information Technology Equipment including Electrical Business Equipment BI National Global IEC CB Scheme Report IEC 60950 all country deviations FCC Part 68 Title 47 Code of Federal Regulations Radio Frequency Devices IC CS03 Radiated and Conducted Emissions Canada FCC Part 15 Class A Title 47 Code of Federal Regulations Radio Frequency Devices ICES 003 Class A Radiated and Conducted Emissions Canada Regulatory Agency Compliance E1 Type Safety Telecom Specification IEC60950 EN60950 Safety of Information Technology Equipment Western Europe CTR012 Business Telecommunications Open Network Provision technical requirements 2048 kbits s digital unstructured leased line attachment requirements for terminal equipment CTRO13 Business Telecommunications Open Network Provision technical requirement 2048 kbits s structured leased line attachment requirements for terminal equipment EN55022 Information Technology Eq
50. x i a A w cw dw r and e To execute the current command and exit the editor press Enter or Return To discard an entire line and create a new command line press DEL at any time Append text on the command line Insert text on the command line Delete a single character Replace a single character Move the cursor to the next word Change Use additional commands with c to change words or groups of words as shown below Change a word after the cursor capital W ignores punctuation 10002367 02 PmT1 and PmE1 User s Manual lH Monitor Initializing Memory ce or cE cb or cB c d dw or dW de or dE db or dB ds Change text to the end of a word capital E ignores punctuation Change the word before the cursor capital B ignores punctuation Change text from the cursorto the end of the line Delete Use additional commands with d to delete words or groups of words as shown below Delete a word after the cursor capital W ignores punctuation Delete to the end of a word capital E ignores punctuation Delete the word before the cursor capital B ignores punctuation Delete text from the cursor to the end of the line INITIALIZING MEMORY The monitor uses the area between 0000 00004g and 0001 000046 for interrupt vector stack data and bss space Any writes to that area can cause unpredictable operation of the monitor The monitor initializes all local memory on power up and or on rese
51. 000 2FF Reserved for the monitor ON CARD DRAM The PmT1 and PmE1 support 16 megabyte DRAM configuration four bytes wide for data storage On card RAM occupies physical addresses starting at 0000 00004g All accesses to on card DRAM must be aligned to natural boundaries For example byte accesses must be aligned to byte boundaries word accesses to word boundaries and long word accesses to long word bound aries The DRAM is controlled by the MPC860P DRAM controller The controller may be pro grammed for most memory sizes and speeds block sizes from 32 kilobytes to 4 gigabytes and write protection In addition to the basic DRAM control functions the MPC860P chip provides several addi tional DRAM related functions Performance enhancing features include programmable delay insertion for controlling RAS recovery time RAS low time CAS setup before RAS time row address hold time CAS recovery time CAS pulse width CAS access time and address access time Dm PmT1 and PmE1 User s Manual 10002367 02 On Card Memory Configuration On card DRAM Register 4 1 LBS Bit 4 MEMS NOB Table 4 3 On card Memory Sizing and Type The Board Configuration register CO00 0180 6 is a byte wide read only register that con tains configuration information about the MPC860P and DRAM Bit 5 is no parity The con figuration registry values are factory set Board Configuration 0 BCR 0x010 7 6 5 4 3 2 1 0 LBS 1 0 MEMS M
52. 002 Cache 0x05000000 0x00000010 EEPROM 0x06000000 0x00000020 Parity DRAM Memory 0x0A000000 0x00000200 Data DRAM Memory 0x0B000000 0x00000400 For example if the module had a memory failure the PLX Mailbox 0 register would contain 0x0B000400 For parity and DRAM failures the same register would contain 0x0A000600 The magic number 0xa5 will not be in the LSB of the PLX Mailbox 0 register because if a memory error is encountered then the debug monitor is entered If all power up tests pass the PLX Mailbox 0 will be 0xA5000000 10002367 02 PmT1 and PmE1 User s Manual 8 17 Monitor Remote Host Commands 8 18 Description Description Description cachetest tests the operation of the data cache The test writes a word to every cache line and verifies that the data was written into the data cache and not into DRAM cachetest eepromtest checks the interface to the I2C EEPROM by writing a byte to the device and then reading it back and verifying the data eepromtest memtest performs an address boundary test throughout all of DRAM The test first clears all of mem ory by writing zeros The test then performs a rotating bit test on each address boundary and writes the test address as data to the test address location The test finishes by verify ing each address location contains its address as data Any failure during the memtest causes an error message to be displayed and the debug monitor is entered The debug monitor
53. 002367 02 Overview CPU RAM Flash Serial I O T1E1 PCI Bus The PmT1 and PmE1 is a single width PMC module designed to provide high speed T1 and E1 interfaces for PMGcompatible baseboards The design is based on the Freescale MPC860P PowerQUICC microprocessor and the PLX Technology PCI9060ES bus interface controller The PmT1 has two standard landed T1 channels and the PmE1 has two standard landed E1 channels An optional EIA 422 port is available COMPONENTS AND FEATURES The following is a brief summary of the PmT1 and PmE1 hardware components and fea tures The CPU for the PmT1 and PmE1 is the Freescale MPC860P PowerQUICC 32 bit micropro cessor chip running at 80MHz See Chapter 3 for processor features The PmT1 and PmE1 module is populated with 16 megabytes of 32 bit wide DRAM The PmT1 and PmE1 module has a 32 pin PLCC flash socket with a 512 kilobyte flash capac ity The PmT1 and PmE1 module has two EIA 232 I O ports implemented with two serial man agement controllers SMCs If the second E1 channel is not required the PmE1 can be fac tory configured to additionally provide a single EIA 422 serial port The PmT1 is factory configured to support the T1 channel using the Dallas Semiconductor DS2151Q controller The PmE1 is factory configured to support the E1 channel using the Dallas Semiconductor DS2153Q controller The PLX Technology PCI9060ES controls the Peripheral Component Interconnect P
54. 11 SCCA Transmission 12 SMC1 Reception 13 SMCI Transmission 14 SMC2 Reception 15 SMC2 Transmission 16 reserved reserved li 18 reserved Lowest 19 RISC Timers CPM Interrupt Handling The CPM RISC controller generates interrupts through the interrupt controller to the CPU The interrupt vector is provided by the CPU The interrupt controller is the focal point for all internal and external interrupt requests by the CPM It handles up to 28 interrupt sources 12 external 16 internal which may be assigned to a programmable interrupt level 1 3 5 7 The priority in which interrupt sources are serviced is generally fixed see the MPC860 PowerQUICC User s Manual but some flexibility is provided to modify the priority structure particularly with respect to the SCCs Dual Port RAM The CPM has 8KB of SRAM configured as dual port memory It can be accessed by the RISC processor the CPU IDMAs and SDMAs The dual port RAM has the following uses any two of which can occur simultaneously Store parameters associated with the SCCs and IDMAs Store buffer descriptors describe the location of data buffers Store data from the serial channels Store RAM microcode for the RISC processor Scratchpad RAM space for the user program 10002367 02 PmT1 and PmE1 User s Manual E Serial I O MPC860P Serial Interface UART HDLC General Purpose Timers The general purpose timers can be configured as four 16
55. 35 P BRGC ssi sserR A RR aps 5 6 MemAdd eeeee eee 8 39 P11 P12 signal descriptions 7 10 local configuration 7 1 MemBase 2 8 31 parity error signal PCI 7 11 PCI configuration 7 1 MemReset esses 8 39 PASS FAIL power up diagnostic flags shared runtime LLL 7 3 MemStats 000 8 39 8 17 SICR 4 See eee vule aote 5 6 MemTop eseeeeeee 8 31 PCI9060ES See PMC PCI SIMODE Rr cakes 5 6 NvHkOffset 0045 8 32 PLX Mailbox 0 power up diagnostic flags regulatory certifications 1 4 NvMonAddr s s 8 32 8 17 request signal PCI 7 11 NvMonOffset 0055 8 32 PMC PCI reset NvMonSize eee0e 8 32 bandwidth 00005 7 8 monitor sequence 8 1 NVOD cen nei ry TET 8 40 base address registers 7 2 7 4 7 5 PClsignal 004 7 11 NVRamACC 2 ee ee eee 8 32 bus interface 00005 7 8 returning boards 2 8 PingPongAddrTest 8 44 deadlocked cycle 7 6 RISC controller 60 5 2 prob coesvRer e eR ree 8 34 direct slave cycles 7 6 RJ 45 jack i oie ded en 6 9 pt enne ees esee s 8 42 EEPROM control register 7 4 ROHS anniina ea see ie fea 1 6 p t d i sececeree rer e 8 42 initialization 04 7 3 putcliats zer mee we 8 30 interrupts 7 8 7 10 S Revilce Pp yee ee ee Ee local direct master cycl
56. 43B6 In this example the number of bytes is 3 the checksum is B646 and the count of the S1 records S2 records and S3 records in the file is 34346 10002367 02 PmT1 and PmE1 User s Manual E Monitor Remote Host Commands Where Example Example S7 S8 and S9 records Termination and Start Address Records S705 aaaaaaaacs S804 aaaaaacs S903 aaaacs S7 S8 or S9 indicates the record type 05 04 03 count of address digits and the cs field a a is a 4 6 or 8 digit address field cs is the checksum These are trailing records There can be only one trailing record per file and it must be the last record in the output file Included in the data for this record is the initial start address for the downloaded code gt 903003CC0 In this example the start address is 3C4g 880480000078 In this example the start address is 800000416 Complete S record File gt S0097A65726F6A756D707A S10F000000001000000000084EFAFFFE93 5030001FB S9030008F4 Here is a line by line explanation of the example file 80097A65726F6A756D707A Contains the ASCII representation of the string zerojump 810F000000001000000000084EFAFFFE93 loads the following data to the following addresses byte 00416 to address 0046 byte 0046 to address 0146 byte 10 to address 0246 byte 0046 to address 0346 byte 00 6 to address 0446 byte 0046 to address 0546 byte 0046 to address 0646 byte 0846 to address 071g byte 4E46 to a
57. 5 2 CPM initialization Val es ss 4e cee onm e rtt ERU EY EI RNV A hit ees 5 2 Table 5 3 RISC Controller Processing Priority 0 cece cece eee cent e 5 2 Table 5 4 Asynchronous Baud Rates 16X oversample 0 0 c eee e eee eee ee ees 5 6 Table 5 5 Synchronous Baud Rates see eee eee ener e ene 5 7 Table 5 6 P14 PO P2 Pin Assighments erro S Rt UTER Ra Hemd ES UNE 5 7 Table 6 1 TDM to T1E1 Port Connections for TDMB P1 ssssssesee een 6 1 Table 6 2 T1E1 Signals from Transceiver P1 eee cece cece e 6 2 Table 6 3 TDM to T1E1 Port Connections for TDMA P2 cece cence ence ence ences 6 2 Table 6 4 T1E1 Signals from Transceiver Porreiro rer cece cece cece eee e nene 6 2 Table 6 5 FDIEQUICC Port Assignments ener rere me prrr RR EREMO taa ence 6 6 Table 6 6 MDI Port Connection Sisse ener err RR eek xe I RR sas eee RET Sale 6 7 Table 6 7 MBIBit Field Eorriat i re eret gu rr ere RRREEPPI EE DIU EET TT Re 6 8 Table 6 8 Compu Shield to RJ45 Pin Assignments 0 0 2 0 cece eee cece II 6 9 Table 7 1 PCI Configuration Registers 0 cece eee eee ener mmm 7 1 Table 7 2 Local Configuration Registers cece cee e eee cere cnet e 7 2 Table 7 3 Shared Runtime Registers ccsckan esata enn ee be e RR XO Hee EE ue rene 7 3 Table 7 4 PCI9060ES PCI Configuration Register Initialization sees ee 0 eee eee 7 4 Table 7 5 PCI9060ES Local Config
58. 6 3 Table 6 4 T1E1 Signals from Transceiver P1 P1 Pin Signal Name P1Pin Signal Name 1 RRING 2 RTIP 3 no connect 4 TRING 5 TTP 6 nocomect i Lc owi TDM to T1E1 Port Connections for TDMA P2 QUICC Pins to Transceiver Direction DS215xQ Function PA 9 LITXDA TSER PA 5 LITCLKA lt TCK PC 5 LITSYNCA 4 TSYNC PA 8 OLIRXDA 4 RSR PA 7 LIRCLKA 8 RCK PC 4 LIRSYNCA RSYNC T1E1 Signals from Transceiver P2 P2 Pin SignalName P2Pin Signal Name 1 RRING 2 RTIP 3 no connect 4 TRING 5 TTIP 6 no connect 7 no connect 8 noconnect Fig 6 1 and the signal list which follows indicate how the QUICC is connected to the DS2151Q T1 or DS2153Q E1 interface controller B PmT1 and PmET User s Manual 10002367 02 TDM Interface Figure 6 1 TDM and FDL Connectivity Diagram RCLK TDMA LI TSYNCA PCS TSYNC LTRSYNCA PCA leg RSYNC L1TXDA PA9 TSER I RSER QUICC L1RXDA PA8 DS21510 LIRCLKA PAZ RCLK PmTI CLK BRGO2 CLK2 PA6 or P2 LL 11TCLKA PAS gt TCLK BRGO2 CLK3 DS2153Q TXD1 PAT PmE1 fo EDUR TXD1 PA14 TLINK RXD1 PA1 5 RLINK TLCLK RLCLK Channel 0 TDMB
59. 89ABCDEF Power Up Memory Test Memory Test at 0x00040000 PASSED Address Boundary Clear PASSED All Memory Address Test PASSED BSS Zeroed Data Section Relocated Exception Vector Table Set to 0x0 Stack has been initialized to 0x10000 8 Monitor Cold Started Power Up EEPROM Test PASSED MPC860 Power Up Cache Test PASSED PCI Bus Interface Initialized Copyright Artesyn Communication Products Inc 2001 Created Thu Jan 11 13 04 24 2001 PM Link TM Debug Monitor Artesyn Communication Products Inc Version Rev 2 6 Monitor command prompt PM T1 Rev 2 6 Note The results of the power up diagnostic tests are displayed at power up or after a reset A failed memory test could indicate a hardware malfunction that should be reported to our Technical Support department at http www emersonembeddedcomputing com contact postsalessupport htm on the internet or send e mail to support artesyncp com At power up and reset the monitor configures the board according to the contents of non volatile configuration memory If the configuration indicates that an autoboot device has been selected the monitor attempts to load an application program from the specified device You can prevent the board from booting the OS if any of the power up tests fail by setting the NVRAM configuration parameter HaltOnFailure see Table 8 1 and page 8 13 PmT1 and PmET User s Manual 10002367 02 Monitor Command line History kor jort lt help ed
60. B User s Manual from Emerson Network Power Embedded Computing PmT1 and PmE 1 High Speed T1 and E1 Interface Module becember 2007 EMERSON Network Power The information in this manual has been checked and is believed to be accurate and reliable HOWEVER NO RESPONSIBILITY IS ASSUMED BY EMERSON NETWORK POWER EMBEDDED COMPUTING FOR ITS USE OR FOR ANY INACCURACIES Specifications are subject to change without notice EMERSON DOES NOT ASSUME ANY LIABILITY ARISING OUT OF USE OR OTHER APPLICATION OF ANY PRODUCT CIRCUIT OR PROGRAM DESCRIBED HEREIN This document does not convey any license under Emerson patents or the rights of others Emerson Consider It Solved is a trademark and Business Critical Continuity Emerson Net work Power and the Emerson Network Power logo are trademarks and service marks of Emerson Network Power Embedded Computing Inc 2007 Emerson Network Power Embedded Computing Inc Revision Level Principal Changes Date 10002367 00 Original release March 2001 10002367 01 RoHS 5 of6 compliance ECRO00272 March 2006 10002367 02 Artwork rev 33 December 2007 Copyright 2007 Emerson Network Power Embedded Computing Inc All rights reserved Regulatory Agency Warnings amp Notices Caution A Caution A The Emerson PmT1 and PmE1 meets the requirements set forth by the Federal Communi cations Commission FCC in Title 47 of the Code of Federal Regulations The following informa
61. CI bus The PmT1 and PmE1 modules appear as peripheral cards to PCI FUNCTIONAL OVERVIEW The following block diagram provides a functional overview for the PmT1 and PmE1 10002367 02 PmT1 and PmE1 User s Manual m Overview Physical Memory Map Figure 1 1 General System Block Diagram PmT1 or PmE1 CPU Ke enamel 1 MPC860P System Interface Unit SIU PmT1 or PmE1 Memory Controller Channel 2 or EIA422 Port Internal External Bus Interface Bus Interface Unit Unit 32 Bit Bus Power PC System Functions Processor Core Real Time Clock PCMCIA ATA Interface gt EIA232 Console and Download Ko serial Ports Communcations Processor Module CPM i I E A32 D32 gt EEPROM 2 kilobytes ant 32 Abo bs DRAM Flash ROM PCI Controller 16 megabytes Socket PCI90x0 2X PMC Connectors P14 PMC Connectors P11 P12 512 kilobytes l Serial EEPROM 128 bytes PHYSICAL MEMORY MAP The physical memory map of the PmT1 and PmE1 is depicted in Fig 1 2 Information on par ticular portions of the memory map can be found in later sections of this manual See Table 1 1 for a list of these references EH PmT1 and PmE1 User s Manual 10002367 02 Overview Physical Memory Map Figure 1 2 Physical Memory Map Hex Address FFFF FFFF Flash ROM Socke
62. Comput ing Technical Support at http www emersonembeddedcomputing com contact postsa lessupport html on the internet or send e mail to support artesyncp com Error and Screen Messages Message Source and Suggested Solution Error while clearing NV memory NV memory has become corrupted Use the nvinit 1 Error while reading NV memory command to restore defaults Error while storing NV memory Hit H to skip auto boot Consult the introduction to this chapter for information about power up conditions PmT1 and PmE1 User s Manual 10002367 02 Monitor Monitor Function Reference Example Message No help for ___ Power up Memory Test FAILED Unknown boot device Unexpected Exception at Warning NV memory board initialization skipped Warning NV memory is invalid using defaults Source and Suggested Solution The topic for help was misspelled or is not available Check the spelling If the topic was a command name use the help command to check the spelling of the command You must use the full command name not an abbreviation A failed memory test could mean a hardware malfunction The boot device is invalid Use nvdisplay to check and edit the BootParams group BootDev field Save a new value with nvupdate There are many possible sources for this error If the error is displayed during boot it could mean that autoboot is enabled and invalid parameters are being used If the error is displaye
63. Configuring the Default Boot Device The default boot device is defined in the nonvolatile memory group BootParams in the field BootDev When the PmT1 and PmE1 is reset or powered up the monitor checks this field and attempts to boot from the specified device The fields in the BootParams group have different meanings for each device For example DevType values are not used for Bus devices but are used by Serial devices to select the format for downloading Currently the monitor supports Serial ROM and Bus as standard If you edit the BootDev field and define a device that is unsupported on your board the monitor will display the message Unknown boot device Defining BootDev as Serial calls the command bootserial defining BootDev as ROM calls the command bootrom and defining BootDev as Bus calls the command bootbus See the Boot Commands Section for details on these commands In this example nvdisplay and nvupdate are used to change the default boot device from the bus to the ROM The changes are made to the BootParams group At the monitor prompt type gt nvdisplay Press lt cr gt until the BootParams group is displayed Group BootParams BootDevBus None Serial ROM Bus EPROM LoadAddress0x40000 ROMBaseO0xfff30000 ROMSize0x40000 DevTypeO 10002367 02 PmT1 and PmE1 User s Manual 8 15 Monitor NVRAM Commands DevNumber0 ClrMemOnBootFalse False True SP CR to continue or E e to Ed
64. Contents continued TestSulte sy as eorenii e PPRSERUUE 8 44 9 Acronyms 10002367 02 PmT1 and PmE1 User s Manual lH Contents continued PmT1 and PmE1 User s Manual 10002367 02 Figures Figure 1 1 General System Block Diagram 0 0c cece cece e cece eect en 1 2 Figure 1 2 Physical Memory Map aree bnOboben viten n Euk ANEREN RANAN dene 1 3 Figure 2 1 PmT1 and PmE1 Front Panel eee e eee eee eect ee eeeeeeeees 2 1 Figure 2 2 ComponentMabp Top rev 33 cereo UU TU E RE tide Exe UH ees 2 2 Figure 2 3 Component Map Bottom rev 33 csse 2 3 Figure 2 4 PmTdandPmEl Installationieoe s Letter t RYE peeFEED ES 2 5 Figure 2 5 Serial Number and Product ID on Bottom Side sslsleeleeeeeeeeeeee 2 8 Figure 3 1 ProcessorBDM Header 1 5cceer esr REI es Sia clean baud PU REPE 3 7 Figure 6 1 TDM and FDL Connectivity Diagram 0 0 ccc e cece mene 6 3 Figure 6 2 MDl Interface Protocol esc ree RR PERPE lena ates e eee eve vele 6 7 Figure 6 3 Front Panel I O Connectors P1 and P2 sss 6 8 Figure 6 4 Front Panel I O Cable Assembly C308A009 05 0 eee eee e eee eee eens 6 9 Figure 7 1 PMC Interface Connectors P11 P12 P14 0 cece cece e eee ence e 7 9 Figure 8 1 Monitor Start up Display s ceiien p ER EEEE E XRREE e EE VE 8 4 10002367 02 PmT1 and PmE1 User s Manual Es blank page PmT1 and PmET User s Manual 10002367 02 Table
65. EMS Local Bus Speed 00 Reserved 01 33 33 MHz with 66 66 MHz processor 10 40 00 MHz with 40 00 MHz processor 11 40 00 MHz with 80 00 MHz processor On card memory type valued 0 Fast page mode FPM 1 Synchronous DRAM not available Memory Size Number of Banks 0000 0111 Reserved 1000 16 onebankof 16M x 32 DRAM Timing One of the primary functions of the MPC860P is to allow flexible control of all important DRAM timing parameters The correct DRAM timing for any reasonable combination of board speed and DRAM speed is handled by the user programmable machine UPM The timing parameters are stored in the UPM s internal RAM Reference Chapter 16 in the MPC860 PowerQUICC User s Manual Freescale 07 2004 Revision 3 for more details about the UPM Table 4 3 describes the wait states for the PmT1 and PmE1 module RAM Acess Time Cycle Total Clocks Wait States Reads 4 3 I 42 32 Writes 3l 2 32 22 Burst Read 4 gi 3 1 2 1 accesses 72 3 1 1 12 10002367 02 PmT1 and PmE1 User s Manual On Card Memory Configuration On card DRAM Cycle Total Clocks Wait States continued Burst Write 4 7 2 1 1 1 accesses 52 2 1 1 12 1 At 40 MHz local bus speed 2 At 33 MHz local bus speed For non burst cycles the number in the Total Clocks column of Table 4 3 is the total num ber of CPU clock cycles required to complete the transfer and the number in the Wait States column is the
66. P Specific Functions Vector Cause of Exception continued 0x27 Software Interrupt level 3 0x28 Hardware interrupt level 4 IRQ4 0x29 Software Interrupt level 4 Ox2a Hardware interrupt level 5 IRQ5 Ox2b Software Interrupt level 5 Ox2c Hardware interrupt level 6 IRQ6 Ox2d Software Interrupt level 6 Ox2e Hardware interrupt level 7 IRQ7 Ox2f Software Interrupt level 7 0x30 PCI9060ES LINTO 0x31 PCI9060ES LSERR The function Veclnit initializes all entries in the interrupt table to reference the unexpected interrupt handler This ensures that the board will not hang when unexpected interrupts are received The unexpected interrupt handler saves the state of the processor at the point the interrupt was detected and then calls the IntrErr function which displays the error and restarts the monitor The function ConnectHandler initializes the entry in the vector table to point to the Handler address The argument Vector indicates the vector number to be connected and the argu ment Handler is the address of the function that will handle the interrupts With this struc ture assembly language programming for interrupts is avoided ConnectHandler returns HANDLERSTRUCT which is the existing handler information The function DisConnectHandler modifies the interrupt table entry associated with Vector to use the unexpected interrupt handler It also de allocates the memory used for the inter rupt wrapper allocated by ConnectHand
67. PmET User s Manual 10002367 02 Setup Caution A Table 2 1 Figure 2 1 This chapter describes the physical layout of the boards the setup process and how to check for proper operation once the boards have been installed This chapter also includes troubleshooting service and warranty information ELECTROSTATIC DISCHARGE Before you begin the setup process please remember that electrostatic discharge ESD can easily damage the components on the PmT1 and PmE1 hardware Electronic devices espe cially those with programmable parts are susceptible to ESD which can result in opera tional failure Unless you ground yourself properly static charges can accumulate in your body and cause ESD damage when you touch the board Use proper static protection and handle the PmT1 and PmE1 board only when absolutely necessary Always wear a wriststrap to ground your body before touching a board Keep your body grounded while handling the board Hold the board by its edges do not touch any components or circuits When the board is not in an enclosure store it in a static shielding bag To ground yourself wear a grounding wriststrap Simply placing the board on top of a static shielding bag does not provide any protection place it on a grounded dissipative mat Do not place the board on metal or other conductive surfaces PMT1 AND PME1 CIRCUIT BOARD The PmT1 and PmE1 circuit board is a PMC module assembly It uses an eight
68. ain register SMCs FF00 0A82 SMCMR1 4823 SMC1 mode register FF00 0A92 SMCMR2 4823 SMC2 mode register SI FFOO OAEO SIMODE 1000 0000 SI Mode register FF00 0AEC SICR 0000 0000 SI Clock route RISC Controller The RISC controller manages the serial interface to the CPM It services all I O requests allowing the CPU on the PmT1 and PmE1 module to dedicate compute time to other tasks The RISC controller implements user chosen protocols manages serial DMA transfers and independent DMA transfers optionally and maintains 16 timers for use in application soft ware See Table 5 3 for the RISC controller processing priority It can communicate with the external processor using the following methods Parameters exchanged through dual port RAM External processor executes special commands via the RISC controller RISC controller generates interrupts through the interrupt controller External processor reads the controller s status event registers Table 5 3 RISC Controller Processing Priority Priority Function Description Highest 1 ResetinRISC Processor Command register or System Reset 2 SDMA Bus Error 3 Commands issued in the RISC Processor Command register E PmT1 and PmET User s Manual 10002367 02 Serial I O The Communications Processor Module Priority Function Description SCC1 Reception 5 SCC1 Transmission 6 SCC2 Reception 7 SCC2 Transmission 8 SCC3 Reception 9 SCC3 Transmission 10 SCC4 Reception
69. an tret praece e 8 31 UART S iersvaes en EROS EA 5 4 gocce e ER EE UnMaskints 8 35 SERR oos oe ERIDI PESE S 7 11 ui c setup requirements 2 25 SICR register s nesese 5 6 WordAddrTest 8 44 RAM SIMODE register 5 6 writelCTRL sseesee 8 36 dedans xprintf esses 8 45 dualport Serre ems 5 3 specifications 10002367 02 PmT1 and PmE1 User s Manual E Index continued environmental 2 6 mechanical sss 2 1 POWEL eee eee eee ee eee 2 6 S records 8 18 8 19 8 24 fileexample 8 26 start address record 8 22 start up display monitor 8 4 staticcontrol 04 2 1 stop signal PCl 7 11 string format 8 6 8 7 symbol format 8 6 8 7 syntax for monitor commands 8 6 8 7 system interface unit SIU 3 4 systems error signal PCl 7 11 T T1 DS2151Q BDL weceteceeccanceara n ese ates ee ER 6 5 lineimpedance 6 4 OVEIVIEW eee eee eee ee eee 1 1 PmT1 and PmET User s Manual TDM interface 6 1 table of contents ii v tables listof 006 iv xi target ready signal PCl 7 11 technical references 1 6 technical support 6 7 terminology 000eee eee 1 6 time division multiplexor TDM 6 1 time slot assigner TSA 5 5 timers general purpose
70. and PmE1 module provides one 32 pin flash socket an EEPROM and one RAM configuration Off card memory may be accessed via the PMC PCl interface SOCKETED FLASH The PmT1 and PmE1 modules have a 32 pin PLCC socket for a byte wide read only flash Up to 512 kilobytes of flash may be installed The socketed flash occupies physical address space FFF0 0000 FFFF FFFF16 To avoid damage please use the proper tool to remove the PLCC device The MPC860P controls the access time for flash The default power up timing allows flash with speeds of 200 nanoseconds or faster We strongly suggest that you use the default timing because of the inherent risks of optimizing timing for a specific configuration and because of the fact that flash may be cached The monitor resides within this socketed device ROM address 0x0 0x30000 and should not be overwritten 12C EEPROM Another memory device on the PmT1 and PmE1 is a 16 kilobit serial EEPROM It is internally organized as 1Kx16 and is accessed through the C interface pins on the MPC860P The EEPROM supports a sixteen byte page write mode and a self timed write cycle It provides a minimum endurance of 100 000 cycles and a minimum data retention of 100 years The IC interface consists of the Serial Clock SCL and the Serial Data SDA lines which are controlled by bits in the PBDIR and PBDAT registers and accessible with longword read write I2C EEPROM Registers Hex Address Register Name Bi
71. art address offset is 000546 so the absolute start address is 5162546 End of file Record 00000001FF is the record start character 00is the record length 0000is the load address field always 0000 E PmT1 and PmE1 User s Manual 10002367 02 Monitor Remote Host Commands Example Olis the record type FFis the checksum This is the end of file record which must be the last record in the file It is the same for all output files Complete Hex Intel File gt 080000002082E446A80A6CCE40 020000020001FB 08000000D0ED0A2744617EFFE8 0400000300010002F6 04003000902BB4FD60 00000001FF Here is a line by line explanation of the example file gt 080000002082E446A80A6CCE40 loads byte 2046 to address 0046 loads byte 8246 to address 0116 loads byte E446 to address 0216 loads byte 4646 to address 0316 loads byte A816 to address 0446 loads byte 0A1g to address 0546 loads byte 6C4e to address 0646 loads byte CE46 to address 0716 gt 020000020001FB sets the segment value to one so 10 must be added to all subsequent load addresses gt 08000000D0ED0A2744617EFFE8 loads byte D046 to address 1046 loads byte ED1gto address 1116 loads byte 0A4c to address 1216 loads byte 274g to address 1316 loads byte 4446 to address 1446 loads byte 6146 to address 1546 loads byte 7E46 to address 1646 loads byte FF4g to address 1716 gt 0400000300010002F6 10002367 02 PmT1 and PmE1 User s Manual 8 23 Monitor
72. atile device which updates the internal data structures and then writes them back to the nonvolatile memory device If errors are encountered during the check save or compare operations an error message is returned from the function NVOp The error codes are listed below NVOP Error Codes Error Number Description NVE NONE 0 No errors NVE_OVERFLOW 1 Nonvolatile device write count exceeded NVE_MAGIC 2 Bad magic number read from nonvolatile device NVE_CKSUM 3 Bad checksum read from nonvolatile device NVE STORE 4 Write to nonvolatile device failed NVE_CMD 5 Unknown operation requested NVE_CMP 6 Data does not compare to nonvolatile device NVFields h Seed Seed Value unsigned long Value The Seed function sets the initial value for the random number generator command rand Serial char get c char get d put c char ch put d char ch baud c Baud 8 42 PmT1 and PmE1 User s Manual 10002367 02 Monitor Standard Monitor Functions Description See also Description int Baud baud_d Baud int Baud tx_empty void The serial support functions defined here provide the ability to read write and poll the monitor s serial devices The monitor initializes and controls two serial devices the con sole to provide the user interface and the modem also known as download or remote device to connect to a development system Each console function has a complement function that perfo
73. ation timers FF00 0280 Clocks and reset FF00 0300 System integration timers keys FF00 0380 Clocks and reset keys Timebase Counter This 64 bit counter provides a timebase reference for software The counter generates a maskable interrupt when it reaches the value programmed into one of four reference regis ters On the PmT1 and PmE1 the timebase clock source is the system clock divided by 16 Decrementer Counter This 32 bit counter provides a decrementer interrupt It is clocked by the same source as the timebase counter system clock divided by 16 SOFTWARE RESET The MPC860P may be reset in software via the PCI9060ES PCI interface chip Writing a one to bit 30 at local address C100 00EC holds the local bus logic in the PCI9060ES reset and LRESETO asserted The contents of the PCI configuration registers and Shared Runtime registers are not reset The PCI adapter software reset can only be cleared from the PCI bus To do a hard reset of the PmT1 and PmE1 from the local bus clear and then set bit 16 in the PCI9060ES register at local address C100 00EC To do a hard reset of the PmT1 and PmET from the PCI9060ES device the same bit must be cleared and then set in software However the PCI is little endian so this bit appears as bit 8 from the big endian point of view of the MPC860P This means that bit 8 of the register at offset 6C46 from the PCI base address must be cleared and then set After this reset the module must be
74. bit or two 32 bit identical timers The best resolution of the time is one clock cycle which translates to 25 nanoseconds at 40 MHz The maximum period is 268 435 456 cycles translating to 6 7 seconds at 40 MHz Independent DMA IDMA Channels The MPC860P has two IDMA channels which may be programmed by the user to transfer data between any combination of memory and I O The IDMA supports 32 bit data and addressing dual or single address modes and three buffer modes single auto and buffer chaining The theoretical maximum data rate of the IDMA with a local bus speed of 25 MHz is 50 MB second Serial DMA SDMA Channels The MPC860P has fourteen SDMA channels dedicated to the transmit receive channels of the serial controllers Data from the serial controllers may be routed either to external RAM orto internal dual port RAM When transfers use the internal dual port RAM other opera tions may occur simultaneously on the PmT1 and PmE1 local bus MPC860P SERIAL INTERFACE Several types of popular serial protocols are available on the PmT1 and PmE1 Please refer to the MPC860 PowerQUICC User s Manual for more detail on these supported protocols The universal asynchronous receiver transmitter protocol is the defacto standard for com municating low speed data between equipment The most popular of these is the EIA 232 standard EIA 232 specifies standard baud rates handshaking protocols and mechani cal electrical details Other popular
75. bus To do a hard reset of the PmT1 and PmE1 from the local bus clear and then set bit 16 in the PCI9060ES register at local address C100 00EC46 To do a hard reset of the PmT1 and PmE1 from the PCI bus the same bit must be cleared and then set in software However the PCI bus is little endian so this bit appears as bit 8 from the big endian point of view of the MPC860P This means that bit 8 of the register at offset 6C46 from the PCI base address must be cleared and then set After this reset the module must be reconfigured on PCI by the baseboard TROUBLESHOOTING In case of difficulty use this checklist E PmT1 and PmE1 User s Manual 10002367 02 Setup Troubleshooting Be sure the PmT1 and PmE1 circuit board is seated firmly in the baseboard and that the baseboard is fully plugged in the chassis Be sure the system is not overheating Check the cables and connectors to be certain they are secure If you are using the PmT1 and PmE1 monitor run the power up diagnostics and check the results Power up Diagnostic Test Commands Section describes the power up diagnostics Check your power supply for proper DC voltages If possible use an oscilloscope to look for excessive power supply ripple or noise over 50 mVpj below 10 MHz Check that your terminal is connected to serial port A SMC1 The PmT1 and PmE1 monitor uses values stored in on card NVRAM IC EEPROM to configure and set the baud rates for its cons
76. cal asynchronous baud rates Asynchronous Baud Rates 16X oversample System Frequency 40 MHz Baud Div16 Frequency Error Rate Value Clock Divider 1 Actual Frequency 50 16 3125 50 0 0 75 16 2083 75 0 0 150 16 1041 150 1 0 0 300 16 521 299 9 0 0 600 1 4167 599 95 0 0 1200 1 2083 1200 2 0 0 2400 1 1042 2399 2 0 0 4800 1 521 4798 5 0 0 9600 1 260 9615 4 0 2 19200 1 130 19230 8 0 2 38400 1 65 38461 5 0 2 57600 1 43 58139 5 0 9 64000 1 39 64102 6 0 2 115200 1 22 113636 4 1 4 56000 1 45 55555 6 0 8 EH PmT1 and PmET User s Manual 10002367 02 Serial I O serial Connector Pin Assignments Note Table 5 5 Note Table 5 6 P14 Pin PO Pin O N Uw a 0 a A System Frequency 40 MHz continued Baud Div16 Frequency Error Rate Value Clock Divider 1 Actual Frequency 76800 1 33 75757 6 1 4 The EIA 232C specification defines a maximum rate of 20 000 bits per second over a typical 50 foot cable 2 500 picofarads maximum load capacitance Higher baud rates are possible but successful operation depends specifically upon the application cable length and overall signal quality The formula for the synchronous baud rate is sync baud rate system frequency clock divider 1 x Div16 The clock divider value is stored in bits 12 1 of the BRGC The Div16 value 1 or 16 is selected with bit 0 of the BRGC Table 5 5 lists the clock divider and Div16 values associated with typical
77. configuration information from the monitor Also refer to the function BootUp on page 8 37 booteprom is an autoboot device that allows you to boot an application program from EPROM booteprom In order for the monitor to jump to the start of the program the following conditions must be met e The start of the program is at FFF4 00001 The first long word of the EPROM image contains a branch link instruction of the form 0100 10xx XXXx XXXX XXXX XXXX XXXX XX0 1 5 You can avoid jumping to an EPROM even if a valid one is present by changing the nonvol atile configuration parameter BootDev to something other than EPROM The default setting is to run an EPROM especially if NVRAM is trashed Also refer to the function BootUp on page 8 37 PmT1 and PmE1 User s Manual 10002367 02 Monitor Boot Commands Description Description Table 8 2 bootrom is an autoboot device that allows you to boot an application program from ROM It copies code from ROM into RAM and then jumps to the RAM address The ROM source address RomBase the RAM destination address LoadAddress and the number of bytes to copy Rom Size are read from the nonvolatile memory group BootParams bootrom When the application is called two parameters are passed to the application from the non volatile memory group BootParams The parameters are seen by the application as shown below Application Device Number unsigned char Device Number T
78. ctor table normally occupies the first 8 kilobytes of RAM with a base address of 0000 0000156 or flash with a base address of FFF0 000046 An unassigned vector position may be used to point to an error routine or for code or data storage Table 3 4 lists the exceptions recognized by the MPC860P in the order of their priority MPC860P Exceptions Vector Address Exception Hex Offset Notes Development port NM O1F00 NMI reset 00100 Trace 00D00 Instruction TLB miss 01100 Instruction TLB error 01300 Machine check 00200 Instruction breakpoint 01D00 Software emulation 01000 Alignment 00600 System call 00C00 Data TLB miss 01200 10002367 02 Highest priority PmT1 and PmE1 User s Manual Central Processing Unit system Interface Unit SIU Table 3 5 Vector Address Exception Hex Offset Notes continued Data TLB error 01400 Data breakpoint 01C00 Peripheral breakpoint 01E00 External interrupt 00500 Decrementer Decrementer Lowest priority CPU Interrupts The logic on the PmT1 and PmE1 module receive external interrupts LSERR and LINTo from the PCI9060ES chip These interrupts are combined on IRQ7 which is the only exter nal interrupt input used on the MPC860P The Conventional Interrupt register and the Interrupt Vector register are available to moni tor the status of the external interrupts These registers are byte wide and read only Attempts to read these registers with data sizes greater than a byte do
79. cycles 10002367 02 PmT1 and PmE1 User s Manual PMC PCI Interface PCI Interrupts LSERR LINTO Table 7 8 Managing Bandwidth It is possible to inadvertently set the PCIS060ES to give a disproportionate bandwidth on either side of the bridge For instance one side may retry frequently because the timer value is slightly less than the time required to gain access to the other side As a result the retries needlessly consume a large percentage of the attempted cycles To avoid this situa tion tune the timer values appropriately for the system devices Bridge to Bridge Considerations Many PMC modules also incorporate a bridge chip between their PCI and local busses essentially creating two bridges that must be crossed to complete a cycle Often the sec ond bridge is a source of long delays due to the associated bus acquisition latency The timer values should be set up to accommodate any additional latency PCI INTERRUPTS The PmT1 and PmE1 has two PCI interrupt lines Asynchronous level output indicating a system error It is asserted to the MPC860P when the PCI bus target abort or master abort status bit is set in the PCI Status Configuration reg ister Asynchronous level output to the MPC860P indicating a local interrupt The PCI to local doorbell register or a PCI BIST interrupt can generate a local interrupt See the PCI9060ES data sheet for more details on the interrupt lines CPU Interrupts describes the inte
80. d at reset or power up and autoboot is not enabled report the error to Emerson Customer Support If the error is displayed after a command has been executed an attempt to perform an operation that causes an exception has probably been made Only minimum configuration has been completed The configuration data structures are invalid Consultthe introduction to this chapter for information about reset conditions 1 Contact report the error to Emerson Network Power Customer Support at http www emersonembeddedcomputing com contact postsalessupport html on the Internet or send e mail to support artesyncp com MONITOR FUNCTION REFERENCE The PmT1 and PmE1 monitor functions fall into three groups PmT1 and PmE1 specific monitor functions processor specific functions and standard Emerson monitor functions In order to save space associated functions have been combined in groups under a single function name If you are looking for a function that is not listed by name in the following sections refer to the index to locate the desired information The functions require spaces between the function name and its arguments No parenthe ses or other punctuation is necessary gt display a0000000 gt ConnectHandler f8 1000 10002367 02 PmT1 and PmE1 User s Manual s29 Monitor PmT1 and PmE1 Specific Functions Description Description Unlike the monitor commands no argument checking takes place for functions that are ca
81. d is 8 and the data characters are the ASCII represen tation of v30bugs The checksum is 6D4 824 PmT1 and PmE1 User s Manual 10002367 02 Monitor Remote Host Commands Where Example Where Example S1 S2 and S3 records Data Records Slnnaaaadid2d3 dncs S2nnaaaaaadid2d3 dncs S3nnaaaaaaaadid2d3 dncs S1 indicates the record type nn is the count of data and checksum bytes a a are the data bytes cs is the checksum These are data records They differ only in that S1 records have 16 bit addresses S2 records have 24 bit addresses and S3 records have 32 bit addresses 810801A00030FFDC95B6 In this example the bytes 0046 3046 FF16 DC16 and 951g are loaded into memory starting at address 01A046 gt S3 0B30000000FFFF5555AAAAD3 In this example the bytes FF46 FF16 5516 5516 AA16 and AAj are loaded into memory starting at address 3000 00004g Note that this address requires an S3 record because the address is too big to fit into the address range of an S 1 record or S2 record S5 records Data Count Records S5nndid2d3 dncs S5 indicates the record type nn is the count of data and checksum bytes dl dn are the data bytes cs is the checksum S5 records are optional When they are used there can be only one per file If an S5 record is included it is a count of the S1 S2 and S3 records in the file Other types of records are not counted in the S5 record gt S50303
82. ddress 0816 E PmT1 and PmE1 User s Manual 10002367 02 Monitor Utilities Definition Definition Definition byte FA1g to address 0916 byte FF1g to address 0A46 byte FE1g to address 0B46 5030001F8 indicates that only one S1 record S2 record or S3 record was sent s9030008F4 indicates that the start address is 000000084 UTILITIES configboard configures the board to the state specified by the nonvolatile memory configuration This includes the serial ports and processor caches if necessary configboard can be used to reconfigure the board s various interfaces after modification of the nonvolatile memory configuration using nvdisplay or nvset This command accepts no parameters configboard ARITHMETIC COMMANDS add adds two integers in decimal the default binary octal or hexadecimal The default numeric base is decimal Specify hexadecimal by typing 16 at the end of the value octal by typing 8 or binary by typing 2 The result of the operation is displayed in hex decimal octal and binary add numberl number2 div divides two integers in decimal the default binary octal or hexadecimal number1 is divided by number2 The command also checks the operation to avoid dividing by zero The default numeric base is decimal Specify hex by typing 16 at the end of the value octal by typing 8 or binary by typing 2 The result of the operation is displayed in h
83. does not require RAM to execute memtest REMOTE HOST COMMANDS The monitor commands transmode download and call are used for downloading applica tions and data in hex Intel format S record format or binary format Hex Intel and S record are common formats for representing binary object code as ASCII for reliable and manageable file downloads Both formats send data in blocks called records which are ASCII strings Records may be separated by any ASCII characters except for the start of record characters S for S records and for hex Intel records In prac tice records are usually separated by a convenient number of carriage returns linefeeds or nulls to separate the records in a file and make them easily distinguishable by humans All records contain fields for the length of the record the data in the record and some kind of checksum Some records also contain an address field Most software requires the hexa decimal characters that make up a record to be in uppercase only transmode stands for transparent mode which means that the console port is connected to the download port via software In this mode a terminal connected to the console port can communicate with a host connected to the download port through the PmT1 and PmE1 as though they were transparent This allows you to edit your source code recom PmT1 and PmET User s Manual 10002367 02 Monitor Remote Host Commands Description Descript
84. e configuration of nonvolatile memory The monitor initializes i e writes to this area but it is left up to the programmer to initialize any other accessible memory areas such as off card or module memory COMMAND SYNTAX Each command may be typed with the shortest number of characters that uniquely identify the command For example you can type nvd instead of nvdisplay There is no distinction between uppercase and lowercase However note that abbreviated command names cannot be used with on line help you must type help and the full command name Press Enter or Return carriage return lt cr gt to execute a command The command line accepts three argument formats string numeric and symbolic Arguments to commands must be separated by spaces Monitor commands that expect numeric arguments assume a default base for each argument However the base can be altered or specified by entering a colon followed by the base See the following examples Typographic Conventions In the following command descriptions Courier font is used to show the command for mat Italic type indicates a field or argument that requires input BOOT COMMANDS bootbus is an autoboot device that allows you to boot an application program over a bus interface This command is used for fast downloads to reduce development time bootbus bootbus uses the LoadAddress field from the nonvolatile memory definitions group BootParams see Table 8 1
85. eading the old value nvinit is used to initialize the nonvolatile memory to the default state defined by the monitor First nvinit clears the memory and then writes the Emerson and monitor data back to the EEPROM nvinit sernum revlev ecolev writes nvinit clears any values you have changed from the default Use nvinit only if the nonvolatile configuration data structures might be in an unknown state and you must return them to a known state sernum serial number revlev revision level ecolev standard ECO level writes the number of writes to nonvolatile memory nvopen reads and checks the monitor and Emerson defined sections If the nonvolatile sections are not valid an error message is displayed nvopen nvset is used to modify the Emerson defined and monitor defined nonvolatile sections 814 PmT1 and PmE1 User s Manual 10002367 02 Monitor NVRAM Commands Description Example Description Note Example nvset group field value To modify the list with the nvset command you must specify the group and field to be modified and the new value The group field and value can be abbreviated as in the exam ples below gt nvset console port A gt nvset con dat 6 nvupdate attempts to write the Emerson and monitor defined nonvolatile sections back to the EEPROM First the data is verified and then it is written to the device The write is verified and all errors are reported nvupdate
86. ed If PowerUpDiags is set the C code power up tests are run The EEPROM test is run and if IsModConfig is set the PCI bus is configured see Table 8 1 10002367 02 PmT1 and PmE1 User s Manual g Monitor Power up Reset Sequence 6 The countdown to autoboot begins if a boot device BootDev is specified If you allow the countdown finish the selected device is booted Reference page 8 7 for booting from specific devices using the boot commands If you cancel configuration before the autoboot begins the board is configured with the default nonvolatile configuration which is summarized in Table 8 1 The configuration groups may be accessed with the NVRAM commands described on page 8 13 Table 8 1 NVRAM Configuration Groups Factory Fields Purpose Default Optional Values Console and Download Port Selects communications port A Console A B B Download Baud Selects baud rate 9600 Parity Selects parity type None Even Odd None Force Data Selects the number of data bits for transfer 8 Bits 5 Bits 6 Bits 7 Bits 8 Bits StopBits Selects the number of stop bits for transfer 1 Bit 1 Bit 2 Bits ChBaudOnBreak Break character causes baud rate change False True False RstOnBreak Break character causes reset Download False True False Cache InstrCache Turn instruction cache on or off On On Off DataCache Turn data cache on or off Off On Off CacheMode Select cache mode type Writethru Copyback Writethru
87. es 7 6 SO records 2 eee eee 8 24 RKBHit 00000 ee 8 31 overview eee 1 1 7 1 1 S3 data records 8 25 RotTest iiec kn 8 44 PClbridge euslsssse 7 3 S 5datarecords Lus 8 25 RTXMT ost met i tarte 8 31 phantom read 7 7 Fs S7 S9 termination and start address Seed cui see ne eve nk 8 42 register map esses 7 1 records i s yr REI vena 8 26 SetMSR Loro fep sche cokers 8 36 retry timers 0 e econ 7 7 8 28 SetNotPowerUp 8 31 power requirements 2 6 a E LADDER SDMA channels 5 4 SetNvDefaults 8 40 power up aland versi b 2 7 SetUnExplntFunct 8 33 COIS roi e sube LI ata ea 8 29 Send 10 re eee SiC aE cc cleans G15 ancueveyenaner ace 8 43 monitor sequence 8 1 iae baudrate ee eee 5 6 SHOMPs coire eieae 8 43 power up diagnostics 8 4 trol fr rmth it 8 43 SETCDY sexe xe ee 8 43 test commands 8 17 Bae se ae an 1 1 kj PE 8 43 prod ctlD i eoe temet 2 7 ee eee dE TestSuite 8 44 aE 5 8 protocols ee eee 5 4 ESSU Decale Saree erate eae ea am p E pa sy aR pecie a aval aai reference manuals 1 7 time_delay 8 31 protection circuitry 6 1 6 4 serial management controller SMC ToFifo 6 0 ee ee eee eee eee 8 38 protocols 5 5 Bemp eese n 8 43 DIG insons tiantiaece 5 4 seridiri mber 2 7 TXMIT eran
88. es not result in a bus error The Conventional Interrupt register at CO00 000C g indicates which PCI9060ES interrupts are active If bit 5 is one LSERR is active If bit 4 is one LINTo is active All other bits in this register read as zero Bits 4 2 of the Interrupt Vector register at CO00 000046 store the vector of the highest priority external interrupt that is pending The vector for LSERR is 1005 the vector for LINTo is 0115 The vector 0005 indicates that no interrupt is pending Internal interrupt sources including the hardware bus monitor the software watchdog timer the periodic interrupt timer PIT the real time clock and the CPM may each be assigned to a particular interrupt level in software Interrupt levels may be programmed for logic low or negative edge assertion SYSTEM INTERFACE UNIT SIU The SIU provides the MPC860P with system configuration and monitoring features In par ticular two system timers are described in the following subsections The memory control ler is also part of the SIU but is described in the On card DRAM Section MPC860P SIU Register Block Map Physical Hex Address Acronym Register Block Name FF00 0000 SIU General System Interface Unit FF00 0080 reserved FF00 0100 MEMC Memory controller PmT1 and PmE1 User s Manual 10002367 02 Central Processing Unit Software Reset Physical Hex Address Acronym Register Block Name continued FF00 0200 System integr
89. essed with the Move to Spe cial Registers mtspr and the Move from Special Registers mfspr instructions 10002367 02 PmT1 and PmE1 User s Manual EN Central Processing Unit MPC860P initialization Table 3 2 MPC860P Special Purpose Register Initialization Decimal Address Register 148 ICR 149 DER 158 ICTRL 638 IMMR MSR Required HexFormat Notes 0000 0000 Interrupt cause 0000 0000 Debug enable 0000 0000 Instruction support control FF00 0000 Internal memory map sets up the base address of the MPC860P internal register block 1002 Machine State register control The internal registers of the MPC860P are mapped to a contiguous 16 kilobyte block of memory space on a 64 kilobyte boundary The special purpose register IMMR specifies the base address of this block The following table is for the four megabyte PmT1 and PmE1 some values may change for different configurations Table 3 3 MPC860P Internal Register Initialization Physical Required Address hex Register Hex Format General SIU FF00 0000 SIUMCR 7062 3900 FF00 0004 SYPCR FFFF FF08 MEMC FF00 0100 BRO FFF0 0501 FF00 0104 ORO FFF8 09F4 FF00 0108 BR1 0000 0081 FF00 010C ORI FFC0 0000 FF00 0110 BR2 0040 0081 FF00 0114 OR2 0000 0000 FF00 0118 BR3 C100 0001 FF00 011C OR3 FFFF 8128 FF00 0120 BRA FF00 0124 ORA C000 0128 FF00 0130 BR6 C000 0401 FF00 0134 OR6 FF80 0120 FF00 0170 MAMR 4E82 1113 System Integration Timers FF00 0200 TBSCR 00C2
90. ex decimal octal and binary div numberi1 number2 10002367 02 PmT1 and PmE1 User s Manual 8 27 Monitor Errors and Screen Messages 8 28 Definition Definition Definition Table 8 5 mul multiplies two integers in decimal the default binary octal or hexadecimal from the monitor The default numeric base is decimal Specify hex by typing 16 at the end of the value octal by typing 8 or binary by typing 2 The result of the operation is displayed in hex decimal octal and binary mul numberl number2 rand is a linear congruent random number generator that uses a function Seed and a variable Value The random number returned is an unsigned long rand sub subtracts two integers in decimal the default binary octal or hexadecimal number2 is subtracted from number1 The default numeric base is decimal Specify hexadecimal by typing 16 at the end of the value octal by typing 8 or binary by typing 2 The result of the operation is displayed in hex decimal octal and binary sub numberl number2 ERRORS AND SCREEN MESSAGES Most commands return an explanatory message for misspelled or mistyped commands missing arguments or invalid values Table 8 5 lists errors that can be attributed to other causes especially errors that indicate a problem in the nonvolatile memory configuration Some errors can be resolved by contacting Emerson Network Power Embedded
91. example might describe the coordinates and depth of a window structure PmT1 and PmE1 User s Manual 10002367 02 Monitor Standard Monitor Functions Table 8 8 struct NVExample NV_Internal Internal unsigned long XPos YPos unsigned short Mag NVEx NVField ExFields XPos char amp NVEx XPos sizeof NVEx XPos NV TYPE DECIMAL 0 100 NULL YPos char amp NVEx YPos sizeof NVEx YPos NV TYPE DECIMAL 0 200 NULL Depth char amp NVEx Mag sizeof NVEx Mag NV TYPE DECIMAL 0 4 NULL NVGroup ExGroups Window sizeof ExFields sizeof NVField ExFields F If passed a pointer to the ExGroups structure the function DispGroup generates the display shown below The second parameter EditFlag indicates whether to allow changes to the data structure after it is displayed same as in the nvdisplay command Window Display Configuration XPos 100 YPos 200 Magnitude 4 The SetNvDefaults function when called with a pointer to the ExGroup structure initializes the data structure to those values specified in the NVGroup structure The second parame ter NumGroups indicates the number of groups to be initialized The NVOp function stores and recovers data structures from nonvolatile memory The only requirement of the data structure to be stored in nonvolatile memory is that the first field of the structure be NVInternal which is where all the bookkeeping for the nonvo
92. fication for detailed usage of these signals All signals are bi directional unless stated otherwise Note A sustained tri state line is driven high for one clock cycle before float ADOO AD31 ADDRESS and DATA bus bits 0 31 tri state lines are used for both address and data han dling A bus transaction consists of an address phase followed by one or more data phases BUSMODE1 4 The PmT1 and PmE1 modules assert BUSMODE1 to indicate to the baseboard that it is present and capable of performing PCI protocols The baseboard uses BUSMODE2 4 to indicate that it is PCI compatible C BEO C BE3 BUS COMMAND and BYTE ENABLES tri state lines have different functions depending on the phase of a transaction During the address phase of a transaction these lines define the bus command During a data phase the lines are used as byte enables CLK CLOCK input signal to the PmT1 and PmET provides timing for PCI transactions DEVSEL DEVICE SELECT sustained tri state signal indicates when a device on the bus has been selected as the target of the current access FRAME CYCLE FRAME sustained tri state line is driven by the current master to indicate the begin ning of an access and continues to be asserted until transaction reaches its final data phase GNT GRANT input signal indicates that access to the bus has been granted to a particular master Each master has its own GNT IDSEL INITIALIZATION DEVICE SELECT input signal acts as a chip
93. for E1 equipment including ETS 300 046 3 and ITU K17 through K20 To ensure compliance with these standards it will be necessary to undergo appropriate testing at an approved lab The PmT1 and PmE1 modules implement the suggested secondary over voltage protec tion circuitry specified by Dallas Semiconductor which targets UL1459 FCC Part 68 BellCore TR NWT 1089 and ITU K17 K20 The DS2153Q provides the ability to shape the interface wave form depending on the impedance and length of the line used The PmE1 can be built to support a variety of line impedances but is normally configured to support Twisted pair 120 Ohm line impedance The PmT1 is configured to support Twisted pair 100 Ohm line impedance PmT1 and PmE1 User s Manual 10002367 02 TDM Interface Configuring the T1 or E1 Interface Note CONFIGURING THE T1 OR E1 INTERFACE The PmT1 and PmE1 framers have typical configuration settings for operation The typical operational mode for T1 is Transmit receive ESF mode enabled Line build out set to 133 feet 0 dB DSX 1 CSU applications B8ZSencoding enabled Jitter attenuator enabled The typical operational mode for E1 is HDB3 enabled CRCA enabled CCS mode enabled time slot 16 is available for use Automatic E bit insertion enabled Automatic resync enabled Automatic remote alarm generation enabled Jitter attenuator enabled Line build out setto 120 ohms Sibits are otherwise managed by
94. gh level Data Link Control Inter integrated Circuit International Electrotechnical Commission Joint Test Action Group Light emitting Diode Medium media Access Control controller Management Data Interface Non Volatile RAM Printed Circuit Board Peripheral Component Interconnect Programmable Logic Device PCI Mezzanine Card Reduced Instruction Set Computer Return Merchandise Authorization Read Only Memory To Be Determined Time Division Multiplexor Universal Asynchronous Receiver transmitter Underwriters Laboratories Universal Serial Bus 10002367 02 PmT1 and PmE1 User s Manual Acronyms continued E PmT1 and PmET User s Manual 10002367 02 A abbreviations for monitor commands 8 6 8 7 acronyms 1 eee eee ee ee ee eee 9 1 ADDRESS and DATA signals PCI 7 10 airflowrate ccc eee ee eee 2 6 ambiguous command monitor 8 29 arithmetic commands 8 27 autoboot cancellation 8 29 B base address registers PCI 7 2 7 4 7 5 baud rate generator control BRGC register eee cece eee eee 5 6 binary download format 8 19 block diagram general 1 1 board product ID e eee eee 2 7 serial number 2 7 board configuration register 4 3 boot commands 8 7 boot device configuration monitor 8 15 booting applications from EPROM ssesss 8 8 fromROM slsssseees 8 9 from serial po
95. here are no arguments for this command The nonvolatile configuration is modified with the NVRAM commands nvdisplay and nvupdate Also refer to the function BootUp on page 8 37 bootserial is an autoboot device that allows you to boot an application program from a serial port bootserial It determines the format of the download and the entry execution address of the down loaded application from the LoadAddress and DevType fields in the nonvolatile memory group BootParams The DevType field selects one of the download formats specified below Device Download Format Device Type Download Format INT MCS86 0 Intel MCS 86 Hexadecimal Format MOT EXORMAT 1 Motorola Exormax Format S0 S3 57 S9 Records HK BINARY 2 Emerson Binary Format The nonvolatile configuration is modified with the NVRAM commands nvdisplay and nvup date When the application is called three parameters are passed to the application from the nonvolatile memory boot configuration section The parameters are seen by the applica tion as shown below Application Number RomSize RomBase unsigned char Number unsigned long RomSize RomBase These parameters allow multiple boards using the same facility to receive different configu ration information from the monitor 10002367 02 PmT1 and PmE1 User s Manual g Monitor Help Commands Description Description Description Description Description Also refer to the function BootUp on page 8 37
96. ialized by the serial EEPROM PmT1 and PmE1 User s Manual 10002367 02 PMC PCI Interface PCI9060ES Initialization Table 7 5 PCI9060ES Local Configuration Register Initialization Local Bus Address hex C100 0080 C100 0084 C100 0088 C100 008C C100 0090 C100 0094 C100 0098 C100 009C C100 00A0 C100 00A4 C100 00A8 C100 00AC Register Local Address Space 0 Range Local Space 0 Local Base Address Local Arbitration Big Little Endian Descriptor Local Expansion ROM Range PCI to local bus BREQo Control Local Bus Region Descriptor to PCI to Local Accesses Local Range Direct Master to PCI Local Bus Base Address Direct Master to PCI memory Local Base Address Direct Master to PCI IJOJCFG PCI Base Address Remap Direct Master to PCI PCI Configuration Address Direct Master to PCI IO CFG Hex Value atthe byte swapped PCI9060ES atthe CPU FF800008 080080FF 00000001 01000000 00400000 00004000 00000000 00000000 00000000 00000000 00000011 11000000 F8030043 430003F8 E0000000 000000E0 40000000 00000040 60000000 00000060 00000007 07000000 00000000 00000000 1 These registers are initialized by the serial EEPROM 2 Bursting on the MPC860P s local bus must remain disabled i e bit 24 of the PCI9060ES s local register at offset 0x98 must be zero 10002367 02 Notes Memory space reads are prefetchable The PCI to local range is set to 2MB of on card DRAM
97. if applicable Figure 2 5 Serial Number and Product ID on Bottom Side D al 1000 1234 AK Ea Product ID N Serial number 1 Y e N c o Q o E A Product Repair If you plan to return the board to Emerson Network Power for service visit http www emersonembeddedcomputing com contact productrepair html on the inter net or send e mail to serviceinfo artesyncp com to obtain a Return Merchandise Authori zation RMA number We will ask you to list which items you are returning and the board serial number plus your purchase order number and billing information if your PmT1 and PmE1 hardware is out of warranty Contact our Test and Repair Services Department for any warranty questions If you return the board be sure to enclose it in an antistatic bag such as the one in which it was originally shipped Send it prepaid to Emerson Network Power Embedded Computing Test and Repair Services Department 8310 Excelsior Drive Madison WI 53717 RMA Please put the RMA number on the outside of the package so we can handle your problem efficiently Our service department cannot accept material received without an RMA num ber E PmT1 and PmE1 User s Manual 10002367 02 Central Processing Unit Table 3 1 The PmT1 and PmE1 module uses the Freescale MPC860P PowerQUICC microprocessor installed as its CPU The MPC860P combines an embedded PowerPC core with
98. in detail Binary Download Format The binary download format consists of two parts Magic number 0x12345670 number of sections Information for each section including the load address unsigned long the section size unsigned long a checksum unsigned long that is the long word sum of the memory bytes of the data section 10002367 02 PmT1 and PmE1 User s Manual 8 19 Monitor Remote Host Commands Note Description Example Note If you download from a UNIX host in binary format be sure to disable the host from mapping cr to lt cr If gt The download port is specified in the nonvolatile memory configuration transmode provides an interface to UNIX through the board by connecting the console to a down load port A null modem cable might be necessary for the connection transmode Several key sequences are used to leave transparent mode and to initiate a download CTRL RETURN Download S record CTRL h Download hex Intel CTRL m Download Motorola S record CTRL b Download binary CTRL ESC Return to monitor This command uses software FIFOs to buffer characters between the two systems This seems to work reasonably well for most processors but can lose characters if large num bers of characters are displayed In general the only complete solution is to use serial inter rupts rather than polling Since this is not likely to happen be aware that the transmode command will allow execution of
99. ion Definition pile initiate and complete the download and return to the monitor all from one terminal This is convenient for downloading because a single control sequence issues a carriage return to the host and issues a download command to the PmT1 and PmE1 call allows execution of a program after a download from one of the board s interfaces This command allows up to eight arguments to be passed to the called address from the com mand line Arguments can be symbolic numeric characters flags or strings The default numeric base is hexadecimal If the application wants to return to the monitor it should save and restore the processor registers Also it is important that special purpose registers remain unchanged call address arg0 argl arg2 arg3 arg4 arg5 arg6 arg7 download provides a serial download from a host computer to the board download b h m address download uses binary hex Intel or Motorola S record format as specified by the following flags b binary address not used h hex Intel load address in memory address record address m Motorola S record load address in memory address record address If no flag is specified the default format is hex Intel Refer to page 8 20 for an example of how to configure the download port using NVRAM commands Binary Download Format Section Hex Intel Format Section and Motor ola S record Format Section describe the download formats
100. ion memory can be used to enable or disable the execution of these tests on power up and reset see the nvdisplay command s Misc group in Table 8 1 The results of the tests are stored at an offset of 0x60 in the I C EEPROM To read the PASS FAIL flags do four byte reads from the EEPROM at 0x60 0x61 0x62 and 0x63 The byte at 0x60 should contain the magic number 0xa5 indicating that the device is functional and that PASS FAIL reporting is supported The values forthe long word when a failure occurs are listed in Table 8 3 Table 8 3 NVRAM Power up Diagnostic PASS FAIL Flags Test Value Read on Failure Serial 0xa5000001 Counter Timer 0xa5000002 Cache 0xa5000010 EEPROM 0xa5000020 The power up PASS FAIL flags are also written to PLX Mailbox 0 The module writes the progress and PASS FAIL status of each of its power up tests to PCI so that the baseboard can determine the power up status of the module and proceed accordingly At the conclu sion of power up the same magic number 0xa5 used in the NVRAM PASS FAIL flags is written to the least significant bit LSB of PLX Mailbox 0 The PLX Mailbox 0 register can be polled until the magic number is displayed and then checked to see if there are any fail mask bits set The following bits in Table 8 4 are used to indicate the power up test sequence and failure Table 8 4 PLX Mailbox 0 Sequence and Fail Mask Bits Power up Test Sequence Bit Fail Mask Bit Counter Timer 0x02000000 0x00000
101. it 3 Press E to edit the group 4 Press cr until the BootDev field is displayed 5 Type the new value ROM 6 Press cr to display the LoadAddress field 7 Type the address where execution begins 8 Press cr to display the ROMBase field 9 Typethe ROM base address 10 Press cr to display the ROMSize field 11 Typethe ROM size 12 Press lt ESC gt or Q to quit the display 13 Type nvupdate to save the new values Example In this example nvdisplay and nvupdate are used to change the default boot device from the bus to the serial port The changes are made to the BootParams group 1 Atthe monitor prompt type gt nvdisplay Press lt cr gt until the BootParams group is displayed Press E to edit the group Press lt cr gt until the BootDev field is displayed Type the new value Serial Press cr until the DevType field is displayed y O UW Hh WU N Type the new value for DevType for example 2 selects downloads in Emerson binary format 8 Edit any other fields you want to modify Whether you use the DevType and DevNumber fields depends on the application 9 Press lt ESC gt or Q to quit the display 10 Type nvupdate to save the new values s6 PmT1 and PmE1 User s Manual 10002367 02 Monitor Power up Diagnostic Test Commands POWER UP DIAGNOSTIC TEST COMMANDS The following on card functional tests are available to be run at any time including power up and reset The nonvolatile configurat
102. itor gt lt ESC gt lt cr gt lt DEL gt aorA iorl xor X cw or cW You can cancel both the nonvolatile configuration sequence and the autoboot sequence by pressing the H key on the console keyboard before the boot ends The monitor is then in a manual mode from which you can execute commands and call functions The monitor also enters manual mode if the autoboot fails Instructions for downloading and executing remote programs are given in the command reference and function reference The monitor provides a command line interface that includes a command history and a vi like line editor The command line interface has two modes insert text mode and com mand mode In insert text mode you can type text on the command line In command mode you can move the cursor along the command line and modify commands Each new line is brought up in insert text mode COMMAND LINE HISTORY The monitor maintains a history of up to 50 command lines for reuse Press the lt ESC gt key from the command line to access the history Move backward in the command history to access a previous command Move forward in the command history to access a subsequent command COMMAND LINE EDITOR The command line editor uses typical UNIX vi editing commands To access an on line description of the editor type help editoror h editor To exit Entry mode and start the editor press lt ESC gt You can use most common vi com mands such as
103. latile memory section is done The first parameter NVOpCmd indicates the command to be per formed A summary of the commands is shown below NVOp Command Command Value Description NV OP FIX 0 Fix nonvolatile section checksum NV OP CLEAR 1 Clear nonvolatile section NV OP CK 2 Check if nonvolatile section is valid NV OP OPEN 3 Open nonvolatile section NV_OP_SAVE 4 Save nonvolatile section NV OP CMP 5 Compare nonvolatile section data 10002367 02 PmT1 and PmE1 User s Manual g Monitor Standard Monitor Functions Table 8 9 See also Description The second parameter Base indicates the base address of the data structure to be oper ated on and the Size parameter indicates the size of the data structure to be operated on The Offset parameter specifies the byte offset in the nonvolatile memory device where the data structure is to be stored An example of how to initialize store and recall the example data structure is shown below NVOp NV_OP_CLEAR amp NVEx sizeof NVEx 0 NVOp NV_OP_SAVE amp NVEx sizeof NVEx 0 NVOp NV_OP_OPEN amp NvEx sizeof NVEx 0 NVOp NV_OP_FIX amp NVEx Sizeof NVEx 0 NVOp NV OP SAVE amp NVEx sizeof NVEx 0 The clear save and open operations cause the nonvolatile device to be cleared and filled with the NVEx data structure then the data structure is filled from nonvolatile memory The fix and save operation are used to modify the nonvol
104. ler Because both ConnectHandler and DisCon nectHandler use the Malloc and Free facilities it is necessary for memory management to be initialized The function probe accesses memory locations that may or may not result in bus error This function returns TRUE if the location was accessed and FALSE if the access resulted in a bus error The argument DirFlag indicates whether a read 0 or a write 1 should be attempted The argument SizeFlag selects either a byte access 1 a word access 2 or a long access 4 The argument Address indicates the address to be accessed and the argument Datais a pointer to the read or write data Interrupts MaskInts UnMaskInts 10002367 02 PmT1 and PmE1 User s Manual E Monitor Standard Monitor Functions 8 36 Description Description PmT1 and PmE1 User s Manual The functions UnMasklnts and Masklnts are used to enable and disable external interrupts atthe processor Status getMSR SetMSR Data ClrMSR Data getTBU getTBL getDEC getSRRO getSRR1 getlC CST getDC CST getICTRL WriteICTRL The functions getMSR setMSR Data and clrMSR return the value of the Machine State register MSR setMSR and cIrMSR either set or clear the bits in the MSR getTBU returns the value of the upper 32 bits of the TimeBase register and getTBL is used for the lower 32 bits Functions getDEC getSRRO getSRR1 getlC CST and getDC CST return the value for the appropriate regi
105. lled directly from the command line PMT1 AND PME1 SPECIFIC FUNCTIONS ChangeBaud ChangeBaud Baud Port struct SCCPort Port int Baud ConfigSerDevs The function ChangeBaud allows the baud rate for the port defined by Port to be modified to the value defined by Baud This function accepts a selected number of values for the baud rate and will configure the port accordingly It is the caller s responsibility to check if the terminal can support the specified baud rate The ConfigSerDevs function uses the current definitions in the nonvolatile memory config uration to configure the serial ports It is important that the configuration be valid when this function is called or unpredictable behavior may result Both serial ports can be configured to use 5 to 8 data bits 1 or 2 stop bits the handshake control lines and odd even or no parity EEPROMAcc unsigned char EEPROMAcc mode offset ch unsigned long mode offset unsigned char ch This function provides the physical interface to the board s nonvolatile memory device The mode indicates one of four access types READ READ PROBE WRITE and WRITE PROBE The probe mode was left for compatibility with earlier versions of the monitor If mode is zero a byte is read from nonvolatile memory If mode is one a byte is written to nonvolatile memory The Offset indicates the byte location to be modified and assumes that nonvola tile memory is a linear array of memory loca
106. ls5 4 Technical References 1 6 Serial DMA SDMA Channels 5 4 MPC860P Serial Interface 5 4 Serial Communication Controllers 2 Setup Crus PE 5 5 Electrostatic Discharge 2 1 Serial Management Controllers PmT1 and PmE1 Circuit Board 2 1 SMC iss ee E NEN LUE P e TET 5 5 Connectors eere 2 4 Time Slot Assigner TSA 5 5 Installation n eeen 2 4 UART Baud Rate Selection 5 6 PmT1 and PmET Setup 2 5 Serial Connector Pin Assignments 5 7 Power Requirements 2 5 Environmental Considerations 2 6 Reset Methods 00000e 2 6 6 TDM Interface Troubleshooting eee 26 The T1 orE1 Line Interface 6 4 Technical Support Se Ses zw Configuring the T1 or E1 Interface 6 5 Product Repair eese zi The T1 FDL Interface 6 5 The Management Data Interface MDI 6 7 3 Central Processing Unit Front Panell O usuusu 6 8 MPC860P Initialization 3 1 MPC860P Exception Handling 3 3 7 PMC PCI Interface CPU IDET BES nieto Mot pies PCI9060ES Register Map 7 1 System Interface Unit SIU 3 4 PCI Configuration Registers 7 1 Timebase Counter 35 Local Configuration Registers 7 2 Decrementer Counter 3 5 Shared Runtime Registers 73 Software Reset feet 35 PCI9060ES Initialization
107. mine the length of strings 10002367 02 PmT1 and PmE1 User s Manual e Monitor Standard Monitor Functions 8 44 Description The function CmpStr compares the two null terminated strings pointed to by Str7 and Str2 If they are equal it returns TRUE otherwise it returns FALSE Note that this version does not act the same as the UNIX strcmp function CmpStr is non case sensitive and only matches characters up to the length of Str1 This is useful for pattern matching and other functions The function StrCmp compares the two null terminated strings pointed to by Str7 and Str2 If they are equal it returns TRUE otherwise it returns FALSE Note that this version acts the same as the UNIX strcmp function The function StrCpy copies the null terminated string Source into the string specified by Dest There are no checks to verify that the string is large enough or is null terminated The only limit is the monitor defined constant MAXLN 80 which is the largest allowed string length the monitor supports The length of the string is returned to the calling function The function StrLen determines the length of the null terminated string Str and returns the length If the length exceeds the monitor defined limit MAXLN the function returns MAXLN The function StrCat concatenates the string SrcStr onto the end of the string DestStr TestSuite TestSuite BaseAddr TopAddr TSPass unsigned long BaseAddr TopAddr int TSPass By
108. n tains plain characters to be processed as is and special characters that are used to indicate the format of the next argument in the argument list There must be at least as many argu ments as special characters or the function may act unreliably Special character sequences are started with the character The characters after the can provide information about left or right adjustment blank and zero padding argument con version type precision and more things too numerous to list 10002367 02 PmT1 and PmE1 User s Manual 5 45 Monitor Standard Monitor Functions If detailed information on the argument formats and argument modifiers is required see your local C programmer s manual for details Not all of the argument formats are sup ported The supported formats are d o u x X c and s 8 46 PmT1 and PmET User s Manual 10002367 02 Acronyms ASCII CPU CSA DRAM EC EEPROM EIA EMC ESD ETSI FCC FDL HDLC c IEC JTAG LED MAC MDI NVRAM PCB PCI PLD PMC RISC RMA ROM TBD TDM UART UL USB American Standard Code for Information Interchange Central Processing Unit Canadian Standards Association Dynamic Random Access Memory European Community Electrically Erasable Programmable Read Only Memory Electronic Industries Alliance Electromagnetic Compatibility Electrostatic Discharge European Telecommunications Standards Institute Federal Communications Commission Facility Data Link Hi
109. ncy When initializing the PCIS060ES make sure that the retry timers are set to a value greater than the maximum latency of the target device For example if the register value for PCI Target Retry Delay Clocks is 246 a PCI master must access the local bus and complete its cycle within 16 clocks In this situation however the Direct Slave cycle would seldom gain access because of the local bus acquisition latency The Direct Slave device must wait for the CPU to finish its local I O cycle and relinquish the local bus Setting the Direct Slave BREQo Delay Clocks value too low has a similar effect on Local Direct Master cycles Avoiding the PCIS060ES Phantom Read As a default Emerson configures the PCI9060ES to favor Local Direct Master cycles by allowing retries only on Direct Slave cycles see Table 7 2 This avoids a problem with the PCI9060ES that can happen when a local bus master attempts to read from a PCI device and a deadlocked cycle occurs that results in a BREQo to the local master The PCI9060ES retries the read cycle on the PCI bus and discards the data before the local bus master retries the cycle This phantom read reading ahead by the PCI9060ES affects target devices that change their data or state upon access such as FIFOs or other devices For example some devices de assert their interrupts after a vector is read In these cases the PCIS060ES phan tom read access can result in a bus error or bad data upon subsequent read
110. ns use the nonvolatile memory configuration to determine how to configure an interface so the data structures must contain valid data before either of these functions are called The InitBoard function initializes the minimum set of hardware to the default state defined by the nonvolatile device structures The hardware initializes the serial port The ConfigCaches function initializes the processor caches to be On or Off as defined by the nonvolatile memory configuration Misc unsigned char MemTop unsigned char MemBase time delay IsPowerUp SetNotPowerUp 10002367 02 PmT1 and PmE1 User s Manual z Monitor PmT1 and PmE1 Specific Functions Description Description Description This is a collection of miscellaneous board support functions The functions MemTop and MemBase are used to determine the addresses of the last and first long words in free memory The size of DRAM is determined by the configuration regis ter The base of free memory is determined by the compiler created variable End which indicates the end of the monitor s bss section The time_delay function provides a fixed delay for timing As a delay generator this func tion can be used to delay in increments of microseconds as specified by the MicroSec argu ment The IsPowerUp function determines if a power up or reset just occurred The SetNotPowerUp function resets the power up register NvHkOffset NvHkOf fset NvMonOf fset
111. nvolatile memory is a linear array of memory locations If there are gaps between bytes on the physical device they are dealt with here The last parameter Val is a pointer to the character location to be written This function returns the number of bytes written to the device or the value read from the device depending on Mode Only bytes that differ are written SetUnExpIntFunct SetUnExpIntFunct Funct unsigned long Funct If desired a program can call the SetUnExplIntFunct function to attach its own interrupt handler to all unexpected interrupts This function attaches the handler specified by Funct The new interrupt handler must determine the source of the unexpected interrupt and remove it MPC860P SPECIFIC FUNCTIONS Cache disable dcache disable icache enable dcache enable icache invalidate dcache invalidate icache Asthe names indicate these functions enable disable and flush the data and instruction caches The enable dcache function enables the data cache in either copyback or write through mode If mode is zero copyback mode is selected If mode is one write through mode is selected The invalidate dcache function flushes all data cache lines and the invalidate_icache function flushes all instruction cache lines Exceptions VecInit void typedef unsigned long VECTORNUM typedef void HANDLERPARM typedef void HANDLER VECTORNUM up to one 1 optional parameter 10002367 02 PmT1
112. oc allocate memory from the memory pool Each of these functions returns a pointer to the memory requested if the request can be satisfied and NULL if there is not enough memory to satisfy the request The function Malloc accepts one argument NumBytes indicating the number of bytes requested The function Calloc accepts two arguments NumElements and Size indicating a request for a specified number of elements of the specified size The function ReAlloc reallocates a memory block by either 10002367 02 PmT1 and PmE1 User s Manual E Monitor Standard Monitor Functions 8 40 See also Description returning the block specified by Block to the free pool and allocating a new block of size NumBytes or by determining that the memory block specified by Block is big enough and returning the same block to be reused The functions Free and CFree return blocks of memory that were requested by Malloc Cal loc or ReAlloc to the free memory pool The address of the block to be returned is specified by the argument MemLoc which must be the same value returned by one of the allocation functions An attempt to return memory that was not acquired by the allocation functions is a fairly reliable way of blowing up a program and should be avoided The function MemReset sets the free memory pool to the empty state This function must be called once for every reset operation and before the memory management facilities can be used It is also necessary
113. ole port The lack of a prompt might be caused by incorrect terminal settings and incorrect configuration of the NVRAM or a malfunctioning NVRAM Try holding down the H character during a reset to abort autoboot using NVRAM parameters If the prompt comes up the NVRAM console parameters are probably configured incorrectly Enter the command nvopen then the command nvdisplay to check the console configuration For more information about the way NVRAM is used to configure the console port baud rates refer to Chapter 8 Technical Support If you need help resolving a problem with your PmT1 and PmE1 visit http www emersonembeddedcomputing com contact postsalessupport html on the Internet or send e mail to support artesyncp com If you do not have internet access call Emerson for further assistance 800 327 1251 or 608 826 8006 US 44 131 475 7070 UK Have the following information available when contacting support PmT1 and PmE1 serial number and product identification see Fig 2 5 monitor version see Fig 8 1 start up display the baseboard serial number and product identification version and part number of the operating system if applicable This information is labeled on the master media supplied by Emerson or another vendor whether your board has been customized for options such as a higher processor speed or additional memory 10002367 02 PmT1 and PmE1 User s Manual Setup Troubleshooting license agreements
114. on Description Description Description setmem allows memory locations to be modified starting at address setmem first displays the value that was read Then you can type new data for the value or leave the data unchanged by entering an empty line If you press lt cr gt after the data the address counts up If you press lt ESC gt after the data the address counts down To quit this command type any illegal hex character for example period setmem b w 1 address swapmem swaps bytecount bytes at the source address with those at the destination address swapmem source destination bytecount testmem performs a nondestructive memory test from startaddr to endaddr If endaddr is zero the address range is obtained from the functions MemBase and MemTop The memory test can be interrupted by pressing any character This command can be used to verify memory DRAM It prints the progress of the test and summarizes the number of passes and failures testmem startaddr endaddr Also refer to the functions MemBase and MemTop in Misc Section um performs a destructive memory test from base addr to top addr This is done by first clear ing all memory in the range specified doing a rotating bit test at each location and finally filling each data location with its own address If top addr is zero the address range is obtained from the functions MemBase and MemTop This command prints the progress
115. on Note 342 DS2151 DS2153 Initialization and Programming Dallas Semiconductor 102899 http www maxim ic com CPU MPC860P PowerQUICC Technical Summary Freescale Semiconductor 07 2004 Rev 3 http www freescale com H PmT1 and PmE1 User s Manual 10002367 02 Overview Additional Information Device Interface EEPROM PCI Document continued CAT93C86 Die Rev C 16 Bit Microwire Serial EEPROM Catalyst Semiconductor Inc Doc No 1091 Rev O 10 13 06 http www catsemi com PCI Local Bus Specification PCI Special Interest Group Revision 2 1 1995 http www pcisig com PCI9060ES PCI Bus Master Interface Chip for Adapters and Embedded Systems data sheet Mountain View CA PLX Technology Inc December1995 VERSION 1 2 http www plxtech com Draft Standard for a Common Mezzanine Card Family CMC P1386 Draft 2 0 April 4 1995 IEEE New York NY Draft Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC P1386 1 Draft 2 0 April 4 1995 IEEE New York NY http www ieee org Serial Interface EIA Subcommittee TR 30 2 on Interface EIA Standard RS 232 D Electronic Industries Association August 1969 http www eia org 1 Frequently the most current information regarding addenda errata for specific documents may be found on the corresponding web site 10002367 02 PmT1 and PmE1 User s Manual Overview Additional Information H PmT1 and
116. only indicate a paragraph which is a 16 byte boundary Stated in C for example address segment lt lt 4 offset or segment ssss offset oooo address aaaaa For addresses with fewer than 16 bits the segment portion of the address is unnecessary The hex Intel checksum is a two s complement checksum of all data in the record except for the initial colon In other words if you add all the data bytes in the record including the checksum itself the lower eight bits of the result will be zero if the record was received correctly Four types of records are used for hex Intel format extended address record data record optional start address record and end of file record A file composed of hex Intel records must end with a single end of file record Extended Address Record 02000002sssscs is the record start character 02is the record length 0000is the load address field always 0000 02 is the record type ssssis the segment address field csis the checksum The extended address record is the upper sixteen bits of the 20 bit address The segment value is assumed to be zero unless one of these records sets it to something else When such a record is encountered the value it holds is added to the subsequent offsets until the next extended address record 10002367 02 PmT1 and PmE1 User s Manual Monitor Remote Host Commands Example Example Example Here the first 02 is the byte coun
117. op the current transaction TRDY TARGET READY sustained tri state signal indicates the target s ability to complete the cur rent data phase of the transaction 10002367 02 PmT1 and PmE1 User s Manual 7 11 PMC PCI Interface PMC Connector Pin Assignments 7 12 PmT1 and PmE1 User s Manual 10002367 02 Monitor The PmT1 and PmE1 monitor consists of a set of about 150 C language functions The mon itor commands constitute a subset of these functions and are designed to provide easy to use tools for PMT1 and PmE1 configurations at power up or reset and communications downloads and other common uses This chapter includes an introduction to monitor operation instructions for command sequences that configure the PmT1 and PmE1 modules a command reference and a func tion reference POWER UP RESET SEQUENCE At power up or board reset the monitor performs hardware initialization autoboot proce dures free memory initialization and if necessary invokes the command line editor In more detail monitor execution starts up as follows The MPC860P is initialized first caches are disabled the memory control UPM user programmable machine is initialized CS chip select memory map and control are initialized and the Systems Interface Unit SIU is initialized The QUICC sections are initialized in the following order the NVRAM clock and data bits and then the console port SMC1 The NVRAM is checked for functionality and
118. or Direct Slave cycles The following PCI9060ES internal register fields control bus priority and also are accessible from the PmT1 and PmE1 monitor see Table 8 1 PmT1 and PmE1 User s Manual 10002367 02 PMC PCI Interface PCI9060ES Initialization Table 7 7 PCI9060ES Bus Priority Control Hex Address Bits Register Field Factory Default Value hex C100 0094 3 0 Direct Slave BREQo Delay Clocks 1 8 clocks C100 0094 4 Local Bus BREQo Enable 1 BREQo enabled C100 0098 31 28 PCI Target Retry Delay Clocks F 120 clocks As an example a user could give priority to the Direct Slave device PCI bus by enabling the BREQo timer and setting Direct Slave BREQo Delay Clocks to a value less than PCI Target Retry Clocks When a deadlock occurs the BREQo timer expires and the PCIS06OES asserts BREQo to the local bus master forcing it to relinquish the bus and retry its cycle later This allows the Direct Slave cycle to complete Alternatively a user could give priority to the Local Direct Master by disabling the BREQo timer and setting PCI Target Retry Clocks to a nominal value When a deadlock occurs the PCI target retry timer expires forcing the Direct Slave device to relinquish the PCI bus and retry its cycle later This allows the Local Direct Master cycle to complete Note The factory default values favor the local bus during deadlocked cycles Tune the timer values appropriately for the system devices Controlling Access Late
119. r Embedded Computing Inc www emersonembeddedcomputing com EMERSON CONSIDER IT SOLVED
120. r part numbers for these connectors are Stewart Connec tor Systems SS 310808 5 and SS 800810 040 250 See Table 6 8 for the Compu Shield and RJ 45 jack pin assignments Figure 6 4 Front Panel I O Cable Assembly C308A009 05 ASX MIR S di Jl MS e I SE UR LOT NS e N 4 a Oe PN DE SZ SS c 8 pin Male Modular Plug 8 pin Female Connector Modular Jack Connector Table 6 8 Compu Shield to RJ45 Pin Assignments P1 and P2 Compu Shield RJ 45 Jack Pin signal Pin Pin signal 1 no connect 1 RRINC 8 2 RRING 2 RTIP 7 3 RTIP 3 6 4 4 TRING 5 5 TRING 5 TTIP 4 6 TTIP 6 3 7 7 2 8 8 1 9 10 no connect 1 This is a straight through cable there is no crossover Caution To reduce risk of fire use only number 26 AWG or larger telecommunication line cord A 10002367 02 PmT1 and PmE1 User s Manual 69 TDM Interface Front Panel O zl PmT1 and PmET User s Manual 10002367 02 PMC PCI Interface Table 7 1 The PmT1 and PmE1 module design complies with the Peripheral Component Interconnect PCI bus interface standard and with the associated PCI Mezzanine Card PMC mechanical interface standard The PmT1 and PmE1 modules must be attached to and controlled by a PMC PCI compliant baseboard The PmT1 and PmE1 use the PLX Technology PCI9060ES interface controller to implement the 5V PMC PCI interface The PMC PCI interface fea
121. rd 8 21 Data Record Lsuuue 8 22 End of file Record 8 22 Motorola S record Format 8 24 SO records User Defined 8 24 S1 S2 and S3 records Data Records ce eee ee eee eee 8 25 S5 records Data Count Records 8 25 S7 S8 and S9 records Termination and Start Address Records suusuu 8 26 Utilities 0 eee eee eee 8 27 configboard 8 27 Arithmetic Commands 8 27 addicere ERR RES ERES 8 27 CIV cst Uem E semuis 8 27 TU sie eee ese tipi ERES 8 28 EINT MEE ceno 8 28 SUD A wae iii ddeweeewns 8 28 Errors and Screen Messages 8 28 Monitor Function Reference 8 29 PmT1 and PmE1 Specific Functions 8 30 ChangeBaud 8 30 EEPROMAGC cossi ee re 8 30 getchar 22 ez setebesesewevuu 8 30 InitBoard eiieeii eee eee ee eee 8 31 IL 8 31 NvHkOffset 02 cece eee 8 32 NvRamAcc ee eee eee eee ee 8 32 SetUnExplntFunct 8 33 MPC860P Specific Functions 8 33 Caches cnexevaviews ioiohewstese 8 33 EXCEPHONS ne se asic iasi e 8 33 INTERRUPTS 26420 ee Dorint 8 35 Stale nee ribasso ib d EEEE 8 36 Standard Monitor Functions 8 36 atoh eee 8 36 BootUp csccieregdncgivesicewtew santas 8 37 INFO csi cca se preter Reps 8 38 ISLeQalcjecsnerreaiasanione nent 8 38 MemMng si osetreriie eme 8 39 NVSUDDOLE ener tr RemebR 8 40 Eq 8 42 Serial ds esseri RkRxG RE RUP 8 42
122. removed your system chassis enclosure must provide the required electromagnetic interference EMI shielding to maintain EMC compliance FCC RULES AND REGULATIONS PART 68 This equipment complies with Part 68 of the FCC rules There is a label on the PmT1 and PmE1 board that contains the FCC registration number If requested this information must be provided to the telephone company 10002367 02 PmT1 and PmE1 User s Manual Es Regulatory Agency Warnings amp Notices continued Board Name PmT1 and PmE1 This board is designed to be connected to the telephone network or premises wiring using a compatible modular jack which is Part 68 compliant This board cannot be used on tele phone company provided coin service Connection to Party Line Service is subject to state tariffs If this board causes harm to the telephone network the telephone company will notify you in advance that temporary discontinuance of service may be required If advance notice is not practical the telephone company will notify the customer as soon as possible Also you will be advised of your right to file a complaint with the FCC if you believe it is necessary The telephone company may make changes in its facilities equipment operations or pro cedures that could affect the operation of the equipment If this happens the telephone company will provide advance notice in order for you to make the necessary modifications in order to maintain uninterrupted
123. rms the same operation on the modem device The modem device func tions are prefixed with the letter R for remote Each serial port is configured at reset according to the nonvolatile memory configuration The functions get_c and get_d read characters from the console and modem devices When called these functions do not return until a character has been received from the serial port The character read is returned to the calling function The functions put_c and put_d write the character c from the console and modem devices When called these functions do not return until a character has been accepted by the serial port The functions baud c and baud d modify the console and modem device baud rates The argument Baud specifies the new baud rate to use forthe port Because these functions accept any baud rate care must be taken to request only those baud rates supported by the terminal or host system The function tx empty checks if the transmitter is available for sending a character If the transmitter is available TRUE is returned otherwise FALSE is returned getchar putchar KBHit ChangeBaud Strings CmpStr Strl Str2 char Stri Str2 StrCmp Str1 Str2 char Stri Str2 StrCpy Dest Source char Dest Source StrLen Str char Str StrCat DestStr SrcStr char DestStr SrcStr These functions provide the basic string manipulation functions necessary to compare copy concatenate and deter
124. rrupt handling by the MPC860P PCI Bus Interface Using the DRAM timing the PCI interface of the PmT1 and PmE1 is capable of the transfer rates given in Table 7 8 The transfer rates to PCI bus are dependent on the baseboard design Local to PCI bus and PCI to local bus does not support bursting PCI to Local Slave Access Timing Cycle Type Wait States Total Clocks Slave Read long word il 5 Slave Write long word 1 5 PMC CONNECTOR PIN ASSIGNMENTS The PmT1 and PmE1 modules have three 64 pin PMC connectors P11 P12 and P14 These connectors support the PCI and serial interfaces The pin arrangement for the 64 pin con nector is shown in Fig 7 1 The possible manufacturer part numbers for this connector are PmT1 and PmE1 User s Manual 10002367 02 PMC PCI Interface PMC Connector Pin Assignments Amp 120534 1 Molex 53483 0649 or Molex 53508 0648 The recommended mating con nectors include Amp 120521 1 Amp 120528 1 and Molex 52763 0649 Refer to Fig 2 1 for the placement of these connectors on the PmT1 and PmE1 module Figure 7 1 PMC Interface Connectors P11 P12 P14 2 64 The PCl interface signals are routed out P11 and P12 Pin assignments for this interface are listed in Table 7 9 The serial I O interface is routed out P14 The pin assignments for this connector are given in Table 5 6 of the serial I O chapter Table
125. rt 8 9 BootParams monitor group 8 2 8 15 Boot p iones reris 8 37 bridge PCI iier mn 7 3 burst cycles eee eee 4 4 b s PCI esee eye tere rns 7 8 command signals 7 10 BUSMODE1 4 signals PCI 7 10 byte enable signals PCI 7 10 C Cache monitor group 8 2 caution statements line cord size 22 eee ee eee 6 9 nvinit command 8 14 checksum S records 8 24 circuit board dimensions 2 1 clock signal PCI 7 10 commandreference 8 6 8 7 command line history editor 8 5 communications processor module CPM ue hrec dota hen ede 5 1 baudrategenerator 5 6 interrupt handling 5 3 register initialization 5 2 RISC controller Ls 5 2 compliance e ee eee 1 4 component map bottom siete a tine bane alia 2 3 LOD MEE C 2 2 Compu Shield 08 6 9 connectors Compu Shield 6 9 Overview lees 2 4 Plandp2 er terr 6 8 RJ 45 jack eet reete 6 9 Console monitorgroup 8 2 contents tableof ii v conventional interrupt register1 4 3 4 counters decrementer 3 5 CPU CPM aaa traut Ea en 5 1 DRAM controller 4 2 exception handling 3 3 IDMA channels Leu 5 4 overview ee eee eee ee eee 1 1 parallel ports 3 5 SDMA channels 5 4 SMG iesus Dese creams
126. s Table 1 1 Address SUMMAN x22 osperbberiprpirsivvbhrpbenr ter pK PE p bebe pr dd 1 4 Table 1 2 unuspic e aenea 1 4 Table 1 3 Regulatory Agency Compliance T1 esses 1 5 Table 1 4 Regulatory Agency Compliance E1 lesse 1 5 Table 1 5 Technical References 2 sce e eee cece eee nee enter eee 1 6 Table 2 1 Circuit Board Dimersiofs cei Aas ydnasangagdor IER erPIRRERRE S Ned Dry 2 1 Table 2 2 Power Requiremients ciere RxR I Rr ene UpU ERR epee eee ews Ie eee 2 6 Table 2 3 Environmental Requirements 0 0c cece cece eee me 2 6 Table 3 1 MPC860P Features cssie cre RR RR e re pLULC PETERE PUER RENE TENNA 3 1 Table 3 2 MPC860P Special Purpose Register Initialization 0 00 cece eee eee 3 2 Table 3 3 MPC860P Internal Register Initialization 0 cece eene 3 2 Table 3 4 MPCB860P Exceptions xr rr mer rU a EE PU eae E IR IM CF bee sees 3 3 Table 3 5 MPC860P SIU Register Block Map sse 3 4 Table 3 6 MPCS860P Ports Aand C eec rendue t ERE PPS I EDDIE 3 6 Table 3 7 Processor BDM Pin Assignments csssesesesesse e 3 7 Table 4 1 I2C EEPROM Registers ssc t eere erem mr ee Sette E Y eH RO epp ree sere 4 1 Table 4 2 I2C EEPROM Memory Map zsdezeterkeert t meer ee TUNRA ee nd ea 4 2 Table 4 3 RAM Acess TIME isses rm Rete rer RR EY S EEEE EEEE EEEE E E ee N 4 3 Table 5 1 MPC860P CPM Register Block Map lesse 5 1 Table
127. sed to reconfigure the board after modifications to the nonvolatile memory nvdisplay The configuration values are displayed in groups Each group has a number of fields Each field is displayed as a hexadecimal or decimal number or as a list of legal values To display the next group press space or cr To edit fields within the displayed group press E To quit the display press lt ESC gt or Q To save the changes type the command nvupdate To quit without saving the changes type the command nvopen Table 8 1 shows all the groups and fields you can edit when you use the nvdisplay command At the monitor prompt type nvdisplay Press cr until the group you want to modify is displayed An example for the group Console is shown below 10002367 02 PmT1 and PmE1 User s Manual 8 13 Monitor NVRAM Commands yY Oo wu A W Description Caution A Description Group Console PortA A B Baud9600 ParityNone Even Odd None Force Data8 bits 5 Bits 6 Bits 7 Bits 8 Bits StopBits2 bits 1 Bit 2 Bits ChBaudOnBreakFalse False True RstOnBreakFalse False True SP CR to continue or E e to Edit Press E to edit the group Press cr until the field you want to change is displayed Type a new value For most fields legal options are displayed in parentheses Press lt ESC gt or Q to quit the display Type nvupdate to save the new value or nvopen to cancel the change by r
128. sing the time slot assigner Each of the internal clocks RCLK TCLK for each SCC can be driven by one of four baud rate generators or one of four external clock pins These clocks have a top rate of one half of the system clock 20 MHz at 40 MHz Serial Management Controllers SMC The MPC860P contains two SMCs configured as UART ports SMC1 is assigned as the DCE console port A and SMC2 is assigned as the DCE download port B The SMC physical inter face is implemented via the serial interface and time slot assigner and may also be con nected to a TDM channel The clock is driven by either one of four baud rate generators or from an external clock pin Time Slot Assigner TSA The TSA allows any combination of SCCs and SMCs to multiplex their data together on either one ortwo time division multiplexed TDM channels A TDM is defined as a serial channel which is divided into channels separated by time Common examples of TDM chan nels are T1 E1 CEPT PCM Highway ISDN Primary Rate and ISDN Basic Rate IDL and GCI You may define your own interface as well The serial interface with TSA implements both the internal route selection and if necessary time division multiplexing for multiplexed serial channels The TSA is completely indepen dent of the protocol used by the SCCs and SMCs The purpose of the TSA is to route data from the specified pins to the desired SCC or SMC at the correct time The SCCs and SMCs then handle the data the
129. ss through the entire memory region and verifying each location The function RotTest performs a long word oriented test of the specified memory region Each memory location is tested by rotating a single bit through the long word location The function PingPongAddrTest is used to test the reliability of memory accesses in an envi ronment where the data addresses are varying widely The intention is to cause the address buffers and multiplexors to change dramatically The function Interact is used to test byte interaction in the memory region specified by StartAddr and EndAddr The main goal of this test is to check for mirrors in memory This is accomplished by testing the interaction between bytes at different points in memory xprintf xprintf CtrlStr Arg0 Argl ArgN char CtrlStr unsigned long Arg0 Argl ArgN xsprintf Buffer CtrlStr Arg0 Argl ArgN char Buffer CtrlStr unsigned long Arg0 Argl ArgN This function serves as a System V UNIX compatible printf without floating point It implements all features of d 0 u x X c and s An additional control statement has been added to allow printing of binary values 75b The xprintf and xsprintf functions format an argument list according to a control string Ctrl Str The function xprintf prints the parsed control string to the console while the function xsprintf writes the characters to the Buffer The control string format is a string that co
130. ster getICTRL and writelCTRL read and write the Instruction Control register This allows user control of the ICTRL register which controls instruction serialization and instruction show cycles STANDARD MONITOR FUNCTIONS atoh unsigned long atoh p char p unsigned long atod p char p unsigned long atoo p char p unsigned long atob p char p 10002367 02 Monitor Standard Monitor Functions Description Description Arguments unsigned long atoX p Base char p int Base BinToHex Val unsigned long Val HexToBin Val unsigned long Val FindBitSet Number unsigned long Number These functions are a collection of numeric conversion programs used to convert character strings to numeric values convert hexadecimal to BCD BCD to hexadecimal and to search for bit values The atoh function converts an ASCII string to a hex number The atod function converts an ASCII string to a decimal number The atoo function converts an ASCII string to an octal number The atob function converts an ASCII string to a binary number The function atoX accepts both the character string p and the numeric base Base to be used in converting the string This can be used for numeric bases other than the standard bases 16 10 8 and 2 The BinToHex function converts a binary value to packed nibbles BCD The HexToBin function converts packed nibbles BCD to binary This function accepts the parameter Val
131. ster C100 0008 08 Byte PCI Revision ID register C100 0009 09 3Bytes PCI Class Code register 10002367 02 PmT1 and PmE1 User s Manual PMC PCI Interface PCI9060ES Register Map Local Bus PCI Offset Address hex Address hex Size Register Name continued C100 000C 0C Byte PCI Cache Line Size register C100 000D 0D Byte PCI Latency Timer register C100 000E OE Byte PCI Header Type register C100 000F OF Byte PCI Built in Self Test BIST register C100 0010 10 Long PCI Base Address register for memory access to Local Configuration and Shared Runtime registers C100 0014 14 Long PCI Base Address register for I O access to Local Configuration and Shared Runtime registers C100 0018 18 Long PCI Base Address register for memory access to local address space C100 001C2F 1C2F E reserved C100 0030 30 Long PCI Expansion ROM Base register C100 0034 3B 343B reserved C100 003C 3C Byte PCI Interrupt Line register C100 003D 3D Byte PCI Interrupt Pin register C100 003E 3E Byte PCI Min Gnt register C100 0000 3F Word PCI Max Lat register Local Configuration Registers The Local Configuration registers map PCI memory and I O into the local memory map These registers may be accessed via local space They may also be accessed via PCI memory and I O space based on the values in the PCI base address registers at C100 001046 and C100 001446 Table 7 2 Local Configuration Registers Local Bus PCI Offset Address hex Address
132. synchronous baud rates Synchronous Baud Rates System Frequency 40 MHz Baud Rate Div16 Frequency Error Kbaud Value Clock Divider 1 Actual Frequency 1544 T1 1 26 1538 5 0 4 2048 E1 1 20 2000 2 3 SERIAL CONNECTOR PIN ASSIGNMENTS The PmT1 and PmE1 module has a 64 pin connector for the serial I O interface The P14 pin assignments including the VME PO and VME P2 pin numbers specific to Emerson base boards are shown in Table 5 6 The VME P2 pin numbers are listed for a module installed in expansion site 1x The VME PO pin numbers are listed for a module installed in expansion site J2x Reference PMC Connector Pin Assignments Section for the remaining PMC connectors P11 and P12 and Front Panel I O Section for the front panel I O connectors P1 and P2 P14 PO P2 Pin Assignments P2Pin Signal P14Pin POPin P2Pin Signal C1 Console RxData 2 C2 Console TxData 4 E 6 z z CA GND 8 C5 A4 Download RxData 10 A5 A5 Download TxData B E 12 10002367 02 PmT1 and PmE1 User s Manual Serial I O serial Connector Pin Assignments P14 Pin POPin P2Pin Signal P14Pin POPin P2Pin Signal 13 14 B6 A7 GND 15 A6 C8 TDM 2 TxTip 16 E7 A8 TDM 2 TxRing 17 o 18 C7 A9 TDM 2 RxTip 19 B7 C10 TDM 2 RxRing 20 A7 A10 TDM 1 TxTip 21 E6 cn TDM 1 TxRingl 22
133. t Access Description FF00 0AB8 Port B Direction 27 R W Set SDA as an input or an output PBDIR 0 Input 1 Output FF00 0AC4 Port B Data 26 R W C EEPROM Clock Line SCL PBDAT 0 Drives SCL low 1 Drives SCL high FF00 0ACA4 PBDAT 27 Ww 12C EEPROM Line Driver SDA 0 Drives SDA low 1 Drives SDA high FF00 0AC4 PBDAT 27 R 12C EEPROM Data on DO SDA 10002367 02 PmT1 and PmE1 User s Manual g On Card Memory Configuration On card DRAM Table 4 2 Note I C EEPROM Operation The IC EEPROM supports a bidirectional bus oriented protocol The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver The device controlling the transfer is the CPU and the I C EEPROM being controlled is the slave The CPU always initiates data transfers and provides the clock for both transmit and receive operations Initialization software for the I2C EEPROM should issue a start condition immediately fol lowed by a stop condition to reset EEPROM to a known state since the chip maintains its state even between power ups Emerson Memory Map The following memory map convention has been established by Emerson for data storage within the I C EEPROM This map allows various operating systems to store their boot parameters without affecting each other I C EEPROM Memory Map Hex Byte Offset Description 400 7FF User nonvolatile data storage 300 3FF Reserved for the operating system
134. t FFF0 0000 CPU Registers FF00 0000 Reserved C101 0000 ieee C100 0000 ne ss egisters C000 0200 meer rye C000 0180 San on egister Kein IDs me ts C000 0000 p Reserved 8000 0000 PCI I O Space 6000 0000 PCI Memory Space 4000 0000 Reserved 0100 0000 DRAM 0000 0000 10002367 02 PmT1 and PmE1 User s Manual E Overview Additional Information Table 1 1 Address Summary Table 1 2 Physical Address Access _ See hex Mode Description Page FFF0 0000 R Flash ROM Socket 4 1 FF00 0000 R W CPU registers 3 2 C101 0000 reserved C100 0000 R W PMCJPCI Interface registers 72 C000 0200 reserved C000 0180 R Board Configuration register 4 3 C000 0080 reserved C000 000C OR Conventional Interrupt register 3 4 C000 0000 R Interrupt Vector register 34 8000 0000 reserved 6000 0000 R W lt PCII O Space 7 2 4000 000 R W PCI Memory Space 72 C101 0000 reserved 0000 0000 R W DRAM 4 2 ADDITIONAL INFORMATION This section lists the PmT1 and PmE1 hardware s regulatory certifications and briefly dis cusses the terminology and notation conventions used in this manual It also lists general technical references Mean time between failures MTBF is listed in the following table MTBF Hours Product Calculation Method Hours PmT1 Bellcore Issue 5 344 234 PmE1 Telecordia Issue 1 1 333 573 Product Certification The PmT1 and PmE1 hardware has been tested
135. t depending on the configuration of nonvolatile memory The monitor initializes i e writes to this area but itis left up to the programmer to initialize any other accessible memory areas such as off card or module memory COMMAND SYNTAX Each command may be typed with the shortest number of characters that uniquely identify the command For example you can type nvd instead of nvdisplay There is no distinction between uppercase and lowercase Note however that abbreviated command names cannot be used with on line help you must type help and the full command name Press Enter or Return carriage return lt cr gt to execute a command The command line accepts three argument formats string numeric and symbolic Arguments to commands must be separated by spaces Monitor commands that expect numeric arguments assume a default base for each argument However the base can be altered or specified by entering a colon followed by the base as in the following examples 1234ABCD 16 hexadecimal 123456789 10 decimal 101010 2 binary g PmT1 and PmE1 User s Manual 10002367 02 Monitor Initializing Memory Definition Example INITIALIZING MEMORY The monitor uses the area between 0000 000046 and 0001 00004 for interrupt vector stack data and bss space Any writes to that area can cause unpredictable operation of the monitor The monitor initializes all local memory on power up and or on reset depending on th
136. t only the data in the ssss field is 3counted 0000 is the address field in this record the address field is meaningless so it is always 0000 The sec ond 02 is the record type in this case an extended address record cs is the checksum of all the fields except the initial colon gt 020000020020DC In this example the segment address is 002046 This means that all subsequent data record addresses should have 20046 added to their addresses to determine the absolute load address Data Record 11aaaa00di1d2d3 dncs is the record start character 11is the record length aaaais the load address This is the load address of the first data byte in the record d1 relative to the current segment if any 00is the record type di dnare data bytes csis the checksum gt 0400100050D55ADF8E In this example there are four data bytes in the record They are loaded to address 1046 if any segment value was previously specified it is added to the address 5046 is loaded to address 1046 D546 to address 1146 5A46 to address 1216 and DF4gto address 1346 The checksum is 8E4g Start Address Record 04000003ssssoooocs is the record start character 04is the record length 0000is the load address field always 0000 03is the record type ssssis the start address segment oooois the start address offset csis the checksum gt 040000035162000541 In this example the start address segment is 516246 and the st
137. t up as an active low high to low transition interrupt Consult the MPC860 PowerQUICC User s Manual for details on configuring the port C interrupt The MDI interface is intended for very low bandwidth communications and or power up configuration The opcode specifies whether a read write or reset cycle is to take place The register address and data are written to and read from the PmT1 and PmE1 modules The PmT1 and PmE1 MDI provides the ability to identify the module monitor interrupts and access the serial configuration Table 6 7 provides the protocol format for communicat ing with the MDI interface For MDI example code contact an Emerson Network Power Technical Support representa tive visit http www emersonembeddedcomputing com contact postsalessupport html on the Internet send e mail to support artesyncp com or call 800 327 1251 10002367 02 PmT1 and PmE1 User s Manual TDM Interface Front Panel O Table 6 7 MDI Bit Field Format Field Width Function Start 2 The 01 transition frames the beginning of an MDI cycle The MDI Interface is reset when the MDIO line which is pulled up is high for greater than 40 clocks OpCode 3 0005 Reserved 0015 Reserved 0105 Module ID Register Read returns 0246 0115 Module Interrupt Register Read Bits 0 3undefined Bit 4INT1 from DS2153 DS2151 Channel 1 Bit 5INT2 from DS2153 DS2151 Channel 1 Bit 6INT1 from DS2153 DS2151 Channel 0 Bit 7INT2 from DS2153
138. teAddrTest BaseAddr TopAddr unsigned char BaseAddr TopAddr WordAddrTest BaseAddr TopAddr unsigned short BaseAddr TopAddr LongAddrTest BaseAddr TopAddr unsigned long BaseAddr TopAddr RotTest BaseAddr TopAddr unsigned long BaseAddr TopAddr PingPongAddrTest BaseAddr TopAddr unsigned long BaseAddr TopAddr Interact Mod StartAddr EndAddr int Mod unsigned char StartAddr EndAddr The function TestSuite and the memory tests which make up this function verify a memory interface Each of these functions accepts two arguments BaseAddr and TopAddr which describe the memory region to be tested The argument TSPass defines the number of passes to perform Each test and the intended goals of the test are described briefly below PmT1 and PmE1 User s Manual 10002367 02 Monitor Standard Monitor Functions Description The function ByteAddrTest performs a byte oriented test of the specified memory region Each location is tested by writing the lowest byte of the location address through the entire memory region and verifying each location The function WordAddrTest performs a word oriented test of the specified memory region Each location is tested by writing the lowest word of the location address through the entire memory region and verifying each location The function LongAddrTest performs a long oriented test of the specified memory region Each location is tested by writing the location addre
139. tion is provided as required by this agency This device complies with part 15 of the FCC Rules Operation is subjectto the following two conditions 1 This device may not cause harmful interference and 2 this device must accept any interference received including interference that may cause undesired operation FCC RULES AND REGULATIONS PART 15 This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to part 15 of the FCC Rules These limits are designed to provide reason able protection against harmful interference when the equipment is operated in a commer cial environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful inter ference to radio communications Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interfer ence at his own expense Making changes or modifications to the PmT1 and PmE1 hardware without the explicit consent of Emerson Network Power could invalidate the user s authority to operate this equipment EMC COMPLIANCE The electromagnetic compatibility EMC tests used a PnT1 and PmE1 model that includes afront panel assembly from Emerson Network Power For applications where the PmT1 and PmE1 is provided without a front panel or where the front panel has been
140. tions The last parameter ch is the character to be written The number of bytes written to the device or the value read from the device is returned depending on mode getchar getchar putchar c char c s30 PmT1 and PmE1 User s Manual 10002367 02 Monitor PmT1 and PmE1 Specific Functions Description Description KBHit void RKBHit TxMT RTxMT These functions provide the low level I O necessary to read write and configure the MPC860P These functions are used to interface to both the console and modem device specified by the argument Port The getchar function reads a character from specified device Port This function is also set up to check for a break and allows the monitor to perform functions like reset or baud changes when a break is detected The function putchar writes the character c to the specified device The functions KBHit and RKBHit poll the console and modem devices for available charac ters If the receiver indicates a character is available these functions return TRUE other wise they return FALSE The functions TxMT and RTxMT poll the console and modem devices if the transmitter can accept more characters If the transmitter indicates a character can be sent these functions return TRUE otherwise they return FALSE InitBoard InitBoard ConfigCaches These functions provide initialization of the board s interfaces at various points in the mon itor Both these functio
141. tures Asynchronous operation between the local and PCI buses operating at up to 33 33 MHz Bi directional bus locking Doorbell interrupts EEPROM power on initialization PCI9060ES REGISTER MAP The PCI9060ES is controlled through registers that are accessible by the MPC860P and the baseboard on which the PmT1 and PmE1 is mounted The registers fall into four groups PCI Configuration registers Local Configuration registers Shared Runtime regis ters and Local DMA registers The local base address of these registers is C100 000046 The PCI base address of these registers is programmable The PCI9060ES registers are readable and writable in byte word or long word accesses unless noted otherwise See page 7 3 for a description of the Emerson specific initialization of these registers For details on the bit fields and functionality of these registers refer to the PCIS060ES data sheet PCI Configuration Registers The PCI Configuration registers are also known as the configuration header The configu ration header is accessed via configuration space The registers map baseboard local mem ory the Local Configuration and Shared Runtime registers into the PCI memory map PCI Configuration Registers Local Bus PCI Offset Address hex Address hex Size Register Name C100 0000 00 Word PCI Vendor ID register C100 0002 02 Word PCI Device ID register C100 0004 04 Word PCI Command register C100 0006 06 Word PCI Status regi
142. uipment Radio Disturbance Characteristics Limits and Methods of Measurement EN55024 Information Technology Equipment Immunity Characteristics Limits and Methods of Measurement ETSI EN300386 Electromagnetic Compatibility and Radio Spectrum Matters ERM Telecommunication Network Equipment Electromagnetic Compatibility EMC Requirements Emerson maintains test reports that provide specific information regarding the methods and equipment used in compliance testing Unshielded external I O cables loose screws or a poorly grounded chassis may adversely affect the PmT1 and PmE1 hardware s ability to comply with any of the stated specifications The UL web site at ul com has a list of Emerson s UL certifications To find the list search in the online certifications directory using Emerson s UL file number E190079 There is a list for products distributed in the United States as well as a list for products shipped to Can ada To find the PmT1 and PmET search in the list for 01439143 xx where xx changes with each revision of the printed circuit board 10002367 02 PmT1 and PmE1 User s Manual Overview Additional Information Active low signals Byte word PLD Radix 2 and 16 Table 1 5 RoHS Compliance The PmT1 and PmE1 are compliant with the European Union s RoHS Restriction of Use of Hazardous Substances directive created to limit harm to the environment and human health by restricting the use of harmf
143. ul substances in electrical and electronic equipment Effective July 1 2006 RoHS restricts the use of six substances cadmium Cd mercury Hg hexavalent chromium Cr VI polybrominated biphenyls PBBs polybrominated diphenyl ethers PBDEs and lead Pb Configurations that are 5 of 6 are built with tin lead solder per the lead in solder RoHS exemption To obtain a certificate of conformity CoC for the PmT1 and PmE1 modules send an e mail to sales artesyncp com or call 1 800 356 9602 Have the part number s e g CO00 for your configuration s available when contacting Emerson Terminology and Notation An active low signal is indicated with an asterisk after the signal name Throughout this manual byte refers to 8 bits word refers to 16 bits and long word refers to 32 bits double long word refers to 64 bits This manual uses the acronym PLD as a generic term for programmable logic device also known as FPGA CPLD EPLD etc Hexadecimal numbers end with a subscript 16 Binary numbers are shown with a subscript 2 Technical References Further information on basic operation and programming of the PmT1 and PmE1 compo nents can be found in the following documents Technical References Device Interface Document Controller T1 E1 DS2153Q E1 Single Chip Transceiver Data Sheet Dallas Semiconductor REV 01106 DS2151Q T1 Single Chip Transceiver Data Sheet Dallas Semiconductor REV 011706 Applicati
144. uration Register Initialization eee ee 7 5 Table 7 6 PCI9060ES Shared Runtime Register Initialization sels eee ee eee ee 7 6 Table 7 7 PCISOGOES Bus Priority Control eerte cerne hen eu 7 7 Table 7 8 PCI to Local Slave Access Timing cece cece cent eee e eee eee eee 7 8 10002367 02 PmT1 and PmE1 User s Manual Es Table 7 9 Connector P11 and P12 Pin Assignments 0 cece eee e eee eee eens 7 9 Table 8 1 NVRAM Configuration Groups 0 cece cece eee eee eee eee n eens 8 2 Table 8 2 Device Download FotMat scccctsscns ps cecestacesctesethesssttecenenreeaes 8 9 Table 8 3 NVRAM Power up Diagnostic PASS FAIL Flags 0 cece cece eee eee eee 8 17 Table 8 4 PLX Mailbox 0 Sequence and Fail Mask Bits 0 00 cece eee ee eee eee 8 17 Table 8 5 Error and Screen Messages eee eee cence e mme 8 28 Table 8 6 Assigned Exception Vectors 0 cece cece eee I 8 34 Table 8 7 IsLegal Function Types eee cece cece mme 8 39 Table 8 8 NVOp Cormmiand suce coda Ee teresa eic stock E be Da eu bd cathe 8 41 Table 8 9 NVOP Error Codes isses e Rec RO Ra ie eR RR YRERIRRRERSZQERER RUE 8 42 H PmT1 and PmET User s Manual 10002367 02 Registers Register 4 1 Board Configuration 0 BCR 0x010 2 cece cece cece cece eee II 4 3 10002367 02 PmT1 and PmE1 User s Manual m blank page E PmT1 and PmET User s Manual 10
145. valid contents i e this is not the first power up If NVRAM is not valid power up diagnostics are run If NVRAM is valid the PowerUpDiags bit is checked to see if diagnostics should be run Refer to Step 6 for a description of the default NVRAM configuration parameters including PowerUpDiags If PowerUpDiags is off the system level initialization is performed Power up Diagnostics Hello World is printed on the console Memory size is read from the configuration register and printed on the console The decrementer and timebase timer is checked for functionality The character sequence 89ABCDEF is printed to test the print hex ASCII routine A Write Read test is performed at location 0x40000 0x05050a0a and its complement is written and read Then an address boundary test is performed System level initialization sets up the system for running compiled C code BSS is cleared The dynamic data section is relocated from ROM to its linked address space starting at 0x2000 The RAM based interrupt vector table is initialized The interrupt prefix is changed to point to the RAM based interrupt table at 000000000 The stack is initialized at OxFFF8 All interrupt vectors in the interrupt vector table are initialized to use the unexpected interrupt handler This handler prints the message Unexpected Interrupt and restarts the monitor Masking of interrupts is reinforced The memory parameters for system memory management e g Malloc are initializ
146. which is assumed to contain a single hex number of value 0 99 The FindBitSet function searches the Number for the first non zero bit The bit position of the least significant non zero bit is returned BootUp BootUp PowerUp int PowerUp The BootUp function is called immediately after the nonvolatile memory device has been opened and the board has been configured according to the nonvolatile configuration This function also determines if memory is to be cleared according to the nonvolatile configura tion and the flag PowerUp The monitor provides an autoboot feature that allows an application to be loaded from a variety of devices and executed This function uses the nonvolatile configuration to deter mine which device to boot from and calls the appropriate bootstrap program The monitor supports the EPROM ROM BUS and SERIAL autoboot devices which are not hardware specific The remainder of the devices may or may not be supported by board specific func tions described elsewhere The flag PowerUp indicates if this function is being called for the first time If so memory must be cleared 10002367 02 PmT1 and PmE1 User s Manual 8 37 Monitor Standard Monitor Functions 8 38 See also Description Description StartMon c NvMonDefs h NVTable c Boot Commands Section InitFifo InitFifo FPtr StartAddr Length struct Fifo FPtr unsigned char StartAddr int Length ToFifo FPtr c struct Fifo
147. y receive The TSA also supports e lor2clocks per data bit programmable delay 0 3 bits between frame sync and frame start fourprogrammable strobe outputs twoclock output pins 10002367 02 PmT1 and PmE1 User s Manual E Serial I O UART Baud Rate Selection Table 5 4 frames up to 8 kilobits long UART BAUD RATE SELECTION The clock sources for each SCC are defined in the SICR register FFOO OAEC and for each SMC are defined in the SIMODE register FF00 0AEO046 Any one of four internal baud rate generators or an external clock may be used The internal baud rate generators are contained in the CPM They can deliver a maximum baud rate at one half of the system clock rate and may be changed on the fly Each baud rate generator may be routed to multiple SCCs and SMCs The baud rate produced by a generator is set within the corresponding Baud Rate Generator Control BRGC register FF00 09F0 9FC46 The baud rate is calculated from the system frequency 40 MHz and the values stored in the BRGC register and depends on whether the serial controller is operating in asynchronous or synchronous mode The formula for the asynchronous baud rate is async baud rate system frequency clock divider 1 x Div16 x 16 The clock divider value is stored in bits 12 1 of the BRGC The Div16 value 1 or 16 is selected with bit 0 of the BRGC Table 5 4 lists the clock divider and Div16 values associated with typi
148. yed is determined by lines If the lines argument is not specified sixteen lines of memory are shown The data is displayed as hex character values on the left and printable ASCII equivalents on the right Nonprintable ASCII characters are printed as a dot displaymem startaddr lines Press any key to interrupt the display If the previous command was displaymem pressing cr displays the next block of memory fillmem fills memory with value starting at address startaddr to address endaddr fillmem b w 1 value startaddr endaddr For example to fill the second megabyte of memory with the data 0x12345678 type gt fill 1 12345678 100000 200000 findmem searches memory for a value from address startaddr to address endaddr for memory loca tions specified by the data searchval findmem b w 1 searchval startaddr endaddr findnotmem searches from address startaddr to address endaddr for memory locations that are different from the data specified by searchval findnotmem b w l searchval startaddr endaddr findstr searches from address startaddr to address endaddr for a string matching the data string searchstr findstr searchstr startaddr endaddr readmem reads a memory location specified by address This command displays the data in hexadeci mal decimal octal and binary format readmem b w 1 address 10002367 02 PmT1 and PmE1 User s Manual 8 11 Monitor Memory Register Commands Description Descripti
149. ymem 8 11 iV aa ADA vh eia seas 8 27 download sssss 8 19 eepromtest ss 8 18 fillimem ion repr en 8 11 findmem e eee eee 8 11 findnotmem 66 8 11 FIRASER sees ete em ee 8 11 help sessi er awe een 8 10 Memes edecanes 8 18 TU PEE E TEE 8 28 nvdisplay 8 9 8 13 8 17 DVihlE isis ce ph net 8 14 10002367 02 NVOPEN ss ave sae ra 8 14 DVSEE sc sania dee p es 8 15 nvupdate 8 9 8 15 Farid sss sas Rd 8 28 readmMeM 2 2 00 cece eee 8 11 setmem cece eee eee 8 12 Sub silver E e rr eee 8 28 swapmem sese 8 12 testmem 0c eee eee 8 12 transmode eee eee 8 20 IITs ecc SATUS ae iene dae aie 8 12 writemem ee eee eee 8 12 writestr cece cece eee eee 8 13 monitor function 4 8 37 BUGD sc eso da wade wen eee 8 36 F101 Ba ar 8 36 atoli axcaiasinddea e FERE CAN 8 36 BOO MM 8 36 Ej dE 8 37 baud isse se mere 8 42 baud_d cece eee eee 8 43 BiniTOHex diet eda 8 37 ByteAddrTest 8 44 CallOGs 3 eit rere 8 39 C Fre EM 8 39 ChangeBaud 8 30 char get eicere ees 8 42 charget d eres 8 42 Gr MSR eo cases 5 ead enw oe 8 36 CMPS rannani e rh wen 8 43 ConfigCaches 8 31 ConfigSerDevs 8 30 ConnectHandler 8 34 disable_dcache 8 33 disable icache 8 33 DisConnectHandler 8 34 DispGroup

Emerson NT5C06D Power Supply User Manual

Contents

Download Pdf Manuals

Related Search

Related Contents