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Emerson KAT4000 Network Hardware User Manual

1. 9005 HOMO NOSYAWA B Polar lt O Ae B E J33 u19 u28 u36 Clock Clock Clock 7 Tun E Connect U56 al fl E 102911 5 1315 Ud 32 Q E Uis DDR2 de SODALIS 545 PLD fi SO DIMM ws 9305 3 5 pur BJ IN M 0323 B 8 Ed luetquaaquez m ax E 7 Fone z
2. 9002 1404402 BER 2 PI i E NAI lt bok Bik Beal gud wee Conn 5 E m 5 i 8 mu Eodem us 6 5 JP4 Serial Port 1 4 IPMC m 002 4 5 7 10 Fat Pipe Module BIE 9s 13 16 Host CPU Tem 201 E fe B 16 8 uan s lt JP3 PLD Prog JTAG d EM um E uzoduzaduzs css casn oM a ical OU wmm 5 EHE NER ABABA E e g w EEE Bul L UY
3. 9007 HOMO NOSYAWA AAAAAAAAAGAG am 816 aC 2009 0 8 a 8 cri E F7 Fuse e2007 EE for 3 3 Volt Supply to 435 JTAG 0 75A g zo 18 B AN TS fng s J35 JTAG Emulation Header B cu eg a Cris g SBER E SW3 Front Panel Reset B C amp uico uio DA a g I 8 2E SE oe 8 IE E fa 5 8 a 2778 E gi g B s adi m cres aa 8 ces aou NEN ou aa 4 aa fig id un a aa 15 gaa Switch i B a a 38 Ane m e ET zu E F 1 Bg ues pg 8 i eS Bg g Soa af deg TT i E E a oa js a z E T Bia as a F10 Fuse B QT a for 3 3 Volt Supply to JP3 JTAG 0 75A meum nd ig B Hg aoe 105 1g gs a ust B 8 8 P B ug ee s
4. KAT4000 Records Value Parameter Status continued Deassertion Event Mask 4800 Lower Non Recoverable Threshold comparison returned Upper Non Recoverable Going High supported Discrete Reading Mask 3838 Upper Non Recoverable Threshold settable Upper Critical Threshold settable Upper Non Critical Threshold settable Upper Non Recoverable Threshold readable Upper Critical Threshold readable Upper Non Critical Threshold _ readable _ Sensor Units 1 00 Analog Data Format unsigned RateUnit Modifier Unit none Percentage no Sensor Units 2 Base Unit 05 Amps _ Sensor Units 3 Modifier Unit 00 Unspecified m Linearization 00 B 2 lea M Tolerance 40 B 00 00 00 _ R exp B Exp d Analog Characteristic Flags 07 NominalReading 000 66 Normal Maximum Normal Minimum 00 _ Sensor Maximum Reading ff lt Sensor Minimum Reading 00 Upper ff Threshold _ Upper Critical Threshold 00 UpperNon Critical Threshold 00 Lower Non Recoverable o Threshold _ Critical Threshold 00 te B _ Lower Non Critical Threshold 00 Positive Going Thre
5. hour backup 1 00 Real Time Clock Block Diagram 5 1 gt 1Hz Oscillator Divider Seconds OSCO 32 768 KHz Minutes FT OUT v Century Hours Voltage V Sense and ol SS Switch Day VBAT Circuitry Date Month Serial SEL Bus Y Year SDA Interface M Address Register nd Control The M41T00 clock operates as a slave device on the serial bus To obtain access the RTC implements a start condition followed by the correct slave address DOh Access the eight bytes in the following order Seconds register Minutes register Century Hours register Day register Date register Month register 10007175 02 KAT4000 User s Manual Real Time Clock clock Operation 7 Yearsregister 8 Control register Table 11 1 CEB CB KAT4000 User s Manual The M41T00 clock continually monitors the supply voltage Vcc for an out of tolerance condition If Vcc falls below switch over voltage Vso the M41T00 Terminates an access in progress Resetsthe device address counter Does notrecognize inputs prevents erroneous data from being written At power up the M41T00 uses at Vso and recognizes inputs CLOCK OPERATION Read the seven Clock registers one byte at a time or in a sequential block Access the Con trol register address location 7 independently An
6. KAT4000 Records Value Parameter Status Record ID 0002 SDR Version 51 Record Type 01 Full Sensor Record Record Length 38 Sensor Owner ID _00 Sensor Owner LUN 00 Sensor Number 00 Entity ID a0 Entity Instance 60 Sensor Initialization 67 Init Scanning Init Sensor Type Init Events gt Sensor Scanning enabled Event Generation _ enabled Sensor Capabilities 4 Ignore Sensor no Auto Re Arm enabled gt Sensor Hysteresis no hysteresis Sensor Threshold Access no threshold Event Message Control global disable only Sensor Type f Event Reading Type Code ef Sensor Specific Assertion Event Mask 000f Deassertion Event Mask 0000 Discrete Reading Mask 000f Sensor Units 1 00 Analog Data Format unsigned Rate Unit none Modifier Unit none Sensor Units 2 Base Unit 00 Unspecified KAT4000 User s Manual 10007175 02 Appendix B sensor Data Records KAT4000 Records _ Value Parameter Status continued Sensor Units 3 Modifier Unit 00 Unspecified Linearization 00 M 00 M Tolerance 00 B 00 00 Accuracy Accuracy Exp 00 00 00 Analog Characteristic Flags 00 Nominal
7. Deassertion Event Mask 4800 Lower Non Recoverable Threshold comparison returned Upper Non Recoverable Going High supported Discrete Reading Mask 3838 Upper Non Recoverable Threshold settable Upper Critical Threshold settable _ Upper Non Critical Threshold settable _ Upper Non Recoverable Threshold readable Upper Critical Threshold readable Upper Non Critical Threshold readable Sensor Units 1 00 Analog Data Format unsigned Rate Unit none Modifier Unit none Percentage no Sensor Units 2 Base Unit 04 Volts Sensor Units 3 Modifier Unit 00 Unspecified Linearization 00 M 06 M Tolerance 00 B 00 B Accuracy 00 Accuracy Accuracy Exp 00 R exp B Exp e0 Analog Characteristic Flags 07 Nominal Reading c8 Normal Maximum d6 Normal Minimum 00 Sensor Maximum Reading fe Sensor Minimum Reading 00 Upper Non Recoverable 10 Threshold Upper Critical Threshold 00 Upper Non Critical Threshold 00 Lower Non Recoverable 00 Threshold Lower Critical Threshold 00 Lower Non Critical Threshold 00 Positive Going Threshold Hyst 02 Value Negative Going Threshold Hyst 00 Value OEM 00 34 KAT4000 User s Manual 10007175 02 Appendix B sensor Data Records KAT4000 Records Value ID String Type Len
8. Priority Function _ Request continued 8 receive 9 MCC2 receive 10 MCC1 transmit 11 MCC2 transmit 12 FCC2 receive 13 FCC2 transmit 14 FCC3 receive 15 FCC3 transmit 16 SCCI receive 17 SCCI transmit 18 SCC2 receive 19 SCC2 transmit 20 SCC3 receive 21 SCC3 transmit 22 SCCA receive 23 SCC4 transmit 24 IDMA 1 4 Emulation option 2 25 SMC1 receive 26 SMC1 transmit 27 SMC2 receive 28 SMC2 transmit 29 SPI receive 30 SPI transmit 31 2 receive 32 PC transmit 33 RISC timer table Lowest 34 IDMA 1 4 emulation option 3H 1 The priority of each IDMA channel is programmed independently MPC8548 PERIPHERAL MODULES Three Speed Ethernet Controllers TSEC Two TSECs incorporate a MAC sublayer that supports 10 Mbps 100 Mbps and 1 Gbps Ethernet networks See Chapter 4 for information on the Ethernet interface 10007175 02 KAT4000 User s Manual 3 11 Central Processing Unit Processor Reset and Clocking Signals 3 12 Table 3 4 HRESET HRESET_REQ SRESET READY KAT4000 User s Manual Local Bus Controller LBC The MPC8548 LBC connects to external memory DSP and ASIC devices There are three separate state machines General Purpose Chip Select Machine GPCM controls access to asynchronous devices User Programmable Machine UPM interfaces synchronous devices TheSynchronous DRAM SDRAM controller provides access to standa
9. KAT4000 Records Value Parameter Status continued Sensor Initialization 67 Init Scanning Init Sensor Type Init Events Sensor Scanning enabled Event Generation enabled Sensor Capabilities 41 Ignore Sensor no Auto Re Arm enabled Sensor Hysteresis no hysteresis Sensor Threshold Access no threshold Event Message Control global disable only Sensor Type 10 Event Reading Type Code 6f Sensor Specific Assertion Event Mask OOff Deassertion Event Mask 0000 Discrete Reading Mask ooff Sensor Units 1 00 Analog Data Format unsigned Rate Unit none Modifier Unit none Percentage no Sensor Units 2 Base Unit 00 Unspecified Sensor Units 3 Modifier Unit 00 Unspecified Linearization 00 00 M Tolerance 00 B 00 B Accuracy 00 Accuracy Accuracy Exp 00 R exp B Exp 00 Analog Characteristic Flags 00 Nominal Reading 00 Normal Maximum 00 Normal Minimum 00 Sensor Maximum Reading 00 Sensor Minimum Reading 00 Upper Non Recoverable 00 ES Threshold Upper Critical Threshold 00 E Upper Non Critical Threshold 00 Lower Non Recoverable 00 Threshold 10007175 02 KAT4000 User s Manual Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Lower Critical Threshold 00 Lower Non Critical Threshold 00 Positive Going Threshold Hyst 0
10. 8 6 Figure 9 1 IPMC Connections Block Diagram 9 2 Figure 9 2 Extension Command Request 9 7 Figure 9 3 Extension Command Response Example 9 7 Figure 9 4 IPMB Entity StrUctute RR er ORE ET E e ERES E EEUU 9 40 Figure 10 1 Synchronization Clock Circuit 10 1 Figure 11 1 M41T00 Real Time Clock Block Diagram 11 1 Figure 12 1 Zone 1 10 12 1 Figure 12 2 Zone 2 Connectors 20 and 23 and Zone 3 Connectors 30 32 12 3 Figure 12 3 Zone3 Connector 33 44 5 hh hr hr ab anes 12 7 Figure 13 1 General System Block Diagram with Face Plate 13 2 Figure 13 2 RTM Component Top 00 13 4 Figure 13 3 Micro D Console 13 5 Figure 13 4 Standard Console Cable Wiring 10007665 13 6 Figure 13 5 Installing KAT Z3DB RTM on the 4000 13 8 Figure 14 1 Example Monitor Start up Display for KAT4000 with GbE Fat Pipe Switch Module 14 2 Figure 14
11. 9 48 Table 9 46 Firmware Upgrade Prepare 9 49 Table 9 47 Firmware Upgrade Write 9 50 Table 9 48 Firmware Upgrade Complete Command 9 50 Table 9 49 Firmware Upgrade Restore Backup 9 51 Table 9 50 Firmware Upgrade Backup Revision Command 9 51 KAT4000 User s Manual 10007175 02 Tables continued T ble 11 1 Map E ds 11 2 Table 12 1 Zone 1 Connector P10 Pin 12 1 Table 12 2 Zone 2 Connector 20 Pin 12 3 Table 12 3 Zone 2 Connector 23 Pin 12 4 Table 12 4 Zone3 Connector 30 Pin 12 5 Table 12 5 Zone 3 Connector 31 Pin 12 5 Table 12 6 Zone 3 Connector 32 Pin 12 6 Table 12 7 Zone 3 Connector 33 Pin 12 7 Table 13 1 Circuit Board 13 3 Table
12. 36 10007175 02 KAT4000 User s Manual Tables continued Table B 23 12V Current SDR Description B 38 Table B 24 12V Volt SDR Description B 40 Table B 25 4 12 Current SDR Description B 41 Table B 26 B4 12V Volt SDR Description B 43 Table B 27 48V Volt SDR meme B 45 Table B 28 48V Current SDR B 47 Table B 29 48V Source Volt SDR Description B 48 Table 30 48V Source Volt SDR Description B 50 Table B 31 3 3V Management SDR Description B 52 Table B 32 12V Volt SDR Description B 54 Table B 33 12V Current SDR B 56 Table B 34 Firmware Progress SDR B 58 KAT4000 User s Manual 10007175 02 Registers Register3 1 12 Control 12 2 2 2 3 4 Register 3 2 MPC8548 Hardware Implementation Dependent Register 0 HIDO 3 6 Regist
13. 9 20 10007175 02 Overview Processor SDRAM Flash The KAT4000 is a single slot Advanced Telecom Computing Architecture AdvancedTCA ATCA carrier with up to four Advanced Mezzanine Cards AMC expansion modules This expansion capability enables a wide variety of control and packet processing applications such as WAN access traffic processing signaling gateways media gateways and many others ATCA is an open architecture telecom platform as defined by the PICMG 3 0 Revi sion 2 0 AdvancedTCA Base Specification The KAT4000 features on board Ethernet and PCI Express switches for the AdvancedMC Common Options Region where the majority of control plane data flows and a flexible modular Fat Pipe Switch FPS to address data plane traffic in the AdvancedMC Fat Pipes Region The FPS is implemented using a plug over module enabling simple maintenance and a rapid upgrade path when a newer switch fabric is required An optional on board pro cessor gives users additional processing power and can be used to off load system manage ment or OA amp M functionality The KAT4000 is an intelligent Field Replaceable Unit FRU and implements a redundant System Management Bus SMB It also fully supports the Intelligent Plattform Management Interface IPMI with AdvancedTCA extensions to support standards based shelf manage ment allowing it to be monitored by a local shelf management controller or by a rem
14. KAT4000 Records Value Parameter Status Record ID 0020 SDR Version 51 Record 01 Full Sensor Record _ Record Length 37 Sensor Owner ID 00 Sensor Owner LUN 00 Sensor Number 00 _ Entity ID a0 Entity Instance 60 Sensor Initialization 67 Init Scanning Init Sensor Type Init Events Sensor Scanning enabled Event Generation enabled B 58 KAT4000 User s Manual 10007175 02 Appendix B sensor Data Records KAT4000 Records _ Value Parameter Status continued Sensor Capabilities 41 Ignore Sensor no Auto Re Arm enabled Sensor Hysteresis no hysteresis Sensor Threshold Access no threshold Event Message Control global disable only Sensor Type of System Firmware Progress Event Reading Type Code 6f Sensor Specific Assertion Event Mask 0007 System Firmware Progress System Firmware Hang System Firmware Error Deassertion Event Mask 0000 Discrete Reading Mask 0007 System Firmware Progress System Firmware Hang System Firmware Error _ Sensor Units 1 00 Analog Data Format unsigned Rate Unit Modifier Unit none Percentage no _ Sensor Units 2 Base Unit 00 unspecified Sensor Units 3 Modifier Unit 00 unspecified Linearization 000
15. 9 26 Table 9 30 IPMC Watchdog 9 27 Table 9 31 Reset Watchdog Timer 9 29 Table 9 32 Set Watchdog Timer 2 9 30 Table 9 33 Get Watchdog 9 31 Tablg9 347 ER LEDS Re Ea D reg ue E uU DE 9 33 Table 9 35 Get FRU LED Properties Command 9 34 Table 9 36 Get LED Color Capabilities 9 34 Table 9 37 Set FRU LED State Command 9 36 Table 9 38 Get FRU LED State 9 38 9 39 IPMISENSOFS 22 4 ona rhe 9 40 Table 9 40 Event Message 2 9 43 Table 9 41 FRU Definitions 9 44 Table 9 42 Link Descriptors 9 45 Table 9 43 Firmware Upgrade Command Summary 9 47 Table 9 44 Firmware Upgrade Status Command 9 47 Table 9 45 Firmware Upgrade Start
16. 924 TOSynchronization Clocks Set Payload Shutdown Time Out MT9045 and MT9046 Clock Synchronizers 9 25 10 2 Get Module State Command 9 25 Enable AMC Site Command 9 26 Disable AMC Site Command 9 26 11 Real Time Clock IPMC Watchdog Timer Commands 9 27 Block 11 1 Watchdog Timer Actions 9 27 Operation 11 1 Watchdog Timer Use Field and 11 2 Expiration Flags 9 27 Using the Timer Use Field and Expiration Flags 9 28 12 Connectors Watchdog Timer Event Logging 9 28 Zone bre EE 12 1 Monitor Support for Watchdog 12 2 9 29 12 4 Reset Watchdog Timer Command 9 29 Set Watchdog Timer Command 9 29 Get Watchdog Timer Command 9 31 13 Rear Transition Module ERU LEDS iiio deem ne de ex 9 33 Components and Features 13 1 Get FRU LED Properties Command9 34 Functional Overview 13 2 Get LED Color Capabilities Command Circuit 13 3 9 34 Face Plates erences 13 5 Set FRU LED State Command 9 36 Connectors 13 5 Get FRU LED State Command 9 38 Console Serial Ports 13 5 Entities and Entity Associations 9 39 Ethernet Port 13 6 Sens
17. Non Critical Threshold 00 Lower Non Recoverable a0 Threshold Lower Critical Threshold 00 Lower Non Critical Threshold 00 Positive Going Threshold Hyst 02 Value _ Negative Going Threshold Hyst 02 Value OEM 00 ID String Length Code c9 Table B 33 12V Current SDR Description KAT4000 Records Value Parameter Status Record ID 001f SDR Version 51 o Record Type 01 Full Sensor Record Record Length 34 KAT4000 User s Manual 10007175 02 Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Sensor Owner ID 00 Sensor Owner LUN 00 Sensor Number 00 Entity ID 0a Entity Instance 60 Sensor Initialization 7 Init Scanning Init Sensor Type Init Hysteresis Init Thresholds Init Events Sensor Scanning enabled Sensor Capabilities 69 Ignore Sensor Auto Re Arm _ enabled Sensor Hysteresis hysteresis is settable readable Sensor Threshold Access threshold is settable readable Event Message Control global disable only Sensor Type 03 Current Event Reading Code l Threshold Assertion Event Mask 0800 Upper Non Recoverable Going High supported Deassertion Event Mask 4800 Lower Non Recoverable Threshold comparison returned Upper No
18. 14 27 a o 14 13 14 15 switchsrom 14 18 imachin stat tegist r MSR 2 3 9 pina ob ee pas shan ee 110 time between failures MTBF EEE E EEE 14 10 VETSION 14 27 14 21 14 27 boot 6 1 5 2 a prr commands monitor 14 12 14 23 NAND 6 2 monitor Jr ET TATS ee ane auto booting 14 1 find 14 13 no CPU 4000 1 14 1 14 15 Ethernet switch configuration 2 basic 144 default settings A 2 b p d 14 9 filios ceste Ee e en 14 18 1 3 oot commands fruinit 14 19 IEEE JUNE DRE FUSE MEM 14 19 ads line interface CLI command reference command syntax 14 8 Pal VNDE MD 14 9 PES VLAN setup A 2 command line interface 14 1 eas MORAN 14 17 web interface A 18 environment parameter commands 14 17 notation conventions 1 12 14 20 14 17 memory map 6 3 environment variables 14 28 iminfo ge 14 23 file load commands 14 12 ACD ERE 14 17 Flash commands 14 15 S MEM POM OMM E 14 18 2 16 Flash programming 14 1 operating tempera
19. The last pair of hex numbers correspond to the following formula n 1000 where is the unique serial number assigned to each board For example if the serial number of a KAT4000 is 2867 the calculated value is 1867 7481 6 Therefore the board s port 2 Ether net address is 00 80 F9 93 07 4B The ports are assigned as follows eTSEC1 Ethernet debug port eTSEC2 Ethernet core switch eTSEC3 Ethernet core switch and eTSEC4 fat pipe switch module ETHERNET ADDRESS FOR THE GBE FAT PIPE SWITCH MODULE The GbE fat pipe switch module has been assigned the Ethernet address range 00 80 F9 06 C0 00 to 00 80 F9 06 FF FF The address format is the same as described in Ethernet Address for the KAT4000 10007175 02 Common Switch Region PCI Express Switch optional Note Note PCI EXPRESS SWITCH OPTIONAL The optional PLX Technology Inc PEX 8524 PCI Express switch device contains 24 PCI Express lanes and up to six ports The PCle switch supports the following One port connected from each site to the switch AMC 0 and AMC 1 One port connected from the processor to the switch one x1 or one x4 port Fourlanes connected from the fat pipe switch module to the switch with these possible port configurations four x1 ports two x2 ports or one x4 port Features of the switch include PCI Express interface at 2 5 Gbps transfer rate e 24PCI Express lanes SerDes 7 0 and 32 16 and up to six p
20. Connector 8 ju2ofuzsdues B n m ant 8 u68 g 1010000 0800 AOODANBODA we m MPCB548 du m 8 B Processor o gin ATCA A B B Connector E BH en Sg aS m BGB BB LET EB C54 comms n uss a 5 H E B ust ca a 1 9 8 a a 100 Q BB J2 B pns mm 8 Em 8 8 sg swe BB Ki 00808 Polar Key Guide a all jus B BR SB S pex ATCA mm e ps Vig ick PHY a gt Cat cna D g PHY B ug E Smm cuz Y 8 10009000 Uni mm PHY 15 LL uss uso E 0m 0 uu PHY EI Eu Flash les RI EE g O 8 s m 8 uss px 050 0 8 um PHY r le BB u79 use oop oo g a al E mm gm 10008ase T to00Baso T HBEEOBgE 00000 098 swi BERI m 223 80 pin ATCA m g TS Zone 2 48 12 volt Power Supply C464 Connector C463 8 C462 uso Lia EET JP7 BR EL 8 C196 gt m el ald 8 u17 k 8 TM Bm B B B P10 B a F2 34 pin ATCA Fe 1 E Connector Mt Fe Bs dios EIE m Q 047 T n GORGE R201 KAT4000 User s Manual 10007175 02 Setup KAT4000 Circuit Board F
21. Ue 7 7 12 5 VoltSDRDescription a 9 8 1 8 Volt SDR DescriptioIr DE yr FREUE B 11 Table B 9 12 VoltSDR Description aa one B 13 TableB 10 1 0 Volt SDRDescription liess B 15 Table B 11 Volt SDR Description B 17 Table B 12 Inflow Temp SDR B 19 Table B 13 Outflow Temp SDR B 21 Table B 14 Version Change SDR B 24 Table B 15 B1 Hot Swap 50 B 25 Table B 16 2 Hot Swap SDR B 27 Table B 17 Hot Swap SDR B 28 Table B 18 Hot Swap SDR B 30 Table B 19 B1 12V Current SDR Description B 31 Table B 20 B1 12V Volt SDR Description B 33 Table B 21 2 12 Current SDR Description 35 Table B 22 2 12 Volt SDR Description
22. 6 3 Table 7 1 PED Registers cete rer ex READ e een D pe 7 1 Table 7 2 PLD Pin Assignments 7 19 Table 7 3 7 20 Table 8 1 1 Pin Assignments sese rtt dinine sre 8 4 9 1 Network Function 9 3 9 2 Completion Codes RARE SEE 9 4 Table 9 3 Format for IPMI Request Message 9 5 Table 9 4 Format for IPMI Response 9 6 Table 9 5 IPMCIPMI Commands exui sh steal crx 9 9 Table 9 6 Vendor Command Summary 2 9 12 Table 9 7 Get Status Coirimand sue nese 9 13 Table 9 8 Get Serial Interface Properties Command 9 14 Table 9 9 Set Serial Interface Properties 9 15 10007175 02 KAT4000 User s Manual Tables continued Table9 10 Get Debug Level Command 9 16 Table 9 11 Set Debug Level 2 9 17 Table 9 12 Get Hardware Address Command isses 9 17 Table 9 13 Set Hardware Add
23. present 2 0 Management power is disabled 1 Management power is enabled 3 0 Management power is bad 1 Management power is good 4 0 Payload power is disabled 1 Payload power is enabled 5 0 Payload power is bad 1 Payload power is good 6 0 buffer is not attached 1 buffer is attached 7 0 buffer is not ready 1 IPMB L buffer is ready Enable AMC Site Command The Enable AMC Site command is used to enable an AMC site Table 9 28 Enable AMC Site Command Type Byte Request Data 1 3 4 Response Data 1 2 4 Data Field PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems AMC Site ID Completion Code PPS IANA Private Enterprise ID MS Byte first 0 00400 16394 Pigeon Point Systems Disable AMC Site Command The Disable AMC Site command is used to disable an AMC site If an AMC site is disabled the IPMC firmware ignores the AMC inserted and acts as if the AMC is not present Table 9 29 Disable AMC Site Command Type Byte Request Data 1 3 4 KAT4000 User s Manual Data Field PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems AMC Site ID 10007175 02 System Management IPMC Watchdog Timer Commands Table 9 30 Type Byte Data Field continued Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems
24. Hex Address FC40 00B0 Clock Syne Interrupt Register 3 Clock Sync Interrupt Register 2 Clock Sync Interrupt Register 1 FC40 00A8 ock Sync Interrupt Regis er FC40 00A4 Clock Control aTCA CLK3 Register GONG Clock Control aTCA CLK3 A Register CAD 609 c Clock Control AMC4 CLK3 Register FC an ODD Clock Control CLK2 Register Hex Address Clock Control AMC4 CLK1 Register FFFF FFFF Clock Control AMC3 CLK3 Register FFFO 0000 Boot Area 1 MB 4 Clock Control CLK2 Register Reserved cogs Cock Control AMC3 CIK1 Register CCSRBAR 8548 Registers 1 lock Control AMC2 CLKG Register FF70 0000 j Clock Control AMC2 CLK2 Register Reserved FC40 0080 FC88 0000 Clock Control AMC2 CLK1 Register 0000 Socketed Flash if installed 512 KB FC40 007C Gack Control CLKG Register i FC40 0078 FC48 0000 Reserved Clock Control CLK2 Register FC40 0074 FC40 0000 CPLD Registers 512 KB en Clock Control Register Reserved FC18 0000 Sess FC40 006C Fat Pipe Switch Registers Clock Sync Secondary Source 3 FC14 0000 if installed 256 FC40 0068 eae FC40 0064 Clock Syne Secondary Source 2 FC1 2 0000 UD SANE SER Clock Sync Secondary Source 1 Ethernet Core Switch Registers 128 KB FC40 0060 Y REESE a FC10 0000 FC00 8000 eserve FC40 0058 Clock Sync Primar
25. 6 In addition to the basic SDRAM control functions the chip provides several additional DRAM related functions and contains the following performance enhancing features Supports page mode minimizing SDRAM cycles on multiple transactions to the same SDRAM page and can be configured to support up to 16 simultaneously opened pages Supports Error Correcting Code ECC and Read Modify Write RMW in the case of partial writes smaller than 64 bit to DRAM ECC provides single bit error correction and two bit error detection NAND FLASH The KAT4000 uses 512 MB or 1 GB of M systems DiskOnChip NAND Flash starting at physi cal address FC00 0000 for non volatile RAM storage and True Flash File System TFFS The DiskOnChip incorporates an embedded flash controller and memory and features hard ware protection and security enabling features an enhanced programmable boot block enabling eXecute In Place XIP functionality using 16 bit access user controlled One Time Programmable OTP partitions and 6 bit Error Detection Code Error Correction Code EDC ECC 52 KAT4000 User s Manual 10007175 02 Memory Configuration NvRAM Allocation Table 6 2 Table 6 3 NVRAM ALLOCATION The KAT4000 uses two eight kilobyte 12 SROMs for storing non volatile information such as board monitor and operating system configurations as well as information specific to a user s application All Emerson specific data is stored in the uppe
26. B aS 5187 E EET ci ae B SW2 Main Reset 2 um HERB am X E 8 20 ja Mam Ms i ust E ee ims ven al S 25 m 5 ud vo s D g ou la m m SW1 IPMC Reset 711920897 U B N swt EE JP2 1 2 IPMC Mode bit MD2 3 4 IPMC Mode bit MD1 8 4812 vo Power Supply ue BB T JP1 PLD Config Header 2 pem A ket default installed ug s socket default installe a Pm lt 34 Ignore SROM gt 5 6 Enable boot redirection 1 7 8 Logic probe C 4 9 10 Standalone SA mode E 8 P cts ri E F2 Fuse cun F6 Fuse b m 8 for 48 Volt Supply to P10 1A for 48 Volt Supply to Power Supply 10A i 8 F2 F5 Fuse id for 48 Volt Supply to Power Supply 10A smi Bi F4 Fuse F1 Fuse lt for 48 Volt Supply to Power Supply 8A q for 48 Volt Supply to P10 1A n e t F3 Fuse for 48 Volt Supply to Power Supply 8A 10007175 02 KAT4000 User s Manual 2 7 Setup KAT4000 Circuit Board Figure 2 5 Jumper Fuse and Switch Locations Bottom 42000 Hot Swap Switch Header
27. Sensor Number 00 Entity ID 14 Power Module DC to DC Converter Entity Instance 60 Sensor Initialization 7 Init Scanning Init Sensor Type Init Hysteresis Init Thresholds Init Events Sensor Scanning enabled Event Generation enabled Sensor Capabilities 69 Ignore Sensor no enabled Sensor Hysteresis hysteresis is settable readable Sensor Threshold Access threshold is settable readable Event Message Control global disable only Sensor Type 02 Voltage Event Reading Code 01 Threshold Assertion Event Mask 4000 Lower Non Recoverable Threshold comparison returned Deassertion Event Mask 4000 Lower Non Recoverable Threshold comparison returned 10007175 02 KAT4000 User s Manual Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Discrete Reading Mask Upper Non Recoverable Threshold settable Upper Critical Threshold settable Upper Non Critical Threshold settable Lower Non Recoverable Threshold settable Lower Critical Threshold settable B Lower Non Critical Threshold settable Non Recoverable Threshold readable Upper Critical Threshold readable Upper Non Critical Threshold readable Lower Non Recoverable Threshold readable Lower Critical Thres
28. 01111 aTCA B 10000 aTCACLIG A 313 10007175 02 KAT4000 User s Manual 7 17 CPLD Clock Synchronizer Registers 7 18 Note Register 7 20 HM PM Note HIC PIC KAT4000 User s Manual Clock Control Bit Input Source Register 10001 aTCA CLK3 B 14 10010 Sync 1 19 44 MHz 10001 Sync 1 2 048 MHz 10100 5 1 1 544 MHz 10101 8 KHz see note 10110 Sync 2 19 44 MHz 10111 Sync 2 2 048 MHz 11000 Sync 2 1 544 MHz 11001 Sync 3 19 44 MHz 11010 Sync 3 2 048 MHz 11011 Sync 3 1 544 MHz 11100 reserved 11111 reserved This 8 KHz source is generated by the PLD based off Sync 1 clocks Therefore the Sync 1 part must be enabled for this clock to be active Clock Synchronizer Interrupt Registers CSI1 CSI3 The Clock Synchronizer Interrupt registers control the clock synchronizer interrupts Default is 0 for all three registers Default register values are shown in the bottom row of the register table Clock Synchronizer Interrupt Registers 1 3 CSI 1 CSI3 at Oxfc40 00a8 Oxfc40 00ac Oxfc40 00b0 respectively 7 6 5 4 3 2 1 0 HM PM HIC PIC HPI PPI HS PS 1 1 0 0 0 0 0 0 Holdover and PLL Lock Loss Interrupt Masks read write 1 Masks interrupt from being generated to CPU 0 Allows interrupt to be generated to CPU Bits 3 2 are not affected by bits 7 6 Holdover and PL
29. 100 4 e User Rear Transition Module circuit Board Table 13 1 CIRCUIT BOARD The KAT Z3DB circuit board is a rear transition module assembly It uses a 6 layer printed circuit board with the following dimensions RTM Circuit Board Dimensions Width Depth 12 687 in 322 25 mm 3 481 in 88 42 mm The following figure shows the component map for the KAT Z3DB circuit board 10007175 02 KAT4000 User s Manual 13 3 Rear Transition Module circuit Board Figure 13 2 RTM Component Top Rev 00 MMe 9 P33 24 Pin 8 P32 ATCA 80 Pin Im lon p31 8 8 80 Pin m s Qu B o o P30 g ATCA 80 Pin P3 RJ45 2h 77 Ki 51 Guide mis 85 E 88 E EISE Ri RIZ O el 13 4 KAT4000 User s Manual 10007175 02 Rear Transition Module race Plate FACE PLATE The rear face plate includes openings for six 9 pin micro D connectors and one RJ45 con nector for serial I O see Fig 13 1 There are also two reset switches a board reset and an IPMI reset CONNECTORS There are several connectors on the KAT Z3DB see Fig
30. page 9 21 0 00400 16394 Pigeon Point Systems Get Handle Switch Command The Get Handle Switch command reads the state of the Hot Swap handle of the IPMC Over riding of the handle switch state is allowed only if the IPMC operates in Manual Standalone mode Table 9 14 GetHandle Switch Command Byte 1 3 Request Data ResponseData 1 E KAT4000 User s Manual Data Field PPSIANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Completion Code PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Handle Switch Status 0x00 The handle switch is open 0x01 The handle switch is closed 0x02 The handle switch state is read from hardware 10007175 02 System Management vendor Commands Set Handle Switch Command The Set Handle Switch command sets the state of the Hot Swap handle switch in Manual Standalone mode Table 9 15 Set Handle Switch Command Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems 4 Handle Switch Status 0x00 The handle switch is open 0x01 The handle switch is closed 0x02 The handle switch state is read from hardware ResponseData 1 Completion Code 2 4 PPS IANA Private Enterprise ID MS Byte first 0 00400 16394 Pigeon Point Systems Get Payload Communication Time Out Command The Get Payload Commun
31. Serial command line interface CLI Web interface Both interfaces use the VSC7376 switch s internal 8051 microprocessor to accept com mands and configure the switch Configuration changes are stored in a serial EEPROM and will remain through system reset The web interface offers only a subset of the CLI configuration options Therefore an Ethernet switch config ured via the CLI may not reflect properly on the web interface Switching between interfaces while configuring a switch is not recommended To configure the switches and VLANs or set up the COM port via the serial Command Line Interface CLI or web interface see the KAT4000 Quick Start Guide for the No CPU Carrier Board 10008506 Default Switch Configuration The default switch configuration is a VLAN unaware L2 switch with automatic learn ing aging enabled on all ports e System The system name string is p711 core or p711_fatpipe Console The password string is empty and inactivity timeout is disabled The prompt is gt Port All used ports are enabled and flow control is disabled Max frame size is 1518 MACtable The table is empty auto learning and aging is enabled The aging timer is 300 seconds VLANs The KAT4000 Quick Start Guide for the No CPU Carrier Board 10008506 defines the default port based VLANs for the no CPU KAT4000 s Ethernet core switch and GbE fat pipe switch module See page 14 27 for the monitor vlan co
32. Set port mode Enable disable flow control Configure simple port based VLANs E KAT4000 User s Manual 10007175 02 Appendix A web Interface Note Note Configure aggregation groups Configure QoS Read and clear statistics counters Restore system defaults The web interface uses port IDs versus the port number i e the physical number of the port Port numbers port port ID 1 are used when discussing Ethernet switch ports For example VLAN port ID 1 is the same as Ethernet switch port 0 All operations are password protected The password must be entered at login The pass word is the same as that used in the command line interface IP mode is disabled in the factory default configuration To use the web interface first enable and configure the IP via the command line interface Set the IP address mask and gateway according to your environment Provided below is an example of how to enable the web interface via the command line interface CLI gt Setup 10 10 129 189 255 255 255 0 10 10 128 14 1 1 It is recommended that the port you plan to use to access the web interface be on its own dedicated VLAN This is because in systems where two or more KAT4000 ports are con nected to another Ethernet switch it may not be possible to access the web interface through that Ethernet switch depending on the switch and how it is configured It is possible to configure the switch so the web interface is
33. IVORO IVOR1 IVOR2 IVOR3 IVOR4 IVOR5 IVOR6 IVOR7 IVOR8 IVOR10 IVOR11 IVOR12 IVOR13 IVOR14 Real Time Clock is an input to the MPC8548 Optionally it can be used to clock the e500 core timer facilities and by the MPC8548 PIC global timer facilities MPC8548 EXCEPTION HANDLING Each type of CPU exception transfers control to a different address in the vector table The vector table normally occupies the first 8 kilobytes of RAM with a base address of 0000 000016 or Flash with a base address of E000 000046 An unassigned vector position may be used to point to an error routine or for code or data storage Table 3 5 lists the exceptions recognized by the MPC8548 and the conditions that cause them 8548 Exceptions Type reserved Critical Input Machine Check Data Storage Interrupt DSI Instruction Storage Interrupt ISI External Interrupt Alignment Program Check Floating Point Unavailable System Call Decrementer Interval Timer Watchdog Timer Data TLB Error Instruction TLB Error Vector OffsetHex Address 00000 00100 00200 00300 00400 00500 00600 00700 00800 00900 00A00 00B00 00C00 00D00 00 00 10007175 02 Notes Caused when MSR CE 1 Caused when MSR ME 1 Caused by one of the following exception conditions read access control write access control byte ordering cache locking or storage synchronization Caused by one of the following exception c
34. If you do not have Internet access please call Emerson for further assistance 800 327 1251 or 608 826 8006 US 44 131 475 7070 UK 10007175 02 KAT4000 User s Manual 2 17 Setup Troubleshooting E KAT4000 User s Manual Product Repair If you plan to return the board to Emerson Network Power for service visit http www artesyncp com support on the internet or send e mail to serviceinfo artesyncp com to obtain a Return Merchandise Authorization RMA number We will ask you to list which items you are returning and the board serial number plus your purchase order number and billing information if your KAT4000 hardware is out of war ranty Contact our Test Services Department for any warranty questions If you return the board be sure to enclose it in an antistatic bag such as the one in which it was originally shipped Send it prepaid to Emerson Network Power Embedded Computing Test Services Department 8310 Excelsior Drive Madison 53717 RMA ft Please put the RMA number on the outside of the package so we can handle your problem efficiently Our service department cannot accept material received without an RMA num ber 10007175 02 Central Processing Unit Table 3 1 This chapter is an overview of the processor logic optional on the KAT4000 It includes information on the CPU exception handling and the I O parallel port pin assignments The KAT4000 uses a Freescale MPC8548 PowerQUICC III micropro
35. Lower Non Recoverable 9c Threshold Lower Critical Threshold 00 Lower Non Critical Threshold 00 Positive Going Threshold Hyst 02 Value _ Negative Going Threshold Hyst 02 Value OEM 00 ID String Length Code ca Table B 32 12V Volt SDR Description KAT4000 Records Value Parameter Status Record ID 001e SDR Version 51 o Record Type 01 Full Sensor Record Record Length 34 KAT4000 User s Manual 10007175 02 Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Sensor Owner ID 00 Sensor Owner LUN 00 Sensor Number 00 Entity ID 0a Entity Instance 60 Sensor Initialization 7f Init Scanning lnit Sensor Type Init Hysteresis B Init Thresholds Init Events Sensor Scanning enabled Event Generation enabled Sensor Capabilities 69 Ignore Sensor no Auto Re Arm enabled Sensor Hysteresis hysteresis is settable readable Sensor Threshold Access threshold is settable readable Event Message Control global disable only Sensor Type 02 Voltage Event Reading Type Code 10 Threshold Assertion Event Mask 4801 Lower Non Recoverable Threshold comparison returned Upper Non Recoverable Going High supported Lower Non Critical Going Low supported Deassertion Event Mask 4801 Lower Non Recoverable Thr
36. Modifier Unit none Percentage no Sensor Units 2 Base Unit 00 Unspecified 10007175 02 KAT4000 User s Manual B 27 Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Sensor Units 3 Modifier Unit 00 Unspecified Linearization 00 M 00 M Tolerance 00 B 00 B Accuracy 00 Accuracy Accuracy Exp 00 R exp B Exp 00 Analog Characteristic Flags 00 Nominal Reading 00 Normal Maximum 00 Normal Minimum 00 Sensor Maximum Reading 00 Sensor Minimum Reading 00 Upper Non Recoverable 00 Threshold Upper Critical Threshold 00 Upper Non Critical Threshold 00 Lower Non Recoverable 00 Threshold Lower Critical Threshold 00 Lower Non Critical Threshold 00 Positive Going Threshold Hyst 00 x Value Negative Going 00 Threshold Hyst Value OEM 00 ID String Type Length Code cb Table B 17 Hot Swap SDR Description KAT4000 Records Value Parameter Status Record ID 000f SDR Version 51 Record Type 01 Full Sensor Record Record Length 36 Sensor Owner ID 00 Sensor Owner LUN 00 Sensor Number 00 Entity ID c1 AMC Module Entity Instance 67 B 28 KAT4000 User s Manual 10007175 02 Appendix B sensor Data Records
37. NT 7 935 lt 8 0331 9 lt 405 NT vzs8 PCle Lane Good 9 9105 NT vzs8 9 5 6994 1508 pugu 0ZG5 NT vzss BIB 4 9 67 NT vzss 8205 NT 259 e Qi KAT4000 User s Manual 10007175 02 Setup KAT4000 Circuit Board Figure 2 8 LEDs Bottom Cj BLUE LED CONN Hot Swap ion LED3 CONN g Pa User LED2 CONN User LED1A_CONN LED1R_CONN Red Amber Out of Service EJ KAT4000 User s Manual 10007175 02 Setup KAT4000 Circuit Board Front Panel Remote IPMI Software Processor RTM Reset The reset signals are routed to the PLD See Chapter 7 for the reset registers The following sources can reset the KAT4000 The front panel reset switch can reset the board The KAT4000 is capable of being reset remotely via the IPMI controller Software is capable of asserting reset to the individual modules see reset on page 14 25 The processor is also capable of resetting the board If a rear transition module is used that utilizes the Zone 3 reset signal the board can be reset from the RTM 10007175 02 KAT4000 User s Manual 2 13 Setup KAT4000 Circuit Board Figure 2 9 KAT4000 Reset Diagram 33V CPU TRST CPU SRESET PU HRESET 33V
38. bootv lt primary secondary gt update source size Check validity of images in Flash bootv lt primary secondary gt check bootvx The bootvx command boots VxWorks from an ELF image where address is the load address of the VxWorks ELF image To use this command the environment variables listed in Table 14 4 must be configured Definition ootvx address 1 dhcp The dhcp command invokes a Dynamic Host Configuration Protocol DHCP client to obtain IP and boot parameters by sending out a DHCP request and waiting for a response from a server 4000 User s Manual 10007175 02 Monitor Boot Commands Definition Table 14 5 Definition dhcp loadaddress bootfilename To use the dhcp command your DHCP server must be configured with the variables desig nated in Table 14 5 DHCP Ethernet Configuration Environment Variable Description Value ipaddr Local IP address for the board Configured e g 192 168 1 1 by DHCP serverip TFTP NFS server address This value must e g 192 168 1 2 be configured after the DHCP IP address is acquired netmask Net mask Obtained by DHCP gatewayip Gateway IP address Obtained by DHCP netdev Ethernet device Obtained by DHCP ethO ethaddr MAC address 00 80 9 autoload gt Boot image from TFTP server after DHCP no acquisition 2 Values for ethaddr netdev and autoload are set by the user 3 The value obtained by the DHCP server may not be
39. de 5 4 Central Processing Unit Components and Features 5 5 MPC8548 3 3 GbE Fat Pipe Switch Module PLD 5 6 Microprocessor Core 500 3 3 Product ID Version Register 5 6 11 3 3 Scratch Register 5 7 L2 Caches 3 3 2 5 7 3 4 Signal Detect Register 5 8 PCI Device and Vendor ID Assignment Switch Reset Register 5 8 3 4 Module Status Register 5 8 L2 Control Register 12 3 4 ORD eat vestes E 10 GbE 1 GbE Fat Pipe Switch Module 5 11 Hardware Implementation Dependent GbE 1 ET Fat Pipe Switch Module i anamer 3 7 HORUM TER FEN rla Components and Features 5 14 KAT4000 User s Manual Contents continued 10 GbE 1 GbE Fat Pipe Switch Module Clock Synchronizer Primary Source PLD 5 16 Registers 1 3 CPS1 CPS3 7 14 Product ID Version Register 5 16 Clock Synchronizer Secondary Source Scratch Register 5 17 Registers 1 3 CSS1 CSS3 7 15 2 5 17 Clock Control Registers CCR1 CCR14 Reserved Register 1 5 18 7 17 Switch Reset Register 5 18 Clock Synchronizer Interrupt Registers Module Status Register 5 19 511 5 7 18 Switch GPIO Register 5 19 JT
40. 256 KB 5 2 FC12 0000 Reserved FC10 0000 R W Ethernet Core Switch Registers 128 KB 4 2 FC00 8000 Reserved FC00 0000 R W NAND Flash 32 KB 6 2 E200 0000 Reserved E000 0000 R W NOR Flash 32 MB 6 1 A000 0000 R W PCI Express Switch sRIO Fat Pipe Switch Module if installed 4 7 or 5 22 1 GB 8000 0000 R W PCI Express Switch if installed 512 MB 4 7 4000 0000 Reserved 0000 0000 R W SDRAM DDR2 512 MB 1 GB 6 2 1 Depends Flash memory size 2 Boththe PCI Express Switch and sRIO Fat Pipe Switch Module are optional If both devices are discovered onboard then the PCle switch will be allocated 512 MB and the sRIO fat pipe switch module will be allocated 1 GB of addressable space If neither device is found onboard the entire 1 5 GB area is reserved 4000 User s Manual 10007175 02 Overview AMC Mapping AMC MAPPING The figure below shows how the KAT4000 maps to the ports defined by the 0 specifi cation Figure 1 3 AMC Port Mapping Regions Port Port Mapping SYNCLK Clocks SYNCLK REFCLK SYNCLK GbE Common Options PCle or GbE Region See below for port routing See below for configuration Fat Pipes Region options 403294410 21529 See below for port routing Extended Options Region Zone 3 40 99UU0 1 0 Definition KAT4000 Implementation AMC to AMC Implementation of Ports 2 and 3 GbE Fat Pipe Switch Module
41. GbE switch features 4 2 glossary of acronyms 15 1 grounding 2 1 H hardware implementation dependent registers HIDx 3 6 to 3 8 header 4 2 5 HobSWapD accro e etat TES 2 10 reference manual 1 13 I2C bus 1 2 installation of the board 2 15 IPMB reference manual 1 14 IPMI completion codes 9 4 E keying information 9 45 entity IDs and instances 9 39 FRU information 9 44 network function codes 9 3 reference manual 1 14 request response messages 9 5 KAT4000 User s Manual continued Serial Interface Protocol Lite SIPL memory commands 14 12 14 19 9 6 Motorola S record 14 32 iprobe eser yet eme 14 18 standard commands 9 9 other commands 14 22 eere tnmen 14 23 vendor commands 9 12 power up reset sequence flowchart 14 12 sensor data 45 1 14 5 14 12 14 6 14 24 start up display of KAT4000 with 10 e E SE 14 13 GbE 1 GbE fat pipe module 14 3 14 24 mo IDEE 2 5 start up display of KAT4000 with GbE 14 14 fat
42. Sensor Units 3 Modifier Unit 00 Unspecified Linearization 00 Linear M 62 M Tolerance 00 B 00 B Accuracy 00 00 c0 Analog Characteristic Flags 07 Nominal Reading 71 Normal Maximum 7c Normal Minimum 66 Sensor Maximum ff Reading Sensor Minimum Reading 00 n Upper Non Recoverable 87 x Threshold Upper Critical Threshold 00 Upper Non Critical Threshold 00 Lower Non Recoverable 5a Threshold Lower Critical Threshold 00 Lower Non Critical Threshold 00 B 18 KAT4000 User s Manual 10007175 02 Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Positive Going Threshold Hyst 03 Value Negative Going Threshold Hyst 03 Value 00 ID String Type Length Code c8 Table B 12 Inflow Temp SDR Description KAT4000 Records Value Parameter Status Record ID 000a SDR Version 51 01 Full Sensor Record Record Length 36 Sensor Owner ID 00 Sensor Owner LUN 00 Sensor Number 00 Entity ID a0 Entity Instance 60 Sensor Initialization 7f Init Scanning Init Sensor Type Init Hysteresis Init Thresholds Init Events Sensor Scanning enabled Ev
43. This region supports data path connections such as GbE It can carry large amounts of data without significantly degrading the speed of transmission This refers to the link width of the port the number of lanes that can be used to intercon nect between two link partners The following diagram shows the implementation of the GbE fat pipe switch module on the KAT4000 Signal Routing of the GbE Fat Pipe Switch Module on the KAT4000 AMC x4 Single Wide Half Full Extended Height AMC z AMC 0 Common Fat Pipes Extended 7376 Ethernet Core Switch Layer 2 Fat Pipe Switch Module 41 13 GbE 4 GbE Base High Speed High Speed Clock RTM I O Fabric A Fabric B Optional 123 120 Zone3 10007175 02 MPC8548 Processor Local bus Fat Pipe Switch Module GbE rat Pipe Switch Module The following block diagram provides a functional overview for the GbE fat pipe switch module Figure 5 3 GbE Fat Pipe Switch Module Block Diagram The Switch SRAM and Flash are only available with the no CPU KAT4000 board 18 GbE VSC7376 po 26 port GbE Switch SPI Management Intere 8 GbE ports 3 2 8 5 ais 2 S 5 3 a o 10007175 02 KAT4000 User s Manual Fat Pipe Switch Module GbE rat Pipe Switch Module GbE Fat Pipe Switch Module Circuit Board The following figures show the component maps for the GbE fat pipe switch module circuit board Figu
44. User s Manual from Emerson Network Power Embedded Computing KAT4000 Carrier for ATCA April 2007 EMERSON Network Power The information in this manual has been checked and is believed to be accurate and reli able HOWEVER NO RESPONSIBILITY IS ASSUMED BY ARTESYN COMMUNICATION PROD UCTS FOR ITS USE OR FOR ANY INACCURACIES Specifications are subject to change without notice ARTESYN COMMUNICATION PRODUCTS DOES NOT ASSUME ANY LIABILITY ARISING OUT OF USE OR OTHER APPLICATION OF ANY PRODUCT CIRCUIT OR PROGRAM DESCRIBED HEREIN This document does not convey any license under Artesyn Communi cation Products patents or the rights of others Artesyn and the Artesyn logo are registered trademarks of Artesyn Technologies and are used by Artesyn Communication Products under license from Artesyn Technologies All other trademarks are property of their respective owners Revision Level Principal Changes Date 10007175 00 Original release January 2007 10007175 01 Added Appendix A February 2007 10007175 02 Added PCle functionality Released 10 GbE 1 GbE April 2007 fat pipe switch Copyright 2007 Artesyn Communication Products All rights reserved Emerson Consider It Solved is a trademark and Business Critical Continuity Emerson Network Power and the Emerson Network Power logo are trademarks and service marks of Emerson Electric Co O 2007 Emerson Electric Co Regulatory Agency Warnings amp Notices Cau
45. 00 RexpBExp 00 _ Analog Characteristic Flags lo _ Nominal Reading 20 37 E iNommaliMinimium To T ara Sensor Maximum Reading 7 Sensor Minimum Reading 80 Upper Non Recoverable 55 Threshold Upper Critical Threshold 4 _ Upper Non Critical Threshold 41 LowerNon Recoverable Threshold _ Lower Critical Threshold 6 o Lower Non Critical Threshold fb 10007175 02 KAT4000 User s Manual B 23 Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Positive Going Threshold Hyst 02 Value Negative Going Threshold Hyst 02 Value OEM 00 ID String Type Length Code cc Table B 14 Version Change SDR Description KAT4000 Records Value Parameter Status Record ID 000c SDR Version 51 01 Full Sensor Record Record Length 39 Sensor Owner ID 00 Sensor Owner LUN 00 Sensor Number 00 Entity ID a0 Entity Instance 60 Sensor Initialization 67 Init Scanning Init Sensor Type lnitEvents Sensor Scanning enabled Event Generation enabled Sensor Capabilities 41 Ignore Sensor Auto Re Arm enabled gt Sensor Hysteresis hysteresis Sensor Threshold Access no thres
46. 11 1 board optional devices 1 3 2 15 serial 2 15 boot from redundant boot bank 6 2 memory configuration 6 1 boot commands monitor 14 9 C caution statements board installlremove 13 7 boards without front panel 2 4 removing socketed PLCC device 6 2 writes to monitor area 14 6 chip select generator CPU 3 12 circuit board dimensions 2 1 1 10 component map bottom x eere 2 3 2 2 connectors AMC pin assignments 8 4 backplane zones 1 3 12 1 console 13 5 J20 through 24 12 2 J30 through J33 12 4 2 4 P1 P2 P4 P7 pinouts 13 5 12 1 contents table ii iii CPLD 7 19 reference manual 1 12 7 1 CPU block diagram 3 2 cache memory 3 3 chip select generator 3 12 exception handling 3 13 functions on the KAT4000 3 3 interrupts and exceptions 3 8 1 1 peripheral request 3 10 reference manual 1 13 reset and clocking signals 3 12 custom AMC requirement
47. 40 W No AMC modules When the KAT4000 is powered off so is the RTM The exact power requirements for the KAT4000 circuit board depend upon the specific configuration of the board including the CPU frequency and amount of memory installed on the board Please contact Emerson Technical Support at 1 800 327 1251 if you have specific questions regarding the board s power requirements Environmental Considerations As with any printed circuit board be sure that air flow to the board is adequate Chassis constraints and other factors greatly affect the air flow rate The environmental require ments are shown in Table 2 6 and Table 2 7 Environmental Requirements Environment Range Relative Humidity Operating 0 to 55 Centigrade ambient Not to exceed 85 Temperature at board non condensing Storage Temperature 40 to 70 Centigrade Not to exceed 95 non condensing Altitude 0 to 4 000 meters above sea level Air Flow Requirements Configuration Power Temperature Air Flow 1 3 GHz processor with 4 182 W 55 21CFM 1 GB DDR2 SDRAM modules 35 5 W per AMC 1 The physical placement of AMC modules greatly affects air flow requirements Air flow is required at the processor to maintain junction temperature less than 105 C at specified ambient temperature 10007175 02 Setup Troubleshooting Cooling requirements are a function of operating software AMC power consumption and AMC airflow resistance
48. Bits 7 5 Reserved Bit 4 IPMB Dump Enable If setto 1 the IPMC provides a trace of IPMB messages that are arriving to going from the IPMC via IPMB O Bit 3 Payload Logging Enable If setto 1 the IPMC provides a trace of SIPL activity on the Payload Interface onto the Serial Debug interface Bit 2 Alert Logging Enable If setto 1 the IPMC outputs important alert messages onto the Serial Debug interface Bit 1 Low level Error Logging Enable If setto 1 the IPMC outputs low level error diagnostic messages onto the Serial Debug interface Bit 0 Error Logging Enable If setto 1 the IPMC outputs error diagnostic messages onto the Serial Debug interface E KAT4000 User s Manual 10007175 02 System Management vendor Commands Set Debug Level Command The Set Debug Level command sets the current debug level of the IPMC firmware Table 9 11 Set Debug Level Command Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID MS Byte first _ 0x00400A 16394 Pigeon Point Systems 4 Bits 7 5 Reserved Bit 4 IPMB Dump Enable If setto 1 the IPMC provides a trace of IPMB messages that are arriving to going from the IPMC via IPMB O Bit 3 Payload Logging Enable If setto 1 the IPMC provides a trace of SIPL activity on the Payload Interface onto the Serial Debug interface Bit 2 Alert Logging Enable If setto 1 the IPMC outputs important alert messages onto the Serial Debug interface Bit
49. Bn PS1 Power connectors to configuration capacitors for GbE or PCI Express Connects to the IPMC PLD via a BMR H8S microcontroller Bn_SATA1_RXD TXD Optional module connectivity test loop to Sata 1 B4 Sata 2 Sata 1 and B1 Sata 2 respectively Bn_SATA2_RXD TXD Optional module connectivity test loop to Sata 1 Sata 2 B2 Sata 2 B2 Sata 1 respec Bn_TRINGn RRINGn KAT4000 User s Manual tively Input receive and output transmit signals to Zone 3 10007175 02 AMC Sites AMC Signals Bn_TTIPn RTIPn CLK1 CLK2 EXPn_B_RX4 TX4 EXPn_B_RX5 TX5 EXPn_B_RX6 TX6 _ _ 7 7 GIGn RX TX PCIE REFCLKn SCL Bn_SDA TCK TDI TDO TMS TRST Input receive and output transmit signals to Zone 3 CLOCK1 Connects to the AMC synchronization clock transceivers CLOCK2 Connects to the AMC synchronization clock transceivers Optional test loop to B3 port 8 B1 B4 B2 B1 B3 and B2 B4 respectively PCI Express interface port output transmit or input receive signals differential pairs Optional test loop to B3 port 9 B1 B4 B2 B1 B3 and B2 B4 respectively Optional test loop to B3 port 10 B1 B4 B2 B1 B3 and B2 B4 respectively Optional test loop to B3 port 11 B1 B4 B2 B1 B3 and B2 B4 respectively Gigabit Ethernet differential pairs to Ethernet core switch ports 0 12 18 and 11 r
50. DEBUG HRESET HRESET REQ FLASH RST PWRGD OR Front Panel CORESW RST RESET BC RST E RST NAND_WARM_RST OSC33_IPMC 3_3V_MP L_PAYLD_EN FP_PWR_GOOD 3 3 PWRGD 25 2 5 PWRGD 1 8V 1_8V_PWRGD 12V 1_2V_PWRGD TOV 1_0V_PWRGD 1 1V CPU CORE _ PWRGD EDEBUG RST FP_RST CLK SYNCI RST CLK SYNC2 RST CLK SYNC3 RST 3 3V MP RST PB oh PRIV I2C SCL PCIE 857 PRIV I2C SDA IPMC_RES Hotswap 3 Switch DDR2 RST E HANDLE PAYLD RST E KAT4000 User s Manual 10007175 02 Setup KAT4000 Setup Note KAT4000 SETUP For step by step setup instructions see the KAT4000 Quick Start Guide 10008585 or the KAT4000 Quick Start Guide for the No CPU Carrier Board 10008506 xx You need the following items to set up and check the operation of the Emerson KAT4000 O KAT4000 carrier chassis and power supply Compatible AMC modules Console serial cable s Optional rear transition module and cable CRT terminal Save the antistatic bag and box for future shipping or storage This guide assumes that the host is running Red Hat Linux 9 0 If you use a different Linux distribution you ll have to adapt these instructions to your implementation Identification Numbers Before you i
51. Definition 000800205 ffffffff x eisai da ege 000800305 5 00080040 TELETELE ffffffff fffffftf 00080050 iude x 000800605 fRI EBSE ek Ra 00080070 FLAPPER eee aces FLASH COMMANDS The Flash commands affect the StrataFlash device on the KAT4000 circuit board There is one Flash bank on the KAT4000 board The following Flash commands access the individual Flash bank as Flash bank 7 To access the individual sectors within each Flash bank the sec tor numbers start at 0 and end at one less than the total number of sectors in the bank For a Flash bank with 128 sectors the following Flash commands access the individual sectors as Othrough 127 cp The cp command can be used to copy data into the Flash device For the cp command syn tax refer to Memory Commands on page 14 12 erase The erase command erases the specified area of Flash memory Erase all of the sectors in the address range from start to end erase start end Erase all of the sectors SF first sector to SL last sector in Flash bank N erase N SF SL Erase all of the sectors in Flash bank N erase bank N Erase all of the secto
52. JTAG HUDS tnt 2 9 Figure 2 7 MEDS TOPs 2 11 2 8 lEDSBOLLOITIT 2 12 Figure 2 9 KAT4000 Reset Diagram iu vert eret hee x RE 2 14 Figure 3 1 MPC8548 Block Diagralmi 42 nno iie Re EROR ce 3 2 Figure 3 2 Processor JTAG COP sss 3 14 Figure 3 3 Processor JTAG COP 2 3 14 Figure 4 1 Board Area NetWork wince uec eire rh aee x e eR ge par Pra eec 4 1 Figure 4 2 VSC7376 GbE Switch Block 4 3 Figure 4 3 8524 Block ie ere reb RER I ne EE 4 8 Figure 4 4 PEX 8524 SPI EEPROM 4 9 Figure 5 1 AMC Port Map Fat Pipes 5 2 Figure 5 2 Signal Routing of the GbE Fat Pipe Switch Module on the 4000 5 2 Figure 5 3 GbE Fat Pipe Switch Module Block 5 3 Figure 5 4 GbE Fat Pipe Switch Module Component Top Rev 00 5 4 Figure 5 5 GbE Fat Pipe Switch Module Component Map Bottom Rev 00 5 4 Figure 5 6 GbE Fat Pipe Switch IRE RR ERR 5 5 Figure 5 7 GbE Fat Pipe
53. OS Watchdog role This indicates that the timer was being used for an OEM specific function Using the Timer Use Field and Expiration Flags The software that sets the Timer Use field is responsible for managing the associated Timer Use Expiration flag For example if System Management Software SMS sets the timer use to SMS OS Watchdog then that same SMS is responsible for acting on and clearing the associated Timer Use Expiration flag In addition software should only interpret or manage the expiration flags for watchdog timer uses that it set For example the monitor should not report watchdog timer expira tions or clear the expiration flags for non monitor uses of the timer This is to allow the soft ware that did set the Timer Use to see that a matching expiration occurred Watchdog Timer Event Logging By default the IPMC will automatically log the corresponding sensor specific watchdog sensor event when a timer expiration occurs A don t log bit is provided to temporarily disable the automatic logging The don t log bit is automatically cleared logging re enabled whenever a timer expiration occurs 10007175 02 System Management IPMC Watchdog Timer Commands Table 9 31 Byte 1 Byte 2 Byte 3 Byte 4 Bytes 5 and 6 Monitor Support for Watchdog Timer If a system Warm Reset occurs the watchdog timer may still be running while the moni tor executes POST Therefore the monitor shoul
54. RCR2 at Oxfc40 0028 7 6 5 4 3 2 1 0 FPR DER BCR NFR reserved 0 0 0 0 FPR FatPipe Module Reset 1 Reset 0 Noreset default 7 10 KAT4000 User s Manual 10007175 02 CPLD Boot and Reset Registers DER Debug Ethernet Reset 1 Reset 0 Noreset default BCR Base Channel Ethernet Reset 1 Reset 0 Noreset default NFR NAND Flash Reset 1 Reset 0 Noreset default R Reserved Boot Device Redirection Register BDRR The read only Boot Device Redirection register indicates which of the three devices the CPU is using as the boot device The BDRR also indicates which device was set as the initial boot device see Fig 7 1 The Boot Redirected Bit BRB 7 is set 1 when the current boot device does not match the initial default boot device This indicates that the image in the default device was defective the watchdog timer expired and the next device was tried The boot redirect circuitry is enabled or disabled by Register Map 7 4 Default register values are dependent on boot settings 10007175 02 KAT4000 User s Manual 7 11 CPLD Boot and Reset Registers 7 12 Figure 7 1 Boot Device Redirection Socketed ROM Flash 0 Register 7 15 Boot Device Redirection Register BDRR at Oxfc40 0030 7 6 5 4 3 2 Jp ds Pa 22 5 6 24681 25578 152 5 6 Boot from socket default Boot device redirection is disabled
55. Sensor Hysteresis hysteresis is settable readable threshold is settable readable Sensor Threshold Access Event Message Control global disable only Sensor Type 03 Current Event Reading Type Code 01 Threshold Assertion Event Mask 0800 Upper Non Recoverable Going High supported Deassertion Event Mask 4800 Lower Non Recoverable Threshold comparison returned Upper Non Recoverable Going High supported Discrete Reading Mask 3838 Upper Non Recoverable Threshold settable Upper Critical Threshold settable Upper Non Critical Threshold settable Upper Non Recoverable Threshold readable Upper Critical Threshold readable Upper Non Critical Threshold readable Sensor Units 1 00 Analog Data Format unsigned RateUnit none Modifier Unit none Percentage no Sensor Units 2 Base Unit 05 Amps Sensor Units 3 Modifier Unit 00 Unspecified Linearization 00 M 8a M Tolerance 40 Bo 0 200 00 R exp B Exp c0 _ Analog Characteristic Flags _ 07 NominalReading 66 Normal Maximum bf Normal Minimum 00 Sensor Maximum Reading B 32 KAT4000 User s Manual 10007175 02 Appendix B sensor Data Records KAT4000 Reco
56. b 80000 is not Some commands may be abbreviated by typing only the first few characters that uniquely identify the command For example you can type h instead of help However commands cannot be abbreviated when accessing online help You must type help and the full command name 10007175 02 Monitor Boot Commands Definition Definition Definition Definition Command Help Access all available monitor commands by pressing the key or entering help Access the monitor online help for individual commands by typing help command The full com mand name must be entered to access the online help Typographic Conventions In the following command descriptions text in Courier shows the command format Square brackets enclose optional arguments and angled brackets lt gt enclose required arguments Italic type indicates a variable or field that requires input BOOT COMMANDS The boot commands provide facilities for booting application programs and operating sys tems from various devices bootd Execute the command stored in the bootcmd environment variable bootd bootelf The bootelf command boots from an ELF image in memory where address is the load address of the ELF image bootelf address bootm The bootm command boots an application image stored in memory passing any entered arguments to the called application When booting a Linux kernel arg can be the address of an initrd image
57. 0 Lock overflow not detected clear 1210 in software 1 Lockoverflow condition detected L2 Snoop Lock Clear sticky bit sets when a snoop invalidated a locked data cache line reserved in full memory mapped SRAM mode 0 Snoop did not invalidate clear L2LO in software 1 Snoop invalidated a locked line 10007175 02 KAT4000 User s Manual Central Processing Unit Microprocessor Core 500 L2LFR L2 cache Lock bits Flash Reset L2 cache must be enabled for reset to occur reserved in full memory mapped SRAM mode 0 L2cachelock bits are not cleared or the clear operation completed 1 Resetoperation clears each L2 cache line s lock bits L2LFRID L2 cache Lock bits Flash Reset select Instruction or Data indicates whether data instruc tion or both bits are reset 00 Notused 01 Reset data locks if L2LFR 1 10 Reset instruction locks if L2LFR 1 11 Reset both data and instruction locks if L2LFR 1 L2STASHDIS 12 Stash allocate Disable disables allocation of lines for stashing 00 12 allocates lines 01 L2does not allocate lines 125 5 12 Stash configuration reserves regions of cache for stash only operation 00 Nostash only region 01 One half of the array is stash only 10 One quarter of the array is stash only 11 One eighth of the array is stash only Hardware Implementation Dependent 0 Register The Hardware Implementation Dependent 0 HIDO register contains bits for CPU specific features Most of th
58. 00 Tes Mo 00 E M Tolerance 00 Es Bo 00 B Accuracy 00 00 R exp B Exp mM 00 Analog Characteristic Flags _ 00 Nominal Reading o0 nz Normal Maximum 00 Normal Minimum 00 Sensor Maximum 00 Reading Sensor Minimum Reading 00 m _ Upper Non Recoverable 700 E Threshold _ Upper Critical Threshold 00 _ Upper Non Critical Threshold 00 Lower Non Recoverable 00 Threshold 10007175 02 KAT4000 User s Manual Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Lower Critical Threshold 00 Lower Non Critical Threshold 00 Positive Going Threshold Hyst 00 Value Negative Going Threshold Hyst 00 Value OEM 00 ID String Type Length Code cc 60 KAT4000 User s Manual 10007175 02 Index A air flow 2 16 AMC 2 4 8 2 custom modules 8 1 1 2 assignments 8 4 reference 1 12 reference manual 1 12 back panel 5 2 4 binary download format 14 32 block diagram CPUS Ls prre NOR 3 2 general 1 5 IPMC connections 9 2 real time clock
59. 0001 _ Table B 3 on page B 2 IPMB Physical 0002 Table B 4 on page B 4 BMC Watchdog 0003 Table B 5 on page B 5 3 3 Volt 0004 _ Table B 6 on page B 7 2 5 Volt 0005 Table B 7 on page B 9 1 8 Volt 0006 Table B 8 on page B 11 1 2 Volt 0007 Table B 9 on page B 13 1 0 Volt 0008 Table B 10 on page B 15 CPU Volt 0009 Table B 11 on page B 17 Inflow Temp 000a Table B 12 on page B 19 Outflow Temp 000b Table B 13 on page B 21 Version Change 000c Table B 14 on page B 24 B1Hot Swap 000d Table B 15 on page B 25 B2 Hot Swap 000e Table B 16 on page B 27 B3 Hot Swap 000 Table B 17 on page 28 B4 Hot Swap 0010 Table B 18 on page B 30 B1 12V Current 0011 Table B 19 on page B 31 B1 12V Volt 0012 Table B 20 on page B 33 B2 12V Current 0013 Table B 21 on page B 35 B2 12V Volt 0014 Table B 22 on page B 36 12V Current 0015 Table B 23 on page B 38 B3 12V Volt 0016 Table B 24 on page B 40 B4 12V Current 0017 Table B 25 on page B 41 B4 12V Volt 0018 Table B 26 on page B 43 48V Volt 0019 Table B 27 on page B 45 48V Current 001a Table B 28 on page B 47 48V Source A Volt 001b Table B 29 on page B 48 48V Source B Volt 001c Table B 30 on page B 50 3 3V Management _ 001d 31 52 10007175 02 KAT4000 User s Manual m Appendix B sensor Data Records Record ID Table Information Sensor Name hex continued 12V Volt 001e Table B 32 on page B 54 12V Current 001f Table B 33
60. 01101 AMC3 CLK2 01110 AMC3 CLK3 01111 AMC4 CLK1 10000 AMC4 CLK2 10001 AMC4 CLK3 10010 reserved 11111 reserved 7 16 KAT4000 User s Manual 10007175 02 CPLD Clock Synchronizer Registers Register 7 19 OE CSS4 0 Clock Control Registers 1 14 The Clock Control registers control the source clock to the various clock destinations Default is OxOE for all 14 registers Default register values are shown in the bottom row of the register table Clock Control Registers 1 14 CCR1 CCR14 at Oxfc40 0070 Oxfc40 0074 Oxfc40 0078 Oxfc40 007c Oxfc40 0080 Oxfc40 0084 Oxfc40 0088 Oxfc40 008c Oxfc40 0090 Oxfc40 0094 Oxfc40 0098 Oxfc40 009c Oxfc40 00a0 Oxfc40 00a4 respectively 7 6 5 4 3 2 1 0 OE reserved 554 CSS3 CSS2 551 CSSO 0 0 1 1 1 0 Clock Enable O Tristates clock driven to site 1 Drives selected clock source to site Reserved Clock Source Select Defines source of clock to be driven to site If self is selected as source logic 0 will be driven Clock Control Bit Input Source Register 00000 AMCI CLKT 71 00001 CLK2 2 00010 3 00011 AMC2 CLK1 4 00100 AMC2CLK2 5 00101 AMC2 CLK3 6 00110 CLK1 3 00111 AMC3 CLK2 8 01000 AMC3 9 01001 AMCA CLK1 10 01010 AMCA CLK2 11 01011 AMCA CLK3 12 01100 aTCACLK1A 01101 aTCA CLK1 B 01110 aTCA CLK2 A
61. 1 Low level Error If set to 1 the outputs low level error diagnostic messages onto the Serial Debug interface Bit 0 Error Logging Enable If set to 1 the IPMC outputs error diagnostic messages onto the Serial Debug interface Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Get Hardware Address Command The Get Hardware Address command reads the hardware address of the IPMC Table 9 12 Get Hardware Address Command Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems 5 Hardware Address 10007175 02 KAT4000 User s Manual 9 17 System Management vendor Commands Set Hardware Address Command The Set Hardware Address command allows overriding of the hardware address read from hardware when the IPMC operates in Manual Standalone mode Table 9 13 Set Hardware Address Command Type Byte Request Data 1 3 4 Response Data 1 Completion Code DataField PPSIANA Private Enterprise ID MS Byte first 0 00400 16394 Pigeon Point Systems Hardware Address If set to 00 the ability to override the hardware address is disabled NOTE A hardware address change only takes effect after an IPMC reset See Reset IPMC Command
62. 1 2 before using the JTAG COP interface P1 to enable CPU A JTAG COP access Attempting to use the TAG COP interface without this shunt in place may cause damage to the board Refer to Table 7 3 for JP1 pin details The 10 JTAG header is provided for programming In System Programmable ISP PLDs see Fig 7 2 The header pin assignments are defined in Table 7 2 10007175 02 KAT4000 User s Manual E Setup KAT4000 Circuit Board JP1 J35 Table 2 4 2 and 3 oos HS Caution A E KAT4000 User s Manual The 10 pin JP1 configuration header is provided for PLD programming Installing a shunt on JP1 pins 1 2 enables the JP3 PLD programming header The header pin assignments are defined in Table 7 3 J35 is the 14 pin JTAG emulation header See Table 2 4 for signal descriptions 35 Signal Descriptions Jumper Pin Signal Description Pin Signal Description 1 IPMC_TCK 2 GND 3 IPMC_TRST 4 GND 5 IPMC 6 GND 35 7 EMUL RESI 8 3_3 volts 9 IPMC_TMS 10 GND 11 IPMC_TDI 12 GND 13 IPMC_RES 14 GND LEDs See Fig 2 7 for the on board Light Emitting Diodes LEDs The KAT4000 has four front panel LEDs See Fig 2 8 for their location The debug LED codes are defined in Table 14 1 The front panel LEDs include The yellow CR2000 and green CR2002 LEDs are user defined The Out Of Service CR2003 programmable LED controlled by the IPMI controller is either red North
63. 1 GBE FAT PIPE SWITCH MODULE Fig 5 8 shows how the 10 GbE 1 GbE fat pipe switch module maps to ports defined by the AMC O specification see Fig 1 3 forthe full port mapping diagram AMC Port Map Fat Pipes Region 10 GbE 1 GbE Port Mapping GbE x1 GbE x1 GbE x1 GbE x1 p AMC 0 Definition 10 GbE 1 GbE Fat Pipe Switch Module Implementation 215 9 14 5 3 Fat Pipes Region 27 This region supports data path connections such as GbE It can carry large amounts of data without significantly degrading the speed of transmission This refers to the link width of the port the number of lanes that can be used to intercon nect between two link partners The following diagram shows the implementation of the 10 GbE 1 GbE fat pipe switch module on the KAT4000 Figure 5 9 Signal Routing of the 10 GbE 1 GbE Fat Pipe Switch Module on the KAT4000 If the GbE core switch is present GbE routes from the fat pipe to the GbE core switch If the GbE core switch is not present GbE routes from the fat pipe to the CPU AMC x4 Single Wide Half Full Extended Height AMC z VSC7376 0 Common Fat Pipes Extended Ethernet Core Switch Layer 2 Optional Fat Pipe Switch Module MPC8548 0 GbE 1 GbE Processor Local bus PCle x1 Base High Speed High Speed Clock RTM I O Fabric A Fabric B Optional 123 120 Zone 3 10007175 02 KAT4000 U
64. 12 3 for pin assignments The 80 pin Zone 3 ZD connectors provide an interconnect to an optional RTM Connec tions include AMC ports 12 20 serial ports a debug Ethernet port and various other inter faces See Table 12 4 Table 12 5 and Table 12 6 for pin assignments The 24 pin Zone 3 connector provides the 3 3 volt 12 volt and transmit receive signals to the AMCs See Table 12 7 for the pin assignments This hot swap switch header is a connector only a switch assembly P N 10005468 xx connects to this socket Header JP4 JP4 is the 16 pin serial port header for the IPMC debug console fat pipe debug console and host debug console See Table 2 2 for signal descriptions See Fig 2 4 for the header s loca tion JP4 Signal Descriptions Jumper Pin Signal Description Pin Signal Description 1 IPMC_RS232_TX 2 GND 3 IPMC_RS232_RX 4 GND 5 no connect 6 GND Jp 7 FP CONN RX 8 GND 9 FP TX 10 GND 11 no connect 12 GND 13 HOST RX 14 GND 15 HOST TX 16 GND Jumpers The following KAT4000 jumpers select the boot device SROM initialization logic probe and whether the IPMC will communicate with the shelf manager system See Table 2 3 for jumper descriptions Fig 2 4 and Fig 2 5 show jumper switch and fuse locations 10007175 02 KAT4000 User s Manual Setup KAT4000 Circuit Board Table 2 3 Jumpers JP2 and 7 Jumper JP2 Register Shunt Description Map 1 2 IPMC Mo
65. 121 12 Flash Invalidate KAT4000 User s Manual 0 L2status and LRU bits are not being cleared 1 Clears all L2 status bits and LRU 10007175 02 Central Processing Unit Microprocessor Core 500 12517 1200 1210 L2INTDIS L2SRAM L2LO L2SLC L2 SRAM Size indicates the total available L2 SRAM size read only 00 Reserved 01 256 kilobyte 10 512 kilobyte 11 1024 kilobyte L2 Data Only mode reserved in full memory mapped SRAM mode 0 12 cache allocates entries for instruction fetches that miss in the L2 1 12 cache allocates entries for processor data loads that miss in the L2 L2 Instruction Only causes L2 cache to allocate lines for instruction cache transactions only reserved in full memory mapped SRAM mode 0 L2cache entries allocated for data loads that miss in the L2 and for processor L1 castouts 1 L2cache allocates entries for instruction fetch misses L2 read Intervention Disable reserved for full memory mapped SRAM mode 0 Cache intervention enabled 1 Cache intervention disabled L2 cache memory mapped SRAM block assignment 12517 L2BLKSIZ 1 block 000 Block 0 cache 001 Block 0 SRAMO 010 111 Reserved 12517 L2BLKSIZx2 2 blocks Block 0 Block 1 000 Notused Cache 001 SRAMO Not used 010 SRAMO Cache 011 SRAMO SRAM1 100 111 Reserved L2 cache Lock Overflow sticky bit sets when an overlook condition is detected in L2 cache reserved in full memory mapped SRAM mode
66. 12V sensor 03 2 12 Volts sensor 02 7 PICMG AMC Module Hot Swaps sensor F0 12V sensor Type 03 12V Volts sensor Type 02 C1 8 PICMG AMC Module 4 Hot sensor Type F0 4 a 12V sensor Type 03 4 a 12V Volts sensor 02 SENSORS AND SENSOR DATA RECORDS The KAT4000 implements a number of sensors as described in Table 9 39 Appendix B details the KAT4000 Sensor Data Record SDR parameter values All values are hexadeci mal IPMI Sensors Sensor Type PICMG FRU Hot Swap FO PICMG FRU Hot Swap FO Event Reading Type Sensor specific Discrete 6F Sensor specific Discrete 6F 10007175 02 Entity ID PICMG Front Board A0 PICMG AMC _ Module C1 Entity Instance Device relative 60 Device relative 61 Event Gen Yes Yes System Management sensors and Sensor Data Records Sensor Name Entity Event continued Sensor Type Event Reading Type Entity ID Instance Gen B2 Hot Swap PICMG FRU Hot Swap FO Sensor specific PICMG AMC Device Yes Discrete 6F Module C1 relative 62 B3 Hot Swap PICMG FRU Hot Swap FO Sensor specific PICMG AMC Device Yes Discrete 6F Module C1 relative 63 B4 Hot Swap PICMG FRU Hot Swap FO Sensor specific PICMG AMC Device Yes Discrete 6F Module C1 relative 64 IPMB Physical PICMG IPMB Physical Sensor s
67. 2 2 Synch clock group 1 CLK1A and CLK1B pairs 3 Synch clock group 2 CLK2A and CLK2B pairs Synch clock group 3 CLK3A and pairs ResponseData 1 Completion Code 2 4 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems 5 Status 0 Ack Shelf Manager acknowledges that board has control 1 Error same as Ack but Shelf Manager believes board should not have been given control of the resource optional 2 Deny Shelf Manager denies control of resource by the board Bused Resource Status Command If the IPMC receives a Bused Resource Control command from 0 it asserts an appro priate event and notifies the payload which uses the Bused Resource Status command over the SIPL When the IPMC receives a Bused Resource Status command the respective bit in the IPMC status is cleared The payload must issue a Bused Resource Status command before the payload communi cation time out time If the payload does not issue such a command before the payload communication time out time the IPMC sends the 0xC3 completion code Time Out in the appropriate Bused Resource Control command reply 10007175 02 System Management vendor Commands Table 9 22 Bused Resource Status Command Type Byte Request Data 1 3 4 5 6 Response Data 1 Data Field PPS IANA Private Enterprise ID MS Byte first 0 00400 16394 Pigeon Point Systems Command Types for Shelf Manager to Board 0 Query i
68. 2 Example Monitor Start up Display for KAT4000 with 10 GbE 1 GbE Fat Pipe Switch Mod etudes Uere RR ede De Ha IP E e P Te 14 3 Figure 14 3 Power up Reset Sequence 14 5 Figure A 1 No CPU KAT4000 System Block A 1 Figure A 2 Web Interface for the Ethernet Core A 20 KAT4000 User s Manual 10007175 02 Tables Table 1 1 KAT4000 Address 1 7 Table 1 2 Regulatory Agency 1 10 Table 1 3 Technical References 1 12 Table 2 1 Circuit Board Dimensions 2 1 Table 2 2 JP4 Signal Descriptioris emet tt ERE I RERO ER Rena 2 5 Table 2 3 umpers P2 and added i oan 2 6 Table 2 4 J35 Signal Descriptions hr eR Rb ERR E arra 2 10 Table 2 5 Typical Power 2 2 16 Table 2 6 Environmental 2 16 Table 2 7 Air Flow 2 16 Table 3 1 MPC8548 Featur s I s
69. 3 0 5 Reserved 10007175 02 KAT4000 User s Manual CPLD version and ID Registers Address Register Map Offset hex Mnemonic Register Name continued 0x60 CSS1 Clock Synchronizer Secondary Source 1 0x64 CSS2 Clock Synchronizer Secondary Source2 7 18 0x68 CSS3 _ Clock Synchronizer Secondary Source 3 0x6C Reserved 0x70 CCR1 Clock Control AMC1 CLK1 0x74 CCR2 Clock Control AMC1 CLK2 0x78 CCR3 Clock Control AMC1 CLK3 0x7C CCR4 Clock Control AMC2 CLK1 0x80 CCR5 Clock Control AMC2 CLK2 0x84 CCR6 Clock Control AMC2 CLK3 0x88 CCR7 Clock Control AMC3 CLK1 0 8 CCR8 Clock Control AMC3 CLK2 nie 0x90 CCR9 Clock Control AMC3 CLK3 0x94 CCR10 Clock Control 4 CLK1 0x98 CCR11 Clock Control AMC4 CLK2 0x9C CCR12 Clock Control AMC4 CLK3 CCR13 Clock Control aTCA CLK3 A 4 CCR14 Clock Control aTCA CLK3 B 8 CSI Clock Synchronizer Interrupt 1 OxAC CSI2 Clock Synchronizer Interrupt 2 7 20 OxBO CSI _ Clock Synchronizer Interrupt VERSION AND ID REGISTERS Product ID Register PIDR The read only Product ID register indicates the product name and configuration The values of these bits are defined by strapping resistors Default register values are shown in the bot tom row of the register table Register 7 1 Product ID Register PIDR at Oxfc40 0000 7 6 5 4 3 2 1 0 PID1 PIDO reserved ECS PCIE 0 0 c
70. 4 3 2 1 0 DIR3 DIR2 DIRI DIRO GPIO3 GPIO2 GPIO1 GPIOO DIR3 DIRO GPIO Direction 0 GPIOx bit reflects the state of the GPIO pin The corresponding GPIO State bit becomes read only 1 GPIOx bit drives the GPIO pin according to the state of the corresponding bit 10007175 02 KAT4000 User s Manual E Fat Pipe Switch Module 10 GbE 1 GbE Fat Pipe Switch Module GPIO3 GPIOO Register 5 16 GPIO2 GPIOO LEDCTRL LED3 LEDO KAT4000 User s Manual GPIO State 0 Logic low 1 Logic high GPIN LED Register The GPIN LED register controls general purpose inputs to the PLD from the carrier There are also four LEDs which are under software control GPIN LED Register GPLED at 0x07 7 6 5 4 3 2 1 0 GPIO2 GPIO1 GPIOO LEDCTRL LED3 LED2 LED1 LEDO General Purpose Input LED Mode Control 0 LEDs 2 0 indicate insufficient voltage LED3 PCI Express Link Up LED2 3 3V supply low LED1 2 5V supply low LEDO 1 0V supply low 1 1 05 3 0 controlled by bits 3 0 LED State 0 Off 1 On 10007175 02 Fat Pipe Switch Module 10 GbE 10 GbE Fat Pipe Switch Module Note Figure 5 15 Fat Pipes x4 Figure 5 16 10 GBE 10 GBE FAT PIPE SWITCH MODULE Fig 5 15 shows how the 10 GbE 10 GbE fat pipe switch module maps to ports defined by the AMC O specification see Fig 1 3 for the full port mapping diagram This fat p
71. 5 6 LSBSEL1 Select AMC Site 1 7 8 LSBSEL5 Select Fat Pipe Module 9 10 LSBSEL6 Select IPMC PLD 7 20 KAT4000 User s Manual 10007175 02 Sites The KAT4000 provides four Advanced Mezzanine Card sites capable of supporting the following AMC form factors single or double width mid size or compact Total power of the AMC sites including optional RTMs shall not exceed 120 watts B style AMC con nectors are used Each site is individually configurable Note When using a compact AMC module the module must have a front panel that fully covers the front opening of the KAT4000 to maintain EMC compliance Note See PICMG 0 Rev 2 0 Advanced Mezzanine Card Base Specification for the maximum allowable com ponent height and PCB width for a custom AMC module designed specifically for the KAT4000 The following features are supported by all AMC interfaces Serial Ports These TTL level signals are for general purpose serial communications The KAT4000 routes the serial ports from the AMC sites directly to the Zone 3 connectors 10 100 1000 Ethernet Ports The KAT4000 provides up to two 1000 5 Ethernet ports from each AMC site into the Ethernet core switch VSC7376 PCI Express Ports Optional The KAT4000 provides one PCle port from each AMC site into the PCI Express switch PEX 8524 GbE sRIO PCle or 10 GbE Ports The KAT4000 provides four ports from each AMC site into the fat
72. 7 bit address The 2 atthe end ofthe offset is the length in bytes of the offset information sent to the device The serial EEPROMs all have two byte offset lengths The RTC has one byte offset length The temperature sensors have zero byte offset lengths imd2 chip address 0 1 2 of objects imm The imm command modifies the primary memory and automatically increments the address imm chip address 0 1 2 imm2 The imm2 command modifies the secondary 2 memory and automatically increments the address imm2 chip address 0 1 2 10007175 02 KAT4000 User s Manual 14 17 Monitor IPMC Commands Definition Definition Definition Definition Definition Definition KAT4000 User s Manual imw The imw command writes fills memory imw chip address 0 1 2 value count inm The inm command modifies 2 memory reads it and keeps the address inm chip address 0 1 2 iprobe The iprobe command probes to discover valid primary 2 bus chip addresses iprobe iprobe2 The iprobe command probes to discover valid secondary bus chip addresses iprobe2 switchsrom The switchsrom command reads bytes from the V C7376 GbE switch EEPROM and writes bytes to the EEPROM switchsrom read offset size switchsrom write source address size IPMC COMMANDS IPMI Baseboard Management Controller BMC watchdog is supported and serviced throughout t
73. Boot from soldered flash Boot device redirection is enabled default BRB reserved BS R SKT FL1 FLO BRB BootRedirected Bit 1 Thecurrent boot device does not match the initial default boot device R Reserved BSJ Boot from Socket Jumper 1 Active boot device is socketed flash SKT Socket Boot Device 1 Theboard booted from socket flash FL1 Flash 1 Boot Device 1 Theboard booted from flash bank 1 FLO Flash 0 Boot Device 1 Theboard booted from flash bank 0 KAT4000 User s Manual 10007175 02 CPLD Clock Synchronizer Registers Register 7 16 FS2 FS1 MS2 MS1 PCCI RSEL CLOCK SYNCHRONIZER REGISTERS Clock Synchronizer Control Registers 1 3 CSC1 CSC3 The Clock Synchronizer Control registers control the functionality of the clock synchronizer devices Default is 0x40 for register 1 and 0x00 for registers 2 and 3 Clock Synchronizer Control Registers 1 3 CSC1 CSC3 at Oxfc40 0040 Oxfc40 0044 Oxfc40 0048 respectively 7 6 5 4 3 2 1 0 FS2 FS1 MS2 MS1 RSEL reserved Default register values for CSC1are shown in the following row 0 1 0 0 0 0 Default register values for CSC2 and CSC3 are shown in the following row 0 0 0 0 0 0 Input Frequency Select 00 19 44MHz 01 8KHz 10 1 544 MHz 11 2 048 MHz Mode Select 00 Normal 01 Holdover 10 Freerun 11 Reserved Ph
74. Commands Serial Command Line Interface CLI A 3 A 13 Log In Log Out Procedures A 3 User Group Commands A 14 Help A 3 QoS Commands 14 Command 4 Mirror Commands A 16 Command Usage Instructions A 5 A sad pu MA Web 18 Command Overview A 6 System Commands A 8 Console Commands 8 Port Commands A 9 17 Appendix B MAC Commands A 10 Sensor Data Records B 1 10007175 02 KAT4000 User s Manual blank page 4000 User s Manual 10007175 02 Figures Figure 1 1 General System Block 2 1 5 Figure 1 2 KAT4000 Memory Mabp s 4 suche p an 1 6 Figure 1 3 AMC Port Mapping 2 1 9 Figure 2 1 Component 02 2 2 Figure 2 2 Component Map Bottom Rev 02 2 3 Figure 2 3 KAT4000 Front Panel norme fee qe va Rr ier seam olen 2 4 Figure 2 4 Jumper Fuse and Switch Locations 2 7 Figure 2 5 Jumper Fuse and Switch Locations 2 8 Figure 2 6
75. Device Interface Document AMC ATCA Advanced Mezzanine Card Base Specification PICMG 0 Rev 2 0 November 15 2006 PCI Express and Advanced Switching on AdvancedMC PICMG AMC 1 Rev 1 0 January 20 2005 AdvancedTCA Base Specification PicMc 3 0 Rev 2 0 March 18 2005 Engineering Change Notice 3 0 2 0 001 PICMG 3 0 Rev 2 0 ECN 3 0 2 0 001 June 15 2005 AdvancedTCA Ethernet Fibre Channel for Advanced TCA Systems PICMG 3 1 Rev 1 0 January 22 2003 http www picmg org CPLD MAX II Device Handbook Altera MII5V1 1 3 Preliminary December 2004 http www altera com EH KAT4000 User s Manual 10007175 02 Overview Additional Information Device Interface CPU EEPROM Ethernet Flash Hot Swap Document MPC8548E PowerQUICC III Integrated Host Processor Family Preliminary Reference Manual Freescale Semiconductor MPC8548ERM Rev 1 July 2005 http www freescale com ATMEL 2 Wire Serial EEPROM 64K AT24C64B Data Sheet ATMEL Corp Rev 3350D SEEPR May 2005 http www atmel com literature HawX G26 26 Port 10 100 1000 Managed Layer 2 Ethernet Switch VSC7376 Data Sheet Vitesse Semiconductor Corp VMDS 10133 Rev 2 1 August 2005 026 Reference Board Manual Software Manual Vitesse Semiconductor Corp RBM0007 Rev 09 November 24 2005 http www vitesse com 88E1111 Integrated 10 100 1000 Ultra Gigabit Ethernet Transceiver Datasheet Mar
76. Firmware Upgrade 9 48 Type Byte Data Field continued Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems 5 Upgrade Status 0 IPMCis not in the firmware upgrade mode 1 IPMCis in the firmware upgrade mode but upgrade session has not been opened yet 2 IPMC is in the firmware upgrade mode and an upgrade session has already been opened must send Firmware Upgrade Start to open it 6 Upgrade Cause if the Upgrade Status parameter is not 0 0 Boot Loader has read an ESC character from the Serial Debug Interface 1 The firmware has received a Firmware Upgrade Start command 2 The master 85 IPMC firmware checksum is invalid 3 Awatchdog reset has occurred while starting the new IPMC firmware 4 The slave 85 IPMC firmware has failed i e has been in reset fortoo long Firmware Upgrade Start Command The Firmware Upgrade Start command switches the IPMC to the upgrade mode If the IPMC firmware receives this command it stores a special magic number in a reserved loca tion of SRAM indicating that the Boot Loader is requested to enter the upgrade mode sends a reply with the 0 Node Busy completion code and reboots When the requestor receives the Node Busy reply it resends the Firmware Upgrade Start request By this time the IPMC firmware has already rebooted to the Boot Loader When the Boot Loader receives the Firmware Upgrade Start request it checks if a fi
77. Hubs AMC Sites 4000 User s Manual The NOR Flash consists of two 16 megabyte banks The supported NAND flash is 512 mega bytes or 1 gigabyte Flash is only implemented on the processor KAT4000 board configura tion Chapter 6 provides more information The KAT4000 uses a Complex Programmable Logic Device CPLD to control board reset logic the Board Configuration Board Revision and User LED registers and miscellaneous board logic Register access to the PLD is only available on the processor KAT4000 board configuration Chapter 7 provides more information Depending on the configuration the KAT4000 Ethernet interface consists of Reduced Gigabit RGMII Serial Gigabit SGMII 1000Base BX Serializer Deserializer SerDes Ether net core or fat pipe switch module Vitesse VSC7376 and 1000Base BX SerDes devices to the AMC sites One 10 100 eTSEC port from the 8548 is available through Zone 3 for Rear Transition Module RTM access This port is for development purposes only An EIA 232 console serial port from the MPC8548 serial 1 is available through an on board header and is optionally routable to Zone 3 for Rear Transition Module RTM access The default serial port settings are 9 600 baud 8 data no parity and 1 stop bit This port is for development purposes only A second serial port serial 2 allows the MPC8548 to communicate with the Intelligent Plat form Management Controller IPMC The default seri
78. If addr is not specified the environment variable loadaddr is used as the default bootm addr arg bootp The bootp command boots an image via a network connection using the BootP TFTP pro tocol If loadaddress or bootfilename is not specified the environment variables loadaddr and bootfile are used as the default bootp loadAddress bootfilename 10007175 02 KAT4000 User s Manual Monitor Boot Commands To use network download commands e g bootp bootvx rarpboot tftpboot the envi ronment variables listed in Table 14 4 must be configured To set a static IP these environ ment variables must be specified through the command line interface Table 14 4 Static IP Ethernet Configuration Environment Variable Description ipaddr Local IP address for the board serverip TFTP NFS server address netmask Net mask gatewayip Gateway IP address netdev eth0 default ethaddr MAC address 1 Ensure that each MAC address on the network is unique bootv The bootv command checks the checksum on the primary image in Flash and boots it if valid If it is not valid it checks the checksum on the secondary image in Flash and boots it if valid If neither checksum is valid the command returns back to the monitor prompt Definition Verify bootup bootv Write image to Flash and update NVRAM bootv lt primary secondary gt write source dest size Update NVRAM based on image already in Flash
79. Interface 10 100 1000BASE T Link Type Extension 0000b Link Grouping ID 00h Independent Channel Link Designator 000100000001b Port 0 Enabled Base Interface Channel 2 Link Type 01h PICMG 3 0 Base Interface 10 100 1000BASE T Link Type Extension 0000b 10007175 02 KAT4000 User s Manual System Management F Keying g KAT4000 User s Manual Field Value Description continued Link Grouping ID 00h Independent Channel Link Designator 111101000000b Port 3 2 1 0 Enabled Fabric Interface Channel 1 Link Type 01h PICMG 3 1 Ethernet Fabric Interface Link Type Extension 0000b Fixed 1000BASE BX Link Grouping ID 00h Independent Channel Link Designator 001101000000b Port 1 0 Enabled Fabric Interface Channel 1 Link Type 01h PICMG 3 1 Ethernet Fabric Interface Link Type Extension 0000b Fixed 1000BASE BX Link Grouping ID Independent Channel Link Designator 000101000000b Port 0 Enabled Fabric Interface Channel 1 Link Type 01h PICMG 3 1 Ethernet Fabric Interface Link Type Extension 0000b Fixed 1000BASE BX Link Grouping ID 00h Independent Channel Link Designator 111101000001b Port 3 2 1 0 Enabled Fabric Interface Channel 2 Link Type 01h PICMG 3 1 Ethernet Fabric Interface Link Type Extension 0000b Fixed 1000BASE BX Link Grouping ID 00h Independent Channel Link Designator 001101000001b Port 1 0 Enabled Fabric Interface Channel 2 Link Type 01h PICMG 3 1 Ethernet Fabric Interface Link Type Extension 0000b
80. KAT4000 IPMC places all messages coming to LUN 10 from IPMB 0 in a dedicated Receive Message Queue and those messages are processed by the payload instead of the IPMC firmware To read messages from the Receive Message Queue the payload software uses the standard Get Message command The payload software is notified about messages coming to LUN 10 via the Get Status command of the SIPL protocol and the payload notifi cation mechanism or if the LPC KCS based Payload Interface is used using the KCS inter rupt The Receive Message Queue of the 4000 IPMC is limited to 128 bytes which is 10007175 02 System Management standard Commands Note Table 9 5 sufficient for storing at least three IPMB messages but may be not enough for a larger number of messages Taking this into account the payload software must read messages from the queue as fast as possible caching them on the on carrier payload side for further handling if it is necessary If the Receive Message Queue is full the KAT4000 IPMC rejects all requests coming to LUN 10 with the COh Node Busy completion code and discards all responses coming to this LUN STANDARD COMMANDS The intelligent peripheral management controller IPMC supports standard IPMI com mands to query board information and to control the behavior of the board These com mands provide a means to identify the controller reset the controller return the controller s self test results re
81. Lower Critical Threshold readable Lower Non Critical Threshold readable Sensor Units 1 00 Analog Data Format unsigned Rate Unit none Modifier Unit none Percentage no Sensor Units 2 Base Unit 04 Volts Sensor Units 3 Modifier Unit 00 Unspecified Linearization 00 M 62 M Tolerance 00 B 00 00 Accuracy Accuracy Exp 00 0 Analog Characteristic Flags 07 Nominal Reading b8 Normal Maximum cb Normal Minimum a6 Sensor Maximum ff Reading Sensor Minimum Reading 00 Upper Non Recoverable dd Threshold Upper Critical Threshold 00 Upper Non Critical Threshold 00 KAT4000 User s Manual 10007175 02 Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Lower Non Recoverable 93 Threshold _ Lower Critical Threshold 00 Lower Non Critical Threshold 00 Positive Going Threshold Hyst 03 Value Negative Going 03 Threshold Hyst Value 00 ID String Type Length Code c5 Table B 9 1 2 Volt SDR Description KAT4000 Records Value Parameter Status Record ID 0007 _5 Version 51 Record Type 01 Full Sensor Record Record Length 30 Sensor Owner ID 00 Sensor Owner LUN 00
82. Management Controller IPMC based on the proprietary BMR H8S ATCA reference design from Pigeon Point Systems The KAT4000 IPMC implements all the standard Intelligent Platform Management Interface IPMI commands and provides hardware interfaces for other system management fea tures such as Hot Swap control LED control power control and temperature and voltage monitoring The IPMC also supports an EIA 232 interface for serial communications via the Serial Interface Protocol Lite SIPL IPMI commands IPMC OVERVIEW The basic features of the KAT4000 IPMC include Conformance to ATCA Base Specification PICMG 3 0 Geographical addressing according to PICMG 3 0 Ability to read and write Field Replaceable Unit FRU data on each capable AMC site Ability to reset IPMC from 0 Ability to read an inlet and outlet temperature sensor Ability to read payload voltage current levels Ability to send event messages to a specified receiver Allsensors generate assertion and or de assertion event messages Support for fault tolerant field upgrades Support for field updates of firmware via the payload processor interface Hardware added to accommodate console redirection over IPMB 10007175 02 KAT4000 User s Manual System Management IPMC Overview The following block diagram shows the IPMC connections for the KAT4000 Figure 9 1 IPMC Connections Block Diagram Payload Processor Payload Interface Power En
83. NAND Flash Two 8 kilobyte banks of non volatile serial EEPROM memory BOOT MEMORY CONFIGURATION The KAT4000 boot default is the 8 bit ROM socket which occupies the physical address space beginning at FC80 0000 Removing the shunt on jumper JP7 pins 1 2 uses the on board Flash as the boot device Read bit 5 of Jumper Settings register at FC40 0018 see Register Map 7 7 for the boot device selection Memory Configuration Jumper Default Jumper Function Options Configuration JP7 Selects monitor Jumper out User Flash Jumper in ROM socket pins 1 2 boot device Jumper in ROM socket USER FLASH The KAT4000 supports three independent Flash regions one socketed and two NOR The KAT4000 will boot from either region and is selected by jumper JP7 1 2 socketed Flash is the default User Flash starts at location 000 000016 with one megabyte at the base of Flash reserved for the monitor Two banks of NOR Flash are available 16 MB each see Table 14 3 for memory address details One bank of socketed Flash in a 32 pin PLCC includes up to 512 kilobytes The Flash devices interface to the most significant data bits of the PowerPC data bus For example if the data path is 64 bits wide the PowerPC data bus is declared as D 0 63 where DO is the most significant bit and D63 is the least significant bit The interface to NOR flash memory is 16 bits which uses bits 0 to 15 on the processor data bus If booting from user Flash t
84. Owner ID _00 Sensor Owner LUN 00 Sensor Number _ 00 mE Entity ID 14 Power Module DGto DC Converter Entity Instance _ 60 Sensor Initialization 7f Init Scanning Init Sensor Type Init Hysteresis Init Thresholds Init Events E Sensor Scanning enabled Event Generation enabled Sensor Capabilities _69 Ignore Sensor no Auto Re Arm enabled gt Sensor Hysteresis hysteresis is settable readable Sensor Threshold Access threshold is settable readable Event Message Control global disable only Sensor Type 02 Voltage 10007175 02 KAT4000 User s Manual Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Event Reading Type Code 01 Threshold Assertion Event Mask _ 4000 Lower Non Recoverable Threshold comparison returned Deassertion Event Mask _ 4000 Lower Non Recoverable Threshold comparison returned Discrete Reading Mask Upper Non Recoverable Threshold settable Upper Critical Threshold settable Upper Non Critical Threshold settable Lower Non Recoverable Threshold settable Lower Critical Threshold settable Lower Non Critical Threshold settable Upper Non Recoverable Threshold readable Upper Critical Threshold readable Upper Non Critical Threshold readable Lower Non Recoverable Threshold readable
85. RXO no connect no connect 7 RTM_RX1 RTM_RX1 B3_TTIP2 B3_TRING2 8 B3_TTIP1 B3_TRING1 B3 RTIP1 B3 RRINGT 9 no connect no connect RTM_RX2 RTM_RX2 10 B3_RTIP3 B3_RRING3 RTM_RX3 RTM_RX3 10007175 02 KAT4000 User s Manual Connectors 7 Row EF GH 1 no connect no connect RTM GPIO3 RTM GPIO2 2 B2 RTIP3 B2 RRING3 RTM_GPIO1 RTM GPIOO 3 GIG4_TX GIG4_TX B2_RTIP4 B2_RRING4 4 B2_TTIP6 B2_TRING6 B2_RTIP6 B2_RRING6 5 B2_TTIP8 B2 TRING8 B2 RTIP8 B2 RRING8 6 GIG4_RX GIG4_RX no connect no connect 7 RTM_TXO 0 B3 2 B3 RRING2 8 RTM_TX1 RTM_TX1 _ no connect _ noconnect 9 B3 TTIP3 B3 TRING3 RTM_TX2 D 10 B3 4 B3_TRING4 RTM_TX3 RTM_TX3 Table 12 6 Zone 3 Connector 32 Pin Assignments Row AB CD 1 FP TX CONN RX 2 connect B1 _TTIP2 B1 TRING2 3 B1 TTIP1 B1 TRING1 B1 RTIP1 B1_RRING1 4 no connect connect RTM_PSO_ no connect CONN 5 B1_RTIP3 B1_RRING3 connect noconnect 6 no connect no connect B1 RTIPA B1 RRINGA4 7 B1 6 B1 TRINGG B1 RTIPG B1_RRING6 8 B1_TTIP8 B1_TRING8 B1 RTIP8 B1 RRINGS 9 no connect no connect no connect no connect 10 no connect no connect B2 RTIP2 B2 RRING2 Row EF GH 1 HOST TX HOST CONN RX no connect no connect 2 12C_RTM_SCL_ I2C_RTM_SDA_ B1 RTIP2 B1 RRING2 BUFF BUFF 3 no connect noconnect no connect no conn
86. Reading 00 Normal Maximum 00 Normal Minimum 00 Sensor Maximum 00 Reading Sensor Minimum Reading 00 Upper Non Recoverable 00 Threshold Upper Critical Threshold 00 Upper Non Critical Threshold 00 LowerNon Recoverable 00 Threshold Lower Critical Threshold 00 Lower Non Critical Threshold 00 Positive Going Threshold Hyst 00 Value Negative Going 00 Threshold Hyst Value 00 ID String Type Length Code cd Table B 5 BMC Watchdog SDR Description KAT4000 Records Value Parameter Status Record ID 0003 SDR Version 51 Record 01 Full Sensor Record _ Record Length 37 Sensor Owner ID 00 _ Sensor Owner LUN 00 Sensor Number 00 Entity ID 03 _ Processor 10007175 02 KAT4000 User s Manual Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Entity Instance 60 Sensor Initialization 67 Init Scanning Init Sensor Type Init Events Sensor Scanning enabled Event Generation enabled Sensor Capabilities 41 Ignore Sensor no Auto Re Arm enabled Sensor Hysteresis no hysteresis Sensor Threshold Access no threshold Event Message Control global disable only Sensor Type 23 Watchdog2 Event Reading Type Code ef Sensor
87. Records KAT4000 Records Value Parameter Status continued Sensor Minimum Reading 00 Upper Non Recoverable 10 Threshold Upper Critical Threshold 00 Upper Non Critical Threshold 00 Lower Non Recoverable 00 Threshold Lower Critical Threshold 00 Lower Non Critical Threshold 00 p Positive Going Threshold Hyst 02 Value Negative Going Threshold Hyst 00 Value OEM 00 o ID String Type Length Code cc Table B 23 B3 12V Current SDR Description KAT4000 Records Value Parameter Status Record ID 0015 SDR Version 51 E m Record Type 01 Full Sensor Record Record Length 37 Sensor Owner ID 00 Sensor Owner LUN 00 BE Sensor Number 00 Entity ID ci AMC Module E Entity Instance 67 Sensor Initialization 5d Init Scanning Init Sensor Type IE Init Hysteresis m Init Thresholds E Sensor Scanning enabled Sensor Capabilities 69 Ignore Sensor no Auto Re Arm enabled Sensor Hysteresis hysteresis is settable readable Sensor Threshold Access threshold is settable readable Event Message Control global disable only 03 Current Event Reading Type Code 01 Threshold E Assertion Event Mask 0800 Upper Non Recoverable Going High supported B 38 KAT4000 User s Manual 10007175 02 Appendix B sensor Data Records
88. Records _ Value Parameter Status Record ID 000b SDR Version 51 _ Record 01 _ Full Sensor Record _ Record Length 037 _ Sensor Owner ID 00 Sensor Owner LUN 00 Sensor Number 00 EntitylD ao Entity Instance 60 10007175 02 KAT4000 User s Manual Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Sensor Initialization 7f Init Scanning Init Sensor Type Init Hysteresis Init Thresholds Init Events Sensor Scanning enabled Event Generation enabled Sensor Capabilities 69 Ignore Sensor no Auto Re Arm enabled Sensor Hysteresis hysteresis is settable readable Sensor Threshold Access threshold is settable readable Event Message Control global disable only Sensor Type 01 Temperature Event Reading Type Code 01 Threshold Assertion Event Mask 7a95 Lower Non Recoverable Threshold comparison returned Lower Critical Threshold comparison returned Lower Non Critical Threshold comparison returned Upper Non Recoverable Going High supported Upper Critical Going High supported Upper Non Critical Going High supported Lower Non Recoverable Going Low supported Lower Critical Going Low supported Lower Non Critical Going Low supported Deassertion Event Mask 7a95 Lower Non Recoverable Threshold comparison returned Lower Critica
89. Register 1 RCR1 at 40 0024 7 9 Register 7 14 Reset Command Register 2 RCR2 at 0 40 0028 7 10 Register 7 15 Boot Device Redirection Register BDRR at 0 40 0030 7 12 Register 7 16 Clock Synchronizer Control Registers 1 3 CSC1 CSC3 at Oxfc40 0040 Oxfc40 0044 Oxfc40 0048 respectively 7 13 Register 7 17 Clock Synchronizer Primary Source Registers 1 3 CPS1 CPS3 at 0xfc40 0050 Oxfc40 0054 0xfc40 0058 44 7 14 Register 7 18 Clock Synchronizer Secondary Source Registers 1 3 CSS1 CSS3 at Oxfc40 0060 Oxfc40 0064 Oxfc40 0068 7 15 10007175 02 KAT4000 User s Manual Registers continued 4000 User s Manual Register 7 19 Clock Control Registers 1 14 CCR1 CCR14 at Oxfc40 0070 0xfc40 0074 0 40 0078 Oxfc40 007c Oxfc40 0080 Oxfc40 0084 0xfc40 0088 Oxfc40 008c 0xfc40 0090 Oxfc40 0094 Oxfc40 0098 Oxfc40 009c Oxfc40 00a0 Oxfc40 00a4 respectively 7 17 Register 7 20 Clock Synchronizer Interrupt Registers 1 3 CSI1 CSI3 at Oxfc40 00a8 Oxfc40 00ac Oxfc40 00b0 respectively 7 7 7 18 Register 9 1 Enable Payload Control Command
90. Scheduler KAT4000 User s Manual The stations implement the PCI Express Base 1 0a Physical Data Link and Transaction layers Each PCI Express station is able to support up to 16 integrated Serializer De serializer 1000Base BX SerDes modules which provide PCI Express hardware interface lanes These lanes can be configured to support up to four PCI Express ports per station The PEX 8524 contains two stations Station 0 and Station 1 connected by non blocking Crossbar Switch fabric From the system model viewpoint each PCI Express port is a virtual PCI to PCI bridge device and contains its own set of PCI Express Configuration registers One of the ports on either station can be designated the Upstream port or primary bus in PCI terms Through use of the Upstream port the firmware configures the other ports during standard enu meration The PCI Express Upstream Station supports Upstream ports and Downstream ports at the same time but lanes from different stations cannot be combined to form ports 10007175 02 Common Switch Region PCI Express Switch optional EEPROM Interface The PEX 8524 has an embedded 64 kilobyte SPI EEPROM controller This direct interface provides the 7 8 MHz serial clock EE SK chip select EE CS and data output EE DO for the EEPROM and receives data input EE DI f
91. Sensor Owner ID 00 _ Sensor Owner LUN 00 Sensor Number 00 Entity ID c1 AMC Module 10007175 02 KAT4000 User s Manual Appendix B sensor Data Records KAT4000 Records Entity Instance Sensor Initialization Sensor Capabilities Parameter Status continued Init Scanning Init Sensor Type Init Hysteresis Init Thresholds Sensor Scanning enabled Ignore Sensor no Auto Re Arm enabled Sensor Hysteresis hysteresis is settable readable Sensor Threshold Access threshold is settable readable Event Message Control global disable only Sensor Type 03 Current Event Reading Type Code 01 Threshold Assertion Event Mask 0800 Upper Non Recoverable Going High supported Deassertion Event Mask 4800 Lower Non Recoverable Threshold comparison returned Upper Non Recoverable Going High supported Discrete Reading Mask 3838 Upper Non Recoverable Threshold settable Upper Critical Threshold settable Upper Non Critical Threshold settable Upper Non Recoverable Threshold readable Upper Critical Threshold readable Upper Non Critical Threshold readable Sensor Units 1 00 Analog Data Format unsigned Rate Unit none Modifier Unit none Percentage no Sensor Units 2 Base Unit 05 Amps Sensor Units 3 Modifier Unit 00 Unspecified Linearization 00
92. Threshold 00 Lower Non Recoverable 00 Threshold Lower Critical Threshold 00 Lower Non Critical Threshold 00 E Positive Going Threshold Hyst 02 Value Negative Going Threshold Hyst 00 Value B 44 KAT4000 User s Manual 10007175 02 Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued OEM 200 ID String Length Code cc Table B 27 48V Volt SDR Description KAT4000 Records Value Parameter Status Record ID 0019 E _ SDR Version 51 _ Record 01 Full Sensor Record Record Length MEM Sensor Owner ID 00 Sensor Owner LUN 00 Sensor Number 00 Entity ID Entity Instance 60 Sensor Initialization 7f Init Scanning Init Sensor Type Init Hysteresis Init Thresholds Init Events Sensor Scanning enabled Sensor Capabilities 69 Ignore Sensor no Auto Re Arm enabled Sensor Hysteresis hysteresis is settable readable Sensor Threshold Access threshold is settable readable Event Message Control global disable only Sensor Type 02 Voltage E Event ReadingTypeCode 01 Threshold AssertionEvent Mask 4801 LowerNon Recoverable Threshold comparison returned _ Upper Non Recoverable Going High supported Lower Non Critical Going Low sup
93. Upper Non Recoverable f8 Threshold _ Upper Critical Threshold 00 p Upper Non Critical Threshold 00 Lower Non Recoverable 7c Threshold Lower Critical Threshold 00 Lower Non Critical Threshold 00 46 KAT4000 User s Manual 10007175 02 Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Positive Going Threshold Hyst 02 Value Negative Going Threshold Hyst 02 Value OEM 00 ID String Type Length Code c9 Table B 28 48V Current SDR Description KAT4000 Records Value Parameter Status Record ID 001a SDR Version 51 Record 01 Full Sensor Record Record Length 34 Sensor Owner ID 00 Sensor Owner LUN 00 Sensor Number 00 Entity ID Entity Instance 60 Sensor Initialization Hf Init Scanning Init Sensor Type lnit Hysteresis Init Thresholds Init Events Sensor Scanning enabled Sensor Capabilities 69 Ignore Sensor no Auto Re Arm enabled Sensor Hysteresis hysteresis is settable readable Sensor Threshold Access threshold is settable readable Event Message Control global disable only Sensor Type 03 Current Event Reading Code 01 Threshold Assertion Event Mask 0800 Upper Non Recoverable Going High supported Deassertion Event Mask 4800 Lower Non Recoverable
94. Ver 5 1906 Clearing ALL of memory DRAM 512 MB Testing Top 1M Area of DRAM PASSED Relocating code to RAM FLASH 16MB e0000000 16MB e1000000 32 MB PCIe Waiting for PCIe Devices Bus Dev Vend DevID Class Int 04 00 14e4 5580 0280 00 03 00 1055 8111 0604 00 02 01 1055 8532 0604 00 02 02 1055 8532 0604 00 02 03 1055 8532 0604 00 02 08 1055 8532 0680 00 02 09 1055 8532 0604 00 02 Oa 1055 8532 0604 00 09 00 1957 7011 0520 00 02 0b 1055 8532 0604 00 01 00 1055 8532 0604 00 Ins serial Out serial Err serial Ser 1114 Diags Mem PASSED Diags I2C PASSED Diags Flash PASSED BootDev Socket I cache enabled D cache enabled write through L2 cache enabled L2CTL 0x20000000 write through IPMC v0 2 1 DOC Turbo Mode Net eTSEC1 eTSEC2 eTSEC3 Core Eth Sw VSC7376 Fat Pipe Eth Sw BCM56580 autoboot in 1 seconds hit h to stop KAT4000 Mon 1 39 gt Monitor command prompt 10007175 02 KAT4000 User s Manual 14 3 Monitor Basic Operation Table 14 1 KAT4000 User s Manual This prompt is also displayed as an indication that the monitor has finished executing a command or function invoked at the command prompt except when the command loads and jumps to a user application The hardware product name KAT4000 and the current software version number are displayed in the prompt Prior to the console port being
95. address hostname EMERSON Target hostname _KAT4000 icache on Enables the processor L1 instruction cache Valid options on off ipaddr 0 0 0 0 Board IP address I2cache on Enables the L2 cache Valid options on off loadaddr 0 100000 Define the address to download user application code to used with TFTP logical slot undefined ATCA chassis logical slot number of KAT4000 location Valid options Not defined in default configuration reported at bootup from the IPMC model KAT4000 Board model number netmask 0 0 0 0 Board sub network mask 10007175 02 KAT4000 User s Manual 14 29 Monitor Environment Variables Default Variable Value Description continued _ wait 0 Specifies time to wait until PCle enumeration occurs When hit q during pcie wait no PCle enumeration will occur and a POST fail flag will be set Valid options time in seconds physical slot undefined ATCA chassis physical slot number of KAT4000 location Valid options Not defined in default configuration reported at bootup from the IPMC powerondiags on Turns POST diagnostics on or off after power on reset Valid options on off preboot undefined Command to execute immediately before auto booting or coming to the prompt rootpath eng Pathname of the NFS server root file system artesyn serial XXXXX Board serial number serverip 0 0 0 0 Boot server IP address shelf_addr undefined ATCA chassis shelf address provided by shelf mana
96. available the monitor will display a four bit hexadecimal value on LED1 through LED4 to indicate the power up status see Table 14 1 See Fig 2 7 for the debug LED locations In the event of a specific initialization error the LED pattern will be displayed and the board initialization will halt Debug LED Codes LED Code Power up Status LED Value BOARD PRE INIT start booting setup BATs done 0x01 SERIAL INIT console init done 0x02 CHECKBOARD get processor and bus speeds done 0x03 SDRAM INIT RAM ECC init done 0x04 AFTER RELOC U Boot relocated to RAM done 0x05 MISC R final init including Ethernet done 0x06 GONE PROMPT 0x00 BASIC OPERATION The monitor performs various configuration tasks upon power up or reset This section describes the monitor operation during initialization of the KAT4000 board The flowchart see Fig 14 3 illustrates the power up and global reset sequence bold text indicates envi ronment variables Power up Reset Sequence The KAT4000 monitor follows the boot sequence in Fig 14 3 before auto booting the oper ating system or application software At power up or board reset the monitor performs hardware initialization diagnostic routines autoboot procedures free memory initializa tion and if necessary invokes the command line The U Boot monitor also detects if the optional PCI Express and serial Rapid I O switches are present Note that the U Boot monitor has the ability to timeout while waiting
97. cleared after every system hard reset or timer time out 10007175 02 KAT4000 User s Manual 9 27 System Management IPMC Watchdog Timer Commands The Timer Use fields indicate Monitor FRB 2 Time out A Fault resilient Booting level 2 FRB 2 time out has occurred This indicates that the last system reset or power cycle was due to the system time out during POST presumed to be caused by a failure or hang related to the bootstrap processor Monitor POST Time out In this mode the time out occurred while the watchdog timer was being used by the moni tor for some purpose other than FRB 2 or OS Load Watchdog OS Load Time out The last reset or power cycle was caused by the timer being used to watchdog the interval from boot to OS up and running This mode requires system management software or OS support The monitor should clear this flag if it starts this timer during POST SMS OS Watchdog Time out OEM KAT4000 User s Manual This indicates that the timer was being used by System Management Software SMS Dur ing run time SMS starts the timer then periodically resets it to keep it from expiring This periodic action serves as a heartbeat that indicates that the OS or at least the SMS task is still functioning If SMS hangs the timer expires and the IPMC generates a system reset When SMS enables the timer it should make sure the SMS bit is set to indicate that the timer is being used in its
98. for specifying individual user groups or a range of user groups The range is 1 26 The lt portlist gt type is very useful when setting up multiple ports in the same mode For example the following commands will divide the ports into two untagged VLANs and enable VLAN awareness Example add 1 1 8 add 2 9 16 pvid 1 8 1 pvid 9 16 2 aware all enable vlan vlan vlan vlan vlan Command Overview Help Up Exit System System System 11 keepIP Configuration Restore Default Name lt name gt System Initialize lt serialnum gt System Reboot Console Configuration KAT4000 User s Manual Console Password Console Timeout Console Prompt lt password gt lt timeout gt lt prompt_string gt Port Configuration lt portlist gt Port Mode lt portlist gt lt mode gt Port Flow Control lt portlist gt Port State lt portlist gt enable Port MaxFrame lt portlist gt Port Statistics lt portlist gt c Port Excessive Collisions Drop MAC Configuration MAC Add lt macaddress gt lt portlist gt MAC Delete lt macaddress gt lt vid gt MAC Lookup lt macaddress gt lt vid gt MAC Table lt vidlist gt MAC Flush MAC Agetime MAC Learning lt agetime gt lt enable disable gt VLAN Configuration lt portlist gt VLAN Add lt vidlist gt lt portlist gt VLAN Delete lt vidlist gt VLAN Lookup lt vidlist gt enable disable disable lt framesiz
99. hexadecimal value such as x followed by ENTER mm b w 1 address In this example the mm command is used to write random 8 bit data starting at the physi cal address 0x80000 mm b 80000 00080000 ff 12 00080001 ff 23 00080002 ff 34 00080003 ff 45 00080004 ff 00080005 ff x gt md b 80000 6 00080000 12 23 34 45 ff ff 4 gt nm The nm command modifies a single object repeatedly Once started the command line prompts for a new value at the selected address After a new value is entered pressing ENTER modifies the value in memory and then the new value is displayed The command line then prompts for a new value to be written at the same address Pressing ENTER with out entering a new value leaves the original value unchanged To exit the nm command enter a non valid hexadecimal value such as x followed by ENTER nm b w 1 address mw The command mw writes value to memory starting at address The number of objects mod ified can be defined by an optional fourth argument count mw b w 1 address value count In this example the mw command is used to write the value Oxabba three times starting at the physical address 0x80000 mw w 80000 abba 3 md 80000 00080000 abbaabba abbaffff ffffffff ffffffff 000800105 10007175 02 Monitor Flash Commands Definition
100. occurs concurrently with the time out action This clears the Timer Use Expiration flags A bit set in byte 4 of this command clears the cor responding bit in byte 5 of the Get Watchdog Timer command These hold the least significant and most significant bytes respectfully of the countdown value The Watchdog Timer decrement is one count 100 ms The counter expires when the count reaches zero If the counter is loaded with zero and the Reset Watchdog command is issued to start the timer the associated timer events occur immediately 10007175 02 KAT4000 User s Manual E System Management IPMC Watchdog Timer Commands Table 9 32 Set Watchdog Timer Command Type Request Data 9 30 KAT4000 User s Manual Byte 1 Data Field Timer Use 7 1b don t log 6 1b don t stop timer on Set Watchdog Timer command new for IPMI v1 5 new parameters take effect immediately If timer is already running countdown value will get set to given value and countdown will continue from that point If timer is already stopped it will remain stopped If the pretime out interrupt bit is set it will get cleared Ob timer stops automatically when Set Watchdog Timer command is received 5 3 reserved 2 0 timer use logged on expiration when don t log bit Ob 000b reserved 001b Monitor FRB 2 010b Monitor POST 011b OS Load 100b SMS OS 101b OEM 110b 111b reserved Timer Actions 7 reserved 6 4 pretime out interrupt logg
101. on page 56 F W Firmware Progress 0020 Table B 34 page B 58 Table B 2 4000 SDR Description KAT4000 Value Parameter Status Record ID 0000 SDR Version 51 Record 12 Controller Record Length 12 Device Slave Address 00 Channel Number 00 Power State Notification cc ACPI System Power State notification required Global Notification ACPI Device Power State notification required Controller Status dynamic Controller Logs Init Agent Errors yes Log Init Agent Errors Accessing Controller yes Misc Controller Info enable event message generation from controller Device Capabilities 29 IPMB Event Generator FRU Inventory Device Sensor Device FRU Entity ID a0 PICMG Front Board FRU Entity Instance _ 60 00 Table B 3 Hot Swap SDR Description KAT4000 Records Value Parameter Status Record ID 0001 SDR Version 51 Record Type 01 Full Sensor Record Record Length 33 Sensor Owner ID 00 Sensor Owner LUN 00 Sensor Number 00 EntityID a0 Entity Instance 60 B KAT4000 User s Manual 10007175 02 Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Sensor Initialization 6
102. pipe module 14 2 MONNE certet 14 24 e header JP1 2 4 test commands 14 21 coste 14 21 CPLD TAG header 7529 booting 14 1 ITE ex eicere exp 14 14 CPU TAG COP 3 14 troubleshooting 14 31 JURO 14 14 CPU TAG COP header P1 2 9 typographic conventions 14 9 seme 14 24 interface pis 1 2 U BOOE swede ged 14 1 phy 14 25 JTAG emulation header 35 updates 14 7 PING eese 14 25 2 10 version number 2 15 14 21 adus 2 9 monitor commands POLE CE re s sese dried 14 16 hubs ero pA res 14 22 rarpboOE oo 14 11 122 PECES 14 22 14 25 28 E 14 22 14 26 4 0 2 5 14 9 14 21 14 9 SCHPE 14 26 14 9 14 19 L 14 9 a 14 21 L2 cache CPU 3 3 14 10 14 26 LEDS 2 10 ven cete ete 14 10 5 14 26 9 33 ku e 14 13 terrm een 14 26 COMO a 14 22 switch
103. pipe switch module optional capable of using GbE sRIO PCle or 10 GbE protocols User 1 0 The AMC connectors provide the user defined I O for custom connectivity The KAT4000 routes the user I O pins from the AMC sites directly to the Zone 3 connectors IPMB L The local IPMB interfaces between the KAT4000 s IPMC and the AMC sites MMC 10007175 02 KAT4000 User s Manual m Sites AMC Connectors Figure 8 1 _ CONNECTORS The connectors for modules B1 through B4 have 170 pins see Fig 8 1 and support the Ethernet core switch the PCI Express Switch the Fat Pipe Switch module and Zone 3 Refer to the component map in Fig 2 1 for the location and orientation of the AMC B connectors on the KAT4000 AMC B Connector 86 el 85 AMC SIGNALS The following signals are available on all four connectors All signals are bi directional unless stated otherwise A sustained tristate line is driven high for one clock cycle before float The signals are the same for each connector since they are differential pairs Bn stands for B1 through B4 Differential pairs from AMC cards B1 B4 to the fat pipe switch module Bn CONSOLE 5 ports from AMC sites to Zone 3 Bn ENABLE This signal connects to the IPMC PLD and enables the MMC on the board Bn LEDCTRL Serial ports from AMC sites to Zone 3 _ 1_
104. replacement selec tion 0 DCFAis disabled 1 DCFAis enabled No op the data and instruction cache touch instructions 0 dcbst and icbt are enabled 1 dcbst and icbt are treated as no ops Hardware Implementation Dependent 1 Register One of the functions of the Hardware Implementation Dependent 1 HID1 register is to display the state of the PLL_CFG 0 4 signals The following register map summarizes HID1 for the MPC8548 CPU 10007175 02 KAT4000 User s Manual Central Processing Unit Interrupts and Exception Processing Register 3 3 MPC8548 Hardware Implementation Dependent Register 1 HID1 32 33 34 39 40 45 46 47 MODE PLL_CFG reserved RFXE R 48 49 50 51 52 63 reserved AST ABE reserved ME PLL MODE Read only for integrated devices 01 Fixed value for MPC8548 PLL_CFG This is reflected directly from configuration input pins read only PLL_CFG 0 4 corre sponds to the integer divide ratio and PLL_CFG is the half mode bit 000100 ratio of 2 1 000101 ratio of 5 2 2 5 1 000110 ratio of 3 1 000111 ratio of 7 2 3 5 1 R Reserved should be cleared RFXE Read Fault Exception Enable controls whether assertion of core fault in causes a machine check interrupt 0 Assertion of core fault in cannot cause a machine check 1 A machine check can occur due to assertion of fault in ASTME Address bus Streaming Mode Enable 0 Mode disabled 1 Mode enabled AB
105. s Manual E Central Processing Unit Figure 3 1 MPC8548 Block Diagram Engine 12C Controller Security Engine I2C Controller Interrupt Controller PIC gt DDR2 Controller Bus Local Bus Controller OCeaN Serial RapidlO or Switch PCI Express Controller TBI RTBI eTSEC Fabric 64 bit PCI X Controller RGMII RMII 10 100 1 Gb MII GMII TBI RTBI eTSEC RGMII RMII 10 100 1 Gb MII GMII 4 Channel DMA Controller TBI RTBI eTSEC RGMII RMII 10 100 1 Gb RTBI eTSEC RMII 10 100 1 Gb 2 2 IRQs DDR2 SDRAM Hash GPIO 4x RapidlO 8x PCI Express PCI X 133 MHz The MPC8548 PowerQUICC III version follows the PowerQUICC Il communications proces sor Some new MPC8548 features used on the KAT4000 include e500 core 32 bit implementation of the Book E architecture Serial Management Channel SMC UART functionality implemented in SCC Fourintegrated 10 100 1000 Ethernet controllers Double Data Rate Two DDR2 SDRAM memory controller 4 port On Chip Network OCeaN full crossbar switch fabric Enhanced debug features For more detailed information reference the Freescale application note Migrating from PowerQUICC II to PowerQUICC KAT4000 User s Manual 10007175 02 Central Processing Unit MPC8548 Functions MPC8548 FUNCTIONS The MPC8548 provides the following functions on the KAT4000 module e Dual dev
106. the processor to take external input fixed interval timer system management performance monitor or decrementer interrupts 0 Disabled 1 Enabled Privilege level 0 Supervisor level instructions are executed 1 User level instructions are executed Machine check Enable 0 Machine check interrupts disabled 1 Machine check interrupts enabled User BTB Lock Enable 0 Execution of the BTB lock instructions for user mode disabled 1 Execution of the BTB lock instructions for user mode enabled Instruction address Space 0 CPU directs all instruction fetches to address space 0 1 CPU directs all instruction fetches to address space 1 Data address Space 0 CPU directs data memory accesses to address space 0 1 CPU directs data memory accesses to address space 1 Marks a process for the Performance Monitor 0 Process is not marked 1 Process is marked PERIPHERAL INTERFACE The MPC8548 uses the peripheral bus to communicate with its peripherals Table 3 3 lists the order in which the processor handles requests from peripherals MPC8548 Peripheral Request Priority Priority Function Request Highest 1 Reset in the Communication Processor Command register CPCR or System Reset SRESET SDMA bus error Commands issued to the CPCR Emergency from FCCs MCCs and SCCs IDMA 1 4 emulation default option 1 jtt FCC1 receive FCC1 transmit 10007175 02 Central Processing Unit MPC8548 Peripheral Modules
107. 0 M 00 00 B 00 B Accuracy 00 Accuracy Accuracy Exp 00 00 00 Characteristic Flags 00 Nominal Reading 200 Normal Maximum 00 Normal Minimum 00 Sensor Maximum Reading 00 _ Sensor Minimum Reading 00 5 _ Upper Non Recoverable 00 Threshold _ Upper Critical Threshold 00 Upper Non Critical Threshold 00 IE Lower Non Recoverable 00 i Threshold Lower Critical Threshold 00 Lower Non Critical Threshold 00 Positive Going Threshold Hyst 00 Value Negative Going Threshold Hyst 00 Value OEM 00 ID String Type Length Code cb Table 19 B1 12V Current SDR Description KAT4000 Records Value Parameter Status Record ID 0011 SDR Version 51 _ Record Type 01 _ Full Sensor Record _ Record Length 37 Sensor Owner ID 00 Sensor Owner LUN 00 Sensor Number 00 EntityID ci AMC Module Entity Instance 65 10007175 02 KAT4000 User s Manual B 31 Appendix B sensor Data Records KAT4000 Records Sensor Initialization Sensor Capabilities It 69 Ignore Sensor Value Parameter 5d Init Scanning Status continued Init Sensor Type Init Hysteresis Init Thresholds Sensor Scanning Auto Re Arm enabled no enabled
108. 0 Value Negative Going Threshold Hyst 00 Value OEM 00 ID String Type Length Code cb Table B 18 B4 Hot Swap SDR Description KAT4000 Records Value Parameter Status Record ID 0010 SDR Version 51 Record Type 01 Full Sensor Record Record Length _36 Sensor Owner ID _00 Sensor Owner LUN 00 Sensor Number 00 Entity ID ci AMC Module Entity Instance _68 Sensor Initialization 67 Init Scanning Init Sensor Type Init Events gt Sensor Scanning enabled Event Generation _ enabled Sensor Capabilities 4 Ignore Sensor no Auto Re Arm enabled gt Sensor Hysteresis no hysteresis Sensor Threshold Access no threshold Event Message Control global disable only Sensor Type fo Event Reading Type Code 6f Sensor Specific Assertion Event Mask ooff Deassertion Event Mask 0000 Discrete Reading Mask ooff Sensor Units 1 00 Analog Data Format unsigned Rate Unit none Modifier Unit none Sensor Units 2 Base Unit 00 Unspecified B 30 KAT4000 User s Manual 10007175 02 Appendix B sensor Data Records KAT4000 Records _ Value Parameter Status continued Sensor Units 3 Modifier Unit 00 Unspecified Linearization 0
109. 0 128 MB This memory region is at the very top of memory and can be reserved not to be cleared on start up or reset Default size of the protected memory region is 0 pram is defined in kilobytes and is a base 10 number The smallest allowable size is 4 4 kB and the largest recommended size is 32768 32 MB pram should be4 kB aligned otherwise U Boot will round pram to the next 4 kB size Sets the boot arguments that are passed into the secondary application images when using the bootv command If not defined bootv will pass the bootargs configuration parameters into both the primary and secondary application images 6 Themoninit command does not initialize these variables Each parameter is only defined if a change from the default setting is desired and is not defined after initialization of the environment variables TROUBLESHOOTING To bypass the full board initialization sequence attach a terminal to the console located on the front of the KAT4000 Configure the terminal parameters to be 9600 bps no parity 8 data bits 1 stop bit Reset the KAT4000 while holding down the s key Pressing the s key forces a configura tion based on default environment variables 10007175 02 KAT4000 User s Manual 14 31 Monitor Download Formats 14 32 KAT4000 User s Manual DOWNLOAD FORMATS The 4000 monitor supports binary and Motorola S Record download formats as described in the following sections Binary The binary fo
110. 0 Oxf address Register address within block 0 255 or 0x00 Oxff Debug Write Register Syntax 10007175 02 KAT4000 User s Manual A 17 Appendix A web Interface Debug Write Register block subblock address value Description Write value to register address block Block identifier 0 7 or 0 0 0 7 subblock Sub block identifier 0 15 or 0x0 Oxf address Register address within block 0 255 or 0x00 Oxff value Register value 0 4294967295 or 0x00000000 Oxfffffftf Debug PHY Read Syntax Debug PHY Read lt portlist gt lt address gt Description Read PHY register for port lt portlist gt Port list lt address gt Register address 0 31 or 0x00 0x1f Default Read all registers Debug PHY Write Syntax Debug PHY Write lt portlist gt lt address gt lt value gt Description Write value to PHY register for port lt portlist gt Port list address Register address 0 31 or Ox00 Ox1f value Register value to write 0 65535 or 0x0000 Oxffff Debug 5 Syntax Debug SetRegs clear lt address gt lt port_no gt lt value gt Description Saves user manual defined switch registers to EEPROM to make values persis tent or clears resets register values address Register address or Ox1b lt port_no gt Port number 0 25 lt value gt Register value to be stored WEB INTERFACE From the web interface it is possible to
111. 00 Value OEM 00 ID String Length Code c9 Table B 29 48V Source A Volt SDR Description KAT4000 Records Value Parameter Status Record ID 0016 gt SDR Version 51 Record Type 01 Full Sensor Record Record Length 48 4000 User s Manual 10007175 02 Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Sensor Owner ID 00 Sensor Owner LUN 00 Sensor Number 00 Entity ID 0a Entity Instance 60 Sensor Initialization 7f Init Scanning lnit Sensor Type Init Hysteresis B Init Thresholds Init Events Sensor Scanning enabled Event Generation enabled Sensor Capabilities 69 Ignore Sensor no Auto Re Arm enabled Sensor Hysteresis hysteresis is settable readable Sensor Threshold Access threshold is settable readable Event Message Control global disable only Sensor Type 02 Voltage Event Reading Type Code 01 Threshold Assertion Event Mask _ 4801 Lower Non Recoverable Threshold comparison returned Upper Non Recoverable Going High supported Lower Non Critical Going Low supported Deassertion Event Mask _ 4801 Lower Non Recoverable Threshold comparison returned Upper Non Recoverable Going High supported Lower Non Critical Going Low supported Discrete Reading Mask 3f3f Upper Non Recoverable Threshold settab
112. 0000 Ww CCSRBAR 8548 Registers 1 MB FC88 0000 Reserved FC80 0000 R W Socketed Flash if installed 512 KB 6 1 FC48 0000 Reserved 40 00 0 R W Clock Synchronizer Interrupt Register 3 CSI3 7 18 FC40 00AC R W Clock Synchronizer Interrupt Register 2 CSI2 7 18 FC40 00A8 R W Clock Synchronizer Interrupt Register 1 CSI1 7 18 FC40 00A4 R W Clock Control aTCA CLK3 B Register CCR14 7 17 FC40 00A0 R W Clock Control aTCA CLK3 A Register CCR13 7 17 FC40 009C R W Clock Control AMC4 CLK3 Register CCR12 7 17 FC40 0098 R W Clock Control AMC4 CLK2 Register CCR11 7 17 FC40 0094 R W Clock Control AMC4 CLK1 Register CCR10 7 17 FC40 0090 R W Clock Control AMC3 CLK3 Register CCR9 7 17 FC40 008C R W Clock Control AMC3 CLK2 Register CCR8 7 17 FC40 0088 R W Clock Control AMC3 CLK1 Register CCR7 7 17 FC40 0084 R W Clock Control AMC2 CLK3 Register CCR6 7 17 FC40 0080 R W Clock Control AMC2 CLK2 Register CCR5 7 17 FC40 007C R W Clock Control AMC2 CLK1 Register CCR4 7 17 FC40 0078 R W Clock Control AMC1 CLK3 Register CCR3 7 17 FC40 0074 R W Clock Control AMC1 CLK2 Register CCR2 7 17 FC40 0070 R W Clock Control AMC1 CLK1 Register CCR1 7 17 FC40 006C Reserved FC40 0068 R W Clock Synchronizer Secondary Source Register 3 CSS3 7 15 FC40 0064 R W Clock Synchronizer Secondary Source Register 2 CSS2 7 15 FC40 0060 R W Clock Synchronizer Secondary Source Register 1 CSS1 7 15 FC40 005C Reserved FC
113. 010203ABCDEF 01 02 03 AB CD EF or 01 02 03 AB CD EF portlist Port list Use none to specify no ports lt gt 1 VLAN ID 1 4095 Default 1 Syntax MAC Delete lt macaddress gt lt vid gt Description Delete MAC address and VLAN ID nacaddress MAC address 12 digit hex string optionally separated with dashes or colons e g 010203ABCDEF 01 02 03 AB CD EF or 01 02 03 AB CD EF vid VLAN ID Default 1 Syntax MAC Lookup lt macaddress gt lt vid gt Description Lookup MAC address and VLAN ID nacaddress MAC address 12 digit hex string optionally separated with dashes or colons e g 010203ABCDEF 01 02 03 AB CD EF or 01 02 03 AB CD EF lt vid gt VLAN ID 1 4095 Default 1 Syntax MAC Table lt vidlist gt Description Show MAC table for the VLAN IDs specified Since the list can be very long only the first 20 entries are shown lt vidlist gt VLAN ID list Syntax MAC Flush Description Removes non static MAC address table entries Syntax MAC Agetime lt agetime gt Description Set or show the MAC age timer in seconds The value zero disables aging agetime Age timer in seconds 0 or 10 65535 Default Show timer Syntax 10007175 02 KAT4000 User s Manual Appendix A serial Command Line Interface CLI VLAN Configuration VLAN Add VLAN Delete VLAN Lookup VLAN Aware KAT4000 User s Manual MAC Learning lt enab
114. 07175 02 CPLD Clock Synchronizer Registers Bit Input Source 01101 AMC3 CLK2 01110 AMC3 CLK3 01111 AMCA CLK1 10000 AMCA CLK2 10001 AMCA CLK3 10010 reserved 11111 reserved Clock Synchronizer Secondary Source Registers 1 3 CSS1 CSS3 The Clock Synchronizer Secondary Source registers define the input secondary source to thethree clock synchronizer devices Default is 0x01 for register 1 0x03 for register 2 and 0x05 for register 3 Register 7 18 Clock Synchronizer Secondary Source Registers 1 3 CSS 1 CSS3 at Oxfc40 0060 Oxfc40 0064 Oxfc40 0068 respectively 7 6 5 4 3 2 1 0 reserved SEC4 SEC3 SEC2 SEC1 SECO Default register values for CSS1 are shown in the following row 0 0 0 0 1 Default register values for CSS2 are shown in the following row 0 0 0 1 il Default register values for CSS3 are shown in the following row 0 0 1 0 1 R Reserved SEC4 0 Secondary Input Source Selection Bit Input Source 00000 aTCA A 00001 aTCACLK1B 00010 aTCA CLK2 A 10007175 02 KAT4000 User s Manual 7 15 CPLD Clock Synchronizer Registers Bit Input Source 00011 aTCA CLK2 B 00100 aTCA CLK3 A 00101 aTCA CLK3 B 00110 AMC1 CLK1 00111 CLK2 01000 CLK3 01001 AMC2 CLK1 01010 AMC2 CLK2 01011 AMC2 CLK3 01100 AMC3 CLK1
115. 1000Base BX SerDes Ethernet ports routed between the processor and the switch Up to two 1000Base BX SerDes Ethernet ports routed between each AMC site and the switch AMC 2 One 1000Base BX SerDes Ethernet port routed between the fat pipe switch module and the switch AMC 2 Four 1000Base BX SerDes Ethernet ports connected from the switch to the Update Channel interface on 20 on the backplane optional Two 1000Base BX SerDes Ethernet ports routed between the switch and Zone 3 Features of the switch include Layer 2 switching capable of running 26 GbE ports at full bit rate Layer 2 features implemented jumbo frames port mirroring quality of service and traffic shaping Automatic configuration to a user definable default state at power up these include non volatile Virtual Local Area Network VLAN table settings with the ability to modify in the field The configuration and management of the switch is done via the processor local bus In the no CPU configuration the on chip 8051 microprocessor controls configuration and management of the switch IEEE 802 10 and port based VLANs IEEE 802 1D spanning tree protocol and IEEE 802 3AD link aggregation control protocol See Fig 4 2 for a block diagram of the switch For more information reference the HawX 626 26 Port 10 100 1000 Managed Layer 2 Ethernet Switch VSC7376 Data Sheet Proprietary information on the Vitesse switch is not available in this user s manual Pl
116. 13 2 Descriptions and pin assign ments are listed below Console Serial Ports There are multiple asynchronous console serial ports on the face plate P1 is for the host serial port P2 is for the fat pipe serial port and P4 P7 are for AMC sites 1 4 These ports operate at EIA 232 signal levels but do not provide any handshaking functionality The con nectors for the console ports are micro DB9 connectors with the following pin assign ments Table 13 2 Console Serial Port Pin Assignments P1 P2 and P4 P7 Pin Signal Pin Signal 1 no connect 6 no connect 2 RXD Data In 7 no connect 3 TXD Data Out 8 no connect 4 no connect 9 no connect 5 ground The standard Emerson console cable 10007665 is cross pinned as shown in Fig 13 4 A straight through 9 pin cable 10007664 also is available Figure 13 3 Micro D Console Cable Micro D Connector Ferrite DB9 Connector Pin 1 10007175 02 KAT4000 User s Manual 13 5 Rear Transition Module setup Figure 13 4 Standard Console Cable Wiring 10007665 xx DB9 Connector Micro DB9 Connector Twisted Pair 9 8 7 6 5 4 5 2 1 SHELL Ethernet Port The face plate has one 10 100BASE T Ethernet port for debug purposes that routes through P30 to the GbE Core Switch This port is not functional with the no CPU KAT4000 configuration This is a standard RJ45 connector with the following pin assignments Table 13 3 Ethernet Po
117. 13 2 Console Serial Port Pin Assignments P1 P2 4 7 13 5 Table 13 3 Ethernet Port Pin Assignments 3 13 6 Table 14 1 Debug LED Codes 14 4 Table 14 2 POST Diagnostic Results Bit Assignments 14 6 Table 14 3 Monitor Address per Flash Device 14 7 Table 14 4 Static IP Ethernet 14 10 Table 14 5 DHCP Ethernet 14 11 Table 14 6 Standard Environment Variables 14 28 Table 14 7 Optional Environment 14 30 Table A 1 General Command Types A 5 Table B 1 Sensor Data Record Sean emcees B 1 Table B 2 KAT4000 IPMC SDR B 2 Table B 3 Hot Swap SDR Descriptions xen toes een B 2 Table B 4 IPMB Physical SDR 4 5 Watchdog SDR 5 6 3 3 Volt Description
118. 14 25 Reeve 14 15 14 25 14 16 14 25 2 Commands 14 16 TUN 2 4 14 26 eeprom 14 16 14 26 err RP 14 17 showmac MEME 14 26 iloop P a us 14 17 showpci I 14 26 14 17 d 14 26 imd2 14 17 switch reg EE 14 27 Imm vee eee ee eee nnn nnn 14 17 14 27 2 14 17 14 27 14 18 Environment Variables 14 28 14 18 Troubleshooting 14 31 14 18 Download 14 32 iprobe2 14 18 14 32 14 18 Motorola S Record 14 32 Commands 14 18 Li ane NEA 14 18 1419 15Acronym List fr led 14 19 PCW cese rr RR re err RR 14 19 SESON 14 19 16 Appendix Environment Parameter Commands 14 20 No CPU 4000 A 1 KAT4000 User s Manual 10007175 02 Contents continued Ethernet Switch Configuration 2 VLAN Commands 12 Default Switch Configuration 2 Aggregation Trunking
119. 18 zone 1 3 12 1 KAT4000 User s Manual 10007175 02 Notes 10007175 02 KAT4000 User s Manual AC Power Systems Embedded Power Precision Cooling Emerson Network Power The global leader in enabling Connectivity Integrated Cabinet Solutions Services Business Critical Continuity DC Power Systems Outside Plant Site Monitoring Embedded Computing Power Switching amp Controls Surge amp Signal Protection Emerson Network Power Embedded Computing Business Critical Continuity Emerson Network Power and the 8310 Excelsior Drive Madison WI 53717 1935 USA Emerson Network Power logo are trademarks and US Toll Free 1 800 356 9602 Voice 1 608 831 5500 FAX 1 608 831 4249 service marks of Emerson Electric Co 2006 Emerson Electric Co Email info artesyncp com www artesyncp com EMERSON CONSIDER IT SOLVED
120. 1_RXD 31 GND 32 Bn_SATA1_TXD 33 _ Bn_SATA1_TXD 34 GND 235 Bn_SATA2_RXD 36 Bn SATA2 RXD 237 _38 Bn SATA2 TXD 39 SATA2 TXD 40 GND 41 _ 42 12V 43 GND 44 AMCn_RXD4 45 _ AMCn_RXD4 46 GND 47 AMCn TXD4 48 AMCn_TXD4 49 GND 250 _ 5 51 _ 5 52 GND 53 AMCn_TXD5 54 AMCn_TXD5 55 GND 56 Bn_SCL 57 12V 258 GND 59 AMCn_RXD6 60 AMCn_RXD6 61 GND 62 AMCn_TXD6 63 AMCn_TXD6 64 GND 65 _ 7 66 _ 7 g KAT4000 User s Manual 10007175 02 AMC Sites Pin Assignments Pin 1 4 Signal Pin B1 B4 Signal 67 GND 68 _ 7 69 TXD7 70 GND 7 Bn SDA 72 12V 73 GND 74 Bn_CLK1 75 Bn_CLK1 76 GND 7 Bn_CLK2 278 CLK2 79 GND 80 Bn_CLK3 81 Bn CLIG 82 83 84 12 85 GND 866 CND 87 EXPn_B_TX4 88 EXPn_B_TX4 89 _ 90 EXPn_B_RX4 91 EXPn B RX4 92 GND 93 EXPn B TX5 94 EXPn_B_TX5 95 _ 96 _ _ 5 97 EXPn B RX5 98 GND 99 EXPn B TX6 100 B TX6 10 GND 102 EXPn B RX6 103 EXPn B RX6 104 GND 105 EXPn_B_TX7 106 EXPn_B_TX7 17 GND 108 B RX7 109 B RX7 2110 GND 111 Bn_CONSOLE_RX 112 Bn_CONSOLE_TX 113 GND 114 Bn_LEDCTRL_RX _115 Bn_LEDCTRL_TX
121. 4 Pigeon Point Systems 4 If the payload responds before the payload communication time out the diagnostic interrupt return code is forwarded to the shelf controller as the completion code of the FRU Control command response Otherwise the completion code is returned Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Get Payload Shutdown Time Out Command When the shelf manager commands the IPMC to shut down the payload i e sends the Set Power Level 0 command the IPMC notifies the payload by asserting an appropriate alert and sending an alert notification to the payload Upon receiving this notification the pay load software is expected to initiate the payload shutdown sequence After performing this sequence the payload should send the Graceful Reset command to the IPMC over the Pay load Interface to notify the IPMC that the payload shutdown is complete 10007175 02 System Management vendor Commands To avoid deadlocks that may occur if the payload software does not respond the IPMC pro vides a special time out for the payload shutdown sequence If the payload does not send the Graceful Reset command within a definite period of time the IPMC assumes that the payload shutdown sequence is finished and sends a Module Quiesced Hot Swap event to the KAT4000 controller Table 9 25 Get Payload Shutdown Time Out Command Type Byte Request D
122. 40 0058 R W Clock Synchronizer Primary Source Register 3 CPS3 7 14 FC40 0054 R W Clock Synchronizer Primary Source Register 2 CPS2 7 14 FC40 0050 R W Clock Synchronizer Primary Source Register 1 CPS1 7 14 FC40 004C Reserved FC40 0048 R W Clock Synchronizer Control Register 3 CSC3 7 13 FC40 0044 R W Clock Synchronizer Control Register 2 CSC2 7 13 FC40 0040 R W Clock Synchronizer Control Register 1 CSC1 7 13 10007175 02 KAT4000 User s Manual Overview Physical Memory Physical Access See Page Address hex Mode Description continued FC40 003C R W RTM GPIO Control Register RGCR 7 7 FC40 0038 R RTM GPIO State Register RGSR 7 6 FC40 0034 R W MISC Control PCle SIO Test Clock Register MISC 7 7 FC40 0030 R Boot Device Redirection Register BDRR 7 12 FC40 002C R W Scratch Register 1 SCR1 7 8 FC40 0028 Reset Command Register 2 RCR2 7 10 FC40 0024 Reset Command Register 1 RCR1 7 9 FC40 0020 R Reset Event Register RER 7 9 FC40 001C R W LED Control Register LEDR 7 5 FC40 0018 R Jumper Settings Register JSR 7 6 FC00 0014 Reserved FC40 0010 R Hardware Configuration Register 0 HCRO 7 4 FC40 000C R W PLL Configuration Register PLLC 7 4 FC40 0008 PLD Version Register PVR 7 3 FC40 0004 Hardware Version Register HVR 7 3 FC40 0000 Product ID Register PIDR 7 2 FC18 0000 Reserved FC14 0000 R W Fat Pipe Ethernet Switch Registers if installed
123. 4000 User s Manual 14 7 Monitor Monitor Command Reference KAT4000 User s Manual Optionally save your settings KAT4000 1 0 gt saveenv TFTP the new monitor binary image to memory location 0x100000 KAT4000 1 0 gt tftpboot 100000 path to file on tftp server Update the monitor KAT4000 1 0 gt moninit serial number 100000 If moninit fails burn the new monitor to a ROM and follow the recovery steps in the Recovering the Monitor section MONITOR COMMAND REFERENCE This section describes the syntax and typographic conventions for the KAT4000 monitor commands Subsequent sections in this chapter describe individual commands which fall into the following categories boot memory Flash environment variables test and other commands Command Syntax The monitor uses the following basic command syntax Command argument 1 argument 2 argument 3 The command line accepts three different argument formats string numeric and symbolic All command arguments must be separated by spaces with the exception of argument flags which are described below Monitor commands that expect numeric arguments assume a hexadecimal base All monitor commands are case sensitive Some commands accept flag arguments A flag argument is a single character that begins with a period There is no white space between an argument flag and a command For example md b 80000 is a valid monitor command while md
124. 4000 User s Manual Bm Connectors 7 2 Pin 13 14 15 16 17 ZONE 2 Signal IPMBA Clock SCL port A IPMBA Data SDA port A IPMBB Clock SCL port B IPMBB Data SDA port B no connect no connect no connect no connect no connect no connect no connect no connect Shelf ground Logic ground Enable B Voltage Return A 48RTNA Voltage Return B 48RTNB 48 volt Early A 48 volt Early B Enable A 48 volt A 48A 48 volt B 48B Insertion Sequence third third third third third third third third third third third third first first fourth first first first first fourth second third Zone 2 ZD defines five backplane connectors 20 through J24 which support the data transport interface The KAT4000 is a Base node board supporting two Base channels therefore only the J23 connector is installed to support the 10BASE T and or 100BASE TX and or 1000BASE T Ethernet Connector 20 is also used for the optional Update Channel and synchronization clock interface Each connector provides 40 differential signal contact pairs with each pair carrying an individual L shaped ground contact The ZD style connec tor provides three levels of sequential mating the third and shortest signal level is not used with PICMG 3 0 backplanes The Zone 2 connector array supports four different interfaces to the ATCA backplane Base Node Interface J23 supports two Base channels Fabri
125. 6 reserved 5 OEM 4 SMS OS 3 OS Load 2 Monitor POST 1 Monitor FRB 2 0 reserved 10007175 02 System Management FRU LEDs Type Response Data continued FRU LEDS Byte 6 7 8 DataField continued Initial countdown value Isbyte 100 ms count Initial countdown msbyte Present countdown value Isbyte The initial countdown value and present countdown values should match immediately after the countdown is initialized Set Watchdog Timer command and after a Reset Watchdog Timer has been executed Note that internal delays in the IPMC may require software to delay up to 100 ms before seeing the countdown value change and be reflected in the Get Watchdog Timer command Present countdown value msbyte This section describes the front panel LEDs controlled by the IPMC and documents how to control each LED with the standard FRU LED commands Reference the PICMG 3 0 Revision 2 0 AdvancedTCA Base Specification for more detailed information The KAT4000 has four Light Emitting Diodes LEDs on the front panel See Fig 2 3 for their location Table 9 34 FRU LEDs LEDs Hot Swap 005 ID hex Reference Designator CR2001 Description The blue Hot Swap LED displays four states On the board can be safely extracted Off the board is operating and not safe for extraction Long blink insertion is in progress Short blink requesting permission for extraction The Out Of Ser
126. 7 GE5 AMC2 port4 2 port 5 GET _ AMC 2 port 6 _ AMC2 port 7 _ 9 3 port 4 GE10 AMC3 port 5 AMC3port6 _ 12 AMC3 port 7 AMC4 port 4 4 AMCA port 5 GE15 AMC4port6 GE16 AMC 4 port 7 E KAT4000 User s Manual 10007175 02 Fat Pipe Switch Module 10 GbE 1 GbE Fat Pipe Switch Module PEX 8111 PCle to PCI Bridge The BCM56580 switch is managed by the PCle connection from the MPC8548 via the PEX8111 bridge chip The PCle to PCI bridge supports forward and reverse transparent bridging between the PCle and PCI buses The bridge s PCI Express port has a single x1 link with a maximum throughput of 250 MB sec per transmit and receive direction The PEX 8111 is compliant with the PCI Local Bus Specification rev 3 0 the PCI to PCI Bridge Archi tecture Specification rev 1 1 the PCI Express Base Specification rev 1 0a and the PCI Express to PCI PCI X Bridge Specification rev 1 0 For more information about this bridge reference the PEX 8111 ExpressLane PCI Express to PCI Bridge Data Sheet at www plx tech com PLD ThePLD is the interface between the local bus the BCM56580 switch and the PEX 8111 PCle to PCI bridge It contains registers for fat pipe module control For more information see 10 GbE 1 GbE Fat Pipe Switch Module PLD SPI SROM The 128 Kb EEPROM is used to store PEX 8111 bridge configuration informatio
127. 7 Init Scanning Init Sensor Type Init Events Sensor Scanning enabled Event Generation enabled Sensor Capabilities 41 Ignore Sensor no Auto Re Arm enabled Sensor Hysteresis no hysteresis Sensor Threshold Access no threshold Event Message Control global disable only Sensor Type 10 Event Reading Type Code 6f Sensor Specific Assertion Event Mask OOff Deassertion Event Mask 0000 Discrete Reading Mask ooff Sensor Units 1 00 Analog Data Format unsigned Rate Unit none Modifier Unit none Percentage no Sensor Units 2 Base Unit 00 Unspecified Sensor Units 3 Modifier Unit 00 Unspecified Linearization 00 00 M Tolerance 00 B 00 B Accuracy 00 Accuracy Accuracy Exp 00 R exp B Exp 00 Analog Characteristic Flags 00 Nominal Reading 00 Normal Maximum 00 Normal Minimum 00 Sensor Maximum Reading 00 Sensor Minimum Reading 00 Upper Non Recoverable 00 ES Threshold Upper Critical Threshold 00 E Upper Non Critical Threshold 00 Lower Non Recoverable 00 Threshold 10007175 02 KAT4000 User s Manual Appendix B sensor Data Records KAT4000 Records Lower Critical Threshold Lower Non Critical Threshold Positive Going Threshold Hyst Parameter Status continued Value Negative Going Threshold Hyst 00 Value OEM 00 ID String Length Code Table 4 Physical SDR Description
128. A 13 Appendix A serial Command Line Interface CLI Aggregation Mode Description Lookup and display link aggregation group portlist Port list Aggregations including any of the ports will be shown Syntax Aggr Mode smac dmac xor Description Set or show link aggregation traffic distribution mode smac xor Aggregation mode SMAC DMAC or XOR Default Show mode User Group Commands User groups provide a way other than VLANs for making port groupings With user groups it is possible to share a port between more user groups User Group Configuration User Group Add User Group Delete User Group Lookup QoS Configuration 4000 User s Manual Syntax User Group Configuration Description Show the user groups Syntax User Group Add lt grouplist gt lt portlist gt Description Add user group entry including the ports grouplist User group ID list lt portlist gt Port list Default All ports Syntax User Group Delete lt grouplist gt Description Delete user group entry lt grouplist gt User group ID list Syntax User Group Lookup lt grouplist gt Description Lookup user group entry and show port members lt grouplist gt User group ID list QoS Commands Syntax QoS Configuration lt portlist gt 10007175 02 Appendix A serial Command Line Interface CLI QoS Mode QoS Default QoS Tagprio QoS DiffServ QoS Us
129. AG 1 7 19 GPIN LED Register 5 20 10 GbE 10 GbE Fat Pipe Switch Module5 21 sRIO Fat Pipe Switch Module 5 22 AMC Sites Connectors 8 2 H 5 sioniste 8 2 Configuration Pin 8 4 Boot Memory Configuration 6 1 SATA 8 6 User Flash celo eri 6 1 On Card SDRAM 6 2 NAND 6 2 NVRAM Allocation 6 3 System Management IPMC Overview 9 1 9 3 CPLD IPMI Completion Codes 9 4 IPMB 9 5 PLD Register Summary 7 1 SIPL Protocol 9 6 Version and ID Registers 7 2 Message 9 7 Product ID Register PIDR 7 2 Stimndardicemiands 9 9 Hardware Version Register HVR 7 3 Vendor Commands 9 12 PLD Version Register PVR 7 3 Get Status Command 9 12 Configuration Registers 7 4 Get Serial Interface Properties Hardware Configuration Register 0 9 14 HCRO 47444 7 4 Set Serial Interface Properties PLL Configuration Register PLLC 7 4 9 15 Miscellaneo
130. AMC 4 200MHz 100 MHz TCLKA TCLKB FCLKA 1 lt 200 MHz 100 MHz TCLKA TCLKB FCLKA AMC2 lt 200MHz 100 MHz TCLKA TCLKB FCLKA or Y Clock Transceiver PCle REFCLK Distribution U PCle Clock Source PLD Wrapper Three Frequency 3 s Output Paths 19 44 MHz 2 1 54 MHz Processor Clock Clock 8 2 048 MHz Interface Selection 1 Selection 2 via Local Bus Primary and Secondary Clock Inputs E key Enable from Processor ATCA J20 FCLKA is either a PCle REFCLK or standard clock signal 10007175 02 KAT4000 User s Manual m Synchronization Clocks 9045 and MT9046 Clock KAT4000 User s Manual All clock circuitry and the synchronization clock interface meets all hard requirements as stated in the latest PICMG3 0 and AMC O specifications as well as those in all relevant AMC subspecifications e Backplane CLK1A B and CLK2A B inputs are Stratum Level 4E and Stratum Level 3 or sources respectively from the main system clock source There are no specific Stratum level requirements for the on board output clocks that may be driven from these Stratum level input clocks Backplane CLK3A B output is selectable as 8 kHz 1 544 MHz 2 048 MHz or 19 44 MHz Backplane CLK3A B is a derived REF clk and has no specific Stratum level quality requirements Backplane clock interfaces are designed to work within the specified bused M LVDS ele
131. AT 0 05 5 19 Register 5 15 Switch GPIO Register at 0 06 5 19 Register 5 16 GPIN LED Register GPLED 0 07 5 20 Register 7 1 Product ID Register at 40 0000 7 2 Register 7 2 Hardware Version Register at Oxfc40 0004 7 3 Register 7 3 Version Register PVR at 40 0008 7 3 Register 7 4 Hardware Configuration Register 0 HCRO at 0 40 0010 7 4 Register 7 5 Configuration Register PLLC at Oxfc40 000c 7 4 Register 7 6 LED Control Register LEDR at 40 001 7 5 Register 7 7 Jumper Settings Register JSR at 40 0018 7 6 Register 7 8 GPIO State Register RGSR at Oxfc40 0038 7 6 Register 7 9 GPIO Control Register RGCR at 0 40 003 7 7 Register 7 10 MISC Control Register MISC at 40 0034 7 7 Register 7 11 Scratch Register 1 SCR1 at 40 002 7 8 Register 7 12 Reset Event Register at 40 0020 7 9 Register 7 13 Reset Command
132. AT4000 User s Manual CONFIGURATION REGISTERS Hardware Configuration Register 0 HCRO The read only Hardware Configuration 0 register indicates various settings of the particular product configuration The values of these bits are defined by strapping resistors Default register values are configuration dependent Hardware Configuration Register 0 HCRO at Oxfc40 0010 7 6 5 4 3 2 1 0 reserved BDR reserved CF1 CFO DDRF Reserved BDR Enable 1 Enable boot redirect circuitry 0 Disable boot redirect circuitry CCB and Core Frequencies MHz Bits 2 0 CCB Core 000 400 800 001 533 800 010 400 1000 011 533 800 100 400 1200 101 533 1333 110 reserved 111 reserved PLL Configuration Register PLLC The PLL Configuration register indicates PLL settings for the MPC8548 processor The initial values of these bits are defined by strapping resistors The values can be overwritten by software Default register values are configuration dependent PLL Configuration Register PLLC at Oxfc40 000c 7 6 5 4 3 2 1 0 R CORE2 COREO SYS3 SYS2 SYS1 SYSO Reserved 10007175 02 CPLD Miscellaneous Registers CORE2 0 SYS3 0 Register 7 6 CPUR CPUG Core CCB PLL Ratio 000 Reserved 001 Reserved 010 Reserved 011 3 2 100 Reserved 101 52 110 3 1 111 Reserved System CCB PLL Ratio 0000 16 1 1100 12 1 All oth
133. America or yellow Europe When lit this LED indicates the KAT4000 is in failed state The blue Hot Swap LED CR2001 displays four states On the board can be safely extracted Off the board is operating and not safe for extraction Long blink insertion in progress Short blink requesting permission for extraction Do not remove the KAT4000 while the blue LED is blinking Reference the PICMG 3 0 Revision 2 0 AdvancedTCA Base Specification for more detailed LED information 10007175 02 it Board 4000 Ci Setup m 5 E 2 0 5 ait lov lt E 55 Ag nn e qe Soa _ _ 59 1 ov lt 95 529E 2 Lov B T 9 E 3543 5 anw 2102 anes AO L EB AZ L a ol H LNO 41532 Ndd AS c gig EB 331039 13235 Ac c 8 131N334D 2 edid BI asad peoj e 331 Dis 2 gt 100g NT vzce IM 037 014 135 NT 7258 Silii 2 vcse BD Bug 1331 Bl NIS jane vad NT vzs
134. Authority International Electrotechnical Commission Input Output Intelligent Plattorm Management Bus Intelligent Plattorm Management Controller Intelligent Plattorm Management Interface In system Programmable Interrupt Vector Offset Register Joint Test Action Group Light emitting Diode 10007175 02 KAT4000 User s Manual Acronym List continued 52 KAT4000 User s Manual LPC LUN MAC MMC NEBS netFn OEM OS PCI PCle PHY PLD POST RMA RMII RTC RTM SATA SDR SDRAM SEL SERDES SGMII SMC SO DIMM SPI sRIO SROM TBD TDM UART UL USB XAUI Low Pin Count Logical Unit Number Medium media Access Control controller Module Management Controller Network Equipment Building System Network Function Code Original Equipment Manufacturer Operating System Peripheral Component Interconnect PCI Express Physical Interface Programmable Logic Device also known as FPGA CPLD EPLD Power on Self Test Return Merchandise Authorization Reduced Media Independent Interface Real Time Clock Rear Transition Module Serial ATA Sensor Data Record Synchronous Dynamic Random Access Memory System Event Log Serializer Deserializer Serial Gigabit Media Independent Interface Serial Management Channel Small Outline Dual In line Memory Module Serial Peripheral Interface Serial Rapid IO Serial Read Only Memory To Be Determined Time Division Multiplexed Universal Asynchronous Receiver Transmitter Underwriters Labora
135. B i tote RB oR Lir nr H i8 LN 8 F8 Fuse optional ru H for 2 5 Volt Supply to P1 COP JTAG 0 75A E d MES EL for 3 Volt Supply to P1 COP JTAG 0 75A B a AAAA DBB cr ai a al E KAT4000 User s Manual 10007175 02 Setup KAT4000 Circuit Board JTAG Interfaces The KAT4000 provides the capability for JTAG type boundary scan testing The IPMC con trols the two JTAG interfaces hubs see Fig 2 6 JTAG hub is connected to the fat pipe switch module two PLDs and the four AMC sites The other hub is connected to the Ether net core switch the PCI Express switch the processor the GbE PHYs and the synchroniza tion clock circuitry See Fig 2 4 and Fig 2 5 for the location of individual headers Figure 2 6 Hubs AMC 1 IPMC GPIO Master Port 2 Master Port 2 SCANSCA112 SCANSCA112 JTAG 5 ti Multiplexer PEX8524 ultiplexer Port 0 Port 3 ap AE PCI Express Switch E A VSC7376 Port 4 thernet Core Switch Layer 2 MPC8548 99 Fat Pipe Processor Switch Module P1 The 16 pin TAG COP P1 header is provided for debug purposes for the processor This inter face provides for boundary scan testing and COP debugger support of the CPU see Fig 3 2 and is compliant with the IEEE 1149 1 standard The header pin assignments are defined in Table 3 6 Caution Install a shunt on JP1 pins
136. Blue 2h Use Red 3h Use Green 4h Use Amber 5h Use Orange 6h Use White 7h Dh Reserved Eh Do not change Fh Use default color Response 1 Completion Code 2 PICMG Identifier indicates that this is a PICMG defined group extension command Use value 00h 10007175 02 KAT4000 User s Manual 9 37 System Management FRU LEDs Get FRU LED State Command The Get FRU LED State command allows the state of the FRU LEDs to be controlled by the management system Table 9 38 Get FRU LED State Command Type Byte Data Field Request Data 1 PICMG Identifier indicates that this is a PICMG defined group extension command Use value 00h 2 FRU Device ID 3 LED ID 00h Blue LED Hot Swap 01h LED 1 005 02h LED 2 03h LED 3 04h FEh OEM defined LEDs FFh Reserved ResponseData 1 Completion Code 2 PICMG Identifier indicates that this is a PICMG defined group extension command Use value 00h 3 LED States Bits 7 3 Reserved set to 0 Bit 2 1b if Lamp Test has been enabled Bit 1 1b if override state has been enabled Bit 2 1b if IPMC has a Local control state 4 Local Control LED Function 00h LED is off default if Local Control not supported 01h FAh LED is blinking Off duration specified by this byte on duration specified by byte 5 in tens of milliseconds FBh FEh Reserved FFh LED is on 5 On Duration LED on time is measured in tens of milliseconds Lamp Test time in hundreds of milliseconds if by
137. Central Processing Unit Microprocessor Core 500 Poll L2CR L21 until itis cleared Enable the L2 cache for normal operation and then set the L2CR L2E Timer Counter Each of the four 32 bit wide timer counters can be selected to operate as a timer or a counter Each timer counter increments with every TCLK rising edge In counter mode the counter counts down to terminal count stops and issues an interrupt In timer mode the timer counts down issues an interrupt on terminal count reloads itself to the programmed value and continues to count Reads from the counter or timer are completed directly from the counter and writes are to the timer counter register PCI Device and Vendor ID Assignment The KAT4000 has been assigned the following PCI identification number Table 3 2 PCI Device and Vendor ID Vendor ID Device ID Description 0 1223 0x001B Reported by the PCI bridge The KAT4000 sets the PCI revision ID to the hardware version number located in the CPLD s Hardware Version register Register Map 7 2 L2 Control Register L2CR Register 3 1 L2 Control Register L2CR 0 1 2 3 4 5 6 8 9 10 11 12 13 15 L2E 121 12512 reserved L2 1210 R L2IN L2SRAM DO TDIS 16 17 18 19 20 21 22 23 24 27 28 29 30 31 reserved L2 L2 R L2LF L2LFRID reserved L2STA R L2STASH LO SLC R SHDIS 12 12 Enable enables L2 cache or memory mapped SRAM L2 array 0 L2array disabled 1 12 array enabled
138. Component Map Bottom Rev 01 10007175 02 KAT4000 User s Manual 5 13 Fat Pipe Switch Module 10 GbE 1 GbE Fat Pipe Switch Module Components and Features The following is a summary of the 10 GbE 1 GbE fat pipe switch module hardware compo nents and features BCM56580 10 GbE 1 GbE Switch The Broadcom BCM56580 is a Layer 2 and 3 network switch with sixteen GbE ports and four 10 GbE ports The switch uses integrated XAUI SerDes for the 10 GbE ports to the ATCA fab ric channels and a single SerDes lane for each 1 GbE port to the AMC modules complying with the CX 4 and PICMG 3 1 standards Table 5 2 defines connectivity for the switch s ports when the fat pipe module is installed on the KAT4000 For more information about this switch reference the BCM56580 16 Port 2 5 GbE Multilayer Switch with Four 10 GbE HiGig Ports Data Sheet at www broadcom com Table 5 2 56580 Switch Ports 10 GbE 1 GbE Switch Port Connection XG1 Fabric Channel 1 FC1 ports 0 3 X02 _ Fabric Channel 2 FC2 ports 0 3 XG3 Reserved 00 CPU or Core Switch build time configured option 1 GbE only GET AMClport4 GE2 AMC 1 port 5 BEN _ AMC 1 port 6 __ 4 AMC 1 port
139. D 000d SDR Version 51 Record Type or Full Sensor Record E Record Length 36 _ Sensor Owner ID _ 00 _ Sensor Owner LUN 00 Sensor Number 00 Entity ID c1 AMC Module Entity Instance 65 10007175 02 KAT4000 User s Manual Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Sensor Initialization 67 Init Scanning Init Sensor Type Init Events Sensor Scanning enabled Event Generation enabled Sensor Capabilities 41 Ignore Sensor no Auto Re Arm enabled Sensor Hysteresis no hysteresis Sensor Threshold Access no threshold Event Message Control global disable only Sensor Type 10 Event Reading Type Code ef Sensor Specific Assertion Event Mask OOff Deassertion Event Mask 0000 Discrete Reading Mask OOff Sensor Units 1 00 Analog Data Format unsigned Rate Unit none Modifier Unit none Percentage no Sensor Units 2 Base Unit 00 Unspecified Sensor Units 3 Modifier Unit 00 Unspecified Linearization 00 M 00 M Tolerance 00 B 00 B Accuracy 00 Accuracy Accuracy Exp 00 00 Analog Characteristic Flags 00 Nominal Reading 00 Normal Maximum 00 Normal Minimum 00 Sensor Maximum Reading 00 Sensor Minimum Reading 00 Upper Non Recoverable 00 Threshol
140. E Address Broadcast Enable for dcbf dcbst dcbi dcbic icbic mbar msync tlbsync 0 Disable address broadcasting for cache and TLB control operations 1 Enable address broadcasting for cache and TLB control operations INTERRUPTS AND EXCEPTION PROCESSING The interrupt process begins when an exception occurs The MPC8548 e500 core processes three types of interrupts machine check critical or noncritical Each interrupt type has separate control and status register sets as listed in the following priority Machine Check highest priority Machine Check Save and Restore registers MCSRRO MCSRR1 save state when they are taken and use rfmci instruction to restore state The machine check enable bit MSR ME can mask these interrupts E KAT4000 User s Manual 10007175 02 Central Processing Unit Interrupts and Exception Processing Noncritical The processor is able to change program flow to handle conditions generated by external signals errors or unusual conditions The Save and Restore registers SRRO SRR1 save state when they are taken and use the rfi instruction to restore state The external interrupt enable bit MSR EE can mask these asynchronous interrupts Critical The Critical Save and Restore registers CSRRO CSRR1 save state when they are taken dur ing a noncritical interrupt or regular program flow and use the rfci instruction to restore state The critical enable bit MSR CE can mask these interrupts This interrupt
141. Firmware Upgrade Backup Revision Command The Firmware Upgrade Backup Revision command reads the revision of the backup firm ware images stored in the master H8S flash memory When the Boot Loader receives this command it validates the checksums of the backup firmware images of the master and slave H8Ss If either of the images is corrupted the checksum is bad the OxCB Requested Data Not Present completion code is returned Otherwise the Boot Loader extracts the major and minor revision of the backup firmware and returns them This command is only supported by the Boot Loader If the IPMC firmware receives this command it sends a reply with the OxC1 Invalid Command completion code Firmware Upgrade Backup Revision Command Type Byte Data Field Request Data 1 Checksum Response Data 1 Completion Code 2 3 Major and Minor Revisions of the backup firmware Firmware Upgrade Termination The Boot Loader exits the upgrade mode upon an explicit request the Firmware Upgrade Complete command from the upgrade initiator Additionally the Boot Loader tracks the traffic coming from the firmware upgrade initiator and if the upgrade data channel has been idle for more than a configurable amount of time the Boot Loader closes the current upgrade session and reverts to the normal mode This ensures that the Boot Loader does not get stuck if the upgrade initiator accidentally loses its connection to the KAT4000 or shelf or does not communicate for a
142. Fixed 1000BASE BX Link Grouping ID 00h Independent Channel Link Designator 000101000001b Port 0 Enabled Fabric Interface Channel 2 Link Type 01h PICMG 3 1 Ethernet Fabric Interface Link Type Extension 0000b Fixed 1000BASE BX Link Grouping ID 00h Independent Channel Link Designator 111110000001b Port 3 2 1 0 Enabled Update Channel Interface Channel 1 Link Type 01h OEM Specific Link Type Extension 0000b Link Grouping ID 00h Independent Channel Carrier Point to Point Connectivity The KAT4000 supports one 1000BASE BX port on AMC port 0 of AMC site B2 B3 and B4 The KAT4000 supports either 1000BASE BX or PCle x1 on AMC port 1 of AMC sites B1 B2 B3 and B4 depending on the configuration 10007175 02 System Management Firmware Upgrade Table 9 43 Table 9 44 FIRMWARE UPGRADE The IPMC firmware upgrade is performed using a set of special upgrade request and reply messages that are delivered to and from the IPMC in the same way as standard IPMI com mands for more information refer to Intelligent Platform Management Bus Communication Protocol specification These upgrade commands are collectively referred to as the Upgrade protocol in this specification All upgrade commands have the net function codes 08h 09h that are reserved by the IPMI specification for firmware upgrade commands Each upgrade request is protected with a checksum that helps to validate the upgrade requests in case they are delivered to the IP
143. IPMC WATCHDOG TIMER COMMANDS The IPMC implements a standardized Watchdog Timer that can be used for a number of system time out functions by System Management Software SMS or by the monitor Set ting a time out value of zero allows the selected time out action to occur immediately This provides a standardized means for devices on the IPMB to perform emergency recovery actions IPMC Watchdog Timer Commands Command See Page Optional Mandatory Reset Watchdog Timer 9 29 M Set Watchdog Timer 9 29 M Get Watchdog Timer 9 31 M Watchdog Timer Actions The following actions are available on expiration of the Watchdog Timer System Reset System Power Off The System Reset and System Power Off on time out selections are mutually exclusive The watchdog timer is stopped whenever the system is powered down A command must be sent to start the timer after the system powers up Watchdog Timer Use Field and Expiration Flags The watchdog timer provides a timer use field that indicates the current use assigned to the watchdog timer The watchdog timer provides a corresponding set of timer use expira tion flags that are used to track the type of time out s that had occurred The time out use expiration flags retain their state across system resets and power cycles as long as the IPMC remains powered The flags are normally cleared solely by the Set Watchdog Timer command with the exception of the don t log flag which is
144. Implementation B4 B3 B2 B1 sRIO Fat Pipe Switch Module Implementation AMC to AMC Implementation of Ports 8 11 10 1 GbE Fat Pipe Switch Module Implementation 10 10 GbE Fat Pipe Switch Module Implementation 10007175 02 sRIO x1 KAT4000 User s Manual Overview Additional Information Clocks Common Options Fat Pipes Extended Options x1 x2 x4 Table 1 2 KAT4000 User s Manual This region supports a subset of the clock architecture as defined in the 0 specifica tion This region supports essential interfaces that are common across multiple Fat Pipe imple mentations This region supports data path connections including GbE sRIO PCle and 10 GbE It can carry large amounts of data without significantly degrading the speed of transmission This region supports Rear Transition Modules Also it may be used to extend the Common Options and Fat Pipes Regions when required This refers to the link width of the port the number of lanes that can be used to intercon nect between two link partners ADDITIONAL INFORMATION This section lists the KAT4000 hardware regulatory certifications and briefly discusses the terminology and notation conventions used in this manual It also lists general technical references Mean time between failures MTBF has been calculated at greater than 315 816 hours for the KAT4000 and greater than 264 795 hours for the KAT4000 with a GbE fat pipe s
145. Intel Corp Hewlett Packard Co NEC Corp Dell Computer Corp Rev 1 0 Feb 12 2004 IPMB Intelligent Platform Management Bus Communications Protocol Specification v1 0 Intel Corp Hewlett Packard Co NEC Corp Dell Computer Corp Rev 1 0 Nov 15 1999 IPMI Platform Management FRU Information Storage Definition v1 0 Intel Document Revision 1 1 Sept 27 1999 http www intel com design servers ipmi spec htm Renesas 16 Bit Single Chip Microcomputer Hardware Manual 85 2168 Group Renesas Technology Corp Rev 3 00 March 12 2004 http www renesas com SCANSTA112 7 port Multidrop IEEE 1149 1 JTAG Multiplexer Data Sheet National Semiconductor Corp DS200512 May 2004 http www national com PCI Express Base Specification Revision 1 0 PCI Special Interest Group PCI SIG July 22 2002 http www pcisig com PEX 8524 Versatile PCI Express Switch Preliminary Data Book PLX Technology Inc Version 0 99 June 2005 http www plxtech com Serial Access Timekeeper M41T00 ST Microelectronics June 2004 http www st com 512MB 64Mx72 DDR2 SDRAM Unbuffered SO DIMM ECC Product Specification Virtium Technology Inc Part Number VL491T6553B D5 CC Rev 1 3 August 2005 http www virtium com TIA EIA 232 F Interface Between Data Terminal Equipment and Data Circuit Terminating Equipment Employing Serial Binary Data Interchange Electronic Industries Association October 1997 http www eia co
146. L Lock Loss Interrupt Clear write only Setting 1 the bit clears interrupts 10007175 02 CPLD Interface HPI PPI Holdover and PLL Lock Loss Pending Interrupt read only 1 Interrupt latched 0 Nointerrupt latched HS PS Holdover and PLL Lock Loss Status read only 1 Indicates synchronizer in holdover PLL lock loss state 0 Indicates synchronizer not in holdover PLL locked JTAG INTERFACE The KAT4000 provides a single 10 pin JTAG header JP3 for in system programming of on board PLDs as well as Altera PLDs on AMC site 1 see Fig 7 2 The header pin assignments are defined in Table 7 2 Table 7 2 PLD Pin Assignments Pin Description Pin Description 1 Test Clock Input TCK 2 ground 1 3 Test Data Output TDO 4 3 3 volts 5 Test Mode Select TMS 6 not connected 7 not connected 8 not connected 9 Test Data Input TDI 10 ground 2 10007175 02 KAT4000 User s Manual 7 19 CPLD Interface Figure 7 2 PLD JTAG Diagram Master Port 2 SCANSCA112 Multiplexer Port 0 Port 3 Fat Pipe Switch Module JP1 is the configuration header for PLD programming Installing a shunt on jumper JP1 pins 1 2 enables the JP3 PLD programming header The header pin assignments are defined in Table 7 3 Table 7 3 JP1 Pin Assignments Shunt Description 1 2 TRANS Enable programming via header enables CPU JTAG COP access 3 4 LSBSELO Select KSL PLD
147. LATION To avoid damaging the module and or baseboard do not force the module onto the baseboard Use proper static protection and handle KAT4000 boards only when absolutely necessary Always wear a wriststrap to ground your body before touching a board Keep your body grounded while handling the board Hold the board by its edges do not touch any components or circuits When the board is not in an enclosure store it in staticshielding bag When installing a KAT Z3DB to the backplane follow these guidelines To prevent ESD damage to the KAT4000 wear a grounding wrist strap and use a grounded work surface while handling the board The ESD strip on the bottom edge of the RTM provides a controlled discharge path before the Zone 3 connec tors engage The KAT Z3DB receives all its power from the front board To install or remove the KAT Z3DB either Hot Swap the KAT4000 or install the KAT Z3DB with the KAT4000 s Hot Swap switch open no power First align the RTM Zone 3 connectors P30 P33 to the KAT4000 connectors 30 33 Then align both two pin ATCA guides the RTM s A1 Zone 3 and K1 Zone 2 to the 10007175 02 KAT4000 User s Manual 13 7 Rear Transition Module installation 4000 K2 and K1 respectively Finally mate the RTM s P33 to the 4000 33 connector and manually push in the module 4 Lockthe Hot Swap ejector handles Figure 13 5 Installing a KAT Z3DB RTM on the KAT4000 13 8 KAT4000 User s M
148. M 8a M Tolerance 40 B 00 B Accuracy 00 Accuracy Accuracy Exp 00 R exp B Exp 0 Analog Characteristic Flags 07 Nominal Reading 66 Normal Maximum bf Normal Minimum 00 Sensor Maximum Reading ES e KAT4000 User s Manual 10007175 02 Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Sensor Minimum Reading 00 E Upper Non Recoverable ff Threshold Upper Critical Threshold 00 Upper Non Critical Threshold 00 Lower Non Recoverable 00 Threshold Lower Critical Threshold 00 Lower Non Critical Threshold 00 Positive Going Threshold Hyst 03 Value Negative Going Threshold Hyst 00 Value OEM 00 ID String Type Length Code cc Table B 26 B4 12V Volt SDR Description KAT4000 Records Value Parameter Status Record ID 0018 SDR Version 51 Record Type 01 Full Sensor Record Record Length 37 Sensor Owner ID 00 Sensor Owner LUN 00 Sensor Number 00 Entity ID ci Module Entity Instance 68 Sensor Initialization 5 Init Scanning Init Sensor Type Init Hysteresis Init Thresholds Sensor Scanning enabled Sensor Capabilities 69 Ignore Sensor no Auto Re Arm enabled Sensor Hysteresis hysteresis is settable readable Sensor Threshold Acc
149. M56580 switch Table 5 3 lists the 8 bit PLD registers followed by the register bit descriptions 10 GbE 1 GbE Fat Pipe PLD Registers Address Access Register Offset hex Mode Mnemonic Register Name Map 0x00 R PIDV Product ID Version Register 5 9 0x01 R W SCR Scratch Register 5 10 0x02 R W 2 Register 5 11 0x03 R Reserved 1 5 12 0x04 R W SRST Switch Reset Register 5 13 0x05 R STAT Module Status Register 5 14 0x06 R W GPIO Switch GPIO Register 5 15 0x07 R W GPLED GPIN LED Register 5 16 Product ID Version Register The read only Product ID Version register indicates the product type PLD code version and hardware version The values of these bits are hard coded inside the PLD Product ID Version Register PIDV at 0x00 7 6 5 4 3 2 1 0 PID3 PID2 PID1 PIDO PVERO HVERO 10007175 02 Fat Pipe Switch Module 10 GbE 1 GbE Fat Pipe Switch Module PID3 PIDO PVER1 PVERO HVER1 HVERO Register 5 10 SCR7 SCRO Register 5 11 SDAS SCLS SDAC Product ID 0000 Fat Pipe Module GbE 0001 Fat Pipe Module sRIO 0010 Fat Pipe Module 10 GbE 1 GbE 0011 Fat Pipe Module 10 GbE 10 GbE All other values are reserved PLD Version 00 Revision 00 Hardware Version 00 Revision 00 Scratch Register The Scratch register can be used by software for reads and writes Accessing this register does not ha
150. MC When the Boot Loader receives this request it writes any remaining cached data to flash sends a success reply exits the upgrade mode and reboots After reboot the Boot Loader performs the standard firmware integrity checks and if they are a success boots the IPMC firmware This command is supported only by the Boot Loader If the IPMC firmware receives this command it sends a reply with the OxC1 Invalid Command completion code Table 9 48 Firmware Upgrade Complete Command Type Byte Data Field Request Data 1 Checksum Response Data 1 Completion Code Firmware Upgrade Restore Backup Command The Firmware Upgrade Restore Backup command makes the Boot Loader restore the firm ware from the backup image If the Boot Loader receives this command it does the follow ing Erasesthe slave H8S flash memory Erases the master H8S firmware area Programs the slave H8S firmware with the backup image stored in the master 85 flash memory Programs the master 85 firmware area with the backup image stored in the master 85 flash memory 4000 User s Manual 10007175 02 System Management Firmware Upgrade Table 9 49 Table 9 50 This command is only supported by the Boot Loader If the IPMC firmware receives this command it sends a reply with the OxC1 Invalid Command completion code Firmware Upgrade Restore Backup Command Type Byte Data Field Request Data 1 Checksum Response Data 1 Completion Code
151. MC over a serial interface A request is considered to be valid if the sum of all of the net work function code LUN byte the command code byte and the request body bytes is 0 modulo 256 If the checksum validation fails the Boot Loader sends a reply with the OxCC Invalid Data In Request The request sender is expected to resend the upgrade request in this case The upgrade replies are not protected with checksums Table 9 43 provides a sum mary of the firmware upgrade commands supported by the Boot Loader Firmware Upgrade Command Summary Command netFn LUN Cmd Firmware Upgrade Status Firmware 08 09 00 00 Firmware Upgrade Start Firmware 08 09 00 01 Firmware Upgrade Prepare Firmware 08 09 00 02 Firmware Upgrade Write Firmware 08 09 00 03 Firmware Upgrade Complete Firmware 08 09 00 04 Firmware Upgrade Restore Backup Firmware 08 09 00 05 Firmware Upgrade Backup Revision Firmware 08 09 00 06 The following sections detail the format of the firmware upgrade requests and replies Firmware Upgrade Status Command The Firmware Upgrade Status command queries the Boot Loader or the IPMC firmware about the firmware upgrade status This command is supported by both the IPMC firmware and the Boot Loader which return the current firmware upgrade status and cause in the Firmware Upgrade Status reply Firmware Upgrade Status Command Type Byte Data Field Request Data 1 Checksum 10007175 02 KAT4000 User s Manual 9 47 System Management
152. PVR coisas saa ka EX RARE ean 7 3 RGR 7 9 ROR 7 10 WP 7 8 RGCR 7 7 7 6 xeu E 7 8 version and 7 2to 7 3 regulatory certifications 1 10 reset and clocking signals CPU 3 12 amp a edlen 2 13 returning 2 18 ex en eene 1 11 RTC OVENWIEW E VERA 1 3 RTM block diagram 13 2 circuit 13 3 5 13 5 face plate 13 5 13 1 installation 13 7 1 4 sped A bi anes 13 6 5 SATA 5 8 6 oa cece we wees ane 9 40 SDRAM See DRAM sensor datarecords 9 40 serial command line interface CLI aggregation trunking commands A 13 command hierarchy A 4 command overview A 6 5 console commands A 8 debug commands A 17 help 3 IPcommands A 16 3 commands 10 mirror commands A 16 no CPU 4000 A 3 10007175 02 portcommands A 9 QoS commands A 14 system commands A 8 user group commands A 14 VLAN commands A 12 serial dat
153. Probe Input State Ignore SROM 1 SROM ignored 0 SROM not ignored Boot From Socket 1 Boot from socketed flash default 0 Boot from NOR flash Reserved TID3 0 Transition Module ID RTM GPIO State Register RGSR The read only RTM GPIO State register reads the state of the GPIO lines to from the RTM Default register values are configuration dependent RTM GPIO State Register RGSR at Oxfc40 0038 7 6 5 4 3 2 1 0 RIO7 RIO6 RIO5 RIO4 RIO3 RIO2 RIO1 RIOO 10007175 02 CPLD Miscellaneous Registers RIO7 0 Register 7 9 RGC7 0 Register 7 10 PCIE SRWP1 SRWPO 1 Logic 1 on the net 0 Logic O on the net RTM GPIO Control Register RGCR The RTM GPIO Control register controls GPIO between the carrier card and the Rear Transi tion Module RTM The GPIO pin buffers are open collector Set 1 the bit if the RTM will drive the GPIO line to avoid contention Default register values are shown in the bottom row of the register table RTM GPIO Control Register RGCR at Oxfc40 003c 7 6 5 4 3 2 1 0 7 RGC6 RGC5 RGC2 RGCO 1 Tristates the driver on the GPIO line externally pulled high 0 Drives logic 0 onto the GPIO line MISC Control Register MISC The MISC Control register controls miscellaneous functions of the board PCle SIO I7C Test Clock Default register values are show
154. R Version 51 Record Type 01 _ Full Sensor Record Record Length 30 _ Sensor Owner ID 00 _ Sensor Owner LUN 00 _ Sensor Number 00 Entity ID 14 Power Module DCto DC Converter Entity Instance 60 Sensor Initialization 7f Init Scanning Init Sensor Type Init Hysteresis nit Thresholds Init Events Sensor Scanning _ enabled Event Generation enabled 10007175 02 KAT4000 User s Manual Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Sensor Capabilities 69 Ignore Sensor no Auto Re Arm enabled Sensor Hysteresis hysteresis is settable readable Sensor Threshold Access threshold is settable readable Event Message Control global disable only Sensor Type 02 Voltage Event Reading Type Code 01 Threshold Assertion Event Mask 4801 Lower Non Recoverable Threshold comparison returned Upper Non Recoverable Going High supported Lower Non Critical Going Low supported Deassertion Event Mask 4801 Lower Non Recoverable Threshold comparison returned Upper Non Recoverable Going High supported Lower Non Critical Going Low supported Discrete Reading Mask Upper Non Recoverable Threshold settable Upper Critical Threshold settable Upper Non Critical Threshold settable Lower Non Recoverable Th
155. SRIO FAT PIPE SWITCH MODULE Fig 5 17 shows how the sRIO fat pipe switch module maps to ports defined by the 0 specification see Fig 1 3 for the full port mapping diagram This fat pipe switch module option is currently not available for order AMC Port Map Fat Pipes Region sRIO Port Mapping 4 sRIO x1 sRIO z 5 3 Fat Pipes Region x4 21529 0 Definition 5 Fat Pipe Switch Module Implementation This region supports data path connections such as sRIO It can carry large amounts of data without significantly degrading the speed of transmission This refers to the link width of the port the number of lanes that can be used to intercon nect between two link partners The following diagram shows the implementation of the sRIO fat pipe switch module on the KAT4000 Signal Routing of the sRIO Fat Pipe Switch Module on the KAT4000 AMC x4 Single Wide Half Full Extended Height 2 0 Extended Serial RIO x4 MPC8548 Processor Fat Pipe Switch Module SRIO x4 sRIO Local bus Base High Speed High Speed Clock RTM Fabric A Fabric B Optional 23 20 Zone 3 10007175 02 Memory Configuration Table 6 1 The KAT4000 includes the following memory devices Two banks of NOR Flash 32 MB total and one bank of socketed Flash 512 KB Upto 1gigabyte of DDR2 Synchronous DRAM SDRAM e Upto 1 gigabyte of
156. Specific Assertion Event Mask 010f Timer Interrupt Power Cycle Power Down Hard Reset Timer Expired status only Deassertion Event Mask 0000 Discrete Reading Mask 010f Timer Interrupt Power Cycle Power Down Hard Reset Timer Expired status only Sensor Units 1 00 Analog Data Format unsigned Rate Unit none Modifier Unit none Percentage no Sensor Units 2 Base Unit 00 Unspecified Sensor Units 3 Modifier Unit 00 Unspecified Linearization 00 00 00 B 00 B Accuracy 00 Accuracy Accuracy Exp 00 R exp B Exp 00 Analog Characteristic Flags 00 Nominal Reading 00 E Normal Maximum 00 H KAT4000 User s Manual 10007175 02 Appendix B sensor Data Records KAT4000 Records _ Value Parameter Status continued Normal Minimum 00 Sensor Maximum Reading 00 Sensor Minimum Reading 00 Upper Non Recoverable 00 Threshold Upper Critical Threshold 00 E Upper Non Critical Threshold 00 LowerNon Recoverable _ 00 Threshold _ Lower Critical Threshold 00 Lower Non Critical Threshold 00 Positive Going Threshold Hyst 00 Value Negative Going Threshold Hyst 00 Value OEM 00 ID String Length Code Table 6 3 3 Volt SDR Description KAT4000 Records Value Parameter Status Record ID 0004 SD
157. Switch Reset ester nere te tetra reet ng ERE 5 6 Figure 5 8 Port Map Fat Pipes Region 10 GbE 1 GbE 5 11 Figure 5 9 Signal Routing of the 10 GbE 1 GbE Fat Pipe Switch Module on the KAT4000 5 11 Figure 5 10 10 GbE 1 GbE Fat Pipe Switch Module Block Diagram 5 12 Figure 5 11 10 GbE 1 GbE Fat Pipe Switch Module Component Top Rev 01 5 13 Figure5 12 10 GbE 1 GbE Fat Pipe Switch Module Component Map Bottom Rev 01 5 13 Figure 5 13 10 GbE 1 GbE Fat Pipe Switch 5 15 Figure 5 14 10 GbE 1 GbE Fat Pipe Switch Reset 5 16 Figure 5 15 AMC Port Map Fat Pipes Region 10 GbE 10 5 21 Figure 5 16 Signal Routing of the 10 GbE 10 GbE Fat Pipe Switch Module on the KAT4000 5 21 Figure 5 17 AMC Port Map Fat Pipes Region SRIO 5 22 Figure 5 18 Signal Routing of the sRIO Fat Pipe Switch Module on the 4000 5 22 Figure 7 1 Boot Device Redirectiori 55 bern SERRE RR MEER 7 12 Figure 7 2 PED erp rr 7 20 Figure 8 1 4425 pe erre REC Rex ol a Mince FUR Ha Rie dies USER E 8 2 10007175 02 KAT4000 User s Manual Figures continued Figure 8 2 Diagram of SATA line
158. The KAT4000 thermal performance must be verified in the end user s operating environment Contact Emerson Technical Support at 1 800 327 1251 for more information TROUBLESHOOTING For instructions on how to properly install and configure the KAT4000 in a system see the KAT4000 Quick Start Guide 10008585 xx or the KAT4000 Quick Start Guide for the No CPU Carrier Board 10008506 If difficulty persists after referencing the Quick Start Guide use this checklist Be sure all modules are seated firmly the AMC modules the 4000 the RTM on the KAT4000 if used and the KAT4000 in the card cage Verify the jumper settings see Table 2 3 Be sure the system is not overheating Check the cables and connectors to be certain they are secure 1 Check your power supply for proper DC voltages 1 Check that your terminal is connected to a console port Technical Support If you need help resolving a problem with your KAT4000 visit http www artesyncp com support index html postsales on the Internet or send e mail to support artesyncp com Please have the following information available KAT4000 serial number monitor revision level product identification from the sticker on the KAT4000 board version and part number of the operating system if applicable whether your board has been customized for options such as a higher processor speed or additional memory license agreements if applicable
159. The isdram command displays the SDRAM configuration information valid chip values range from 50 to 57 10007175 02 KAT4000 User s Manual 14 23 Monitor Other Commands 14 24 Definition Definition Definition Definition Definition KAT4000 User s Manual isdram addr loop The loop command executes an infinite loop on address range loop b w 1 address number of objects memmap The memmap command displays the board s memory map layout memmap moninit The moninit command resets the NVRAM and serial number and it writes the monitor to Flash The KAT4000 must be booted from the boot socket for this command to function in the default state The proper region of Flash memory will be unlocked and erased prior to copying the monitor software into it The command flags s or d force the monitor to be programmed to a single s bank of flash or dual d banks of flash If the command flags are not used then moninit checks for the number of banks of flash If there are two banks of flash then moninit automatically programs both banks for redundancy Also the serial number can be obtained from the fru data if fru is used as a parameter Initialize environment variables and serial number in NVRAM and copy the monitor from the socket to NOR soldered Flash moninit s d lt serial or fru Initialize environment variables and serial number in NVRAM but do not update the monitor in NOR Flash m
160. The upgrade initiator sends a Firmware Upgrade Complete command to finish the firmware upgrade The Boot Loader writes the remaining cached data to the slave H8S flash and reboots the IPMC After reset the Boot Loader validates the master H8S firmware checksum and passes control to the IPMC 10007175 02 Synchronization Clocks The KAT4000 implements a flexible clocking circuit based on a clock selection holdover chip with a PLD wrapper This PLD wrapper allows local software control of the source clock selection from these input options backplane CLK1A B backplane CLK2A B backplane CLK3A B AMCn TCLKA AMCn TCLKB or AMCn FCLKA Any of these clock sources can sent to the following output clocks backplane CLK3A B AMCn TCLKA AMCn TCLKB or AMCn FCLKA Transceiver buffers are used to convert all M LVDS clocks to from TTL levels and CLK2 on the backplane are inputs only See Fig 10 1 fora diagram of this circuitry See Clock Synchronizer Registers on page 7 13 for information on configuring the stra tum clock buffers selecting the primary and secondary clock sources and selecting the output source Note The pins for TCLKC and TCLKD are routed to the Zone 3 connector interface If these signals are used on a rear transition module there could be a conflict with an AMC module that uses these clocks Figure 10 1 Synchronization Clock Circuit Diagram AMC 3 lt 200MHz 100 MHz TCLKA FCLKA
161. Threshold comparison returned Upper Non Recoverable Going High supported Discrete Reading Mask 3838 Upper Non Recoverable Threshold settable Upper Critical Threshold settable Upper Non Critical Threshold settable Upper Non Recoverable Threshold readable Upper Critical Threshold readable Upper Non Critical Threshold readable 10007175 02 KAT4000 User s Manual B 47 Appendix B sensor Data Records KAT4000 Records Parameter Status continued Sensor Units 1 00 Analog Data Format unsigned Rate Unit none Modifier Unit Percentage no Sensor Units 2 Base Unit 05 5 B _ Sensor Units Modifier Unit 00 Unspecified _ Linearization 700 HN M 11 M Tolerance 240 B 00 B Accuracy 00 Accuracy Accuracy Exp 00 R exp B Exp cO Analog Characteristic Flags 07 Nominal Reading 93 Normal Maximum ef Normal Minimum 00 Sensor Maximum Reading ff Sensor Minimum Reading 00 Upper Non Recoverable ff Threshold Upper Critical Threshold 200 Non Critical Threshold 00 Lower Non Recoverable 00 Threshold Lower Critical Threshold 00 Lower Non Critical Threshold 00 Positive Going Threshold Hyst 02 Value _ Negative Going Threshold Hyst
162. UN Get Power Level PICMG 2C 2D 00 12 Bused Resource Control PICMG 2C 2D 00 17 Release Query Force Bus Free The IPMC implements many standard IPMI commands For example software can use the watchdog timer commands to monitor the system s health Normally the software resets the watchdog timer periodically to prevent it from expiring The IPMI specification allows for different actions such as reset power off and power cycle to occur if the timer expires The watchdog s timer use fields can keep track of which software Operating System Sys tem Management etc started the timer Also the time out action and timer use infor mation can be logged automatically to the System Event Log SEL when the time out occurs Please refer to the IPMI specification listed in Table 1 3 for details about each com mand s request and response data The IPMC also implements ATCA commands see the ATCA Base Specification PICMG 3 0 10007175 02 KAT4000 User s Manual System Management vendor Commands VENDOR COMMANDS The IPMC supports additional IPMI commands that are specific to Pigeon Point and or Emerson This section provides detailed descriptions of those extensions Table 9 6 Vendor Command Summary Command netFn LUN Get Status OEM 2E 2F 00 00 Get Serial Interface Properties OEM 2E2F 00 01 Set Serial Interface Properties OEM 2E 2F 00 02 Get Debug Level OEM 2E2F 00 03 Se
163. _ 116 GND 117 RRINGI 118 Bn_RTIP1 119 _120 Bn_TRING1 21017 Bn_TTIP1 022 GND 123 Bn_RRING2 124 _ 2 125 GND 126 Bn TRING2 127 Bn_TTIP2 128 GND 129 RRING3 130 Bn_RTIP3 131 GND 132 Bn_TRING3 133 Bn_TTIP3 134 GND 135 Bn_RRING4 136 Bn_RTIP4 137 GND 2138 TRING4 139 Bn_TTIP4 140 GND 141 Bn RRING5 142 Bn_RTIP5 143 GND 144 TRING5 10007175 02 KAT4000 User s Manual Sites SATA Lines Figure 8 2 KAT4000 User s Manual Pin B1 B4 Signal Pin B1 B4 Signal 145 Bn TTIP5 146 GND 147 Bn RRING6 148 Bn RTIP6 149 GND 150 TRING6 151 Bn TTIP6 152 GND 153 Bn RRING7 154 Bn RTIP7 155 GND 156 Bn TRING7 157 Bn TTIP7 158 GND 159 Bn RRING8 160 Bn RTIP8 161 GND 162 Bn_TRING8 163 Bn_TTIP8 164 GND 165 TCK 166 TMS 167 TRST 168 TDO 169 TDI 170 GND SATA LINES This section displays the SATA line connections for AMCs in the KAT4000 Use SATA lines to link AMC modules with storage devices e g SATA hard drive or Emerson Ethernet test card Diagram of SATA line connections B4 B3 B2 B1 SATA WARNER 2 SATA 1 SATA 2 SATA 1 SATA 2 SATA 1 10007175 02 System Management The KAT4000 provides an intelligent hardware management system as defined in the AdvancedTCA Base Specification PICMG 3 0 0 This system implements an Intel ligent Platform
164. a path configuration 4 3 serial I O 2 4 1 2 serial interface reference manual 1 14 2 15 2 15 serial ports console 13 5 setup requirements 2 15 signal descriptions PCl 8 2 specifications environmental 2 16 2 1 eei 2 16 SROM 55 6 3 static control 2 1 Switches is s 2 8 synchronization clock 10 1 OVEIVIEW 1 3 reference 1 14 system management 1 3 T table of contents ii iii tables technical references 1 12 technical support terminology 1 12 test commands monitor 14 21 3 4 troubleshooting ete e 2 17 MONIEOE 14 31 0 UL certifications 1 11 UL number 1 11 V version 25566 sm 2 15 operating 2 15 VLAN 4 3 KAT4000 User s Manual continued W web interface Z no CPU 4000 A 18 PET n VLAN setup aoo tace
165. ables and Boot AMC Sites B1 B4 Payload Device Management Reset Select Temperature Sensors CPU Inlet CPU Outlet Temp Sensor Temp Sensor 0x90 0x92 CPU Present AMC Sites B1 B4 Ready Payload Power Current Monitor 1 M C RTM Present CPU Core Voltage AMC Sites B1 B4 Enable Sensors Pig eon Poi nt RTM Payload Power Enable 5 RTM Management Power Enable Reference Design 12 Bus IPMC Debug Console roprieta p opriet ry Front Panel ShMC Present LEDs from JP7 IPMC Reset Switch Hot Swap Switch 318VN3 8 318VN3 Isolation Isolation 0 E KAT4000 User s Manual 10007175 02 System Management IPMI Messaging IPMI MESSAGING All IPMI messages contain a Network Function Code field which defines the category for a particular command Each category has two codes assigned to it one for requests and one for responses The code for a request has the least significant bit of the field set to zero while the code for a response has the least significant bit of the field set to one Table 9 1 lists the network function codes as defined in the IPMI specification used by the IPMC Table 9 1 Network Function Codes Hex Code Value s Type Description 00 01 Chassis chassis device 00 command request 01 response requests responses chassis control and status functions 02 03 Bridge bridge
166. abric the processor and the Update Channel optional A Vitesse VSC7376 GbE switch implements this function Ethernet Core Switch optional on page 4 2 provides more information The PCle switch provides the interconnect between the AMC sites the processor and the fat pipe switch module A PLX Technology PEX 8524 PCle switch implements this function PCI Express Switch optional on page 4 7 provides more information Of the Ethernet core switch and the PCI Express switch at least one of the two switches must be used on the board The board can also use both switches 10007175 02 KAT4000 User s Manual Overview Components and Features Fat Pipe Switch Module A high speed fat pipe switch is provided as a plug over module It supports GbE Serial Rapid IO sRIO PCI Express PCle or 10 Gigabit Ethernet 10 GbE This switch provides an interconnect between the AMC sites the ATCA high speed fabric ports the processor the PCle switch and the Ethernet core switch See Fat Pipe Switch Module Chapter 5 for information on your module s configuration Rear Transition Module RTM The optional transition modules provide access to 16 or 32 ports when are installed on the KAT4000 AMC site ports 12 20 are routed to Zone 3 for Rear Transition Module RTM I O 64 AMC signals route to 264 pins in Zone 3 see Zone 3 page 12 4 There are nine T1 E1 ports per AMC site routed as differential pairs 64 signals Ther
167. aci eR pasar her Tp DERE E SR RE 3 1 Table 3 2 PCI Device and Vendor ID des te eorr eek dx e pe prag M reae ses 3 4 Table 3 3 MPC8548 Peripheral Request 3 10 Table 3 4 8548 Chip Select e Ie Iam PUR cad 3 12 Table 3 5 MPC8548 ExceptiorlS Ee REA ID Haus Ne bait epe ends 3 13 Table 3 6 Processor JTAG COP Pin Assignments 1 3 15 Table 4 1 KAT4000 PHYs and Address 4 4 4 2 Ethernet Core Switch Off Board 4 4 Table 4 3 GbE Fat Pipe Module Ethernet Switch Off Board 4 5 Table 4 4 Ethernet Port Address Numbering esses 4 6 Table 4 5 PEX 8524 TAG Sigilals 35 eo hup Rh RR aa RE 4 9 Table 5 1 GbE Fat Pipe PLD Registers 5 6 Table 5 2 BCM56580 Switch Ports se rr rr n PERDER pane 5 14 Table 5 3 10 GbE 1 GbE Fat Pipe PLD 5 16 Table 6 1 Memory Configuration 6 1 Table 6 2 NVRAM Memory Map User EEPROM 1 write protected Justo anoche 6 3 Table 6 3 NVRAM Memory Map User 2
168. ad and write the controller s SROMs read the temperature voltage and watchdog sensors get specific information such as thresholds for each sensor read and write the Field Replaceable Unit FRU data reserve and read the Sensor Data Record SDR repository configure event broadcasts bridge an IPMI request to the public IPMB and return the response Table 9 5 lists the IPMI commands supported by the IPMC along with the hexadecimal values for each command s Network Function Code netFn Logical Unit Number LUN and Command Code All values are hexadecimal IPMC IPMI Commands Command netFn LUN Set Event Receiver Sensor Event 04 05 00 00 Get Event Receiver Sensor Event 04 05 00 01 Platform Event Event Message Sensor Event 04 05 00 02 Get Device SDR Information Sensor Event 04 05 00 20 Get Device SDR Sensor Event 04 05 00 21 Reserve Device SDR Repository Sensor Event 04 05 00 22 Get Sensor Reading Factors Sensor Event 04 05 00 23 10007175 02 KAT4000 User s Manual E System Management standard Commands Command continued netFn LUN Set Sensor Hysteresis Sensor Event 04 05 00 24 Get Sensor Hysteresis Sensor Event 04 05 00 25 Set Sensor Thresholds Sensor Event 04 05 00 26 Get Sensor Thresholds Sensor Event 04 05 00 27 Set Sensor Event Enable Sensor Event 04 05 00 28 Get Sensor Event Enable Sensor Event 04 05 00 29 Rearm Sensor Events Sensor Event 04 05 00 2A G
169. al 10007175 02 Monitor Troubleshooting Variable app lock size bootverifycmd dhcp client id dhcp user class e keying pri bootargs pci memsize pram sec bootargs Description continued Size of user NOR soldered flash protection area Sets the U Boot boot command that is used to execute the primary and secondary application images when using the bootv command If not defined bootv uses the U Boot go command as the default Populates the Client Identifier Option 61 in the DHCP request Packet See dhcp page 10 Populates the User Class Information Option 77 in the DHCP request Packet See dhcp on page 10 Enables the Update Channels and payload ports that go off the KAT4000 fat pipe switch module to high speed fabric fat pipe switch module to AMCs and GbE from fat pipe switch module to Ethernet core switch For debug use only If e keying is set to on or if the variable is not present the ports are disabled The e keying variable is only used on power up Sets the boot arguments that are passed into the primary application images when using the bootv command If not defined bootv will pass the bootargs configuration parameters into the primary application image Sets the amount of SDRAM memory made available on the PCI bus The minimum setting is 16 megabytes If not set 128 MB of SDRAM are available over PCI This parameter takes a hex value Valid options all size in hex 0 800000
170. al port settings are 115 200 baud 8 data no parity and 1 stop bit The private bus consists of the following devices temp sensors the 48V con verter AMC A to D converters and an optional connection to Zone 3 for Rear Transition Module RTM access One processor 2 bus links to the following two user SEEPROMs the CPU init SEEPROM the Real Time Clock RTC the SO DIMM and the fat pipe switch module if used Another processor 2 bus provides an optional connection to Zone 3 for Rear Transition Module RTM access The IPMC controls the two Joint Test Action Group JTAG interfaces hubs One JTAG hub is connected to seven ports the KSL PLD the IPMC PLD the fat pipe switch module and the four AMC sites The other hub is connected to five ports the VSC7376 switch the PEX8524 switch the clock synchronizers the IPMC GPIO and GbE PHYs See JTAG Interfaces on page 2 9 for more information The KAT4000 has four single width mid size Advanced Mezzanine Card AMC sites which allow for use of up to four compatible AMC modules Double width and compact modules can also be accommodated B style AMC connectors are used The KAT4000 complies 10007175 02 Overview Components and Features System Management Synchronization Clock RTC Caution No CPU Configuration Ethernet Core Switch PCI Express Switch Note with the PICMG AMC 0 Revision 2 0 Advanced Mezzanine Card Base Specifi
171. also includes watchdog timer time out inputs Machine State Register The Machine State register MSR configures the state of the MPC8548 On initial power up of the KAT4000 most of the MSR bits are cleared Please refer to the MPC8548 PowerQuicc Ill Integrated Communications Processor Reference Manual for more detailed descriptions of the individual bit fields Register 3 4 CPU Machine State Register MSR 32 36 37 38 39 44 45 46 47 reserved UCLE SPE reserved WE CE R 48 49 50 51 52 53 54 55 57 58 59 60 61 62 63 EE PR R ME R UBLE DE reserved IS D R PM reserved R Reserved should be cleared UCLE User mode Cache Lock Enable restricts user mode cache line locking by the operating sys tem 0 Any cache lock instruction takes a cache locking DSI exception 1 Acache locking DSI is not taken SPE Signal Processing Engine enable 0 An SPE APU unavailable exception occurs 1 Software can execute supported SPE and SPFP APU instructions WE Wait state Enable allows the core complex to signal a request for power management 0 continues processing 1 CPU enters wait state CE Critical Enable 0 Critical input and watchdog timer interrupts disabled 1 Critical input and watchdog timer interrupts enabled 10007175 02 KAT4000 User s Manual E Central Processing Unit Peripheral Interface 3 10 PR ME UBLE IS DS Table 3 3 KAT4000 User s Manual External interrupt Enable allows
172. and LED 1 can be either red or amber this command is used to determine the valid color prior to issuing a Set FRU LED State command Table 9 36 Get LED Color Capabilities Command Type Byte Data Field Request Data 1 PICMG Identifier indicates that this is a PICMG defined group extension command Use value 00h 2 _ FRU Device ID 3 LED ID FFh Reserved 9 34 KAT4000 User s Manual 10007175 02 System Management FRU LEDs Type Response Data Data Field continued Completion Code CCh If the LED ID contained in the Request data is not present on the FRU PICMG Identifier indicates that this is a PICMG defined group extension command Use value 00h LED Color Capabilities when a bit is set the LED supports the color Bit 7 Reserved set to 0 Bit 6 LED supports white Bit 5 LED supports orange Bit 4 LED supports amber Bit 3 LED supports green Bit 2 LED supports red Bit 1 LED supports blue Bit 0 Reserved set to 0 Default LED Color in Local Control State Bit 7 Reserved set to 0 Bits 3 0 Oh Reserved 1h Blue 2h Red 3h Green 4h Amber 5h Orange 6h White 7h Fh Reserved Default LED Color in Override State Bit 7 Reserved set to 0 Bits 3 0 Oh Reserved 1h Blue 2h Red 3h Green 4h Amber 5h Orange 6h White 7h Fh Reserved 10007175 02 KAT4000 User s Manual 9 35 System Management FRU LEDs Set FRU LED State Command The Se
173. and Immunity circuit pack level testing only EN300386 Electromagnetic Compatibility and Radio Spectrum Matters ERM Telecommunication Network Equipment Electromagnetic Compatibility EMC Requirements AS NZS 3548 003 Standard for radiated and conducted emissions for Australia and New Zealand Class A Emerson maintains test reports that provide specific information regarding the methods and equipment used in compliance testing Unshielded external I O cables loose screws a poorly grounded chassis may adversely affect the KAT4000 s ability to comply with any of the stated specifications UL Certification The UL web site at ul com has a list of Emerson s UL certifications 1 Tofind the list go to the web site and search in the online certifications directory using Emerson s UL file number E190079 There is a list for products distributed in the United States as well as a list for products shipped to Canada 2 Products are listed by board type followed by the model name and or number The KAT4000 is an AdvancedTCA ATCA blade The model number is KAT4000 s Printed Circuit Board PCB artwork number which is 10007505 xx RoHS Compliance The KAT4000 all fat pipe modules listed in Chapter 5 and the RTM described in Chapter 13 are compliant with the European Union s RoHS Restriction of Use of Hazardous Sub stances directive created to limit harm to the environment and human health by restrict ing the use of harm
174. anual 10007175 02 Monitor Section 14 Auto Repeat Command History TFTP Boot Auto Boot Flash Programming The KAT4000 monitor is based on the Embedded PowerPC Linux Universal Boot U Boot Project program available under the GNU General Public License GPL For instructions on how to obtain the source code for this GPL program please visit http www arte syncp com send an e mail to support artesyncp com or call Emerson at 800 327 1251 This chapter describes the monitor s basic features operation and configuration sequences This chapter also serves as a reference for the monitor commands and func tions COMMAND LINE FEATURES The 4000 monitor uses a command line interface with the following features After entering a command you can re execute it simply by pressing the ENTER or RETURN key Recall previously entered commands using the up and down arrow keys You can use the TFTP protocol to load application images via Ethernet into the KAT4000 s memory You can store specific boot commands in the environment to be executed automatically after reset You can write application images into Flash via the U Boot command line The upper 1 MB at the base of Flash and 128 KB of each Flash bank is reserved for the monitor and environment variables One megabyte is reserved at the second bank of flash The moninit command will load both banks of flash see moninit on page 14 24 with the monitor and d
175. applicable to your development application 4 Ensure that each MAC address on the network is unique 5 If autoload is not set or configured to yes ensure that the DHCP provides proper information for autoboot If proper autoboot information is not provided an error may occur rarpboot The rarpboot command boots an image via a network connection using the RARP TFTP protocol If loadaddress or bootfilename is not specified the environment variables loadaddr and bootfile are used as the default To use this command the environment variables listed in Table 14 4 must be configured rarpboot loadaddress bootfilename tftpboot The tftpboot command loads an image via a network connection using the TFTP protocol The environment variable s ipaddr and serverip are used as additional parameters to this command If loadaddress or bootfilename is not specified the environment variables loadaddr and bootfile are used as the default To use this command the environment vari ables listed in Table 14 4 must be configured The port used is defined by the ethport environment variable If a 1 1 is selected for ethport the TFTP process will cycle through each port until a connection is found or all ports have failed 10007175 02 KAT4000 User s Manual Monitor File Load Commands Definition offset baudrate Definition offset baudrate Definition Definition Definition Definition E KAT4000 User s Manual tftpboot
176. apter IPMB PROTOCOL The IPMB message protocol is designed to be robust and support many different physical interfaces The IPMC supports messages over the IPMB interface Messages are defined as either a request or a response as indicated by the least significant bit in the Network Func tion Code of the message Table 9 3 shows the format of an IPMI request message followed by each byte description Table 9 3 Format for IPMI Request Message Byte Bits 7 6 5 4 3 2 1 0 1 rsSA 2 netFn rsLUN 3 Checksum 4 45 5 rqSeq rqLUN 6 Command 7 N Data 1 Checksum The first byte contains the responder s Slave Address rsSA The second byte contains the Network Function Code netFn and the responder s Logical Unit Number rsLUN Thethird byte contains the two s complement checksum for the first two bytes Thefourth byte contains the requester s Slave Address rqSA Thefifth byte contains the requester s Sequence Number rqSeq and requester s Logical Unit Number rqLUN The Sequence number may be used to associate a specific response to a specific request Thesixth byte contains the Command Number 10007175 02 KAT4000 User s Manual System Management SIPL Protocol Table 9 4 4000 User s Manual e The seventh byte and beyond contain parameters for specific commands if required The final byte is the two s complement checksum of all of the message data after the first checksum An IPMI response m
177. ase Continuity Control Input Controls state changes between Holdover and Normal modes Please refer to Chapter 7 for further details Input Reference Select 1 Secondary Clock 0 Primary Clock Reserved 10007175 02 KAT4000 User s Manual 7 13 CPLD Clock Synchronizer Registers 7 14 Register 7 17 R PRI4 0 KAT4000 User s Manual Clock Synchronizer Primary Source Registers 1 3 CPS1 CPS3 The Clock Synchronizer Primary Source registers define the input primary source to the three clock synchronizer devices Default is 0x00 for register 1 0x02 for register 2 and 0x04 for register 3 Clock Synchronizer Primary Source Registers 1 3 CPS1 CPS3 at Oxfc40 0050 Oxfc40 0054 Oxfc40 0058 respectively 7 6 5 4 3 2 1 0 reserved PRI4 PRI3 PRI2 PRIO Default register values for CPS1 are shown in the following row 0 0 0 0 0 efault register values for CPS2 shown the following row 0 0 0 1 0 Default register values for CPS3 are shown in the following row 0 0 1 0 0 Reserved Primary Input Source Selection Bit Input Source 00000 aTCA 00001 aTCA CLK1 B 00010 aTCA CLK2 A 00011 aTCA CLK2 B 00100 aTCACLK3A 00101 00 00110 AMC1CLK1 00111 2 01000 AMCICIG 0100 2 01010 AMC2CLK2 01011 2 01100 AMC3CLK1 100
178. ata 1 3 Response Data 1 2 4 5 6 Data Field PPS IANA Private Enterprise ID MS Byte first 0 00400 16394 Pigeon Point Systems Completion Code PPS IANA Private Enterprise ID MS Byte first 0 00400 16394 Pigeon Point Systems Time Out measured in hundreds of milliseconds LSB first Set Payload Shutdown Time Out Command The Set Payload Shutdown Time Out command is defined as follows Table 9 26 Set Payload Shutdown Time Out Command Type Byte Request Data 1 3 4 5 Response Data 1 2 4 Data Field PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Time Out measured in hundreds of milliseconds LSB first Completion Code PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Get Module State Command The Get Module State command is used to query the state of an AMC via any of the external interfaces Table 9 27 GetModule State Command Type Byte Request Data 1 3 4 Data Field PPS IANA Private Enterprise ID MS Byte first 0 00400 16394 Pigeon Point Systems AMC Site ID KAT4000 User s Manual 10007175 02 System Management vendor Commands Type Byte ResponseData 1 2 4 5 Data Field continued Completion Code PPS IANA Private Enterprise ID MS Byte first 0 00400 16394 Pigeon Point Systems Status 0 0 site is enabled 1 AMC site is disabled 1 0 AMCis not present 1
179. ations of the fat pipe switch module GbE 10 GbE 1 GbE 10 GbE 10 GbE and sRIO Note The 10 GbE 10 GbE and sRIO modules are not yet available for order All fat pipe switch configurations support Four ports connected from each AMC site to the fat pipe switch capable of interchangeably using GbE sRIO or 10 GbE protocols Eight GbE 1000Base BX SerDes ports connected from the backplane high speed fabric to the fat pipe switch Two ports connected from the fat pipe switch to Zone 3 for optional RTM access The GbE and 10 GbE configurations also provide One port for a dedicated GbE channel from the MPC8548 processor to the fat pipe switch One portfor a dedicated GbE channel from the Ethernet core switch to the fat pipe switch The sRIO configuration also provides Oneorfour ports for a dedicated sRIO channel from the 8548 processor to the fat pipe switch 10007175 02 KAT4000 User s Manual Fat Pipe Switch Module GbE rat Pipe Switch Module GBE FAT PIPE SWITCH MODULE Fig 5 1 shows how the GbE fat pipe switch module maps to ports defined by the AMC O specification see Fig 1 3 for the full port mapping diagram Figure 5 1 AMC Port Map Fat Pipes Region GbE Port Mapping 4 Fat Pipes x1 Figure 5 2 KAT4000 User s Manual GbE x1 GbE x1 GbE x1 1 0 Definition Fat Switch Module Implementation 203 seg o4 L Fat Pipes Region
180. c Channel 2 2 2 Tx2 2 Rx2 2 Rx2 2 2 2 Tx0 2 2 RxO 2 3 FabricChannel1 2 1 Tx2 1 Rx2 1 lt Rx2 1 4 1 RxO 1 RxO 1 5 Base Ethernet1 XBC1_TRO XBC1_TRO XBC1_TR1 XBC1_TR1 6 Base Ethernet 2 XBC2_TRO XBC2_TRO XBC2_TR1 XBC2 TRI 7 10 no connect Row Interface EF 1 Fabric Channel 2 Tx3 2 Tx3 2 Rx3 2 Rx3 2 2 Tx1 2 Rx1 2 Rx1 2 3 FabricChannel1 3 1 Tx3 1 Rx3 1 _ 1 4 Tx1 1 Rx1 1 Rx1 1 5 Base Ethernet XBC1_TR2 XBC1_TR2 XBC1_TR3 6 2 XBC2_TR2 XBC2_TR2 2 TR3 XBC2_TR3 7 10 no connect ZONE 3 These optional Zone 3 type A connectors 30 through J33 support a Rear Transition Mod ule RTM Features include Two SerDes ports from the Ethernet core switch e Routing all AMC user I O Power routed to support active logic with hot swap control 2 bus from IPMC for system management purposes 12 bus from payload processor Payload processor debug Ethernet port connection KAT4000 with CPU Console serial port interfaces for the payload processor KAT4000 without CPU Console serial port interfaces for the Ethernet core switch and fat pipe Ethernet switch console ports Connectors 30 through J32 use the same ZD style connector as Zone 2 10007175 02 KAT4000 User s Manual Conn
181. c Interface J23 supports two Fabric channels The fabric interface connection is controlled by the system E keying process E KAT4000 User s Manual 10007175 02 Connectors 7 2 Sixsignal pairs 12 pins are available to support the optional Synchronization Clock Interface 20 for 8 KHz 19 44 KHz and user defined clocks e Ten signal pairs are available for an optional Update Channel interface 20 Figure 12 2 Zone 2 Connectors 20 and 23 and Zone 3 Connectors 30 32 Row H Row G Row F Row E Row D Row C Row B Row ETER ERRER ERRER EREE ETER jeu EREE 10 6 Table 12 2 Zone 2 Connector 20 Pin Assignments 5 10 In Table 12 3 example B1 Dx m p signifies no connect UC TX2 UC_TX0 no connect CLK2A CLK3A UC_TX3 UC_TX1 no connect AB CLK1A no connect UC_TX2 UC TXO no connect EF CLK2A CLK3A UC TX3 UC TXI no connect xisthe differential pair A D 10007175 02 CLK1B no connect UC_RX2 UC_RX0 no connect CLK2B CLK3B UC_RX3 UC_RX1 no connect CD CLK1B no connect UC_RX2 UC_RXO no connect GH CLK2B CLK3B UC_RX3 UC_RX1 no connect KAT4000 User s Manual 12 3 Connectors 7 mis logical slot number 1 16 pisthe polarity Table 12 3 Zone 2 Connector 23 Pin Assignments Row Interface AB CD 1 Fabri
182. cation with the exception of a couple non conformances See the KAT4000 Errata for details Each AMC site is individually configurable Chapter 8 provides more information The KAT4000 supports an Intelligent Platform Management Interface IPMI based on a Renesas microcontroller with a UART interface for processor to IPMC communication fixed rate at 115 200 baud and dual redundant IPMB AJB interfaces The IPMC allows for fea tures such as remote shutdown remote reset payload voltage monitoring temperature monitoring and access to Field Replaceable Unit FRU data Chapter 9 provides more information The synchronization clock interface consists of MT9045 or MT9046 T1 E1 system synchro nizers Chapter 10 provides more information The Real Time Clock RTC is an ST9Microelectronics M41T00 Serial Access Timekeeper Chapter 11 provides more information There are no serviceable parts in this product Return all damaged boards to Emerson for repair see page 2 18 KAT4000 Options Ano CPU KAT4000 board configuration is available This configuration includes 256 Kb of SRAM memory used by the internal 8051 microcontroller on the VSC7376 Ethernet core switch for run time code storage This configuration omits SDRAM and NOR and NAND flash Appendix A provides more information The Ethernet core switch provides the interconnect between the fat pipe switch module the Ethernet ports on the AMC sites two channels on the ATCA backplane Base f
183. ce per icache chip selects environment 4 variable Initialize fat pipe Ethernet switch Initialize if installed flash Engle er Configure L2 cache per 2 T and I2mode Turn off debug Y Initialize malloc environment vars LEDs and blink area front panel red Initiali LED per blinked nitialize the Y environment var U Boot environment Display LED 0111 Initialize e PCle a Main Loop N 10007175 02 KAT4000 User s Manual Monitor Monitor Recovery and Updates POST Diagnostic Results The KAT4000 Power On Self Test POST diagnostic results are stored as 32 bit value in I C NVRAM at the offset 0x1 DD8 0x1DDB Errors will also be stored in the Vital Products Data section and FRU user space area for access by other devices Each bit indicates the results of a specific test therefore this field can store the results of up to 32 diagnostic tests Table 14 2 assigns the bits to specific tests Table 14 2 POST Diagnostic Results Bit Assignments Bit Diagnostic Test Value 0 SDRAM 1 Flash 2 3 Ethernet Core Switch 0 Passed the test 4 Reserved 1 Failure detected 5 PCle Timeout if Root Complex currently not implemented 6 31 Reserved Monitor SDRAM Usage Monitor SDRAM usage is typically around 1 MB for monitor code and stack support Please note that the monitor stack grows downward from below where the monitor code resides in the upper 512 KB The monitor C stack will t
184. cessor For more detailed information refer to the MPC8548E PowerQUICC III Integrated Host Processor Family Refer ence Manual Refer to Fig 3 1 for a block diagram of the MPC8548 The MPC8548 is divided into two main system blocks as outlined in the following table 8548 Features Category 8548 Key Features Microprocessor Core Embedded e500 Core Full 32 bit Book E architecture integer data types of 8 16 and 32 bits 32 bit floating point data type capable of issuing and completing two instructions per clock cycle 7 pipeline stages Auxiliary Processing Units APUs page address translation core registers memory management unit L1 Cache 32 kilobyte data and 32 kilobyte instruction cache 32 byte line eight way set associative parity protection L2 Cache 512 kilobytes eight way set associative CPU Core Speed 1 GHz or 1 3 GHz with a 400 MHz or 533 MHz DDR2 bus respectively Peripheral Modules Ethernet Four 10 100 1000 enhanced three speed controllers eTSEC full Local Bus Controller LBC High Speed Serial Interfaces half duplex support for high speed interconnect a set of multiplexed pins support two high speed interface standards 1x 4x serial RapidlO with message unit and up to x4 PCI Express DDR2 SDRAM memory controller General Purpose Chip Select Machine GPCM and three User Programmable Machines UPM PCle sRIO 10007175 02 KAT4000 User
185. ck Configuration CPU 999 MHz CCB 399 MHz DDR 199 MHz LBC 49 MHz KATA000 AMC Carrier Emerson Network Power Embedded Computing PLD Ver 2 I2C ready Clearing ALL of memory Board a DRAM 512 MB Testing Top 1M Area of DRAM PASSED Relocating code to RAM FLASH 16MB8e0000000 16MB8e1000000 32 MB L2 cache enabled PCIe none In serial Out serial Err serial Ser 1086 Diags Mem PASSED Diags I2C PASSED Diags Flash PASSED BootDev Soldered Flash Bank 1 I cache enabled D cache enabled write through L2 cache enabled L2CTL 0xa0000000 write through IPMC v0 1 1 DOC Turbo Mode Net eTSEC1 eTSEC2 eTSEC3 eTSECA Core Eth Sw VSC7376 Monitor command prompt Fat Pipe Eth Sw VSC7376 KAT4000 Mon 1 01d gt V 142 KAT4000 User s Manual 10007175 02 Monitor Command Line Features The monitor command prompt in Fig 14 2 is the result of a successful hardware boot of the KAT4000 with a 10 GbE 1 GbE fat pipe switch module Figure 14 2 Example Monitor Start up Display for KAT4000 with 10 GbE 1 GbE Fat Pipe Switch Module U Boot 1 1 4 Apr 03 2007 15 20 30 1 3d Hardware initialization CPU 8548 E Version 2 0 0x80390020 Core E500 Version 2 0 0x80210020 Clock Configuration PU 999 MHz CCB 399 MHz DR 199 MHz LBC 49 MHz Board KAT4000 AMC Carrier Emerson Network Power Embedded Computing cPLD
186. command request and response respectively Figure 9 2 Extension Command Request Example B8 00 01 40 00 12 Data Pigeon Point IANA Command Code rqSeq 00 Bridge 00 NetFn Code 2 LUN 00 Figure 9 3 Extension Command Response Example BC 0001 00 0A 40 00 34 2 5 Data Pigeon Point IANA Completion Code Command Code rqSeq 00 Bridge 00 NetFn Code 2F LUN 00 MESSAGE BRIDGING The Message Bridging facility is responsible for bridging messages between various inter faces of the KAT4000 IPMC As required by the AMC O specification the KAT4000 IPMC supports message bridging between the IPMB 0 and IPMB L interfaces using the standard Send Message command 10007175 02 KAT4000 User s Manual System Management Message Bridging E KAT4000 User s Manual The KAT4000 IPMC also supports message bridging between the Payload Interface and IPMB O which allows the payload to send custom messages to and receive them from other shelf entities such as the shelf manager Message bridging is implemented using the Send Get Message commands and also via LUN 10 of the KAT4000 IPMC The following example illustrates how the Send Get Message and Get Address Info com mands can be used by the payload software to get the physical location of the board in the shelf The payload software sends the Get Address Info c
187. cters Port Commands Port Configuration Syntax Port Configuration lt portlist gt Description Show the configured and current speed duplex mode flow control mode and state for the port lt portlist gt Port list Default All ports Port Mode Syntax Port Mode lt portlist gt lt mode gt Description Set or show the speed and duplex mode for the port lt portlist gt Port list Default All ports lt mode gt Port speed and duplex mode Default Show configured and current mode 10hdx 10 Mbit s half duplex 10fdx 10 Mbit s full duplex 100hdx 100 Mbit s half duplex 100fdx 100 Mbit s full duplex 1000fdx 1 Gbit s full duplex auto Auto negotiation of speed and duplex Port Flow Control Syntax Port Flow Control lt portlist gt enable disable Description Set or show flow control mode for the port portlist Port list Default All ports 10007175 02 KAT4000 User s Manual mnm Appendix A serial Command Line Interface CLI Port State Port MaxFrame Port Statistics enable disable Enable disable flow control Default Show flow control mode Syntax Port State lt portlist gt enable disable Description Set or show the state for the port lt portlist gt Port list Default All ports enable disable Enable disable port state Default Show state Syntax Port MaxFrame lt portlist gt lt framesize gt reset Description Set or sho
188. ctrical requirements AMC synchronization clocks are sourced from or drive the ATCA backplane synchronization clock interface AMC clock interfaces are designed to work within the specified point to point M LVDS electrical requirements Clocks received from and transmitted to AMC sites have no specific Stratum level quality requirements A configuration of this board is available with no clock interface circuitry MT9045 AND MT9046 CLOCK SYNCHRONIZERS The MT9045 and MT9046 T1 E1 System Synchronizers contain a digital phase locked loop DPLL which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links The devices have reference switching and frequency holdover capa bilities to help maintain connectivity during temporary synchronization interruptions The MT9045 is compliant to Stratum 3 and Stratum 4 4E specifications The MT9046 can be used to provide a cost reduced clock interface compliant to only Stratum 4 4E specifica tions 10007175 02 Real Time Clock Section 11 Figure 11 1 The standard Real Time Clock RTC for the KAT4000 is provided 41700 device from STMicroelectronics This device has power sense circuitry and uses eight bytes of non vola tile RAM for the clock calendar function The M41T00 is powered from the 3 3 volt rail during normal operation and uses a single super capacitor which provides a minimum two
189. d Upper Critical Threshold 00 Upper Non Critical Threshold 00 Lower Non Recoverable 00 Threshold E KAT4000 User s Manual 10007175 02 Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Lower Critical Threshold 00 Lower Non Critical Threshold 00 Positive Going Threshold Hyst 00 Value Negative Going Threshold Hyst 00 Value OEM 00 ID String Length Code cb Table 16 2 Hot Swap SDR Description KAT4000 Records Value Parameter Status Record ID 000e SDR Version 51 Record 01 Full Sensor Record Record Length 36 Sensor Owner ID 00 Sensor Owner LUN 00 Sensor Number 00 Entity ID AMC Module Entity Instance 66 Sensor Initialization 67 Init Scanning Init Sensor Type Init Events Sensor Scanning enabled Event Generation enabled Sensor Capabilities 41 _ Ignore Sensor no _ Auto Re Arm enabled Sensor Hysteresis no hysteresis Sensor Threshold Access no threshold Event Message Control global disable only Sensor Type Event Reading Type Code ef Sensor Specific Assertion Event Mask O0ff Deassertion Event Mask 0000 Discrete Reading Mask ooff Sensor Units 1 00 _ Analog Data Format unsigned Rate Unit none
190. d _ Rate Unit none Modifier Unit none Percentage no Sensor Units 2 Base Unit 04 Volts Sensor Units 3 Modifier Unit 200 Unspecified Linearization 00 M 62 00 B 00 B Accuracy 00 Accuracy Accuracy Exp 00 R exp B Exp cO Analog Characteristic Flags 07 Nominal Reading 67 Normal Maximum 76 Normal Minimum 57 Sensor Maximum Reading Sensor Minimum Reading 00 Upper Non Recoverable 76 Threshold _ Upper Critical Threshold 00 Upper Non Critical Threshold 00 Lower Non Recoverable 52 Threshold Lower Critical Threshold 00 Lower Non Critical Threshold 00 KAT4000 User s Manual 10007175 02 Appendix B sensor Data Records KAT4000 Records _ Value Parameter Status continued Positive Going Threshold Hyst 03 Value Negative Going Threshold Hyst 03 Value OEM 00 ID String Type Length Code c5 Table B 11 CPU Volt SDR Description KAT4000 Records Value Parameter Status Record ID 0009 SDR Version 51 Sensor Model v1 5 Record Type 01 Full Sensor Record Record Length 33 Sensor Owner ID 00 Sensor Owner LUN 00 Sensor Number 00 Entity ID 03 Processor Entity Instance 60 Sensor Initialization 7f Init Scanning Init Sensor T
191. d and waits for the Graceful Reset command from the payload If the IPMC receives such a command before the payload communication time out time it sends the 0x00 completion code Success to the shelf manager Other wise the OxCC completion code is sent 10007175 02 KAT4000 User s Manual 9 23 System Management vendor Commands Table 9 23 Table 9 24 4000 User s Manual The IPMC does not reset the payload on receiving the Graceful Reset command or time out If the IPMC participation is necessary the payload must request the IPMC to perform a payload reset The Graceful Reset command is also used to notify the IPMC about the com pletion of the payload shutdown sequence Graceful Reset Command Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems ResponseData 1 Completion Code 2 4 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Diagnostic Interrupt Results The IPMC supports the Issue Diagnostic Interrupt feature of the FRU Control command The payload is notified about a diagnostic interrupt over the SIPL The payload is expected to return diagnostic interrupt results before the payload communication time out using the Diagnostic Interrupt Results command of the SIPL Diagnostic Interrupt Results Command Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID MS Byte first 0x00400A 1639
192. d allows the application programmer to get the status of the red out of service LED or to turn the LED on or off when an application fails to load fruled get fru id led id led state led function on off on time color fruled set fru id led id led function on off on time color Turns the red out of service LED on fruled set 0 1 Oxff 02 Turns the red out of service LED off fruled set 01002 ipmcfw The ipmcfw command restores the previous IPMC firmware from the backup IPMC firm ware stored in the controller The upgrade argument upgrades the IPMC firmware with the upgrade image held in memory ipmcfw restore upgrade source address gt sensor The sensor command probes reads and prints the sensor information from the IPMI 10007175 02 KAT4000 User s Manual E Monitor Environment Parameter Commands Definition sensor probe read dump Sensor probe prints out each sensor number and name sensor probe sensor number Sensor read prints out the sensor reading for sensor sensor read sensor number Sensor dump prints out the raw Sensor Data Record SDR information for sensor sensor dump sensor number ENVIRONMENT PARAMETER COMMANDS The monitor uses on board non volatile memory for the storage of environment parame ters Environment parameters are stored as ASCII strings with the following format Parameter Name Parameter Value Some environmen
193. d take steps to stop or restart the watch dog timer early in POST Otherwise the timer may expire later during POST or after the OS has booted Reset Watchdog Timer Command The Reset Watchdog Timer command is used for starting and restarting the Watchdog Timer from the initial countdown value that was specified in the Set Watchdog Timer com mand If a pretime out interrupt has been configured the Reset Watchdog Timer command will not restart the timer once the pretime out interval has been reached The only way to stop the timer once it has reached this point is via the Set Watchdog Timer command Reset Watchdog Timer Command Type Byte Data Field Request Data Response Data 1 Completion Code Set Watchdog Timer Command The Set Watchdog Timer command is used for initializing and configuring the watchdog timer The command is also used for stopping the timer If the timer is already running the Set Watchdog Timer command stops the timer unless the don t stop bitis set and clears the Watchdog pretime out interrupt flag see Get Message Flags command in the IPMI specification v1 5 IPMC hard resets system hard resets and the Cold Reset command also stop the timer and clear the flag This selects the timer use and configures whether an event will be logged on expiration This selects the time out action and pretime out interrupt type This sets the pretime out interval If the interval is set to zero the pretime out action
194. de bit MD2 out factory use only used for initial programming of the IPMC controller default 3 4 IPMC Mode bit MD1 N A out factory use only used for initial programming of the IPMC controller default 1 2 Boot from socket in boot from ROM socket default out boot from soldered flash 3 4 Ignore SROM in CPU ignores SROM default out CPU loads from SROM 5 6 Boot redirect see Register Map 7 4 and Register Map 7 15 in disabled The board only attempts to boot from the device specified by JP7 1 2 out enabled default The board cycles through the boot devices until a valid boot image is executed 7 8 Logic probe Reserved out default 9 10 Standalone SA mode in in ATCA standalone mode the IPMC disconnects IPMB 0 then activates deactivates the board itself out in ATCA normal mode the IPMC communicates with the shelf manager to activate deactivate the board default Note Jumper settings for JP7 pins 1 2 3 4 and 5 6 are not applicable to the no CPU KAT4000 board configuration EH KAT4000 User s Manual 10007175 02 Setup KAT4000 Circuit Board Figure 2 4 Jumper Fuse and Switch Locations Top P1 CPU JTAG COP
195. dress range starting at 0x40000 and ending at 0x80000 gt find 1 40000 80000 12345678 Searching from 0x00040000 to 0x00080000 Match found data 0x12345678 Adrs 0x00050a6c gt The command md displays the contents of memory starting at address The number of objects displayed can be defined by an optional third argument of objects The memory s numerical value and its ASCII equivalent is displayed md b w 1 address of objects In this example the md command is used to display thirty two 16 bit words starting at the physical address 0x80000 md w 80000 20 00080000 FLEE ftff PEEL TELE ffff 000800105 PLE TEEF EEFE 5 0045 8 00080020 FEET 10007175 02 4000 User s Manual 14 13 Monitor Memory Commands Definition Example Definition Definition Example 4000 User s Manual 000800305 ELEF LETE EELE PELE 2 mm The mm command modifies memory one object at a time Once started the command line prompts for a new value at the starting address After a new value is entered pressing ENTER auto increments the address to the next location Pressing ENTER without entering a new value leaves the original value for that address unchanged To exit the mm command enter a non valid
196. duct Serial Number Asset Tag FRU File ID Multi Record Area E Keying Records Description Version number of the overall FRU data structure defined by the IPMI FRU specification Version number of the Internal Use Area data structure defined by the IPMI FRU specification 0x100 bytes are allocated for customer use in this area Version number of the Board Information Area data structure defined by the IPMI FRU specification 0x01 English Variable expressed as the number of minutes since 12 00 AM on January 1 1996 Emerson Network Power Embedded Computing KAT4000 Variable formatted as 711A XXXX Variable formatted as 10 2 Variable for example 711 01 Version number of the Product Information Area data structure defined by the IPMI FRU specification 0x01 English Emerson Network Power Embedded Computing 4000 Variable formatted as 10 2 Not used same information is provided by the part number Variable formatted as 711A XXXX Not Used Variable for example p711a_c01 See E Keying 10007175 02 System Management F Keying Item Description continued Maximum Module Current 7 0 Amps Per Site Maximum Internal Current 15 0 Amps All Sites E KEYING This section details the interfaces governed by E keying and the protocols they support Specifically this includes the interfaces implemented by
197. e Optional Data for sensor and event type Checksum 2 Event generating sensors with a Threshold Event Reading Type 0x01 initiate an event message when a sensor reading crosses the defined threshold The default thresholds for a particular sensor are retrieved by sending the IPMC a Get Sensor Thresholds command The system management controller must send the IPMC a Get Sensor Reading command to retrieve the current sensor reading Please refer to the IPMI specification listed in Table 1 3 for complete details on using these commands 10007175 02 KAT4000 User s Manual 9 43 System Management FRU Inventory FRU INVENTORY The IPMC stores Field Replaceable Unit FRU information in its boot memory SROM The data structure contains information such as the product name part number serial number manufacturing date and E keying information Please refer to the IPMI specification for complete details on the FRU data structure Table 9 41 lists the general contents of the KAT4000 s FRU information Table 9 41 FRU Definitions KAT4000 User s Manual Item Common Header Version Internal Use Area Version Internal Use Size Board Information Area Version Language Code Manufacturing Date Time Board Manufacturer Board Product Name Board Serial Number Board Part Number FRU File ID Product Information Area Version Language Code Manufacturer Name Product Name Product Part Model Number Product Version Pro
198. e Thefollowing command types use port IDs versus the port number i e the physical number of the port Port numbers port port ID 1 used when discussing Ethernet switch ports For example VLAN port ID 1 is the same as Ethernet switch port 0 Table 1 General Command Types Command Type Description port Port identifier Any number in the range 1 26 lt portlist gt Comma and or dash separated port list This type can be used for specifying individual ports or a range of ports The keyword none can be used to specify an empty port list The keyword all can be used to specify all ports Example 1 3 8 12 lt macaddress gt MAC Address format hh hh hh hh hh hh hh hh hh hh hh hh or hhhhhhhhhhhh The hh is a hexadecimal number in the range 0x00 to OxFF Example 00 00 24 F1 02 03 vid VLAN ID Decimal number in the range 1 4095 The keyword all can be used to specify all VLAN IDs See note 10007175 02 KAT4000 User s Manual Appendix A serial Command Line Interface CLI Command Type Description continued lt vidlist gt Comma and or dash separated VLAN ID list This type can be used for specifying individual VLAN IDs or a range of VLAN IDs The keyword none can be used to specify an empty VLAN ID list Example 1 2 4 6 lt class gt Internal class of service 1 8 highest 1 lt grouplist gt Comma and or dash separated user group list This type can be used
199. e Upper Critical Threshold readable Upper Non Critical Threshold readable Lower Non Recoverable Threshold readable Lower Critical Threshold readable Lower Non Critical Threshold readable Sensor Units 1 00 Analog Data Format unsigned RateUnit none Modifier Unit none Percentage no Sensor Units 2 Base Unit 04 Volts Sensor Units 3 Modifier Unit 00 Unspecified Linearization 00 7b M Tolerance 00 B 00 00 Accuracy Accuracy Exp 00 c0 Analog Characteristic Flags 07 Nominal Reading cc Normal Maximum 46 Normal Minimum c2 Sensor Maximum ff Reading KAT4000 User s Manual 10007175 02 Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Sensor Minimum Reading 00 Upper Non Recoverable f4 Threshold Upper Critical Threshold 00 Upper Non Critical Threshold 00 E Lower Non Recoverable a3 Threshold Lower Critical Threshold 00 Lower Non Critical Threshold 00 E Positive Going Threshold Hyst 02 E Value Negative Going Threshold Hyst 02 Value OEM 00 ID String Length Code Table B 8 1 8 Volt SDR Description KAT4000 Records _ Value Parameter Status Record ID 0006 SDR Version 51 Record 01 Full Sensor Record Record Length _30 Sensor
200. e are sepa rate 2 connections to the and the processor and two ports each from the fat pipe switch module and the Ethernet Core switch A serial port and GbE port are provided for development purposes only 4000 User s Manual 10007175 02 Overview Functional Overview SS M Sejl FUNCTIONAL OVERVIEW The following block diagram provides a functional overview for the KAT4000 Figure 1 1 General System Block Diagram To Zone 3 gt Optional AMC x4 Single Width Half Full Extended Height PEX8524 AMC 0 Common lt Extended PCI Express Switch Optional PCle or GbE Update Channel To Zone 3 bo Optional 5 7376 local bus Ethernet Core Switch Layer 2 Optional E 5 a 5 8 5 Y MPC8548 4 SERDES Processor Zone 3 Connections gt IPMB Base High Speed High Speed Clock RTM I O abric A abric B Optional P10 23 J20 Zone3 10007175 02 KAT4000 User s Manual Overview Physical Memory PHYSICAL MEMORY MAP Fig 1 2 illustrates the 4000 memory map Figure 1 2 KAT4000 Memory Map
201. e gt reset ear enable disable none lt vid gt 10007175 02 Appendix A serial Command Line Interface CLI VLAN Aware lt portlist gt enable disable VLAN PVID lt portlist gt lt vid gt none VLAN Frame Type lt portlist gt all tagged Aggr Configuration Aggr Add portlist Aggr Delete portlist Aggr Lookup portlist Aggr Mode smac dmac xor User Group Configuration User Group Add lt grouplist gt lt portlist gt User Group Delete lt grouplist gt User Group Lookup lt grouplist gt QoS Configuration lt portlist gt QoS Mode portlist taglport diffserv QoS Default lt portlist gt lt class gt QoS Tagprio lt portlist gt lt tagpriolist gt lt class gt QoS DiffServ lt dscpno gt lt class gt QoS Userprio lt portlist gt lt tagprio gt QoS Shaper lt portlist gt disable lt rate gt QoS Policer lt portlist gt disable lt rate gt Mirror Configuration Mirror Port lt port gt Mirror Source lt portlist gt enable disable IP Configuration IP Setup lt ipaddress gt lt ipmask gt lt ipgateway gt lt vid gt IP Mode enable disable IP ARP IP Ping lt ip_addr gt lt number_of_passes gt Debug Read Register lt block gt lt subblock gt lt address gt Debug Write Register lt block gt lt subblock gt lt address gt lt value gt Debug PHY Read lt portlist gt lt address gt Debug PHY Write lt portlist
202. e jumper from JP7 pins 1 2 The monitor always resides in the top 512 KB block of NOR flash as shown in Table 14 3 Monitor Address per Flash Device Address Range hex _ Device 8 0000 Monitor Location in Flash Bank1 16 MB EOF8 0000 EOFF FFFF Monitor Location in Flash 16 MB E1F6 0000 E1F6 1000 Redundant Environment Variables EOF6 0000 EOF6 1000 Environment Variables Resetting Environment Variables To restore the monitor s standard environment variables execute the following commands and insert the appropriate data in the italicized fields KAT4000 1 0 gt moninit serial number noburn Press the s key on the keyboard during reset to force the default environment variables to be loaded See Environment Variables for more information Optionally save your settings KAT4000 1 0 gt saveenv Updating the Monitor via TFTP To update the monitor via TFTP ensure that an appropriate VLAN is set up in the Ethernet switch see the KAT4000 Quick Start Guide 10008585 xx and execute the following com mands inserting the appropriate data in the italicized fields If necessary edit your network settings KAT4000 1 0 gt setenv ipaddr 192 168 1 100 KAT4000 1 0 gt setenv gatewayip 192 168 1 1 KAT4000 1 0 gt setenv netmask 255 255 255 0 KAT4000 1 0 gt setenv serverip 10 64 16 168 KAT4000 1 0 gt setenv ethport all 10007175 02 KAT
203. e may cause damage to the board Refer to Table 7 3 for JP1 pin details Figure 3 2 Processor Diagram 3 3V 2 5V optional 33V PICO FUSE CPU 511 cpu CPU TDI CPU TDI CPU TCK CPU e TMS CPU TMS MP CES 5 11K 1 DEBUG SRESET rocessor 3_3V al DEBUG_HRESET CPU CKSTP OUT CPU CKSTP OUT CPU HRESET DEBUG HRESET CPU SRESET KSL DEBUG SRESET CPU TRST PLD DEBUG TRST Figure 3 3 Processor Header 3 14 KAT4000 User s Manual 10007175 02 Central Processing Unit No Processor Configuration Table 3 6 Processor JTAG COP Pin Assignments P1 CPU CKSTP OUT CPU TCK CPU TDI CPU TDO CPU TMS DEBUG HRESET DEBUG SRESET DEBUG_TRST Pin Signal Pin Signal 1 CPU_TDO 2 Not connected 3 CPU_TDI 4 DEBUG TRST 5 Not connected 6 JT_3_3V fused 7 CPU TCK 8 Not connected 9 CPU TMS 10 Not connected 11 DEBUG_SRESET 12 GND 13 DEBUG_HRESET 14 Not connected 15 CPUCKSTPOUT 16 GND Checkstop Output when asserted this output signal indicates that the CPU has detected a checkstop condition and has ceased operation Test Clock Input scan data is latched at the rising edge of this signal Test Data Input this signal acts as the input port for scan instructions and data Test Data Output this signal acts as the output port for
204. ease refer to the Vitesse web site for documentation http www vitesse com 10007175 02 Common Switch Region Ethernet Core Switch optional Figure 4 2 VSC7376 GbE Switch Block Diagram Frame Bus one m eem irs port Shared RX and Shared RX and FIFO FIFO Analyzer Arbiter X X Y Y x Policer Shaper Shaper o o 9 9 8051 CPU i RS232 Interface 5 Y Y Serial Interface RS232 Categorizer Rewriter Categorizer Rewriter Parallel Interface MII Management Interface A Control Status MIIM Registers gt Y GPIO p 5 10 100 1000 10 100 1000 MAC MAC SGMII SerDes SGMII SerDes SI or iCPU RAM Flash Switch Configuration The processor has a local bus connection to the Ethernet core switch and the fat pipe switch module reads and writes directly to the registers On power up the configuration values are read from flash and the chip is initialized To configure the switch see the KAT4000 Quick Start Guide 10008585 For the no CPU KAT4000 Ethernet switch configuration see Appendix A or the KAT4000 Quick Start Guide for the No CPU Carrier Board 10008506 High Speed Serial Data Path Configuration The KAT4000 design implements several types of high speed serial protocols Gbe sRIO and PCle Prope
205. ect 4 B1 TTIP3 _ B1 TRING3 12V RTM no connect 5 1 4 B1 TRING4 connect no connect 6 B1 TTIP5 1 TRINGS B1 RTIPS B1 RRINGS 7 B1 TTIP7 B1 TRING7 B1 RTIP7 B1 RRING7 8 connect no connect connect connect 9 no connect no connect B2 TTIP2 B2_TRING2 10 B2 TTIP1 B2 TRING1 2 RTIP1 B2 RRING1 E KAT4000 User s Manual 10007175 02 Connectors 7 Figure 12 3 Zone 3 Connector 33 1 6 4 m NIE EE SIE EE HE NI gt Table 12 7 Zone 3 Connector 33 Pin Assignments B AMC3 C AMC2 D 1 1 B4 CONSOLE TX B3 CONSOLE TX B2 CONSOLE TX B1 CONSOLE TX 2 B4 CONSOLE RX B3 CONSOLE B2 CONSOLE RX B1 CONSOLE 3 GND GND GND GND 4 B4 LEDCTRL TX LEDCTRL TX B2 LEDCTRL TX B1 LEDCTRL TX 5 B4 LEDCTRL RX LEDCTRL 2 LEDCTRL RX LEDCTRL 6 12V RTM IPMB RTM SDA 3 3VMPRTM IPMB_RTM_SCL_ BUFF BUFF 10007175 02 KAT4000 User s Manual 12 7 blank page E KAT4000 User s Manual 10007175 02 Section 13 Rear Transition Module The KAT Z3DB is an optional single slot ATCA Rear Transition Module RTM providing rear shelf I O access for the KAT4000 This RTM is for development purposes only It has not been tested for EMI EMC or ESD Th
206. ectors 7 Spare AMC site I O will all be routed to Zone 3 as generic differential pairs carrying thing from SerDes to TDM signals to single ended GPIO signals and is capable of data rates as high as 3 125 Gbps Table 12 4 Zone 3 Connector 30 Pin Assignments Row AB CD 1 FP CONN TX FP CONN RX B3 4 B3_RRING4 2 B3_TTIP6 B3_TRING6 B3_RTIP6 B3_RRING6 3 B3_TTIP8 B3 TRING8 B3 RTIP8 B3 RRING8 4 RTM_ENET_TX RTM_ENET_TX no connect no connect 5 RTM_ENET_RX RTM_ENET_RX B4_RTIP2 B4_RRING2 6 HOST_CONN_TX HOST_CONN_RX RTM_ID1 PB_RST 7 B4_TTIP3 B4_TRING3 IPMC_RST_PB RTM_IDO 8 B4_TTIP4 B4_TRING4 RTM_ID3 no connect 9 B4 TTIP5 B4 TRING5 B4 RTIP5 B4 RRING5 10 B4 TTIP7 B4 TRING7 BA RTIP7 B4 RRING7 Row EF GH 1 B3 TTIP5 B3 TRING5 B3 5 B3 RRING5 2 B3 TTIP7 B3 TRING7 B3 RTIP7 B3 RRING7 3 GIG6_TX GIG6_TX no connect no connect 4 no connect no connect B4_TTIP2 B4_TRING2 5 B4_TTIP1 B4_TRING1 B4_RTIP1 B4_RRING1 6 GIG6_RX GIG6_RX RTM_PS1_CONN AMC PP 7 B4 RTIP3 4 RRING3 RTM ID2 no connect 8 no connect no connect B4 RTIPA B4 RRINGA 9 B4_TTIP6 B4_TRING6 B4_RTIP6 B4_RRING6 10 B4 TTIP8 B4 TRING8 B4 RTIP8 B4 RRING8 Table 12 5 Zone 3 Connector 31 Pin Assignments Row AB CD 1 no connect no connect RTM_GPIO7 RTM_GPIO6 2 B2_TTIP3 B2_TRING3 RTM_GPIO5 RTM_GPIO4 3 B2_TTIP4 B2_TRING4 no connect no connect 4 B2 TTIP5 B2 TRING5 B2 RTIP5 B2 RRING5 5 B2 TTIP7 B2 TRING7 B2 RTIP7 B2 RRING7 6 RTM_RX0 RTM
207. ed on expiration when don t log bit Ob 000b none 001b SMI 010b NMI Diagnostic Interrupt 011b Messaging Interrupt this is the same interrupt as allocated to the messaging interface 100b 111b reserved 3 reserved 2 0 time out action 000b no action 001b Hard Reset 010b Power Down 011b Power Cycle 100b 111b reserved Pretime out interval in seconds 1 based 10007175 02 System Management IPMC Watchdog Timer Commands Type Byte DataField continued Request Data 4 Timer Use Expiration flags clear continued Ob leave alone 1b clear timer use expiration bit 7 reserved 6 reserved 5 OEM 4 SMS OS 3 OS Load 2 Monitor POST 1 Monitor FRB 2 0 reserved 5 Initial countdown value Isbyte 100 ms count 6 Initial countdown value msbyte Response 1 Completion Code 1 Potential race conditions exist with implementation of this option If the Set Watchdog Timer command is sent just before a pretime out interrupt or time out is set to occur the time out could occur before the command is executed To avoid this condition it is recommended that software set this value no closer than three counts before the pretime out or time out value is reached Get Watchdog Timer Command This command retrieves the current settings and present countdown of the watchdog timer The Timer Use Expiration flags in byte 5 retain their states across system resets and system power cycles With the e
208. efault envi ronment variables When BDRR is enabled see Table 2 3 and the monitor is loaded to both banks of flash see on page 14 24 the hardware watchdog timer may cause a reset that will then boot from the next flash bank see Fig 7 1 At power up or after a reset the monitor runs diagnostics and reports the results in the start up display see Fig 14 1 During the power up sequence the monitor configures the board according to the environment variables see Environment Variables on page 14 28 If the configuration indicates that autoboot is enabled the monitor attempts to load the application from the specified device If the monitor is not configured for auto boot or a failure occurs during power up the monitor enters normal command line mode Also the optional e keying environment variable enables connections at power up for debug purposes only to the Update Channel and payload ports that go off the KATA000 See Table 14 7 for more information 10007175 02 KAT4000 User s Manual m Monitor Command Line Features The monitor command prompt in Fig 14 1 is the result of a successful hardware boot of the KAT4000 with a GbE fat pipe switch module Figure 14 1 Example Monitor Start up Display for KAT4000 with GbE Fat Pipe Switch Module U Boot 1 1 4 Jan 9 2007 11 15 43 1 01 Hardware initialization gt CPU 8548 E Version 2 0 0x80390020 Core E500 Version 2 0 0x80210020 Clo
209. endix A serial Command Line Interface CLI VLAN PVID VLAN Frame Type lt portlist gt Port list Default All ports enable disable Enable disable VLAN awareness Default Show awareness Syntax VLAN PVID lt portlist gt lt vid gt none Description Set or show the port VLAN ID Untagged frames received on the port will be classified to this VLAN ID Frames classified to this VLAN ID will be sent untagged on the port lt portlist gt Port list Default All ports lt vid gt Port VLAN ID 1 4095 Default Show The none option can be used for trunk links Syntax VLAN Frame Type lt portlist gt all tagged Description Set or show the accepted frame type for the port lt portlist gt Port list Default All ports all tagged Accept all or only tagged Default Show frame type Aggregation Trunking Commands Aggregation Configuration Aggregation Add Aggregation Delete Aggregation Lookup Syntax Aggr Configuration Description Shows the aggregation groups and the aggregation mode Syntax Aggr Add lt portlist gt Description Add link aggregation group including ports portlist Aggregation port list Syntax Aggr Delete portlist Description Delete link aggregation group portlist Port list Aggregations including any of the ports will be deleted Syntax Aggr Lookup portlist 10007175 02 KAT4000 User s Manual
210. ent Generation enabled Sensor Capabilities 69 Ignore Sensor no Auto Re Arm enabled Sensor Hysteresis hysteresis is settable readable Sensor Threshold Access threshold is settable readable Event Message Control global disable only Sensor Type 01 Temperature Event Reading Type Code 01 Threshold 10007175 02 KAT4000 User s Manual Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Assertion Event Mask 7 95 Lower Non Recoverable Threshold comparison returned Lower Critical Threshold comparison returned Lower Non Critical Threshold comparison returned Upper Non Recoverable Going High supported Upper Critical Going High supported Upper Non Critical Going High supported Lower Non Recoverable Going Low supported _ Lower Critical Going Low supported Lower Non Critical Going Low supported Deassertion Event Mask 7a95 Lower Non Recoverable Threshold comparison returned Lower Critical Threshold comparison returned Lower Non Critical Threshold comparison returned Upper Non Recoverable Going High supported Upper Critical Going High supported Upper Non Critical Going High supported Lower Non Recoverable Going Low supported Lower Critical Going Low supported Lower Non Critical Going Low supported Discrete Reading Mask Upper Non Recoverable Threshold settable Upper Critical Threshold settable Upper Non Critical Threshold settable Lower Non Recoverable Threshold settable Lower Critical Thr
211. er Status continued Sensor Initialization 5d Init Scanning Init Sensor Init Hysteresis Init Thresholds Sensor Scanning enabled Sensor Capabilities 69 Ignore Sensor no Auto Re Arm enabled Sensor Hysteresis hysteresis is settable readable Sensor Threshold Access threshold is settable readable Event Message Control global disable only 02 Voltage Event Reading Type Code 01 Threshold Assertion Event Mask 0800 Upper Non Recoverable Going High supported Deassertion Event Mask _ 4800 Lower Non Recoverable Threshold comparison returned Upper Non Recoverable Going High supported Discrete Reading Mask 3838 Upper Non Recoverable Threshold settable Upper Critical Threshold settable Upper Non Critical Threshold settable Upper Non Recoverable Threshold readable Upper Critical Threshold readable Upper Non Critical Threshold readable Sensor Units 1 _00 Analog Data Format unsigned Rate Unit none Modifier Unit none Percentage no Sensor Units 2 Base Unit 04 Volts Sensor Units 3 Modifier Unit 00 Unspecified Linearization 00 06 M Tolerance 00 B 00 00 Accuracy Accuracy Exp 00 Rexp B Exp 0 Analog Characteristic Flags 07 Nominal Reading c8 Normal Maximum d6 Normal Minimum 00 Sensor Maximum Reading fe 10007175 02 KAT4000 User s Manual B 37 Appendix B sensor Data
212. er 3 3 8548 Hardware Implementation Dependent Register 1 HID1 3 8 Register 3 4 CPU Machine State Register MSR 3 9 Register 5 1 Product Version Register PIDV at 0 00 5 7 Register 5 2 Scratch Register SCR 0 01 5 7 5 3 I2C Register ZC 0 02 2 sies hr ether eher hr rtr hahere 5 7 Register 5 4 Signal Detect Register SDET at 0 03 5 8 Register 5 5 Switch Reset Register SRST at 0X04 5 8 Register 5 6 Module Status Register STAT at 0 05 5 9 Register 5 7 Switch GPIO Register GPIO 0 06 5 9 Register 5 8 Register GPLED 0 07 5 10 Register 5 9 Product ID Version Register PIDV at 0 00 5 16 Register 5 10 Scratch Register SCR at OXO1 5 17 Register 5 11 2 Register IC at Ox02 2 5 17 Register 5 12 Reserved Register 1 at 0X03 5 18 Register 5 13 Switch Reset Register SRST at 0 04 5 18 Register 5 14 Module Status Register ST
213. erprio Description Show the configured QoS mode default class and DSCP mapping for the port lt portlist gt Port list Default All ports Syntax QoS Mode lt portlist gt tag port diffserv Description Set or show the QoS mode for the port lt portlist gt Port list Default All ports diffserv Enable tag port or IP differentiated services class of service for the port Default Show mode Syntax QoS Default lt portlist gt lt class gt Description Set or show the default class In tag mode the default class is used for untagged frames In port mode the default class is used as the port priority In diffserv mode the default class is used for non IP frames lt portlist gt Port list Default All ports lt 1 gt 1 Internal class of service Default Show class Syntax QoS Tagprio lt portlist gt lt tagpriolist gt lt class gt Description Set or show the VLAN user priority mapping lt portlist gt Port list Default All ports lt tagpriolist gt VLAN user priority list 0 7 Default All user priorities lt class gt Internal class of service Default Show class Syntax QoS DiffServ lt dscpno gt lt class gt Description Set or show the IP Differentiated Services mapping dscpno IP DSCP list 0 63 Default All DSCP values lt 1 gt 1 Internal class of service Default Show class Syntax QoS U
214. errupt from regis ters 0xa8 or OxbO The hardware will issue resets to the clock synchronizers for 10ms Software must wait at least 10ms before accessing these devices Default register values are shown in the bottom row of the register table Reset Command Register 1 RCR1 at Oxfc40 0024 7 6 5 4 3 2 1 0 CPUH CSR1 CSR2 CSR3 PCIE 2 FSHR CER 0 0 0 0 0 0 0 0 CPU Hard Reset 1 Reset 0 Noreset default 10007175 02 KAT4000 User s Manual CPLD Boot and Reset Registers CSR1 Clock Synchronizer 1 Reset 1 Reset 0 Noreset default CSR2 Clock Synchronizer 2 Reset 1 Reset 0 Noreset default CSR3 Clock Synchronizer 3 Reset 1 Reset 0 Noreset default PCIE PCI Express Reset 1 Reset 0 Noreset default I2C 12 Bus Reset 1 Reset 0 Noreset default FSHR NOR Flash Reset 1 Resets NOR flash to a known state 0 Noreset default CER CoreEthernet Reset 1 Reset 0 Noreset default Reset Command Register 2 RCR2 Set only one bit in this register at a time If reset when in a locked state a clock synchronizer will issue a loss of lock interrupt To prevent this mask the interrupt from registers 8 OxaC or Oxb0 The hardware will issue resets to the clock synchronizers for 10ms Software must wait at least 10ms before accessing these devices Default register values are shown the bottom row of the register table Register 7 14 Reset Command Register 2
215. ers are reserved MISCELLANEOUS REGISTERS LED Control Register LEDR The KAT4000 has multiple light emitting diodes LED for status and software develop ment see Section LEDs for LED location and description The LED Control register con trols the card s LEDs Setting 1 the bit enables the LED By default the LEDs are not set Default is Default register values are shown in the bottom row of the register table LED Control Register LEDR at Oxfc40 001c 7 6 5 4 3 2 1 0 CPUR CPUG R LDM DBG3 DBG2 DBG1 DBGO 1 1 1 0 0 0 0 CPU Red LED 1 On 0 Off CPU Green LED 1 On 0 Off Reserved 10007175 02 KAT4000 User s Manual CPLD Miscellaneous Registers LDM DBG3 0 Register 7 7 PRB IROM BFS Register 7 8 KAT4000 User s Manual LED Debug Mode Setting 0 puts the four debug LEDs into user mode allowing software to turn them off on individually By default they are in hardware debug mode and are connected to specific internal external signals 1 Debug mode probes are enabled default 0 Debug mode probes are disabled Debug LEDs 1 On 0 Off Jumper Settings Register JSR The read only Jumper Settings register indicates miscellaneous external settings Default register values are configuration dependent Jumper Settings Register JSR at Oxfc40 0018 7 6 5 4 3 2 1 0 PRB IROM BFS R TID3 TID2 TID1 TIDO Logic
216. ese bits are cleared on initial power up of the KAT4000 Please refer to the MPC8548 PowerQuicc Ill Integrated Communications Processor Reference Manual for more detailed descriptions of the HIDx registers The following register map summarizes HIDO for the MPC8548 processor Register 3 2 MPC8548 Hardware Implementation Dependent Register 0 HIDO 32 33 39 40 41 42 43 47 EM reserved DOZ NAP reserved CP E 48 49 50 51 55 56 57 58 62 63 R TB STB reserved EN DCF reserved NOP EN CLK MAS7 A TI EMCP Enable Machine Check Pin masks further machine check exceptions caused by assertion of KAT4000 User s Manual MCP 0 MCP is disabled 1 MCP is enabled 10007175 02 Central Processing Unit Microprocessor Core e500 SLP TBEN STBCLK EN MAS7 DCFA NOPTI Reserved should be cleared Doze power management mode 0 Doze mode disabled 1 Doze mode enabled power management mode 0 Nap mode disabled 1 Nap mode enabled Sleep power management mode enable 0 Sleep mode disabled 1 Sleep mode enabled Time Base Enable 0 Time base disabled no counting 1 Time base enabled Select Time Base Clock functions if the time base is enabled 0 Time base is based on the processor clock 1 Time base is based on the RTC input Enable MAS7 update enables updating MAS7 by tibre and tibsx 0 MAS7 is not updated 1 MASZ is updated Data Cache Flush Assist forces data cache to ignore invalid sets on miss
217. eshold comparison returned Upper Non Recoverable Going High supported Lower Non Critical Going Low supported Discrete Reading Mask 3f3f Upper Non Recoverable Threshold settable Upper Critical Threshold settable Upper Non Critical Threshold settable Lower Non Recoverable Threshold settable Lower Critical Threshold settable Lower Non Critical Threshold settable Upper Non Recoverable Threshold readable Upper Critical Threshold readable Upper Non Critical Threshold readable Lower Non Recoverable Threshold readable Lower Critical Threshold readable Lower Non Critical Threshold readable 10007175 02 KAT4000 User s Manual Appendix B sensor Data Records KAT4000 Records Parameter Status continued Sensor Units 1 00 Analog Data Format unsigned Rate Unit none Modifier Unit none Percentage no Sensor Units 2 Base Unit 04 Volts B _ Sensor Units Modifier Unit 00 Unspecified _ Linearization 00 M 06 M Tolerance 00 B 00 B Accuracy 00 Accuracy Accuracy Exp 00 R exp B Exp 0 Analog Characteristic Flags 07 Nominal Reading c8 Normal Maximum 46 Normal Minimum ba Sensor Maximum Reading ff Sensor Minimum Reading 00 Upper Non Recoverable 10 Threshold Upper Critical Threshold 200
218. eshold settable Lower Non Critical Threshold settable Upper Non Recoverable Threshold readable Upper Critical Threshold readable Upper Non Critical Threshold readable Lower Non Recoverable Threshold readable Lower Critical Threshold readable Lower Non Critical Threshold readable Sensor Units 1 80 Analog Data Format twos complement Rate Unit none Modifier Unit none Percentage no Sensor Units 2 Base Unit 01 Degrees C Sensor Units 3 Modifier Unit 00 Unspecified Linearization 00 M 64 M Tolerance 00 B 00 E KAT4000 User s Manual 10007175 02 Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued B Accuracy 00 Accuracy Accuracy Exp 00 E R exp B Exp Analog Characteristic Flags 07 Nominal Reading 16 _ Normal Maximum 37 Normal Minimum 00 _ Sensor Maximum Reading 7f _ Sensor Minimum Reading 280 Non Recoverable 4b Threshold _ Upper Critical Threshold 41 Upper Non Critical Threshold 237 Lower Non Recoverable f Threshold Lower Critical Threshold 6 Lower Non Critical Threshold fb Positive Going Threshold Hyst 02 Value Negative Going Threshold Hyst 02 Value 00 ID String Type Length Code cb Table 13 Outflow Temp SDR Description KAT4000
219. espec tively CLOCK3 Connects to the PCI Express clock SERIAL 12 CLOCK To IPMC IC buffer SERIALI C DATA ADDRESS IPMC I C buffer TEST CLOCK INPUT JTAC clocks state information and test data into and out of the device during operation of the TAP TEST DATA INPUT JTAC serially shifts test data and test instructions into the device during TAP operations TEST DATA OUTPUT serially shifts test data and test instructions out of the device during TAP operations TEST MODE SELECT JTAC controls the state of the TAP controller input signal in the device TEST RESET JTAG is the asynchronous reset for the JTAG controller input signal 10007175 02 KAT4000 User s Manual AMC Sites Pin Assignments PIN ASSIGNMENTS Each connector has 170 pins see Fig 8 1 and supports PCle and GbE signals the Ethernet core switch the PCI Express switch the fat pipe switch module user I O configuration sig nals and Zone 3 Table 8 1 B1 B4AMC Pin Assignments Pin B1 B4 Signal Pin B1 B4 Signal 1 2 12V 3 Bn_PS1 4 33V 5 33V 6 Reserved 7 GND 8 Reserved 9 12V 10 GND EE GlGn_RX 12 GIGn_RX GND 14 GIGn_TX 15 GIGn_TX 16 GND 17 33V _ 18 12V _19 GND 220 Bn_P1_RX 21 Bn P1 RX 122 GND 23 Bn_P1_TX 24 P1 TX 25 GND 26 33V 27 12V 28 GND _29 _ Bn_SATA1_RXD 30 Bn_SATA
220. ess threshold is settable readable Event Message Control global disable only Sensor Type 02 Voltage Event Reading Type Code 01 Threshold Assertion Event Mask 0800 Upper Non Recoverable Going High supported 10007175 02 KAT4000 User s Manual B 43 Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Deassertion Event Mask 4800 Lower Non Recoverable Threshold comparison returned Upper Non Recoverable Going High supported Discrete Reading Mask 3838 Upper Non Recoverable Threshold settable Upper Critical Threshold settable _ Upper Non Critical Threshold settable _ Upper Non Recoverable Threshold readable Upper Critical Threshold readable Upper Non Critical Threshold readable Sensor Units 1 00 Analog Data Format unsigned Rate Unit none Modifier Unit none Percentage no Sensor Units 2 Base Unit 04 Volts Sensor Units 3 Modifier Unit 00 Unspecified Linearization 00 M 06 M Tolerance 00 B 00 B Accuracy 00 Accuracy Accuracy Exp 00 R exp B Exp e0 Analog Characteristic Flags 07 Nominal Reading c8 Normal Maximum d6 Normal Minimum 00 Sensor Maximum fe Reading Sensor Minimum Reading 00 Upper Non Recoverable 10 Threshold Upper Critical Threshold 00 Upper Non Critical
221. essage see Table 9 4 is similar to a IPMI request message The main dif ference is that the seventh byte contains the Completion Code and the eighth byte and beyond hold data received from the controller rather than data to send to the controller Also the Slave Address and Logical Unit Number for the requester and responder are swapped Format for IPMI Response Message Byte Bits 7 6 5 4 3 2 1 0 d 2 rqLUN 3 Checksum 4 rsSA 5 rsSeq rsLUN 6 Command 7 Completion Code 8 N Data N 1 Checksum SIPL PROTOCOL The KAT4000 IPMC supports the Serial Interface Protocol Lite SIPL protocol It supports raw IPMI messages in SIPL and handles these messages the same way as it handles IPMI messages from the IPMB O bus except that the replies route to either the payload or serial debug interface Messages are entered as case insensitive hex ASCII pairs separated optionally by a space as shown in the following examples 18 00 22 newline 180022 newline The IPMC does not however support SIPL ASCII text commands as defined by the IPMI specification The 4000 IPMC does support Pigeon Point Systems extension commands imple mented as OEM IPMI commands These commands use Network Function Codes 2E 2F hex and the message body is transferred similarly to raw IPMI messages as described previously 10007175 02 System Management Message Bridging The following figures show an example of an extension
222. et Sensor Events Sensor Event 04 05 00 28 Get Sensor Reading Sensor Event 04 05 00 2D Set Sensor Type Sensor Event 04 05 00 2E Get Sensor Type Sensor Event 04 05 00 2F Get Device ID Application 06 07 00 01 Broadcast Get Device ID Application 06 07 00 01 Cold Reset Application 06 07 00 02 Warm Reset Application 06 07 00 03 Get Self Test Results Application 06 07 00 04 Get Device GUID Application 06 07 00 08 Reset Watchdog Timer Application 06 07 00 22 Set Watchdog Timer Application 06 07 00 24 Get Watchdog Timer Application 06 07 00 25 Send Message Application 06 07 00 34 Get FRU Inventory Area Info Storage OA OB 00 10 Read FRU Data Storage OB 00 11 Write FRU Data Storage OA OB 00 12 Get PCIMG Properties PICMG 2C 2D 00 00 Get Address Info PICMG 2C 2D 00 01 FRU Control PICMG 2C 2D 00 04 Get FRU LED Properties PICMG 2C 2D 00 05 Get LED Color Capabilities PICMG 2C 2D 00 06 Set FRU LED State PICMG 2C 2D 00 07 Get FRU LED State PICMG 2C 2D 00 08 Set IPMB State Command PICMG 2C 2D 00 09 Set FRU Activation Policy PICMG 2C 2D 00 Get FRU Activation Policy PICMG 2C 2D 00 OB Set FRU Activation PICMG 2C 2D 00 0C Get Device Locator Record ID PICMG 2C 2D 00 oD Get Port State PICMG 2C 2D 00 OE Set Port State PICMG 2C 2D 00 OF Compute Power Properties PICMG 2C 2D 00 10 Set Power Level PICMG 2C 2D 00 11 E KAT4000 User s Manual 10007175 02 System Management standard Commands Command continued netFn L
223. f board has control of the bus 0 In control 1 No control 1 Release request a board to release control of the bus 0 1 Refused 2 No control 2 Force board to release control of bus immediately 0 Ack 1 No control 3 Bus Free informs board that the bus is available 0 Accept 1 Not needed Command Types for Board to Shelf Manager 0 Request to seize control of the bus 0 Grant 1 Busy 2 Defer 3 Deny 1 Relinquish control of the bus Shelf Manager can reassign control of bus 0 1 Error 2 Notify Shelf Manager that control of the bussed resource has been transferred to this board from another authorized board 0 Ack 1 Error 2 Deny Bused Resource ID 0 Metallic Test Bus pair 1 1 Metallic Test Bus pair 2 2 Synch clock group 1 CLK1A and CLK1B pairs 3 Synch clock group 2 CLK2A and CLK2B pairs 4 Synch clock group 3 CLK3A and CLK3B pairs Status 0 Ack Shelf Manager acknowledges that board has control 1 Error same as Ack but Shelf Manager believes board should not have been given control of the resource optional 2 Deny Shelf Manager denies control of resource by the board Completion Code PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Graceful Reset Command The IPMC supports the Graceful Reboot option of the FRU Control command On receiving such a command the IPMC sets the Graceful Reboot Request bit of the IPMC status sends a status update notification to the payloa
224. for PCIE WAIT See Table 14 6 for default environ ment variables settings 10007175 02 Monitor Basic Operation Figure 14 3 Power up Reset Sequence Flowchart OBERE Y RESET Y Y i Initialize HIDO Init serial port per Enumerate PCI Initialize MSR baudrate 15 module a Yes Per enumerate environment var root complex es environment LED 0011 variable Y Relocate the 8548 Y CCSRBDR base Display version Perform board address string diagnostics per _____ _ powerondiags environment var Y Y Map LAWBARs Display CPU TLBs board and bus X Speed Dis play board LED 0100 serial number 4 Invalidate the Y Y L2 cache mr LED 0001 iro Enable MPC8548 external interrupts Y Initialize Eth t Init SDRAM Clear Invalidate and Pel IR ports enable the L1 per clearmem and elocate IRQ data cache configure per ecc handlers and environment vars IRQ traps 4 Initialize Y disk on chip Setup initial stack Configure dcache and data region per cachemode Y in cache and dcache environment vars Initialize core T Ethernet switch if installed Relocate U Boot to RAM Configure the LED 0110 Configure icache MPC8548 devi
225. fthe help command is issued for a specific command the command syntax and a description of the command are shown The command hierarchy and the help utility are demonstrated in the following example enter Commands at top level System System commands Console Console commands Port Port commands MAC MAC table commands VLAN VLAN commands Aggregation Aggregation Trunking commands User Group User Group commands QoS QoS commands Mirror Mirror commands IP IP commands Debug Debug commands gt console enter Console enter Commands at Console level Console Configuration Console Password password Console Timeout lt timeout gt 10007175 02 KAT4000 User s Manual nm Appendix A serial Command Line Interface CLI Note KAT4000 User s Manual Console Prompt prompt string gt Console password Syntax Console Password lt password gt Description Set or display console password The empty string disables the password check lt password gt Password string of up to 16 characters Console Command Hierarchy The CLI is hierarchical with two levels top level and group level The group level consists of the following groups System Console Port MAC e VLAN Aggregation UserGroup QoS Mirror e IP Debug Test The Test group is for Emerson internal use only At top level enter a command by giving the full c
226. ful substances in electrical and electronic equipment Effective July 1 2006 RoHS restricts the use of six substances cadmium Cd mercury Hg hexavalent chromium Cr VI polybrominated biphenyls PBBs polybrominated diphenyl ethers 10007175 02 KAT4000 User s Manual Overview Additional Information PBDEs and lead Pb Configurations that are RoHS compliant are built with lead free sol der Configurations that are 5 of 6 are built with tin lead solder per the lead in solder RoHS exemption To obtain a certificate of conformity CoC for the KAT4000 or other modules send an e mail to sales artesyncp com or call 1 800 356 9602 Have the part number s e g CO00 for your configuration s available when contacting Emerson Terminology and Notation Active low signals An active low signal is indicated with an asterisk after the signal name Byte word Throughout this manual byte refers to 8 bits word refers to 16 bits and long word refers to 32 bits double long word refers to 64 bits PLD This manual uses the acronym PLD as a generic term for programmable logic device also known as FPGA CPLD EPLD etc Radix 2 and 16 Hexadecimal numbers end with a subscript 16 or begin with Ox Binary numbers are shown with a subscript 2 Technical References Further information on basic operation and programming of the KAT4000 components can be found in the following documents Table 1 3 Technical References
227. g 8 8 885 RES H E 8 B uo PR a E a 8B ome 5 fie B ad 8 E E d BET di a of ieee 227 ET A ger 8 50g B uim af 8 AAAA DONA AAA 10007175 02 KAT4000 User s Manual 2 3 Setup KAT4000 Circuit Board Front Panel The front panel shown in Fig 2 3 consists of four single width mid size Advanced Mezza nine Card AMC sites double width and compact modules can be accommodated a hot swap LED an out of service LED two user LEDs see LEDs on page 2 10 for more informa tion and a reset switch Note When using a compact AMC module the module must have a front panel that fully covers the front opening of the KAT4000 to maintain EMC compliance Figure 2 3 KAT4000 Front Panel 5 Front Panel Hot Out of service Reset qnd user LEDs 2 Switch ys AMC4 B EMERSON KAT4000 Note The electromagnetic compatibility EMC tests used a KAT4000 model that includes a front panel assembly from Emerson Caution For applications where the KAT4000 is provided without a front panel or where the front panel has been removed your system chassis enclosure must provide the required electromagnetic interference EMI shielding to maintain CE compliance Connectors The KAT4000 circuit board has various con
228. g High supported Lower Non Critical Going Low supported Discrete Reading Mask 3f3f Upper Non Recoverable Threshold settable Upper Critical Threshold settable Upper Non Critical Threshold settable Lower Non Recoverable Threshold settable Lower Critical Threshold settable Lower Non Critical Threshold settable Upper Non Recoverable Threshold readable Upper Critical Threshold readable Upper Non Critical Threshold readable Lower Non Recoverable Threshold readable Lower Critical Threshold readable Lower Non Critical Threshold readable 10007175 02 KAT4000 User s Manual B 53 Appendix B sensor Data Records KAT4000 Records Parameter Status continued Sensor Units 1 00 Analog Data Format unsigned Rate Unit none Modifier Unit none Percentage no Sensor Units 2 Base Unit 04 Volts B _ Sensor Units Modifier Unit 00 Unspecified _ Linearization 00 M M Tolerance 00 00 B Accuracy 00 Accuracy Accuracy Exp 00 R exp B Exp cO Analog Characteristic Flags 07 Nominal Reading Normal Maximum cc Normal Minimum b9 Sensor Maximum Reading ff Sensor Minimum Reading 00 Upper Non Recoverable e9 ES Threshold Upper Critical Threshold 200 Non Critical Threshold 00
229. ge The number of times pulses are blanked subtracted neg ative calibration or split added positive calibration depends on this five bit byte Adding counts accelerates the clock and subtracting counts slows the clock down Don tcare bit 10007175 02 KAT4000 User s Manual 11 3 blank page KAT4000 User s Manual 10007175 02 Connectors Section 12 Figure 12 1 Table 12 1 There are multiple connectors on the KAT4000 Reference Fig 2 1 and Fig 2 2 for their loca tions Whether individual backplane connectors are populated on the KAT4000 depends on the specific product configuration The backplane connectors Zones 1 through 3 are described in this chapter ZONE 1 Connector P10 provides the ATCA Zone 1 power dual redundant 48V DC and system management connections Four levels of sequential mating provide proper functionality during live insertion or extraction Zone 1 Connector P10 17 13 33 0000 OO OO 32 27 Ooooe 00700 9 9998 20 16 OW UU Zone 1 Connector P10 Pin Assignments Pin Signal Insertion Sequence 1 reserved NA 2 reserved 3 reserved NA 4 reserved 5 Hardware Address bitO HAO third 6 HA1 third 7 HA2 third 8 HA3 third 9 HA4 third 10 third 11 HA6 third 12 HA7 odd parity bit third 10007175 02 KAT
230. ger Valid options Not defined in default configuration reported at bootup from the IPMC stderr serial Sets the standard destination for console error reporting Valid options serial nc Net Console stdin serial Sets the standard source for console input Valid options serial nc Net Console stdout serial Sets the standard destination for console output Valid options serial nc Net Console switch srom init off Switch initialization EEPROM or over PCI default Valid options on off tftp port TSEC 1 Selects which Ethernet port will be used for tftp Valid options all TSEC 1 TSEC 2 TSEC 3 TSEC 4 write enable socket off Enable writing to the flash socket Valid options on off The monitor supports optional environment variables that enable additional functionality The moninit command see moninit on page 14 24 clears all environment variables and sets the standard environment variables to the default values All optional environment variables are removed after moninit However it can clear all optional variables Table 14 7 lists the monitor s optional environment variables Table 14 7 Optional Environment Variables Variable Description app lock base Assigns where to start block lock protection at the base of NOR soldered flash If assigned region does not fall within the NOR flash area no user application locking will occur except for the monitor block locking protection 14 30 KAT4000 User s Manu
231. ging IPMI Completion Codes All IPMI response messages contain a hexadecimal Completion Code field that indicates the status of the operation Table 9 2 lists the Completion Codes as defined in the IPMI specifi cation used by the IPMC Table 9 2 Completion Codes Code Description Generic Completion Codes 00 0 00 Command completed normally CO Node busy command could not be processed because command processing resources are temporarily unavailable C1 Invalid command indicates an unrecognized or unsupported command C2 Command invalid for given LUN Time out while processing command response unavailable C4 Out of space command could not be completed because of a lack of storage space required to execute the given command operation C5 Reservation canceled or invalid Reservation ID C6 Request data truncated C7 Request data length invalid C8 Request data field length limit exceeded C9 Parameter out of range one or more parameters in the data field of the Request are out of range This is different from Invalid data field code CC because it indicates that the erroneous field s has a contiguous range of possible values CA Cannot return number of requested data bytes CB Requested sensor data or record not present cc Invalid data field in Request CD Command illegal for specified sensor or record type CE Command response could not be provided CF Cannot execute duplicated request for devices that can
232. gt lt address gt lt value gt Debug SetRegs clear lt address gt lt port_no gt lt value gt Detailed Command Descriptions Some of the commands have optional parameters If the optional parameter is omitted a default value may be used or the command may display the current setting i e function as a get command In Example 1 the omitted parameter is interpreted as the display command Example 1 Syntax System Name lt name gt gt system name enter System Name SuperSwitch 01 In Example 2 the omitted parameter is interpreted as the default value VLAN ID 1 Example 2 Syntax MAC Add lt macaddress gt lt portlist gt lt vid gt gt mac add 010203ABCDEF 16 lt enter gt The following sections list the individual commands by showing the syntax and a descrip tion of each command 10007175 02 KAT4000 User s Manual A 7 Appendix A serial Command Line Interface CLI System Configuration System Commands Syntax System Configuration all Description Show system name software version hardware version and management MAC address Optionally show the full configuration a11 Show the total switch configuration Default System configuration only System Restore Default Syntax System Name System Initialize System Reboot Console Configuration Console Password KAT4000 User s Manual System Restore Default keepIP Description Restore factory default confi
233. gth Code cc Parameter Table B 21 B2 12V Current SDR Description Status continued KAT4000 Records Value Parameter Status Record ID 0013 SDR Version 51 Record Type 01 Full Sensor Record Record Length 37 Sensor Owner ID 00 Sensor Owner LUN 00 Sensor Number 00 x Entity ID ci _ AMC Module Entity Instance 66 Sensor Initialization 5d Init Scanning Init Sensor Type Init Hysteresis Init Thresholds Sensor Scanning enabled Sensor Capabilities 69 Ignore Sensor no Auto Re Arm enabled Sensor Hysteresis hysteresis is settable readable Sensor Threshold Access threshold is settable readable Event Message Control global disable only Sensor Type 03 Current Event Reading Type Code 01 Threshold Assertion Event Mask 0800 Upper Non Recoverable Going High supported Deassertion Event Mask _ 4800 Lower Non Recoverable Threshold comparison returned Upper Non Recoverable Going High supported Discrete Reading Mask 3838 Upper Non Recoverable Threshold settable Upper Critical Threshold settable Upper Non Critical Threshold settable Upper Non Recoverable Threshold readable Upper Critical Threshold readable Upper Non Critical Threshold readable Sensor Units 1 00 Analog Data Format unsigned Rate Unit none Modifier Unit none Percentage no Sensor Units 2 Base Uni
234. guration 1 Preserve IP configuration Default Not preserved Syntax System Name lt name gt Description Set or show the system name The empty string clears the system name lt name gt String of up to 16 characters Default Show system name Syntax System Initialize serialnum Description Set Ethernet address and initialize NVRAM to default configuration serialnum Second half of the carrier board s serial number for example 1001 if the serial number is 7114 1001 Default Show serial number Syntax System Reboot Description Reboot the switch Console Commands Syntax Console Configuration Description Show configured console password and timeout Syntax Console Password lt password gt Description Set or show the console password The empty string disables the password check 10007175 02 Appendix A serial Command Line Interface CLI password Password string of up to 16 characters Console Timeout Syntax Console Timeout lt timeout gt Description Set or show the console inactivity timeout in seconds The value zero disables timeout lt timeout gt Timeout value in seconds 0 60 10000 Console Prompt Syntax Console Prompt lt prompt_string gt Description Set or show the console prompt string The empty string clears the prompt string prompt string Command prompt string of up to 10 chara
235. hardware configuration register The CPLD is in system pro grammable ISP A single JTAG interface is provided for local programming Remote pro gramming via the IPMC is also possible All reset sources and loads are connected to the CPLD The board can be remotely reset via the IPMI controller Software can also assert a board level reset PLD REGISTER SUMMARY The PLD registers start at address 0 0000 6 Table 7 1 lists the 8 bit PLD registers fol lowed by the register bit descriptions PLD Registers Address Offset hex Mnemonic Register Name Register Map 0x00 PIDR Product ID 7 1 0x04 HVR Hardware Version 7 2 0x08 PVR PLD Version 73 0x0C PLLC PLL Configuration 7 5 0x10 HCRO Hardware Configuration 0 7 4 0 14 Reserved 0x18 JSR Jumper Settings 7 7 Ox1C LEDR LED Control 27 6 0 20 Reset Event 7 12 0x24 RCRI Reset Command 1 7 13 0x28 RCR2 Reset Command 2 7 14 0 2 SCR1 Scratch 1 7 11 0x30 BDRR Boot Device Redirection 745 OG4 MISC MISC Control 7 10 0580 RGSR RTM GPIO State 7 8 OGC _ RTM GPIO Control 7 9 0x40 CSCI _ Clock Synchronizer Control 1 0x44 652 _ Clock Synchronizer Control 2 7 16 0x48 CSC3 Clock Synchronizer Control 3 0 Reserved 0x50 CPS1 Clock Synchronizer Primary Source 1 0x54 52 _ Clock Synchronizer Primary Source 2 7 17 0x58 CPS3 _ Clock Synchronizer Primary Source
236. he baud rate ID defines the interface baud rate as follows 0 9600 bps 1 19200 bps 2 38400 bps 3 57600 bps unsupported Set Serial Interface Properties Command The Set Serial Interface Properties command is used to set the properties of a particular serial interface Table 9 9 Set Serial Interface Properties Command Type Byte Field Request Data 1 3 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems 4 Interface ID 0 Serial Debug Interface 1 Payload Interface Bit 7 Echo On If this bit is set the IPMC enables echo for the given serial interface Bits 6 4 Reserved Bits 3 0 Baud Rate ID The baud rate ID defines the interface baud rate as follows 0 9600 bps 1 19200 bps 2 38400 bps 3 57600 bps unsupported 4 115200 bps unsupported Response 1 Completion Code 2 4 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems 10007175 02 KAT4000 User s Manual E System Management vendor Commands Get Debug Level Command The Get Debug Level command gets the current debug level of the IPMC firmware Table 9 10 Get Debug Level Command Type Byte Request Data 1 3 Response Data 1 Response Data 5 Data Field PPS IANA Private Enterprise ID MS Byte first 0 00400 16394 Pigeon Point Systems Completion Code PPS IANA Private Enterprise ID MS Byte first 0 00400 16394 Pigeon Point Systems
237. he four AMC sites the Ethernet core switch and an 88E1111 Gigabit PHY J2 is a 180 pin high speed connector that provides an interface to the RTM channel clock PLD processor and Zone 2 via fabric channels 1 and 2 Reset of the GbE fat pipe switch is shown in Fig 5 7 GbE Fat Pipe Switch Reset From the RESET VSC7376 KAT4000 gt 41 13 Switch GbE Fat Pipe Switch Module PLD The PLD is used to interface to the fat pipe VSC7376 Ethernet switch and is located from FC14 0000 FC15 FFFF Internal registers of the PLD can only be accessed by the KAT4000 s CPU when not using the built in 8051 microcontroller on the VSC7376 switch The PLD can not be accessed via the 8051 microcontroller Table 5 1 lists the 8 bit PLD registers followed by the register bit descriptions GbE Fat Pipe PLD Registers Address Access Register Offset hex Mode Mnemonic Register Name Map 0x00 PIDV Product ID Version Register 5 1 0x01 SCR _ Scratch Register 52 0x02 Register 5 3 0x03 R W SDET _ Signal Detect Register 5 4 0 04 SRST Switch Reset Register 5 5 0x05 R STAT Module Status Register 5 6 0x06 R W Switch Register 57 0x07 _ GPIN LED Register 58 Product ID Version Register The read only Product ID Version register indicates the product type PLD code version and hardware version The values of these bit
238. he monitor boot process The BMC watchdog is disabled if the monitor goes to the monitor prompt fru The fru command opens closes saves sets shows dumps and loads fru data to and from the IPMC fru command argl arg2 1 command open close save set show dump load create fru open id fru close fru save fru set section chassis board product gt lt field gt lt value gt fru set section field value section chassis board product 10007175 02 Monitor IPMC Commands Definition Definition Example Definition fru set chassis field value field type part serial fru set board field value field date maker name serial part file fru set product field value field maker name part version serial asset file fru show fru dump address fru load lt address gt lt size gt Set data in the internal use area fru set internal source addr internal use offset count The fru create command loads a default fru image to a blank fru device fru create id default product name fru create id address size product name fruinit The fruinit command initializes the following fru data fields part number build date and serial number in the board and product sections fruinit fru id part number build date serial number fruled The fruled comman
239. he processor initially maps one megabyte addressing of Flash memory beginning at FFF0 000046 at the top of the address space When 8 bit Flash device is installed in the PLCC socket it always appears at 80 0000 6 and is mirrored at FFF0 000046 when the socket is the boot device 10007175 02 KAT4000 User s Manual Memory Configuration SDRAM Caution When removing socketed PLCC devices always use an extraction tool designed specifically A for that task Otherwise you risk damaging the PLCC device The KAT4000 supports a redundant boot bank This boot bank is automatically used if the primary bank fails to boot properly The primary and redundant banks are designated from the local processor as well as remotely over IPMI The watchdog timer on the 8548 will be used to change the boot select direction after a watchdog expiration event ON CARD SDRAM The KAT4000 supports 512 megabytes and 1 gigabyte of 72 bit wide DDR2 SDRAM This interface implements eight additional bits to permit the use of Error Correcting Code ECC ECC can also be disabled for specific configurations The SDRAM interface clock speed is 200 MHz A low profile small outline dual inline memory module SO DIMM is installed in a 200 pin socket to reduce board density and routing constraints 12 serial EEPROM on the SO DIMM provides the serial presence detects SPD SDRAM occupies physical addresses from 0000 000016 to
240. hold Event Message Control global disable only Sensor Type 2b Event Reading Type Code 6f Sensor Specific Assertion Event Mask OOff Deassertion Event Mask 0000 Discrete Reading Mask ooff Sensor Units1 00 Analog Data Format unsigned Rate Unit none Modifier Unit none Percentage no Sensor Units 2 Base Unit 00 Unspecified Sensor Units 3 Modifier Unit 00 Unspecified Linearization 00 KAT4000 User s Manual 10007175 02 Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued M 00 M Tolerance 00 B 00 B Accuracy 00 Accuracy Accuracy Exp 00 00 Analog Characteristic Flags 00 Nominal Reading 00 E Normal Maximum 00 Normal Minimum 00 Sensor Maximum Reading 00 _ Sensor Minimum Reading 00 Upper Non Recoverable 00 Threshold Upper Critical Threshold 00 _ Upper Non Critical Threshold 00 LlowerNon Recoverable 00 Threshold Lower Critical Threshold 00 _ Lower Non Critical Threshold 00 _ Positive Going Threshold Hyst 00 Value Negative Going Threshold Hyst 00 Value 00 ID String Type Length Code ce Table B 15 Hot Swap SDR Description KAT4000 Records Value Parameter Status Record I
241. hold readable Lower Non Critical Threshold readable Sensor Units 1 00 Analog Data Format unsigned _ Rate Unit none Modifier Unit none Sensor Units 2 Base Unit 04 Volts Sensor Units 3 Modifier Unit 200 Unspecified Linearization 00 M 62 M Tolerance 00 00 00 Accuracy Accuracy Exp 00 R exp B Exp cO Analog Characteristic Flags 07 Nominal Reading 7b Normal Maximum 87 Normal Minimum 6f Sensor Maximum ff Reading Sensor Minimum Reading 00 _ Upper Non Recoverable 93 Threshold Upper Critical Threshold 00 Upper Non Critical Threshold 00 Lower Non Recoverable 62 Threshold Lower Critical Threshold 00 Lower Non Critical Threshold 00 KAT4000 User s Manual 10007175 02 Appendix B sensor Data Records KAT4000 Records _ Value Parameter Status continued Positive Going Threshold Hyst 03 Value Negative Going Threshold Hyst 03 Value OEM 00 ID String Type Length Code c5 Table B 10 1 0 Volt SDR Description KAT4000 Records Value Parameter Status Record ID 0008 SDR Version 51 Record 01 Full Sensor Record Record Length 30 Sensor Owner ID 00 Sensor Owner LUN 00 Sensor Number 00 Entity ID 14 Powe
242. ication Time Out command reads the payload communication time out value Table 9 16 Get Payload Communication Time Out Command Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems ResponseData 1 Completion Code 2 4 PPS IANA Private Enterprise ID MS Byte first 0 00400 16394 Pigeon Point Systems 5 Payload Time out Payload communication time out measured in hundreds of milliseconds Thus the payload communication time out may vary from 0 1 to 25 5 seconds 10007175 02 KAT4000 User s Manual E System Management vendor Commands Table 9 17 Register 9 1 Table 9 18 KAT4000 User s Manual Set Payload Communication Time Out Command The Set Payload Communication Time Out command sets the payload communication time out value Set Payload Communication Time Out Command Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems 4 Payload Time out Payload communication time out measured in hundreds of milliseconds Thus the payload communication time out may vary from 0 1 to 25 5 seconds Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Enable Payload Control Command The Enable Payload Control command enables payload control from the Serial Debug inter face Enable Payl
243. ices Two 12 controllers Programmable interrupt controller DDR2 SDRAM memory controller e General purpose I O GPIO Chip select generation for the local bus devices DMA capability e PCI X bus interface sRIO or PCle controller Four three speed Ethernet controllers MICROPROCESSOR CORE E500 L1 Cache The MPC8548 processor implements two separate 32 kilobyte level one L1 instruction and data caches that are eight way set associative The L1 supports a four state modi fied exclusive shared invalid MESI cache coherency protocol The caches also employ pseudo least recently used PLRU replacement algorithms within each way L2 Cache The internal 512 kilobyte L2 cache is an eight way set associative instruction and data cache The L2 cache is fully pipelined to provide 32 bytes per clock to the L1 caches The L2 Control L2CTL register configures and operates the L2 SRAM array The L2CTL is read write and contents are cleared during power on reset The L2 cache is cleared following a power on or hard reset Before enabling the L2 cache configuration parameters must be set in the L2CR and the L2 tags must be globally invali dated Initialize the L2 cache during system start up per the following sequence 1 Power on reset is automatically performed by the assertion of HRESET signal 2 Verify that L2CR L2E 0 3 Perform an L2 global invalidate by setting L2CR L21 10007175 02 KAT4000 User s Manual
244. igure 2 2 Component Map Bottom Rev 02 9002 149 402 NOS H3IWI3 2010 age 816 em 8 B te 22008 C712 618 2507 f Ma i T ona g m g 05 5 158 B om Os t 000 8 oue 26 n CELL a p age m h 210 mp zr g 2 a 4 666 T a B 000 E 2 m 1 g ij i mma cred E cres Sa M m gg fig 8000880088 E B Be B EHEB i 2h B 8 008 a 8 00 o 1 T H u95 H 096 8 B rp a Es 8 a aa 8 a 5 0 1 cu brem s u83 Ae lee Aaa NSCTATS Site 8 Soca 8 B lt B a 02 000 a ELI 8 8 mn a in a 05 iu amm 1408 om 0 8 E 1 ta
245. info command displays the Board Information Structure bdinfo coninfo The coninfo command displays the information for all available console devices coninfo crc32 The crc32 command computes a CRC32 checksum on count bytes starting at address crc32 address count date The date command will set or get the date and time and reset the RTC device 10007175 02 Monitor Other Commands Definition Definition Definition Definition Definition Definition Setthe date and time date MMDDhhmm CC YY ss Display the date and time date Reset the RTC device date reset echo The echo command echoes args to console echo args enumpci The enumpci command enumerates the PCle bus when the hardware is the PCle Root Complex in the system enumpci go The go command runs an application at address addr passing the optional argument arg to the called application go addr arg help The help or command displays the online help Without arguments all commands are displayed with a short usage message for each To obtain more detailed information for a specific command enter the desired command as an argument help command iminfo The iminfo command displays the header information for an application image that is loaded into memory at address addr Verification of the image contents magic number header and payload checksums are also performed iminfo addr addr isdram
246. ing Sensor Data Records and the Device SDR Repository Under certain circumstances some sensors connected to the IPMC can generate Event Messages for the system management controller To enable these messages the system management controller must send a Set Event Receiver command to the IPMC along with the address of the Event Receiver Table 9 40 shows the format of an Event Message E KAT4000 User s Manual 10007175 02 System Management sensors and Sensor Data Records Note Each byte has eight bits Table 9 40 Event Message Format Byte 0 1 10 11 12 13 Field RsSA NetFn RsLUN Chki RqSA RqSeq RqLUN Cmd EvMRev Sensor Type Sensor Number Event Dir Event Type Event Data 0 Event Data 1 Event Data 2 Chk2 Description Responder s Slave Address Address of Event Receiver Net Function Code 0x04 in upper 6 bits Responder s LUN in lower 2 bits Checksum 1 Requester s Slave Address Address of our board on IPMB Request Sequence number in upper 6 bits Requester s LUN in low 2 bits Command Always 0x02 for event message Event Message Revision 0x04 for IPMI 1 5 Indicates event class type of sensor that generated the message A unique number indicating the sensor that generated the message Upper bit indicates direction 0 Assert 1 Deassert Lower 7 bits indicate type of threshold crossing or state transition Data for sensor and event type Optional Data for sensor and event typ
247. ion Handling 3 13 RoHS Compliance 1 11 JTAG COP Interface 3 14 Terminology and Notation 1 12 No Processor Configuration 3 15 Technical References 1 12 Common Switch Region Ethernet Core Switch optional 4 2 Setup ze Switch Configuration 4 3 Electrostatic Discharge 2 1 4000 Circuit Board 2 1 nian sped Pront Panel 2 4 4 3 CannBdtoms 2 4 On Board Path Device Settings 4 4 ARE Off Board Path Device Settings 4 4 4 Ethernet Transceivers 4 5 ER anda ins Ethernet Address for the KAT4000 4 5 JTAG 2 9 Ethernet Address forthe GbE Fat Pipe Switch 2 10 Module 4 6 Io M 2 13 PCI Express Switch optional 4 7 4000 2 15 PCI Express Interface 4 8 Identification Numbers 2 15 EEPROM Interface 4 9 Power Requirements 2 16 JTAG Controller Interface 4 9 Environmental Considerations 2 16 Troubleshooting 2 17 2 Technical Support 2 17 Fat Pipe Switch Module Product Repair 2 18 GbE Fat Pipe Switch Module 5 2 GbE Fat Pipe Switch Module Circuit i o ites vas
248. ipe switch module option is currently not available for order AMC Port Map Fat Pipes Region 10 GbE 10 GbE Port Mapping 4 10 GbE 21509 401229uuo 5 Fat Pipes Region _ MEME i AMC 0 Definition 10 GbE 10 GbE Fat Pipe Switch Module Implementation This region supports data path connections such as 10 GbE It can carry large amounts of data without significantly degrading the speed of transmission This refers to the link width of the port the number of lanes that can be used to intercon nect between two link partners The following diagram shows the implementation of the 10 GbE 10 GbE fat pipe switch module on the KAT4000 Signal Routing of the 10 GbE 10 GbE Fat Pipe Switch Module on the KAT4000 If the GbE core switch is present GbE routes from the fat pipe to the GbE core switch If the GbE core switch is not present GbE routes from the fat pipe to the CPU AMC x4 Single Wide Half Full Extended Height AMC z 0 Extended VSC7376 Fat Pipes Ethernet Core Switch Layer 2 Optional Fat Pipe Switch Module MPC8548 10 GbE 10 GbE Processor Local bus PCle x1 Base High Speed High Speed Clock RTM Fabric A Fabric B Optional 23 J20 Zone3 10007175 02 KAT4000 User s Manual 5 21 Fat Pipe Switch Module sRIO Fat Pipe Switch Module 5 22 Note Figure 5 17 Fat Pipes x1 x4 Figure 5 18 KAT4000 User s Manual
249. is RTM connects to the KAT4000 s Zone 3 connectors 30 32 and ATCA connector 33 This chapter describes the physical layout of the RTM and the installation process COMPONENTS AND FEATURES ATCA RTM Form Factor The RTM has a K1 alignment feature in Zone 2 an A1 Zone 3 alignment and keying feature Zone 3 connectors an ESD discharge strip four AMC site serial ports an ethernet debug port a host serial port a fat pipe serial port and board and IPMI reset switches Console Port Interface EIA 232 is routed through six micro D connectors P2 P4 P7 and RJ45 connector P3 at the rear I O face plate Reset The RTM front panel provides two reset switches a board reset and an IPMI reset Note TheRTM reset switches are not functional with the rev 00 KAT4000 10007175 02 KAT4000 User s Manual 13 1 Rear Transition Module runctional Overview FUNCTIONAL OVERVIEW The following block diagram provides a functional overview for the KAT Z3DB Figure 13 1 RTM General System Block Diagram with Face Plate Serial I O e Zone 3 Micro D Serial Port to the Connectors Fat Pipe Switch Module 1 Micro D Serial Port to the CPU 10 100BASE T RJ45 Debug Ethernet Port Board Reset Switch IPMI Reset Switch Micro D Serial Port to AMC4 Micro D Serial Port to AMC3 gt Micro D Serial Portto AMC2 Micro D Serial Port to AMC1 13 2 KAT4000 User s Manual 10007175 02
250. istates clock line pulled high externally 12 Address Values in these bits drive address to IC ROM Signal Detect Register The Signal Detect register drives the signal detect signals on the VSC7376 Ethernet switch Default is 0x00 Signal Detect Register SDET at 0x03 7 6 5 4 3 2 1 0 SDET7 SDET6 SDET5 SDET4 SDET3 SDET2 SDET1 SDETO Signal Detect State 0 Drives logic low on net 1 Tristate output Signal is externally pulled high Switch Reset Register The Switch Reset register allows for software control of reset to the VSC7376 Ethernet switch Default is 0x00 Switch Reset Register SRST at 0x04 7 6 5 4 3 2 1 0 reserved SRST Reserved Switch Reset 0 Switch not held in reset 1 Switch held in reset Software must ensure that the switch is held in reset for the minimum amount of time as listed in the VSC7376 Ethernet switch data sheet Module Status Register The read only Module Status register contains information relating to the module status such as power supply state switch operational mode and switch interrupt state 10007175 02 Fat Pipe Switch Module GbE rat Pipe Switch Module Register 5 6 CPU S2V5 S1V2 INT1 INTO Register 5 7 GPIO7 GPIOO Note Module Status Register STAT at 0x05 7 6 5 4 3 2 1 0 reserved CPU S2V5 S1V2 INT INTO Reserved Switch Mode 0 Internal 8051 microconto
251. l Threshold 00 Lower Non Critical Threshold 00 Positive Going Threshold Hyst 02 Value _ Negative Going Threshold Hyst 02 Value OEM 00 ID String Length Code cf Table B 31 3 3V Management SDR Description KAT4000 Records Value Parameter Status Record ID 001d SDR Version 51 o Record Type 01 Full Sensor Record Record Length 35 52 4000 User s Manual 10007175 02 Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Sensor Owner ID 00 Sensor Owner LUN 00 Sensor Number 00 Entity ID 0a Entity Instance 60 Sensor Initialization 7f Init Scanning lnit Sensor Type Init Hysteresis B Init Thresholds Init Events Sensor Scanning enabled Event Generation enabled Sensor Capabilities 69 Ignore Sensor no Auto Re Arm enabled Sensor Hysteresis hysteresis is settable readable Sensor Threshold Access threshold is settable readable Event Message Control global disable only Sensor Type 02 Voltage Event Reading Type Code 01 Threshold Assertion Event Mask _ 4801 Lower Non Recoverable Threshold comparison returned Upper Non Recoverable Going High supported Lower Non Critical Going Low supported Deassertion Event Mask _ 4801 Lower Non Recoverable Threshold comparison returned Upper Non Recoverable Goin
252. l Threshold comparison returned Lower Non Critical Threshold comparison returned Upper Non Recoverable Going High supported Upper Critical Going High supported Upper Non Critical Going High supported Lower Non Recoverable Going Low supported Lower Critical Going Low supported Lower Non Critical Going Low supported B 22 KAT4000 User s Manual 10007175 02 Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Discrete Reading Mask _ Upper Non Recoverable Threshold settable Upper Critical Threshold settable Upper Non Critical Threshold settable Lower Non Recoverable Threshold settable Lower Critical Threshold settable Lower Non Critical Threshold settable Upper Non Recoverable Threshold readable Upper Critical Threshold readable _ Upper Non Critical Threshold readable Lower Non Recoverable Threshold _ readable Lower Critical Threshold readable LlowerNon Critical Threshold readable _ Sensor Units 1 80 AnalogDataFormat twoscomplement Rate Unit none m Modifier Unit none Percentage no _ Sensor Units 2 Base Unit 01 DegreesC Sensor Units 3 Modifier Unit 00 Unspecified _ Linearization 00 M P M Tolerance 00 Bo 200 00 _ Accuracy Accuracy Exp
253. le Upper Critical Threshold settable Upper Non Critical Threshold settable Lower Non Recoverable Threshold settable Lower Critical Threshold settable Lower Non Critical Threshold settable Upper Non Recoverable Threshold readable Upper Critical Threshold readable Upper Non Critical Threshold readable Lower Non Recoverable Threshold readable Lower Critical Threshold readable Lower Non Critical Threshold readable 10007175 02 KAT4000 User s Manual B 49 Appendix B sensor Data Records KAT4000 Records Parameter Status continued Sensor Units 1 00 Analog Data Format unsigned Rate Unit none Modifier Unit none Percentage no Sensor Units 2 Base Unit 04 Volts B _ Sensor Units Modifier Unit 00 Unspecified _ Linearization _ 00 M 1a M Tolerance 40 B 00 B Accuracy 00 Accuracy Accuracy Exp 00 R exp B Exp 40 Analog Characteristic Flags 07 Nominal Reading ab Normal Maximum ff Normal Minimum 00 Sensor Maximum Reading ff Sensor Minimum Reading 00 Upper Non Recoverable Threshold Upper Critical Threshold 200 Non Critical Threshold 00 Lower Non Recoverable 00 Threshold Lower Critical Threshold 00 Lower Non Critical Threshold 00 Positi
254. le disable gt Description Enable disable MAC table auto learning enable disable Enable or disable MAC table learning default disable VLAN Commands VLANs use port IDs versus the port number i e the physical number of the port Port numbers port port ID 1 are used when discussing Ethernet switch ports For exam ple VLAN port ID 1 is the same as Ethernet switch port 0 Syntax VLAN Configuration lt portlist gt Description Show the VLAN aware mode port VLAN ID and accepted frame type for the port and the permanently stored VLAN table lt portlist gt Port list Default All ports Syntax VLAN Add lt vidlist gt lt portlist gt Description Add VLAN entry and include ports in member set lt vidlist gt VLAN ID list lt portlist gt Port list Default All ports Syntax VLAN Delete lt vidlist gt Description Delete VLAN entry all ports excluded from member set lt vidlist gt VLAN ID list Syntax VLAN Lookup lt vidlist gt Description Lookup VLAN entry and show port list lt vidlist gt VLAN ID list Syntax VLAN Aware lt portlist gt enable disable Description Set or show the VLAN awareness mode for the port VLAN aware ports will strip the VLAN tag from received frames and insert the tag in transmitted frames except PVID VLAN unaware ports will not strip the tag from received frames or insert the tag in transmit ted frames 10007175 02 App
255. les and deletes unwanted environment variables Set the environment variable name to value or adds the new variable name and value to the environment setenv name value Removes the environment variable name from the environment setenv name TEST COMMANDS The commands described in this section perform diagnostic and memory tests diags The diags command runs the Power On Self Test POST diags mtest The mtest command performs a simple SDRAM read write test mtest start end pattern 10007175 02 KAT4000 User s Manual 14 21 Monitor Other Commands 14 22 Definition Definition Definition Definition Definition Definition KAT4000 User s Manual um um command is a destructive memory test Press the key to quit this test the moni tor completes running the most recent iteration and exits to the default prompt after dis playing cumulative results for the completed iterations um b w 1 base addr top addr OTHER COMMANDS This section describes all the remaining commands supported by the KAT4000 monitor autoscr The autoscr command runs a script starting at address addr from memory A valid autoscr header must be present autoscr addr base The base command prints or sets the address offset for memory commands Displays the address offset for the memory commands base Sets the address offset for the memory commands to off base off bdinfo The bd
256. ller disabled parallel interface used for management access 1 Internal 8051 microcontroller enabled 2 5V Power Supply Status 0 Power supply out of spec 1 Power supply within spec 1 2V Power Supply Status 0 Power supply out of spec 1 Power supply within spec Switch Interrupts 0 Nointerrupt pending 1 Interrupt pending Switch GPIO Register The Switch GPIO register drives the GPIO signals on the VSC7376 Ethernet switch Default is 0x00 Switch GPIO Register GPIO at 0x06 7 6 5 4 3 2 1 0 GPIO7 GPIO6 GPIOS GPIO4 2 GPIOO GPIO State 0 Drive logic low 1 Drive logic high When the internal 8051 microcontroller is enabled GPIOs 5 4 are disabled as they are used for other func tions The PLD will tristate these pins GPIN LED Register The GPIN LED register controls general purpose inputs to the PLD from the carrier There are also four LEDs which are under software control 10007175 02 KAT4000 User s Manual Fat Pipe Switch Module GbE rat Pipe Switch Module Register 5 8 GPIN LED Register GPLED at 0x07 7 6 5 4 3 2 1 0 GPIO2 GPIO1 RSVD LED3 LED2 LED1 LEDO GPIO2 GPIOO0 General Purpose Input from 5 7376 RSVD Reserved LED3 LEDO LED State 0 Off 1 On EI KAT4000 User s Manual 10007175 02 Fat Pipe Switch Module 10 GbE 1 GbE Fat Pipe Switch Module Figure 5 8 Fat Pipes x4 10 GBE
257. loadaddress bootfilename FILE LOAD COMMANDS The file load commands load files over the serial port loadb The loadb command loads a binary file over the serial port The command takes two optional parameters The address offset parameter allows the file to be stored in a location different than what is indicated within the binary file by adding the value off to the file s absolute address The baudrate parameter allows the file to be loaded at baud instead of the monitor s con sole baudrate The file is not automatically executed the loadb command only loads the file into memory loadb off baud loads The loads command loads an S Record file over the serial port The command takes two optional parameters The address offset parameter allows the file to be stored in a location different than what is indicated within the S Record file by adding the value off to the file s absolute address The baudrate parameter allows the file to be loaded at baud instead of the monitor s con sole baudrate The file is not automatically executed the loads command only loads the file into memory loads off baud MEMORY COMMANDS The memory commands allow you to manipulate specific regions of memory For some memory commands the data size is determined by the following flags The flag b is for data in 8 bit bytes The flag wis for data in 16 bit words The l is for data in 32 bit long words These flags a
258. lue Description baudrate 9600 Console baud rate Valid rates 9600 14400 19200 38400 57600 115200 bmc wd timeout 1 This sets the time out in seconds for the BMC watchdog before booting the OS If set to 1 then the BMC watchdog is disabled before booting the OS Valid options 1 1 65535 Command to execute when auto booting or executing the bootd command bootcmd bootdelay 1 Choose the number of seconds the Monitor counts down before booting user application code Valid options time in seconds 1 to disable autoboot bootfile Path to boot file on server used with TFTP set this to path file bin to specify filename and location of the file to load bootretry 1 Setthe number of seconds the Monitor counts down before booting user application code used only with autoboot If the boot commands fails it will try again after bootretry seconds Valid options time in seconds 1 to disable bootretry bootstopkey h Press during power up reset initialization to terminate the monitor autoboot sequence and go to the monitor prompt cachemode write Sets the L1 cache mode to write through or copy back Valid options write copy clearmem on Select whether to clear unused SDRAM memory used by monitor is excluded on power up and reset Valid options on off dcache on Enables the processor L1 data cache Valid options on off ecc on Enable ECC initialization all of memory is cleared during ECC initializatio
259. m MT9045 T1 E1 OC3 System Synchronizer Data Sheet Zarlink Semiconductor Inc February 2005 MT9046 T1 E1 System Synchronizer with Holdover Data Sheet Zarlink Semiconductor Inc February 2005 http www zarlink com 10007175 02 Overview Additional Information 3 Frequently the most current information regarding addenda errata for specific documents may be found on the corresponding web site 10007175 02 KAT4000 User s Manual EH blank page E KAT4000 User s Manual 10007175 02 Setup Caution A Table 2 1 This chapter describes the physical layout of the board and the setup process including power requirements and environmental considerations This chapter also includes trouble shooting service and warranty information ELECTROSTATIC DISCHARGE Before you begin the setup process please remember that electrostatic discharge ESD can easily damage the components on the KAT4000 hardware Electronic devices espe cially those with programmable parts are susceptible to ESD which can result in opera tional failure Unless you ground yourself properly static charges can accumulate in your body and cause ESD damage when you touch the board Use proper static protection and handle KAT4000 boards only when absolutely necessary Always wear a wriststrap to ground your body before touching a board Keep your body grounded while handling the board Hold the board by its edges do not touch any componen
260. mands that allow you to read and write memory on the serial EEPROMs and 12 devices eeprom The eeprom command reads and writes from the EEPROM For example eeprom read 53 100000 1800 100 reads 100 bytes from offset 0x1800 in serial EEPROM 0x53 right shifted 7 bit address and places itin memory at address 0x100000 Read write cnt bytes from devaddr EEPROM at offset off eeprom read devaddr addr off cnt eeprom write devaddr addr off cnt 10007175 02 Monitor EEPROM I2C Commands Definition Definition Definition Definition Definition Definition icrc32 The icrc32 computes a CRC32 checksum icrc32 chip address 0 1 2 count iloop The iloop command reads in an infinite loop on the specified address range iloop chip address 0 1 2 of objects imd The imd command displays the primary 2 bus memory For example imd 53 1800 2 100 displays 100 bytes from offset 0x1800 of I C device 0x53 right shifted 7 bit address The 2 atthe end ofthe offset is the length in bytes of the offset information sent to the device The serial EEPROMs all have two byte offset lengths The Real Time Clock RTC has a one byte offset length The temperature sensors have zero byte offset lengths imd chip address 0 1 2 of objects imd2 The imd2 command displays the secondary 2 bus memory For example imd 53 1800 2 100 displays 100 bytes from offset 0x1800 of I C device 0x53 right shifted
261. mmand Aggregation No ports are aggregated but aggregation mode is set to XOR User Groups User group 1 exists and includes all ports QoS Port mode is enabled The four highest VLAN tag priorities are given high priority Default priority is high All shaper and policers are disabled 10007175 02 Appendix A serial Command Line Interface CLI Mirror Mirroring is disabled IP IP mode is disabled and no IP address mask gateway is configured To enable the web interface an IP address must be configured SERIAL COMMAND LINE INTERFACE CLI Through the serial based switch configuration you have all the configuration options found in the web application and more The command line offers the option of configuring the devices directly without having to create a separate VLAN just for the web configura tion The direct serial method allows for the board to be fully configured without using a dedicated Ethernet port for configuration General CLI usage instructions and command details are described below Log In Log Out Procedures 1 Togetaccess to the CLI log in when prompted No password is required 2 Logoutat any time and at any context level using the exit command Help Utility Access help by pressing the key or entering help The help info depends on the context At top level a list of command groups is displayed e At group level list of the command syntaxes for the current group is displayed I
262. mode lt portlist gt Source port list Default All ports enable disable Enable disable mirroring of frames received on port Default Show mir ror mode IP Commands Syntax 10007175 02 Appendix A serial Command Line Interface CLI IP Configuration Description Show configured IP address mask gateway VLAN ID and mode Setup Syntax P Setup ipaddress gt lt ipmask gt ipgateway gt lt vid gt Description Set or show IP configuration ipaddress address Default Show IP configuration ipmask IP subnet mask Default Subnet mask for address class ipgateway Default IP gateway Default 0 0 0 0 lt via gt VLAN ID 1 4095 Default 1 IP Mode Syntax P Mode enable disable Description Activate or deactivate the IP configuration enable disable Enable disable IP Default Show IP mode IP Arp Syntax P Arp Description Show the current content of the ARP table IP Ping Syntax IP Ping lt ip_addr gt lt number_of_passes gt Description Send one ICMP ECHO packet to the IP address provided lt ip_addr gt IP address to ping lt number_of_passes gt Number of passes to ping default 1 Debug Commands Debug Read Register Syntax Debug Read Register lt block gt lt subblock gt lt address gt Description Read register address block Block identifier 0 7 or 0 0 0 7 subblock Sub block identifier 0 15 or 0x
263. n A jumper allows the JTAG to bypass the switch and or the PEX bridge See Fig 5 12 for details Figure 5 13 10 GbE 1 GbE Fat Pipe Switch TMS TCK BCM TDO R From the PLD TDI KAT4000 PLD TDO R PLD TDO To the KAT4000 BCM TDO EX TDO R PEX TDO p 56580 10 GbE 1 GbE Switch LEDs CR2 green and CR3 5 red on the bottom side of the board are generic LEDs for use by the firmware High Speed Connectors J1 is a 120 pin high speed connector that provides an interface to the four AMC sites the BCM56580 switch and the 8111 PCle to PCI bridge 2 is a 180 pin high speed connec tor that provides an interface to the RTM channel PCle channel PLD the 12 connection to the processor and Zone 2 via fabric channels 1 and 2 J4 and 5 are PMC connectors that attach to a PCI analyzer for debug use only Reset Resetofthe 10 GbE 1 GbE fat pipe switch is shown in Fig 5 14 10007175 02 KAT4000 User s Manual E Fat Pipe Switch Module 10 GbE 1 GbE Fat Pipe Switch Module Figure 5 14 Table 5 3 Register 5 9 E KAT4000 User s Manual 10 GbE 1 GbE Fat Pipe Switch Reset 3CM PCI RESET 10 GbE 1 GbE KAT4000 BCM_TRST Switch PCIE_RST PEX_PCI_RESET Tasserted with PCIE_RST or for PCI Express Hot Reset or when PCI Express link is down 10 GbE 1 GbE Fat Pipe Switch Module PLD The PLD is used to interface to the BC
264. n Valid options on off 14 28 KAT4000 User s Manual 10007175 02 Monitor Environment Variables Default Variable Value Description continued ecc ibit report off Select the reporting of single bit correctable ECC errors to the console errors of 2 or more bits are always reported Valid options on off enumerate on PCI bus enumeration Valid options on off ethaddr 00 80 F9 KAT4000 board Ethernet address for TSEC_1 port The last 92 00 00 digits are the board serial number in hex 00 80 F9 92 FF FF ethladdr 00 80 F9 KAT4000 board Ethernet address for TSEC_2 port The last 93 00 00 digits the board serial number in hex 00 80 F9 93 FF FF eth2addr 00 80 F9 KAT4000 board Ethernet address for TSEC_3 port The last 94 00 00 digits are the board serial number in hex 00 80 F9 94 FF FF eth3addr 00 80 F9 KAT4000 board Ethernet address for TSEC_4 port The last 95 00 00 digits are the board serial number in hex 00 80 F9 95 FF FF ethport all Select which Ethernet port will be used for TFTP and ping Valid options all eTSEC1 eTSEC2 eTSEC3 eTSEC4 The ports are assigned as follows eTSEC1 Ethernet debug port eTSEC2 Ethernet core switch eTSEC3 Ethernet core switch and eTSECA fat pipe switch module fru id undefined Corresponds to KAT4000 processing resources Valid options Not defined in default configuration reported at bootup from the IPMC gatewayip 0 0 0 0 Select the network gateway machine IP
265. n Recoverable Going High supported Discrete Reading Mask 3838 Upper Non Recoverable Threshold _ settable Upper Critical Threshold settable Upper Non Critical Threshold _ settable Upper Non Recoverable Threshold readable Upper Critical Threshold readable Upper Non Critical Threshold readable Sensor Units 1 _00 Analog Data Format unsigned Rate Unit none Modifier Unit none Percentage no Sensor Units 2 Base Unit 05 Amps Sensor Units 3 Modifier Unit 00 Unspecified Linearization 00 M 6d E M Tolerance 00 B 00 B Accuracy 00 Accuracy Accuracy Exp 00 10007175 02 KAT4000 User s Manual B 57 Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued R exp B Exp 90 Analog Characteristic Flags 07 _ Nominal Reading 53 i Normal Maximum al _ Normal Minimum 00 _ Sensor Maximum Reading fe Sensor Minimum Reading 00 Upper Non Recoverable cf Threshold _ Upper Critical Threshold 200 _ Upper Non Critical Threshold 00 Lower Non Recoverable 00 Threshold Lower Critical Threshold 00 Lower Non Critical Threshold 00 Positive Going Threshold Hyst 03 Value _ Negative Going Threshold Hyst 00 EE Value 00 ID String Type Length Code c9 Table B 34 F W Firmware Progress SDR Description
266. n for the last reset and the other two force one of several types of reset Reset Event Register RER The read only Reset Event register contains the bit corresponding to the most recent event which caused a reset If the entire register does not contain a bit 1 itis a Power On Reset POR condition Default register values are dependent on reset events 10007175 02 CPLD Boot and Reset Registers Register 7 12 SHR WE COPS COPH PAYR PBR Register 7 13 CPUH Reset Event Register RER at Oxfc40 0020 7 6 5 4 3 2 1 0 R SHR WE COPS COPH PAYR R PBR Reserved Software Issued Hard Reset 1 Thelastreset was caused by a write to the Reset Command register Watchdog Expiration 1 Areset was caused by the expiration of the watchdog timer MPC8548 COP Soft Reset 1 ACOP header soft reset SRESET has occurred MPC8548 COP Hard Reset 1 ACOP header hard reset HRESET has occurred Payload Reset 1 AnIPMC Payload reset has occurred Push Button Reset 1 The switch POR RST caused a reset Reset Command Register 1 RCR1 Reset Command registers 1 and 2 force one of several types of resets as shown below A reset sequence is initiated by writing a one to a valid bit then the bit is automatically Cleared Set only one bit in this register at a time If reset when in a locked state a clock syn chronizer will issue a loss of lock interrupt To prevent this mask the int
267. n in the bottom row of the register table MISC Control Register MISC at Oxfc40 0034 7 6 5 4 3 2 1 0 PCIE SRWP1 SRWPO FWP1 FWPO NFWP SDA SCL PCle Root Complex 1 Root complex for PCle system 0 Not the root complex for PCle system Serial ROM 1 Write Protect 1 Write protected 0 Notwrite protected Serial ROM 0 Write Protect 1 Write protected 0 Notwrite protected 10007175 02 KAT4000 User s Manual CPLD Boot and Reset Registers FWP1 FWPO NFWP SDA SCL Register 7 11 SCR7 0 KAT4000 User s Manual Flash 1 Write Protect 1 Not write protected 0 Write protected Flash 0 Write Protect 1 Not write protected 0 Write protected NAND Flash Write Protect 1 Write protected 0 Notwrite protected 2 SDA Output Driver State Bit state indicates PLD s output level on the bus SCL Output Driver State Bit state indicates PLD s output level on the bus Scratch Register 1 SCR1 Scratch register 1 can be used as reading writing test register Default register values are shown in the bottom row of the register table Scratch Register 1 SCR1 at Oxfc40 002c 7 6 5 4 3 2 1 0 SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCRI SCRO Scratch bits BOOT AND RESET REGISTERS The reset signals are routed to and distributed by the CPLD To support this functionality the CPLD includes three registers one indicates the reaso
268. nectors see Fig 2 1 summarized as follows EIA 232 A serial port is accessible off of the CPU through an on board header for development pur poses and routes to Zone 3 Ethernet A 10 100 Ethernet port is accessible off of the CPU through Zone 3 AMC Expansion Sites 1 4 Each site is capable of supporting an AMC module depending on the configuration using style connectors 1 4 map to sites B1 B4 see Table 8 1 for pin assignments Backplane Connectors Whether individual backplane connectors are populated on the KAT4000 depends on the specific product configuration PICMG 3 0 specification defines three connector zones on the backplane e Zone 1 is the power connection dual redundant 48V DC and system management connections P10 Zone2isthe data transport interface covering Base Fabric and Synchronization clock interfaces 20 through J24 E KAT4000 User s Manual 10007175 02 Setup KAT4000 Circuit Board P10 120 23 130 32 133 12000 2 2 Zone 3 ATCA is for the optional Rear Transition Module RTM I O interconnect 30 through J33 This connector provides the power and IPMB to the KAT4000 The P10 connector has four levels of sequential mating to provide the proper functionality during live insertion or extraction of the KAT4000 See Table 12 1 for the pin assignments The 80 pin Zone 2 ZD connectors provide three levels of sequential mating See Table 12 2 and Table
269. no longer accessible For example if configured to access the interface through VID 1 by default always be sure that the port you are using to access the web interface remains on VLAN 1 If the web interface is no longer accessible use the CLI to recover 10007175 02 KAT4000 User s Manual Appendix A web Interface Figure 2 Web Interface for the Ethernet Core Switch Jog Me fossu 468 10 Oe Artesyn KAT4000 Core Gigabit Ethernet Switch m Fort Segmentation VLAN Configuration mnt Wm M2 1 Monitering Maintenance E KAT4000 User s Manual 10007175 02 Appendix B SENSOR DATA RECORDS This appendix details the KAT4000 IPMI Sensor Data Record SDR parameter values from Sensors and Sensor Data Records on page 9 40 Table B 1 is a summary of all the KAT4000 SDRs with a link to the detailed sensor record All values are hexadecimal The no CPU KAT4000 configuration includes all of the SDRs listed in Table B 1 with the exception of the following BMC Watchdog CPU Volt and F W Firmware Progress Table B 1 Sensor Data Record Record ID Sensor Name hex Table Information KAT4000 0000 Table B 2 on page B 2 Hot Swap
270. nology Equipment Immunity characteristics Limits and methods of measurement EN300386 V 1 3 1 Electromagnetic compatibility and radio spectrum matters ERM Telecommunication network equipment EMC requirements As manufacturer we hereby declare that the product named above has been designed to comply with the relevant sections of the above referenced specifications This product complies with the essential health and safety requirements of the EMC Directive and RTTE Directive We have an internal production control system that ensures compliance between the manufactured products and the technical documentation Bill Fleury Compliance Engineer Issue date April 3 2007 C FMERSON Network Powe KAT4000 User s Manual 10007175 02 Contents Interrupts and Exception Processing 3 8 10007175 02 1 Overview Machine State Register 3 9 Peripheral Interface 3 10 8548 Peripheral Modules 3 11 Functi J Three Speed Ethernet Controllers unctional Overview 1 5 TSEC 341 Physical Memory 0 e E 1 9 Local Bus Controller LBC 3 12 Additional Information 1 10 Chip Select 3 12 Product Certification 1 10 Processor Reset and Clocking Signals 3 12 UL 1 11 MPC8548 Except
271. not return the response returned for the original instance of the request These devices should provide separate commands that allow the completion status of the original request to be determined An Event Receiver does not use this completion code but returns the 00 completion code in the response to valid duplicated requests DO Command response could not be provided SDR Repository in update mode D1 Command response could not be provided device in firmware update mode D2 Command response could not be provided Baseboard Management Controller BMC initialization or initialization agent in progress D3 Destination unavailable cannot deliver request to selected destination This code can be returned if a request message is targeted to SMS but receive message queue reception is disabled for the particular channel D4 Cannot execute command insufficient privilege level D5 Cannot execute command parameter s not supported in present state FF Unspecified error KAT4000 User s Manual 10007175 02 System Management IPMB Protocol Code Description continued Device Specific OEM Codes 01 7E 01 7E Device specific OEM completion codes command specific codes also specific for a particular device and version Interpretation of these codes requires prior knowledge ofthe device command set Command Specific Codes 80 BE 80 BE Standard command specific codes reserved for command specific completion codes described in this ch
272. nother reason Firmware Upgrade Sequence The normal IPMC firmware upgrade sequence is as follows in the simple configuration The IPMC firmware receives a Firmware Upgrade Start command After parsing this command the firmware sends a Node Busy reply and reboots to the Boot Loader The Boot Loader enters the upgrade node 10007175 02 KAT4000 User s Manual System Management Firmware Upgrade E KAT4000 User s Manual The upgrade initiator resends the Firmware Upgrade Start command and the Boot Loader returns a success reply indicating that an upgrade session has been opened The upgrade initiator issues a Firmware Upgrade Prepare master H8S flash command to erase the master H8S flash The Boot Loader erases the master H8S flash and returns a success reply The upgrade initiator sequentially writes the new master H8S firmware to the master H8S flash using the Flash Upgrade Write command The Boot Loader acknowledges each write by sending a success reply to the upgrade initiator The upgrade initiator issues a Firmware Upgrade Prepare slave H8S flash command to erase the slave H8S flash The Boot Loader writes the cached data to the master 85 flash erases the slave H8S flash and returns a success reply The upgrade initiator sequentially writes the new slave 85 firmware to the slave 85 flash using the Flash Upgrade Write command The Boot Loader acknowledges each write by sending a success reply to the upgrade initiator
273. nstall the KAT4000 circuit board in a system you should record the following information O The board serial number 711 The board serial number appears on a bar code sticker located on the back of the board O The board product identification This sticker is located near the board serial number The monitor version The version number of the monitor is on the monitor start up display The operating system version and part number This information is labeled on the master media supplied by Emerson or another verdor Any custom or user ROM installed including version and serial number It is useful to have these numbers available when you contact the Technical Support department at Emerson 10007175 02 KAT4000 User s Manual Setup KAT4000 Setup Table 2 5 Note Table 2 6 Table 2 7 EI KAT4000 User s Manual Power Requirements The KAT4000 draws all payload power from the dual redundant 48 volt inputs on the ATCA connector P10 Zone 1 Under normal operating conditions the power requirement is shared between the two 48 volt supplies Power is limited to 200 watts maximum includ ing AMC and optional RTM sites with 80W maximum per site and a combined max of 120W to all four sites and the RTM if used Optional RTMs receive their power from the KAT4000 Table 2 5 lists the board s typical power requirements Typical Power Requirement Configuration Watts 1 3 GHz 8548 processor 1 GB DDR2 SDRAM
274. nterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Response Data 5 Bit 7 Graceful Reboot Request continued If set to 1 indicates that the payload is requested to initiate the graceful reboot sequence Bit 6 Diagnostic Interrupt Request If set to 1 indicates that a payload diagnostic interrupt request has arrived Bit 5 Shutdown Alert If set to 1 indicates that the payload is going to be shutdown Bit 4 Reset Alert If set to 1 indicates that the payload is going to be reset Bit 3 Sensor Alert If set to 1 indicates that at least one of the IPMC sensors detects threshold crossing Bits 2 1 Mode The current IPMC modes are defined as 0 Normal 1 Standalone 2 Manual Standalone Bit 0 Control If set to 0 the IPMC control over the payload is disabled 6 Bits 4 7 Metallic Bus 2 Events These bits indicate pending Metallic Bus 2 requests arrived from the shelf manager 0 Metallic Bus 2 Query 1 Metallic Bus 2 Release 2 Metallic Bus 2 Force 3 Metallic Bus 2 Free Bits 0 3 Metallic Bus 1 Events These bits indicate pending Metallic Bus 1 requests arrived from the shelf manager 0 Metallic Bus 1 Query 1 Metallic Bus 1 Release 2 Metallic Bus 1 Force 3 Metallic Bus 1 Free 10007175 02 KAT4000 User s Manual 9 13 System Management vendor Commands Type Byte Response Data 8 c
275. o used on the KAT4000 board For more information about the VSC7376 see Ethernet Core Switch optional on page 4 2 The default fat pipe switch is not configured To configure the switch see the KAT4000 Quick Start Guide 10008585 PLD The PLD is the interface between the local bus and the VSC7376 parallel interface It con tains registers for fat pipe module control For more information see GbE Fat Pipe Switch Module PLD SROM EEPROM The 64 Kb EEPROM is used to store VSC7376 configuration information Flash Available only with the no CPU KAT4000 board The 4 Mb asynchronous flash is used to store firmware on the VSC7376 switch SRAM Memory Available only with the no CPU KAT4000 board The 256 Kb asynchronous SRAM is used by the on board VSC7376 firmware Resistors allow the JTAG to bypass the switch See Fig 5 6 for details Figure 5 6 GbE Fat Pipe Switch JTAG TMS TCK VSC7376 Ethernet Switch PLD_TDI LD TDO R PLD TDO From the ALA LD VSC7376 VSC7376_TDO_ To the KAT4000 P 4000 LEDs CR2 4 green and CR5 red on the bottom side of the board are generic LEDs for use the firmware High Speed Connectors 10007175 02 KAT4000 User s Manual EH Fat Pipe Switch Module GbE rat Pipe Switch Module Reset Figure 5 7 Table 5 1 EH KAT4000 User s Manual J1 is a 120 pin high speed connector that provides an interface to t
276. oad Control Command Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Disable Payload Control Command The Disable Payload Control command disables payload control from the Serial Debug interface Disable Payload Control Command Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Response Data 1 Completion Code _ 2 4 PPS IANA Private Enterprise ID MS Byte first 0 00400 16394 Pigeon Point Systems 10007175 02 System Management vendor Commands Reset IPMC Command The Reset IPMC command allows the payload to reset the IPMC over the SIPL Table 9 19 Reset IPMC Command Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems 4 Reset Type Code 0x00 Cold IPMC reset to the current mode 0x01 Cold IPMC reset to the Normal mode 0x02 Cold IPMC reset to the Standalone mode 0x03 Cold IPMC reset to the Manual Standalone mode 0x04 Reset the IPMC and enter Upgrade mode Response Data Completion Code 2 4 PPS IANA Private Enterprise ID MS Byte first 0 00400 16394 Pigeon Point Systems Hang IPMC Command The IPMC provides a way to test the wa
277. old 01 Processor 03 Device Yes relative 60 B1 12 Volt Voltage 02 Threshold 01 PICMG AMC Device Yes Module C1 relative 61 B1 12 Curr Current 03 Threshold 01 PICMG AMC Device Yes Module C1 relative 61 B2 12 Volt Voltage 02 Threshold 01 PICMG AMC Device Yes Module C1 relative 62 B2 12 Curr Current 03 Threshold 01 PICMG AMC Device Yes Module C1 relative 62 B3 12 Volt Voltage 02 Threshold 01 PICMG AMC Device Yes Module C1 relative 63 B3 12 Curr Current 03 Threshold 01 PICMG AMC Device Yes Module C1 relative 63 B4 12 Volt Voltage 02 Threshold 01 PICMG AMC Device Yes Module C1 relative 64 B4 12 Curr Current 03 Threshold 01 PICMG AMC Device Yes Module C1 relative 64 Inflow Temp Temperature 01 Threshold 01 PICMG Front Device Yes Board A0 relative 60 Outflow Temp Temperature 01 Threshold 01 PICMG Front Device Yes Board A0 relative 60 Progress System Firmware Sensor specific PICMG Front Device Yes Progress OF Discrete 6F Board A0 relative 60 2 Only supported on configurations with a CPU 3 Only supported on configurations with a CPU and PCle switch The IPMC implements a Device Sensor Data Record SDR Repository that contains SDRs for the IPMC the FRU device and each sensor A system management controller may use the Get Device SDR command to read the repository and dynamically discover the capabilities of the board Please refer to the IPMI specification listed in Table 1 3 for more information on us
278. ommand string including group or change context into a group by entering the name of the group At group level enter commands for the particular group chosen without specifying the group name or return to the top level by entering the up command The current level and group is indicated by the prompt At top level the prompt will be gt At group level the prompt will display the actual group for example System 10007175 02 Appendix A serial Command Line Interface CLI Also at group level use the slash key to refer to a context relative to the top level e g from the system group enter a console configuration command or change context into the console group by entering console Command Usage Instructions Commands are not case sensitive e Use the horizontal arrow keys and to move the cursor within the command you are entering Usethe backspace key provided you are using a terminal that sends the BS 8 character when the backspace key is pressed to delete chars from the command you are entering Usethe vertical arrow keys and to scroll through a command history buffer of the latest 20 commands issued e fusing a terminal that supports home and end keys e g HyperTerminal use these keys to move the cursor to respectively the start of the command line and the end of the command line Commands Table A 1 shows general parameter types used in command syntaxes and descriptions Not
279. ommand to the BMR H8S ATCA Using the SIPL protocol BO xx 01 00 The BMR H8S ATCA returns its IPMB address in the Get Address Info reply In this example 721615 the IPMB O address of the 85 ATCA 4 00 01 00 00 FF 72 FF 00 01 07 The payload software composes a Get Address Info command requesting the responder to provide its addressing information for FRU device 0 The request is composed in the IPMB format The responder address is set to 2016 for the shelf manager The requester address is set to the value obtained in the previous step 20 BO 30 72 00 01 00 8D The payload software forwards the command composed in the previous step to the shelf manager using the Send Message command The Send Get Message in SIPL format is 18 xx 34 40 20 BO 30 72 00 01 00 8D The BMR H8S ATCA firmware sends the Get Address Info request to the shelf manager waits for a reply to this request and sends this reply to the payload software in the Send Get Message response 1C 00 34 00 72 B4 DA 20 00 01 00 00 41 82 FF 00 FF 00 1E The payload software extracts the Get Address info reply from the Send Get Message response and gets the physical address of the board from it The second message bridging implementation bridging via LUN 10 allows the payload to receive responses to requests sent to IPMB 0 via the Send Message command with request tracking disabled as well as receive requests from 0 To provide this functionality the
280. onditions execute access control or byte ordering Caused when MSR EE 1 Caused when the processor core cannot perform a memory access Caused by one of the following exception conditions illegal instruction privileged instruction trap or unimplemented operation If MSR FP 0 the floating point registers are disabled and attempting to execute any floating point instruction causes a floating point unavailable exception Caused by the execution of a System Call sc instruction Caused when TSR DIS 1 TCR DIE 1 and MSR EE 1 Caused when TSR FIS 1 TCR FIE 1 and MSR EE 1 Caused when TSR WIS 1 TCR WIE 1 and MSR CE 1 Caused by a Data TLB Miss exception condition Caused by an Instruction TLB Miss exception condition KAT4000 User s Manual 3 13 Central Processing Unit Interface Vector OffsetHex IVOR Address Notes continued IVOR15 Debug 00 00 Caused when a debug exception exists in the DBSR and when DBCRO IDM 1 and MSR DE 1 JTAG COP INTERFACE A single JTAG COP header is provided for debug purposes for the processor This interface provides for boundary scan testing of the CPU see Fig 3 2 and is compliant with the IEEE 1149 1 standard The header pin assignments are defined in Table 3 6 Caution Install a shunt on JP1 pins 1 2 before using the TAG COP interface P1 to enable CPU A JTAG COP access Attempting to use the JTAG COP interface without this shunt in plac
281. onfiguration dependent KAT4000 User s Manual 100071 75 02 CPLD version and ID Registers PID1 PIDO ECS PCIE Register 7 2 R HVR1 HVRO Register 7 3 PCV7 0 PID Select 00 KAT4000 01 Reserved 10 Reserved 11 Reserved Reserved Ethernet Core Switch 1 Ethernet Core Switch is installed 0 Ethernet Core Switch is not installed PCI Express Switch 1 Express Switch is installed 0 PCI Express Switch is not installed Hardware Version Register HVR The read only Hardware Version register indicates artwork revision and notifies of any other change to the hardware The values of these bits are defined by strapping resistors Hardware Version Register HVR at Oxfc40 0004 7 6 5 4 3 2 1 0 reserved HVR1 HVRO Reserved Hardware Version Register This is hard coded in the PLD and changes with every major PCB version Version starts at Ox00 PLD Version Register PVR The read only PLD Version register provides a hard coded tracking number that changes with each CPLD code release PLD Version Register PVR at Oxfc40 0008 7 6 5 4 3 2 1 0 PCV7 PCV6 PCV5 PCV4 PCV3 PCV2 PCV1 PCVO PLD Code Version This is hard coded in the PLD and changes with every major code version Version starts at Ox00 10007175 02 KAT4000 User s Manual CPLD Configuration Registers Register 7 4 BDR CF1 CFO DDRF Register 7 5 K
282. oninit s d lt serial or fru noburn Initialize environment variables and serial number in NVRAM and copy the monitor from src address into NOR Flash moninit s d lt serial or fru src address pci The pci command enumerates the PCI bus It displays enumeration information about each detected device The pci command allows you to display values for and access the PCI Con figuration Space Display a short or long list of PCI devices on the bus specified by bus pci bus long 10007175 02 Monitor Other Commands Definition Example Definition Definition Show the header of PCI device bus device function pci header b d f Display the PCI configuration space CFG pci display b w 1 b d f address of objects Modify read and keep the CFG address pci next b w 1 b d f address Modify automatically increment the CFG address pci modify b w 1 b d f address Write to the CFG address pci write b w 1 b d f address value phy The phy command reads or writes to the contents of the PHY registers The values changed via this command are not persistent and clear after a hard or soft reset The port options are all eTSEC1 eTSEC2 eTSEC3 and eTSEC4 and 1 and base2 via the switch reads the register contents at the address specified W writes the address value to the register address specified A reads the contents of all registers phy p
283. ontinued Data Field continued Bits 4 7 Clock Bus 2 Events These bits indicate pending Clock Bus 2 requests arrived from the shelf manager 0 Clock Bus 2 Query 1 Clock Bus 2 Release 2 Clock Bus 2 Force 3 Clock Bus 2 Free Bits 0 3 Clock Bus 1 Events These bits indicate pending Clock Bus 1 requests arrived from the shelf manager 0 Clock Bus 1 Query 1 Clock Bus 1 Release 2 Clock Bus 1 Force 3 Clock Bus 1 Free Bits 4 7 Reserved Bits 0 3 Clock Bus 3 Events These bits indicate pending Clock Bus 3 requests arrived from the shelf manager 0 Clock Bus 3 Query 1 Clock Bus 3 Release 2 Clock Bus 3 Force 3 Clock Bus 3 Free Get Serial Interface Properties Command The Get Serial Interface Properties command is used to get the properties of a particular serial interface Table 9 8 Get Serial Interface Properties Command Type Byte Request Data 1 3 4 KAT4000 User s Manual Data Field PPS IANA Private Enterprise ID MS Byte first 0x00400A 16394 Pigeon Point Systems Interface ID 0 Serial Debug Interface 1 Payload Interface 10007175 02 System Management vendor Commands Type Response Data Byte Data Field continued Completion Code 1 2 4 PPS IANA Private Enterprise ID MS Byte first 0 00400 16394 Pigeon Point Systems 5 Bit 7 Echo On If this bitis set the IPMC enables echo for the given serial interface Bits 6 4 Reserved Bits 3 0 Baud Rate ID T
284. ors and Sensor Data Records 9 40 ZONES is oes y eR E EAS ERES 13 6 FRU Inventory 9 44 EEEE e re Rn 13 6 9 45 Identification Numbers 13 7 Base Point to Point Connectivity 9 45 13 7 Carrier Point to Point Connectivity9 46 Firmware Upgrade 9 47 Firmware Upgrade Status Command 14 Monitor 9 47 Command Line Features 14 1 Firmware Upgrade Start Command Basic Operation 14 4 9 48 Power up Reset Sequence 14 4 Firmware Upgrade Prepare Command POST Diagnostic Results 14 6 9 49 Monitor SDRAM Usage 14 6 Firmware Upgrade Write Command Monitor Recovery and Updates 14 6 9 49 Recovering the Monitor 14 7 Firmware Upgrade Complete Resetting Environment Variables 14 7 9 50 Updating the Monitor via 14 7 Firmware Upgrade Restore Backup Monitor Command Reference 14 8 9 50 Command Syntax 14 8 Firmware Upgrade Backup Revision Command 14 9 9 51 10007175 02 4000 User s Manual Contents continued Typographic Conventions 14 9 usce scc etm 14 21 Boot 14 9 14 21 14 9 se
285. ort R W A address value The following is an example of a read of register address Ox1a phy eTSEC2 Oxla The following is an example of a write to register address Ox1a where 0 is the data to write phy eTSEC2 Oxla 0 ping The ping command sends a ping over Ethernet to check if the host can be reached The port used is defined by the ethport environment variable If 1 is selected for ethport the ping process cycles through each port until a connection is found or all ports have failed ping host reset The reset command performs a hard reset of the CPU by writing to the reset register on the board Without any arguments the KAT4000 CPU is reset reset 10007175 02 KAT4000 User s Manual 14 25 Monitor Other Commands 14 26 Definition Example Note Definition Definition Definition Definition KAT4000 User s Manual run The run command runs the commands in an environment variable var run var Use for variable substitution the syntax variable_name should be used for variable expansion gt setenv cons opts console tty0 console ttyS0 baudrate gt printenv cons opts cons_opts console tty0 console ttyS0 baudrate Use the character to escape execution of the as seen in the setenv command above In this example the value for baudrate will be inserted when cons_opts is executed script The script command runs a list of monitor commands out of memor
286. orted Discrete Reading Mask 3f3f Upper Non Recoverable Threshold settable Upper Critical Threshold settable Upper Non Critical Threshold settable Lower Non Recoverable Threshold settable Lower Critical Threshold settable Lower Non Critical Threshold settable Upper Non Recoverable Threshold readable Upper Critical Threshold readable Upper Non Critical Threshold readable Lower Non Recoverable Threshold readable Lower Critical Threshold readable Lower Non Critical Threshold readable 10007175 02 KAT4000 User s Manual Appendix B sensor Data Records KAT4000 Records Parameter Status continued Sensor Units 1 00 Analog Data Format unsigned Rate Unit none Modifier Unit none Percentage no Sensor Units 2 Base Unit 04 Volts B _ Sensor Units Modifier Unit 00 Unspecified _ Linearization _ 00 M 1a M Tolerance 40 B 00 B Accuracy 00 Accuracy Accuracy Exp 00 R exp B Exp 40 Analog Characteristic Flags 07 Nominal Reading ab Normal Maximum ff Normal Minimum 00 Sensor Maximum Reading ff Sensor Minimum Reading 00 Upper Non Recoverable Threshold Upper Critical Threshold 200 Non Critical Threshold 00 Lower Non Recoverable 00 Threshold Lower Critica
287. orts assign x1 x2 or x4 lanes to ports 0 1 8 9 100r 11 Link power management states LO LOs L1 L2 L3 Ready and L3 and device power management states DO and D3hot EEPROM interface signals boundary scan interface signals Compliant with PCI Express Base 1 0a and PCI Standard Hot Plug r1 0 The device ID for the PEX 8524 switch reads 8532h because the PEX 8524 and PEX 8532 share the same base device For more information reference the PEX 8524 Versatile PCI Express Switches Data Book Proprietary information on the PCle switch is not available in this user s manual Please refer to the PLX Technology web site for documentation http www plxtech com 10007175 02 KAT4000 User s Manual Common Switch Region PCI Express Switch optional PCI Express Interface Figure 4 3 8524 Block Diagram qnm m guo vm Een quum en m Station 0 Station 1 1 Ingress Egress Lanes Scheduler Scheduler Lanes Crossbar Crossbar Switch Switch gt Ingress Egress PCI Express Non Blocking PCI Express Upstream Crossbar Downstream Mq Station 0 Switch Fabric Station 1 lt gt Crossbar Crossbar Switch Switch Egress Ingress Egress Ingress Scheduler
288. ote OA amp M system over Ethernet COMPONENTS AND FEATURES The following is a brief summary of the KAT4000 hardware components and features The Central Processing Unit CPU is a Freescale Semiconductor MPC8548 PowerQUICC processor operating at a rate of up to 1 3 GHz with a 533 MHz DDR2 bus The MPC85468 contains 32 kB separate level one L1 data and instruction caches and 512 kB L2 cache The processor has a local bus that connects to the socketed NOR and NAND flash Ethernet core switch fat pipe switch module and PLD The processor also has a COP JTAG for debugging purposes Chapter 3 provides more information The KAT4000 includes a 64M x 72 bit Double Data Rate Two DDR2 Synchronous Dynamic Random Access Memory SDRAM Small Outline Dual In line Memory Module SO DIMM Options include 512 megabytes and 1 gigabyte The interface implements eight additional bits to permit the use of Error Correcting Code ECC SDRAM is only implemented on the processor KAT4000 board configuration On Card SDRAM on page 6 2 provides more information The KAT4000 includes three independent Flash regions socketed NOR and NAND The blade is capable of booting from either an 8 bit 32 pin PLCC ROM socket up to 512 kilo bytes in size or from a 16 bit NOR Flash region that consists of one or two Flash devices 10007175 02 KAT4000 User s Manual Overview Components and Features CPLD Ethernet Serial I O IC Bus JTAG
289. pecific PICMG Front Device Yes Link F1 Discrete 6F Board A0 relative 60 BMC Watchdog Watchdog 2 23 Sensor specific Processor 03 Device Yes Discrete 6F relative 60 48V Volt Voltage 02 Threshold 01 Power Supply 0A Device Yes relative 60 48V Curr Current 03 Threshold 01 Power Supply 0A Device Yes relative 60 48V Feed A Volt Voltage 02 Threshold 01 Power Supply 0A Device Yes relative 60 48V Feed B Volt Voltage 02 Threshold 01 Power Supply 0A Device Yes relative 60 3 3V Mgmt Voltage 02 Threshold 01 Power Supply 0A Device Yes relative 60 12V Volt Voltage 02 Threshold 01 Power Supply 0A Device Yes relative 60 12V Curr Current 03 Threshold 01 Power Supply 0A Device Yes relative 60 3 3V Voltage 02 Threshold 01 Power Device Yes Module DCto DC relative 60 Converter 14 2 5V Voltage 02 Threshold 01 Power Device Yes Module DCto DC relative 60 Converter 14 1 8V Voltage 02 Threshold 01 Power Device Yes Module DCto DC relative 60 Converter 14 1 5V Voltage 02 Threshold 01 Power Device Yes Module DCto DC relative 60 Converter 14 1 2V Voltage 02 Threshold 01 Power Device Yes Module DCto DC relative 60 Converter 14 1 0V Voltage 02 Threshold 01 Power Device Yes Module DCto DC relative 60 Converter 14 10007175 02 KAT4000 User s Manual g System Management sensors and Sensor Data Records Sensor Name Entity Event continued Sensor Type Event Reading Type Entity ID Instance CPU Volt Voltage 02 Thresh
290. ported _ Deassertion Event Mask 4801 Lower Non Recoverable Threshold comparison returned _ Upper Non Recoverable Going High supported Lower Non Critical Going Low supported 10007175 02 KAT4000 User s Manual Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Discrete Reading Mask Upper Non Recoverable Threshold settable Upper Critical Threshold settable Upper Non Critical Threshold settable Lower Non Recoverable Threshold settable Lower Critical Threshold settable _ Lower Non Critical Threshold settable Non Recoverable Threshold readable Upper Critical Threshold readable Upper Non Critical Threshold readable Lower Non Recoverable Threshold readable Lower Critical Threshold readable Lower Non Critical Threshold readable Sensor Units 1 00 Analog Data Format unsigned _ Rate Unit none Modifier Unit none Percentage no Sensor Units 2 Base Unit 04 Volts Sensor Units 3 Modifier Unit 200 Unspecified Linearization 00 M 23 M Tolerance 40 00 B Accuracy 00 Accuracy Accuracy Exp 00 R exp B Exp do Analog Characteristic Flags 07 Nominal Reading a5 Normal Maximum 8 Normal Minimum 7c Sensor Maximum Reading Sensor Minimum Reading 00
291. r Module DC to DC Converter Entity Instance 60 Sensor Initialization 7f Init Scanning Init Sensor Type Init Hysteresis Init Thresholds Init Events Sensor Scanning enabled Event Generation enabled Sensor Capabilities 69 Ignore Sensor no Auto Re Arm enabled Sensor Hysteresis hysteresis is settable readable Sensor Threshold Access threshold is settable readable Event Message Control global disable only Sensor Type 02 Voltage Event Reading Code 01 Threshold Assertion Event Mask 4000 Lower Non Recoverable Threshold comparison returned Deassertion Event Mask 4000 Lower Non Recoverable Threshold comparison returned 10007175 02 KAT4000 User s Manual Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Discrete Reading Mask Upper Non Recoverable Threshold settable Upper Critical Threshold settable Upper Non Critical Threshold settable Lower Non Recoverable Threshold settable Lower Critical Threshold settable B Lower Non Critical Threshold settable Non Recoverable Threshold readable Upper Critical Threshold readable Upper Non Critical Threshold readable Lower Non Recoverable Threshold readable Lower Critical Threshold readable Lower Non Critical Threshold readable Sensor Units 1 00 Analog Data Format unsigne
292. r Non Recoverable Threshold readable Upper Critical Threshold readable Upper Non Critical Threshold readable Sensor Units 1 00 Analog Data Format unsigned Rate Unit none Modifier Unit none Percentage no Sensor Units 2 Base Unit 04 Volts B 40 KAT4000 User s Manual 10007175 02 Appendix B sensor Data Records KAT4000 Records _ Value Parameter Status continued Sensor Units 3 Modifier Unit 00 Unspecified Linearization 00 06 M Tolerance 00 B 00 B Accuracy 00 Accuracy Accuracy Exp 00 00 0 Analog Characteristic Flags 07 Nominal Reading c8 Normal Maximum d6 Normal Minimum 00 Sensor Maximum fe Reading Sensor Minimum Reading 00 Upper Non Recoverable Threshold Upper Critical Threshold 00 Upper Non Critical Threshold 00 Lower Non Recoverable 00 Threshold Lower Critical Threshold 00 Lower Non Critical Threshold 00 Positive Going Threshold Hyst 02 Value Negative Going 00 Threshold Hyst Value ID String Length Code cc Table B 25 B4 12V Current SDR Description KAT4000 Records Value Parameter Status Record ID 0017 _ SDR Version 51 _ Record Type 01 Full Sensor Record Record Length 37
293. r setup of the devices driving data onto and receiving data from the inter connecting transmission lines is important for optimal performance Configurable device parameters include drive strength gain impedance equalization and pre emphasis The configuration of some serial paths has been set by Emerson and should not be changed For paths that go off the board e g to AMC sites the backplane the user must be aware of device register settings for devices at both ends of the transmission line and set them appropriately to meet device specifications and achieve full bandwidth performance 10007175 02 KAT4000 User s Manual Common Switch Region Ethernet Core Switch optional Caution A Note Table 4 1 Note Table 4 2 mn KAT4000 User s Manual On Board Path Device Settings On board device values are determined by Emerson Do not change these values Altering on board device values could cause system failure Proprietary information regarding register function or effect is not available in this user s manual Please contact the PHY or switch manufacturer directly for details Table 4 1 lists the KAT4000 PHYs and their respective addresses KAT4000 PHYs and Address Values PHY Address Base Channel 1 TSEC2 0 2 Base Channel 2 TSEC3 O3 TSEC2 from CPU to Ethernet switch 0 4 TSEC3 from CPU to Ethernet switch 0 5 Fat Pipe TSEC4 0x6 The Ethernet core switch has the following on board po
294. r two kilobits of each device The remainder of each device is available for the user s application Table 6 2 and Table 6 3 define the organization of data within the SROMs NVRAM Memory Map User EEPROM 1 write protected T Address Offset hex Name Window Size bytes Boot verify secondary area 16 Ox1FEO Ox1FEF Boot verify primary area 16 0x1 EE0 0x1 EEF Operating system parameters 256 0x0000 0x1EDF User defined 7903 1 EEPROM 1 is write protected to facilitate securing data 2 The boot verify areas are for redundancy e g if an application stops working access the secondary boot data area to bring up a working application 3 The operating system parameters area is for future VxWorks implementation NVRAM Memory Map User EEPROM 2 Address Offset hex Window Size bytes Ox1FF0 Ox1FFF Emerson reserved area 5887 0x0800 0x08FF Miscellaneous 256 0x07F0 0x07FF Power on self test POST 16 0x0000 0x07EF User defined 2032 4 The Emerson reserved area is for Emerson internal use only for test software error logging and miscellaneous data storage 10007175 02 KAT4000 User s Manual blank page KAT4000 User s Manual 10007175 02 CPLD Table 7 1 In addition to reset and interrupt registers the complex programmable logic device CPLD provides the peripheral bus interface for user LEDs configuration jumpers board revision boot device selection and the
295. rameter Status Record ID 0005 SDR Version 51 Record Type 01 Full Sensor Record Record Length 230 _ Sensor Owner ID 00 _ Sensor Owner LUN 00 Sensor Number 00 Entity ID 14 Power Module DCto DC Converter Entity Instance 60 E Sensor Initialization 7f nit Scanning Init Sensor Type Init Hysteresis Init Thresholds Init Events Sensor Scanning enabled Event Generation enabled 10007175 02 KAT4000 User s Manual Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Sensor Capabilities 69 Ignore Sensor no Auto Re Arm enabled Sensor Hysteresis hysteresis is settable readable Sensor Threshold Access threshold is settable readable Event Message Control global disable only Sensor Type 02 Voltage Event Reading Type Code 01 Threshold Assertion Event Mask 4000 Lower Non Recoverable Threshold comparison returned Deassertion Event Mask 4000 Lower Non Recoverable Threshold comparison returned Discrete Reading Mask Upper Non Recoverable Threshold settable Upper Critical Threshold settable Upper Non Critical Threshold settable Lower Non Recoverable Threshold settable Lower Critical Threshold settable Lower Non Critical Threshold settable Upper Non Recoverable Threshold readabl
296. rd SDRAM Chip Select Generation The MPC8548 memory controller functions as a chip select CS generator to access on board memory devices saving the board s area which results in reduced cost power con sumption and increased flexibility Table 3 4 lists the chip selects for the KAT4000 module MPC8548 Chip Select Select Assignment CSO Boot Socketed or NOR Flash CS1 Flash 0 CS2 Flash 1 CS3 Socketed Flash cs4 Programmable Logic Device PLD CS5 NAND Flash cs6 Ethernet Core Switch cs7 Fat Pipe 2 Jumper selectable see Jumpers on page 2 5 for jumper options PROCESSOR RESET AND CLOCKING SIGNALS The MPC8548 external reset and clocking signals include Hard Reset input completely resets the MPC8548 and causes a power on reset POR sequence Hard Reset Request output causes internal block requests that HRESET be asserted This can be requested by a hardware device for example a watchdog timer event Soft Reset input causes a machine check interrupt assertion to the e500 core to undergo its soft reset sequence Ready output means the MPC8548 has completed the reset operation and is not in a power down nap doze or sleep or debug state 10007175 02 Central Processing Unit MPC8548 Exception Handling SYSCLK System Clock is the primary clock input to the e500 core and all the devices and interfaces that operate synchronously with the core RTC Table 3 5 IVOR
297. rds Value Parameter Status continued Sensor Minimum Reading 00 E Upper Non Recoverable ff Threshold Upper Critical Threshold 00 Upper Non Critical Threshold 00 Lower Non Recoverable 00 Threshold Lower Critical Threshold 00 Lower Non Critical Threshold 00 Positive Going Threshold Hyst 03 Value Negative Going Threshold Hyst 00 Value OEM 00 ID String Type Length Code cc Table B 20 B1 12V Volt SDR Description KAT4000 Records Value Parameter Status Record ID 0012 SDR Version 51 Record Type 01 Full Sensor Record Record Length 37 Sensor Owner ID 00 Sensor Owner LUN 00 Sensor Number 00 Entity ID ci Module Entity Instance 65 Sensor Initialization 5d Init Scanning Init Sensor Type Init Hysteresis Init Thresholds Sensor Scanning enabled Sensor Capabilities 69 Ignore Sensor no Auto Re Arm enabled Sensor Hysteresis hysteresis is settable readable Sensor Threshold Access threshold is settable readable Event Message Control global disable only Sensor Type 02 Voltage Event Reading Type Code 01 Threshold Assertion Event Mask 0800 Upper Non Recoverable Going High supported 10007175 02 KAT4000 User s Manual B 33 Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued
298. re 5 4 GbE Fat Pipe Switch Module Component Top Rev 00 B vias TED B BBBB ra eb agg Bw ti U5 BBE 027 VSC7376 26 Port Q wo L1 5 i 5 6 GbE Switch ES ms 1 for processorless 2 15 E i C22 Switch SRAM cmi Du 07 Flash for processorless KAT4000 J2 Figure 5 5 GbE Fat Pipe Switch Module Component Map Bottom Rev 00 ABARRA BEBEBEBB m BEBE Em E Ed B Ed Ed m Er 8 E ES B Bg 2 5 B eg KAT4000 User s Manual 10007175 02 Fat Pipe Switch Module GbE rat Pipe Switch Module Components and Features The following is a summary of the GbE fat pipe switch module hardware components and features VSC7376 HawX G26 GbE Switch The Vitesse VSC7376 GbE switch is a multilayer switch with 26 tri speed 10 100 1000 Mbps SGMII Ethernet ports and integrated 1000Base BX SerDes interfaces It is located from FC16 0000 FC17 FFFF This type of switch is als
299. re optional arguments and describe the objects on which the command oper ates If you do not specify a flag memory commands default to 32 bit long words Numeric arguments are in hexadecimal 10007175 02 Monitor Memory Commands Definition Note Definition Example Definition Example Definition Example cmp The cmp command compares count objects between addr1 and addr2 Any differences are displayed on the console display b w 1 addrl addr2 count cp The cp command copies count objects located at the source address to the target address If the target address is located in the range of the Flash device it will program the Flash with count objects from the source address The cp command does not erase the Flash region prior to copying the data The Flash region must be manually erased using the erase command prior to using the cp command cp b w 1 source target count In this example the cp command is used to copy 0x1000 32 bit values from address 0x100000 to address 0x80000 cp 100000 80000 1000 find The find command searches from base addrto top addr looking for pattern For the find command to work properly the size of pattern must match the size of the object flag The a option searches for the absence of the specified pattern find b w 1 a base addr top addr pattern In this example the find command is used to search for the 32 bit pattern 0x12345678 in the ad
300. requests 02 request 03 response responses message contains data for bridging to the next bus Typically the data is another message which also may be a bridging message This function is only present on bridge nodes 04 05 Sensor sensor and event 04 command request 05 response Event requests responses for configuration and transmission of Event Messages and system Sensors This function may be present on any node 06 07 App application 06 command request 07 response requests responses message is implementation specific for a particular device as defined by the IPMI specification 08 09 Firmware firmware transfer 08 command request 09 response requests responses firmware transfer messages match the format of application messages as determined by the particular device 0A OB Storage non volatile command request response storage requests may be present on any node that provides responses nonvolatile storage and retrieval services Reserved reserved 36 network functions 18 pairs 30 3F OEM vendor specific 16 network functions 8 pairs The vendor defines functional semantics for cmd and data fields The cmd field must hold the same value in requests and responses for a given operation to support IPMI message handling and transport mechanisms The controller s Manufacturer ID value identifies the vendor or group 10007175 02 KAT4000 User s Manual System Management IPMI Messa
301. reshold settable Lower Critical Threshold settable Lower Non Critical Threshold settable Upper Non Recoverable Threshold readable Upper Critical Threshold readable Upper Non Critical Threshold readable Lower Non Recoverable Threshold readable Lower Critical Threshold readable Lower Non Critical Threshold readable Sensor Units 1 00 Analog Data Format unsigned Rate Unit none Modifier Unit none Percentage no Sensor Units 2 Base Unit 04 Volts Sensor Units 3 Modifier Unit 00 Unspecified Linearization 00 M a2 M Tolerance 00 B 00 B Accuracy 00 Accuracy Accuracy Exp 00 R exp B Exp cO Analog Characteristic Flags 07 Nominal Reading cc KAT4000 User s Manual 10007175 02 Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Normal Maximum 96 Normal Minimum c2 Sensor Maximum Reading Sensor Minimum Reading 00 Upper Non Recoverable f5 Threshold Upper Critical Threshold 00 Upper Non Critical Threshold 00 _ Lower Non Recoverable a3 Threshold Lower Critical Threshold 00 _ Lower Non Critical Threshold 00 _ Positive Going Threshold Hyst 02 ES Value Negative Going 02 Threshold Hyst Value OEM 00 ID String Type Length Code c5 Table B 7 2 5 Volt SDR Description KAT4000 Records Value Pa
302. ress Command 9 18 Table 9 14 Get Handle Switch 9 18 Table 9 15 Set Handle Switch 9 19 Table 9 16 Get Payload Communication Time Out Command 9 19 Table 9 17 Set Payload Communication Time Out Command 9 20 Table 9 18 Disable Payload Control 9 20 Table 9 19 ResetIPMC 2 2 9 21 Table 9 20 Hang IPMC Command 9 21 Table 9 21 Bused Resource Control 9 22 Table 9 22 Resource Status 9 23 Table 9 23 Graceful Reset Command 9 24 Table 9 24 X Diagnostic Interrupt Results 9 24 Table 9 25 Get Payload Shutdown Time Out 9 25 Table 9 26 Set Payload Shutdown Time Out 9 25 Table 9 27 Get Module State Command 2 9 25 Table 9 28 Enable AMC Site 2 9 26 Table 9 29 Disable AMC Site
303. rmats and associated commands include Executable binary files go VxWorks and QNX ELF bootm bootvx or bootelf Compressed gzipped VxWorks and QNX ELF bootm Linux kernel images bootm Compressed gzipped Linux kernel images bootm Motorola S Record S Record download uses the standard Motorola S Record format This includes load address section size and checksum all embedded in an ASCII file 10007175 02 Acronym List AMC ASCII ATA ATCA BIOS BDRR BMC Cmd CPU CRT CSA CT DDR2 ECC EIA EMC ESD ETSI FCC FRU GbE GMII GNU GPIO GPL 2 1 IEC 10 IPMB IPMC IPMI ISP IVOR JTAG LED Advanced Mezzanine Card American Standard Code for Information Interchange Advanced Technology Attachment Advanced Telecom Computing Architecture or AdvancedTCA Basic Input output System Boot Device Redirection Register Baseboard Management Controller Command code Central Processing Unit Cathode Ray Tube Canadian Standards Association Computer Telephony Double Data Rate Two European Community Error correcting Code Electronic Industries Alliance Electromagnetic Compatibility Electrostatic Discharge European Telecommunications Standards Institute Federal Communications Commission Field Replaceable Unit Gigabit Ethernet Gigabit Media Independent Interface GNU s Not Unix General Purpose Input Output General Public License Inter integrated Circuit Internet Assigned Numbers
304. rmware upgrade ses sion has not been opened yet If it has the Boot Loader returns a reply with the OxD1 Device In Firmware Update Mode completion code If a firmware upgrade session has not been opened yet the Boot Loader opens it and returns a success reply This command is supported by both the IPMC firmware and the Boot Loader Table 9 45 Firmware Upgrade Start Command KAT4000 User s Manual Type Byte Data Field Request Data 1 Checksum Response Data 1 Completion Code 10007175 02 System Management Firmware Upgrade Table 9 46 Firmware Upgrade Prepare Command The Firmware Upgrade Prepare command prepares the IPMC for programming of a new firmware image Preparation of the slave H8S flash memory includes only erasing the slave 85 flash while preparation of the master 85 flash memory includes the following Erasing the backup copies of the firmware in the master 85 flash Making a backup copy of the master 85 firmware in the master 85 flash Fetching the slave H8S firmware over SPI and making a backup copy of it in the master 85 flash Erasing the master 85 firmware area This command is supported only by the Boot Loader If the IPMC firmware receives this command it sends a reply with the OxC1 Invalid Command completion code Firmware Upgrade Prepare Command Type Byte Data Field Request Data 1 This specifies the target device that should be prepared for programming and must have one of
305. rom the EEPROM Figure 4 4 8524 SPI EEPROM Interface 3 3 8524 Station 0 Station 1 itin RM EE DO EEPROM EEPROM Controller Configuration Data JTAG Controller Interface The PEX 8524 supports a five pin JTAG interface that complies with IEEE standard 1149 1 and 1149 6 Boundary Scan signals The JTAG interface consists of the following signals Table 4 5 PEX 8524 Signals Signal Signal Type Description JTAG_ TCK Test clock This is the clock source for the 8524 Test Access Port TAP and may be any frequency from 0 to 10 MHz _ TDI Test data input in This inputs data to the TAP TDO Testdata out This transmits serial data from the TAP output 5 Test mode The TAP state machine uses the TMS to select determine the mode TRST Test reset dn This resets JTAG and the TAP It should be toggled or held at 0 for the PEX 8524 to function properly 10007175 02 KAT4000 User s Manual B blank page E KAT4000 User s Manual 10007175 02 Fat Pipe Switch Module The fat pipe switch module is a plug over module that provides a high speed interconnect between the AMC modules the ATCA high speed fabric ports the processor and the Ethernet core switch or the PCle switch on the KAT4000 There are four configur
306. rovides the interconnect between the fat pipe switch module the Ethernet ports on the AMC sites the processor two channels on the ATCA backplane base fabric Zone 3 and the Update Channel optional see Fig 4 1 The PCI Express switch provides the interconnect between the AMC sites the processor and the fat pipe switch module Both switches are optional however at least one of the two must be used on the board The board can also use both switches Board Area Network AMC x4 Single Wide Mid Size or Compact 7 10 0 2 B1 12 13 B2 18 20 B3 22 24 B4 11 14 16 7376 Ethernet Core Switch Layer 2 Optional 4 SERDES TSEC2 TSEC3 TSEC4 MPC8548 Processor Optional 558 8 11 B3 GbE Fat Pipe 14 17 B4 Switch Module Optional 18 21 82 Zone 3 gt Connections 2 3 Opt 4 SERDES IPMB Base High Speed High Speed Clock RTM abric A abric B Optional P10 23 20 Zone3 10007175 02 KAT4000 User s Manual Common Switch Region Ethernet Core Switch optional ETHERNET CORE SWITCH OPTIONAL Note 4000 User s Manual The optional Vitesse VSC7376 GbE switch is a multilayer switch with 26 tri speed 10 100 1000 Mbps SGMII Ethernet ports and integrated 1000Base BX SerDes inter faces The GbE switch supports the following Two SGMII Ethernet ports connected from the switch to the ATCA backplane base fabric via PHYs PICMG 3 0 Two
307. rs in all of the Flash banks erase all flinfo The flinfo command prints out the Flash device s manufacturer part number size number of sectors and starting address of each sector Print information for all Flash memory banks flinfo Print information for the Flash memory in bank flinfo N 10007175 02 KAT4000 User s Manual hes Monitor EEPROM I2C Commands Definition Definition 4000 User s Manual protect The protect command enables or disables the Flash sector protection for the specified Flash sector Protection is implemented using software only The protection mechanism inside the physical Flash part is not being used Protect all of the Flash sectors in the address range from start to end protect on start end Protect all of the sectors SF first sector to SL last sector in Flash bank protect N SF SL Protect all of the sectors in Flash bank N protect on bank N Protect all of the sectors in all of the Flash banks protect on all Remove protection on all of the Flash sectors in the address range from start to end protect off start end Remove protection on all of the sectors SF first sector to SL last sector in Flash bank N protect off N SF SL Remove protection on all of the sectors in Flash bank N protect off bank N Remove protection on all of the sectors in all of the Flash banks protect off all EEPROM I2C COMMANDS This section describes com
308. rt Pin Assignments P3 KAT4000 User s Manual Pin Signal Pin Signal 1 TX 5 connect 2 6 RX 3 RX 7 no connect 4 28 no connect Zone 3 P30 P32 are the ATCA 80 pin Zone 3 ZD connectors for routing serial host and fat pipe data See Table 12 4 Table 12 5 and Table 12 6 for pin assignments The 24 Zone P33 connector routes serial I O to the AMCs See Table 12 7 for pin assign ments SETUP You need the following items to set up and check the operation of the Emerson KAT Z3DB The KAT4000 baseboard Compatible AMC modules 7 Micro D cable Emerson part number C0007665 00 cross pinned or C0007664 00 straight through 10007175 02 Rear Transition Module Installation Caution A Caution A Note Card cage and power supply Computer terminal When you unpack the module save the antistatic bag and box for future shipping or stor age Identification Numbers Before you install the KAT Z3DB in a system you should record the following information The board serial number 711 The board serial number appears on a bar code sticker located at the top of the board near A1 see Fig 13 2 The board product identification ID This product ID sticker is located in the middle of the board across from P5 and P6 see Fig 13 2 It is useful to have these numbers available when you contact Technical Support at Emer son INSTAL
309. rts 14 15 16 and 17 The Ethernet switch on the GbE fat pipe switch module uses on board port 13 Off Board Path Device Settings Modify off board register values with the switch reg or phy commands See phy page 14 25 or switch reg page 14 27 for details Proprietary information regarding register function or effect is not available in this user s manual Please contact the switch manufacturer directly for details Table 4 2 shows the Ethernet core switch default off board ports Ethernet Core Switch Off Board Ports Destination Port Update Channel 7 8 9 10 Zone 3 4 6 1 4 12 13 18 20 1 10007175 02 Common Switch Region Ethernet Address for the KAT4000 Table 4 3 shows the GbE fat pipe s Ethernet switch default off board ports Table 4 3 GbE Fat Pipe Module Ethernet Switch Off Board Ports Destination Port AMC1 22 23 24 25 AMC2 18 19 20 21 AMC3 8 9 10 11 AMC4 14 15 16 17 Fabric Channel 1 4 5 6 7 Fabric Channel 2 0 1 2 3 Ethernet Transceivers The Marvell 88E1111 gigabit Ethernet transceivers are used to interface between the pro cessor MACs and the Ethernet switch ports They are also used to connect two switch ports to the backplane base channel 1 and 2 interfaces The 88E1111 device is 10 100 1000BASE T IEEE 802 3 compliant The Broadcom BCM5241 10 100BASE TX FX transceiver provides a physical interface to the processor s debug Ethernet MAC eTSEC1 The BCM5241 complies with
310. rved PCI Bus Bridge EEPROM Write Protect 0 Writing to EEPROM is disabled 1 Writing to EEPROM is enabled Switch JTAG Enable 0 is disabled switch does not operate Switch register CMIC_TAP_CONTROL is enabled for JTAG control of the switch via PCI or IC When this bit is cleared the PLD and PCI bus bridge are inaccessible over 1 JTAG is enabled normal switch operation Switch Reset 0 Switch not held in reset 1 Switch held in reset 10007175 02 Fat Pipe Switch Module 10 GbE 1 GbE Fat Pipe Switch Module Note Software must ensure that the switch is held in reset for the minimum amount of time as listed in the Ether net switch data sheet Module Status Register The read only Module Status register contains information relating to the module status such as power supply state switch operational mode and switch interrupt state Register 5 14 Module Status Register STAT at 0x05 7 6 5 4 3 2 1 0 reserved 53 3 S2V5 51 0 reserved R Reserved S3V3 3 3V Power Supply Status 0 Power supply out of spec 1 Power supply within spec S2V5 2 5V Power Supply Status 0 Power supply out of spec 1 Power supply within spec S1V2 1 0V Power Supply Status 0 Power supply out of spec 1 Power supply within spec Switch GPIO Register The Switch GPIO register drives the GPIO signals on the PLX8111 PCle to the PCI bridge Default is 0x00 Register 5 15 Switch GPIO Register GPIO at 0x06 7 6 5
311. s 8 1 customer support See technical support D DRAM 6 2 1 1 reference manual 1 14 E EEPROM reference manual 1 13 EIA 232 2 4 E keying 9 45 12 2 14 1 environment parameter commands sce cu some mee pae c 14 20 environment variables 14 7 equipment for setup 2 15 ESD 2 1 Ethernet 55 4 5 Artesyn identifier 4 5 2 4 4 2 1 2 reference manual 1 13 transceivers 4 5 ethernet core switch 1 3 Ethernet switch configuration 4 3 exception handling CPU 3 13 10007175 02 F fat pipe switch GbE 1 5 11 PLD registers 5 16 10 GbE 10 GbE 5 21 m 5 2 PLD registers 5 6 1 4 5 1 opp 5 22 features IPMI x aii att rre Bide 9 1 1 1 figures iii ix file load commands monitor 14 12 Flash commands monitor 14 15 1 1 reference manual 1 13 6 1 2 8
312. s are hard coded inside the PLD 10007175 02 Fat Pipe Switch Module GbE rat Pipe Switch Module Register 5 1 Product ID Version Register PIDV at 0x00 7 6 5 4 3 2 1 0 PID3 PID2 PID1 PIDO PVERT PVERO HVERO PID3 PIDO Product ID 0000 Fat Pipe Module GbE 0001 Fat Pipe Module sRIO 0010 Fat Pipe Module 10 GbE 1 GbE 0011 Fat Pipe Module 10 GbE 10 GbE All other values are reserved PVER1 PVERO PLD Version 00 Revision 00 HVER1 HVERO Hardware Version 00 Revision 00 Scratch Register The Scratch register can be used by software for reads and writes Accessing this register does not have any affect on operations Default is 0x00 Register 5 2 Scratch Register SCR at 0x01 7 6 5 4 3 2 1 0 SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCRO SCR7 SCRO Scratch Register The register controls operations on the 1 C bus Default is OxOf Register 5 3 12C Register I2C at 0x02 7 6 5 4 3 2 1 0 reserved SDA SCL ADDO R Reserved SDA SDA Control 0 Drives logic 0 on the data line 1 Tristates data line pulled high externally 10007175 02 KAT4000 User s Manual Fat Pipe Switch Module GbE rat Pipe Switch Module SCL ADD1 ADDO Register 5 4 SDET7 SDETO Register 5 5 SRST Note 4000 User s Manual SCL Control 0 Drives logic 0 on the clock line 1 Tr
313. scan instructions and data Test Mode Select this input signal is the test access port TAP controller mode signal Hard Reset this input signal indicates that a complete Power on Reset must be initiated by the processor Soft Reset this input signal indicates that the processor must initiate a System Reset inter rupt Test Reset this input signal resets the test access port NO PROCESSOR CONFIGURATION If a processor is not used on the KAT4000 the Ethernet core switch and GbE fat pipe switch module optional are managed by an 8051 microcontroller internal to each switch Cus tom configuration of the switch is possible through one of two user interfaces on each switch See Appendix A for more information 10007175 02 KAT4000 User s Manual 3 15 blank page 3 16 KAT4000 User s Manual 10007175 02 Section 4 Common Switch Region Figure 4 1 PEX8524 PCI Express Switch Optional 8 B1 9 B2 10 83 11 4 2 SERDES 1 To Zone 3 lt gt 19 2 SERDES GMII RGMII 10 100 Debug Eth MII 15 17 gt Optional The KAT4000 supports multiple interfaces This chapter describes the Ethernet core switch switch configuration Ethernet address and PCI Express switch The board area network BAN refers to the routing of the Ethernet ports using the Vitesse VSC7376 Gigabit Ether net GbE core switch or the PCle ports using the PEX 8524 PCI Express switch The Ethernet core switch p
314. ser s Manual 5 11 Fat Pipe Switch Module 10 GbE 1 GbE Fat Pipe Switch Module The following block diagram provides a functional overview for the 10 GbE 1 GbE fat pipe switch module Figure 5 10 10 GbE 1 GbE Fat Pipe Switch Module Block Diagram SDA SCL 17 GbE LED Interface 56580 ports 16 port GbE 4 10 GbE Switch PCI Management Interface 5 Q po lt PEX8111 PCle to PCI Bridge Address bus 8 bit data bus E KAT4000 User s Manual 10007175 02 Fat Pipe Switch Module 10 GbE 1 GbE Fat Pipe Switch Module 10 GbE 1 GbE Fat Pipe Switch Module Circuit Board The following figures show the component maps for the 10 GbE 1 GbE fat pipe switch mod ule circuit board Figure 5 11 10 GbE 1 GbE Fat Pipe Switch Module Component Map Top Rev 01 Em Ji Le leg _ E us g B Tr NE 80156580 5 197 dij 16 Port GbE UN U 5 4 Port 10 GbE PLD E Switch E 24 m pue Gs Q Bl J2 Y2 Figure 5 12 10 GbE 1 GbE Fat Pipe Switch Module
315. serprio lt portlist gt lt tagprio gt Description Set or show the default VLAN user priority for received untagged frames lt portlist gt Port list Default All ports 10007175 02 KAT4000 User s Manual Appendix A serial Command Line Interface CLI QoS Shaper QoS Policer Mirror Configuration Mirror Port Mirror Source IP Configuration E KAT4000 User s Manual tagprio VLAN tag user priority 0 7 Default Show user priority Syntax QoS Shaper lt portlist gt disable lt rate gt Description Set or show the shaper configuration lt portlist gt Port list Default All ports disable lt rate gt Disable or set leaky bucket rate to a of the port speed 0 100 Default Show shaper rate Syntax QoS Policer lt portlist gt disable lt rate gt Description Set or show the policer configuration lt portlist gt Port list Default All ports disable rate Disable or set leaky bucket rate to a of the port speed 0 100 Default Show policer rate Mirror Commands Syntax Mirror Configuration Description Show the mirror destination port and mirror mode for source ports Syntax Mirror Port lt port gt Description Set or show the mirror destination port port Mirror destination port Default Show mirror port Syntax Mirror Source lt portlist gt enable disable Description Set or show the source port mirror
316. shold Hyst 03 Value _ Negative Going 00 Threshold Hyst Value OEM 00 10007175 02 KAT4000 User s Manual B 39 Appendix B sensor Data Records KAT4000 Records ID String Type Length Code Value cc Parameter Status continued Table B 24 12V Volt SDR Description KAT4000 Records Value Parameter Status Record ID 0016 SDR Version 51 m Record Type 01 Full Sensor Record Record Length 37 Sensor Owner ID 00 Sensor Owner LUN 00 Sensor Number 00 Entity ID ci AMC Module Entity Instance 67 Sensor Initialization 5 Init Scanning Init Sensor Type Init Hysteresis Init Thresholds Sensor Scanning enabled Sensor Capabilities 69 Ignore Sensor no Auto Re Arm enabled Sensor Hysteresis hysteresis is settable readable Sensor Threshold Access threshold is settable readable Event Message Control global disable only Sensor Type 002 Voltage Event Reading Type Code 10 Threshold Assertion Event Mask 0800 Upper Non Recoverable Going High supported Deassertion Event 4800 Lower Non Recoverable Threshold comparison returned Upper Non Recoverable Going High supported Discrete Reading Mask 3838 Upper Non Recoverable Threshold settable Upper Critical Threshold settable Upper Non Critical Threshold settable Uppe
317. t 05 Amps 10007175 02 KAT4000 User s Manual B 35 Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Sensor Units 3 Modifier Unit 00 Unspecified Linearization 00 M 8a M Tolerance 40 B 00 B Accuracy 00 Accuracy Accuracy Exp 00 R exp B Exp cO Analog Characteristic Flags 07 Nominal Reading 66 Normal Maximum bf Normal Minimum 00 Sensor Maximum Reading ff Sensor Minimum Reading 00 Upper Non Recoverable ff Threshold Upper Critical Threshold 00 Upper Non Critical Threshold 00 Lower Non Recoverable 00 Threshold Lower Critical Threshold 00 Lower Non Critical Threshold 00 Positive Going Threshold Hyst 03 x Value Negative Going Threshold Hyst 00 Value OEM 00 ID String Type Length Code cc Table B 22 B2 12V Volt SDR Description KAT4000 Records Value Parameter Status Record ID 0014 SDR Version 51 Record Type 01 Full Sensor Record Record Length 37 Sensor Owner ID 00 Sensor Owner LUN 00 Sensor Number 00 Entity ID c1 AMC Module Entity Instance 66 B 36 KAT4000 User s Manual 10007175 02 Appendix B sensor Data Records KAT4000 Records _ Value Paramet
318. t Debug Level OEM 2E 2F 00 04 Get Hardware Address OEM 2E 2F 00 05 Set Hardware Address OEM 2E 2F 00 06 Get Handle Switch OEM 2E 2F 00 07 Set Handle Switch OEM 2E 2F 00 08 Get Payload Communication OEM 2E 2F 00 09 Time Out Set Payload Communication OEM 2E 2F 00 Time Out Enable Payload Control OEM 2E 2F 00 0B Disable Payload Control OEM 2E 2F 00 0C Reset IPMC OEM 2E 2F 00 00 Hang 2E 2F 00 OE Bused Resource Control OEM 2E 2F 00 OF Bused Resource Status OEM 2E 2F 00 10 Graceful Reset OEM 2E 2F 00 11 Diagnostic Interrupt Results OEM 2E 2F 00 212 Get Payload Shutdown Time OEM 2E 2F 00 15 Out 5 Payload Shutdown Time OEM 2E2F 00 16 Out _ Get Module State 2E2F 00 27 Enable AMC Site OEM 2E2F 00 28 Disable AMC Site OEM 2E2F 00 29 Get Status Command The IPMC firmware notifies the payload about changes of all status bits except for bits 0 2 by sending an unprintable character ASCII 07 BELL over the Payload Interface The pay load is expected to use the Get Status command to identify pending events and other SIPL 4000 User s Manual 10007175 02 System Management vendor Commands commands to provide a response if necessary The event notification character is sent in a synchronous manner and does not appear in the contents of SIPL messages sent to the payload Table 9 7 Get Status Command Type Byte Data Field Request Data 1 3 PPS IANA Private E
319. t FRU LED State command allows the state of the FRU LEDs to be controlled by the management system Table 9 37 Set FRU LED State Command Type Request Data 9 36 KAT4000 User s Manual Byte 1 Data Field PICMG Identifier indicates that this is a PICMG defined group extension command Use value 00h FRU Device ID LED ID 00h Blue LED Hot Swap 01h LED 1 005 02h LED 2 03h LED 3 04h FEh OEM defined LEDs FFh Lamp Test all LEDs under management control are addressed 10007175 02 System Management FRU LEDs Type Byte Data Field continued 4 LED Function 00h LED off override 01h FAh LED blinking override FBh Lamp Test state Turn on LED specified in byte 3 for the duration specified in byte 5 then return to the highest priority state FCh LED state restored to Local Control state FDh FEh Reserved FFh LED on override 5 On Duration LED on time is measured in tens of milliseconds Lamp Test time in hundreds of milliseconds if byte 4 FBh time value must be less than 128 Other values when Byte 4 FBh are reserved Otherwise this field is ignored and shall be set to Oh 6 Color When Illuminated sets the override color when LED Function is 01h FAh and FFh This byte sets the Local Control color when LED Function is FCh This byte may be ignored during Lamp Test or may be used to control the color during the lamp test when LED Function is FBh Bits 7 4 Reserved set to 0 Bits 3 0 Oh Reserved 1h Use
320. t variables are used for board configuration and identification by the monitor The environment parameter commands deal with the reading and writing of these parameters Refer to Environment Variables on page 14 28 for a list of monitor environ ment variables Redundant environment parameters allow you to store a backup copy of environment parameters should they ever become corrupt The redundant environment parameters are only used if the main parameters are corrupt To save environment variables Use moninit to save default environment variables to both primary and secondary environment parameters 2 Usesaveenv to save to the primary environment variables 3 Setthe next save to the secondary image For example 4000 User s Manual Primary Env Variables OxEOF6 0000 Secondary Env Variables if installed OxE1F6 0000 10007175 02 Monitor Test Commands Definition Definition Definition Definition Definition printenv The printenv command displays all of the environment variables and their current values to the display Print the values of all environment variables printenv Print the values of all environment variable exact match name printenv name saveenv The saveenv command writes the environment variables to non volatile memory Saveenv setenv The setenv command adds new environment variables sets the values of existing environ ment variab
321. tchdog timer support by implementing the Hang IPMC command which simulates firmware hanging by entering an endless loop Table 9 20 Hang IPMC Command Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID MS Byte first 0 00400 16394 Pigeon Point Systems Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID MS Byte first 0 00400 16394 Pigeon Point Systems 10007175 02 KAT4000 User s Manual System Management vendor Commands Table 9 21 E KAT4000 User s Manual Bused Resource Control Command To send a Bused Resource Control command to the shelf manager the payload uses the Bused Resource Control command of the SIPL Bused Resource Control Command Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID MS Byte first 0 00400 16394 Pigeon Point Systems 4 Command Types for Shelf Manager to Board 0 Query if board has control of the bus 1 Release requests a board to release control of the bus 2 Force board to release control of bus immediately 3 Bus Free informs board that the bus is available Command Types for Board to Shelf Manager 0 Request to seize control of the bus 1 Relinquish control of the bus Shelf Manager can reassign control of bus 2 Notify Shelf Manager that control of the bussed resource has been transferred to this board from another authorized board 5 Bused Resource ID 0 Metallic Test Bus pair 1 1 Metallic Test Bus pair
322. te 4 FBh time value must be less than 128 Other values when Byte 4 FBh are reserved Otherwise this field is ignored and shall be set to Oh 9 38 KAT4000 User s Manual 10007175 02 System Management Entities and Entity Associations DataField continued 6 Local Control Color Bits 7 4 Reserved set to 0 Bits 3 0 Oh Reserved 1hBlue 2h Red 3h Green 4h Amber 5h Orange 6h White 7h Fh Reserved Lamp Test is in effect LED override state is off LED override state is blinking Off duration is specified by this byte on duration specified by byte 8 in tens of milliseconds FBh FEh Reserved FFh LED override state is on Override State On Duration is required if either override state or Lamp Test is in effect in tens of milliseconds 29 Override State Color Bits 7 4 Reserved set to 0 Bits 3 0 Oh Reserved 1h Blue 2h Red 3h Green 4h Amber 5h Orange 6hWhite 7h Fh Reserved 10 Lamp Test Duration is optional if Lamp Test is not in effect hundreds of milliseconds ENTITIES AND ENTITY ASSOCIATIONS The AdvancedTCA specification see PICMG Engineering Change Notice 3 0 listed in Table 1 3 uses Entity IDs and Instances to describe physical components associated with FRUs Device relative Entities are unique to a specific IPMC and are referenced as follows in the specification r ipmb lun Entity ID gt lt En
323. tenv 14 21 14 9 Test 14 21 14 9 MAGS 14 21 PEERS 14 9 slve 14 21 DOO 14 10 em 14 22 bootvx 14 10 Other Commands 14 22 falta o 14 10 14 22 14 11 base nbi eee 14 22 tftpboot oos en 14 11 14 22 File Load Commands 14 12 coninfo 14 22 14 12 14 22 10845 14 12 Ej 14 22 Memory Commands 14 12 OCHO ones e php Rede seine 14 23 14 13 14 23 RR RE AUR 14 13 14 23 TING 14 13 14 23 ING 14 13 iminfo 14 23 ER ERE 14 14 s 14 23 RED EE ES 14 14 pop 14 24 Dn ace Mcr 14 14 14 24 Flash Commands 14 15 14 24 14 15 ES 14 24 5 M 14 15 PHY cn oan ted eee
324. the IEEE 802 3 standard ETHERNET ADDRESS FOR THE KAT4000 The Ethernet address for your board is a unique identifier on a network and must not be altered The address consists of 48 bits Medium Access Control MAC 47 0 divided into two equal parts The upper 24 bits define a unique identifier that has been assigned to Arte syn Communication Products by IEEE The lower 24 bits are defined by Artesyn for identifi cation of each of our products The Ethernet address for the KAT4000 is a binary number referenced as 12 hexadecimal digits separated into pairs with each pair representing eight bits The address assigned to the KAT4000 has the following form 00 80 F9 xx yy zz 00 80 F9 is Artesyn s identifier The last three bytes of the Ethernet address comprise the data for the Ethernet addresses in non volatile memory NVRAM The KAT4000 has been assigned the Ethernet address range 00 80 F9 92 00 00 to 00 80 F9 95 FF FF The format is shown in Table 4 4 10007175 02 KAT4000 User s Manual Common Switch Region Ethernet Address for the GbE Fat Pipe Table 4 4 Ethernet Port Address Numbering 4000 User s Manual Ethernet Identifier Offset MAC Description Hex Byte 5 15 0 LSB of serial number 1000 Byte4 MSB of serial number 1000 Byte3 23 16 Port 4 eTSEC4 95 Port 3 eTSEC3 94 Port 2 eTSEC2 93 Port 1 eTSEC1 92 Byte 2 47 24 Assigned to Artesyn by IEEE F9 Byte 1 80 Byte 0 00
325. the KAT4000 and the E keying def inition that corresponds to each interface The IPMC supports E keying for the KAT4000 per the PICMG 3 0 Revision 2 0 3 1 Revision 1 0 and specifications The e keying information for the blade is stored in the Board Point to Point Connectivity Record and Carrier Connectivity Record located in the MultiRecord Area of the FRU Inventory Information see page 9 44 The Board Point to Point Connectivity Record and Carrier Connectivity Record each contain a Link Descrip tor list where each Link Descriptor details one type of point to point protocol supported by the referenced channels Base Point to Point Connectivity The KAT4000 supports one 10 100 1000BASE T port on Base Interface Channels 0 and 1 and also four 10 100 1000BASE BX ports on the Update Interface Channels Depending on the configuration the KAT4000 can support one of the following on Fabric Interface Chan nels A and B One two orfour 1000BASE BX ports GbE Fat Pipe Module Configurations sRIO x4 ports sRIO Fat Pipe Switch Module Configurations e 10 GbE ports 10 GbE 1 GbE or 10 GbE 10 GbE Fat Pipe Switch Module Configurations Table 9 42 shows the Point to Point Connectivity Record Link Descriptors for the KAT4000 with a GbE Fat Pipe Switch Module Table 9 42 Link Descriptors Field Value Description Link Designator 000100000000b Port 0 Enabled Base Interface Channel 1 Link Type 01h PICMG 3 0 Base
326. the following values 0 The flash memory of the master H8S 1 The flash memory of the slave H8S 2 Checksum Response Data 1 Completion Code Firmware Upgrade Write Command The Firmware Upgrade Write command programs a portion of a new firmware image onto the IPMC The Boot Loader internally gathers data transferred to it via Firmware Upgrade Write requests and programs it to flash when the Boot Loader has accumulated an entire flash page This command is supported only by the Boot Loader If the IPMC firmware receives this command it sends a reply with the 0xC1 Invalid Command completion code 10007175 02 KAT4000 User s Manual System Management Firmware Upgrade Table 9 47 Firmware Upgrade Write Command Type Byte Data Field Request Data 1 Specifies the target device that is to be programmed with the data provided in the request body The offset of the location at which the data is to be programmed to the target devices is a 3 byte value supplied in little endian format 2 4 Offset LSB MSB The offset of the location at which the data is to be programmed to the target devices is a 3 byte value supplied in little endian format 5 N Data 1 N Data is required to be transferred sequentially because the IPMC firmware does not support the read modify write operations N 1 Checksum Response 1 Completion Code Firmware Upgrade Complete Command The Firmware Upgrade Complete command completes the programming of the IP
327. tion A Caution A The Emerson KAT4000 meets the requirements set forth by the Federal Communications Commission FCC in Title 47 of the Code of Federal Regulations The following information is provided as required by this agency This device complies with part 15 of the FCC Rules Operation is subject to the following two conditions 1 This device may not cause harmful interference and 2 this device must accept any interference received including interference that may cause undesired operation FCC RULES AND REGULATIONS PART 15 This equipment has been tested and found to comply with the limits for a Class B digital device pursuant to part 15 of the FCC Rules These limits are designed to provide reason able protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communica tions However there is no guarantee that interference will not occur in a particular installa tion If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one or more of the following measures Reorient or relocate the receiving antenna Increase the separation between the equipment and receiver Connectthe eq
328. tity Instance 60 gt Using this terminology a KAT4000 CPU and no PCle configuration installed in Logical Slot 1 IPMB 82 has the description in Fig 9 4 10007175 02 KAT4000 User s Manual 9 39 System Management sensors and Sensor Data Records Figure 9 4 Table 9 39 Sensor Name Hot Swap BlHotSwap KAT4000 User s Manual IPMB Entity Structure FRU 0 r 82 0 AO 0 PICMG Front Board FRU 1 r 82 FRU2 r 82 FRU 3 r 82 FRU 4 r 82 Hot Swaps sensor Type FO Physicals sensor Type F1 alnflow Temps sensor 01 Outflow Temps sensor 01 aF W Progressa sensor Type OF 03 0 Processor Watchdogs sensor Type 23 Volts sensor 02 0 Power Supply 48 Volta sensor 02 48 sensor Type 03 48 Feed A Volta sensor Type 02 48 Feed Volta sensor Type 02 3 3V Mgmta sensor 02 12V Volta sensor Type 02 12V Curra sensor Type 03 14 0 Power Module an 3 3Va Sensor 02 an 2 5 sensor 02 1 8 sensor 02 1 2 sensor 02 1 0Va sensor 02 C1 5 PICMG AMC Module 1B1 Hot Swaps sensor F0 1 12 sensor 03 1 12 Volts sensor Type 02 C1 6 PICMG AMC Module 2 Hot Swaps sensor F0 2
329. tories Universal Serial Bus X 10 Gigabit Attachment Unit Interface 10007175 02 Appendix NO CPU KAT4000 The following block diagram provides a functional overview for the no CPU KAT4000 board configuration This configuration includes 256 Kb of SRAM memory used by the internal 8051 microcontroller on the VSC7376 Ethernet core switch for run time code storage This configuration omits SDRAM and NOR and NAND flash Also this configuration may not sup port some IPMC payload features Figure 1 No CPU KAT4000 System Block Diagram AMC x4 Single Width Half Full Extended Height AMC 0 Common Extended PEX8524 Fat Pipes PCI Express Switch Optional PCle or GbE on port 1 ERDE VSC7376 IPMB L 12 Ethernet SERDES ________ Layer 2 Optional Q p UN SS 55 29 38 ES es To Zone 3 2 2 SERDES IPMB Base High Speed High Speed Clock RTM I O Fabric A Fabric B Optional P10 23 20 Zone3 10007175 02 KAT4000 User s Manual m Appendix A Ethernet Switch Configuration Note Note n KAT4000 User s Manual ETHERNET SWITCH CONFIGURATION If a processor is not used on the KAT4000 the Ethernet core switch and GbE fat pipe switch module optional are managed by an 8051 microcontroller internal to each switch Cus tom configuration of the switch is possible through one of two user interfaces on each switch
330. ts or circuits When the board is not in an enclosure store it in a staticshielding bag To ground yourself wear a grounding wriststrap Simply placing the board on top of a staticshielding bag does not provide any protection place it on a grounded dissipative mat Do not place the board on metal or other conductive surfaces KAT4000 CIRCUIT BOARD The KAT4000 is a 16 layer 8U form factor circuit board that conforms to the PICMG 3 0 Rev 2 and AMC 0 Rev 2 mechanical specifications with the exception of a couple non con formances See the KAT4000 Errata for details It has the following physical dimensions Circuit Board Dimensions Component Component Height Width Depth Thickness Height top side bottom side 12 687 in 11 024 in 0 075 in 0 84 in 0 144 in 322 25 mm 280 0 mm 1 9 mm 21 33 mm 3 65 mm The following figures show the component maps for the KAT4000 circuit board Figures are also provided for the front panel LEDs fuse jumper and JTAG locations 10007175 02 KAT4000 User s Manual E Setup KAT4000 Circuit Board Figure 2 1 Component Map Top Rev 02
331. ture prog 9 ees 14 18 KAT4000 User s Manual 10007175 02 continued overview 9 1 P PCI device and vendorID 3 4 revision 3 4 sigrials sete s 8 2 PCI Express switch EEPROM controller 4 9 4 7 4 9 1 3 reference 1 14 PLD 1 2 power supply requirements 2 16 product code Ethernet 4 5 re eene 2 15 2 18 programmable logic device PLD 5 6 5 16 7 1 R real time clock block diagram 11 1 operation 11 1 1 3 reference 1 14 register 11 2 redundant boot bank 6 2 references manuals and data books 1 12 registers 10 GbE 1 GbE fat pipe switch module 5 16to 5 20 10 GbE 10 GbE fat pipe switch module 5 16to 5 20 BDRR scere de 7 11 bootandreset 7 8to 7 12 ug m 7 17 clock synchronizer 7 13 to 7 19 configuration 7 4 to 7 5 ceo sepe 7 14 Ra 7 13 jv m 7 18 7 15 ISR 7 6 7 5 5 7 7 miscellaneous 7 5to 7 8 PIDR ber 7 2 qc 7 4
332. uipment into an outlet on a circuit different from that to which the receiver is connected Consult the dealer or an experienced radio TV technician for help Making changes or modifications to the KAT4000 hardware without the explicit consent of Emerson Network Power could invalidate the user s authority to operate this equipment EMC COMPLIANCE The electromagnetic compatibility EMC tests used a KAT4000 model that includes a front panel assembly from Emerson Network Power For applications where the KAT4000 is provided without a front panel or where the front panel has been removed your system chassis enclosure must provide the required electromagnetic interference EMI shielding to maintain CE compliance 10007175 02 KAT4000 User s Manual Regulatory Agency Warnings amp Notices continued EC Declaration of Conformity According to EN 45014 1998 Manufacturer s Name Emerson Network Power Embedded Computing Manufacturer s Address 8310 Excelsior Drive Madison Wisconsin 53717 Declares that the following product in accordance with the requirements of 89 336 EEC Directive and 99 5 EC RTTE Directive and their amending directives Product ATCA Carrier Model Name Number KAT4000 10007505 xx has been designed and manufactured to the following specifications EN55022 1998 Information Technology Equipment Radio disturbance characteristics Limits and methods of measurement EN55024 1998 Information Tech
333. update to the Clock registers is delayed for 250 ms to allow the read to be completed before the update occurs This delay does not alter the actual clock time The eight byte clock register sets the clock and reads the date and time from the clock as summarized in Table 11 1 RIC Register Map Address Data Function Range 07 D6 D5 D3 D2 DO BCD Format 00 ST 10 Seconds Seconds Seconds 00 59 01 X 10 Minutes Minutes Minutes 00 59 CEB CB 10 Hours Hours Century 0 1 02 Hours 00 23 03 X x X x Day Day 01 07 04 X X 10 Date 22 Date __ 01 31 05 X X X 10M Month Month 01 12 06 10 Years Years Years 00 99 07 OUT FT 5 Calibration Control Stop bit 1 Stopsthe oscillator O Restarts the oscillator within one second Century Enable Bit 1 Causes CB to toggle either from 0 to 1 or from 1 to 0 at the turn of the century 0 CBwill nottoggle Century Bit 10007175 02 Real Time Clock clock Operation Day Date OUT Calibration Day of the week Day of the month Output level 1 Default at initial power up 0 FT OUT pin 7 driven low when FT is also zero Frequency Test bit 1 Whenoscillator is running at 32 768 Hz the FT OUT pin will toggle at 512 Hz 0 TheFT OUT pin is an output driver default at initial power up Sign bit 1 Positive calibration 0 Negative calibration Calibration bits calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 sta
334. us Registers 7 5 Get Debug Level Command 9 16 LED Control Register LEDR 7 5 Set Debug Level Command 9 17 Jumper Settings Register JSR 7 6 RTM State Register RGSR 7 6 RTM GPIO Control Register RGCR 7 7 MISC Control Register MISC 7 7 Get Hardware Address Command 9 17 Set Hardware Address Command 9 18 Get Handle Switch Command 9 18 Set Handle Switch Command 9 19 Scratch Register 1 SCR1 7 8 Get Payload Communication Time Out Boot and Reset Registers 7 8 9 19 Reset Event Register RER 7 8 Set Payload Communication Time Out Reset Command Register 1 RCR1 7 9 9 20 Reset Command Register 2 RCR2 7 10 Boot Device Redirection Register Enable Payload Control Command9 20 Disable Payload Control Command BDRR 43 oeste 7 11 9 20 Clock Synchronizer Registers 7 13 Reset Command 9 21 Clock Synchronizer Control Registers 1 Hang Command 9 21 3 5 1 5 7 13 Bused Resource Control Command 9 22 m KAT4000 User s Manual 10007175 02 Contents continued Bused Resource Status Command 9 22 Firmware Upgrade Termination 9 51 Graceful Reset Command 9 23 Firmware Upgrade Sequence 9 51 Diagnostic Interrupt Results 9 24 Get Payload Shutdown Time Out
335. ve Going Threshold Hyst 02 Value _ Negative Going 02 Threshold Hyst Value OEM 00 ID String Length Code cf Table B 30 48V Source B Volt SDR Description KAT4000 Records Value Parameter Status Record ID 001c SDR Version 51 Record Type 01 Full Sensor Record _ Record Length KAT4000 User s Manual 10007175 02 Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Sensor Owner ID 00 Sensor Owner LUN 00 Sensor Number 00 Entity ID 0a Entity Instance 60 Sensor Initialization 7f Init Scanning lnit Sensor Type Init Hysteresis B Init Thresholds Init Events Sensor Scanning enabled Event Generation enabled Sensor Capabilities 69 Ignore Sensor no Auto Re Arm enabled Sensor Hysteresis hysteresis is settable readable Sensor Threshold Access threshold is settable readable Event Message Control global disable only Sensor Type 02 Voltage Event Reading Type Code 10 Threshold Assertion Event Mask 4801 Lower Non Recoverable Threshold comparison returned Upper Non Recoverable Going High supported Lower Non Critical Going Low supported Deassertion Event Mask 4801 Lower Non Recoverable Threshold comparison returned Upper Non Recoverable Going High supported Lower Non Critical Going Low supp
336. ve any affect on operations Default is 0x00 Scratch Register SCR at 0x01 7 6 5 4 3 2 1 0 SCR7 SCR6 SCR5 SCRA SCR3 SCR2 SCR1 SCRO Scratch 12C Register The register controls operations on the 2 bus Default is OxOf 12 Register I2C at 0x02 7 6 5 4 3 2 1 0 reserved SDAS SCLS SDAC SCLC ADDO Reserved SDA State This read only bit gives the current state of the I C SDA line SCL State This read only bit gives the current state of the 2 SCL line SDA Control 0 Drives logic 0 on the data line 1 Tristates data line pulled high externally 10007175 02 KAT4000 User s Manual 5 17 Fat Pipe Switch Module 10 GbE 1 GbE Fat Pipe Switch Module SCLC ADD1 ADDO Register 5 12 Register 5 13 WP JTAG EN RESET EI KAT4000 User s Manual SCL Control 0 Drives logic 0 on the 12 clock line 1 Tristates clock line pulled high externally 12 Address Values in these bits drive address to the Ethernet switch Reserved Register 1 This read only register is reserved for future use Reserved Register 1 at 0x03 7 6 5 4 3 2 1 0 reserved Reserved Switch Reset Register The Switch Reset register allows for software control of reset to the BCM56580 Ethernet switch Default is 0x00 Switch Reset Register SRST at 0x04 7 6 5 4 3 2 1 0 reserved EE WP EN RESET Rese
337. vell Doc No MV S100649 00 Rev G February 10 2006 http www marvell com BCM5241 10 100Base TX FX Transceiver Preliminary Data Sheet Broadcom Corporation Document 5241 DS03 R 6 21 05 http www broadcom com Intel StrataFlash Embedded Memory P30 Data Sheet Intel Order Number 306666 Rev 002 August 2005 http www intel com AMD AM291V040B 4 Megabit 512 K x 8 Bit CMOS 3 0 Volt only Uniform Sector 32 Pin Flash Memory Data Sheet Advanced Micro Devices Inc Publication 421354 Rev E June 11 2004 http www amd com mDOC H3 Embedded Flash Drive EFD featuring Embedded TrueFFS Flash Management Software Preliminary Data Sheet M Systems Flash Disk Pioneers Ltd 92 DS 1205 10 Rev 0 2 June 2006 http www m systems com mobile LTC94211 Hot Swap Controller with Multifunction Current Control Linear Technology Corporation LT TP 0702 2K 4211f LTC94300A 1 LTC 4300A 2 Hot Swappable 2 Wire Bus Buffers Linear Technology Corporation LT TP 0203 2K sn4300a http www linear com Hot Swap Specification PICMG 2 1 Rev 2 0 January 17 2001 http www picmg org 10007175 02 KAT4000 User s Manual 1 13 Overview Additional Information Device Interface IPMI IPMB JTAG PCI Express Real Time Clock SDRAM SO DIMM Module Serial Interface Synchronization Clock Interface E KAT4000 User s Manual Document Intelligent Platform Management Interface Specification v2 0
338. version command displays the monitor s current version number version vlan The vlan command creates one or more new VLANs using vid as the VLAN identification VID value and deletes one or more existing VLANs whose VLAN ID matches the VLAN ID value vid These variables are set using a comma separated list of port names This com mand sets an untagged port based VLAN and the VLAN table entry with the port s default VID In this configuration each port is assigned to one VLAN vlan add core fp vidl portlistl vid2 portlist2 vlan delete core fp vidl vid2 vlan show core fp To create VLAN 1 on the core switch vlan add core 1 14 15 To create VLANs 2 3 on the fat pipe switch vlan add fp 2 18 17 0 3 19 22 6 3 21 17 1 4 20 23 10 o delete VLAN 1 on the core switch o vlan delete core 1 delete VLANs 2 3 on the fat pipe switch o lt an delete fp 2 3 o delete all VLANs the fat pipe switch vlan delete fp all 10007175 02 KAT4000 User s Manual 14 27 Monitor Environment Variables show VLANs in use on the fat pipe switch vlan show fp ENVIRONMENT VARIABLES Press the s key on the keyboard during reset to force the default monitor environment vari ables to be loaded during hardware initialization but before diagnostic testing Table 14 6 lists the monitor s standard environment variables Table 14 6 Standard Environment Variables Default Variable Va
339. vice programmable LED controlled by the IPMI controller is either red North America or amber Europe When lit this LED indicates the KAT4000 is in a failed state The green LED is user defined but frequently is used as an In Service indicator When used as an In Service indicator a lit LED indicates that the KAT4000 is functioning properly The amber LED is user defined CR2003 CR2002 CR2000 10007175 02 KAT4000 User s Manual 9 33 System Management FRU LEDs Get FRU LED Properties Command This command allows software to determine which LEDs are under IPMC control Table 9 35 Get FRU LED Properties Command Type Byte Data Field Request Data 1 PICMG Identifier indicates that this is a PICMG defined group extension command Use value 00h 2 FRU Device ID MEM ResponseData 1 Completion Code 2 PICMG Identifier indicates that this is a PICMG defined group extension command Use value 00h 3 General Status LED Properties indicates the FRU s ability to control the four general status LEDs When a bit is set the FRU can control the associated LED Bits 7 4 Reserved set to 0 Bit 3 LED3 Bit 2 LED2 Bit 1 LED1 Bit 0 Blue LED 4 Application Specific LED Count is the number of application specific LEDs under IPMC control 00h FBh Number of application specific LEDs under control If none are present this field is FCh FFh Reserved Get LED Color Capabilities Comm
340. w the maximum frame size in bytes including FCS for frames received on the port Tagged frames are allowed to be 4 bytes longer than the maximum frame size Use the reset option to return to the default setting lt portlist gt Port list Default All ports lt framesize gt reset Maximum frame size or reset to 1518 bytes Default Show maximum frame size Syntax Port Statistics lt portlist gt clear Description Show or clear statistics for the port portlist Port list Default All ports clear Clear port statistics Default Show statistics Port Excessive Collisions Drop MAC Configuration MAC Add E KAT4000 User s Manual Syntax Port Excessive Collisions Drop enable disable Description Enable or disable drop of frames when excessive collisions occur in half duplex mode enable disable Enable disable frame drop Default Show excessive collisions drop mode MAC Commands Syntax MAC Configuration Description Show the permanently stored MAC table and the MAC aging timer Syntax 10007175 02 Appendix A serial Command Line Interface CLI MAC Delete MAC Lookup MAC Table MAC Flush MAC Age Time MAC Learning MAC Add lt macaddress gt lt portlist gt none lt vid gt Description Add a static MAC address table entry and VLAN ID on ports lt macaddress gt MAC address 12 digit hex string optionally separated with dashes or colons e g
341. witch module MTBFs were calculated using Method Case 3 Telcordia Issue 1 model at 30 C Product Certification The KAT4000 hardware has been tested to comply with various safety immunity and emissions requirements as specified by the Federal Communications Commission FCC Industry Canada IC Underwriters Laboratories Inc 9 UL and the European Union Direc tives CE mark The following table summarizes this compliance Regulatory Agency Compliance Type Specification Safety IEC60950 EN60950 Safety of Information Technology Equipment Western Europe UL60950 CSA C22 2 No 60950 Third Edition Safety of Information Technology Equipment including Electrical Business Equipment BI National AS NZS 60950 2000 Safety Standard for Australia and New Zealand Global IEC CB Scheme Report IEC 60950 all country deviations 10007175 02 Overview Additional Information Type Specification continued Environmental NEBS Telcordia GR 63 applies to an entire system Section 4 3 Equipment Handling Criteria Section 4 4 1 Earthquake Environment and Criteria Zone 4 Section 4 4 3 Office Vibration Environment and Criteria Section 4 4 4 Transportation Vibration Criteria EMC FCC Part 15 Class B Title 47 Code of Federal Regulations Radio Frequency Devices ICES 003 Class A Industry Canada Interference causing Equipment Standard for Digital Apparatus NEBS Telcordia GR 1089 level 3 Emissions
342. xception of bit 6 in the Timer Use byte the Timer Use Expi ration flags are cleared using the Set Watchdog Timer command They may also become cleared because of a loss of IPMC power firmware update or other cause of IPMC hard reset Bit 6 of the Timer Use byte is automatically cleared to Ob whenever the timer times out is stopped when the system is powered down enters a sleep state or is reset Table 9 33 Get Watchdog Timer Command Type Byte Data Field Request Data 10007175 02 KAT4000 User s Manual 9 31 System Management IPMC Watchdog Timer Commands Type Response Data 9 32 KAT4000 User s Manual DataField continued Completion Code Timer Use 7 1b don t log 6 1b timer is started running Ob timer is stopped 5 3 reserved 2 0 timer use logged on expiration if don t log bit 0 000b reserved 001b Monitor FRB 2 010b Monitor POST 011b OS Load 100b SMS OS 101b OEM 110b 111b reserved Timer Actions 7 reserved 6 4 pretime out interrupt 000b none 001b SMI 010b NMI Diagnostic Interrupt 011b Messaging Interrupt this would be the same interrupt as allocated to the messaging interface 100b 111b reserved 3 reserved 2 0 time out action 000b no action 001b Hard Reset 010b Power Down 011b Power Cycle 100b 111b reserved Pretime out interval in seconds 1 based Timer Use Expiration flags 1b timer expired while associated use was selected 7 reserved
343. y The list is an ASCII string of commands separated bythe character and terminated with the charac ters script address is the starting location of the script A script is limited to 1000 characters Script script address showmac The showmac command displays the Processor MAC addresses assigned to each Ethernet port showmac showpci The showpci command scans the PCle bus and lists the base address of the devices The default PCI interface is PCI 1 showpci sleep The sleep command executes a delay of N seconds Delay execution for N seconds N is a decimal value sleep N 10007175 02 Monitor Other Commands Definition Example Definition Definition Example switch The switch reg command reads or writes to the Ethernet core switch or fat pipe Ethernet switch registers The values changed via this command are not persistent and clear after a hard or soft reset Option values are as follows switch core or fp port 0 25 block 1 7 and sub block 0 15 R reads the register contents at the address specified W writes the address value to the register address specified Switch reg switch port op block sub block op R W address value The following is an example of a read of register address Ox1a Switch reg core 0 Oxla The following is an example of a write to register address where 0 is the data to write Switch reg core 0 Oxla 0 version The
344. y Source 3 NAND Flash 32 KB Clock Sync Primary Source 2 FC00 0000 FC40 0054 Clock Sync Primary Source 1 Reserved FC40 0050 200 0000 FC40 004C i NOR Flash 32 MB FC40 0048 Clock Sync Control Register 3 000 0000 ECAG 0644 Clock Sync Control Register 2 2040 6040 Clock Sync Control Register 1 Switch sRIO Fat Pipe Module RTM GPIO Control Regist if installed 1 GB FC40 003C END A m sr ate Register FC40 0038 PCI Express Switch Rien Xpress 00 evice Redirection Register if installed 512 MB FC49 0030 Scratch Register 1 8000 0000 FC40 002C i 40 0098 Reset Command Register 2 Reset Command Register 1 Reserved Reset Event Register j LED Control Register J Settings Registe umper ettini Ister 3FFF FFFF FC40 0018 p g g Reserved SDRAM FC40 0014 Eene 1FFEFFFF DERE DDR2 Can DOO Hardware Config Register 0 DDR2 1 GB PLL Configuration Register 512 MB PLD Version Register 0000 0000 FC40 0008 T 5 FC40 0004 Hardware Version Register 0000 Product ID Register H KAT4000 User s Manual 10007175 02 Overview Physical Memory Table 1 1 summarizes the physical addresses for the KAT4000 and provides references to more detailed information Table 1 1 KAT4000 Address Summary Physical Access Address hex Mode Description See Page FFF0 0000 R W Boot Area 1 MB FF80 0000 Reserved FF70
345. ype Init Hysteresis Init Thresholds Init Events Sensor Scanning enabled Event Generation enabled Sensor Capabilities 69 Ignore Sensor no Auto Re arm enabled Sensor Hysteresis hysteresis is settable readable Sensor Threshold Access threshold is settable readable Event Message Control global disable only Sensor Type 02 Voltage Event Reading Type Code 01 Threshold Assertion Event Mask 4000 Lower Non Recoverable Threshold comparison returned Deassertion Event Mask 4000 Lower Non Recoverable Threshold 10007175 02 comparison returned KAT4000 User s Manual B 17 Appendix B sensor Data Records KAT4000 Records Value Parameter Status continued Discrete Reading Mask 3f3f Upper Non Recoverable Threshold settable Upper Critical Threshold settable Upper Non Critical Threshold settable Lower Non Recoverable Threshold _ settable Lower Critical Threshold settable Lower Non Critical Threshold settable _ Upper Non Recoverable Threshold readable Upper Critical Threshold readable Upper Non Critical Threshold readable Lower Non Recoverable Threshold readable Lower Critical Threshold readable Lower Non Critical Threshold readable Sensor Units 1 00 Analog Data Format unsigned Rate Unit none Modifier Unit none Percentage no Sensor Units 2 Base Unit 04 Volts
346. ypically not grow beyond 512 KB therefore the upper 1 MB of SDRAM is reserved for monitor use Note The monitor has the ability to preserve not overwrite areas of memory defined by the pram environment variable Caution Any writes to these areas can cause unpredictable operation of the monitor A MONITOR RECOVERY AND UPDATES This section describes how to recover and or update the monitor given one or more of the following conditions e fthereis no console output the monitor may be corrupted and need recovering see the Recovering the Monitor section e Ifthe monitor still functions but is not operating properly then you may need to reset the environment variables see the Resetting Environment Variables section e f you are having Ethernet problems in the monitor you may need to set the serial number since the MAC address is calculated from the serial number variable 4000 User s Manual 10007175 02 Monitor Monitor Recovery and Updates Table 14 3 Note Recovering the Monitor Make sure that a monitor ROM device is installed in the PLCC socket on the KAT4000 Ensure there is a jumper on JP7 across pins 1 and 2 Issue the following command where serial number is the board s serial number at the monitor prompt KAT4000 1 0 gt moninit serial number moninit will also reset environment variables to the default state To boot from soldered flash power down the board and remove th

Emerson KAT4000 Network Hardware User Manual

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