Eiki AH-55701 Projector User Manual
Contents
1. Oscillator le INT ROM STACK 3 Timming Control 1 1 STACKS STACK 5 Interrupt Instruction STACK 6 ENTCC Control Register RI TCC STACK 7 Sleep gt Instruction ALU S Decoder amp Wake Up t Control R3 ACC Fig 2 The Functional Block Diagram of EM78P458 459 IOC6 R6 PPPPPPPP PPPPPPPP 55555555 66666666 01234567 01234567 4 1 Operational Registers 1 RO Indirect Addressing Register RO is not a physically implemented register Its major function is to perform as an indirect addressing pointer Any instruction using RO as a pointer actually accesses data pointed by the RAM Select Register R4 2 R1 Time Clock Counter Increased by an external signal edge through the TCC pin or by the instruction cycle clock The signals to increase the counter are decided by Bit 4 and Bit 5 of the CONT register Writable and readable as any other registers 3 R2 Program Counter amp Stack R2 and hardware stacks are 12 bit wide The structure is depicted in Fig 4 Generates 4Kx13 bits on chip ROM addresses to the relative programming instruction codes One program page is 1024 words long This specification is subject to change without prior notice 8 07 01 2003 V1 3 EM78P458 459 OTP ROM The contents of R2 are set to all 0 s upon a RESET condition JMP instru2. ABC IS gt Fsco ADCI 2 op o x _OPL_ 7 A A ae Internal E RC 4 3 2 s 4 3 2 1 o 2 1 0 1 0 3 7 6 5 4 3 2 1 o 4 3 AD CMPCON A A 4 ADCON AD CMPCON RF ADDATA ADCON CMPCO N AD CMPCO N GCON S DATA BUS i Fig 12 The Functional Block Diagram of Analog to Digital Conversion This specification is subject to change without prior notice 31 07 01 2003 V1 3 T7 EM78P458 459 ADLAN OTP ROM 1 ADC Control Register ADCON R9 AD CMP CON IOCA0 GCON IOC90 1 1 ADCON R9 The ADCON register controls the operation of the A D conversion and decides which pin should be currently active BIT 7 6 5 4 3 2 1 0 SYMBOL IOCS ADRUN ADPD ADIS2 ADIS1 ADISO vae 9 9 o 9 9 9 9 9 Init Value Initial value at power on reset ADRUN bit 4 ADC starts to RUN 1 an A D conversion is started This bit can be set by software 0 7 reset on completion of the conversion This bit can not be reset in software ADPD bit 3 ADC Power down Mode 1 ADC is operating 0 switch off the resistor reference to save power even when the CPU is operating ADIS2 ADISO bit 2 0 Analog Input Select 000 ANO 001 AN1 010 AN2 011 AN3 100 AN4 101 AN5 110 AN6 111 ANT Change occurs only when the ADIF bit and the ADRUN bit are both LOW 1 2 AD CMP CON IOCAO The AD CMP CON register defines the pins of Port 6 as analog inputs or as digital I O
3. Items Temperature under bias torage temperature nput voltage This specification is subject to change without prior notice 56 07 01 2003 V1 3 T7 EM78P458 459 ADLAN OTP ROM 6 ELECTRICAL CHARACTERISTICS 6 1 DC Electrical Characteristic Ta 0 C 70 C 2o VSS 0V Symbol Parameter Condition Min Max Unit C eN rwootewnocears 20 LL 8 Me Fxt DC 20 MHz IL InputLeakage Current for input pins VIN VDD VSS sf m ViHi Inputhigh Voltage vDD 5V___ Pots56 20 v VILT InputlowVoltageVDD 5V Pots5 6 VIHT1 Input High Threshold Voltage VDD 5V RESET TCC 20 J v VILT input Low Threshold Voltage VDD 5V Reset Tece fos VIHX1 ClockInputHigh Voltage DD 5bV osci 25 J VILXi Clock Input Low Voltage VDD 5V os o v VIH2 Input High Voltage VDD 3V__ Ports 5 6 15 J VviL2 InputLowVoltageVDD 3V Pors56 os V VIHT2 Input High Threshold Voltage DD 3V RESET TCC 15 J v VILT2 Input Low Threshold Voltage DD 3V _ RESET TCC 04 V VIHX2 Clock Input High Voltage DD 3 V osci 15 J Jv hel nae a ee EE re eme Output High Voltage VOH1 Ports 5 6 IOH 12 0 mA Output Low Voltage P51 P57 P60 P63 VOL1 P66 P67 IOL 12 0 mA 0 4 Output Low Voltage P64 P65 mee uisa T sor lane Poa All input and I O pin
4. frequency can be affected easily by noise humidity and leakage The smaller the Rext in the RC oscillator the faster its frequency will be On the contrary for very low Rext values for instance 1 KO the oscillator becomes unstable because the NMOS cannot discharge the current of the capacitance correctly Based on the above reasons it must be kept in mind that all supply voltage the operation temperature the components of the RC oscillator the package types and the way the PCB is layout have certain effect on the system frequency Vcc Rext OSCI Cext EM78P458 EM78P459 Fig 22 Circuit for External RC Oscillator Mode Table 14 RC Oscillator Frequencies Average Fosc 5V 25 C Average Fosc 3V 25 C 3 57 MHz 2 94 MHz 20 pF 2 63MHz 1 92 MHz 1 30 MHz 1 22 MHz 100k 150 KHz 153 KHz This specification is subject to change without prior notice 48 07 01 2003 V1 3 T7 EM78P458 459 ADLAN OTP ROM 1 43 MHz 1 35 MHz 100 pF 980 KHZ 877 KHz 520 KHz 465 KHz 100k 57 KHz 54 KHz 340 KHz 320 KHz 175 KHz 170 KHz 100k 19 KHz 19 KHz Note 1 Measured on DIP packages 510 KHz 470 KHz 300 pF 2 Design reference only 4 RC Oscillator Mode with Internal Capacitor If both precision and cost are taken into consideration EM78P257A B also offers a special oscillation mode It is equipped with an internal capacitor and an external resistor connected to Vcc The internal capacitor functions as tem
5. individually BIT 7 2 5 4 3 2 1 0 MEL VREFS COE IMS2 IMS1 IMSO CKR1 CKRO tvass o som poe 1 94 9 1 9 1 94 sinit Value Initial value at power on reset VREFS Bit 7 The input source of the Vref of the ADC This specification is subject to change without prior notice 32 07 01 2003 V1 3 T7 EM78P458 459 ADLAN OTP ROM 0 The Vref of the ADC is connected to Vdd default value and the P53 VREF pin carries out the function of P53 1 The Vref of the ADC is connected to P53 VREF CE Bit 6 Control bit used to enable comparator 0 Disable comparator 1 Enable comparator COE Bit 5 Set P57 as the output of the comparator 0 the comparator acts as an OP if CE 1 1 act as a comparator if CE 1 IMS2 1MSO Bit 4 Bit 2 ADC configuration definition bit CKR1 and CKRO Bit 1 and Bit 0 The conversion time select 00 Fosc 4 01 Fosc 16 10 Fsco 64 11 The oscillator clock source of ADC is from WDT ring oscillator frequency frequency 256 18ms 14 2Khz 1 3 GCON IOC90 As shown in Fig 12 OP1 and OP2 the gain amplifiers are located in the middle of the analog input pins ADC1 and ADC5 and the 8 1analog switch The GCON register controls the gains Table 7 Table 7 Shows the Gains and the Operating Range of ADC BIT 7 6 5 zs as 1 0 SYMBOL OP2E OP1E G22 G11 G10 vas o 9 0 0 0 9 9 0 Table 8 The Gains and the Operating Range of ADC G10 G12 G20 G22 Gain Ran
6. 72 EM78P458 459 LN m EM78P458 459 8 BIT MICRO CONTROLLER Version 1 3 ELAN MICROELECTRONICS CORP No 12 Innovation 1 RD Science Based Industrial Park Hsin Chu City Taiwan R O C TEL 03 5639977 FAX 03 5782037 SL 5630118 FAE T7 EM78P458 459 ADLAN OTP ROM a LLL LL LI Specification Revision History Version Content 1 0 Initial version 1 1 Modify ERC frequency 2003 03 06 1 2 Add AD amp OP spec 2003 05 07 1 3 Change Power on reset content 2003 07 01 Application Note AN 001 A D Pre amplifier AN 002 Calibration Offset on A D AN 003 Example of Microcomputer Digital Thermometer AN 004 Tips on how to apply EM78P458 AN 005 Tips on how to apply A D Converter AN 006 AD amp R4 AN 007 Enhancing Noise Immunity This specification is subject to change without prior notice 2 07 01 2003 V1 3 EM78P458 459 OTP ROM 1 GENERAL DESCRIPTION EM78P458 and EM78P459 are 8 bit microprocessors designed and developed with low power and high speed CMOS technology It is equipped with a 4K 13 bit Electrical One Time Programmable Read Only Memory OTP ROM With its OTP ROM feature it is able to offer a convenient way of developing and verifying user s programs Moreover user can take advantage of EMC Writer to easily program his development code This specification is subject to change without prior notice 3 07 01 2003 V1 3 EM78P458 459 OTP ROM 2 FEATU
7. Default value while power on reset NN General purpose l O pin P51 P57 23 2 pues Di Default value while power on reset 3 E General purpose I O pin E XT Default value while power on reset INT 14 Ff External interrupt pin triggered by falling edge d 4 Analog to Digital Converter ADCi ADCB SA 1 Defined by AD CMPCON IOCA0 2 4 pme 696 0 Pulse width modulation outputs PWM2 Defined by PWMCON 10C51 lt 6 7 MF External reference voltage for ADC Denes by AD CMPCON IOCAO lt 7 gt gt the Vin input pins of the comparators gt the Vin input pins of the comparators Pin CO is the output of the comparator Defined by AD CMPCON IOCAO 5 6 If it remains at logic low the device will be reset Wake up from sleep mode when pins status changes Voltage on RESET Vpp must not be over Vdd during normal mode Pull high is on if RESET is asserted Real time clock counter with Schmitt trigger input pin it must be tied to VDD or VSS if it is not in use ENTCC 5 t Enable TCC 0 Disable TCC MSS 6 7 jGround This specification is subject to change without prior notice 7 07 01 2003 V1 3 EM78P458 459 OTP ROM 4 FUNCTION DESCRIPTION Y WDT Timer PC STACKO WDT Prescalr qg _____ STACK 1 Time out STACK 2
8. Power on reset 2 RESET pin input low or 3 WDT time out if enabled The device is kept in a RESET condition for a period of approximately 18ms one oscillator start up timer period after the reset is detected Once the RESET occurs the following functions are performed The oscillator is running or will be started The Program Counter R2 is set to all 0 All I O port pins are configured as input mode high impedance state The Watchdog Timer and prescaler are cleared When power is switched on the upper 3 bits of R3 are cleared The bits of the CONT register are set to all 1 except for the Bit 6 INT flag The bits of the IOCBO register are set to all 1 The IOCCO register is cleared The bits of the IOCDO register are set to all 1 Bit 7 of the IOCEO register is set to 1 and Bit 6 is cleared Bits 0 6 of RF register and bits 0 6 of IOCFO register are cleared Executing the SLEP instruction will assert the sleep power down mode While entering sleep mode the WDT if enabled is cleared but keeps on running The controller can be awakened by This specification is subject to change without prior notice 26 07 01 2003 V1 3 EM78P458 459 OTP ROM 1 External reset input on RESET pin 2 WDT time out if enabled 3 Port 6 input status change if enabled 4 Comparator high The first two cases will cause the EM78P458 459 to reset The T and P
9. Stack 3 gog Stack 4 00 y Page 0 re 3FF Stack 6 400 Stack 7 01 1 y Page 1 7FF 800 10 gt Page 2 BFF coo 11 M Page 3 FFF Fig 3 Program Counter Organization This specification is subject to change without prior notice 9 07 01 2003 V1 3 T7 EM78P458 459 AALAN OTP ROM 4 R3 Status Register 7 6 5 4 3 2 1 0 CMPOUT PS1 PSO T P Z DC C Bit 7 CMPOUT the result of the comparator output Bit 6 PS1 5 PSO Page select bits PS0 PS1 are used to select a program memory page When executing a JMP CALL or other instructions which cause the program counter to be changed e g MOV R2 A PSO PS1 are loaded into the 11th and 12th bits of the program counter where it selects one of the available program memory pages Note that RET RETL RETI instruction does not change the PSO PS1 bits That is the return will always be to the page from the place where the subroutine was called regardless of the current setting of PSO PS1 bits Program memory page Address Page 0 000 3FF Page 1 400 7FF Te 1 o Page2 00BFF pot 1 J Page3 CO FFF Bit 4 T Time out bit Setto 1 by the SLEP and WDTC commands or during Power on and reset to 0 by WDT time out Bit 3 P Power down bit Set to 1 during power on or by a WDTC command and reset to 0 by a SLEP command Bit 2 Z Zero flag Set to 1 if the result of an arithmetic or logic
10. R1 Clear TCC and prescaler MOV A OBxxxx1110 Select WDT prescaler CONTW WDTC Clear WDT and prescaler MOV A OBOxxxxxxx Disable WDT IOW RE MOV R6 R6 Read Port 6 MOV A 90B00000x1x Enable Port 6 input change interrupt This specification is subject to change without prior notice 27 07 01 2003 V1 3 EM78P458 459 OTP ROM IOW RF ENI or DISI Enable or disable global interrupt SLEP Sleep NOP Similarly if the Comparator High Interrupt is used to wake up the EM78P458 459 as in Case c above the following instructions must be executed before SLEP MOV A 0Bxx000110 Select internal TCC clock CONTW CLR R1 Clear TCC and prescaler MOV A 90B x1 110 Select WDT prescaler CONTW WDTC Clear WDT and prescaler MOV A OBOxxxxxxx Disable WDT IOW RE MOV A 0B01xxxxxx Enable comparator high interrupt IOW RF ENI or DISI Enable or disable global interrupt SLEP Sleep NOP One problem user must be aware of is that after waking up from the sleep mode the WDT function will enable automatically The WDT operation being enabled or disabled should be handled appropriately by software after waking up from the sleep mode 2 The Status of T and P of STATUS Register A RESET condition is initiated by one of the following events 1 A power on condition 2 A high low high pulse on RESET pin or 3 Watchdog Timer time out The values of T and P as listed in Table 5 bel
11. RoR 7 k O 0101 OOrr rrr O5rr INCAR RHI SAP Z 9 Ek O 0101 Otrr rer O5r INCR RHR Z p eee ee fe wees eei O i Eg PC 1 SP 1 OOKk kkkk kkkk 1kkk CALL k Page k gt PC k gt A 1 1100 kkkk kkkk 1Ckk RETL k Top of Stack gt PC 1 1101 kkkk kkkk 1Dkk SUBAK Z C DC PC 1 SP 1 1111 kkkk kkkk 1Fkk ADD Ak Z C DC R2 A gt R2 0 0000 0010 0000 0020 Bits 8 9 of R2 unchanged Z C DC Note 1 This instruction is applicable to IOC50 1OC60 IOC90 IOCFO 0C51 IOCF1 only Note 2 This instruction is not recommended for RF operation Note 3 This instruction cannot operate under RF This specification is subject to change without prior notice 54 07 01 2003 V1 3 EM78P458 459 OTP ROM 4 16 Timing Diagrams AC Test Input Output Waveform 2 s 4 a Pa om P 2 0 gt TEST POINTS a 0 8 0 4 AC Testing Input is driven at 2 4V for logic 1 and 0 4V for logic 0 Timing measurements are made at 2 0V for logic 1 and 0 8V for logic 0 RESET Timing CLK 0 Instruction 1 NOP Executed ei EE LE DI LILI LJ LJ L4 LJ IRESET y Tdrh TCC Input Timing CLKS 0 a Tins B CLK x X x Tcc por X fs lt Ttcc gt This specification is subject to change without prior notice 55 07 01 2003 V1 3 T7 EM78P458 459 ADLAN OTP ROM 5 ABSOLUTE MAXIMUM RATINGS
12. and COE to 0 4 Interrupt e CMPIE IOCFO0 6 must be enabled Interrupt occurs at the rising edge of the comparator output pin The actual change on the pin can be determined by reading the Bit CMPOUT R3 lt 7 gt CMPIF RF 6 the comparator interrupt flag can only be cleared by software 5 Wake up from SLEEP Mode This specification is subject to change without prior notice 42 07 01 2003 V1 3 T7 EM78P458 459 PATTI OTP ROM f enabled the comparator remains active and the interrupt remains functional even under SLEEP mode If a mismatch occurs the interrupt will wake up the device from SLEEP mode The power consumption should be taken into consideration for the benefit of energy conservation f the function is unemployed during SLEEP mode turn off comparator before entering into sleep mode 4 11 The Initialized Values after Reset Table 11 The Summary of the Initialized Values for Registers locso Dre Pp P RESET and WDT Wake up from Pin Changed 1 i PD7 PD PDS PD4 PD3 7PD2 7PD1 7PDO IOCBO RESET and WDT Wake up from Pin Changed UO P Ob6 OD5 OD4 OD3 OD2 qp d pm p px 4 IPH7 no n n n n RESET and WDT eres RESET and WDT n n n n 1 1 1 1 1 7 F 7 1 1 Ol Ol X eka RESET and WDT IOC90 GCON locs1 Ol C67 janes Ol Oo meen RESET and WDT lt 9 5 al N m m REF 12 p
13. cleared by the WDTC or SLEP instructions Fig 5 depicts the circuit diagram of TCC WDT e R1 TCC is an 8 bit timer counter The TCC clock source can be internal or external clock input edge selectable from TCC pin If TCC signal source is from internal clock TCC will increase by 1 at every instruction cycle without prescaler Referring to Fig 5 selection of CLK Fosc 2 or CLK Fosc 4 depends on the CODE Option bit CLKS CLK Fosc 2 if CLKS bit is 0 and CLK Fosc 4 if CLKS bit is n If TCC signal source is from external clock input TCC will increase by 1 at every falling edge or rising edge of TCC pin The watchdog timer is a free running on chip RC oscillator The WDT will keep on running even after the oscillator driver has been turned off i e in sleep mode During normal operation or sleep mode a WDT time out if enabled will cause the device to reset The WDT can be enabled or disabled at any time during the normal mode by software programming Refer to WDTE bit of IOCEO register Without presacler the WDT time out period is approximately 18 ms NOTE VDD 5V Setup time period 16ms 5 VDD 3V Setup time period 19ms 5 This specification is subject to change without prior notice 22 07 01 2003 V1 3 EM78P458 459 OTP ROM CLK Fosc 2 or Fosc 4
14. flags of R3 can be used to determine the source of the reset wake up Case 3 is considered the continuation of program execution and the global interrupt ENI or DISI being executed decides whether or not the controller branches to the interrupt vector following wake up If ENI is executed before SLEP the instruction will begin to execute from the address 0x8 after wake up If DISI is executed before SLEP the execution will restart from the instruction right next to SLEP after wake up Only one of the Cases 2 to 4 can be enabled before entering into sleep mode That is a if Port 6 Input Status Change Interrupt is enabled before SLEP WDT must be disabled by software However the WDT bit in the option register remains enabled Hence the EM78P458 459 can be awakened only by Case 1 or 3 b if WDT is enabled before SLEP Port 6 Input Status Changed Interrupt must be disabled Hence the EM78P458 459 can be awakened only by Case 1 or 2 Refer to the section on Interrupt for further details c if Comparator High Interrupt is enabled before SLEP WDT must be disabled by software However the WDT bit in the option register remains enabled Hence the EM78P458 459 can be awakened only by Case 1 or 4 If Port 6 Input Status Change Interrupt is used to wake up the EM78P458 459 as in Case a above the following instructions must be executed before SLEP MOV A 0Bxx000110 Select internal TCC clock CONTW CLR
15. 11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 BitO MS ENWDT CLKS PTB HLF RCT HLP ID Bit 12 MS Oscillator type selection 0 RC type This specification is subject to change without prior notice 51 07 01 2003 V1 3 EM78P458 459 OTP ROM 1 XTAL type Bit 11 ENWTD Watchdog timer enable bit 0 Enable 1 Disable Bit 10 CLKS Clocks of each instruction cycle 0 Two clocks 1 Four clocks Refer to the section of Instruction Set Bit 9 PTB Protect bit 0 Enable 1 Disable Bit 8 HLF XTAL frequency selection 0 Low frequency 1 High frequency Bit 7 RCT Resistor Capacitor 0 Inter C External R 1 External RC Bit 6 HLP Power consumption selection 0 Low power 1 High power Bit 5 Bit 0 ID 5 ID 0 Customers ID Bit 12 SIGN2 Polarity bit of offset voltage 0 Negative voltage 1 Positive voltage e Bit 11 Bit 9 VOF2 2 VOF2 0 Offset voltage bits Bit 8 SIGN1 Polarity bit of offset voltage 0 Negative voltage 1 Positive voltage Bit 7 Bit 5 VOF1 2 VOF210 Offset voltage bits Bit 4 Bit 0 Not used This specification is subject to change without prior notice 52 07 01 2003 V1 3 T7 EM78P458 459 ADLAN OTP ROM 4 15 Instruction Set Each instruction in the instruction set is a 13 bit word divided into an OP code and one or more operands Normally all instructions are executed within one single instruction cycle one instruction consists of 2 os
16. Bit 6 CMPIE CMPIF interrupt enable bit 0 disable CMPIF interrupt 1 enable CMPIF interrupt Bit 7 Unimplemented read as 0 Individual interrupt is enabled by setting its associated control bit in the IOCFO to 1 Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction Refer to Fig 11 IOCFO register is both readable and writable 11 lOC51 PNMCON 7 6 5 4 3 2 1 0 PWM2E PWM1E T2EN T1EN T2P1 T2PO T1P1 T1PO Bit 7 PWM2E PWM2 enable bit 0 PWM2 is off default value and its related pin carries out the P52 function 1 PWM2 is on and its related pin will be set to output automatically Bit 6 PWM1E PWM1 enable bit 0 PWM1 is off default value and its related pin carries out the P51 function 1 PWM1 is on and its related pin will be set to output automatically Bit 5 T2EN TMR2 enable bit 0 TMR2 is off default value 1 TMR2 is on Bit 4 T1EN TMR1 enable bit 0 TMR1 is off default value 1 TMR1 is on Bit 3 Bit 2 T2P1 T2P0 TMR2 clock prescale option bits T2P1 T2PO Prescale 1 2 Default This specification is subject to change without prior notice 19 07 01 2003 V1 3 2 a EM78P458 459 PATTI OTP ROM DN LLL LLLLL OIII Bit 1 Bit 0 T1P1 T1P0 TMR1 clock prescale option bits T1P1 T1PO Prescale 1 2 Default 12 IOC61 DT1L the Least Significant Byte Bit 7 Bit 0 of Du
17. DATA BUS gt M gt M pU NN U u L I TCC R1 Pin gt 2 cycles 1 X o X t TCC overflow TE TS PAB interrupt M 9 y 8 bit Counter WDT DUX t PSRO PSR2 PAB 8 to 1 MUX X u WDTE 4 PAB in IOCE MUS WDT timeout Fig 5 Block Diagram of TCC and WDT 4 4 I O Ports Port 5 Port 6 and the I O registers are bi directional tri state I O ports The function of Pull high Pull down and Open drain can be set internally by IOCBO IOCCO and IOCDO respectively Port 6 features an input status changed interrupt or wake up function Each I O pin can be defined as input or output pin by the I O control register IOC50 IOC60 The I O registers and I O control registers are both readable and writable The I O interface circuits for Port 5 and Port 6 are shown in the following Fig 6 Fig 7 and Fig 8 respectively This specification is subject to change without prior notice 23 07 01 2003 V1 3 EM78P458 459 OTP ROM IOD PORTA NOTE Pull down is not shown in the figure Fig 6 The Ccircuit of I O Port and I O Control Register for Port 5 PCRD P50 INT POR IOD Bit 6 of IOCEO p DPQ CLK LO INT NOTE Pull high down and Open drain are not shown in the figure Fig 7 The Circuit of I O Port and I O Control Register for P50 INT This specification is subject to change without pri
18. EM78P459AM Power on voltage detector available 2 0V 0 15V This specification is subject to change without prior notice 5 07 01 2003 V1 3 Ceo EM78P458 459 PATTI OTP ROM 3 PIN ASSIGNMENT rm P56 CIN 1 24 P55 CIN P57 CO 2 23 P54 TCC P56 CIN 1 20 P55 CIN P60 ADCI 3 22 OSCI P57 CO 2 19 P54 TCC P61 ADC2 4 21 Osco P60 ADCI 3 18 OSCI ENTCC 5 20 RESET P61 ADC2 4 17 OSCO VSS 6 z 19 VDD z VSS 7 5 18 VDD VSS 5 z 16 VDD P62 ADC3 6 is P53 VREF P62 ADC3 gp cuam P53 VREF A P63 ADC4 7 OO 1 Pipin P63 ADC4 9 16 P52 PWM2 P64 ADC5 8 13 P51 PWM1 P64 ADCS 10 15 PSI PWMI P65 ADC6 9 12 P50 INT P65 ADC6 11 14 P50 INT P66 ADC7 10 11 P67 ADC8 P66 ADC7 12 13 P67 ADC8 Fig 1 Pin Assignment Table 1 EM78P458 Pin Description Symbo j PinNo Type A fFuntin MDD 16 Powersupply O XTAL type Crystal input terminal or external clock input pin RC type RC oscillator input pin XTAL type Output terminal for crystal oscillator or external clock input pin RC type Clock output with a period of one instruction cycle time the prescaler is determined by the CONT register External clock signal input Ge
19. Fig 19 Circuit for Crystal Resonator This specification is subject to change without prior notice 46 07 01 2003 V1 3 T7 EM78P458 459 AALAN OTP ROM Table 13 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonators Oscillator Type Frequency Mode C1 pF C2 pF Ceramic Resonators HXT LXT 25 25 200KHz Crystal Oscillator 455KHz 20 40 20 150 HXT 1 0MHz 15 30 15 30 2 0MHz 4 0MHz OSCI EM78P458 EM78P459 Fig 20 Circuit for Crystal Resonator Series Mode 4 7K 10K m Vdd OSCI o lt EM78P458 10K YS EM78P459 Fig 21 Circuit for Crystal Resonator Parallel Mode This specification is subject to change without prior notice 47 07 01 2003 V1 3 EM78P458 459 OTP ROM 3 External RC Oscillator Mode For some applications that do not require precise timing calculation the RC oscillator Fig 22 could offer users with an effective cost savings Nevertheless it should be noted that the frequency of the RC oscillator is influenced by the supply voltage the values of the resistor Rext the capacitor Cext and even by the operation temperature Moreover the frequency also changes slightly from one chip to another due to the manufacturing process variation In order to maintain a stable system frequency the values of the Cext should not be less than 20pF and that the value of Rext should not be greater than 1M ohm If they cannot be kept in this range the
20. P1 and T2P0 Options of 1 2 1 8 1 32 and 1 64 are defined by TMRx It is cleared when any type of reset occurs TMR1X and TMR2X TMR1H TWR1L and TMR2H TMR2L Timer X register TMRX is increased until it matches with PRDX and then is reset to 0 TMRX cannot be read PRDX PRD1 and PRD2 PWM period register This specification is subject to change without prior notice 40 07 01 2003 V1 3 EM78P458 459 OTP ROM ComparatorX Comparator 1 and Comparator 2 To reset TMRX while a match occurs and the TMRXIF flag is set at the same time 3 Programming the Related Registers When defining TMRX refer to the related registers of its operation as shown in Table 9 It must be noted that the PWMX bits must be disabled if their related TMRXs are employed That is bit 7 and bit 6 of the PWMCON register must be set to 0 Table 10 Related Control Registers of TMR1 and TMR2 Address Name Bit 7 Bit 6 Bit5 Bit4 Bit3 Bit2 Bit1 BitO IOC51 PWMCON IOC51 PWM2E PWM1E T2EN T1EN T2P1 T2PO T1P1 TT1PO 4 Timer programming procedures steps 1 Load PRDX with the TIMER period 2 Enable interrupt function by writing IOCFO if required 3 Load a desired value to PWMCON with the TMRX prescaler value and enable both TMRX and disable PWMX 4 10 Comparator EM78P458 459 has one comparator which has two analog inputs and one output The comparator can be employed to wake up from the sleep mode Fig 16 sh
21. RDX with the PWM period 2 Load DTX with the PWM Duty Cycle 4 Set PWMX pin to be output by writing a desired value to IOC51 1 2 3 Enable interrupt function by writing IOCFO if required 4 5 Load a desired value to IOC51 with TMRX prescaler value and enable both PWMX and TMRX This specification is subject to change without prior notice 39 07 01 2003 V1 3 EM78P458 459 OTP ROM 4 9 Timer 1 Overview Timer1 TMR1 and Timer2 TMR2 TMRX are 10 bit clock counters with programmable prescalers respectively They are designed for the PWM module as baud rate clock generators TMRX can be read written and cleared at any reset conditions 2 Function description Fig 15 shows TMRX block diagram Each signal and block are described as follows Fosc 1 2 L8 To PWMIIF MUX 132 1 f l set 1 64 gt x TMRIX amp o Period l Match Comparator a TIPO TIPI PRDI _t Data Bus Data Bus 4 T2P0 T2PI Comparator 34 T Y N Period Fosc Y TMR2X reset 4 Match 1 2 i 1 8 gt 1 32 ep MUX 1 64 gt To PWM2IF TMRIX TMRIH TMRIL TMR2X TMR2H TMR2L Fig 15 TMRX Block Diagram Fosc Input clock Prescaler TIPO and T1P1 T2
22. RES Operating voltage range 2 3V 5 5V Operating temperature range 0 C 70 C Operating frequency range base on 2 clocks Crystal mode DC 20MHz 2clks 5V DC 8MHz 2clks 3V RC mode DC 4MHz 2clks 5V DC 4MHz 2clks 3V Low power consumption Less than 1 5 mA at 5V 4MHz Typically 15 pA at 3V 32KHz Typically 1 uA during sleep mode 4K x 13 bits on chip ROM 84 x 8 bits on chip registers SRAM 2 bi directional I O ports 8 level stacks for subroutine nesting 8 bit real time clock counter TCC with selective signal sources trigger edges and overflow interrupt 8 bit multichannel Analog to Digital Converter with 8 bit resolution Dual Pulse Width Modulation PWM with 10 bit resolution One pair of comparators Power down SLEEP mode Six available interruptions TCC overflow interrupt Input port status changed interrupt wake up from the sleep mode External interrupt ADC completion interrupt PWM period match completion Comparator high interrupt Programmable free running watchdog timer 8 Programmable pull down I O pins 7 programmable pull high I O pins 8 programmable open drain I O pins Two clocks per instruction cycle This specification is subject to change without prior notice 4 07 01 2003 V1 3 EM78P458 459 OTP ROM Package types 20 pin DIP 300mil EM78P458AP 20 pin SOP 300mil EM78P458AM 24 pin skinny DIP 300mil EM78P459AK 24 pin SOP 300mil
23. ange without prior notice 17 07 01 2003 V1 3 T7 EM78P458 459 AALAN OTP ROM 9 IOCEO WDT Control Register Bit 7 WDTE Control bit is used to enable Watchdog Timer 0 Disable WDT 1 Enable WDT WDTE is both readable and writable Bit 6 EIS Control bit is used to define the function of the P50 INT pin 0 P50 input pin only 1 INT external interrupt pin In this case the I O control bit of P50 bit O of IOC50 must be set to 1 When EIS is O the path of INT is masked When EIS is 1 the status of INT pin can also be read by way of reading Port 5 R5 Refer to Fig 7 EIS is both readable and writable Bits 0 5 Not used 10 IOCFO Interrupt Mask Register 7 6 5 4 3 2 1 0 CMPIE PWM2IE PWMI1IE ADIE EXIE ICIE TCIE Bit 0 TCIE TCIF interrupt enable bit 0 disable TCIF interrupt 1 enable TCIF interrupt Bit 1 ICIE ICIF interrupt enable bit 0 disable ICIF interrupt 1 enable ICIF interrupt Bit 2 EXIE EXIF interrupt enable bit 0 disable EXIF interrupt 1 enable EXIF interrupt Bit 3 ADIE ADIF interrupt enable bit 0 disable ADIF interrupt 1 enable ADIF interrupt Bit 4 PWMTIE PWMIIF interrupt enable bit 0 disable PWM 1 interrupt 1 enable PWM1 interrupt This specification is subject to change without prior notice 18 07 01 2003 V1 3 P iN OTP ROM Bit 5 PWM2IE PWMZ2IF interrupt enable bit 0 disable PWM 2 interrupt 1 enable PWM2 interrupt
24. at any reset conditions If employed they can be turned down for power saving by setting T1EN bit PWMCON lt 4 gt or T2bEN bit PWMCON lt 5 gt to 0 This specification is subject to change without prior notice 38 07 01 2003 V1 3 EM78P458 459 OTP ROM 3 PWM Period PRDX PRD1 or PRD2 The PWM period is defined by writing to the PRDX register When TMRX is equal to PRDX the following events occur on the next increment cycle TMRX is cleared The PWMX pin is set to 1 The PWM duty cycle is latched from DT1 DT2 to DTL1 DTL2 lt Note gt The PWM output will not be set if the duty cycle is 0 The PWMXIF pin is set to 1 The following formula describes how to calculate the PWM period PERIOD PRDX 1 4 1 Fosc TMRX prescale value 4 PWM Duty Cycle DTX DT1H DT1L and DT2H DT2L DTL DL1H DL1L and DL2H DL2L The PWM duty cycle is defined by writing to the DTX register and is latched from DTX to DLX while TMRX is cleared When DLX is equal to TMRX the PWMX pin is cleared DTX can be loaded at any time However it cannot be latched into DTL until the current value of DLX is equal to TMRX The following formula describes how to calculate the PWM duty cycle Duty Cycle DTX 1 Fosc TMRX prescale value 5 Comparator X To change the output status while the match occurs the TMRXIF flag will be set at the same time 6 PWM Programming Procedures Steps 1 Load P
25. be fetched from address 001H This specification is subject to change without prior notice 30 07 01 2003 V1 3 EM78P458 459 OTP ROM vcc P IRQn p R Q i NS v IRQn lt heLk ow avr gr AFAD IRQm RE ENI DISI a Poc 10D c CLK lt a t IOCFWR BE SET IOCF a IOCFRD RFWR Fig 11 Interrupt Input Circuit 4 7 Analog To Digital Converter ADC The analog to digital circuitry consists of an 8 bit analog multiplexer three control registers ADCON R9 AD CMP CON IOCAO GCON IOC90 one data register ADDATA RA and an ADC with 8 bit resolution The functional block diagram of the ADC is shown in Fig 12 The analog reference voltage Vref and analog ground are connected via separate input pins The ADC module utilizes successive approximation to convert the unknown analog signal into a digital value The result is fed to the ADDATA Input channels are selected by the analog input multiplexer via the ADCON register Bits ADISO ADIS1 and ADIS2 ADCS Vref gt ADC7 ADC6 Y ic ADCS to gt gt E ADC Power Down r R P Start to Convert t L A E successive approximation oOon ADC4 gt ADC3 gt
26. change without prior notice 37 07 01 2003 V1 3 Fosc 1 2 1 8 1 32 1 64 Fosc 1 2 1 8 1 32 1 64 Data Bus ba MUX latch DLIH DLIL DTIH DTIL EM78P458 459 OTP ROM Comparator TIPO TIPI TIEN TMRIH TMRIL reset T2P0 T2PI T2EN PRDI Comparator 9 To PWMIIF Duty Cycle J Match a PWMI gt gt EISE gt S IOCSI Period Match e Data Bus latch To PWM2IF DT2H TPT MUX DT2L DL2H a Duty Cycle Comparator r i Match J wae PWM2 TMR2H TMR2L 4E0 5 A l reset Period FER OQ gt s IOCS5I Comparator 1 PRD2 Duty Cycle Period Match Fig 13 The Functional Block Diagram of the Dual PWMs PRDI TMRI DTI TMRI Fig 14 The Output Timing of the PWM 2 Increment Timer Counter TMRX TMR1H TWR1L or TMR2H TWR2L TMRX are ten bit clock counters with programmable prescalers They are designed for the PWM module as baud rate clock generators TMRX can be read written and cleared
27. characterized but not tested 2 These parameters are for design guidance only and are not tested 3 Specifications subject to change without notice This specification is subject to change without prior notice 59 07 01 2003 V1 3 T7 EM78P458 459 ADLAN OTP ROM APPENDIX Package Types OTP MCU Package Type Pin Count Package Size EM78P458AP DIP 20 pin 300mil EM78P458AM 300mil EM78P459AK Skinny DIP 300mil EM78P459AM 300mil This specification is subject to change without prior notice 60 07 01 2003 V1 3
28. cillator periods unless the program counter is changed by instruction MOV R2 A ADD R2 A or by instructions of arithmetic or logic operation on R2 e g SUB R2 A BS C R2 6 CLR R2 In this case the execution takes two instruction cycles In addition the instruction set has the following features 1 Every bit of any register can be set cleared or tested directly 2 The I O registers can be regarded as general registers That is the same instruction can operate on I O registers The symbol R represents a register designator that specifies which one of the registers including operational registers and general purpose registers is to be utilized by the instruction The symbol b represents a bit field designator that selects the value for the bit located in the register R that is affected by the operation The symbol k represents an 8 or 10 bit constant or literal value Table 16 The list of the instruction set of EM78P458 459 None 0 0000 0001 rrr 001r IORR OCR2A None lt Note1 gt AND R A A amp RoR O 0011 OOrr rrrr O3rr XOR A R AGORA O 0011 O1rr rrrr O3rr XOR R A A R gt R This specification is subject to change without prior notice 53 07 01 2003 V1 3 T7 EM78P458 459 ADLAN OTP ROM O 0100 OOrr rr O4rr_ MOVAR ORAZ O 0100 Ofrr rrr S O4rr MOVRAR RRO Z k O 0100 f r rer O4rr COMAR RA Z k O 0100 11rr rer O4rr COMR
29. ck Table 5 4 12 Oscillator 1 Oscillator Modes The EM78P458 and EM78P459 can be operated in four different oscillator modes such as High XTAL oscillator mode HXT Low XTAL oscillator mode LXT External RC oscillator mode ERC and RC oscillator mode with Internal capacitor IC Users can select one of them by programming the This specification is subject to change without prior notice 45 07 01 2003 V1 3 T7 EM78P458 459 PATTI OTP ROM MASK Option The up limited operation frequency of crystal resonator on the different VDDs is listed in Table 11 Table 12 The Summary of Maximum Operating Speeds Conditions Two clocks 2 Crystal Oscillator Ceramic Resonators XTAL EM78P458 459 can be driven by an external clock signal through the OSCI pin as shown in Fig 18 below noc Ext OSCI Ox Sock EM78P458 EM78P459 OSCO Fig 18 Circuit for External Clock Input In the most applications pin OSCI and pin OSCO can be connected with a crystal or ceramic resonator to generate oscillation Fig 19 depicts such circuit The same applies to the HXT mode and the LXT mode Table 12 provided the recommended values of C1 and C2 Since each resonator has its own attribute user should refer to their specifications for appropriate values of C1 and C2 RS a serial resistor may be necessary for AT strip cut crystal or low frequency mode OSCI EM78P458 EM78P459 OSCO AWA C2
30. ction allows the direct loading of the lower 10 program counter bits Thus JMP allows PC to jump to any location within a page CALL instruction loads the lower 10 bits of the PC and then PC 1 is pushed into the stack Thus the subroutine entry address can be located anywhere within a page RET RETL k RETI instruction loads the program counter with the contents of the top of stack ADD R2 A allows a relative address to be added to the current PC and the ninth and tenth bits of the PC are cleared MOV R2 A allows to load an address from the A register to the lower 8 bits of the PC and the ninth and tenth bits of the PC are cleared Any instruction that is written to R2 e g ADD R2 A MOV R2 A BC R2 6 will cause the ninth bit and the tenth bit A8 A9 of the PC to be cleared Thus the computed jump is limited to the first 256 locations of a page n the case of EM78P458 459 the most two significant bits A11 and A10 will be loaded with the content of PS1 and PSO in the status register R3 upon the execution of a JMP CALL or any other instructions set which write to R2 All instructions are single instruction cycle fclk 2 or fclk 4 except for the instructions which write to R2 need one more instruction cycle A11 A10 A9 A8 A7 ox A0 I 35 Stack 0 GAEEN Stack 1 RET RETI Stack 2 RETL K
31. current leakage from the RESET pin is about 5pA it is recommended that R should not be great than 40 K In this way the voltage at Pin RESET is held below 0 2V The diode D acts as a short circuit at power down The capacitor C is discharged rapidly and fully Rin the current limited resistor prevents high current discharge or ESD electrostatic discharge from flowing into Pin RESET VDD IRESET EM78P458 LO EM78P459 Fig 24 External Power on Reset Circuit 2 Residue Voltage Protection When battery is replaced device power Vdd is taken off but residue voltage remains The residue voltage may trips below Vdd minimum but not to zero This condition may cause a poor power on reset Fig 25 and Fig 26 show how to build a residue voltage protection circuit This specification is subject to change without prior notice 50 07 01 2003 V1 3 T7 EM78P458 459 ADLAN OTP ROM VDD e e VDD EM78P458 33K EM78P459 a OP 10K IRESET 3 y A4 p 1N4684 Fig 25 Circuit 1 for the Residue Voltage Protection VDD e VDD EM78P458 R1 gt EM78P459 SY lt IRESET M R2 Fig 26 Circuit 2 for the Residue Voltage Protection 4 14 CODE OPTION EM78P458 459 has one CODE option word and one Customer ID word that are not a part of the normal program memory Word 0 Word 1 Bit12 BitO Bit12 BitO Code option12 0 Code option12 0 1 Code Option Register Word 0 Bit12 Bit
32. e WM2 MeN IOC61 Bit7 Bit OTHE Power on 9 o o o we f o RESET and WDT 0 0 0 0 0 0 0 0 N A N A N A N A N A N A N A N A N A N A N A This specification is subject to change without prior notice 43 07 01 2003 V1 3 T7 EM78P458 459 AALAN OTP ROM Address Name ResetTye Bi7 Bite Bits Bit4 Bits Bit2 Bi T eri Poweron o 1 of o of o f o TIH f mesTadwoT o 3 o o o f o j o Wake up from Pin Change P P P P P o j P j P qe IOC81 PRD1 RESET and WDT Wake up from Pin Changed o e o e e Bitz Bite Bits Bit4 Bits Bite Bit Bito ocot Co 0 o o O72 WEE ac Tp L9 RESET and WDT Wake up from Pin Changed IOCA1 DT2H RESET and WDT Oo ALI2 SIGN2 VOF2 2 VOF2 1 VOF2 0 Wake up from Pin Changed IOCB1 PRD2 ip i oa o o P Bit Bits Bits Bits Bits Bite Bit locct 0 DERE 0 z o o IOCD1 o DL1H RESET and WDT o o o of o 3 o m f o Dre rep ee o o o o o o o f o o o o o Bit7 IOCE1 DL2L DL2H RESET and WDT Wake up from Pin Changed INTE coi RESET and WDT Wake up from Pin Changed N A N A N A N A N A N A N A N A A N ROUAR RESET and WDT X X 1 1 U Wake up from Pin Changed n ae nie Jump to address 0x08 or continue to e
33. finition bit The following Table describes how to define the characteristic of each pin of R6 Table 3 Description of AD Configuration Control Bits Bit 1 Bit 0 CKR1 CKRO The prescaler of oscillator clock rate of ADC 00 1 4 default value 01 1 16 10 1 64 11 The oscillator clock source of ADC is from WDT ring oscillator frequency frequency 256 18ms 14 2Khz 6 IOCBO Pull down Control Register 7 6 5 4 3 2 1 0 IPD7 PD6 PD5 PD4 PD3 PD2 PD1 PDO Bit 0 PDO Control bit is used to enable the pull down of the P60 pin 0 Enable internal pull down 1 Disable internal pull down Bit 1 PD1 Control bit is used to enable the pull down of the P61 pin Bit 2 PD2 Control bit is used to enable the pull down of the P62 pin Bit 3 PD3 Control bit is used to enable the pull down of the P63 pin This specification is subject to change without prior notice 16 07 01 2003 V1 3 T7 EM78P458 459 AALAN OTP ROM Bit 4 PD4 Control bit is used to enable the pull down of the P64 pin Bit 5 PD5 Control bit is used to enable the pull down of the P65 pin Bit 6 PD6 Control bit is used to enable the pull down of the P66 pin Bit 7 PD7 Control bit is used to enable the pull down of the P67 pin OCBO register is both readable and writable 7 lOCCO Open Drain Control Register a 6 5 4 3 2 1 0 OD7 OD6 OD5 OD4 OD3 OD2 OD1 ODO Bit 0 ODO Control bit used
34. ge of Operating Voltage 0 Vref 0 1 8 Vref 0 1 16 Vref 0 1 32 Vref Note Vref can not be less than 3 volts 2 ADC Data Register ADDATA RA This specification is subject to change without prior notice 33 07 01 2003 V1 3 EM78P458 459 OTP ROM When the A D conversion is complete the result is loaded to the ADDATA The START END bit is clear and the ADIF is set 3 A D Sampling Time The accuracy linearity and speed of the successive approximation A D converter are dependent on the properties of the ADC and the comparator The source impedance and the internal sampling impedance directly affect the time required to charge the sample holding capacitor The application program controls the length of the sample time to meet the specified accuracy Generally speaking the program should wait for 1 us for each KO of the analog source impedance and at least 1 ws for the low impedance source After the analog input channel is selected this acquisition time must be done before the conversion can be started 4 AID Conversion Time CKRO and CKR1 select the conversion time Tct in terms of instruction cycles This allows the MCU to run at the maximum frequency without sacrificing the accuracy of A D conversion For the EM78P458 459 the conversion time per bit is about 4 u s Table 8 shows the relationship between Tct and the maximum operating frequencies Table 9 Tct vs the Maximum Operat
35. gister Register Bank 0 Bank 1 3F 3F Fig 4 Data Memory Configuration This specification is subject to change without prior notice 11 07 01 2003 V1 3 EM78P458 459 OTP ROM 8 R9 ADCON Analog to Digital Control 7 6 5 4 3 2 1 0 IOCS ADRUN ADPD ADIS2 ADIS1 ADISO Bit 7 Bit 6 Unemployed read as 0 Bit 5 IOCS Select the Segment of IO control register 1 Segment 1 IOC51 1IOCF1 selected 0 Segment 0 IOC50 IOCFO selected Bit 4 ADRUN ADC starts to RUN 1 an A D conversion is started This bit can be set by software 0 reset on completion of the conversion This bit can not be reset though software Bit 3 ADPD ADC Power down mode 1 ADC is operating 0 switch off the resistor reference to save power even while the CPU is operating Bit2 Bit0 ADIS2 ADISO Analog Input Select 000 ANO 001 AN1 010 AN2 011 AN3 100 AN4 101 AN5 110 AN6 111 ANT They can only be changed when the ADIF bit and the ADRUN bit are both LOW 9 RA ADDATA the converted value of ADC When the A D conversion is complete the result is loaded into the ADDATA The START END bit is cleared and the ADIF is set 10 RB An 8 bit general purpose register 11 RC A 2 bit Bit Oand Bit 1 register 12 RD This specification is subject to change without prior notice 12 07 01 2003 V1 3 EM78P458 459 OTP ROM An 8 bit gene
36. ion Frequency CKRO CKR1 Operation Mode Max operation frequency Fsco 4 1 MHz Fsco 16 Fsco 64 16MHz Internal RC 5 AID Operation During Sleep Mode In order to reduce power consumption the A D conversion remains operational during sleep mode and is obligated to implement the internal RC clock source mode As the SLEP instruction is executed all the operations of the MCU will stop except for the A D conversion The RUN bit will be cleared and the result will be fed to the ADDATA when the conversion is completed If the ADIE is enabled the device will wake up Otherwise the A D conversion will be shut off no matter what the status of ADPD bit is 6 Programming Steps Considerations 1 Programming steps Follow these steps to obtain data from the ADC This specification is subject to change without prior notice 34 07 01 2003 V1 3 EM78P458 459 OTP ROM 1 Write to the three bits IMS2 IMSO on the AD CMP CON 1 register to define the characteristics of R6 Digital I O analog channels and voltage reference pin 2 Write to the ADCON register to configure AD module a Select A D input channel ADAS2 ADASO b Select the proper gains by writing to the GCON register optional c Define A D conversion clock rate CKR1 CKRO d Set the ADPD bit to 1 to begin sampling 3 Put ENI instruction if the interrupt function is employed 4 Set the ADRUN bit to 1 5 Wait f
37. ltage 1 Positive voltage Bit 5 Bit 3 VOF2 2 VOF2 0 Offset voltage bits Bit 1 Bit 0 PWM2 9 PWM2 8 The Most Significant Byte of PWM1 Duty Cycle A specified value keeps the PWM2 output to stay at high until the value matches with TMR2 17 IOCB1 PRD2 Period of PWM2 The content of IOCB1 is a period time base of PWM2 The frequency of PWM2 is the reverse of the period 18 IOCC1 DL1L the Least Significant Byte Bit 7 Bit 0 of Duty Cycle Latch of PWM1 The content of IOCC1 is read only 19 IOCD1 DL1H the Most Significant Byte Bit 1 Bit 0 of Duty Cycle Latch of PWM1 The content of IOCD1 is read only 20 IOCE1 DL2L the Least Significant Byte Bit 7 Bit 0 of Duty Cycle Latch of PWM2 The content of IOCE1 is read only 21 IOCF1 DL2H the Most Significant Byte Bit 1 Bit 0 of Duty Cycle Latch of PWM2 The content of IOCF1 is read only This specification is subject to change without prior notice 21 07 01 2003 V1 3 EM78P458 459 OTP ROM 4 3 TCC WDT amp Prescaler An 8 bit counter is available as prescaler for the TCC or WDT The prescaler is available for either the TCC or WDT only at any given time and the PAB bit of CONT register is used to determine the prescaler assignment The PSRO PSR2 bits determine the prescale ratio The prescaler is cleared each time the instruction is written to TCC under TCC mode The WDT and prescaler when assigned to WDT mode are
38. neral purpose Input only EE Default value while power on reset P51 P57 Cow EE E General purpose l O pin Default value while power on reset J a General purpose I O pin Padi GEL Default value while power on reset pt 6 1 Vf External interrupt pin triggered by falling edge E RU 4 Analog to Digital Converter AD EIS ADCS eek Defined by AD CMPCON IOCA0 lt 2 4 gt 13 14 O Pulse width modulation outputs This specification is subject to change without prior notice 6 07 01 2003 V1 3 Ceo EM78P458 459 VAY 7 OTP ROM PwM2 fDefined by PWMCON IOC51 6 7 gt m L External reference voltage for ADC Defined by AD CMPCON IOCA0 lt 7 gt gt the input pin of Vin of the comparator gt the input pin of Vin of the comparator Pin CO is the output of the comparator Defined by AD CMPCON IOCAO 5 6 Real time clock counter with Schmitt trigger input pin it must be tied to VDD or VSS if itis not in use MSS 5 Grun Table 2 EM78P459 Pin Description Sc an Power supply osci XTAL type Crystal input terminal or external clock input pin RC type RC oscillator input pin EN XTAL type Output terminal for crystal oscillator or external clock input pin RC type Clock output with a period of one instruction cycle time the prescaler is determined by the CONT register External clock signal input General purpose Input only
39. operation is zero Bit 1 DC Auxiliary carry flag Bit 0 C Carry flag 5 R4 RAM Select Register Bits 0 5 are used to select registers address 00 3F in the indirect address mode Bit 6 is used to select bank 0 or bank 1 Bit 7 is a general purpose read write bit See the configuration of the data memory in Fig 4 6 R5 R6 Port 5 Port 6 R5 and R6 are l O registers T R7 R8 All of these are 8 bit general purpose registers This specification is subject to change without prior notice 10 07 01 2003 V1 3 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E OF 10 11 1E 1F 20 21 3F EM78P458 459 OTP ROM RO RI TCO R2 PC STACK 0 R9 5 IOCS R3 Status STACK 1 R4 RSR STACK 2 0 Jd R5 Port 5 STACK 3 10C50 IOC51 PWMCON R6 Port 6 STACK 4 IOC60 IOC61 DTIL R7 STACK 5 IOC71 DTIH R8 STACK 6 IOC81 PRDI R9 ADCON STACK 7 IOC90 GCON IOC91 DT2L RA ADDATA IOCA0 AD CMPCON IOCAI DT2H RB TMRIL IOCB0 IOCBI PRD2 RC TMRIH IOCCO IOCCI DLIL RD TMR2L IOCD0 IOCD1 DL1H RE TMR2H IOCEO IOCE1 DL2L RF IOCF0 IOCF1 DL2H 16x8 Common Register PSR7 PSR6 00 20 20 32x8 32x8 Bank Bank Re
40. or either the interrupt flag to be set or the ADC interrupt to occur 6 Read ADDATA the conversion data register 7 Clear the interrupt flag bit ADIF 8 For next conversion go to Step 1 or Step 2 as required At least 2 Tct is required before next acquisition starts Note To obtain an accurate value it is necessary to avoid any data transition on I O pins during AD conversion 2 The Demonstration Programs To define the general registers R_0 Indirect addressing register PSW Status register PORT5 PORT6 R_F OXF Interrupt status register To define the control register 10C50 0X5 Control Register of Port 5 IOC60 0X6 Control Register of Port 6 C_INT OXF Interrupt Control Register This specification is subject to change without prior notice 35 07 01 2003 V1 3 ADC Control Registers ADDATA 0xA ADCON R 0x9 ADCONC 0xA GCON 0x9 To define bits in ADCONR ADRUN 0x4 ADPD 0x3 ORG 0 JMP INITIAL ORG 0x08 User program CLRR F BS ADCONR ADRUN RETI INITIAL MOV A OBXXXX1XXX IOW C INT MOV A QOxXX EM78P458 459 OTP ROM The contents are the results of ADC f 6 5 4 3 2 1 0 jon IOCS ADRUN ADPD ADIS2 ADIS1 ADISO jf 6 5 4 3 2 1 0 VREFS X X IMS2 IMS1 IMSO CKR1 CKRO D 7 6 5 4 3 2 1 0 OPE2 OPE1 G22 G21 G20 G12 G11 G10 ADC is executed as the bit is set Power Mode of ADC Initial addres
41. or notice 24 07 01 2003 V1 3 P60 P67 EM78P458 459 OTP ROM IOD PORT xCE Q Al NOTE Pull high down and Open drain are not shown in the figure Fig 8 The Circuit of I O Port and I O Control Register for P60 P67 ISLEP gt Interrupt ENI Instruction CLK DISI Instruction Interrupt Wake up from SLEEP Next Instruction Wake up from SLEEP Fig 9 Block Diagram of Port 6 with Input Changed Interrupt Wake up This specification is subject to change without prior notice 07 01 2003 V1 3 EM78P458 459 OTP ROM Table 4 Usage of Port 6 Input Changed Wake up Interrupt Function Usage of Port 6 Input Status Changed Wake up Interrupt I Wake up from Port 6 Input Status Change II Port 6 Input Status Change Interrupt a Before SLEEP 1 Read I O Port 6 MOV R6 R6 1 Disable WDT 2 Execute ENI 2 Read I O Port 6 MOV R6 R6 3 Enable interrupt Set IOCFO 1 3 Execute ENI or DISI 4 IF Port 6 changed interrupt 4 Enable interrupt Set IOCFO 1 Interrupt vector 008H 5 Execute SLEP instruction b After wake up 1 IF ENI 2 Interrupt vector 008H 2 IF DISI 5 Next instruction 4 5 RESET and Wake up 1 The function of RESET and Wake up A RESET is initiated by one of the following events 1
42. ow are used to check how the processor wakes up Table 6 shows the events which may affect the status of T and P This specification is subject to change without prior notice 28 07 01 2003 V1 3 T7 EM78P458 459 ADLAN OTP ROM Table 5 The Values of RST T and P after RESET RESET wake up during SLEEP mode 1 0 WDT during Operatingmode 0 P WDT wake up during SLEEP mode 0 0 Wake up on pin change during SLEEP mode 1 0 P Previous status before reset Table 6 The Status of RST T and P being Affected by Events Ee T 5 WDT time out 0 P SLEP instruction 1 0o Wake up on pin changed during SLEEP mode L4 o P Previous value before reset Oscillator Setup time Fig 10 Block Diagram of Reset of Controller This specification is subject to change without prior notice 29 07 01 2003 V1 3 EM78P458 459 OTP ROM 4 6 Interrupt The EM78P458 459 has six interrupts as listed below 1 2 1 TCC overflow interrupt 3 Port 6 Input Status Change Interrupt External interrupt P50 INT pin 4 5 6 Analog to Digital conversion completed When TMR1 TMR2 matches with PRD1 PRD2 respectively in PWM we ama we Dae we we When the comparators output change Before the Port 6 Input Status Change Interrupt is enabled reading Port 6 e g MOV R6 R6 is necessary Each Port 6 pin will have this feature if its stat
43. ows the circuit of the comparator Cin CMP it 4 Cin 4 Fig 16 Comparator Operating Mode 1 External Reference Signal The analog signal that is presented at Cin compares to the signal at Cin and the digital output CO of the comparator is adjusted accordingly The reference signal must be between Vss and Vdd The reference voltage can be applied to either pi of comparator Threshold detector applications may be of the same reference The comparator can operate from the same or different reference source 2 Comparator Outputs This specification is subject to change without prior notice 41 07 01 2003 V1 3 EM78P458 459 OTP ROM The compared result is stored in the CMPOUT of R3 The comparator outputs is output to P57 by programming bit5 lt COE gt of the AD CMPCON register to 1 P57 must be defined as an output if implemented as the comparator output Fig 17 shows the comparator output block diagram To C0 From op VO p CMRD EN EN To CMPOUT To CPIF a y From other comparator Fig 17 The Output Configuration of a Comparator 3 Using as An Operation Amplifier The comparator can be used as an operation amplifier if a feedback resistor is connected from the input to the output externally In this case the Schmitt trigger can be disabled for power saving by setting CE to 1
44. perature compensator In order to obtain more accurate frequency a precise resistor is recommended e Vcc i Rext OSCI EM78P458 EM78P459 Fig 23 Circuit for Internal C Oscillator Mode Table 15 R Oscillator Frequencies Average Fosc 5V 25 C Average Fosc 3V 25 C 2 22 MHz 2 17 MHz 100k 1 15 MHz 1 14 MHz 300k 375 KHz 370 KHz Note 1 Measured on DIP packages 2 Design reference only This specification is subject to change without prior notice 49 07 01 2003 V1 3 EM78P458 459 OTP ROM 4 13 Power on Considerations 1 Any microcontroller is not warranted to start proper operation before the power supply stabilizes in steady state EM78P458 459 POR voltage range is 1 2V 1 8V Under customer application when power is OFF Vdd must drop to below 1 2V and remains OFF for 10us before power can be switched ON again This way the EM78P458 459 will reset and work normally The extra external reset circuit will work well if Vdd can rise at very fast speed 50 ms or less However under most cases where critical applications are involved extra devices are required to assist in solving the power up problems External Power on Reset Circuit The circuit shown in Fig IV 13 1 1 implements an external RC to produce a reset pulse The pulse width time constant should be kept long enough to allow Vdd to reach minimum operation voltage This circuit is used when the power supply has a slow rise time Because the
45. ral purpose register 13 RE A 2 bit Bit O and Bit 1 register 14 RF Interrupt Status Register 7 6 5 4 3 2 1 0 CMPIF PWM2IF PWM1IF ADIF EXIF ICIF TCIF 1 means interrupt request and 0 means no interrupt occurs Bit 0 TCIF TCC overflow interrupt flag Set when TCC overflows reset by software Bit 1 ICIF Port 6 input status change interrupt flag Set when Port 6 input changes reset by software Bit 2 EXIF External interrupt flag Set by falling edge on INT pin reset by software Bit 3 ADIF Interrupt flag for analog to digital conversion Set when AD conversion is completed reset by software Bit 4 PWMTIF PWM1 Pulse Width Modulation interrupt flag Set when a selected period is reached reset by software Bit 5 PWM2IF PWM2 Pulse Width Modulation interrupt flag Set when a selected period is reached reset by software Bit 6 CMPIF High compared interrupt flag Set when a change occurs in the output of Comparator reset by software Bit 7 Unemployed read as 0 RF can be cleared by instruction but cannot be set IOCFO is the interrupt mask register Note that to read RF will result to logic AND of RF and IOCFO 15 R10 R3F All of these are 8 bit general purpose registers 4 2 Special Purpose Registers 1 A Accumulator Internal data transfer or instruction operand holding It can not be addressed This specification is subject to change wi
46. s Interrupt vector To dlear the ADCIF bit To start to execute the next AD conversion if necessary Enable the interrupt function of ADC X by application Interrupt disabled lt 6 gt This specification is subject to change without prior notice 36 07 01 2003 V1 3 EM78P458 459 OTP ROM CONTW MOV A 0B00000000 To employ Vdd as the reference voltage to define P60 as IOW ADCONC an analog input and set clock rate at fosc 4 En ADC MOV A QOBXXXXXXX1 To define P60 as an input pin and the others are dependent IOW PORT6 on applications MOV A 0B01000101 To enable the OP1 and set the gain as 32 IOW GCON BS ADCONR ADPD To disable the power down mode of ADC ENI Enable the interrupt function BS ADCONR ADRUN Start to run the ADC If the interrupt function is employed the following three lines may be ignored POLLING JBC ADCONR ADRUN To check the ADRUN bit continuously JMP POLLING ADRUN bit will be reset as the AD conversion is completed User program 4 8 Dual Sets of PWM Pulse Width Modulation 1 Overview In PWM mode both PWM1 and PWM2 pins produce up to a 10 bit resolution PWM output see Fig 13 for the functional block diagram A PWM output has a period and a duty cycle and it keeps the output in high The baud rate of the PWM is the inverse of the period Fig 14 depicts the relationships between a period and a duty cycle This specification is subject to
47. s at VDD Power down current output pin floating WDT enabled All input and I O pins at VDD Power down current output pin floating WDT disabled RESET High Fosc 32KHz Operating supply current VDD 3V at two Crystal type two clocks clocks output pin floating WDT disabled RESET High Fosc 32KHz Operating supply current VDD 3V at two Crystal type two clocks output pin floating WDT enabled RESET High Fosc 2MHz ICC3 Operating supply current VDD 5 0V at Crystal type two clocks two clocks output pin floating F RESET High Fosc 4MHz ICCA4 Operating supply current VDD 5 0V at Crystal type two clocks two clocks A output pin floating This specification is subject to change without prior notice 57 07 01 2003 V1 3 lt He TEH lt lt lt T7 EM78P458 459 ADLAN OTP ROM 6 2 AC Electrical Characteristic Ta 0 C 70 C VDD 5V 5 VSS 0V Symbol Pane Conos a e Wax Unt Dok mpucuKdwygde T amp Tof s x akero ER EL E CLKS 0 RC e 500 DC e 1 rath Bois reset td me macae 95 Ls Reser gue wan Taz asc RS wet Watchdog imer pered Tase 8 W a ape E um 5 RR RR E IN 20 Tdelay Output pin delay time Cload 20pF 50 N selected prescaler ratio a a ERNEUT GR RT Analog reference voltage AREF Vass Z 2 5V 30 Vass ee RN Resolu
48. t is connected to the 8 1 analog switch 0 OP2 is off default value and bypasses the input signal to the ADC 1 OP2 is on Bit 6 OP1E Enable the gain amplifier whose input is connected to P60 and output is connected to the 8 1 analog switch 0 OP1 is off default value and bypasses the input signal to the ADC 1 OP1 is on Bit 5 Bit 3 622 and G20 Select the gain of OP2 000 IS x 1 default value 001 IS x 2 010 IS x 4 011 IS x 8 100 IS x 16 101 IS x 32 Legend IS the input signal Bit 2 Bit 0 G12 and G10 Select the gain of OP1 000 IS x 1 default value 001 IS x 2 010 2 IS x4 011 IS x8 100 IS x 16 101 IS x 32 Legend S the input signal 5 IOCA0 AD CMPCON 7 6 5 4 3 2 1 0 VREFS CE COE IMS2 IMS1 IMSO CKR1 CKRO Bit 7 The input source of the Vref of the ADC 0 The Vref of the ADC is connected to Vdd default value and the P53 VREF pin carries out the function of P53 This specification is subject to change without prior notice 15 07 01 2003 V1 3 T7 EM78P458 459 AALAN OTP ROM 1 The Vref of the ADC is connected to P53 VREF Bit 6 CE Comparator enable bit 0 Comparator is off default value 1 Comparator is on Bit 5 COE Set P57 as the output of the comparator 0 the comparator acts as an OP if CE 1 1 act as a comparator if CE 1 Bit4 Bit2 IMS2 IMSO Input Mode Select ADC configuration de
49. thout prior notice 13 07 01 2003 V1 3 T7 EM78P458 459 AALAN OTP ROM 2 CONT Control Register 7 6 5 4 3 2 1 0 INTE INT TS TE PAB PSR2 PSR1 PSRO Bit 0 PSRO Bit 2 PSR2 TCC WDT prescaler bits TCC Rate WDT Rate 1 2 1 1 Bit 3 PAB Prescaler assignment bit 0 TCC 1 WDT Bit 4 TE TCC signal edge 0 increment if the transition from low to high takes place on the TCC pin 1 increment if the transition from high to low takes place on the TCC pin Bit 5 TS TCC signal source 0 internal instruction cycle clock If P54 is used as I O pin TS must be 0 1 transition on the TCC pin Bit 6 INT Interrupt enable flag 0 masked by DISI or hardware interrupt 1 enabled by the ENI RETI instructions Bit 7 INTE INT signal edge 0 interrupt occurs at the rising edge on the INT pin 1 interrupt occurs at the falling edge on the INT pin CONT register is both readable and writable 3 IOC50 IOC60 I O Port Control Register 1 puts the relative I O pin into high impedance while 0 defines the relative I O pin as output OC50 and IOC60 registers are both readable and writable This specification is subject to change without prior notice 14 07 01 2003 V1 3 T7 EM78P458 459 ADLAN OTP ROM 4 IOC90 GCON I O Configuration amp Control of ADC 7 6 5 4 3 2 1 0 OP2E OP1E G22 G21 G20 G12 G11 G10 Bit 7 OP2E Enable the gain amplifier which input is connected to P64 and outpu
50. tion Vdd Varer 5 0V Vass 0 0V 6 7 8 Bits LN Lneartyeror Vdd 251055VTa 25C o 32 fise DNL Differential nonlineareror Vdd 251055VTa 25C o 205 209 LSB Vdd Varer 5 0V Vass 0 0V Ls Pu oum tL analog voltage source TCN AD conversion time _Vdd Varer 5 0V Vass 0 0V_ 10 10 TAD Vdd Varer 5 0V Vass 0 0V ADOV A D OP output voltage swing au Re Vass 0 0V RL 10KO ADSR A D OP slew rate Vdd Varer 5 0V Vass 0 0V Power Supply Rejection Vdd 5 0V 0 5V Co f 32 LSB Note 1 These parameters are characterized but not tested 2 These parameters are for design guidance only and are not tested 3 It will not consume any current other than minor leakage current when A D is off 4 The A D conversion result never decrease with an increase in the input voltage and has no missing code 5 Specifications subject to change without notice 6 4 Comparator OP Characteristic Vdd 5 0V Vss 0V Ta 0 to 70 C Symbol Parameter Condition Min Typ Max Unit SR Sewme 01 02 Vus This specification is subject to change without prior notice 58 07 01 2003 V1 3 T7 EM78P458 459 ADLAN OTP ROM input voltage range manan T A i 2 02 os lS TERA pone Parra war sv vad m E ICI Offset voltage Vdd 5 0V Vss 0 0V 10 320 mv we copetatngnengs 80 EXEC esp eem Note 1 These parameters are
51. to enable the open drain of the P64 pin 0 Enable open drain output 1 Disable open drain output Bit 1 OD1 Control bit is used to enable the open drain of the P65 pin Bit 2 OD2 Control bit is used to enable the open drain of the P66 pin Bit 3 OD3 Control bit is used to enable the open drain of the P67 pin Bit 4 OD4 Control bit is used to enable the open drain of the P51 pin Bit 5 OD5 Control bit is used to enable the open drain of the P52 pin Bit 6 OD6 Control bit is used to enable the open drain of the P54 pin Bit 7 OD7 Control bit is used to enable the open drain of the P57 pin e OCCO register is both readable and writable 8 IOCDO Pull high Control Register 7 6 5 4 3 2 1 0 PH7 PH6 PH5 IPH3 PH2 PH1 PHO Bit 0 PHO Control bit is used to enable the pull high of the P60 pin 0 Enable internal pull high 1 Disable internal pull high Bit 1 PH1 Control bit is used to enable the pull high of the P61 pin Bit 2 PH2 Control bit is used to enable the pull high of the P62 pin Bit 3 PH3 Control bit is used to enable the pull high of the P63 pin Bit 4 Not used Bit 5 PH5 Control bit is used to enable the pull high of the P53 pin Bit 6 PH6 Control bit is used to enable the pull high of the P55 pin Bit 7 PH7 Control bit is used to enable the pull high of the P56 pin OCDO register is both readable and writable This specification is subject to ch
52. ty Cycle of PWM1 A specified value keeps the output of PWM1 to stay at high until the value matches with TMR1 13 IOC71 DT1H the Most Significant Byte Bit 1 Bit 0 of Duty Cycle of PWM1 7 6 5 4 3 2 1 0 CALI SIGN1 VOF1 2 VOF1 1 VOF1 0 z PWM1 9 PWM1 8 Bit 7 CALI1 Calibration enable bit 0 Calibration disable 1 Calibration enable Bit 6 SIGN1 Polarity bit of offset voltage 0 Negative voltage 1 Positive voltage Bit 5 Bit 3 VOF1 2 VOF1 0 Offset voltage bits Bit 1 Bit 0 PWM1 9 PWM1 8 The Most Significant Byte of PWM1 Duty Cycle A specified value keeps the PWM1 output to stay at high until the value matches with TMR1 14 IOC81 PRD1 Period of PWM1 The content of OC81 is a period time base of PWM1 The frequency of PWMI is the reverse of the period 15 IOC91 DT2L the Least Significant Byte Bit 7 Bit 0 of Duty Cycle of PWM2 A specified value keeps the of PWM1 output to stay at high until the value matches with TMR2 16 IOCA1 DT2H the Most Significant Byte Bit 1 Bit 0 of Duty Cycle of PWM2 7 6 5 4 3 2 1 0 CALI2 SIGN2 VOF2 2 VOF2 1 VOF2 0 PWM 2 9 PWM2I8 Bit 7 CALI2 Calibration enable bit This specification is subject to change without prior notice 20 07 01 2003 V1 3 EM78P458 459 OTP ROM 0 Calibration disable 1 Calibration enable Bit 6 SIGN2 Polarity bit of offset voltage 0 Negative vo
53. us changes Any pin configured as output or P50 pin configured as INT is excluded from this function Port 6 Input Status Change Interrupt will wake up the EM78P458 459 from the sleep mode if it is enabled prior to going into the sleep mode by executing SLEP When the controller is wake up it will continue to execute the succeeding program if the global interrupt is disabled or branches out to the interrupt vector 008H if the global interrupt is enabled RF the interrupt status register that records the interrupt requests in the relative flags bits IOCFO is an interrupt mask register The global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction When one of the interrupts when enabled occurs the next instruction will be fetched from address 008H Once in the interrupt service routine the source of an interrupt can be determined by polling the flag bits in RF The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine to avoid recursive interrupts The flag except ICIF bit in the Interrupt Status Register RF is set regardless of the status of its mask bit or the execution of ENI Note that the outcome of RF will be the logic AND of RF and IOCFO refer to Fig 11 The RETI instruction ends the interrupt routine and enables the global interrupt the execution of ENI When an interrupt is generated by the INT instruction when enabled the next instruction will
54. xecute next instruction Gp2 psi PSO T P z DC ue Ew 3 o4 o wu 4 of ti x J o Jj L B pp up ee ej 0x04 RA RSR Bs7 Bse qo o qoe quocp oce DU Em o u 9 d uw d u 0 P P P P P RESET and WDT C U O O Ol Ol IOCF1 O 0 Ol Ol O U This specification is subject to change without prior notice 44 07 01 2003 V1 3 T7 EM78P458 459 AALAN OTP ROM 0x05 pe p Pwen if iaf p 4 q aif n De repe lp P P T RESET and WDT Wake up from Pin Changed n RESET and WDT Wake up from Pin Changed LP P68 P a P z Doop zm ADCON o EE j m o o P Bi6 o o P o o o0 O Ol Wake up from Pin Changed RA ADDDATA IRESET and WDT RI R Ol O n n n n Wake up from Pin Changed TMR1L IRESET and WDT n n n n o o P o o o ie O o o of o 3 o m f o Dre rep ee o o o o o o o o of o o o o o P o o of of o TMR2L o o of of o Oe T p qp quj o o ee p ofo f o TMR2H 6 o of ofo J o 0 l o o o o P PWM2IF R o o o o o j o ISR o o of of of o e p e e ee ee pe ee 1 g 72 9 Pe desplome p Lre d gp p m p rp P X not used U unknown or don t care P previous value before reset R8 R9 B RC TMR1H RESET and WDT RD E F t che
Download Pdf Manuals
Related Search