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Canon Xsi Camera Accessories User Manual

1. Indicates property damage message i 30000000000000000000000000000000000000000000000000 30000000000000000000000000000000000000000000000000 No danger encountered Pay attention to important information MVME3100 Single Board Computer Installation and Use 6806800M28C About this Manual ee Summary of Changes This manual has been revised and replaces all prior editions Part Number Publication Date Description 6806800M28C December 2012 Added Declaration of Conformity on page 22 6806800M28B August 2011 Updated Safety Notes on page 148 and Sicherheitshinweise on page 152 6806800M28A April 2011 EA version MVME3100 Single Board Computer Installation and Use 6806800M28C 19 About this Manual 20 MVME3100 Single Board Computer Installation and Use 6806800M28C Chapter 1 Hardware Preparation and Installation 1 1 1 2 1 2 1 Overview The MVME3100 is a single slot single board computer based on the MPC8540 PowerQUICC III integrated processor The MVME3100 provides serial ATA SATA USB 2 0 2eSST VMEbus interfaces dual 64 bit 100 MHz PMC sites up to 128MB of Flash dual 10 100 1000 Ethernet one 10 100 Ethernet and five serial ports This board supports front and rear I O and a single SODIMM module for DDR memory Access to rear I O is available with the MV
2. 01051 MVME3100 Single Board Computer Installation and Use 6806800M28C 141 Specifications The preferred measurement location for a component may be junction case or ambient as specified in the table Junction temperature refers to the temperature measured by an on chip thermal device Case temperature refers to the temperature at the top center surface of the component Air temperature refers to the ambient temperature near the component Figure A 2 Secondary Side Components a U1054 01028 142 MVME3100 Single Board Computer Installation and Use 6806800M28C Appendix B Related Documentation B 1 Emerson Network Power Embedded Computing Documents The Emerson Network Power Embedded Computing publications listed below are referenced in this manual You can obtain electronic copies of Emerson Network Power Embedded Computing publications by contacting your local Emerson sales office For documentation of final released GA products you can also visit the following website http www emersonnetworkpowerembeddedcomputing com gt Solution Services Technical Documentation Search This site provides the most up to date copies of Emerson Network Power E
3. Command Description bmb Block Move Byte Halfword Word bmh bmw br Assign Delete Display User Program Break Points bsb Block Search Byte Halfword Word bsh bsw bvb Block Verify Byte Halfword Word bvh bvw cdDir 1509660 File System Directory Listing cdGet 1509660 File System File Load clear Clear the Specified Status History Table s cm Turns on Concurrent Mode csb Calculates a Checksum Specified by Command line Options csh csw devShow Display Show Device Node Table diskBoot Disk Boot Direct Access Mass Storage Device download Down Load S Record from Host ds One Line Instruction Disassembler echo Echo Line of Text elfLoader ELF Object File Loader errorDisplay Display the Contents of the Test Error Status Table eval Evaluate Expression execProgram Execute Program fatDir FAT File System Directory Listing fatGet FAT File System File Load 44 MVME3100 Single Board Computer Installation and Use 6806800M28C MOTLoad Firmware Table 3 1 MOTLoad Commands continued Command Description fdShow Display Show File Discriptor flashLock Flash Memory Sector Lock flashProgram Flash Memory Program flashShow Display Flash Memory Device Configuration Data flashUnlock Flash Memory Sector Unlock gd Go Execute User Program Direct Ignore Break Points gevDelete Global Environment Variable Delete gevDump Global E
4. Note SW2 has been configured to work in PCI X mode only The default setting is OFF Table 1 4 Slot Geographical Address Settings Slot Address GAPGA 4 0 SW3 SW4 SW5 SW6 SW7 SW8 1 111110 OFF OFF OFF OFF OFF ON 2 111101 OFF OFF OFF OFF ON OFF 3 011100 ON OFF OFF OFF ON ON 4 111011 OFF OFF OFF ON OFF OFF 5 011010 ON OFF OFF ON OFF ON 6 011001 ON OFF OFF ON ON OFF 7 111000 OFF OFF OFF ON ON ON 8 110111 OFF OFF ON OFF OFF OFF 9 010110 ON OFF ON OFF OFF ON 10 010101 ON OFF ON OFF ON OFF 11 110100 OFF OFF ON OFF ON ON 12 0 10011 ON OFF ON ON OFF OFF 13 110010 OFF OFF ON ON OFF ON 14 110001 OFF OFF ON ON ON OFF 15 0 10000 OFF ON ON ON ON 16 101111 OFF ON OFF OFF OFF OFF 17 001110 ON ON OFF OFF OFF ON 18 001101 ON ON OFF OFF ON OFF 19 101100 OFF ON OFF OFF ON ON 28 MVME3100 Single Board Computer Installation and Use 6806800M28C Table 1 4 Slot Geographical Address Settings continued Hardware Preparation and Installation Slot Address GAP GA 4 0 SW3 SW4 SW5 SW6 SW7 SW8 20 001011 ON ON OFF ON OFF OFF 21 101010 OFF ON OFF ON 1 4 4 PMCI O Voltage Configuration The onboard PMC sites may be configured to support 3 3V or 5 0V I O PMC modules To support 3 3V or 5 0V I O PMC modules both PMC I O keying pins must be installed in the holes If both keying pins are
5. Pin Signal Signal Pin 39 PAR 5V PCIRSTH 40 41 C BEI C BEO 42 43 C BE3 C BE2 44 45 AD1 ADO 46 47 AD3 AD2 48 49 AD5 AD4 50 51 AD7 AD6 52 53 AD9 AD8 54 55 AD11 AD10 56 57 AD13 AD12 58 59 AD15 AD14 60 61 AD17 AD16 62 63 AD19 AD18 64 65 AD21 AD20 66 67 AD23 AD22 68 69 AD25 AD24 70 71 AD27 AD26 72 73 AD29 AD28 74 75 AD31 AD30 76 MVME3100 Single Board Computer Installation and Use 6806800M28C 85 Pin Assignments Table 5 1 PMC Expansion Connector J4 Pin Assignments continued Pin Signal Signal Pin 77 PAR64 GND No Connect 78 79 5 C BE4 80 81 C BE7 C BE6 82 83 AD33 AD32 84 85 AD35 AD34 86 87 AD37 AD36 88 89 AD39 AD38 90 91 AD41 AD40 92 93 AD43 AD42 94 95 AD45 AD44 96 97 AD47 AD46 98 99 AD49 AD48 100 101 AD51 AD50 102 103 AD53 AD52 104 105 AD55 AD54 106 107 AD57 AD56 108 109 AD59 AD58 110 111 AD61 AD60 112 113 AD63 AD62 114 All PMC expansion signals are shared with the USB controller MVME3100 Single Board Computer Installation and Use 6806800M28C Pin Assignments 5 2 2 Ethernet Connectors GENET1 J41B GENET2 J2B ENET1 J2A There is one 10 100 and two 10 100 1000Mb s full duplex Ethernet interfaces using the MPC8540 Fast Ethernet Controller FEC and two Triple Speed Ethernet Controllers TSEC One Gigabit Eth
6. 95 Table 5 12 VMEP2 Connector Pinouts ehh hh men 97 Table 5 13 MVME721 Host I O Connector J10 Pin 98 Table 5 14 Planar sATA Power Connector J30 Pin 100 Table 5 15 USB Connector J27 Pin Assignments 100 Table 5 16 SATA Connectors J28 and J29 Pin 101 Table 5 17 Boundary Scan Header J24 Pin 5510 lt 101 Table 5 18 Processor COP Header J25 Pin Assignments 102 Table 6 1 Default Processor Address Map e ne 103 Table 6 2 MOTLoad s Processor Address 104 Table 6 3 System I O Memory Map 2 eee eee eee II mme 105 MVME3100 Single Board Computer Installation and Use 6806800M28C 9 List of Tables Table 6 4 Table 6 5 Table 6 6 Table 6 7 Table 6 8 Table 6 9 Table 6 10 Table 6 11 Table 6 12 Table 6 13 Table 6 14 Table 6 15 Table 6 16 Table 6 17 Table 6 18 Table 6 19 Table 6 20 Table 7 1 Table 7 2 Table 7 3 Table 7 4 Table 7 5 Table 7 6 Table 7 7 Table 7 8 Table 7 9 Table 7 10 Table A 1 Table A 2 Table A 3 Table B 1 Table B 2 Table B 3 System Status Register ele Ie LE ooh Kt R
7. nenne 40 333 Command eroe er ee ne ee er 41 3 4 Using the Command Line Interface cece cece eee ne 46 3 4 1 Command Line Rules 0 cece cece 48 3 4 2 Command Line Help 00 cece eee e eee n mn 48 3 5 BIEMWare settings suser ives de Ge 49 3 5 1 Default VME Settings liess eme 49 MVME3100 Single Board Computer Installation and Use 6806800M28C 3 Contents 3 5 2 Control Register Control Status Register 5 53 3 5 3 Displaying VME Settings II 53 3 5 4 Editing VME Settings 54 3 5 5 Deleting VME SettingS 0 cc cece cece ene eee eh me e 55 3 5 6 Restoring Default VME SettingS 0 cece cece eee teen 55 3 6 Remote Start nescis Re Ee PERE ER ERN OU ERE EE ETE DUE EE EN E EE E EE UE 56 3 7 Alternate Boot Images and Safe Start cc cee cece eee cece teen een 57 3 8 Firmware Startup Sequence Following 57 3 9 Firmware Scan for Boot Image nee eee he een hee 58 3 10 Boot Images save see 60 3 10 1 Checksum Algorithm avavavavanavvrevenevennenneeuenennnennernnennnenee 60 3 10 2 Image Flags ii rasen bee tebe doe EIE P baa peda ge aaa ees 61 3 10 3 RR a eines 62 3 10 4 Alternate Boot Data St
8. 77 4 10 68 USB i anne Seow dees Cede DR RU Rb pcr PER are 78 4 10 7 PMC Expansion san a a ra 78 4 11 General Purpose eh emer 79 4 12 Real time Clock Battery e he eere 79 4 13 Reset Control ne EE ER 79 AAA Debug Support oer RR rer hp rr PE Eden pr a 80 S JPIn ASSIgHImIentss dioec PIRE UE 81 9 1 ONE edna Be 81 5 2 COn TO re er 81 5 2 1 PMC Expansion Connector J4 0 2 0 0 cece cece eee eee eee seen 82 5 2 2 Ethernet Connectors GENET1 J41B GENET2 J2B 1 2 85 5 2 3 PCI Mezzanine Card PMC Connectors J11 J14 J21 23 85 5 2 4 Serial Port Connectors COM1 J41A 2 5 2 95 5 2 5 VMEb s PT Connector Ke Reg 95 5 2 6 VMEbus P2 Connector ee een RR a e IS oes 97 5 2 7 MVME721 PMC I O Module PIM Connectors J10 14 98 5 2 8 Planar sATA Power Connector 30 100 5 2 9 JSB Connector 27 i eee eter ee onn x es eR OR Me kle h n 100 5 2 10 sATA Connectors J28 29 ee 101 5 3 Headers ann en ee a ne een ae 101 5 3 1 Bound
9. SATA TX SATA TX GND SATA RX SATA RX U A WIN GND 5 3 5 3 1 Headers This section describes the pin assignments of the Headers on the MVME3100 For Hheader settings refer to Configuring Hardware on page 22 Boundary Scan Header J24 The 14 pin boundary scan header provides an interface for programming the on board PLDs and for boundary scan testing debug purposes The pin assignments for this header are as follows Table 5 17 Boundary Scan Header 24 Pin Assignments Pin Signal Signal Pin 1 TRST L GND 2 3 TDO GND 4 MVME3100 Single Board Computer Installation and Use 6806800M28C 103 Pin Assignments Table 5 17 Boundary Scan Header 24 Pin Assignments continued Pin Signal Signal Pin 5 TDI GND 6 7 TMS GND 8 9 TCK GND 10 11 NC GND BSCANEN L 12 13 BSCAN AW L GND 14 Pin 12 must be grounded in the cable in order to enable boundary scan 5 3 2 Processor COP Header 25 There is one standard 16 pin header that provides access to the COP function The pin assignments for this header are as follows Table 5 18 Processor COP Header J25 Pin Assignments Pin Signal Signal Pin 1 CPU TDO No Connect 2 3 CPU TDI CPU TRST L 4 5 Pullup CPU VIO 3 3V 6 7 CPU TCK CPU CKSTPI 8 9 CPU TMS No Connect 10 11 CPU SRST GND optional pull down 12 13
10. unsigned int checksum 0 while startPtr lt endPtr checksum startPtr 62 MVME3100 Single Board Computer Installation and Use 6806800M28C MOTLoad Firmware startPtr return checksum 3 10 2 Image Flags The image flags of the header define various bit options that control how the image will be executed Table 3 2 MOTLoad Image Flags Name Value Interpretation COPY_TO_RAM 0x00000001 Copy image to RAM at ImageRamAddress before execution IMAGE_MCG 0x00000002 MCG specific image IMAGE_POST 0x00000004 POST image DONT_AUTO_RUN 0x00000008 Image not to be executed e COPY RAM If set this flag indicates that the image is to be copied to RAM at the address specified in the header before control is passed If not set the image will be executed in flash In both instances control will be passed at the image offset specified in the header from the base of the image IMAGE MCG If set this flag defines the image as being an Alternate MOTLoad as opposed to USER image This bit should not be set by developers of alternate boot images IMAGE POST If set this flag defines the image as being power on self test image This bit flag is used to indicate that the image is a diagnostic and should be run prior to running either USER or boot images POST images are expected but not required to return to the boot block code upon completion MVME3100 Single Board Com
11. 202 0024 32 bits Tick Timer 3 Compare Register 0xE202 0034 32 bits Tick Timer 4 Compare Register 0xE202 0044 32 bits BIT 31 0 FIELD Tick Timer Compare Value OPER R W RESET 0 MVME3100 Single Board Computer Installation and Use 6806800M28C 121 Memory Maps 6 1 16 4 Counter Registers When enabled the tick timer Counter register increments every microsecond Software may read or write the counter at any time Table 6 20 Tick Timer Counter Registers Tick Timer 1 Counter Register 0xE202 0018 32 bits Tick Timer 2 Counter Register 0xE202 0028 32 bits Tick Timer 3 Counter Register 0xE202 0038 32 bits REG Tick Timer 4 Counter Register 0xE202 0048 32 bits BIT 31 0 FIELD Tick Timer Counter Value OPER R W RESET 0 6 1 17 Geographical Address Register The VMEbus Status register in the TSi148 provides the VMEbus geographical address of the MVME3100 This register reflects the inverted states of the geographical address pins at the 5 row 160 pin P1 connector 122 MVME3100 Single Board Computer Installation and Use 6806800M28C Programming Details Chapter 7 7 1 Introduction This chapter includes additional programming information for the MVME3100 single board computer Items discussed include MPC8540 Reset Configuration on page 124 MPC8540 Interrupt Controller on page 129 Local Bus Controller Chip Select Assignments on page 130 Two Wire
12. This indicator is illuminated by software assertion of its Defined LED silkscreen corresponding register bit 3 Power DS1 Red This indicator is illuminated to indicate power supply Supply Fail silkscreen fail condition 0 054 SATA 0 activity indicator Activity silkscreen SATA 1 DS5 Green SATA 1 activity indicator Activity silkscreen 38 MVME3100 Single Board Computer Installation and Use 6806800M28C Startup and Operation Table 2 3 Additional Onboard Status Indicators continued Function Label Color Description MPC8540 DS3 Green Indicates that the MPC8540 has completed the reset Ready silkscreen operation and is not in a power down state The MPC8540 Ready is multiplexed with the MPC8540 TRIG OUT so the LED can be programmed to indicate one of three trigger events based on the value in the MPC8540 TOSR register GENET 1 DS2 Off Extremely poor Signal to Noise ratio cannot receive data Link Quality silkscreen Slow Blink Poor SNR receive errors detected Green Fair SNR close to data error threshold Fast Blink Green Good SNR on link Green GENET 2 053 Same as DS2 Link Quality MVME3100 Single Board Computer Installation and Use 6806800M28C 39 Startup and Operation 40 MVME3100 Single Board Computer Installation and Use 6806800M28C Chapter 3 MOTLoad Firmware 3 1 3 2 3 3 3 3 1 Overview The MOTLoad f
13. REN ES PRICE PIER PUT PLE 13 1 Hardware Preparation and Installation 00 19 L QVEIVIEW We ees een ETER E snudde S 19 12 Getting Started nenne ener serverne ERREUR PER A HERREN 19 1 2 1 Overview of Startup Procedures 19 1 2 2 Unpacking Guidelines 0 0 2 0 ieee cece cee een II 20 1 3 Configuring Hardware enn nnn nee een mee 20 1 3 4 eee hme hehe 21 1 3 2 Configuration Switch 54 sh mee 24 1 3 3 Geographical Address Switch 53 25 1 3 4 PMCI O Voltage Configuration 0 eee ccc II 27 1 3 5 RTM SEEPROM Address Switch 1 c ccs 27 1 4 Installing Hardware 0 cece cece eee III HII ene e eee eeees 28 1 5 Connecting to Peripherals 1 0 2 0 cece cece eme 29 1 6 Completing the Installation 31 2 Startupand Operation 33 21 33 2 2 Applying Power see aka UST 33 23 Switches and Indicators u a ne 33 3 MOTLoadFTrmMWare urn 39 3 1 OVEIVIOW hun 39 3 2 Implementation and Memory 1 lt 39 3 3 MOTLoad Commands ccc cece cece nce ene ne nee m me 39 3 3 1 Utilities os serere n ea esse la es 39 33 2
14. 00000000 Outbound Image 7 Translation Offset Lower Register 4F000000 Outbound Image 7 2eSST Broadcast Select Register 00000000 3 5 2 3 5 3 MVME3100 gt Outbound window 7 OTAT7 is enabled 2eSST timing at SST320 transfer mode of SCT CR CSR Supervisory access The window accepts transfers on the PCI X Local Bus from 0xB1000000 0xB1FF0000 and translates them onto the VMEbus using an offset of 0x4F000000 thus an access to 0xB1000000 on the PCI X Local Bus becomes an access to 0x00000000 on the VMEbus Displaying VME Settings vmeCfg s m Displays Master Enable state vmeCfg s i 0 7 Displays selected Inbound Window state vmeCfg s o 0 7 Displays selected Outbound Window state vmeCfg s r184 Displays PCI Miscellaneous Register state vmeCfg s r188 Displays Special PCI Target Image Register state vmeCfg s r400 Displays Master Control Register state vmeCfg s r404 Displays Miscellaneous Control Register state MVME3100 Single Board Computer Installation and Use 6806800M28C Control Register Control Status Register Settings The CR CSR base address is initialized to the appropriate setting based on the Geographical address that is the VME slot number See the VME64 Specification and the VME64 Extensions for details As a result a 512K byte CR CSR area can be accessed from the VMEbus using the CR CSR AM code To display the changeable VME setting type the following at the firm
15. testSerialExtLoop Serial External Loopback testSeriallntLoop Serial Internal Loopback testStatus Display the Contents of the Test Status Table testSuite Execute Test Suite testSuiteMake Make Create Test Suite testWatchdogTimer Tests the Accuracy of the Watchdog Timer Device tftpGet TFTP Get MVME3100 Single Board Computer Installation and Use 6806800M28C 47 MOTLoad Firmware Table 3 1 MOTLoad Commands continued Command Description tftpPut TFTP Put time Display Date and Time transparentMode Transparent Mode Connect to Host tsShow Display Task Status upLoad Up Load Binary Data from Target version Display Version String s vmeCfg Manages user specified VME configuration parameters vpdDisplay VPD Display vpdEdit VPD Edit wait Wait for Test Completion waitProbe Wait for I O Probe to Complete 3 4 Using the Command Line Interface Interaction with MOTLoad is performed via a command line interface through a serial port on the SBC which is connected to a terminal or terminal emulator for example Window s Hypercomm The default MOTLoad serial port settings are 9600 baud 8 bits no parity The MOTLoad command line interface is similar to a UNIX command line shell interface Commands are initiated by entering a valid command a text string at the MOTLoad command line prompt and pressing the carriage return key to signif
16. 21 AD28 AD27 22 23 AD25 GND 24 25 GND C BE3 26 27 AD22 AD21 28 29 AD19 5V 30 31 3 3V VIO AD17 32 33 FRAME GND 34 35 GND IRDY 36 37 DEVSEL 5V 38 39 GND LOCK 40 41 PCI RSVD PCI RSVD 42 43 PAR GND 44 45 3 3V VIO AD15 46 47 AD12 AD11 48 49 AD09 5V 50 51 GND C BEO 52 53 AD06 AD05 54 55 AD04 GND 56 57 3 3V VIO ADO3 58 59 ADO2 ADO1 60 88 MVME3100 Single Board Computer Installation and Use 6806800M28C Pin Assignments Table 5 3 PMC Slot 1 Connector J11 Pin Assignments continued Pin Signal Signal Pin 61 AD00 5V 62 63 GND REQ64 64 Table 5 4 PMC Slot 1 Connector 12 Pin Assignments Pin Signal Signal Pin 1 12V TRST 2 3 TMS TDO 4 5 TDI GND 6 7 GND Not Used 8 9 Not Used Not Used 10 11 Pull up 3 3V 12 13 RST Pull down 14 15 3 3V Pull down 16 17 Not Used GND 18 19 AD30 AD29 20 21 GND AD26 22 23 AD24 3 3V 24 25 IDSEL1 AD23 26 27 3 3V AD20 28 29 AD18 GND 30 31 AD16 C BE2 32 33 GND IDSEL1B 34 35 TRDY 3 3V 36 37 GND STOP 38 39 PERR GND 40 41 3 3V SERR 42 43 C BEI GND 44 MVME3100 Single Board Computer Installation and Use 6806800M28C Pin Assignments Table 5 4 PMC Slot 1 Connector J12 Pin Assignments continued Pin Signal Signal Pin 45 AD14 AD13 46 47 M66EN AD10 48 49 A
17. 33 Table 2 2 MVME721 LED Status Indicators 0 cece ccc eee nee 36 Table 2 3 Additional Onboard Status Indicators 0 0 0 36 Table 3 1 MOTLoad Commands eu ee ever aa t EE 41 Table 3 2 MOTEoad Image Flags u ee 61 Table 4 1 MVME3100 Features Summary 0 0 cece eee eee eee hen 67 Table 4 2 MVME721 RTM Features Summary 69 Table 5 1 PMC Expansion Connector J4 Pin Assignments 82 Table 5 2 Ethernet Connectors Pin Assignment 85 Table 5 3 PMC Slot 1 Connector J11 Pin Assignments 85 Table 5 4 PMC Slot 1 Connector J12 Pin Assignments 87 Table 5 5 PMC Slot 1 Connector J13 Pin Assignments 88 Table 5 6 PMC Slot 1 Connector J14 Pin Assignments 89 Table 5 7 PMC Slot 2 Connector J21 Pin Assignments 91 Table 5 8 PMC Slot 2 Connector J22 Pin Assignments 92 Table 5 9 PMC Slot 2 Connector J23 Pin Assignments 93 Table 5 10 COM Port Connector Pin Assignments 95 Table 5 11 VMEbus P1 Connector Pin Assignments
18. Most options on the MVME3100 are software configurable Configuration changes are made by setting bits in control registers after the board is installed in a system Jumpers switches are used to control those options that are not software configurable These jumper settings are described further on in this section If you are resetting the board jumpers from their default settings it is important to verify that all settings are reset properly 1 4 1 MVME3100 Layout Figure 1 1 on page 25 illustrates the placement of the jumpers headers connectors switches and various other components on the MVME3100 There are two switch blocks which have user selectable settings Refer to Table 1 2 Table 1 3 and Table 1 4 for switch settings There is one switch on the MVME721 Refer to Table 1 5 and Table 1 6 for switch settings MVME3100 Single Board Computer Installation and Use 6806800M28C 23 Hardware Preparation and Installation The MVME3100 is factory tested and shipped with the configuration described in the following sections 24 MVME3100 Single Board Computer Installation and Use 6806800M28C Hardware Preparation and Installation Figure 1 1 Layout U1025 U1026 U1027 MVME3100 Single Board Computer Installation a
19. PCI bus A speed Indicates the frequency of PCI bus A 00 33 MHz 01 66 MHz 10 100 MHz 11 133 MHz PCIX_A PCI X bus A A set condition indicates that bus A is operating in PCI X mode A cleared condition indicates PCI mode PCI A 64B PCI bus A 64 bit A set condition indicates that bus A is enabled to operate in 64 bit mode cleared condition indicates 32 bit mode RSVD Reserved for future implementation Table 6 9 PCI Bus B Status Register REG BIT PCI Bus B Status Register 0xE2000005 7 6 5 4 3 2 1 0 MVME3100 Single Board Computer Installation and Use 6806800M28C 113 Memory Maps Table 6 9 PCI Bus B Status Register continued REG PCI Bus B Status Register OXE2000005 FIELD S a QI S S 3 D 5 5 LA a a a OPER R R R R R R R R RESET X x X 0 1 X x x PCI_B_SPD PCI bus B speed Indicates the frequency of PCI bus B 00 33 MHz 01 66 MHz 10 100 MHz 11 133 MHz PCIX_B PCI X bus B A set condition indicates that bus B is operating in PCI X mode A cleared condition indicates PCI mode PCI_B_64B PCI bus B 64 bit A set condition indicates that bus B is enabled to operate in 64 bit mode A cleared condition indicates 32 bit mode ERDY1 EREADY1 Indicates that the PrPMC module installed in PMC site 1 is ready for enumeration when set If cleared the PrPMC module is not ready for enumeration If no PrPMC is installe
20. Sicherheitshinweise Schaltereinstellungen Betrieb Fehlfunktion des Produktes Schalter die mit Reserved gekennzeichnet sind k nnen mit produktionsrelevanten Funktionen belegt sein Das ndern dieser Schalter kann im normalen Betrieb St rungen ausl sen Verstellen Sie nur solche Schalter die nicht mit Reserved gekennzeichnet sind Besch digung des Blades Hohe Luftfeuchtigkeit und Kondensat auf der Oberfl che des Blades k nnen zu Kurzschliissen f hren Betreiben Sie das Blade nur innerhalb der angegebenen Grenzwerte f r die relative Luftfeuchtigkeit und Temperatur Stellen Sie vor dem Einschalten des Stroms sicher dass sich auf dem Blade kein Kondensat befindet Umweltschutz 154 Umweltverschmutzung Falsche Entsorgung der Produkte schadet der Umwelt Entsorgen Sie alte Produkte gem der in Ihrem Land g ltigen Gesetzgebung und den Empfehlungen des Herstellers MVME3100 Single Board Computer Installation and Use 6806800M28C HOW TO REACH LITERATURE AND TECHNICAL SUPPORT Tempe Arizona USA 1 800 759 1107 1 602 438 5720 Munich Germany 49 89 9608 0 For literature training and technical assistance and support programs visit www emersonnetworkpowerembeddedcomputing com Emerson Network Power www emersonnetworkpowerembeddedcomputing com The global leader in enabling Business Critical Continuity AC Power Systems Embedded Computing Outside Plant I Services I Connectivity u Embedded
21. will need to install and configure your MVME3100 single board computer and MVME721 rear transition module RTM It provides specific preparation and installation information and data applicable to the board MVME3100 Single Board Computer Installation and Use 6806800M28C 13 About this Manual As of the printing date of this manual the MVME3100 supports the models listed below Model Number Description MVME3100 1152 677 MHz MPC8540 PowerQUICC III integrated processor 256 MB DDR SDRAM 64MB flash Gigabit Ethernet SATA IEEE handles MVME3100 1263 833 MHz MPC8540 Power QUICC III integrated processor 512MB DDR SDRAM 128 MB flash Gigabit Ethernet SATA USB PCI expansion connector IEEE handles MVME721 101 Rear Transition Module direct connect 75 mm PIM socket for PMC1 1 0 four serial 10 100 1000 Enet 10 100 Enet Abbreviations This document uses the following abbreviations Abbreviation Description AC Alternating Current ASIC Application Specific Integrated Circuit ATA Advanced Technology Attachment BLT Block Transfer CMC Common Mezzanine Card COM Communication COP Common On chip Processor COTS Commercial Off the Shelf CPU Central Processing Unit CTS Clear To Send DC Direct Current DDR Double Data Rate DIN Deutsches Insitut f r Normung eV DMA Direct Memory Access DPA Downlink Packet Access DRAM Dynamic Random Access Memory 14
22. 3 3V 58 59 No Connect No Connect 60 61 No Connect No Connect 62 63 No Connect No Connect 64 MVME3100 Single Board Computer Installation and Use 6806800M28C 101 Pin Assignments 5 2 8 Planar sATA Power Connector J30 There is 2mm pitch header installed as a planar header on the MVME3100 board to provide power to a serial ATA SATA drive mounted on the board or somewhere within the chassis The pin assignments for this header are as follows Table 5 14 Planar sATA Power Connector J30 Pin Assignments Pin Signal 1 5V 2 5V 3 GND 4 GND 5 2 9 USB Connector 27 There is one USB Type Aconnector located on the MVME3100 front panel The pin assignments are as follows Table 5 15 USB Connector J27 Pin Assignments Pin Signal 1 USB VBUS 5 0V 2 USB DATA 3 USB DATA 4 GND 102 MVME3100 Single Board Computer Installation and Use 6806800M28C Pin Assignments 5 2 10 sATA Connectors J28 and J29 The MVME3100 has two sATA connectors J28 is an internal type SATA connector located on the planar and is intended to connect to drive located on the board or somewhere inside the chassis J29 is an external type SATA connected located on the front panel and is intended to connect to an external SATA drive The pin assignment for these connectors is as follows Table 5 16 sATA Connectors J28 and J29 Pin Assignments Signal GND
23. 4 2 E202 0020 External PLD Tick Timer 2 Control Register 4 2 E202 0024 External PLD Tick Timer 2 Compare Register 4 2 E202 0028 External PLD Tick Timer 2 Counter Register 4 2 E202 002C Reserved 4 2 E202 0030 External PLD Tick Timer 3 Control Register 4 2 E202 0034 External PLD Tick Timer 3 Compare Register 4 2 E202 0038 External PLD Tick Timer 3 Counter Register 4 2 E202 003C Reserved 4 2 E202 0040 External PLD Tick Timer 4 Control Register 4 2 E202 0044 External PLD Tick Timer 4 Compare Register 4 2 E202 0048 External PLD Tick Timer 4 Counter Register 4 2 E202 004C E2FF Reserved 1 FFFF 1 Reserved for future implementation 2 32 bit write only 3 Byteread write capable 108 MVME3100 Single Board Computer Installation and Use 6806800M28C Memory Maps 6 1 5 System Status Register The MVME3100 board System Status register is read only register used to provide board status information Table 6 4 System Status Register REG System Status Register 2000000 BIT 7 6 5 4 3 2 1 0 FIELD z lt amp a a 24 a gt gt gt ra gt lt ea V4 ce ce lt pE R RESET 0 0 0 X 0 0 0 0 BD TYPE Board type These bits indicate the board type 00 VME SBC 01 PrPMC 10 11 Reserved ABORT This bit reflects the current state of the on board abort signal This is a debounced version of the abort switch and m
24. D32 Supervisory access The window accepts transfers on the PCI X Local Bus from 0x91000000 0xAFFF0000 and translates them onto the VMEbus using an offset of 0x70000000 thus an access to 0x91000000 on the PCI X Local Bus becomes an access to 0x01000000 on the VMEbus MVME3100 gt vmeCfg s 2 Displaying the selected Default VME Setting interpreted as Outbound Outbound Outbound Outbound Outbound Image Image Image Image Image 2 2 2 2 2 follows Attribute Register Starting Address Starting Address Ending Address Upper Ending Address Lower MVME3100 Single Board Computer Installation and Use 6806800M28C 80001061 Upper Register 00000000 Lower Register B0000000 Register 00000000 Register BOFF0000 53 Firmware 54 Outbound Image 2 Translation Offset Upper Register 00000000 Outbound Image 2 Translation Offset Lower Register 40000000 Outbound Image 2 2eSST Broadcast Select Register 00000000 MVME3100 gt Outbound window 2 2 is enabled 2eSST timing at SST320 transfer mode of SCT A24 D32 Supervisory access The window accepts transfers on the PCI X Local Bus from 0xB0000000 0xBOFF0000 and translates them onto the VMEbus using an offset of 0x40000000 thus an access to 0xB0000000 on the PCI X Local Bus becomes an access to 0xF0000000 the VMEbus MVME3100 gt vmeCfg s 03 Displaying the selected Default VME Se
25. Once launched most MOTLoad tests operate automatically without any user interaction There are a few tests where the functionality being validated requires user interaction that is switch tests interactive plug in hardware modules etc Most MOTLoad test results error data status data are logged not printed All MOTLoad tests commands have complete and separate descriptions refer to the MOTLoad Firmware Package User s Manual for this information All devices that are available to MOTLoad for validation verification testing are represented by a unique device path string Most MOTLoad tests require the operator to specify a test device at the MOTLoad command line when invoking the test A listing of all device path strings can be displayed through the devShow command If an SBC device does not have a device path string it is not supported by MOTLoad and can not be directly tested There are a few exceptions to the device path string requirement like testing RAM which is not considered a true device and can be directly tested without a device path string Refer to the devShow command description page in the MOTLoad Firmware Package User s Manual MVME3100 Single Board Computer Installation and Use 6806800M28C 3 3 3 MOTLoad Firmware Most MOTLoad tests can be organized to execute as group of related tests testSuite through the use ofthe testSuite command The expert operator can customize their testing by defining an
26. Use 6806800M28C Pin Assignments Table 5 8 PMC Slot 2 Connector J22 Pin Assignments continued Pin Signal Signal Pin 39 PERR GND 40 41 3 3V SERR 42 43 C BEI GND 44 45 AD14 AD13 46 47 M66EN AD10 48 49 AD08 3 3V 50 51 ADO7 REQ1B 52 53 3 3V GNT1B 54 55 Not Used GND 56 57 Not Used EREADY1 58 59 GND Not Used 60 61 ACK64 3 3V 62 63 GND No Connect MONARCH 64 Table 5 9 PMC Slot 2 Connector J23 Pin Assignments Pin Signal Signal Pin 1 Reserved GND 2 3 GND C BE7 4 5 C BE6 C BES 6 7 C BE4 GND 8 9 3 3V VIO PAR64 10 11 AD63 AD62 12 13 AD61 GND 14 15 GND AD60 16 17 AD59 AD58 18 19 AD57 GND 20 21 3 3V VIO AD56 22 MVME3100 Single Board Computer Installation and Use 6806800M28C 95 Pin Assignments Table 5 9 PMC Slot 2 Connector J23 Pin Assignments continued Pin Signal Signal Pin 23 AD55 AD54 24 25 AD53 GND 26 27 GND AD52 28 29 AD51 AD50 30 31 AD49 GND 32 33 GND AD48 34 35 AD47 AD46 36 37 AD45 GND 38 39 3 3V VIO AD44 40 41 AD43 AD42 42 43 AD41 GND 44 45 GND AD40 46 47 AD39 AD38 48 49 AD37 GND 50 51 GND AD36 52 53 AD35 AD34 54 55 AD33 GND 56 57 3 3V VIO AD32 58 59 Reserved Reserved 60 61 Reserved GND 62 63 GND Reserved 64 96 MVME3100 Single Board Computer Installation and Use 6806800M28
27. bytes Device Function Notes 90 000 N A 051621 temperature sensor 130 MVME3100 Single Board Computer Installation and Use 6806800M28C Programming Details Table 7 4 I2C Bus Device Addressing continued Device Address I2C Bus A2 A1 Address binary Size bytes Device Function Notes A0 000 256x8 DDR memory SPD SODIMM module i banks 1 and 2 corresponding to MPC8540 memory controller chip selects 0 and 1 A2 001 Reserved A4 010 65 536 8 User configuration 2 A6 011 65 536 8 User configuration 2 A8 100 8192x8 VPD on board system configuration 2 AA 101 8192x8 RTM VPD off board configuration 23 AC 110 Reserved AE 111 Reserved D0 N A N A DS1375 real time clock 1 Each SPD defines the physical attributes of each bank or group of banks If both banks of a SODIMM are populated they are the same speed and memory size 2 This is a dual address serial EEPROM 3 The device address is user selectable using switches on the RTM The recommended address setting for the MVME3100 is AA 7 6 User Configuration EEPROM The MVME3100 board provides two 64KB dual address serial EEPROMs for a total of 128KB user configuration storage These EEPROMs are hardwired to have device IDs as shown in Table 7 4 on page 130 and each device ID will not be used for any other function Refer to the 2 Wire Serial EEPROM Datasheet listed in Appendix B Related Documentation for addition
28. not in the same location or if the keying pins are not installed the PMC sites will not function Note that setting the PMC I O voltage to 5 0V forces the PMC sites to operate in PCI mode instead of PCI X mode The default factory configuration is for 3 3V PMC I O voltage 1 4 5 SEEPROM Address Switch 51 A 4 position SMT configuration switch is located on the RTM to set the device address of the RTM serial EEPROM device The switch settings are defined in the following table Table 1 5 RTM EEPROM Address Switch Assignments Position SW1 SW2 SW3 SW4 Function 1 2 Not Used OFF 1 1 1 Table 1 6 EEPROM Address Settings Device Address A 2 0 swi SW2 SW3 A0 000 ON ON ON A2 001 OFF ON ON A4 010 ON OFF ON A6 011 OFF OFF ON A8 100 ON ON OFF AA Factory 101 OFF ON OFF MVME3100 Single Board Computer Installation and Use 6806800M28C 29 Hardware Preparation and Installation Table 1 6 EEPROM Address Settings continued Device Address A 2 0 SW1 sw2 SW3 AC 110 ON OFF OFF 111 The RTM EEPROM address switches must be set for address in order for this device to accessible by MotLoad 1 5 Installing Hardware NOTICE Damage of the Product and Additional Devices and Modules Incorrect installation or removal of additional devices or modules may damage the product or the ad
29. vmeCfg d r40C Deletes User AM Codes Register state vmeCfg d rF70 Deletes VMEbus Register Access Image Control Register state 3 5 6 Restoring Default VME Settings To restore all of the changeable VME setting back to their default settings type the following at the firmware prompt vmeCfg z MVME3100 Single Board Computer Installation and Use 6806800M28C 57 MOTLoad Firmware OM 3 6 Remote Start As described in the MOTLoad Firmware Package User s Manual listed in Appendix B Related Documentation remote start allows the user to obtain information about the target board download code and or data modify memory on the target and execute downloaded program These transactions occur across the VMEbus in the case of the MVME3100 MOTLoad uses one of four mailboxes in the Tsi148 VME controller as the inter board communication address IBCA between the host and the target CR CSR slave addresses configured MOTLoad are assigned according to the installation slot inthe backplane as indicated by the VME64 Specification For reference the following values are provided Slot Position CS CSR Starting Address 1 0x0008 0000 0x0010 0000 0x0018 0000 0x0020 0000 0x0028 0000 0x0030 0000 0x0038 0000 0x0040 0000 0x0048 0000 0x0050 0000 0x0058 0000 0x0060 0000 wml ojlo o ul al win For further details on CR CSR space please refer to the VME64 Specif
30. which of the Ethernet PHYs originated their combined OR d interrupt Table 6 11 Interrupt Detect Register REG Interrupt Detect Register 2000007 BIT 7 6 5 4 3 2 1 0 FIELD gt gt gt T N d S S S S J i ce ce ce ce ce FH R R R R R R R R RESET 1 1 1 0 0 0 0 0 TSEC1_PHY TSEC1 PHY interrupt If cleared the interrupt is not asserted If set the TSEC1 interrupt is asserted TSEC2_PHY TSEC2 PHY interrupt If cleared the TSEC2 interrupt is not asserted If set the TSEC2 interrupt is asserted FEC_PHY FEC PHY interrupt If cleared the FEC interrupt is not asserted If set the FEC interrupt is asserted RSVD Reserved for future implementation 6 1 11 Presence Detect Register The MVME3100 provides a Presence Detect register that may be read by the system software to determine the presence of optional devices Table 6 12 Presence Detect Register REG Presence Detect Register 2000008 BIT 7 6 5 4 3 2 1 0 116 MVME3100 Single Board Computer Installation and Use 6806800M28C Memory Maps Table 6 12 Presence Detect Register continued REG FIELD Presence Detect Register 2000008 OPER RESET x PEP x x PMCIP RSVD RSVD RSVD nm 6 1 12
31. 00M28C Pin Assignments Table 5 6 PMC Slot 1 Connector J14 Pin Assignments continued Pin Signal Signal Pin 13 PMC1_13 P2 C7 PMC1_14 P2 A7 14 15 PMC1_15 P2 C8 PMC1_16 P2 A8 16 17 PMC1_17 P2 C9 PMC1_18 P2 A9 18 19 PMC1_19 P2 C10 PMC1_20 P2 A10 20 21 PMC1PMC1_21 P2 C11 PMC1_22 P2 A11 22 23 PMC1_23 P2 C12 PMC1_24 P2 A12 24 25 PMC1_25 P2 C13 PMC1_26 P2 A13 26 27 PMC1_27 P2 C14 PMC1_28 P2 A14 28 29 PMC1_29 P2 C15 PMC1_30 2 15 30 31 PMC1_31 P2 C16 PMC1_32 P2 A16 32 33 PMC1_33 P2 C17 PMC1_34 P2 A17 34 35 PMC1_35 P2 C18 PMC1_36 P2 A18 36 37 PMC1_37 P2 C19 PMC1_38 P2 A19 38 39 PMC1_39 P2 C20 PMC1_40 P2 A20 40 41 PMC1 41 2 21 PMC1 42 2 21 42 43 43 2 22 PMC1 44 2 22 44 45 45 2 23 PMC1 46 2 23 46 47 47 2 24 PMC1 48 2 24 48 49 PMC1 49 2 25 50 2 25 50 51 51 2 26 PMC1 52 2 26 52 53 PMC1 53 2 27 PMC1 54 2 27 54 55 55 2 28 PMC1 56 2 28 56 57 57 2 29 58 2 29 58 59 PMC1 59 P2 C30 PMC1 60 P2 A30 60 61 PMC1 61 P2 C31 PMC1 62 P2 A31 62 63 PMC1 63 P2 C32 PMC1 64 P2 A32 64 92 MVME3100 Single Board Computer Installation and Use 6806800M28C Pin Assignments Table 5 7 PMC Slot 2 Connector J21 Pin Assig
32. 16 name string eg MVME3100 void globalData 16K zeroed user defined unsigned int reserved 12 altBootData t MVME3100 Single Board Computer Installation and Use 6806800M28C MOTLoad Firmware 3 10 4 3 10 5 Alternate Boot Data Structure The globalData field of the alternate boot data structure points to an area of RAM which was initialized to zeroes by the boot loader This area of RAM is not cleared by the boot loader after execution of a POST image or other alternate boot image is executed It is intended to provide a user a mechanism to pass POST image results to subsequent boot images The boot loader performs no other initialization of the board than that specified prior to the transfer of control to either a POST USER or MCG image Alternate boot images need to initialize the board to whatever state the image may further require for its execution POST images are expected but not required to return to the boot loader Upon return the boot loader proceeds with the scan for an executable alternate boot image POST images that return control to the boot loader must ensure that upon return the state of the board is consistent with the state that the board was in at POST entry USER images should not return control to the boot loader Alternate Boot Images and Safe Start Some later versions of MOTLoad support alternate boot images and a safe start recovery procedure If safe start is available on
33. 61 MOTLoad Firmware 3 10 Boot Images Valid boot images whether POST USER or are located on 1MB boundaries within flash The image may exceed 1MB in size An image is determined valid through the presence of two valid image keys and other sanity checks valid boot image begins with structure as defined in the following table Name Type Size Notes UserDefined unsigned integer 8 User defined ImageKey 1 unsigned integer 1 0x414c5420 ImageKey 2 unsigned integer 1 0x424f4f54 ImageChecksum unsigned integer 1 Image checksum ImageSize unsigned integer 1 Must be multiple of 4 ImageName unsigned character 32 User defined ImageRamAddress unsigned integer 1 RAM address ImageOffset unsigned integer 1 Offset from header start to entry ImageFlags unsigned integer 1 Refer to Image Flags on page 63 ImageVersion unsigned integer 1 User defined Reserved unsigned integer 8 Reserved for expansion 3 10 1 Checksum Algorithm The checksum algorithm is a simple unsigned word add of each word 4 byte location in the image The image must be multiple of 4 bytes in length word aligned The content of the checksum location in the header is not part of the checksum calculation The calculation assumes the location to be zero The algorithm is implemented using the following code Unsigned int checksum Unsigned int startPtr starting address Unsigned int endPtr ending address
34. 6806800M28C MOTLoad Firmware The scan is performed downwards from boot block image and searches first for POST then USER and finally MCG images In the case of multiple images of the same type control is passed to the first image encountered in the scan Safe Start whether invoked by hitting ESC on the console within the first five seconds following power on reset or by setting the Safe Start jumper interrupts the scan process The user may then display the available boot images and select the desired image The feature is provided to enable recovery in cases when the programmed Alternate Boot Image is no longer desired The following output is an example of an interactive Safe Start ABCDEInteractive Boot Mode Entered boot gt Interactive boot commands d show directory of alternate boot images c continue with normal startup q quit without executing any alternate boot image r address execute specified or default alternate image p address execute specified or default POST image this help screen h this help screen boot d FFE00000 Size 00100000 Flags 00000003 Name MOTLoad Addr FFD00000 Size 00100000 Flags 00000003 Name MOTLoad boot c NOPORSTUVabcdefghijkilmn3opgrsstuvxyzaWXZ Copyright Motorola Inc 1999 2004 All Rights Reserved MOTLoad RTOS Version 2 0 PAL Version 0 b EA02 MVME3100 gt MVME3100 Single Board Computer Installation and Use 6806800M28C
35. 800M28C 73 Functional Description Figure 4 2 721 RTM Block Diagram Rear Panel io See ae Future Option 1 1 t 1 I PIM 10 1 5 GigE 10 100 Serial Serial Serial Serial B SATA H 45 45 45 45 45 45 1 1 1 1 10 100 PMG 1 Jn4 10 Serial Port 4 Serial Port 3 Serial Port 2 Serial Port 1 VPD 8K8 Bus 2 4390 0106 4 4 Processor The MVME3100 supports the MPC8540 processor The processor core frequency runs at 833 or 667 MHz The MPC8540 has integrated 256KB L2 cache 4 5 System Memory The MPC8540 provides one standard DDR SDRAM SODIMM socket This socket supports standard single or dual bank unbuffered SSTL 2 DDR I JESD8 9B compliant SODIMM module with ECC The MPC8540 DDR memory interface supports up to 166 MHz 333 MHz data rate operation 74 MVME3100 Single Board Computer Installation and Use 6806800M28C Functional Description 4 6 4 6 1 4 6 2 Local Bus Interface The MVME3100 uses the MPC8540 local bus controller LBC for access to on board Flash and I O registers The LBC has programmable timing modes to support devices of different access times as well as device widths of 8 16 and 32 bits The MVME3100 uses the LBC in GPCM general purpose chip select machine mode to interface to two physical banks of
36. 8540 Reference Manual listed in Appendix B Related Documentation for additional details regarding the operation of the MPC8540 PIC MVME3100 Single Board Computer Installation and Use 6806800M28C 129 Programming Details 7 4 Local Bus Controller Chip Select Assignments The following table shows local bus controller LBC bank and chip select assignments for the MVME3100 board Table 7 3 LBC Chip Select Assignments LBC Bank Data Bus Chip Select Local Bus Function Size Width Notes 0 Boot Flash bank 32MB 128MB 32 bits 1 1 Optional second Flash bank 32MB 128MB 32 bits 1 2 Control Status registers 64 KB 32 bits 2 3 Quad UART 64 KB 8 bits 4 32 bit timers 64 KB 32 bits 3 5 7 Not used 1 Flash bank size determined by VPD flash packet 2 Contro Status registers are byte read and write capable 3 32 bit timer registers are byte readable but must be written as 32 bits 1 5 Two Wire Serial Interface Atwo wire serial interface for the MVME3100 is provided by an I C compatible serial controller integrated into the MPC8540 The MPC8540 I C controller is used by the system software to read the contents of the various I C devices located on the MVME3100 The following table contains the I C devices used for the MVME3100 and their assigned device addresses Table 7 4 12C Bus Device Addressing Device Address 12 Bus 2 1 Address binary Size
37. C Pin Assignments 5 2 4 Serial Port Connectors COM1 J41A COM2 COM5JJ2A D There is one front access asynchronous serial port interface SPO that is routed to the R 45 front panel connector There are four asynchronous serial port interfaces SP1 SPA which are routed to the P2 connector The pin assignments for these connectors are as follows Table 5 10 COM Port Connector Pin Assignments Pin Signal 1 No connect RTS NI DJAJ BR S No connect 5 2 5 VMEbus P1 Connector The VME P1 connector is a 160 pin DIN The P1 connector provides power and VME signals for 24 bit address and 16 bit data The pin assignments for the P1 connector is as follows Table 5 11 VMEbus P1 Connector Pin Assignments ROWZ ROWA ROW B ROWC ROWD 1 Reserved D00 BBSY D08 5V 1 2 GND D01 BCLR D09 GND 2 3 Reserved D02 ACFAIL D10 Reserved 3 4 GND D03 BGOIN D11 Reserved 4 5 Reserved D04 BGOOUT D12 Reserved 5 6 GND D05 BG1IN D13 Reserved 6 7 Reserved D06 BGTOUT D14 Reserved 7 MVME3100 Single Board Computer Installation and Use 6806800M28C 97 Pin Assignments Table 5 11 VMEbus P1 Connector Pin Assignments continued ROW 2 ROW ROW B ROW ROW D 8 GND D07 BG2IN D15 Reserved 8 9 Reserved GND BG2OUT GND GAP_L 9 10 GND SYSC
38. C P2 D 1 SPIRX PMC1 102 5V PMC1 101 E1 1 2 GND PMC1 104 GND PMC1 103 E1 1 3 SPITX PMC1 106 VRETRY_L PMC1_IO5 GND 4 GND PMC1 108 VA24 PMC1 107 E1 2 5 5 1 5 1 1010 VA25 PMC1 109 E1 2 6 GND PMC1 1012 VA26 PMC1 1011 GND 7 SPIRTS PMC1 1014 VA27 PMC1 1013 NC 8 GND PMC1 1016 VA28 PMC1 1015 NC 9 SP2RX 1 1018 VA29 PMC1 1017 GND 10 GND PMC1 1020 VA30 PMCI 1019 NC 11 SP2TX PMC1 1022 1 PMC1 1021 NC 12 GND PMC1 1024 GND PMC1 1023 GND 13 SP2CTS PMC1 1026 5V PMC1 1025 I2C SDA 14 GND PMC1 1028 VD16 PMC1 1027 I2C SCL 15 SP2RTS PMC1_IO30 VD17 PMC1 1029 E1 LINK 16 GND PMC1 1032 VD18 PMC1 1031 E1 ACT 17 SP3RX PMC1 1034 VD19 PMC1 1033 E2 LINK 18 GND PMC1 1036 VD20 PMC1 1035 E2 ACT 19 SP3TX 1 1038 VD21 1 1037 GND 20 GND PMC1 1040 VD22 PMC1_IO39 E2 4 21 SP3CTS PMC1 1042 VD23 PMC1 1041 E2 4 22 GND PMC1 1044 GND PMC1 1043 GND Pin Assignments Table 5 12 VME P2 Connector Pinouts continued Pin P2 Z P2 A P2 B P2 C P2 D 23 SP3RTS PMC1 1046 VD24 PMC1 1045 E2 3 24 GND PMC1 1048 VD25 PMC1 1047 E2 3 25 SPARX PMC1_IO50 VD26 PMC1_IO49 GND 26 GND PMC1 1052 VD27 PMC1_IO51 E2 2 27 SPATX PMC1 1054 VD28 PMC1 1053 E2 2 28 GND PMC1 1056 VD29 PMC1 1055 GND 29 SPACTS PMC1_IO58 VD30 PMC1_IO57 E2 1 30 GND PMC1_IO60 VD31 PMC1_IO59 E2 1 31 SPARTS PMC1 1062 GND PMC1 1061 GND 32 GND PMC1 1064 5V PMC1 1063 5V 5 2 7 MVME721 PMC I O Module PIM Co
39. CPU HRST KEY no pin 14 15 CPU CKSTPO L GND 16 Pin 6 3 3V has a resettable fuse and can supply up to 0 5A to power I O buffers in the COP controller 104 MVME3100 Single Board Computer Installation and Use 6806800M28C 2 5 Chapter 6 6 1 6 1 1 Table 6 1 Default Processor Address Map Memory Maps Default Processor Memory Map The MPC8540 presents a default processor memory map following RESET negation The following table shows the default memory map from the point of view of the processor The e500 core only provides one default TLB entry to access boot code and it allows for accesses within the highest 4KB of memory To access the full 8MB of default boot space and the 1 of CCSR space additional TLB entries must be set up within the e500 core for mapping these regions Refer to the MPC8540 Reference Manual listed in Appendix B Related Documentation for details This is the default location for the CCSRs but it is not mapped after reset Processor Address Start End Size Definition Notes 0000 0000 FF6F FFFF 4087M Not mapped FF70 0000 FF7F FFFF 1M MPC8540 CCS Registers 1 FF80 0000 FFFF FFFF 8M Flash 2 Only FFFF F000 to FFFF FFFF is mapped after reset The e500 core fetches the first instruction from FFFF FFFC following a reset MVME3100 Single Board Computer Installation and Use 6806800M28C 105 Memory Maps 6 1 2 MOT
40. D ER aa en 119 6 1 16 4 Counter Reglsters see na 120 6 1 17 Geographical Address 120 7 Programming Detalls an needa E PIA e VIN rel t RING GR TS NR E 121 7 1 Introduction seeker a nn 121 7 2 8540 Reset Configuration 0 cece ccc cnet e rn 122 7 3 MPC8540 Interrupt Controller 0 cece ec ccc cece eee mme 127 7 4 Local Bus Controller Chip Select Assignments 128 7 5 Two Wire Serial Interface ccc nen n eee n nee e nee e mem enn 128 7 6 User Configuration EEPROM 0 cece cece cece teen he een tent eee een 129 3 VPDEEPROM 2 3 nen een Rca Sara s ee ee pa hc en seas 130 7 8 RIMVPDEEPROM titt teni xe en nn ee 130 7 9 Ethernet PHY Address ana a ea nen 130 FAO Flash e rette diem ee ee eier 131 7 11 PGIIDSEL Definition u cee as en es en RR 132 7 12 PCI Arbitration Assignments 134 7 13 Clock Distribution odes 134 7 14 8540 Real Time Clock Input n 136 7 15 MPC8540 LBC Clock Divisor 2 cece HI 136 A Specifications ass 137 Power Requirements awvuvvvvrannvnunnvvnvanvvvuannvuuannvuannnnuunnenunanennn 137 6 MVME3100 Single Board Computer Installation and Use 6806800M28C Contents A 2 Environme
41. D08 3 3V 50 51 ADO7 REQ1B 52 53 3 3V GNTIB 54 55 Not Used GND 56 57 Not Used EREADYO 58 59 GND Not Used 60 61 ACK64 3 3V 62 63 GND No Connect MONARCH 64 Table 5 5 PMC Slot 1 Connector 13 Pin Assignments Pin Signal Signal Pin 1 Reserved GND 2 3 GND C BE7 4 5 C BEGH C BE5 6 7 C BE4 GND 8 9 3 3V VIO PAR64 10 11 AD63 AD62 12 13 AD61 GND 14 15 GND AD60 16 17 AD59 AD58 18 19 AD57 GND 20 21 3 3V VIO AD56 22 23 AD55 AD54 24 25 AD53 GND 26 27 GND AD52 28 90 MVME3100 Single Board Computer Installation and Use 6806800M28C Pin Assignments Table 5 5 PMC Slot 1 Connector J13 Pin Assignments continued Pin Signal Signal Pin 29 AD51 AD50 30 31 AD49 GND 32 33 GND AD48 34 35 AD47 AD46 36 37 AD45 GND 38 39 3 3V VIO AD44 40 41 AD43 AD42 42 43 AD41 GND 44 45 GND AD40 46 47 AD39 AD38 48 49 AD37 GND 50 51 GND AD36 52 53 AD35 AD34 54 55 AD33 GND 56 57 3 3V VIO AD32 58 59 Reserved Reserved 60 61 Reserved GND 62 63 GND Reserved 64 Table 5 6 PMC Slot 1 Connector J14 Pin Assignments Pin Signal Signal Pin 1 PMC1_1 P2 C1 PMCI 2 P2 A1 2 3 PMC1_3 P2 C2 PMCI 4 P2 A2 4 5 5 P2 C3 PMCI 6 P2 A3 6 7 PMCI 7 P2 C4 PMCI 8 P2 A4 8 9 PMC1 9 P2 C5 PMC1 10 P2 A5 10 11 11 P2 C6 PMCI 12 P2 A6 12 MVME3100 Single Board Computer Installation and Use 68068
42. Dump Dump PCI Device Configuration Header Register pciShow Display PCI Device Configuration Header Register pciSpace Display PCI Device Address Space Allocation ping Ping Network Host portSet Port Set portShow Display Port Device Configuration Data rd User Program Register Display reset Reset System rs User Program Register Set set Set Date and Time sromRead SROM Read sromWrite SROM Write sta Symbol Table Attach stl Symbol Table Lookup stop Stop Date and Time Power Save Mode taskActive Display the Contents of the Active Task Table tc Trace Single Step User Program td Trace Single Step User Program to Address 46 MVME3100 Single Board Computer Installation and Use 6806800M28C MOTLoad Firmware Table 3 1 MOTLoad Commands continued Command Description testDisk Test Disk testEnetPtP Ethernet Point to Point testNvramRd NVRAM Read testNvramRdWr NVRAM Read Write Destructive testRam RAM Test Directory testRamAddr RAM Addressing testRamAlt RAM Alternating testRamBitToggle RAM Bit Toggle testRamBounce RAM Bounce testRamCodeCopy RAM Code Copy and Execute testRamEccMonitor Monitor for ECC Errors testRamMarch RAM March testRamPatterns RAM Patterns testRamPerm RAM Permutations testRamQuick RAM Quick testRamRandom RAM Random Data Patterns testRtcAlarm RTC Alarm testRtcReset RTC Reset testRtcRollOver RTC Rollover testRtcTick RTC Tick
43. E Embedded Computing for Business Critical Continuity MVME3100 Single Board Computer Installation and Use P N 6806800M28C December 2012 EMERSON Network Power 9 2011 Emerson All rights reserved Trademarks Emerson Business Critical Continuity Emerson Network Power and the Emerson Network Power logo are trademarks and service marks of Emerson Electric Co 2008 Emerson Electric Co All other product or service names are the property of their respective owners Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries Java and all other Java based marks are trademarks or registered trademarks of Sun Microsystems Inc in the U S and other countries Microsoft Windows and Windows Me are registered trademarks of Microsoft Corporation and Windows XP is a trademark of Microsoft Corporation PICMG CompactPCI AdvancedTCA and the PICMG CompactPCI and AdvancedTCA logos are registered trademarks of the PCI Industrial Computer Manufacturers Group UNIX is a registered trademark of The Open Group in the United States and other countries Notice While reasonable efforts have been made to assure the accuracy of this document Emerson assumes no liability resulting from any omissions in this document or from the use of the information obtained therein Emerson reserves the right to revise this document and to make changes from ti
44. F0000 Translation Offset Upper Register 00000000 00000000 MVME3100 Single Board Computer Installation and Use 6806800M28C MOTLoad Firmware Inbound window 0 is not enabled Virtual FIFO at 256 bytes 2eSST timing at 551320 respond to 2eSST 2eVME MBLT and BLT cycles A32 address space respond to Supervisor User Program and Data cycles Image maps from 0x00000000 to 0x1FFF0000 on the VMbus translates 1x1 to the PCI X bus thus 1x1 to local memory To enable this window set bit 31 of ITATO to 1 vg Forinbound Translations the Upper Translation Offset Register needs to be set to OxFFFFFFFF to Io ensure proper translations to the PCI X Local Bus MVME3100 gt vmeCfg s ol Displaying the selected Default VME Setting interpreted as Outbound Outbound Outbound Outbound Outbound Outbound Outbound Outbound MVME3100 Image Image Image Image Image Image Image Image 1 KR follows Attribute Register Starting Address Starting Address Ending Address Upper Ending Address Lower Translation Offset Upp 80001462 Upper Register 00000000 Lower Register 91000000 Register 00000000 Register AFFF0000 r 00000000 Translation Offset Low r Regist r 70000000 r Regist 2eSST Broadcast Select Register 00000000 Outbound window 1 OTAT 1 is enabled 2eSST timing at SST320 transfer mode of 2eSST A32
45. J10 J14 Planar sATA Power Connector J30 USB Connector J27 5 Connectors J28 and J29 The following headers are described in this chapter Boundary Scan Header J24 Processor COP Header J25 5 2 Connectors This section describes the pin assignments and signals for the connectors on the MVME3100 MVME3100 Single Board Computer Installation and Use 6806800M28C 83 Pin Assignments 5 2 1 PMC Expansion Connector One 114 pin Mictor connector with a center row of power and ground pins is used to provide PCI expansion capability The pin assignments for this connector are as follows Table 5 1 PMC Expansion Connector J4 Pin Assignments Pin Signal Signal Pin 1 3 3V GND 3 3V 2 3 PCICLK PMCINTA 4 5 GND PMCINTB 6 7 PURST PMCINTC 8 9 HRESET PMCINTD 10 11 TDO TDI 12 13 TMS TCK 14 15 TRST PEP 16 17 PCIXGNT PCIXREQ 18 19 12V 12V 20 21 PERR SERR 22 23 LOCK No Connect 24 25 DEVSEL No Connect 26 27 GND PCI XCAP 28 29 TRDY IRDY 30 31 STOP FRAME 32 33 GND M66EN 34 35 ACK64 No Connect 36 37 REQ64 No Connect 38 84 MVME3100 Single Board Computer Installation and Use 6806800M28C Pin Assignments Table 5 1 PMC Expansion Connector J4 Pin Assignments continued
46. LED set condition illuminates the LED and cleared condition extinguishes the LED USR3 LED User LED 3 This bit controls the planar USR3 LED set condition illuminates the LED and a cleared condition extinguishes the LED RSVD Reserved for future implementation MVME3100 Single Board Computer Installation and Use 6806800M28C 111 Memory Maps Flash Control Status Register The MVME3100 provides software controlled bank write protect and map select functions as well as boot block select bank write protect and activity status for the Flash Table 6 7 Flash Control Status Register REG BIT Flash Control Status Register 2000003 N a AR N FIELD MAP SEL F WP SW OPER 7 FLASH RDY 2 2 RESET x FBT_BLK_SEL RSVD RSVD RSVD x HW 112 FLASH_RDY Flash ready This bit provides the current state of the Flash devices Ready Busy pins These open drain output pins from each Flash device are wire OR d to form Flash Ready FBT_BLK_SEL Flash boot block select This bit reflects the current state of the BOOT BLOCK B SELECT switch A cleared condition indicates that boot block A is selected and mapped to the highest address A set condition indicates that boot block B is selected and mapped to the highest address F_WP_HW Hardware Flash bank write protect swit
47. LK BG3IN SYSFAIL 10 11 Reserved GND BG3OUT L 11 12 GND 051 BRO SYSRESET Reserved 12 13 Reserved 050 BR1 LWORD GA2_L 13 14 GND WRITE BR2 AM5 Reserved 14 15 Reserved GND BR3 A23 GA3_L 15 16 GND DTACK AMO A22 Reserved 16 17 Reserved GND AM1 A21 GA4_L 17 18 GND 5 2 20 Reserved 18 19 Reserved GND AM3 A19 Reserved 19 20 GND LACK GND A18 Reserved 20 21 Reserved IACKIN SERA 17 Reserved 21 22 GND IACKOUT SERB A16 Reserved 22 23 Reserved AMA GND A15 Reserved 23 24 GND A07 IRQ7 A14 Reserved 24 25 Reserved A06 IRQ6 A13 Reserved 25 26 GND 05 IRQ5 12 Reserved 26 27 Reserved A04 IRQ4 11 Reserved 27 28 GND A03 IRQ3 A10 Reserved 28 29 Reserved A02 IRQ2 09 Reserved 29 30 GND A01 IRQ1 A08 Reserved 30 31 Reserved 12V 5VSTDBY 12V GND 31 32 GND 5V 5V 5V 5V 32 98 MVME3100 Single Board Computer Installation and Use 6806800M28C 5 2 6 Pin Assignments VMEbus P2 Connector The VME P2 connector is a 160 pin DIN Row B of the P2 connector provides power to the MVME3100 and to the upper eight VMEbus address lines and additional 16 VMEbus data lines The pin assignments for the P2 connector are the same for both the MVME3100 and MVME721 and are as follows Table 5 12 VME P2 Connector Pinouts MVME3100 Single Board Computer Installation and Use 6806800M28C Pin P2 Z P2 A P2 B P2
48. Load s Processor Memory MOTLoad s processor memory map is given in the following table Table 6 2 MOTLoad s Processor Address Map Processor Address Start End Size Definition Notes 0000 0000 top dram 1 dram size System Memory on board DRAM 2GB max 8000 0000 DFFF FFFF 1 5GB PCI Memory Space VME E000 0000 EOFF FFFF 16MB PCI I O Space 100 0000 E10F FFFF 1MB MPC8540 CCSR E1100 0000 E1FF FFFF 15MB Not Used E200 0000 E2FF FFFF 16MB Status Control Registers UARTs External Timers E300 0000 EFFF FFFF 208MB Not Used F000 0000 F7FF FFFF 128MB Reserved 12 bottom flash FFFF FFFF flash_size Flash 128MB max 1 Reserved for future larger flash devices 2 The flash is ligically one back but may be physically implemented in two banks After RESET the MPC8540 does not map any PCI memory space inbound or outbound and does not respond to Config cycles 6 1 3 VMEMemory The MVME3100 is fully capable of supporting both the PReP and the CHRP VME Memory Map examples with RAM size limited to 2GB 106 MVME3100 Single Board Computer Installation and Use 6806800M28C 6 1 4 Memory Maps System 1 0 Memory System resources including System Control and Status registers external timers and the QUART are mapped into 16MB address range from the MVME3 100 via the MPC8540 local bus controller LBC The memory map is defined in the following table including t
49. M28C 69 Functional Description Table 4 1 MVME3100 Features Summary continued Feature Description PCI Interface Bus A 66 MHz PCI X mode One TSi148 VMEbus controller One serial ATA SATA controller One MPC8540 Two PCI6520 PCI X to PCI X bridges primary side Bus B 33 66 100 MHz PCI PCI X PCI 2 2 and PCI X 1 0b compliant Two 3 3V 5V selectable 64 bit single wide PMC sites or one double wide PMC site PrPMC ANSI VITA 32 2003 and PCI X Auxiliary ANSI VITA 39 2003 compliant One PCI6520 PCI X to PCI X bridge secondary side Bus C 1263 version 33 MHz PCI PCI 2 2 compliant One USB 2 0 controller One PCI expansion connector for interface to PMCspan One PCI6520 PCI X to PCI X bridge secondary side I O One front panel RJ45 connector with integrated LEDs for front I O one serial channel One front panel RJ45 connector with integrated LEDs for front I O one 10 100 1000 Ethernet channel One front panel external sATA data connector for front 1 0 one SATA channel One front panel USB Type A upright receptacle for front I O one USB 2 0 channel 1263 version PMC site 1 front I O and rear P2 I O PMC site 2 front I O Serial ATA One four channel sATA controller one channel for front panel I O one channel for planar I O one channel for future rear PO I O and one channel is not used One planar data connector and one planar power connecto
50. ME721 rear transition module RTM Front panel connectors on the MVME3100 board include one RJ 45 connector for the Gigabit Ethernet one RJ 45 connector for the asynchronous serial port one USB port with one type A connector one sATA port with one external sATA connector and a combined reset and abort switch Rear panel connectors on the MVME721 board include one RJ 45 connector for each of the 10 100 and 10 100 1000 BaseT Ethernets and four RJ 45 connectors for the asynchronous serial ports The RTM also provides two planar connectors for one PIM with rear I O Getting Started This section provides an overview of the steps necessary to install and power up the MVME3100 and a brief section on unpacking and ESD precautions Overview of Startup Procedures The following table lists the things you will need to do before you can use this board and tells where to find the information you need to perform each step Be sure to read this entire chapter including all Caution and Warning notes before you begin Table 1 1 Startup Overview What you need to do Refer to Unpack the hardware Unpacking Guidelines on page 22 Identify various components on the board MVME3100 Layout on page 23 Install the MVME3100 board in a chassis on page 30 MVME3100 Single Board Computer Installation and Use 6806800M28C 21 Hardware Preparation and Installation Table 1 1 Startup Overview continued What
51. MVME3100 Single Board Computer Installation and Use 6806800M28C About this Manual Abbreviation Description DUART Dual Universal Asynchronous Receiver Transmitter ECC Error Correction Code ENET Ethernet ENV Environment ESD Electrostatic Discharge FAT File Allocation Table FEC Fast Ethernet Controller FIFO First In First Out FPU Floating Point Unit GA Geographic Address GENET Gigabit Ethernet GEV Global Environment Variable GMII Gigabit Media Independent Interface GPCM General Purpose Chip select Machine IBCA Inter Board Communication Address IDE Integrated Drive Electronics I O Input Output IEEE Institute of Electrical and Electronics Engineers LBC Local Bus Controller LED Light Emitting Diode MB Megabyte MBLT Multiplexed Block Transfer MHz Megahertz MIIM MII Management MMU Memory Management Unit MPU Memory Protection Unit Microprocessor Unit MTBF Mean Time Between Failure MVME3100 Single Board Computer Installation and Use 6806800M28C 15 About this Manual Abbreviation Description NVRAM Non Volatile RAM OS Operating System PAL Physical Abstraction Layer PCB Printed Circuit Board PCI Peripheral Connect Interface PCI X Peripheral Component Interconnect X PHY Physical Layer PIC Programmable Interrupt Controller PIM PCI Mezzanine Card Input Ou
52. N LEE TRE E ES PEE 107 System ControlRegister swunnnvvnvnanenenenenenenunnanenenenenenenen 108 System Indicator Register un u ee VE 109 Flash Control Status Register II 110 PCIB s Status Register u rete ee hr RR sn 111 PCI Bus Status Register 111 PCI Bus Status Register 0 eee cece 113 Interrupt Detect Register sus seen 114 Presence Detect Register sine nn ae 114 PED Revision Register innri san 115 PLD Data Code Register 116 TesEReglstet T eee eee ee reset e ae tp bas 116 NESE 20 inc o DE der 117 Prescalar Register eR abe ew eds E da 117 Tick Timer Control Registers aaanavnnuunauvnanvnannnaennaeunnenanennee 118 Tick Timer Compare Registers 119 Tick Timer Counter Registers essesleesseeeeeeee 120 MPC8540 Power on Reset Configuration Settings 122 MPC8540 Interrupt Controller 0 0 2 cece cece eee eee I 127 LBC Chip Select Assignments 128 I2C Bus Device Addressing 0 0 0 cee cece cece eee n een n 128 PHY Types and Management Bus Addresses 130 Flash Options ae ees deeded aaa 131 IDSEL and Interru
53. OPER R W RESET E7 MVME3100 Single Board Computer Installation and Use 6806800M28C 119 Memory Maps Prescalar Adjust The prescaler adjust value is determined by the following formula Prescaler adjust 256 CLKIN CLKOUT where CLKIN is the input clock source in MHz and CLKOUT is the desired output clock reference in MHz 6 1 16 2 Control Registers The prescaler provides the clock required by each of the four timers The tick timers require 1 MHz clock input The input clock to the prescaler is 25 MHz The default value is set for E7 which gives a I MHz reference clock for a 25 MHz input clock source Table 6 18 Tick Timer Control Registers Tick Timer 1 Control Register 0xE2020010 32 bits Tick Timer 2 Control Register 0xE2020020 32 bits Tick Timer 3 Control Register 0xE2020030 32 bits REG Tick Timer 4 Control Register 0 2020040 32 bits BIT 31 11 10 9 8 7 6 5 4 3 2 1 0 FIELD a a E m LL gt gt 0 u S Ju 2 2 5 2 8 18 R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 ENG Enable counter When this bit is high the counter increments When this bit is low the counter does not increment Clear counter on compare When this bit is high the counter is reset to 0 when it compares with the compare register When this bit is low the counter is not reset COVF Clear overflow bits The overf
54. Option Setting Description State of Bit vs Function TSEC2_ Resistors 11 Local Bus Output Hold 00 0 added buffer delays 0 TXD 6 5 Configuration added buffer delays for LALE 01 3 added buffer delays 1 added buffer delay for LALE 10 2 added buffer delays 1 added buffer delay for LALE 1 added buffer delay 0 added buffer delays for LALE TSEC2_ Fixed 000 RapidlO Device ID 3 000 Unconnected Inputs TXD 2 4 lower order bits LA27 Resistor 1 CPU Boot 0 CPU boot hold off mode 500 core boots without waiting for configuration by an external master LA 28 31 PLD logic 0011 for CCB Clock Ratio 0000 16 1 100 MHz Clock SYSCLK _ PCI bus 0010 2 1 0011 3 1 0101 for 66 MHz 0100 4 1 0110 6 1 1000 8 1 1001 9 1 1010 10 1 1100 12 1 126 MVME3100 Single Board Computer Installation and Use 6806800M28C Programming Details Table 7 1 MPC8540 Power on Reset Configuration Settings continued MPC8540 Signal Select Option ae Description State of Bit vs Function LWE 0 1 _L4 Resistors 11 PCI Output Hold 00 1 added buffer delay configuration 01 0 added buffer delays 10 3 added buffer delays 11 2 added buffer delays 11 PCI X Output Hold 00 3 added buffer delays 01 2 added buffer delays 10 1 added buffer delay LWE 2 3 _L Resistors 11 MPC8540 Host Agent 00 Agent of RapidlO and Configuration PCI PCI X 01 Agent
55. PMC1P PMC module 1 present If cleared there is PMC module installed in site 1 If set the PMC module is installed PMC2P PMC module 2 present If cleared there is no PMC module installed in site 2 If set the PMC module is installed PEP PMCspan present If cleared there is no PMCspan module installed If set the PMCspan module is installed RSVD Reserved for future implementation PLD Revision Register The MVME3100 provides a PLD Revision register that may be read by the system software to determine the current revision of the timers registers PLD Table 6 13 PLD Revision Register REG PLD Revision Register 2000009 BIT 7 6 5 4 3 2 1 0 FIELD PLD_REV OPER R RESET 01 PLD REV 8 bit field containing the current timer register PLD revision The revision number starts with 01 MVME3100 Single Board Computer Installation and Use 6806800M28C 117 Memory Maps 95 6 1 13 PLD Data Code Register The MVME3100 PLD provides a 32 bit register that contains the build date code of the timers registers PLD Table 6 14 PLD Data Code Register REG PLD Data Code Register 200000 BIT FIELD OPER R W RESET XXXX yy Last two digits of the year mm Month dd Day vv Version 6 1 14 Test Register 1 The MVME3100 provides a 32 bit general purpose read write register that can be used by software for PLD test or general status bit storage T
56. Power JJ Power Switching amp Control Site Monitoring BI DC Power Systems Integrated Cabinet Solutions Precision Cooling I Surge amp Signal Protection Emerson Business Critical Continuity Emerson Network Power and the Emerson Network Power logo are trademarks and service marks of Emerson Electric Co All other product or service names are the property of their respective owners O 2011 Emerson Electric Co
57. SPA which are routed to the P2 connector Refer to the ST16C554D Datasheet listed in Appendix B Related Documentation for additional details and or programming information PCI PCI X Interfaces and Devices The MVME3100 provides three separate PCI PCI X bus segments Bus segment A operates in 66MHz PCI X mode andis connected to the MPC8540 the Tsi148 VME controller the serial ATA 5 controller and two PCI X to PCI X bridges Bus segment B is bridged between bus A and the two PMC sites and operates in 33 66 MHz PCI or 66 100 MHz PCI X mode depending on the slowest speed PMC installed Bus segment C is bridged between bus A the USB controller and the PMCspan connector Bus C operates at 33 MHz PCI mode MPC8540 PCI X Interface The MPC8540 PCI X controller is configured to operate in PCI X mode only host bridge mode Bus A mode switch must be in OFF position in order to be fixed in PCI X mode The mode cannot be changed by software Refer to the MPC8540 Reference Manual listed in Appendix B Related Documentation for additional details and or programming information MVME3100 Single Board Computer Installation and Use 6806800M28C 77 Functional Description 4 10 2 4 10 3 4 10 4 151148 VME Controller The VMEbus interface for the MVME3100 is provided by the TSi148 ASIC The TSi148 provides the required VME VME extensions and 2eSST functions Transceivers are used to buffer the VME signals between the TSi148 and
58. Serial Interface on page 130 User Configuration EEPROM on page 131 VPD EEPROM on page 132 RTM VPD EEPROM on page 132 Ethernet PHY Address on page 132 Flash Memory on page 133 PCIIDSEL Definition on page 134 PCI Arbitration Assignments on page 136 Clock Distribution on page 136 MPC8540 Real Time Clock Input on page 138 MPC8540 LBC Clock Divisor on page 138 MVME3100 Single Board Computer Installation and Use 6806800M28C 123 Programming Details eee 7 2 8540 Reset Configuration The MVME3100 supports the power on reset POR pin sampling method for MPC8540 reset configuration The states ofthe various configuration pins on the MPC8540 are sampled when reset is de asserted to determine the desired operating modes The following table describes the configuration options and the corresponding default setting Refer to the MPC8540 Reference Manual listed in Appendix Related Documentation for additional details and or programming information Table 7 1 MPC8540 Power on Reset Configuration Settings Default MPC8540 Signal Select Option Setting Description State of Bit vs Function PCI REQ64 L PLD logic 0 PCI 32 Configuration 0 PCI PCI X interface is 64 bit 1 PCI PCI X interface is 32 bit PCI_GNTI_L Resistor 0 PCI Interface I O o 25 ohmadrivers 1 42 ohm drivers PCI GNT2 L Resistor 1 PCI Arbiter 0 Disabled on chip PCI PCI Configuration X arbiter 1 Enab
59. VME3100 gt te te ambiguous MVME3100 gt MVME3100 Single Board Computer Installation and Use 6806800M28C 49 MOTLoad Firmware 3 4 1 3 4 2 Command Line Rules There are few things to remember when entering MOTLoad command Multiple commands are permitted on single command line provided they are separated by single semicolon Spaces separate the various fields on the command line command arguments options The argument option identifier character is always preceded by a hyphen character Options are identified by single character Option arguments immediately follow no spaces the option Allcommands command options and device tree strings are case sensitive Example MVME3100 flashProgram d dev flash0 n00100000 For more information on MOTLoad operation and function refer to the MOTLoad Firmware Package User s Manual Command Line Help Each MOTLoad firmware package has an extensive product specific help facility that can be accessed through the he1p command The user can enter help at the MOTLoad command line to display a complete listing of all available tests and utilities Example MVME3100 help For help with a specific test or utility the user can enter the following at the MOTLoad prompt help command name The help command also supports a limited form of pattern matching Refer to the help command page Example MVME3100 help testRa
60. a com Publication Number 80A3020 1 02 54215 10 100 1000BASE T Gigabit Transceiver Broadcom Corporation Web Site www broadcom com BCM5421 52215 10 100BASE Tx Single Channel Signi PHY Transceiver Broadcom Corporation Web Site www broadcom com BCM5221 Sil3214A SATALink 4 Port PCI or PCI X Host Controller Datasheet Silicon Image Corporation Web Site http www siliconimage com docs Sil DS 0160 C pdf Sil DS 0160 C pdf S29GLxxxN MirrorBit Flash Family S29GL512N S29GL256N S29GL128N AMD Inc Web Site www amd com us en FlashMemory 27631 Revision A Amendment 3 May 13 2004 mPD720101 USB 2 0 Host Controller Datasheet NEC Electronics Web Site www necel com usb en document index html 16265EJ3V0DS00 April 2003 PCI6520CB Data Book PLX Technology Inc 870 Maude Avenue Sunnyvale CA 94085 Web Site www plxtech com EXAR ST16C554 554D ST68C554 Quad UART with 16 Byte FIFOs EXAR Corporation 48720 Kato Road Fremont CA 94538 Web Site www exar com 5116 554 5540 Rev 3 1 0 144 MVME3100 Single Board Computer Installation and Use 6806800M28C Related Documentation Table B 2 Manufacturers Documents continued Document Title and Source Publication Number 2 Wire Serial EEPROM AT24C512 Atmel Corporation San Jose CA Web Site www atmel com atmel support Maxim DS1621 Digital Thermometer and Thermostat DS1621 Maxim Integrate
61. able 6 15 Test Register 1 REG Test Register 1 0xE2000010 BIT 31 0 FIELD TESTI OPER R W RESET 0000 TEST1 General purpose 32 bit read write field 118 MVME3100 Single Board Computer Installation and Use 6806800M28C 5 6 1 15 Test Register 2 The MVME3100 provides a second 32 bit test register that reads back the complement of the data in test register 1 Table 6 16 Test Register 2 REG Test Register 2 2000014 BIT 31 0 FIELD TEST2 OPER R W RESET FFFF TEST2 Aread from this address returns the complement of the data pattern in test register 1 A write to this address writes the uncomplemented data to register TEST1 6 1 16 External Timer Registers The MVME3100 provides a set of tick timer registers for access to the four external timers implemented in the timers registers PLD These registers are 32 bit registers and are not byte writable The following sections describe the external timer prescaler and control registers 6 1 16 1 Prescalar Register The prescaler provides the clock required by each of the four timers The tick timers require a 1 MHz clock input The input clock to the prescaler is 25 MHz The default value is set for E7 which gives a I MHz reference clock for a 25 MHz input clock source Table 6 17 Prescalar Register REG Prescalar Register 0xE2020000 8 bits of 32 BIT 7 6 5 4 3 2 1 0 FIELD Prescalar Adjust
62. al details MVME3100 Single Board Computer Installation and Use 6806800 28 131 Programming Details 1 7 7 8 7 9 VPD The MVME3100 board provides 8KB dual address serial EEPROM containing vital product data VPD configuration information specific to the MVME3100 Typical information that may be present in the EEPROM may include manufacturer board revision build version date of assembly memory present options present L2 cache information etc The VPD EEPROM is hardwired to have device ID as shown in Table 7 4 on page 130 Refer to the 2 Wire Serial EEPROM Datasheet listed in Appendix Related Documentation for additional details RTM VPD EEPROM The MVME3100 board provides an 8KB dual address serial EEPROM containing VPD configuration information specific to the MVME3100 RTM Typical information that may be present in the EEPROM may include manufacturer board revision build version date of assembly options present etc The RTM VPD EEPROM device ID is user selectable with the recommended value for MVME3100 as shown in Table 7 4 on page 130 Refer to the2 Wire Serial EEPROM Datasheet listed in Appendix B Related Documentation for additional details Ethernet PHY Address The assigned Ethernet PHY addresses on the MPC8540 management MIIM bus is shown in the following table Table 7 5 PHY Types and Management Bus Addresses MPC8540 PHY MIIM Addres
63. ar fashion Beyond that MOTLoad utilities and MOTLoad tests are distinctly different Utilities The definition ofa MOTLoad utility application is very broad Simply stated it is considered a MOTLoad command if it is not aMOTLoad test Typically MOTLoad utility applications are applications that aid the user in some way that is they do something useful From the perspective of MOTLoad examples of utility applications are configuration data status displays data manipulation help routines data status monitors etc MVME3100 Single Board Computer Installation and Use 6806800M28C 41 MOTLoad Firmware 3 3 2 42 Operationally MOTLoad utility applications differ from MOTLoad test applications in several ways Only one utility application operates at any given time that is multiple utility applications cannot executing concurrently Utility applications may interact with the user Most test applications do not Tests MOTLoad test application determines whether or not the hardware meets a given standard Test applications are validation tests Validation is conformance to a specification Most MOTLoad tests are designed to directly validate the functionality of a specific SBC subsystem or component These tests validate the operation of such SBC modules as dynamic memory external cache NVRAM real time clock etc All MOTLoad tests are designed to validate functionality with minimum user interaction
64. ary Scan Header 24 101 5 3 2 Processor COP Header J25 cece cece eect een cent cents nennen 102 6 Memory Maps ss 103 61 Memory ee haken 103 6 1 1 Default Processor Memory 0 0 103 6 1 2 MOTLoad s Processor Memory 104 6 1 3 VMEMemory Map socer ea am 104 6 1 4 System I O Memory Map eee cece III me 105 6 1 5 System Status Register u nennen Shen 107 6 1 6 System Control Register ee nec mnn 108 6 1 7 System Indicator Register 2 0 eee cece eee een eee 109 MVME3100 Single Board Computer Installation and Use 6806800M28C Contents 6 1 8 Flash Control Status Register 110 6 1 9 PCI Bus Status Registers ossei igers nessen ened E eere ee nee 111 6 1 10 Interrupt Detect Register gt ccc n 114 6 1 11 Presence Detect Register cet een nn 114 6 1 12 PLD Revision Register 0 cece cece ener III 115 6 1 13 PLD Data Code Register 0 6 cece cece cence nent sn 116 6 1 14 Test Register nn en needed 116 6 1 15 Test Register 2 2 0000 nk 117 6 1 16 External Timer Registers 0 cece eee eee se 117 6 1 16 1 Prescalar Register u een ea 117 6 1 16 2 Control Registers cece cece 118 6 1 16 3 Compare Registe si eee ee P
65. aster is enabled MVME3100 gt vmeCfg s r234 Displaying the selected Default VME Setting interpreted as follows VMEbus Master Control Register 00000003 MVME3100 MVME3100 Single Board Computer Installation and Use 6806800M28C 51 Firmware The VMEbus Master Control Register is set to the default RESET condition MVME3100 gt vmeCfg s r238 Displaying the selected Default VME interpreted VMEbus Control Register MVME3100 gt as follows 00000008 Setting The VMEbus Control Register is set to Global Timeout of 2048 useconds MVME3100 gt vmeCfg s r414 Displaying the selected Default VME Setting interpreted as follows CRG Attribute Register 00000000 CRG Base Address Upper Register 00000000 CRG Base Address Lower Register 00000000 MVME3100 gt The CRG Attribute Register is set to the default RESET condition MVME3100 gt vmeCfg s i0 Displaying the selected Default VME interpreted Inbound Image Inbound Image Inbound Image Inbound Image Inbound Image Inbound Image Inbound Image MVME3100 gt 52 as follows Attribute Register Starting Address Upp Starting Address Low Ending Address Upper Ending Address Lower Translation Offset Lower Register Setting 000227AF r Register 00000000 r Register 00000000 Register 00000000 Register 1FF
66. ay be used to determine the state of the abort switch A cleared condition indicates the abort switch is not depressed while a set condition indicates the abort switch is asserted SAFE START ENV safe start This bit reflects the current state of the ENV safe start select switch A set condition indicates that firmware should use the safe ENV settings A cleared condition indicates that the ENV settings programmed in NVRAM should be used by the firmware RSVD Reserved for future implementation MVME3100 Single Board Computer Installation and Use 6806800M28C 109 Memory Maps 6 1 6 System Control Register The MVME3100 board System Control register provides board control bits Table 6 5 System Control Register System Control Register 0xE2000001 0 FIELD 5 2 a a a 3 OPER R W R R R R W R W RESET 0 0 0 0 0 x 1 1 TSTAT_MASK Thermostat mask This bit masks the 051621 temperature sensor thermostat output Ifthis bit is cleared the thermostat output is enabled to generate an interrupt Ifthe bit is set the thermostat output is disabled from generating an interrupt EEPROM_WPEEPROM Write protect This bit provides protection against inadvertent writes to the on board EEPROM devices Clearing this bit will enable writes to the EEPROM devices Setting this bit write protects the devices The devices are write protected following a reset BRD_RST Board reset These bits force a har
67. ch status This bit reflects the current state of the FLASH BANK WP switch A set condition indicates that the entire Flash bank is write protected A cleared condition indicates that the Flash bank is not write protected F_WP_SW Software Flash bank write protect This bit provides software controlled protection against inadvertent writes to the Flash memory devices A set condition indicates that the entire Flash is write protected A cleared condition indicates that the Flash bank is not write protected only when the hardware write protect bit is also not set This bit is set during reset and must be cleared by the system software to enable writing of the Flash devices MAP_SEL Memory map select When this bit is cleared the Flash memory map is controlled by the Flash Boot Block Select switch When the map select bit is set boot block A is selected and mapped to the highest address MVME3100 Single Board Computer Installation and Use 6806800M28C 6 1 8 Memory Maps 6 1 9 RSVD Reserved for future implementation PCI Bus Status Registers The PCI Bus Status registers provide PCI bus configuration information for each of the PCI buses Table 6 8 PCI Bus A Status Register PCI Bus Status Register 2000004 3 FIELD ca a amp I lt I a a a lt lt a a e X ce ce X a a a OPER R R R R R R R R RESET 0 0 0 0 1 x 0 1 PCI_A_SPD
68. com 54615 PHY is used for each TSEC interface and each TSEC interface and PHY is configured to operate in GMII mode One Gigabit Ethernet interface is routed to a front panel RJ 45 connector with integrated LEDs for speed and activity indication The other Gigabit Ethernet interface is routed to P2 for rear I O MVME3100 Single Board Computer Installation and Use 6806800M28C Functional Description 4 9 4 10 4 10 1 Broadcom BCM5221 PHY is used for the FEC interface The Fast Ethernet interface is routed to P2 forrear I O Isolation transformers are provided on board for each interface The assigned PHY addresses for the MPC8540 management MIIM interface can be found in the MVME3100 Single Board Computer Programmer s Reference Guide listed in Appendix Related Documentation Each Ethernet interface is assigned an Ethernet Station Address The address is unique for each device The Ethernet Station Addresses are displayed on labels attached to the PMC front panel keep out area Asynchronous Serial Ports TheMVME3100 board contains one front access asynchronous serial port interface using serial port 0 from the MPC8540 dual UART DUART device This serial port is routed to the RJ 45 front panel connector This board also contains one quad UART QUART device connected to the MPC8540 device controller bus to provide additional asynchronous serial ports The QUART provides four asynchronous serial ports SP1
69. connector 128 Front panel sATA connector J29 Planar sATA connector J30 Planar sATA power connector J41B 10 100 1000Mb s Ethernet connector COM port connector P1 P2 VME backplane connectors Table 1 8 MVME721 Rear Transition Module Connectors Connector Function J1B 1 J1D COM port connectors 32 MVME3100 Single Board Computer Installation and Use 6806800M28C Hardware Preparation and Installation Table 1 8 MVME721 Rear Transition Module Connectors continued Connector Function J2A 10 100 1000Mb s Ethernet connector J2B 10 100Mb s Ethernet connector J10 PIM power ground J14 PIM I O P2 VME backplane connector 1 7 Completing the Installation Verify that hardware is installed and the power peripheral cables connected are appropriate for your system configuration Replace the chassis or system cover reconnect the system to the AC or DC power source and turn the equipment power on MVME3100 Single Board Computer Installation and Use 6806800M28C 33 Hardware Preparation and Installation 34 MVME3100 Single Board Computer Installation and Use 6806800M28C Chapter 2 Startup and Operation 2 1 2 2 2 3 Introduction This chapter gives you information about the Power up procedure Runtime switches and indicators Applying Power After you verify that all necessary hardware preparation is complete and all connec
70. d this bit is always set ERDY2 EREADY2 Indicates that the PrPMC module installed in PMC site 2 is ready for enumeration when set If cleared the module is not ready for enumeration If no is installed the bit is always set 5 0V_VIO 5 0V VIO Enabled This bit set indicates that the PMC bus PCI bus B is configured for 5 0V VIO 114 MVME3100 Single Board Computer Installation and Use 6806800M28C Memory Maps 3 3V VIO 3 3V enabled This bit set indicates that the PMC bus PCI bus B is configured to 3 3V VIO Table 6 10 PCI Bus C Status Register PCI Bus Status Register 0xE2000006 3 FIELD S a a a a 2 G ce o ce ce a a R R R R R R RESET X X X 0 1 X X X PCI C SPD PCI bus C speed Indicates the frequency of PCI bus C 00 33 MHz 01 66 MHz 10 100 MHz 11 133 MHz PCIX_C PCI X bus C A set condition indicates that bus C is operating in PCI X mode A cleared condition indicates PCI mode PCI_C_64B PCI bus C 64 bit A set condition indicates that bus C is enabled to operate in 64 bit mode A cleared condition indicates 32 bit mode RSVD Reserved for future implementation MVME3100 Single Board Computer Installation and Use 6806800M28C 115 Memory Maps 6 1 10 Interrupt Detect Register The MVME3100 provides an Interrupt Detect register that may be read by the system software to determine
71. d Products Web Site www maxim ic com Maxim DS1375 Serial Real Time Clock Rev 121203 Maxim Integrated Products Web Site www maxim ic com TSOP Type I Shielded Metal Cover SMT Yamaichi Electronics USA Web Site www yeu com B 3 Related Specifications For additional information refer to the following table for related specifications As an additional help a source for the listed document is provided Please note that while these sources have been verified the information is subject to change without notice Table B 3 Related Specifications Document Title and Source Publication Number VITA http www vita com VME64 Specification ANSI VITA 1 1994 VME64 Extensions ANSI VITA 1 1 1997 2eSST Source Synchronous Transfer VITA 2 0 2003 PCI Special Interest Group PCI SIG http www pcisig com Peripheral Component Interconnect PCI Local Bus Specification PCI Local Bus Revision 2 0 2 1 2 2 Specification PCI X Addendum to the PCI Local Bus Specification Rev 1 0b MVME3100 Single Board Computer Installation and Use 6806800M28C 145 Related Documentation Table B 3 Related Specifications continued Document Title and Source Publication Number IEEE http www ieee org IEEE Common Mezzanine Card Specification CMC Institute of Electrical and P1386 Draft 2 0 Electronics Engineers Inc IEEE PCI Mezzanine Card Specification PMC P1386 1 Draft 2 0 Institute
72. d creating a custom testSuite s The list of built in and user defined MOTLoad testSuites and their test contents can be obtained by entering testSuite dat the MOTLoad prompt All testSuites that are included as part of a product specific MOTLoad firmware package are product specific For more information refer to the test Suite command description page in the MOTLoad Firmware Package User s Manual Test results and test status are obtained through the test Status errorDisplay and taskActive commands Refer to the appropriate command description page in the MOTLoad Firmware Package User s Manual for more information Command List The following table provides a list of all current MOTLoad commands Products supported by MOTLoad may or may not employ the full command set Typing help at the MOTLoad command prompt will display all commands supported by MOTLoad for a given product Table 3 1 MOTLoad Commands Command Description as One Line Instruction Assembler bcb Block Compare Byte Halfword Word bch bcw bdTempShow Display Current Board Temperature bfb Block Fill Byte Halfword Word bfh bfw blkCp Block Copy blkFmt Block Format bIkRd Block Read blkShow Block Show Device Configuration Data blkVe Block Verify blkWr Block Write MVME3100 Single Board Computer Installation and Use 6806800M28C 43 MOTLoad Firmware Table 3 1 MOTLoad Commands continued
73. d environmental limits Make sure the product is completely dry and there is no moisture on any surface before applying power Environment Environmental Damage Improperly disposing of used products may harm the environment Always dispose of used products according to your country s legislation and manufacturer s instructions 150 MVME3100 Single Board Computer Installation and Use 6806800M28C Safety Notes MVME3100 Single Board Computer Installation and Use 6806800M28C 151 Sicherheitshinweise Dieses Kapitel enth lt Hinweise die potentiell gef hrlichen Prozeduren innerhalb dieses Handbuchs vorrangestellt sind Beachten Sie unbedingt in allen Phasen des Betriebs der Wartung und der Reparatur des Systems die Anweisungen die diesen Hinweisen enthalten sind Sie sollten au erdem alle anderen Vorsichtsma nahmen treffen die f r den Betrieb des Produktes innerhalb Ihrer Betriebsumgebung notwendig sind Wenn Sie diese Vorsichtsma nahmen oder Sicherheitshinweise die an anderer Stelle diese Handbuchs enthalten sind nicht beachten kann das Verletzungen oder Sch den am Produkt zur Folge haben Emerson ist darauf bedacht alle notwendigen Informationen zum Einbau und zum Umgang mit dem Produkt in diesem Handbuch bereit zu stellen Da es sich jedoch um ein komplexes Produkt mit vielf ltigen Einsatzm glichkeiten handelt k nnen wir die Vollst ndigkeit der im Handbuch enthaltenen Informationen nicht garantiere
74. d in electronics or electrical engineering are authorized to install remove or maintain the product The information given in this manual is meant to complete the knowledge of specialist and must not be used as replacement for qualified personnel Keep away from live circuits inside the equipment Operating personnel must not remove equipment covers Only factory authorized service personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Do not install substitute parts or perform any unauthorized modification of the equipment or the warranty may be voided Contact your local Emerson representative for service and repair to make sure that all safety features are maintained The blade has been tested in a standard Emerson system and found to comply with the limits for a Class A digital device in this system pursuant to part 15 of the FCC Rules EN 55022 Class Arespectively These limits are designed to provide reasonable protection against harmful interference when the system is operated in a commercial environment MVME3100 Single Board Computer Installation and Use 6806800M28C 148 Safety Notes This is Class product based on the standard of the Voluntary Control Council for Interference by Information Technology Interference VCCI If this equipment is used in domestic environment radio disturbance may arise When such trouble occur
75. d reset of the board If a pattern is written in bits 5 7 where bit 7 is set bit 6 is cleared and bit 5 is set 101 a hard reset is generated Any other pattern written in bits 5 7 does not generate a hard reset These bits are cleared automatically when the board reset has been completed These bits are always cleared during a read RSVD Reserved for future implementation 110 MVME3100 Single Board Computer Installation and Use 6806800M28C Memory Maps 6 1 7 System Indicator Register The MVME3100 board provides System Indicator register that may be read by the system software to determine the state of the on board status indicator LEDs or written to by system software to illuminate the corresponding on board LEDS Table 6 6 System Indicator Register REG System Indicator Register 0xE2000002 BIT 7 6 5 4 3 2 1 0 FIELD amp a a a a e N 1 2 2 2 n A 2 ce ce a 2 R R R R R W R W R W R W RESET 0 0 0 0 0 0 0 1 BRD FAIL Board fail This bit controls the board fail LED located on the front panel A set condition illuminates the front panel LED and cleared condition extinguishes the front panel LED USR1 LED User LED 1 This bit controls the USR1 LED located on the front panel A set condition illuminates the front panel LED and cleared condition extinguishes the front panel LED USR2 LED User LED 2 This bit controls the planar USR2
76. ditional devices or modules Before installing or removing additional devices or modules read the respective documentation Damage of Circuits Electrostatic discharge and incorrect installation and removal of the product can damage circuits or shorten their life Before touching the product make sure that your are working in an ESD safe environment or wear an ESD wrist strap or ESD shoes Hold the product by its edges and do not touch any components or circuits Product Malfunction Switches marked as Reserved might carry production related functions and can cause the product to malfunction if their setting is changed Donotchange settings of switches marked as reserved 30 MVME3100 Single Board Computer Installation and Use 6806800M28C Hardware Preparation and Installation Procedure Use the following steps to install the MVME3100 into your computer chassis 1 W N 8 Attach an ESD strap to your wrist Attach the other end of the ESD strap to electrical ground refer to Unpacking Guidelines The ESD strap must be secured to your wrist and to ground throughout the procedure Remove any filler panel that might fill that slot Install the top and bottom edge of the MVME3100 into the guides of the chassis Ensure that the levers of the two injector ejectors are in the outward position Slide the MVME3100 into the chassis until resistance is felt Simultane
77. e protection of both physical banks Regardless of the state of the software Flash write protect bit in the Flash Control Status register write protection is enabled for both banks when this switch is ON When this switch is OFF write protection is controlled by the state of the software Flash write protect bit and can only be disabled by clearing this bit in the Flash Control Status register Refer to Flash Control Status Register on page 112 for more information TheF WE HW bit reflects the state of the switch and is only software readable whereas the F WP SW bit supports both read and write operations The MVME3100 provides dual boot option for booting from one of two separate boot images in the boot Flash bank which are referred to as boot block A and boot block Boot blocks and B are each 1MB in size and are located at the top highest address 2 MB of the boot Flash memory space Boot block A is located at the highest 1 block and block is the next highest 1MB block FLASH boot block switch is used to select between boot block and boot block When the switch is OFF the Flash memory map is normal and block A is selected When the MVME3100 Single Board Computer Installation and Use 6806800M28C 133 Programming Details 7 11 switch is ON block Bis mapped to the highest address as shown below The SEL bit in the Flash Control Status register can override the switch and restore the memory map to t
78. een 33 MHz and 133 MHz on either primary or secondary port Refer to the PCI6520CB Data Book listed in Appendix Related Documentation for additional details and or programming information MVME3100 Single Board Computer Installation and Use 6806800M28C Functional Description 4 10 5 PCI Mezzanine Card Slots The MVME3100 provides two PMC sites that support standard PMCs or PrPMCs Both PMC sites are located on PCI bus B and operate at the same speed and mode as determined by the slowest PMC module The board routing supports maximum of 100 MHz PCI X operation on each site Signaling voltage Vio for the two PMC sites is dependent on keying pin installation options and can be configured for 5V or 3 3V Both sites must be configured for the same Vio voltage or the Vio voltage will be disabled Each PMC site has enough 3 3V and 5V power allocated to support 25 watt max PMC or PrPMC from either supply PMC slot 1 supports Feature Description Mezzanine Type PMC PCI Mezzanine Card Mezzanine Size S1B Single width and standard depth 75mm x 150mm with front panel PMC Connectors 111 J12 J13 and J14 32 64 bit PCI with front and rear I O Signaling Voltage VIO 3 3V 5V tolerant or 5V selected by keying pin PMC slot 2 supports Feature Description Mezzanine Type PMC PCI Mezzanine Card Mezzanine Size S1B Single width and standard depth 75mm x 150mm with front panel PMC Co
79. en the 3 3V and battery voltages The battery provides backup power to the RTC for a minimum of one year at nominal temperature Reset Control Logic The sources of reset on the MVME3100 are the following Power up Reset switch Watchdog timer System Control register bit VMEbus reset A board level hard reset generates a reset for the entire board including the MPC8540 local PCI PCI X buses Ethernet PHYs serial ports Flash devices and PLD s If the 100 is configured as the VME system controller the VME bus and local TSi148 reset input are also reset MVME3100 Single Board Computer Installation and Use 6806800M28C 81 Functional Description 4 14 Debug Support The MVME3100 provides boundary scan header for boundary scan test access and device programming This board also provides a separate standard COP header for MPC8540 COP emulation 82 MVME3100 Single Board Computer Installation and Use 6806800M28C Chapter 5 Pin Assignments 5 1 Overview This chapter provides pin assignments for various connectors and headers on the MMVE3100 single board computer and the MVME721 transition module PMC Expansion Connector J4 Ethernet Connectors GENET 1 J41B GENET2 2B ENET1 2A PCI Mezzanine PMC Connectors J11 J14 J21 J23 Serial Port Connectors COM2 COM5 J2A D VMEbus P1 Connector VMEbus P2 Connector MVME721 PMC I O Module PIM Connectors
80. ernet interface is routed to a front panel RJ 45 connector with integrated LEDs for speed and activity indication The other Gigabit Ethernet interface and the 10 100 interface are routed to P2 for rear I O The pin assignments for these connectors are as follows Table 5 2 Ethernet Connectors Pin Assignment Pin Signal 1000 Mb s 10 100 Mb s 1 MDIOO _DA TD 2 MDIOO _DA TD 3 MDIO1 _DB RD 4 MDIO1 _DC Not Used 5 MDIO2 _DG Not Used 6 MDIO2 _DB RD 7 MDIO3 _DD Not Used 8 MDIO3 _DD Not Used 5 2 3 PCI Mezzanine Card PMC Connectors J11 14 J21 J23 There are seven 64 pin SMT connectors on the MVME3100 to provide 32 64 bit PCI interfaces and P2 I O for one optional add on PMC PMC slot connector J14 contains the signals that go to VME P2 I O rows A C D and 7 The pin assignments for these connectors are as follows Table 5 3 PMC Slot 1 Connector J11 Pin Assignments Pin Signal Signal Pin 1 TCK 12V 2 3 GND INTA 4 5 INTB INTC 6 MVME3100 Single Board Computer Installation and Use 6806800M28C 87 Pin Assignments Table 5 3 PMC Slot 1 Connector J11 Pin Assignments continued Pin Signal Signal Pin 7 PMCPRSNTI 5V 8 9 INTD PCI RSVD 10 11 GND 3 3Vaux 12 13 CLK GND 14 15 GND PMCGNT1 16 17 PMCREQ1 5V 18 19 3 3V VIO AD31 20
81. es soft start current limiting over current detection and power enable for port 1 Refer to the uPD720101 USB 2 0 Host Controller Datasheet listed in Appendix B Related Documentation for additional details PMC Expansion The MVM3E3100 provides additional PMC module capability through the use of a connector on bus C that is compatible with the PMCspan boards Up to four additional PMC modules may be added by using existing PMCspan boards Refer to the PMCspan PMC Adapter Carrier Board Installation and Use manual listed in Appendix B Related Documentation for additional details MVME3100 Single Board Computer Installation and Use 6806800M28C Functional Description 4 11 4 12 4 13 General Purpose Timers There are a total of eight independent 32 bit timers Four timers are integrated into the MPC8540 and four timers are in the PLD The four MPC8540 timers are clocked by the RTC input which is driven by I MHz clock The clock source for the four timers in the PLD is 25 MHz Refer to the MPC8540 Reference Manual listed in Appendix B Related Documentation for additional details and or programming information Real time Clock Battery There is an on board Renata SMT battery holder on the MVME3100 This SMTU2430 1 holder allows for quick and easy replacement of a 3V button cell lithium battery CR2430 which provides back up power to the on board DS1375 A battery switching circuit provides automatic switching betwe
82. ges are supported With Alternate Boot Image support the bootloader code in the boot block examines the upper 8MB of the flash bank for Alternate Boot images If an image is found control is passed to the image Firmware Startup Sequence Following Reset The firmware startup sequence following reset of MOTLoad is to Initialize cache MMU FPU and other CPU internal items Initialize the memory controller Search the active flash bank possibly interactively for a valid POST image If found the POST images executes Once completed the POST image returns and startup continues Search the active flash bank possibly interactively for a valid USER boot image If found the USER boot image executes A return to the boot block code is not anticipated MVME3100 Single Board Computer Installation and Use 6806800M28C 59 Firmware Ifavalid USER boot image is not found search the active flash bank possibly interactively for a valid MCG boot image anticipated to be upgrade of MCG firmware If found the image is executed A return to the boot block code is not anticipated Execute the recovery image of the firmware in the boot block if no valid USER or MCG image is found During startup interactive mode may be entered by either setting the Safe Start jumper switch or by sending an lt ESC gt to the console serial port within five seconds of the board reset During interactive mode the user has the optio
83. gle Board Computer Installation and Use 6806800M28C Chapter 4 Functional Description O o L0 2 1 _ 4 1 Overview This chapter describes the MVME3100 and the MVME721 rear transition module RTM on a block diagram level 4 2 Features The following tables list the features of the MVME3100 and its RTM Table 4 1 MVME3100 Features Summary Feature Description Processor Host Single 833 MHz MPC8540 PowerQUICC III integrated processor Controller Memory Controller e500 core Integrated 256KB L2 cache SRAM Integrated four channel DMA controller Integrated PCI PCI X controller Two integrated 10 100 1000 Ethernet controllers Integrated 10 100 Ethernet controller Integrated dual UART Integrated I2C controller Integrated programmable interrupt controller Integrated local bus controller Integrated DDR SDRAM controller System Memory One SODIMM socket Up to DDR333 ECC One ortwo banks of memory on a single SODIMM C Interface One 8KB VPD serial EEPROM Two 64KB user configuration serial EEPROMs One real time clock with removable battery One temperature sensor Interface to SPD s on SODIMM and P2 for RTM VPD Flash 128MB soldered Flash with two alternate 1 MB boot sectors selectable via a hardware switch Hardware switch or software bit write protection for entire logical bank MVME3100 Single Board Computer Installation and Use 6806800
84. he normal configuration with block A selected Upon RESET this mapping reverts to the switch selection PCI IDSEL Definition Each PCI device has an associated address line connected via a resistor to its IDSEL pin for configuration space accesses The following table shows the IDSEL assignments for the PCI devices and slots on each of the PCI buses on the board along with the corresponding interrupt assignment to the PIC external interrupt pins Refer to the MPC8540 Reference Manual and PCI6520CB Data Book and for details on generating configuration cycles on each of the PCI busses Table 7 7 IDSEL and Interrupt Mapping for PCI Devices Device Number AD Line PCI Device PCI Bus Field for IDSEL or Slot Device Slot INT to MPC8540 Ext IRQ INTA INTB INTCH INTD A 0b0_0000 internal MPC8540 8540 See Note following table 0b0 0001 17 TSi148 VME IRQO IRQ1 IRQ2 IRQ3 0b0 0010 18 PCI6520 1 0b0 0011 19 PCI6520 2 0b0_0100 20 Sil3124A IRQ2 SATA B 0b0 0000 16 PMC1 IRQ4 IRQ5 IRQ6 IRQ7 PCI6520 1 Primary 0b0 0001 17 PMC1 IRQ5 IRQ6 IRQ7 IRQ4 Secondary 0b0_0010 18 PMC2 IRQ6 IRQ7 IRQ4 IRQ5 Primary 0b0 0011 19 PMC2 IRQ7 IRQ4 IRQ5 IRQ6 Secondary 134 MVME3100 Single Board Computer Installation and Use 6806800M28C Programming Details Table 7 7 IDSEL and Interrupt Mapping for PCI Devices continued Device Number ADLi
85. he LBC bank chip select used to decode the register Table 6 3 System I O Memory LBC Bank Address Definition Chip Select Notes E200 0000 System Status Register 2 3 E200 0001 System Control Register 2 3 E200 0002 Status Indicator Register 2 3 E200 0003 Flash Control Status Register 2 3 E200 0004 PCI Bus A Status Register 2 3 E200 0005 PCI Bus B Status Register 2 3 E200 0006 PCI Bus C Status Register 2 3 E200 0007 Interrupt Detect Register 2 3 200 0008 Presence Detect Register 2 3 E200 0009 PLD Revision 2 3 E200 000C PLD Date Code 32 bits 2 3 E200 0010 Test Register 1 32 bits 2 3 E200 0014 Test Register 2 32 bits 2 3 200 0018 Reserved 1 E200 OFFF E201 1000 COM 2 QUART channel 1 3 E201 1FFF E201 2000 COM 3 QUART channel 2 3 E201 2FFF E201 3000 COM 4 QUART channel 3 3 E201 3FFF E201 4000 COM 5 QUART channel 4 3 E201 4FFF MVME3100 Single Board Computer Installation and Use 6806800M28C 107 Memory Maps Table 6 3 System Memory Map continued LBC Bank Address Definition Chip Select Notes E201 5000 Reserved 1 E201 FFFF E202 0000 External PLD Tick Timer Prescaler Register 4 2 E202 0010 External PLD Tick Timer 1 Control Register 4 2 E202 0014 External PLD Tick Timer 1 Compare Register 4 2 E202 0018 External PLD Tick Timer 1 Counter Register 4 2 E202 001C Reserved
86. he clock tree frequencies on bus have default configuration of 66 MHz The 33 66 100 MHz clocks are dynamically configured at reset depending on the state of the PCIXCAP and M66EN pins on bus B M l 4 The PCI clock trees are not required to synchronized with each other Table 7 10 Clock Assignments Clock Tree Device Clock Signal s Frequency MHz Source Qty VIO MPC8540 8540 66 100 1 3 3V TSi148 CLK_VME 66 100 A 1 3 3V sATA CLK_SATA 66 100 A 1 3 3V PCI6520 Primary CLK_P2P_ABP 66 100 A 2 3 3V CLK_P2P_ACP 1 PMC1 33 66 100 1 3 3V PMC2 PMC2 33 66 100 B 1 3 3V PCI6520 CLK_P2P_ABS 33 66 100 B 1 3 3V SeeD CLK_P2P_ACS 33 1 3 3V USB CLK_USB 33 C 1 3 3V PMCspan CLK_SPAN 33 C 1 3 3V MPC9855 CLK66 25 Oscillator 2 3 3V 54615 CLK25 25V PHY 25 Oscillator 2 2 5V Buffer BCM5221 CLK25 33V PHY 25 Oscillator 1 3 3V Buffer MVME3100 Single Board Computer Installation and Use 6806800M28C 137 Programming Details Table 7 10 Clock Assignments continued Clock Tree Device Clock Signal s Frequency MHz Source Qty VIO Control and Timers CLK25 33V PLD 25 Oscillator 1 3 3V PLD Buffer CLK LBC CCB CLK 8 333 MPC8540 1 3 3V MHz 8 QUART CLK_UART 1 8432 Oscillator 1 3 3V sATA CLK25 25 Oscillator 1 3 3V USB CLK48 48 Oscillator 1 3 3V RTC CLK32 32 768 kHz Crys
87. ication listed in Appendix B Related Documentation The MVME3100 uses a Discovery for its VME bridge The offsets of the mailboxes in the Discovery II are defined in the Discovery Il User Manual listed in Appendix B Related Documentation but are noted here for reference 58 MVME3100 Single Board Computer Installation and Use 6806800M28C MOTLoad Firmware 3 7 3 8 Mailbox 0 is at offset 71348 in the CR Mailbox 1 is at offset 7f34C in the CR Mailbox 2 is at offset 71350 in the CR Mailbox 3 is at offset 71354 in the CR CSR space CSR space CSR space CSR space a a The selection of the mailbox used by remote start on an individual MVME3100 is determined by the setting of a global environment variable GEV The default mailbox is zero Another GEV controls whether remote start is enabled default or disabled Refer to the Remote Start appendix in the MOTLoad Firmware Package User s Manual for remote start GEV definitions The MVME3100 s IBCA needs to be mapped appropriately through the master s VMEbus bridge For example to use remote start using mailbox 0 on an MVME3100 installed in slot 5 the master would need a mapping to support reads and writes of address 0x002ff348 in VME CR CSR space 0x280000 0x7f348 Alternate Boot Images and Safe Start Some later versions of MOTLoad support Alternate Boot Images and a Safe Start recovery procedure If Safe Start is available on the MVME3100 Alternate Boot Ima
88. irmware package serves as a board power up and initialization package as well as a vehicle from which user applications can be booted secondary function of the MOTLoad firmware is to serve in some respects as a test suite providing individual tests for certain devices This chapter includes a list of standard MOTLoad commands the default VME and firmware settings that are changeable by the user remote start and the alternate boot procedure MOTLoad is controlled through an easy to use UNIX like command line interface The MOTLoad software package is similar to many end user applications designed for the embedded market such as the real time operating systems currently available Refer to the MOTLoad Firmware Package User s Manual listed in Appendix Related Documentation for more details Implementation and Memory Requirements The implementation of MOTLoad and its memory requirements are product specific The MVME3100 Single Board Computer SBC is offered with a wide range of memory for example DRAM external cache flash Typically the smallest amount of on board DRAM that an Emerson SBC has is 32 MB Each supported product line has its own unique binary image s Currently the largest compressed image is less than 1 MB in size MOTLoad Commands MOTLoad supports two types of commands applications utilities and tests Both types of commands are invoked from the MOTLoad command line in a simil
89. led on chip PCI PCI X arbiter PCI Resistor 1 PCI Debug PCI debug enabled Configuration PCI GNTA L Switch 0 PCI PCI X Configuration 1 PCI mode EC MDC Resistor 1 TSEC Width 0 Ethernet in reduced Configuration mode RTBI or RGMII Ethernet in standard mode TBI or GMII 124 MVME3100 Single Board Computer Installation and Use 6806800M28C Programming Details Table 7 1 MPC8540 Power on Reset Configuration Settings continued Default MPC8540 Signal Select Option Setting Description State of Bit vs Function TSEC1 Resistor 0 TSEC1 Protocol TSEC1 controller uses TXD7 Configuration GMII protocol RGMII if TSEC1 configured in reduced mode 1 TSEC1 controller uses TBI protocol RTBI if TSECT configured in reduced mode TSEC1_ Resistors 111 Boot ROM Location 000 PCI PCI X dl 001 DDR SDRAM 011 RapidlO 101 Local Bus GPCM 8 bit ROM 110 Local Bus GPCM 16 bit ROM 111 Local Bus GPCM 32 bit ROM TSEC2_ Resistor 0 TSEC2 Protocol TSEC2 controller uses TXD7 Configuration GMII protocol or RGMII if TSEC2 configured in reduced mode 1 TSEC2 controller uses TBI protocol or RTBI if TSEC2 configured in reduced mode MVME3100 Single Board Computer Installation and Use 6806800M28C 125 Programming Details Table 7 1 MPC8540 Power on Reset Configuration Settings continued Default MPC8540 Signal Select
90. llowing reset of MOTLoad is to Initialize cache MMU FPU and other CPU internal items Initialize the memory controller Search the active flash bank possibly interactively for a valid Power On Self Test POST image If found the POST images executes Once completed the POST image returns and startup continues Search the active flash bank possibly interactively for a valid USER boot image If found the USER boot image executes A return to the boot block code is not anticipated If a valid USER boot image is not found search the active flash bank possibly interactively for a valid Alternate MOTLoad boot image anticipated to be an upgrade of alternate MOTLoad firmware If found the image is executed A return to the boot block code is not anticipated Execute the recovery image of the firmware in the boot block if no valid USER or alternate MOTLoad image is found During startup interactive mode may be entered by either setting the Safe Start jum per switch or by sending an lt ESC gt to the console serial port within five seconds of the board reset During interactive mode the user has the option to display locations at which valid boot images were discovered specify which discovered image is to be executed or specify that the recovery image in the boot block of the active flash bank is to be executed MVME3100 Single Board Computer Installation and Use 6806800M28C 67 Firmware 68 MVME3100 Sin
91. low counter is cleared when 1 is written to this bit OVF Overflow bits These bits are the output of the overflow counter The overflow counter is incremented each time the tick timer sends an interrupt to the local bus interrupter The overflow counter can be cleared by writing a 1 to the COVF bit ENINT Enable interrupt Whenthis bit is high the interrupt is enabled Whenthis bit is low the interrupt is not enabled CINT Clear interrupt 120 MVME3100 Single Board Computer Installation and Use 6806800M28C Memory Maps 6 1 16 3 INTS Interrupt status RSVD Reserved for future implementation Compare Registers The tick timer counter is compared to the Compare register When they are equal the tick timer interrupt is asserted and the overflow counter is incremented If the clear on compare mode is enabled the counter is also cleared For periodic interrupts this equation should be used to calculate the compare register value for a specific period T Compare register value T us When programming the tick timer for periodic interrupts the counter should be cleared to zero by software and then enabled If the counter does not initially start at 0 the time to the first interrupt may be longer or shorter than expected The rollover time for the counter is 71 6 minutes Table 6 19 Tick Timer Compare Registers Tick Timer 1 Compare Register 0 202 0014 32 bits Tick Timer 2 Compare Register
92. m MVME3100 Single Board Computer Installation and Use 6806800M28C MOTLoad Firmware 3 5 3 5 1 Usage testRam aPh bPh iPd nPh tPd v Description RAM Test Directory Argument Option Description a Ph Address to Start Default Dynamic Allocation b Ph Block Size Default 16KB i Pd Iterations Default 1 n Ph Number of Bytes Default 1MB t Ph Time Delay Between Blocks in OS Ticks Default 1 v O Verbose Output MVME3100 gt Firmware Settings The following sections provide additional information pertaining to the VME firmware settings ofthe MVME3100 A few VME settings are controlled by hardware jumpers while the majority of the VME settings are managed by the firmware command utility vmecfg Default VME Settings As shipped from the factory the MVME3100 has the following VME configuration programmed via Global Environment Variables GEVs for the Tsi148 VME controller The firmware allows certain VME settings to be changed in order for the user to customize the environment The following is a description of the default VME settings that are changeable by the user For more information refer to the MOTLoad User s Manual and Tundra s Tsi148 User Manual listed in Appendix B Related Documentation MVME3100 gt vmeCfg s m Displaying the selected Default VME Setting interpreted as follows VME PCI Master Enable Y N Y MVME3100 The PCI M
93. mbedded Computing product documentation Table B 1 Emerson Network Power Embedded Computing Documents Document Title Publication Number MVME3100 Single Board Computer Programmer s Reference Guide 6806800G37 MOTLoad Firmware Package User s Manual 6806800C24 PMCspan PMC Adapter Carrier Board Installation and Use 6806800A59 B 2 Manufacturers Documents For additional information refer to the following table for manufacturers data sheets or user s manuals As an additional help a source for the listed document is provided Please note that while these sources have been verified the information is subject to change without notice Table B 2 Manufacturers Documents Document Title and Source Publication Number MPC8540 Integrated Processor Hardware Specifications MPC8540EC Freescale Semiconductor Technical Call Center Telephone 1 800 521 6274 Web Site www freescale com MPC8540 PowerQUICC III Integrated Host Processor Reference Manual MPC8540RM Freescale Semiconductor Technical Call Center Telephone 1 800 521 6274 Web Site www freescale com MVME3100 Single Board Computer Installation and Use 6806800M28C 143 Related Documentation Table B 2 Manufacturers Documents continued Document Title and Source Tsi148 PCI X to VME Bus Bridge User Manual Tundra Semiconductor Corporation 603 March Road Ottawa Ontario Canada K2K 2M5 Web Site www tundr
94. me to time in the content hereof without obligation of Emerson to notify any person of such revision or changes Electronic versions of this material may be read online downloaded for personal use or referenced in another document as a URL to a Emerson website The text itself may not be published commercially in print or electronic form edited translated or otherwise altered without the permission of Emerson It is possible that this publication may contain reference to or information about Emerson products machines and programs programming or services that are not available in your country Such references or information must not be construed to mean that Emerson intends to announce such Emerson products programming or services in your country Limited and Restricted Rights Legend If the documentation contained herein is supplied directly or indirectly to the U S Government the following notice shall apply unless otherwise agreed to in writing by Emerson Use duplication or disclosure by the Government is subject to restrictions as set forth in subparagraph b 3 of the Rights in Technical Data clause at DFARS 252 227 7013 Nov 1995 and of the Rights in Noncommercial Computer Software and Documentation clause at DFARS 252 227 7014 Jun 1995 Contact Address Emerson Network Power Embedded Computing 2900 South Diablo Way Suite 190 Tempe AZ 85282 USA Contents About this Manual u se
95. ments or commands in body text Courier Bold Used to characterize user input and to separate it from system output Reference Used for references and for table and figure descriptions File gt Exit Notation for selecting a submenu lt text gt Notation for variables and keys text Notation for software buttons to click on the screen and parameter description MVME3100 Single Board Computer Installation and Use 6806800M28C 7 About this Manual 18 Notation Description Repeated item for example node 1 node 2 node 12 Omission of information from example command that is not necessary at the time being Ranges for example 0 4 means one of the integers 0 1 2 3 and 4 used in registers A XOOOCOOOOCODODOQOOO0000O000000 D0000000000000000000000 OOCODOOCOOOUCCOUCOCCOOCOCOQOOCOOUOQDOOO0DOO00000000 QUC KC XXOCOOUOOODOUODUOCDQODOCUUOOODOOOOUODOOOODQOOO0OOOO CCEE Logical OR Indicates a hazardous situation which if not avoided could result in death or serious injury 30O0O00000000000000000000000000000000000000O00000000 C JOU HIKING IEH IHK IHK IKKE MINI 9 6 6 7 2 8 5 2 2 6 5 2 2 6 2 2X0 OOOO OO OIE Indicates a hazardous situation which if not avoided may result in minor or moderate injury XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
96. n Falls Sie weitere Informationen ben tigen sollten wenden Sie sich bitte an die f r Sie zust ndige Gesch ftsstelle von Emerson Das Produkt wurde entwickelt um die Sicherheitsanforderungen f r SELV Ger te nach der Norm EN 60950 1 f r informationstechnische Einrichtungen zu erf llen Die Verwendung des Produkts in einer anderen Anwendung erfordert eine Sicherheits berpr fung f r diese spezifische Anwendung Einbau Wartung und Betrieb d rfen nur von durch Emerson ausgebildeter oder im Bereich Elektronik oder Elektrotechnik qualifiziertem Personal durchgef hrt werden Die in diesem Handbuch enthaltenen Informationen dienen ausschlie lich dazu das Wissen von Fachpersonal zu erg nzen k nnen dieses jedoch nicht ersetzen Halten Sie sich von stromf hrenden Leitungen innerhalb des Produktes fern Entfernen Sie auf keinen Fall Abdeckungen am Produkt Nur werksseitig zugelassenes Wartungspersonal oder anderweitig qualifiziertes Wartungspersonal darf Abdeckungen entfernen um Komponenten zu ersetzen oder andere Anpassungen vorzunehmen Installieren Sie keine Ersatzteile oder f hren Sie keine unerlaubten Ver nderungen am Produkt durch sonst verf llt die Garantie Wenden Sie sich f r Wartung oder Reparatur bitte an die f r Sie zust ndige Gesch ftsstelle von Emerson So stellen Sie sicher dass alle sicherheitsrelevanten Aspekte beachtet werden MVME3100 Single Board Computer Safety Notes Summary 6806800M28C 152 Sicherheitshi
97. n to display locations at which valid boot images were discovered specify which discovered imageis to be executed or specifythat the recovery image in the boot block of the active Flash bank is to be executed 3 9 Firmware Scan for Boot Image The scan is performed by examining each 1MB boundary for a defined set of flags that identify the image as being Power On Self Test POST USER or MCG MOTLoad is an MCG image POST is user developed Power On Self Test that would perform a set of diagnostics and then return to the bootloader image User would be boot image such as the VxWorks bootrom which would perform board initialization A bootable VxWorks kernel would also be a USER image Boot images are not restricted to being MB or less in size however they must begin on 1MB boundary within the 8MB of the scanned flash bank The Flash Bank Structure is shown below Address Usage OxFFF00000 to OxFFFFFFFF OxFFEOO000 to OXFFFFFFFF Boot block Recovery code Reserved for MCG use MOTLoad update image OxFFD00000 to OxFFDFFFFF First possible alternate image FBD00000 or F7D00000 Bank Bank A actual OxFFCO0000 to OxFFCFFFFF Second possible alternate image or F7C00000 Bank Bank A actual Alternate boot images OxFF899999 to OxFF8FFFFF Fb800000 or F3800000 Last possible alternate image Bank B Bank A actual MVME3100 Single Board Computer Installation and Use
98. nd Use 6806800M28C 25 Hardware Preparation and Installation 0 OHM 1 4 2 Configuration Switch S4 An 8 position SMT configuration switch controls the VME SCON setting Flash bank write protect and the safe start ENV settings It also selects the Flash boot image The default setting on all switch positions is OFF Table 1 2 Configuration Switch S4 Settings Setting Switch Pos OFF Factory Default ON Notes SAFE_START 1 Normal ENV settings Safe ENV settings This switch status is should be used should be used readable from System Status register 1 bit 5 Software may check this bit and act accordingly BOOT BLOCK 2 Flash memory map is Boot block B is SELECT normal and boot block selected and mapped is selected tothe highest address FLASH BANK WP 3 Entire Flash is not write Flash is write protected protected Reserved 4 VME SCON 5 Auto SCON mode Manual SCON mode Manual SCON mode AUTO MANUAL works in conjunction MODE with the VME SCON SELECT switch MANUAL VME 6 Non SCON mode Always SCON mode This switch is only SCON SELECT effective when the VME SCON AUTO MANUAL switch is ON Reserved 7 26 MVME3100 Single Board Computer Installation and Use 6806800M28C Hardware Preparation and Installation Table 1 2 Configuration Switch 54 Settings continued Switch TRST SELECT 1 4 3 Pos HRESET will assert TRST Se
99. ndard 16 pin COP header Boundary scan support Switches for VME geographical addressing in a three row backplane Software Support VxWorks operating system Linux operating system Table 4 2 MVME721 RTM Features Summary Feature Description I O One five row P2 backplane connector for serial and Ethernet I O passed from the MVME3100 Four RJ 45 connectors for rear panel I O four asynchronous serial channels Two 45 connectors with integrated LEDs for rear panel I O one 10 100 1000 Ethernet channel and one 10 100 Ethernet channel One PIM site with rear panel I O MVME3100 Single Board Computer Installation and Use 6806800M28C 71 Functional Description Table 4 2 MVME721 RTM Features Summary continued Feature Description Miscellaneous Four status indicators 10 100 1000 and 10 100 Ethernet link speed and activity LEDs 72 MVME3100 Single Board Computer Installation and Use 6806800M28C Functional Description 4 3 Block Diagrams Figure 4 1 shows block diagram of the overall board architecture and Figure 4 2 shows block diagram of the 721 rear transition module architecture Figure4 1 MVME3100 Block Diagram Front Panel PMC 1 Front IO PMC 2 Front IO 166 MHz Memory Bus SODIMM Up to 1GB DDR Memory PCI X 66 100 MHz PCI 33 66 MHz SATA Sil3124A 4377 0106 MVME3100 Single Board Computer Installation and Use 6806
100. ne PCI Device PCI Bus Field for IDSEL or Slot Device Slot INT to MPC8540 Ext IRQ INTA INTB INTC INTD C 0b0 0000 16 uPD740101 IRQ4 IRQ5 IRQ6 PCI6520 2 USB ObO 0100 20 21150 on PMCSpan PCI Expansion 0b0 0010 18 PMCSpan IRQ6 IRQ7 IRQ4 IRQ5 21150 Slot 1 0b0 0011 19 PMCSpan IRQ7 IRQ4 IRQ5 IRQ6 Slot 2 0b0 0100 20 PMCSpan IRQ4 IRQ5 IRQ6 IRQ7 Slot 3 0b0 0101 21 PMCSpan IRQ5 IRQ6 IRQ7 IRQ4 Slot 4 The Device Number is as listed when Bus A is in PCI X mode If Bus A is in PCI mode add 0x16 0b1 0000 to the listed Device Number The following table shows the Vendor ID and the Device ID for each of the planar PCI devices on the MVME3100 Table 7 8 Planar PCI Device Identification Function Device Vendor ID Device ID System Controller MPC8540 0x1057 0x0008 PCI X to PCI X Bridge PCI6520CB 0x10B5 0x6520 VME Controller TSi148 Ox10E3 0x0148 SATA Controller Sil3124A 0x1095 0x3124 USB Controller uPD720101 0x1033 0x0035 MVME3100 Single Board Computer Installation and Use 6806800M28C 135 Programming Details 7 12 PCI Arbitration Assignments The integrated PCI X arbiters internal to the MPC8540 and the PCI6520 bridges provide PCI arbitration for the MVME3100 The MPC8540 provides arbitration support for itself and the four PCI X devices on PCI bus A The PCI6520 secondary PCI X interface arbiters support external bus masters in addition to the PCI6520 One secondary arbi
101. nfigured by an external master 4 Dependent on PCI PCI X mode configuration 5 Required to meet 2 ns hold time requirement 6 Meets 0 7 ns hold time requirement 128 MVME3100 Single Board Computer Installation and Use 6806800M28C Programming Details 7 Local bus LAD 0 31 is sampled during but only LAD 28 31 are configurable by resistor option Software can use this value to inform the firmware or operating system about initial board configuration 8 ECC signals from memory devices must be disconnected 7 3 MPC8540 Interrupt Controller The MVME3100 uses the MPC8540 integrated programmable interrupt controller PIC to manage locally generated interrupts Currently defined external interrupting devices and interrupt assignments along with corresponding edge levels and polarities are shown in the following table Table 7 2 MPC8540 Interrupt Controller Interrupt Edge Level Polarity Interrupt Source Notes leel VMEO 1 1 Level Low VME1 External Timers 2 Level Low VME2 sATA 3 Level Low VME3 UARTs OR d 2 4 Level Low PMCSpan PMCs USB 5 Level Low PMCspan PMCs 6 Level Low PMCspan PMCs 7 Level Low PMCspan PMCs 8 Level Low ABORT 9 Level Low Temp Sensor 10 Level Low Ethernet PHYs 4 11 Level Low DS1375 Alarm Interrupt 1 External timers are implemented in a PLD 2 External UARTs are implemented using a QUART Refer to the MPC
102. nments Pin Signal Signal Pin 1 12V 2 3 GND INTC 4 5 INTD INTA 6 7 PMCPRSNT 14 5V 8 9 INTB PCI_RSVD 10 11 GND 3 3Vaux 12 13 GND 14 15 GND PMCGNTI 16 17 1 5V 18 19 3 3V VIO AD31 20 21 AD28 AD27 22 23 AD25 GND 24 25 GND C BE3 26 27 AD22 AD21 28 29 AD19 5V 30 31 3 3V VIO AD17 32 33 FRAME GND 34 35 GND IRDY 36 37 DEVSEL 5V 38 39 GND LOCK 40 41 PCI_RSVD PCI_RSVD 42 43 PAR GND 44 45 3 3V VIO AD15 46 47 AD12 AD11 48 49 ADO9 5V 50 51 GND C BEO 52 53 AD06 ADO5 54 MVME3100 Single Board Computer Installation and Use 6806800M28C 93 Pin Assignments Table 5 7 PMC Slot 2 Connector J21 Pin Assignments continued Pin Signal Signal Pin 55 AD04 GND 56 57 3 3V VIO AD03 58 59 AD02 ADO1 60 61 ADOO 5V 62 63 GND REQ64 64 Table 5 8 PMC Slot 2 Connector J22 Pin Assignments Pin Signal Signal Pin 1 12V TRST 2 3 TMS TDO 4 5 TDI GND 6 7 GND Not Used 8 9 Not Used Not Used 10 11 Pull up 3 3V 12 13 RST Pull down 14 15 3 3V Pull down 16 17 Not Used GND 18 19 AD30 AD29 20 21 GND AD26 22 23 AD24 3 3V 24 25 IDSEL1 AD23 26 27 3 3V AD20 28 29 AD18 GND 30 31 AD16 C BE2 32 33 GND IDSEL1B 34 35 TRDY 3 3V 36 37 GND STOPH 38 94 MVME3100 Single Board Computer Installation and
103. nnectors 10 J14 PMC Host I O connector 10 routes only power and ground from VME P2 There are no Host I O signals on this connector The MVME3100 routes I O from J14 of PMC Slot 1 to VME P2 rows A and C The MVME721 routes these signals pin for pin from VME P2 to PMCI O Module connector J14 See Table 5 13 and Table 5 6 for the pin assignments Table 5 13 MVME721 Host I O Connector J10 Pin Assignments Pin Signal Signal Pin 1 No Connect No Connect 2 3 No Connect No Connect 4 5 5V No Connect 6 7 No Connect No Connect 8 9 No Connect 3 3V 10 11 No Connect No Connect 12 13 GND No Connect 14 15 No Connect No Connect 16 100 MVME3100 Single Board Computer Installation and Use 6806800M28C Pin Assignments Table 5 13 MVME721 Host I O Connector J10 Pin Assignments continued Pin Signal Signal Pin 17 No Connect GND 18 19 No Connect No Connect 20 21 5V No Connect 22 23 No Connect No Connect 24 25 No Connect 3 3V 26 27 No Connect No Connect 28 29 GND No Connect 30 31 No Connect No Connect 32 33 No Connect GND 34 35 No Connect No Connect 36 37 5V No Connect 38 39 No Connect No Connect 40 41 No Connect 3 3V 42 43 No Connect No Connect 44 45 GND No Connect 46 47 No Connect No Connect 48 49 No Connect GND 50 51 No Connect No Connect 52 53 5V No Connect 54 55 No Connect No Connect 56 57 No Connect
104. nnectors J21 J22 and J23 32 64 bit PCI with front I O Signalling Voltage VIO 3 3V 5V tolerant or 5V selected by keying pin You cannot use 3 3V and 5V PMCs together the voltage keying pin on slots 1 and 2 must be identical When in 5V mode the bus runs at 33 MHz In addition the PMC connectors are located such that a double width PMC may be installed in place of the two single width PMCs MVME3100 Single Board Computer Installation and Use 6806800M28C 79 Functional Description In this case the MVME3100 supports Feature Mezzanine Type PMC PCI Mezzanine Card Description Mezzanine Size Double width and standard depth 150mm x 150mm with front panel PMC Connectors 111 J12 J13 14 J21 J22 and J23 32 64 bit PCI with front and rear I O J14 only Signaling Voltage 3 3V 5V tolerant or 5V selected by keying pin 4 10 6 4 10 7 On PMC site 1 the user I O J14 signals will only support the low current high speed signals and are not to be used for any current bearing power supply usage The maximum current rating of each pin signal is 100 mA USB The USB 2 0 host controller provides USB ports with integrated transceivers for connectivity with any USB compliant device or hub USB channel 1 is routed to a single USB connector located at the front panel DC power to the front panel USB port is supplied via USB power switch which provid
105. ntal Specifications aaanavmnavnavenaennaenneeraeenaennaeunnenanenner 137 A 3 Thermally Significant Components 138 B Related Documentation 2 e seria haa 000000000 sede 141 B 1 Emerson Network Power Embedded Computing Documents 141 B 2 Manufacturers Documents 00 e ccc eee e nee ene ne he sheer 141 3 Related Specifications een sn 143 Safety Notes ves dad nere ee Fe eiker 146 Sicherheitshinweise auseinander 150 MVME3100 Single Board Computer Installation and Use 6806800M28C 7 Contents 8 MVME3100 Single Board Computer Installation and Use 6806800M28C List of Tables Table 1 1 Startup OVELVIEW DEIN eden ee 19 Table 1 2 Configuration Switch S4 Settings 22222eeeseneeeeeeeseeeeeen ee 24 Table 1 3 Geographical Address Switch Assignments 25 Table 1 4 Slot Geographical Address Settings 0 26 Table 1 5 RTM EEPROM Address Switch Assignments 27 Table 1 6 EEPROM Address Settings eee nee ene hmm e 27 Table 1 7 MVME3100 Connectors 01 cece cece ehh 30 Table 1 8 MVME721 Rear Transition Module 30 Table 2 1 Front Panel LED Status Indicators 0 ccc cece cece e ete
106. nvironment Variable s Dump NVRAM Header Data gevEdit Global Environment Variable Edit gevinit Global Environment Variable Area Initialize NVRAM Header gevList Global Environment Variable Labels Names Listing gevShow Global Environment Variable Show gn Go Execute User Program to Next Instruction go Go Execute User Program gt Go Execute User Program to Temporary Break Point hbd Display History Buffer hbx Execute History Buffer Entry help Display Command Test Help Strings I2CacheShow Display state of L2 Cache and L2CR register contents I3CacheShow Display state of L3 Cache and L3CR register contents mdb Memory Display Bytes Halfwords Words mdh mdw memShow Display Memory Allocation mmb Memory Modify Bytes Halfwords Words mmh mmw mpuFork Execute program from idle processor MVME3100 Single Board Computer Installation and Use 6806800M28C 45 MOTLoad Firmware Table 3 1 MOTLoad Commands continued Command Description mpuShow Display multi processor control structure mpusStart Start the other MPU netBoot Network Boot BOOT TFTP netShow Display Network Interface Configuration Data netShut Disable Shutdown Network Interface netStats Display Network Interface Statistics Data noCm Turns off Concurrent Mode pciDataRd Read PCI Device Configuration Header Register pciDataWr Write PCI Device Configuration Header Register pci
107. nweise EMV Das Blade wurde in einem Emerson Standardsystem getestet Es erf llt die f r digitale Ger te der Klasse A g ltigen Grenzwerte in einem solchen System gem den FCCRichtlinien Abschnitt 15 bzw EN 55022 Klasse A Diese Grenzwerte sollen einen angemessenen Schutz vor St rstrahlung beim Betrieb des Blades in Gewerbe sowie Industriegebieten gew hrleisten Das Blade arbeitet im Hochfrequenzbereich und erzeugt St rstrahlung Bei unsachgem em Einbau und anderem als in diesem Handbuch beschriebenen Betrieb k nnen St rungen im Hochfrequenzbereich auftreten Warnung Dies ist eine Einrichtung der Klasse A Diese Einrichtung kann im Wohnbereich Funkst rungen verursachen In diesem Fall kann vom Betreiber verlangt werden angemessene Ma nahmen durchzuf hren Installation Besch digung von Schaltkreisen Elektrostatische Entladung und unsachgem er Ein und Ausbau von Blades kann Schaltkreise besch digen oder ihre Lebensdauer verk rzen Bevor Sie Blades oder elektronische Komponenten ber hren vergewissern Sie sich da Sie in einem ESD gesch tzten Bereich arbeiten Besch digung des Produktes und der Zusatzmodule Fehlerhafter Ein oder Ausbau von Zusatzmodulen f hrt zu Besch digung des Produktes oder der Zusatzmodule Lesen Sie deshalb vor dem Ein oder Ausbau von Zusatzmodulen die Dokumentation und benutzen Sie angemessenes Werkzeug MVME3100 Single Board Computer Installation and Use 6806800M28C 153
108. of Electrical and Electronics Engineers Inc USB http www usb org developers docs Universal Serial Bus Specification Revision 2 0 April 27 2000 146 MVME3100 Single Board Computer Installation and Use 6806800M28C Related Documentation MVME3100 Single Board Computer Installation and Use 6806800M28C 147 Safety Notes EMC This section provides warnings that precede potentially dangerous procedures throughout this manual Instructions contained in the warnings must be followed during all phases of operation service and repair of this equipment You should also employ all other safety precautions necessary for the operation of the equipment in your operating environment Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment Emerson intends to provide all necessary information to install and handle the product in this manual Because of the complexity of this product and its various uses we do not guarantee that the given information is complete If you need additional information ask your Emerson representative This product is a Safety Extra Low Voltage SELV device designed to meet the EN60950 1 requirements for Information Technology Equipment The use of the product in any other application may require safety evaluation specific to that application Only personnel trained by Emerson or persons qualifie
109. of a RapidlO 10 Agent of a Host of both RapidlO and PCI PCI X LALE LGPL2 Resistor 01 e500 Core Clock PLL 00 2 1 ea 10 3 1 11 7 2 LGPLO LGPL1 Fixed 11 RapidlO Transmit Clock 00 Reserved 01 RapidlO rcv clock is source of xmit clock 10 RapidlO xmit clock inputs are source of xmit clock CCB clock is source of xmit clock MVME3100 Single Board Computer Installation and Use 6806800M28C 127 Programming Details Table 7 1 MPC8540 Power on Reset Configuration Settings continued Default MPC8540 Signal Select Option Setting Description State of Bit vs Function LGPL3 LGPL5 Fixed 11 Boot Sequencer 00 Reserved 01 Boot sequencer enabled with normal I2C address mode 10 Boot sequencer enabled with extended I2C address mode Boot sequencer disabled LAD 28 31 Resistor 7 XX General Purpose POR XX General purpose Configuration configuration vector to be placed in register bits MSRCIDO Resistor 1 Memory Debug 0 Debug info from the LBC Configuration is driven on MSRCID amp MDVAL pins Debug info from the DDR SDRAM controller is driven on MSRCID amp MDVAL pins MSRCID1 Resistor 1 DDR Debug Debug info on ECC pins Configuration instead of normal ECC ECC pins function in normal mode 1 The selected configuration settings are indicated dark cell outlines 2 External arbitration is required 3 e500 core does not boot until co
110. on board Flash an on board quad UART QUART on board 32 bit timers and the System Control Status registers Refer to the MVME3100 Single Board Computer Programmer s Reference Guide listed in Appendix Related Documentation for the LBC bank and chip select assignments Flash Memory The MVME3100 provides one physical bank of soldered on Flash memory The bank is composed of two physical Flash devices configured to operate in 16 bit mode to form a 32 bit Flash bank The default configuration for the 100 1263 is 128MB using two 512Mb devices and for the MVME3100 1152 it is 64MB using two 256Mb devices Refer to the MVME3100 Single Board Computer Programmer s Reference Guide listed in Appendix B Related Documentation for more information Control and Timers Logic The MVME3100 control and timers logic resides on the local bus This logic provides the following functions on the board Local bus address latch e Chip selects for Flash banks and QUART e System Control and Status registers e Four32 bittick timers Real time clock RTC 1 MHz reference clock Refer to the MVME3100 Single Board Computer Programmer s Reference Guide listed in Appendix B Related Documentation for more information MVME3100 Single Board Computer Installation and Use 6806800M28C 75 Functional Description 4 7 4 8 IC Serial Interface and Devices The MVME3100 provides the following on board I2C serial devices connected to
111. ously move the injector ejector levers in an inward direction Verify that the MVME3100 is properly seated and secure it to the chassis using the two screws located adjacent to the injector ejector levers Connect the appropriate cables to the MVME3100 To remove the board from the chassis press the red locking tabs IEEE handles only and reverse the procedure 1 6 Connecting to Peripherals When the MVME3100 is installed in a chassis you are ready to connect peripherals and apply power to the board MVME3100 Single Board Computer Installation and Use 6806800M28C 31 Hardware Preparation and Installation Figure 1 1 on page 25 shows the locations of the various connectors while Table 1 7 and Table 1 8 list them for you Refer to Chapter 5 Pin Assignments for the pin assignments of the connectors listed below NOTICE Damage of the Product and Additional Devices and Modules e Incorrect installation or removal of additional devices modules damages the product or the additional devices or modules Before installing or removing additional devices or modules read the respective documentation and use appropriate tools Table 1 7 MVME3100 Connectors Connector Function JA expansion connector J11 J12 J13 14 mezzanine card PMC slot 1 connector J21 J22 J23 PCI mezzanine card PMC slot 2 connector J24 Boundary scan header J25 COP header J27 USB
112. pt Mapping for PCI Devices 132 Planar PCI Device Identification sss 133 PCI Arbitration Assignments cece cece cece ene eee e 134 Clock Assignments teases 135 Current Requirements en ar 137 MVME3100 Specifications 0 cece cece cece cece e 137 Thermally Significant Components 0c cece eee eee eee eee 138 Emerson Network Power Embedded Computing Documents 141 Manufacturers Documents 0 c cece cece eee nennen 141 Related Specifications eee I e 143 MVME3100 Single Board Computer Installation and Use 6806800M28C List of Figures Figure 1 1 Board Layout 23 Figure 1 2 Geographical Address Switch Settings 25 Figure 2 1 Front Panel LEDs and Connectors 35 Figure 4 1 MVME3100 Block Diagram 71 Figure 4 2 MVME721 RTM Block 72 Figure A 1 Primary Side lt 139 Figure A 2 Secondary Side Components cece cece cece eee nee 140 MVME3100 Single Board Computer Installation and Use 6806800M28C 11 List of Figures 12 MVME3100 Single Board Computer Installa
113. puter Installation and Use 6806800M28C 63 Firmware Ny 14 3 10 3 DONT AUTO RUN If set this flag indicates that the image is not to be selected for automatic execution user through the interactive command facility may specify the image to be executed MOTLoad currently uses an Image Flag value of 0x3 which identifies itself as an Alternate MOTLoad image that executes from RAM MOTLoad currently does not support execution from flash User Images These images are user developer boot code for example VxWorks bootrom image Such images may expect the system software state to be as follows upon entry The MMU is disabled L1 instruction cache has been initialized and is enabled L1 data cache has been initialized invalidated and is disabled L2 cache is disabled L3 cache is disabled RAM has been initialized and is mapped starting at CPU address 0 If RAM ECC or parity is supported RAM has been scrubbed of ECC or parity errors The active Flash bank boot is mapped from the upper end of the address space If specified by COPY TO RAM the image has been copied to RAM at the address specified by ImageRamAddress CPU register R1 the stack pointer has been initialized to a value near the end of RAM CPU register R3 is added to the following structure typedef struct altBootData unsigned int ramSize board s RAM size in MB void flashPtr ptr to this image in flash char boardType
114. r for an interface to the sATA hard disk drive USB 1263 version One four channel USB 2 0 controller one channel for front panel Ethernet Two 10 100 1000 MPC8540 Ethernet channels for front panel I O and rear P2 I O One 10 100 MPC8540 Ethernet channel for rear P2 I O 70 MVME3100 Single Board Computer Installation and Use 6806800M28C Functional Description Table 4 1 MVME3100 Features Summary continued Feature Description Serial Interface 16550 compatible 9 6 to 115 2 KBAUD MPC8540 asynchronous serial channel for front panel I O One quad UART controller to provide four 16550 compatible 9 6 to 115 2 KBAUD asynchronous serial channels for rear P2 I O Timers Four 32 bit MPC8540 timers Four 32 bit timers in a PLD Watchdog Timer One MPC8540 watchdog timer VME Interface VME64 ANSI VITA 1 1994 compliant VME64 Extensions ANSI VITA 1 1 1997 compliant 2eSST ANSI VITA 1 5 2003 compliant VITA 41 0 version 0 9 compliant Two five row 1 and P2 backplane connectors One TSi148 VMEbus controller Form Factor Standard 6U VME Miscellaneous One front panel reset abort switch Four front panel status indicators 10 100 1000 Ethernet link speed and activity board fail and user software controlled LED Six planar status indicators one power supply status LED two user software controlled LEDs three sATA activity LEDs one per channel One sta
115. re on any surface before applying power Thermally Significant Components table also supplies the component reference designator and the maximum allowable operating temperature You can find components on the board by their reference designators Versions of the board that are not fully populated may not contain some of these components Table A 3 Thermally Significant Components Max Allowable Component Measurement Reference Designator Generic Description Temperature Celsius Location U1012 Processor 0 C to 105 C 32 F to 221 F Junction 0 C to 70 C 32 F to 158 F Ambient 021 0 C to 70 C 32 F to 158 F Ambient U1009 U1010 PCI Bridge 0 C to 70 C 32 F to 158 F Ambient U5000 SATA Controller 0 C to 70 C 32 F to 158 F Ambient U1028 U1029 Gigabit Ethernet 0 C to 70 C 32 F to 158 F Ambient U1039 Ethernet 10 100 PHY 40 C to 85 C 40 F to 185 F Ambient U1051 U1052 Clock Driver 40 C to 85 40 F to 185 F Ambient U1054 Programmable Logic Device 0 C to 85 C 32 F to 185 F Junction 140 MVME3100 Single Board Computer Installation and Use 6806800M28C Specifications Figure A 1 Primary Side Components 021
116. ructure eee eee 63 3 10 5 Alternate Boot Images and Safe 5 63 3 10 6 Boot Image Firmware Scan 2 ieee eee II 64 3 11 Startup sequence Ep PEE RR E ner ev ana 65 4 Functional Descriptionic vecors vaart ne P PEINE P VES SUUS 67 EE OTEREN 67 AZ Features 67 43 Block Diagrams hen 71 44 PROCESSOR Sass ee 72 4 5 System Memory ee 72 4 6 LocalBusinterface anne 73 46 1 Flash Memory ansehe nase 73 4 6 2 Control and Timers 9 eee eh m emen 73 4 7 2C Serial Interface and Devices 0 ccc cece cece eee e 74 4 8 Ethernet Interfaces hern 74 4 9 Asynchronous Serial Ports 0 eee e cece ee eee mne 75 4 10 PCI PCI X Interfaces and Devices 0c cece ccc ence teen ene 75 4 10 1 MPC8540 PCI X Interface ne nee nennen nennen 75 4 10 2 TSi148 VME Controller 0 0 0 ccc cc cece cence nent tence heme 76 4 10 3 Serial ATA Host Controller 0 0 ccc cece cece cence nent me 76 4 10 4 PCI X to PCI X Bridges 0 ccc cece eee eee eee hh e ees 76 MVME3100 Single Board Computer Installation and Use 6806800M28C Contents 4 10 5 PCI Mezzanine Card 5 0 5
117. s Ethernet Port Function Location PHY Types 4 0 TSEC1 Gigabit Ethernet port routed to front 54615 01 TSEC2 Gigabit Ethernet port routed to P2 54615 02 Fast Ethernet 10 100 Ethernet port routed to P2 BCM5221 03 Controller 132 MVME3100 Single Board Computer Installation and Use 6806800M28C Programming Details 7 10 Flash Memory The MVME3100 is designed to provide one or two physical banks of soldered on Flash memory Each bank may be populated with two AMD Spansion MirrorBit 3 0V devices configured to operate in 16 bit mode to form 32 bit Flash bank The Flash bank connected to LBC Chip Select 0 is the boot bank and is always populated The second Flash bank connected to LBC Chip Select 1 may or may not be populated depending on Flash size requirements and available Flash devices The VPD Flash packet s will determine which banks are populated and the size of the devices Software must program one or two LBC chip selects based on the VPD Flash packet information The following table defines the supported Flash density options for each bank The factory configuration for the MVME3100 1152 is one bank of 64MB for the MVME3100 1263 it is one bank of 128MB Table 7 6 Flash Options Flash Bank Size Spansion Part Number Device Size 32MB S29GL128N 128 Mbit 64MB S29GL256N 256 Mbit 128MB S29GL512N 512 Mbit A hardware Flash bank write protect switch is provided on the MVME3100 to enable writ
118. s the user may be required to take corrective actions The blade generates and uses radio frequency energy and if not installed properly and used in accordance with this guide may cause harmful interference to radio communications Operating the system in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense Installation Damage of Circuits Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten their life Before touching the blade or electronic components make sure that you are working in an ESD safe environment Damage of the Product and Additional Devices and Modules Incorrect installation or removal of additional devices or modules damages the product or the additional devices or modules Before installing or removing additional devices or modules read the respective documentation and use appropriate tools Configuration Switches Jumpers Product Malfunction Switches marked as Reserved might carry production related functions and can cause the product to malfunction if their setting is changed Do not change settings of switches marked as reserved MVME3100 Single Board Computer Installation and Use 6806800M28C 149 Safety Notes Operation Product Damage High humidity and condensation on surfaces cause short circuits Do not operate the product outside the specifie
119. s first for POST then USER and finally Alternate MOTLoad images In the case of multiple images of the same type control is passed to the first image encountered in the scan Safe Start whether invoked by hitting ESC on the console within the first five seconds following power on reset or by setting the Safe Start jumper interrupts the scan process The user may then display the available boot images and select the desired image The feature is provided to enable recovery in cases when the programmed Alternate Boot Image is no longer desired The following output is an example of an interactive Safe Start ABCDEInteractive Boot Mode Entered boot Interactive boot commands d show directory of alternate boot images c continue with normal startup q quit without executing any alternate boot image r address execute specified or default alternate image p address execute specified or default POST image this help screen MVME3100 Single Board Computer Installation and Use 6806800M28C MOTLoad Firmware h this help screen boot gt d FFE00000 Size 00100000 Flags 00000003 Name MOTLoad Addr FFD00000 Size 00100000 Flags 00000003 Name MOTLoad boot gt c NOPORSTUVabcdefghijkilmn3opgrsstuvxyzaWXZ Copyright Motorola Inc 1999 2004 All Rights Reserved MOTLoad RTOS Version 2 0 PAL Version 0 b EA02 E3100 gt 3 11 Startup Sequence The e e firmware startup sequence fo
120. t Panel LED Status Indicators continued Function Label Color Description GENET 1 Link SPEED Off No link speed Yellow 10 100Base T operation Green 1000Base T operation GENET 1 Activity ACT Blinking Green Activity proportional to bandwidth utilization Off No activity 36 MVME3100 Single Board Computer Installation and Use 6806800M28C Startup and Operation Figure 2 1 Front Panel LEDs and Connectors ABORT RESET MVME3100 Single Board Computer Installation and Use 6806800M28C 37 Startup and Operation The MVME721 rear transition module also has four status indicators The following table describes these indicators Table 2 2 MVME721 LED Status Indicators Function Label Color Description GENET 2 Link Speed SPEED Off No link Yellow 10 100Base T operation Green 1000Base T operation GENET 2 Activity ACT Blinking Green Activity proportional to bandwidth utilization Off No activity ENET 1 Link Speed SPEED Off No link Yellow 10 100Base T operation ENET 1 Activity ACT Blinking Green Activity proportional to bandwidth utilization Off No activity Table 2 3 Additional Onboard Status Indicators Function Label Color Description User DS7 Green This indicator is illuminated by software assertion of its Defined LED silkscreen corresponding register bit 2 User 058
121. tal 1 3 3V 7 14 8540 Real Time Clock Input The MPC8540 real time clock RTC input is driven by a 1 MHz clock generated by the control and timers PLD This provides a fixed clock reference forthe RTC that software can use as a known timing reference To select this 1 MHz clock as the RTC timer reference software must set the SEL TBCLK bit in the MPC8540 HIDO register 7 15 MPC8540 LBC Clock Divisor The MPC8540 LBC clock output is used by the control and timers PLD The LBC clock is derived from divide by 2 4 or 8 ratio of the internal CCB core complex bus clock as determined by the clock ratio register LCRR CLKDIV For proper operation of the local bus CLKDIV must be set for divide by 8 which is the default value The software must leave this register configured for divide by 8 during initialization 138 MVME3100 Single Board Computer Installation and Use 6806800M28C Specifications A 1 Power Requirements In its standard configuration the MVME3100 requires 5 V for operation On board converters supply the processor core voltage 3 3 V 1 8 V and 2 5 V For any installed PMC card that requires 12 V or 12 V these voltages must be supplied by the chassis Table A 1 provides an estimate of the typical and maximum current required from each of the input supply voltages Table A 1 Current Requirements Model Power MVME3100 Typical 4 5 A 22 5 W 5 V 0 No PMCs or peripherals attached Maxim
122. ter provides arbitration for the PMC sites on PCI bus B and the other provides arbitration for the PMCspan and USB host controller on PCI bus C The arbitration assignments on the MVME3100 are shown in the follow table so that software may set arbiter priority assignments if necessary Table 7 9 PCI Arbitration Assignments PCI Bus Arbitration Assignment PCI Master s A MPC8540 PCI REQ GNT 0 SATA Controller A MPC8540 PCI REQ GNT 1 TSI148 VME Controller A MPC8540 PCI REQ GNT 2 PCI6520 Bus A to Bus B bridge A MPC8540 PCI REQ GNT 3 PCI6520 Bus A to Bus C bridge B PCI6520 1S REQ GNT 0 PMC site 1 primary master B PCI6520 1S REQ GNT 1 PMC site 1 secondary master B PCI6520 1 S REQ GNT 2 PMC site 2 primary master B PCI6520 1 S REQ GNT 3 PMC site 2 secondary master C PCI6520 2 5 REQ GNT 0 USB Controller C PCI6520 2 5 REQ GNT 1 PMCspan 7 13 Clock Distribution The clock function generates and distributes all of the clocks required for system operation The clock tree is designed in such a manner as to maintain the strict edge to edge jitter and low clock to clock skew required by the devices Additional clocks required by individual devices are generated near the devices using individual oscillators Table 7 10 on page 137 lists 136 MVME3100 Single Board Computer Installation and Use 6806800M28C Programming Details the clocks required on the MVME3100 along with their frequency and source T
123. the MPC8540 I2C controller interface serial EEPROM for VPD Two 64KB serial 5 for user configuration data storage 256 byte serial EEPROM on SODIMM for SPD Maxim 051375 RTC Maxim DS1621 temperature sensor serial EEPROM on RTM VPD The Maxim DS1375 RTC implemented on the MVME3100 provides an alarm interrupt routed to the MPC8540 programmable interrupt controller PIC A Maxim DS32KHz temperature controlled crystal oscillator provides the RTC reference A battery backup circuit for the RTC is provided on board The Maxim DS1621 digital temperature sensor provides a measure of the temperature of the board The I C interface is also routed to the on board SODIMM socket This allows the serial presence detect SPD in the serial EEPROM which is located on the memory module to be read and used to configure the memory controller accordingly Similarly the I2C interface is routed to the P2 connector for access to the serial EEPROM located on the RTM The device address for the RTM serial EERPOM is user selectable using configuration switches on the RTM Refer to the MVME3100 Single Board Computer Programmer s Reference Guide in Appendix B Related Documentation for more information Ethernet Interfaces The MVME3100 provides one 10 100 and two 10 100 1000 Mb s full duplex Ethernet interfaces using the MPC8540 Fast Ethernet Controller FEC and two Triple Speed Ethernet Controllers TSEC A Broad
124. the MVME3100 alternate boot images are supported With alternate boot image support the boot loader code in the boot block examines the upper 8 MB of the flash bank for alternate boot images If an image is found control is passed to the image MVME3100 Single Board Computer Installation and Use 6806800M28C 65 MOTLoad Firmware 3 10 6 Boot Image Firmware Scan The scan is performed by examining each 1 boundary for a defined set of flags that identify the image as being POST USER or Alternate MOTLoad POST is a user developed Power On Self Test that would perform a set of diagnostics and then return to the boot loader image USER would be a boot image such as the VxWorks bootrom which would perform board initialization bootable VxWorks kernel would also be USER image Boot images are not restricted to being 1 MB or less in size however they must begin on I MB boundary within the 8 MB of the scanned flash bank The flash bank structure is shown below Address OxFFF00000 to OxFFFFFFFF Boot block Recovery code Usage OxFFEOOOOO to OXFFFFFFFF Backup MOTLoad image OxFFD00000 to OxFFDFFFFF First possible alternate image OxFFC00000 to OxFFCFFFFF Second possible alternate image Alternate boot images OxFF899999 to OxFF8FFFFF Bottom of flash flash size varies per product The scan is performed downwards beginning at the location of the first possible alternate image and searche
125. the VME backplane Refer to the TSi148 User s Manual listed in Appendix Related Documentation for additional details and or programming information Serial ATA Host Controller The sATA host controller uses the Silicon Image Sil3124A PCI X to Serial ATA Controller This device provides four sATA channels at 1 5Gb s and is compliant with the Serial ATA High speed serialized AT Attachment Specification Revision 1 0 It also supports the native command queuing feature of SATA Il The MVME3100 uses two of the four SATA channels Channel 0 is routed to a SATA connector mounted on the front panel for an external drive connection Channel 1 is routed to planar SATA connector for an inside the chassis drive connection Collocated with the planar connector is a SATA power connector The sATA controller can operate in legacy Native PCI IDE and Direct Port Access DPA mode The MVME3100 provides two programmable LEDs to indicate SATA channel activity Refer to the Sil3124A PCI X to Serial ATA Controller Datasheet listed in Appendix Related Documentation for additional details and or programming information PCI X to PCI X Bridges The MVME3100 uses two PLX PCI6520 PCI X to PCI X bridges to isolate the primary PCI bus bus A These bridges isolate bus A from bus B with the PMC sites and from bus C with the USB controller and PMCspan interface The PCI6520 is a 64 bit 133 MHz PCI X r1 0b compliant device It operates asynchronously betw
126. tion and Use 6806800M28C About this Manual Overview of Contents This manual is divided into the following chapters and appendices Hardware Preparation and Installation provides MVME3100 board preparation and installation instructions as well as ESD precautionary notes Startup and Operation provides the power up procedure and identifies the switches and indicators on the MVMEM3100 MOTLoad Firmware describes the basic features of the firmware product Functional Description describes the MVME3100 and the MVME721 RTM on block diagram level Pin Assignments provides pin assignments for various headers and connectors on the MMVE3100 single board computer Memory Maps provides information on memory maps and system and configuration registers Programming Details provides additional programming information including IDSEL mapping interrupt assignments for the MPC8540 interrupt controller Flash memory two wire serial interface addressing and other device and system considerations Specifications provides power requirements and environmental specifications Related Documentation provides a listing of related Emerson manuals vendor documentation and industry specifications Safety Notes summarizes the safety instructions in the manual Sicherheitshinweise is German translation of the Safety Notes chapter The MVME3100 Single Board Computer Installation and Use manual provides the information you
127. tions are made correctly you can apply power to the system When you are ready to apply power to the MVME3100 Verify that the chassis power supply voltage setting matches the voltage present in the country of use if the power supply in your system is not auto sensing e On powering up the MVME3100 brings up the MOTLoad prompt MVME3100 gt Switches and Indicators The MVME3100 board provides single push button switch that provides both abort and reset ABT RST functions When the switch is pressed for less than five seconds an abort interrupt is generated to the processor If the switch is held for more than five seconds a board hard reset is generated The board hard reset will reset the MPC8540 local PCI PCI X buses Ethernet PHYS serial ports Flash devices and PLD s If the MVME3100 is configured as the VME system controller the VME bus and local TSi148 reset input are also reset The MVME3100 has four front panel indicators The following table describes these indicators Table 2 1 Front Panel LED Status Indicators Function Label Color Description Board Fail FAIL Yellow Board has a failure After Power On or reset this LED is ON until extinguished by firmware or software User Defined USER 1 Green This indicator is illuminated by software assertion of its corresponding register bit MVME3100 Single Board Computer Installation and Use 6806800M28C 35 Startup and Operation Table 2 1 Fron
128. tput Module PLD Programmable Logic Device PMC PCI Mezzanine Card IEEE P1386 1 POST Power On S Test PrPMC Processor PMC QUART Quad Universal Asynchronous Receiver Transmitter RAM Random Access Memory RTC Real Time Clock RTM Rear Transition Module RTOS Real Time Operating System SATA Serial AT Attachment SBC Single Board Computer SDRAM Synchronous Dynamic Random Access Memory SIG Special Interest Group SMT Surface Mount Technology SNR receive data Poor SNR SPD Serial Presence Detect SROM Trivial File Transfer Protocol TSEC Triple Speed Ethernet Controllers 16 MVME3100 Single Board Computer Installation and Use 6806800M28C About this Manual Abbreviation Description TSOP Thin Small Outline Package UART Universal Asynchronous Receiver Transmitter UNIX UNIX operating system USB Universal Serial Bus VIO Input Output Voltage VITA VMEbus International Trade Association VME VersaModule Eurocard VMEbus VersaModule Eurocard bus VPD Vital Product Data WP Write Protect Conventions The following table describes the conventions used throughout this manual Notation Description 0x00000000 Typical notation for hexadecimal numbers digits are O through F for example used for addresses and offsets 0b0000 Same for binary numbers digits are 0 and 1 bold Used to emphasize a word Screen Used for on screen output and code related ele
129. tting interpreted as follows Outbound Image Attribute Register 80001061 Outbound Image Starting Address Upper Register 00000000 Outbound Image Starting Address Lower Register B3FF0000 Outbound Image Ending Address Upper Register 00000000 Outbound Image Ending Address Lower Register B3FF0000 Outbound Image Translation Offset Upper Register 00000000 Outbound Image Translation Offset Lower Register 4C000000 Outbound Image 2eSST Broadcast Select Register 00000000 MVME3100 3 3 3 3 3 3 3 3 Outbound window 3 OTAT3 is enabled 2eSST timing at SST320 transfer mode of SCT A16 D32 Supervisory access The window accepts transfers on the PCI X Local Bus from OxB3FF0000 0xB3FF0000 and translates them onto the VMEbus using an offset of 0x4C000000 thus an access to on the PCI X Local Bus becomes an access to OxFFFF0000 on the VMEbus MVME3100 gt vmeCfg s 07 Displaying the selected Default VME Setting interpreted as follows Outbound Image 7 Attribute Register 80001065 Outbound Image 7 Starting Address Upper Register 00000000 Outbound Image Starting Address Lower Register B1000000 Outbound Image Ending Address Upper Register 00000000 Outbound Image Ending Address Lower Register BIFF0000 I I MVME3100 Single Board Computer Installation and Use 6806800M28C MOTLoad Firmware Outbound Image 7 Translation Offset Upper Register
130. tting OFF Factory Default ON Normal MPC8540 TRST Isolates the board mode where the board HRESET from TRST and allows the board to reset without resetting the MPC8540 JTAG COP interface Geographical Address Switch S3 The TSi148 VMEbus Status register provides the VMEbus geographical address of the MVME3100 This switch reflects the inverted states of the geographical address signals Notes This switch should remain in the OFF position unless MPC8540 emulator is attached Applications not using the 5 row backplane can use the geographical address switch to assign a geographical address Figure 1 2 Geographical Address Switch Settings 1 16 1 16 Not used Not used PCI X mode PCI X mode GAP 0 GAP 1 GA4 0 GA4 1 GA3 0 GAS 1 GA2 0 GA2 1 GA1 0 GA1 1 GAO 0 GAO 1 Factory Default Table 1 3 Geographical Address Switch Assignments Position SW1 sw2 SW3 SW4 SW5 SW6 SW7 SW8 Function Not PCI Bus GAP GA4 GA3 GA2 GA1 GAO Used Amode MVME3100 Single Board Computer Installation and Use 6806800M28C 27 Hardware Preparation and Installation Table 1 3 Geographical Address Switch Assignments continued Position SW1 sw sw3 SW4 SW5 SW6 SW7 SW8 Factory OFF OFF OFF OFF OFF OFF OFF OFF Setting PCI 1 1 1 1 1 1 Default mode
131. um 5 6 A 28 W 5 0 V In 3 row chassis PMC current should be limited to 32 watts total of both PMC slots In a 5 row chassis the PMC sites can support a total of 50 watts A 2 Environmental Specifications Table A 2 lists the environmental specifications along with the board dimensions Table A 2 MVME3 100 Specifications Characteristics Specifications Operating Temperature 0 to 55 C 32 F to 131 F or inlet air temperature with forced air cooling Storage Temperature 40 to 85 C 40 F to 185 F Relative Humidity Operating 5 to 90 non condensing Non operating 5 to 90 non condensing Vibration Operating 6 Gs RMS 5 200 Hz sine Non operating 6 Gs RMS 20 2000 Hz random Physical Dimensions 6U 4HP wide 233 4 mm x 160 mm x 19 8 mm 9 2 in x 6 3 in x 0 8 in Weight 468 g 16 5 oz IEEE handles MTBF 122 480 hours calculated based on MIL HDBK 217F Notice 1 MVME3100 Single Board Computer Installation and Use 6806800M28C 139 Specifications A 3 The following table summarizes components that exhibit significant temperature rises These are the components that should be monitored in order to assess thermal performance The NOTICE Product Damage High humidity and condensation on surfaces cause short circuits Do not operate the product outside the specified environmental limits Make sure the product is completely dry and there is no moistu
132. ware prompt Firmware vmeCfg s r40C Displays User AM Codes Register state vmeCfg s rF70 Displays VMEbus Register Access Image Control Register state 3 5 4 Editing VME Settings To edit the changeable VME setting type the following at the firmware prompt vmeCfg m Edits Master Enable state vmeCfg i 0 7 Edits selected Inbound Window state vmeCfg 0 7 Edits selected Outbound Window state vmeCfg r184 Edits PCI Miscellaneous Register state vmeCfg r188 Edits Special PCI Target Image Register state vmeCfg e r400 Edits Master Control Register state vmeCfg e r404 Edits Miscellaneous Control Register state vmeCfg r40C Edits User AM Codes Register state vmeCfg e rF70 Edits VMEbus Register Access Image Control Register state MVME3100 Single Board Computer Installation and Use 6806800M28C MOTLoad Firmware 3 5 5 Deleting VME Settings To delete the changeable VME setting restore default value type the following at the firmware prompt vmeCfg d m Deletes Master Enable state vmeCfg d i 0 7 Deletes selected Inbound Window state vmeCfg d o 0 7 Deletes selected Outbound Window state vmeCfg d r184 Deletes PCI Miscellaneous Register state vmeCfg d r188 Deletes Special PCI Target Image Register state vmeCfg d r400 Deletes Master Control Register state vmeCfg d r404 Deletes Miscellaneous Control Register state
133. y the end of input MOTLoad then performs the specified action An example of a MOTLoad command line promptis shown below The MOTLoad prompt changes according to what product it is used on for example MVME5500 MVME6100 MVME3100 Example MVME3100 gt If an invalid MOTLoad command is entered at the MOTLoad command line prompt MOTLoad displays a message that the command was not found Example 48 MVME3100 Single Board Computer Installation and Use 6806800M28C MOTLoad Firmware MVME3100 gt mytest mytest not found MVME3100 gt If the user enters a partial MOTLoad command string that can be resolved to a unique valid MOTLoad command and presses the carriage return key the command will be executed as if the entire command string had been entered This feature is a user input shortcut that minimizes the required amount of command line input MOTLoad is an ever changing firmware package so user input shortcuts may change as command additions are made Example MVME3100 gt version Copyright Motorola Inc 1999 2002 All Rights Reserved MOTLoad RTOS Version 2 0 PAL Version 0 1 Motorola MVME3100 Example MVME3100 gt ver Copyright Motorola Inc 1999 2002 All Rights Reserved MOTLoad RTOS Version 2 0 PAL Version 0 1 Motorola MVME3100 If the partial command string cannot be resolved to a single unique command MOTLoad will inform the user that the command was ambiguous Example M
134. you need to do Refer to Connect any other equipment you will be using Connecting to Peripherals on page 31 Verify the hardware is installed Completing the Installation on page 33 1 2 2 Unpacking Guidelines Unpack the equipment from the shipping carton Refer to the packing list and verify that all items are present Save the packing material for storing and reshipping of equipment If the shipping carton is damaged upon receipt request that the carrier s agent be present during the unpacking and inspection of the equipment Damage of Circuits Electrostatic discharge and incorrect installation and removal of the product can damage circuits or shorten their life Before touching the product make sure that your are working in an ESD safe environment or wear an ESD wrist strap or ESD shoes Hold the product by its edges and do not touch any components or circuits 1 3 Declaration of Conformity For Declaration of Conformity refer MVME3100 Series Declaration of Conformity 1 4 Configuring Hardware This section discusses certain hardware and software tasks that may need to be performed prior to installing the board in a chassis To produce the desired configuration and ensure proper operation of the MVME3100 you may need to carry out certain hardware modifications before installing the module 22 MVME3100 Single Board Computer Installation and Use 6806800M28C Hardware Preparation and Installation

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