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Agilent Technologies 01664

1. Pin Signal Pin Signal 1 5 00 V 11 5 20 V 2 5 00 V 12 Ground 3 5 00 V 13 12 V 4 5 00 V 14 Ground 5 Ground Digital 15 12V 6 Ground Digital 16 Ground 7 Ground Digital 17 12 V Display 8 Ground Display 18 5 20 V 9 3 50 V 19 15 V Fan 10 Ground 20 Ground Fan A 0 500V Pin 1 Front af o 5 00V Instrument oO 5 00V QO 5 00V O Ground Display O Ground Display O Ground Display O Ground Display OO 3 50V O Ground ELH 5 20V O Ground Ol 12V O Ground Ol 12V O Ground O 12V Display QO 5 20V LJ 15V Fan 01660033 HI Ground Fan Pin 20 WARNING Troubleshooting To test the CRT monitor signals To test the CRT monitor signals Refer to chapter 6 Replacing Assemblies for instructions to remove or replace covers and assemblies Hazard voltages exist on the power supply the CRT and the CRT driver board This procedure is to be performed by service trained personnel aware of the hazards involved such as fire and electrical shock Remove the cover of the instrument Check the CRT monitor input cable for the signals and the power supplies listed in the table below The cable is the wide ribbon cable connecting the monitor to the acquisition board CRT Monitor Cable Signals Pin Signal Pin Signal 1 NC 2 12V 3 Ground 4 Ground 5 12V 6 Ground 7 12V 8 Ground 9 12V 10 HSYNC 11 VSYNC 12 12V
2. 0101010101010101 1010101010101010 9 If the display looks like the figure then the cable passed the test If the display does not look similar to the figure then there is a possible problem with the cable or probe tip assembly Causes for cable test failures include the following e open channel e channel shorted to a neighboring channel e channel shorted to either ground or a supply voltage Return to the troubleshooting flowchart 5 31 Troubleshooting To test the auxiliary power To test the auxiliary power The 5 V auxiliary power is protected by a current overload protection device If the current on pins 1 and 39 exceed 0 33 amps the circuit will open When the short is removed the circuit will reset in approximately 1 minute There should be 5 V after the 1 minute reset time Equipment Required Equipment Critical Specifications Recommended Model Part Digital Multimeter 0 1 mV resolution better than Agilent 3478A 0 005 accuracy e Using the multimeter verify the 5 V on pins 1 and 39 of the probe cables 1 5V 2 GND 39 5V MISCZEX5 5 32 To remove and replace the Handle 6 5 Feet and tilt stand 6 5 Cover 6 5 Disk drive 6 6 Power supply 6 7 Main circuit board 6 7 Switch actuator assembly 6 8 Rear panel assembly 6 9 Front panel and keyboard 6 10 Intensity adjustment 6 10 Monitor 6 11 Handle plate 6 11 Fan 6 12 Line filter 6 12
3. c Select Master Clock then select a double edge for the clock of the pod under test Turn off the other clocks analyzer Format MACHINE 1 Run State Acquisition Mode aster C Full Channel 4k Memory SOMHz JI Symbols Master Clock d Inthe Master Clock menu select Setup Hold then select 4 0 0 0 ns for the pod being tested Select Done Select Done again to exit the Master Clock menu analyzer Format MACHINE 1 Run State Acquisition Mode Full Channel 4k Memory 50MHz 3 5 0 5 ns 3 0 1 0 ns ds A1 A2 2 5 1 5 ns Te 2 0 2 0 ns 1 5 2 5 ns 1 0 3 0 ns 0 5 3 5 ns 5 29 Troubleshooting To test the logic analyzer probe cables e Select the field to the right of the pod being tested then select TTL Analyzer Format MACHINE 1 State Acquisition Mode Master Clock Full Channel 4k Memory SOMHz jt Jt Clock Inputs Pod A2 TTL Master Clock _ Labels Labi Lab2 Lab3 Lab4 Labs Lave Lab i Lab 5 Set up the Trigger menu a Press the Trigger key b Select Clear Trigger then select All Analyzer Trigger MACHINE 1 Print Modify Sequence Level State Sequence Lev Arming While storing anystate Control Q TRIGGER on a 1 time Replace Sequence Level icquisition Store anystate Delete Sequence Level Control Add Sequ
4. 01664B12 5 13 Troubleshooting To use the flowcharts GP IB RS 232 No CHART 12 OPTION INSTALLED PERFORM GP IB SELF TEST DOES SELF TEST PASS REPLACE MAIN CIRCUIT ASSEMBLY VERIFY GP IB CONFIGURATION CONFIGURATIONS OK RECONFIGURE GP IB CHECK GP IB CABLE IS m SEATED ON SOCKET ON MAIN CIRCUIT ASSEMBLY PERFORM RS 232C EXTERNAL LOOPBACK TEST IS CABLE SEATED DOES TEST PASS RESEAT CABLE CHECK CABLE CONTINUITY RS 232C GP B CABLES SWITCHED ON MAIN CIRCUIT ASSEMBLY IS CABLE GOOD SWITCH CABLES AND RE RUN RS 232C TEST sy Troubleshooting Flowchart 12 REPLACE CABLE REPLACE MAIN CIRCUIT ASSEMBLY 01664B13 5 14 Troubleshooting To check the power up tests To check the power up tests The logic analyzer automatically performs power up tests when you apply power to the instrument during the boot up sequence The revision number of the operating system shows in the upper right corner of the screen during these power up tests As each test completes either passed or failed prints on the screen in front of the name of each test 1 Disconnect all inputs then insert the operating system disk into the disk drive 2 Let the instrument warm up for a few minutes then cycle
5. To use the flowcharts 5 2 To check the power up tests 5 15 To run the self tests 5 16 To test the power supply voltages 5 21 To test the CRT monitor signals 5 23 To test the keyboard signals 5 24 To test the disk drive voltages 5 25 To perform the BNC test 5 27 To test the logic analyzer probe cables 5 28 To test the auxiliary power 5 32 Troubleshooting CAUTION Troubleshooting This chapter helps you troubleshoot the logic analyzer to find defective assemblies The troubleshooting consists of flowcharts self test instructions and tests This information is not intended for component level repair If you suspect a problem start at the top of the first flowchart During the troubleshooting instructions the flowcharts will direct you to perform other tests The service strategy for this instrument is the replacement of defective assemblies This instrument can be returned to Agilent Technologies for all service work including troubleshooting Contact your nearest Agilent Technologies Sales Office for more details Electrostatic discharge can damage electronic components Use grounded wriststraps and mats when you perform any service to this instrument or to the cards in it To use the flowcharts Flowcharts are the primary tool used to isolate defective assemblies The flowcharts refer to other tests to help isolate the trouble The circled letters on the charts indicate connections with the other fl
6. 1 3000 V d Inthe oscilloscope Delta T menu select Start On Neg Edge 1 Select Stop on Pos Edge 1 e Ifthe pulse width is outside the limits adjust the pulse generator channel 2 width and select the oscilloscope Precision Edge Find until the pulse width is within limits 3 31 Testing Performance To test the single clock single edge state acquisition 10 Using the Delay mode of the pulse generator channel 1 position the pulses according to the setup hold combination selected 0 0 ps or 100 ps a Inthe oscilloscope Delta V menu set the Marker 1 Position to Chan 1 then set Marker 1 at 1 3000 V Set the Marker 2 Position to Chan 2 then set Marker 2 at 1 3000 V b In the oscilloscope Delta T menu select Start on Pos Edge 1 Select Stop on Neg Edge 1 c Adjust the pulse generator channel 1 Delay then select Precision Edge Find in the oscilloscope Delta T menu Repeat this step until the pulses are aligned according to the setup time of the setup hold combination selected 11 Select the clock to be tested a Inthe Master Clock menu select the clock field to be tested then select the clock edge as indicated in the table The first time through this test use the top clock and edge Clocks J KL b Connect the clock to be tested to the pulse generator channel 2 output c Select Done to exit the Master Clock menu see illustration Analyzer Format MACHINE 1 Run State Acquisition
7. 218mm a foggq0eas gj 367mm l 17 4 442mm 01664e10 Weight 26 lb 1 8 kg 1 6 Product Regulations Safety EMC Emissions Immunity Performance Codes General Information Supplemental Characteristics IEC 348 UL 1244 CSA Standard C22 2 No 231 Series M 89 This product meets the requirement of the European Communities EC EMC Directive 89 336 KEC EN55011 CSIPR 11 GSM Group1 Class A equipment SABS RAA Act No 24 1990 EN50082 1 Code Notes IEC 801 2 ESD 4kV CD 8kV AD 2 IEC 801 3 Rad 3V m 1 IEC 801 4 EFT 1kV 2 1 PASS Normal operations no effect 2 PASS Temporary degradation self recoverable 3 PASS Temporary degradation operator intervention required 4 FAIL Not recoverable component damage 2Notes None 1 7 General Information Recommended Test Equipment Recommended Test Equipment Equipment Required Equipment Pulse Generator Digitizing Oscilloscope Function Generator Digital Multimeter BNC Banana Cable BNC Tee Cable SMA Coax Cable Oty 3 Adapter Qty 4 Adapter Coupler Oty 4 20 1 Probes Qty 2 BNC Test Connector 17x2 Qty 1 BNC Test Connector 6x2 Qty 4 Digitizing Oscilloscope BNC Shorting Cap BNC Banana Adapter Light Power Meter Alignment Tool A Adjustment P Performance Tests Critical Sp
8. Change Dir Utilities H_system Execute DOS Filename Date le Description PYTEST_ 6Sep94 St 217600 HP1664 System Test Prog 01 00 PY_032 8Sep94 151 51968 HP1664 Analyzer Test Prog O1 00 SYSTEM 6Sep94 Sit 238336 HP1664 System Software 0O1 00 SY S_032 8Sep94 Ste 530432 HP1664 Analyzer Software Y01 00 PHD DOS Disk Space bytes Total 1474560 Free 418816 3 Select the box labeled Load Test System then press the Select key Load the disk containing the performance verification self tests into the disk drive normally the same as the boot disk 4 Select the box labeled Continue and press the Select key 5 After the test files have been loaded the Analy PV menu is displayed Select All Analyzer Tests You can run all tests at one time except for the Data Input Inspection by running All Analyzer Tests To see more details about each test when troubleshooting failures you can run each test individually This example shows how to run all tests at once When the tests finish the status for each test shows Passed or Failed and the status for the All Analyzer Tests changes from Untested to Tested Analy PY Data Input Inspection Board Tests status PASSED Chip 5 Tests All Analyzer Tests status PASSED status TESTED 6 Select Analy PV then select Sys PV in the pop up menu 3 3 R 10 Testing Performance To perform the self tests Select the Printer Controller
9. 2 Disable the pulse generator channel 2 COMP with the LED off 3 Using the Delay mode of the pulse generator channel 1 position the pulses according to the setup time of the setup hold combination selected 0 0 ps or 100 ps a Inthe oscilloscope Delta V menu set the Marker 1 Position to Chan 1 then set Marker 1 at 1 3000 V Set the Marker 2 Position to Chan 2 then set Marker 2 at 1 3000 V b In the oscilloscope Delta T menu select Start on Pos Edge 1 Select Stop on Pos Edge 1 3 40 Testing Performance To test the multiple clock multiple edge state acquisition c Adjust the pulse generator channel 1 Delay then select Precision Edge Find in the oscilloscope Delta T menu Repeat this step until the pulses are aligned according to the setup time of the setup hold combination selected 0 0 ps or 100 ps l i Dee ee et pY 4 Select the clocks to be tested a Select the clock field to be tested and then select JT KT as the clock edges b Select Done to exit the Master Clock menu analyzer Format MACHINE 1 Run State Acquisition Mode Master Clock Full Channel 2K Memory SOMHz i Symbols Master Clock ouais oorr And oa ort Setup Hold 3 41 Testing Performance To test the multiple clock multiple edge state acquisition If you have not already created a Compare file for the previous test single clock single edge state acquisition page 3 31 use the f
10. Service Guide Publication number 01664 97005 Second edition January 2000 For Safety information Warranties and Regulatory information see the pages at the end of the book Copyright Agilent Technologies 1987 2000 All Rights Reserved Agilent Technologies 1664A Logic Analyzer Agilent Technologies 1664A Logic Analyzer The Agilent Technologies 1664A is a 50 MHz State 500 MHz Timing Logic Analyzer Features Some of the main features of the 1664A Logic Analyzer is as follows 32 data channels and 2 clock data channels 3 5 inch disk drive Centronix parallel interface with GPIB and RS 232C interfaces available as options Variable setup hold time 4 kbytes deep memory on all channels with 8 kbytes in half channel mode Marker measurements 12 levels of trigger sequencing for state and 10 levels of sequential triggering for timing 100 MHz time and number of states tagging Full programmability with optional interface Service Strategy The service strategy for this instrument is the replacement of defective assemblies This service guide contains information for finding a defective assembly by testing and servicing the 1664A This logic analyzer can be returned to Agilent Technologies for all service work including troubleshooting Contact your nearest Agilent Technologies Sales Office for more details il E24 01660 The Agilent Technologies 1664A Logic A
11. LOW BRIGHT k 5 o o a SUBBRIGHT FOCUS CONTRAST Yoke ee V LIN a V SIZE LO V HOLD H HOLD 1668E22 6 If the grid pattern is not centered horizontally adjust the H Hold 7 If you need to adjust the intensity go to the next page If you are finished with the adjustments turn off the instrument then remove the power cord Install the cover on the instrument 4 4 WARNING To adjust the CRT intensity Do not touch the CRT monitor sweep board High voltages exist on the sweep board that can cause personal injury Equipment Required Equipment Critical Specification Recommended Model Part Alignment Tool 1 8710 1300 Light Power Meter United Detector 351 Turn off the logic analyzer then disconnect the power cord Remove the cover Refer to chapter 6 Replacing Assemblies for instructions to remove the cover Connect the power cord insert the operating system disk then turn on the logic analyzer Access the Display Test e If you just finished adjusting the CRT monitor alignment go to step 4 e To Access the Display Test perform the following steps a Insert the disk containing the functional performance verification tests normally the same disk into the disk drive then load the functional performance verification operating system into the logic analyzer refer to Chapter 3 To Perform The Self Tests b Enter the Sys PV tests and enter the Display Tes
12. Optional GPIB and or RS 232C cables 6 13 To return assemblies 6 14 Replacing Assemblies WARNING CAUTION CAUTION Replacing Assemblies This chapter contains the instructions for removing and replacing the assemblies of the logic analyzer Also in this chapter are instructions for returning assemblies Hazardous voltages exist on the power supply the CRT and the CRT driver board To avoid electrical shock disconnect the power from the instrument before performing the following procedures After disconnecting the power wait at least three minutes for the capacitors on the power supply board and the CRT driver board to discharge before servicing the instrument Damage can occur to electronic components if you remove or replace assemblies when the instrument is on or when the power cable is connected Never attempt to remove or install any assembly with the instrument on or with the power cable connected Replacement Strategy These replacement procedures are organized as if disassembling the complete instrument from the first assembly to be removed to the last Some procedures say to remove other assemblies of the instrument but do not give complete instructions Refer to the procedure for that specific assembly for the instructions Use the exploded view of the instrument on the next page as a reference during the replacement procedures Electrostatic discharge can damage electronic components Use gro
13. To make the test connectors The test connectors connect the logic analyzer to the test equipment Materials Required Description Recommended Part Qty BNC f Connector Agilent 1250 1032 5 100 Q 1 resistor Agilent 0698 7212 8 Berg Strip 17 by 2 1 Berg Strip 6 by 2 4 20 1 Probe Agilent 54006A 2 Jumper wire 1 Build four test connectors using BNC connectors and 6 by 2 sections of Berg strip a Solder a jumper wire to all pins on one side of the Berg strip b Solder a jumper wire to all pins on the other side of the Berg strip Solder two resistors to the Berg strip one at each end between the end pins Solder the center of the BNC connector to the center pin of one row on the Berg strip ond Solder the ground tab of the BNC connector to the center pin of the other row on the Berg strip f On two of the test connectors solder a 20 1 probe The probe ground goes to the same row of pins on the test connector as the BNC ground tab o Jumper 2 a 20 1 Probe 100 ohm 1 RF Resistor 2 6x2 Berg Strip BNC Panel Mount Connector 16550E06 3 6 Testing Performance To make the test connectors 2 Build one test connector using a BNC connector and a 17 by 2 section of Berg strip a Solder a jumper wire to all pins on one side of the Berg strip b Solder a jumper wire to all pins on the other side of the Berg strip c Solder the center of the BNC connector to the center pin of one row on the Berg str
14. should be used Do not use repaired fuses or short circuited fuseholders To do so could cause a shock of fire hazard e Service instructions are for trained service personnel To avoid dangerous electric shock do not perform any service unless qualified to do so Do not attempt internal service or adjustment unless another person capable of rendering first aid and resuscitation is present e If you energize this instrument by an auto transformer for voltage reduction make sure the common terminal is connected to the earth terminal of the power source e Whenever it is likely that the ground protection is impaired you must make the instrument inoperative and secure it against any unintended operation Do not operate the instrument in the presence of flammable gasses or fumes Operation of any electrical instrument in such an environment constitutes a definite safety hazard Do not install substitute parts or perform any unauthorized modification to the instrument e Capacitors inside the instrument may retain a charge even if the instrument is disconnected from its source of supply e Use caution when exposing or handling the CRT Handling or replacing the CRT shall be done only by qualified maintenance personnel Safety Symbols A Instruction manual symbol the product is marked with this symbol when it is necessary for you to refer to the instruction manualin order to protect against damage to
15. the product Hazardous voltage symbol Earth terminal symbol Used to indicate a circuit common connected to grounded chassis WARNING The Warning sign denotes a hazard It calls attention to a procedure practice or the like which if not correctly performed or adhered to could result in personal injury Do not proceed beyond a Warning sign until the indicated conditions are fully understood and met CAUTION The Caution sign denotes a hazard It calls attention to an operating procedure practice or the like which if not correctly performed or adhered to could result in damage to or destruction of part or all of the product Do not proceed beyond a Caution symbol until the indicated conditions are fully understood or met Agilent Technologies P O Box 2197 1900 Garden of the Gods Road Colorado Springs CO 80901 Product Warranty This Agilent Technologies product has a warranty against defects in material and workmanship for a period of one year from date of shipment During the warranty period Agilent Technologies will at its option either repair or replace products that prove to be defective For warranty service or repair this product must be returned to a service facility designated by Agilent Technologies For products returned to Agilent Technologies for warranty service the Buyer shall prepay shipping charges to Agilent Technologies and Agilent Technologies shall pay shippi
16. 01664808 an Troubleshooting To use the flowcharts CHART 7 NOTE VERIFY THAT THERE ARE NO BENT OR BROKEN PINS ON THE SYSTEM BOARD CABLE CONNECTOR HP PART NUMBER 1252 4181 5 9 Troubleshooting To use the flowcharts CHART 1 CHART 8 DOES PRINTER OPERATE AT ALL DOES PRINTER OPERATE AT ALL REPLACE PRINTER WITH KNOWN GOOD PRINTER CHECK CABLE CONTINUITY AND RESEAT CABLE t REPLACE SUSPECT YES PRINTER DOES PRINTER OPERATE AT ALL ARE RANDOM CHARACTERS BEING PRINTED NO YES REPLACE MAIN CIRCUIT CHECK PRINTER CONFIGURATION ASSEMBLY PRINTER TYPE SHOULD MATCH PRINTER BEING USED DOES PRINTER TYPE MATCH PRINTER BEING USED OBTAIN PRINTER THAT IS SUPPORTED BY LOGIC gt ANALYZER CHANGE PRINTER TYPE SELECTION 01664809 Troubleshooting Flowchart 8 5 10 DOES HIL TEST PASS REPLACE MAIN CIRCUIT ASSEMBLY Troubleshooting To use the flowcharts CHART 9 DO THE FRONT PANEL KEYPAD TEST AND EXERCISE RPG DOES RPG WORK CONNECT KNOWN GOOD EXTERNAL KEYBOARD OR MOUSE TO EXTERNAL KEYBOARD CONNECTOR DOES KEYBOARD OR MOUSE CURSOR APPEAR IS FRONT PANEL CABLE CONNECTED DOES KEYBOARD OR MOUSE OPERATE PROPERLY CHECK FRONT PANEL
17. 22 P Q TWISTED PAIR WITH 1 ATN MRE 11 23 P Q TWISTED PAIR WITH 11 SHIELD 12 24 SIGNAL GROUND APEN 2 TYPE 57 MICRORIBBON CONNECTOR GPIB Interface Connector RS 232C Optional The logic analyzer interfaces with RS 232C communication lines through a standard 25 pin D connector The logic analyzer is compatible with RS 232C protocol When a hardwire handshake method is used the Data Terminal Ready DTR line pin 20 on the connector is used to signal if space is available for more data in the logical I O buffer Pin outs of the RS 232C connectors are listed in the following table RS 232C Signal Definitions Pin Function Number 1 Protective Ground 2 Transmitted Data TD 3 Received Data RD 4 Request to Send RTS 5 Clear to Send CTS 6 Data Set Ready DSR 7 Signal Ground 8 Data Carrier Detect DCD 20 Data Terminal Ready DTR 23 Data Signal Rate Selector RS 232C Standard AA BA BB CA CB CC AB CF cD CH CI Signal Direction and Level Not applicable Data from Mainframe High Space 0 12 V Low Mark 1 12 V Data to Mainframe High Space 0 3 V to 25 V Low Mark 1 3 V to 25 V Signal from Mainframe High ON 12 V Low OFF 12 V Signal to Mainframe High ON 3 V to 12 V Low OFF 3 V to 25 V Signal to Mainframe High ON 3 V to 25 V Low OFF 3 V to 25 V Not applicable Signal to Mainframe Hi
18. 3 50 NOTE Testing Performance To test the single clock multiple edge state acquisition Check the setup hold combination 1 Select the logic analyzer setup hold time a Inthe logic analyzer Format menu select Master Clock The first time through this test assign the clocks according to the first testing combination in step 3 of these procedures b Inthe Master Clock menu select Setup Hold c Inthe Setup Hold menu select the setup hold field then select for all pods the setup hold combination to be tested The first time through this test use the top combination in the following table Setup Hold Combinations 4 0 0 0 ns 0 0 4 0 ns 2 0 2 0 ns d Select Done to exit the setup hold combinations analyzer Format MACHINE 1 Run State Acquisition Mode Full Channel 2K Memory SOMHz TORE 0 5 4 0 ns Symbols 4 0 0 5 ns 0 0 4 5 ns 3 5 1 0 ns ds AI A2 3 0 1 5 ns E 2 5 2 0 ns 2 0 2 5 ns 1 5 3 0 ns 1 0 3 5 ns Using the Delay mode of the pulse generator Channel 2 position the pulses according to the setup time of the setup hold combination selected 0 0 ps or 100 0 ps a Inthe oscilloscope Delta V menu set the Marker 1 Position to Chan 1 then set Marker 1 at 1 3000 V Set the Marker 2 Position to Chan 2 then set Marker 2 at 1 3000 V b In the oscilloscope Delta T menu select Start on Pos Edge 1 Select Stop on Pos Edge 1 Select Precisio
19. CABLE FOR CONTINUITY a al AND RECONNECT REPLACE FRONT PANEL BOARD DOES HIL TEST PASS YES Troubleshooting Flowchart 9 REPLACE MAIN CIRCUIT ASSEMBLY 01664B10 END 5 11 Troubleshooting To use the flowcharts CHART 1 CHART 10 PERFORM BNC TEST PROBLEM STILL PRESENT DOES TEST PASS NO PANEL CONNECTED TO MAIN CIRCUIT ASSEMBLY CONNECT CABLES REPLACE MAIN CIRCUIT ASSEMBLY 01664B11 Troubleshooting Flowchart 10 5 12 GP IB RS 232 OPTION INSTALLED INSTALL GP IB RS 232 OPTION Troubleshooting To use the flowcharts CHART 11 DOES INTERNAL LOOPBACK TEST FAIL REPLACE MAIN CIRCUIT ASSEMBLY DOES EXTERNAL LOOPBACK TEST FAIL VERIFY RS 232C CONFIGURATION INSTALL CONNECTOR ON RS 232C PORT AND RE RUN TEST LOOPBACK CONNECTOR INSTALLED 2 DOES EXTERNAL LOOPBACK TEST FAIL CHECK RS 232C CABLE IS SEATED IN CORRECT SOCKET ON MAIN CIRCUIT ASSEMBLY RESEAT CABLE AND RE RUN TEST IS CABLE SEATED DOES EXTERNAL LOOP BACK TEST FAIL IS CABLE GOOD CHECK RS 232C CABLE CONTINUITY Troubleshooting Flowchart 11 REPLACE CABLE pO REPLACE MAIN CIRCUIT ASSEMBLY
20. CRT driver board up out of the chassis Using a nut driver remove the three hex nuts attaching the monitor and ground bracket to the chassis then remove the screw Slide the monitor assembly and ground bracket to the rear and up out of the chassis Reverse this procedure to install the monitor When installing the CRT driver board check that the board is properly inserted in the circuit board tracks To remove and replace the handle plate Using previous procedures remove the following assemblies e Handle e Rear Feet e Cover Remove the four screens that attach the handle plate to the chassis Remove the handle plate To remove the handle plate align the plate toward the front of the instrument then move it up and out of the instrument Reverse this procedure to install the handle plate 6 11 ao a fF WwW WD aoa aA Fw WD Replacing Assemblies To remove and replace the fan To remove and replace the fan Using previous procedures remove the following assemblies e Handle e Rear Feet e Cover e Disk Drive e Power Supply e Rear Panel Disconnect the fan cable from the main circuit board Remove the four fan screws Lift the fan away from the rear panel Lift the fan guard away from the rear panel Reverse this procedure to install the fan When installing the fan verify the correct orientation of the fan If you mount the fan backwards the instrument will overheat Also check the corr
21. REPLACE MAIN CIRCUIT ASSEMBLY Troubleshooting Flowchart 2 01664803 Troubleshooting To use the flowcharts CHART 1 CHART 3 REMOVE SWEEP CABLE FROM CRT DRIVER BOARD POUR SWEEF CABCE REPLACE CRT SUPPLY VOLTAGES CONTINUITY MONITOR ASSEMBLY OK OK REMOVE DISK DRIVE CABLE FROM DISK DRIVE REPLACE SWEEP CARTE POWER SUPPLY VOLTAGES ae PEA L gs CABLE CONTINUITY DRIVE ASSEMBLY OK OK REMOVE POWER SUPPLY CABLE FROM MAIN CIRCUIT REPLACE SWEEP CABLE _ ASSEMBLY POWER POWER SUPPLY REPLACE MAIN CIRCUIT o SUPPLY VOLTAGES CABLE CONTINUITY ASSENGA OK OK REPLACE POWER SUPPLY CABLE g 01664B04 REPLACE POWER SUPPLY ASSEMBLY Troubleshooting Flowchart 3 Troubleshooting To use the flowcharts CHART 1 CHART 4 DISCONNECT SWEEP CABLE FROM CRT DRIVER BOARD Y CHECK FOR VOLTAGES AND SIGNALS VOLTAGES AND SIGNALS OK YES REPLACE CRT MONITOR ASSEMBLY SWEEP CABLE CONTINUITY OK REPLACE SWEEP CABLE n a REPLACE MAIN CIRCUIT ASSEMBLY 01664805 Troubleshooting Flowchart 4 5 6 Troubleshooting To use the flowcharts RARI CHART 5 PERFORM FRONT PANEL KEYBOARD SELF TEST PASS YES SELF TEST NO Y CHECK SIGNAL INPUT TO KEYBO
22. Required Equipment Critical Specifications Recommended Model Part Pulse Generator 100 MHz 3 5 ns pulse width lt 600 ps rise time Agilent 8131A Option 020 Digitizing Oscilloscope gt 6 GHz bandwidth lt 58 ps rise time Agilent 54121T SMA Coax 18 GHz bandwidth Agilent 8120 4948 Qty 3 Adapter Qty 4 SMA m BNC f Agilent 1250 1200 Coupler Oty 4 BNC m m Agilent 1250 0216 BNC Test Connector 6x2 Qty 4 Set up the equipment Turn on the equipment required and the logic analyzer Let them warm up for 30 minutes before beginning the test if you have not already done so Set up the pulse generator Pulse Generator Setup Channel 1 Channel 2 Period Delay 0 ps Delay Ops 22 0 ns Width 3 5 ns Width 3 5 ns High 0 9 V High 0 9 V Low 1 7 V Low 1 7 V 3 17 Testing Performance To test the glitch capture Set up the oscilloscope Oscilloscope Setup Time Base Display Delta V Delta T Time Div 1 00 ns div mode avg V markers on T markers on delay 17 7000 ns of avg 16 marker 1 position Chan 1 start on Pos Edge 1 screens dual marker 2 position Chan 2 stop on Pos Edge 1 Channel Channel 1 Channel 2 Display on on Probe Atten 20 00 20 00 Volts Div 400 mV 400 mV Offset 1 3000 V 1 3000 V Set up the logic analyzer Press the Config key Assign all pod fields to Machine 1 To assign the pod fields select the pod fields then select Machine 1 in the pop
23. To order using the direct mail order system contact your nearest Agilent Technologies Sales Office Within the USA Agilent Technologies can supply parts through a direct mail order system The advantages to the system are direct ordering and shipment from the Agilent Technologies Part Center in Mountain View California There is no maximum or minimum on any mail order There is a minimum amount for parts ordered through a local Agilent Technologies Sales Office when the orders require billing and invoicing Transportation costs are prepaid there is a small handling charge for each order and no invoices In order for Agilent Technologies to provide these advantages a check or money order must accompany each order Mail order forms and specific ordering information are available through your local Agilent Technologies Sales Office Addresses and telephone numbers are located in a separate document at the back of the service guide Exchange Assemblies Some assemblies are part of an exchange program with Agilent Technologies The exchange program allows you to exchange a faulty assembly with one that has been repaired and performance verified by Agilent Technologies After you receive the exchange assembly return the defective assembly to Agilent Technologies A United States customer has 30 days to return the defective assembly If you do not return the defective assembly within the 30 days Agilent Technologies will charge you an additiona
24. acquisition 3 34 To test the single clock multiple edge state acquisition 3 45 To test the time interval accuracy 3 54 Performance Test Record 3 59 Testing Performance Testing Performance This chapter tells you how to test the performance of the logic analyzer against the specifications listed in chapter 1 To ensure the logic analyzer is operating as specified you perform software tests self tests and manual performance tests on the analyzer The logic analyzer is considered performance verified if all of the software tests and manual performance tests have passed The procedures in this chapter indicate what constitutes a Pass status for each of the tests The Logic Analyzer Interface To select a field on the logic analyzer screen use the arrow keys to highlight the field then press the Select key For more information about the logic analyzer interface refer to the Agilent Technologies 1660 Series Logic Analyzer User s Reference Test Strategy For a complete test start at the beginning with the software tests and continue through to the end of the chapter For an individual test follow the procedure in the test The examples in this chapter were performed using an 1664A The performance verification procedures starting on page 3 8 are each shown from power up To exactly duplicate the set ups in the tests save the power up configuration to a file on a disk then load that file at the start of each test If a
25. depress the retaining ears on both sides of the assembly next to the front panel and push the assembly out the front Install the new switch actuator assembly Make sure that the line filter switch is in the off position a Route the cable through the front panel then snap the pushbutton into the front panel b Snap the nipple into the switch plunger c Position the free end of the outer casing into the switch mounting chassis The edge of the outer casing should be all the way against the inner edge of the switch mounting chassis d Close the clamp by pushing it into the switch assembly until the clamp is seated Verify the push on push off action of the assembly oO gt Seana Replacing Assemblies To remove and replace the rear panel assembly To remove and replace the rear panel assembly Using previous procedures remove the following assemblies e Handle e Rear Feet e Cover Remove the switch actuator cable from the line filter according to To remove and replace the switch actuator assembly Disconnect the BNC In Out and fan cables on the Main Circuit board Disconnect the RS 232C an GPIB cables from the Main Circuit board Remove the two standoffs connecting the parallel printer connector socket to the rear panel Remove the two screws connecting the keyboard connector socket to the rear panel Remove the six rear panel screws Lift the rear panel away from the chassis Reverse this procedure to in
26. e Maximum state acquisition speed e Setup Hold time for single clock multiple edge state acquisition This test checks data channels using a multiple edge single clock at three selected setup hold times Equipment Required Equipment Critical Specifications Recommended Model Part Pulse Generator 100 MHz 3 5 ns pulse width lt 600 ps rise time Agilent 8131A option 020 Digitizing Oscilloscope gt 6 GHz bandwidth lt 58 ps rise time Agilent 54121T Adapter SMA m BNC f Agilent 1250 1200 SMA Coax Cable Oty 3 18 GHz bandwidth Agilent 8120 4948 BNC Cable BNC m m 48 in gt 2 GHz bandwidth Agilent 8120 1840 Coupler BNC m m Agilent 1250 0216 BNC Test Connector 6x2 Qty 4 Set up the equipment Turn on the equipment required and the logic analyzer Let them warm up for 30 minutes before beginning the test if you have not already done so Set up the pulse generator according to the following table Pulse Generator Setup Channel 1 Channel 2 Period Doub 0 ps Delay 0 ps 40 ns Width 4 0 ns Deyc 50 High 0 9 V High 0 9 V Low 1 7 V Low 1 7 V COMP Disabled COMP Disabled LED off LED off 3 45 Testing Performance To test the single clock multiple edge state acquisition Set up the oscilloscope Oscilloscope Setup Time Base Display Delta V Delta T Time Div 1 00 ns div avg V markers on T markers on of avg 16 marker 1 position Chan 1 start on Neg Edge
27. field next to Sys PV then select System Test in the pop up menu then press the Select key Coama Disk Printer Controller Utilities Exit Test 34 Channel Communications 50 MHz STATI O 7 500 MHz TIMI HPIB Printer Setup a RS 232C Install a formatted disk that is not write protected into the disk drive If the 1664A has the RS 232C option 020 connect an RS 232C loopback connector onto the RS 232C port Select All System Tests You can run all tests at one time except for the Front Panel Test and Display Test by running All System Tests To see more details about each test when troubleshooting failures you can run each test individually This example shows how to run all tests at once When the tests finish the status for each test shows Passed or Failed and the status for the All System Tests changes from Untested to Tested Note that the Front Panel Test and Display Test remain Untested and the RS 232C Test will display FAILED if option 020 is not installed Sys P System Test ROM Test Disk Test status PASSED status PASSED RAM Test status PASSED HP IB Test Front Panel Test status PASSED status UNTESTED RS 232C Test Display Test status FAILED status UNTESTED HIL Test All System Tests status PASSED status TESTED Select the Front Panel Test A screen duplicating the front panel appears o
28. k Acq Control Accumulate Current Sample Period 8 000 ns off Next Sample Period 8 000 ns pma sec Div Delay Markers Acquisition Time 100 ns 0 s off 23 Aug 1993 14 00 27 TEITTE Test the next channels e Return to Connect the logic analyzer on page 3 18 and connect and test the next combination of data and clock channels until all pods are tested To access pod 2 in the Format menu select pod 1 field then select pod 2 in the pop up menu 3 22 To test the single clock single edge state acquisition Testing the single clock single edge state acquisition verifies the performance of the following specifications e Minimum master to master clock time e Maximum state acquisition speed e Setup Hold time for single clock single edge state acquisition e Minimum clock pulse width This test checks the data channels using a single edge clock at three selected setup hold times Equipment Required Equipment Critical Specifications Recommended Model Part Pulse Generator 100 MHz 3 5 ns pulse width lt 600 ps rise time Agilent 8131A option 020 Digitizing Oscilloscope gt 6 GHz bandwidth lt 58 ps rise time Agilent 54121T Adapter SMA m BNC f Agilent 1250 1200 SMA Coax Cable Oty 3 18 GHz bandwidth Agilent 8120 4948 BNC Cable BNC m m 48 in gt 2 GHz bandwidth Agilent 8120 1840 Coupler BNC m m Agilent 1250 0216 BNC Test Connector 6x2 Oty 4 Se
29. key on the front panel The corresponding key on the screen will change from a light to a dark color b Test the knob by turning it in both directions c Note any failures then press the Done key a second time to exit the Front Panel Test The test screen shows the Front Panel Test status changed to Tested Select the Display Test A white grid pattern is displayed These display screens can be used to adjust the display a Select Continue and the screen changes to full bright b Select Continue and the screen changes to half bright c Select Continue and the test screen shows the Display Test status changed to Tested 17 Troubleshooting To run the self tests To exit the tests press the System key then select Exit Test in the pop up menu and press the select key Reinstall the disk containing the operating system then select Exit Test System and press the select key If you are performing the self tests as part of the troubleshooting flowchart return to the flowchart WARNING Troubleshooting To test the power supply voltages To test the power supply voltages To check the voltages the power supply must be loaded by either the acquisition board or with an added resistor Refer to chapter 6 Replacing Assemblies for instructions to remove or replace covers and assemblies Hazard voltages exist on the power supply the CRT and the CRT driver board This procedure is to be performed b
30. panel enter 1 160 V 1 mV DC offset Use the multimeter to verify the voltage The activity indicators for pod 1 should show all data channels and the J clock channel at a logic high 3 Using the Modify down arrow on the function generator decrease offset voltage in 1 mV increments until all activity indicators for pod 1 show the channels are at a logic low Record the function generator voltage in the performance test record Analyzer Format MACHINE 1 Timing Acquisition Mode Conventional Full Channel 250 MHz Clock Inputs Pod A2 E Labels Labi 4 Using the Modify up arrow on the function generator increase offset voltage in 1 mV increments until all activity indicators for pod 1 show the channels are at a logic high Record the function generator voltage in the performance test record Pnalyzer Format MACHINE 1 Timing Acquisition Mode Conventional Full Channel 250 MHz Symbals Clock Inputs Pod A2 lt Labels 3 12 Testing Performance To test the threshold accuracy Test the User threshold 1 Move the cursor to the field to the right of Pod 1 Type 6 00 then use the left and right cursor control keys to highlight V Press the Select key 2 On the function generator front panel enter 5 718 V 1 mV DC offset Use the multimeter to verify the voltage The activity indicators
31. performance verification procedures in chapter 3 of this service guide make up the parametric performance verification for the logic analyzer Refer to chapter 3 Testing Performance for further information about parametric performance verification Power up Self Tests The power up self tests are divided into two parts The first part is the system memory tests and the second part is the microprocessor interrupt test The system memory tests are performed before the logic analyzer actually displays the power up self test screen Both the system ROM and RAM are tested during power up The interrupt test is performed after the power up self test screen is displayed The following describes the power up self tests ROM Test The ROM test performs several checksum tests on various read only memory elements including the system ROM as well as the various software modules present in flash ROM Passing the ROM test implies that the microprocessor can access each ROM memory address and that each ROM segment provides checksums that match previously calculated values Theory of Operation System Tests System PV RAM Test The RAM test checks the video RAM VRAM system dynamic RAM DRAM and static RAM memory within the real time clock IC The microprocessor first performs a write read in each memory location of the VRAM At each VRAM memory location a test pattern is written read and compared An inverse test pattern is then writ
32. power by turning off then turning on the power switch If the instrument is not warmed up the power up test screen will complete before you can view the screen 3 As the tests complete check if they pass or fail Performing Power Up Self Tests passed ROM text passed RAM test passed Interrupt test passed Display test passed HIL Controller test passed HIL Devices test No Disk Front Disk test Troubleshooting To run the self tests To run the self tests Self tests identify the correct operation of major functional areas of the instrument You can run all self tests without accessing the interior of the instrument If a self test fails the troubleshooting flowcharts instruct you to change a part of the instrument 1 If you just did the power up self tests go to step 2 If you did not just do the power up self tests disconnect all inputs insert the operating system disk then turn on the power switch Wait until the power up tests are complete 2 Press the System key then select the field next to System Select Test in the pop up menu and then press the Select key Disk Load from file PYTEST_ Printer Controller Change Dir Utilities H_system Execute DOS Filename Date le Description PVTEST_ 8Sep94 St 217600 HP1664 System Test Prog VOI PY_032 8Sep94 Sit 51966 HP1664 Analyzer Test Prog VO SYSTEM 8Sep94 Sit 238336 HP1664 System Software VOI S S
33. select Precision Edge Find in the oscilloscope Delta Tmenu Repeat this step until the pulses are aligned according to the setup time of the setup hold combination selected 0 0 ps or 100 ps Select the clock to be tested a Inthe Master Clock menu select the clock field to be tested then select the clock edge as indicated in the table The first time through this test use the top clock and edge in the following table Clocks JT KT b Connect the clock to be tested to the pulse generator channel 2 output c Select Done to exit the Master Clock menu Analyzer Format MACHINE 1 Run State Acquisition Mode Full Channel 2k Memory SomHz JI Symbols Master Clock 3 30 5 ez Testing Performance To test the single clock single edge state acquisition Note This step is only done the first time through the test to create a Compare file For subsequent runs go to step 6 Use the following to create a Compare file a Press Run The display should show a checkerboard pattern of alternating As and 5s Verify the pattern by scrolling through the display b Press the List key In the pop up menu use the RPG knob to move the cursor to Compare Press Select c Inthe Compare menu move the cursor to Copy Listing to Reference then select Execute in the pop up menu and press the Select Key d Move the cursor to Specify Stop Measurement and press the Select key Press Select again t
34. up menu In the Analyzer 1 box select the Type field Select Timing in the pop up menu Analyzer Configuration Cance Analyzer 1 Analyzer 2 Name MACHINE 1 Type Type Cost _ Unassigned Pods Alt J A2 K Connect the logic analyzer Using SMA cables connect the oscilloscope to the pulse generator channel 1 Output channel 2 Output and Trig Output Using the 6 by 2 test connectors connect the first combination of logic analyzer clock and data channels listed in the table to the pulse generator You will repeat this test for the remaining combinations Testing Performance To test the glitch capture Connect the Logic Analyzer to the Pulse Generator Testing To Agilent 8131A To 8131A Channel To 8131A Channel To 8131A Channel Combinations Channel 1 Output 1 Output 2 Output 2 Output 1 Pod 1 Pod 1 Pod 1 Pod 1 ch 0 2 4 6 ch 1 3 5 7 ch 8 10 12 14 ch 9 11 13 15 J clock 2 Pod 2 Pod 2 Pod 2 Pod 2 ch 0 2 4 6 ch 1 3 5 7 ch 8 10 12 14 ch 9 11 13 15 K clock o0o0D0D000 T 259 sair Sl B887 pede BEE System 5858 Q essressess EF lea agaouuoog gj O Ps 8131A Option 20 ongi bugs Pods 1 amp 2 DATA 16 Co CLK 1 01664E07 Testing Performance To test th
35. 1 screen dual marker 2 position Chan 1 stop on Neg Edge 2 Channel Channel 1 Channel 2 Display on on Probe Atten 20 00 20 00 Offset 13V 13V Volts Div 400 mV 400 mV Set up the logic analyzer Set up the Configuration menu a Press the Config key b Assign all pods to Machine 1 To assign all pods select the pod fields then select Machine 1 c Select the Type field in the Analyzer 1 box then select State Analyzer Configuration Analyzer 1 Analyzer 2 Name MACHINE 1 Type Type Coot Unassigned Pods Al i A2 K 3 46 2 Set up the Format menu a Press the Format key Select State Acquisition Mode then select Full Channel 4K Memory 50MHz b Select the field to the right of each pod field then select ECL Analyzer Format MACHINE 1 State Acquisition Mode ew Cea er som Full Channel 4k Memory SOMH2 Master Clock Jt Testing Performance To test the single clock multiple edge state acquisition Symbols Clock Inputs Pod A2 TTL Pod at TTL i Labels Master Clock Master Clock Labi Lab2 Lab3 Lab4 Labs Lab6 Lab Lab 3 Set up the Trigger menu a Press the Trigger key Select Clear Trigger then select All b Select the Count Off field then select Time in the pop up menu Select Done to exit the menu c Select the field labele
36. 13 Ground 14 Ground 15 Ground 16 Video 17 Ground 18 NC 19 Ground 20 NC 5 23 WARNING 3 4 5 6 7 8 Troubleshooting To test the keyboard signals To test the keyboard signals Refer to chapter 6 Replacing Assemblies for instructions to remove covers and assemblies Hazard voltages exist on the power supply the CRT and the CRT driver board This procedure is to be performed by service trained personnel aware of the hazards involved such as fire and electrical shock Turn off the instrument and remove the power cable Without disconnecting the keyboard cable follow the keyboard removal procedure to loosen the keyboard Leave the keyboard in place in front of the instrument Reconnect the power cable install the operating system disk then turn on the instrument Run the Front Panel Test pressing all of the keys If arandom key is not operating then go to the next step If a group of keys do not work then check the keyboard voltages and signals Keyboard Connector Signals Pin Signal Pin Signal 1 Keyboard Return 13 Keyboard Scan 2 14 i 3 15 4 16 5 17 6 18 7 19 LED 8 20 5V 9 Keyboard Scan 21 Ground 10 g 22 Knob 11 23 Ground 12 24 Knob Allow the keyboard assembly to fall forward from the front panel Separate the elastomeric keypad and keyboard panel from the PC board Using a paper clip or screwdriver short the PC board trace of the non operating key a
37. 4 BNC Cable Agilent 10503A BNC Banana Adapter 1251 2277 Press the Config key Assign pods 1 and 2 to Machine 1 To assign the pod field select the pods 1 and 2 field then select Machine 1 in the pop up menu In the Analyzer 1 box select the Type field Select Timing in the pop up menu Set up the trigger menu a Press the Trig key Select Clear Trigger All b Select Arming Control In the Arming Control pop up menu select the field labeled Run then select Port In Press the Done key Attach a BNC shorting cap to the External Trigger Input on the rear panel of the logic analyzer Using a BNC cable connect the External Trigger output to the oscilloscope channel 1 input Set the oscilloscope to Trigger On and measure TTL voltage levels Press the RUN front panel key The warning MACHINE 1 Waiting on level 1 will appear Remove the shorting cap from the rear panel External Trigger input BNC The warning will go away and the oscilloscope will display a positive going TTL pulse 5 27 Troubleshooting To test the logic analyzer probe cables To test the logic analyzer probe cables This test allows you to functionally verify the probe cable and probe tip assembly of any of the logic analyzer pods Only one probe cable can be tested at a time Repeat this test for each probe cable to be tested Equipment Required Equipment Critical Specification Recommended Model Part Pulse Generator 100 MHz 3 5 ns pul
38. 660 44703 1 Keyboard spacer MP27 01660 44702 1 Front panel spacer MP28 01660 94306 Keyboard template enter accessory MP29 01660 94305 Keyboard template F1 F8 accessory MP30 01664 04101 1 Rear panel cover plate RS 232 GPIB MP31 16555 60001 1 Ferrite Core Assembly MP32 01664 44701 1 Rubber Spacer Ferrite MP33 01660 94304 1 Label Pods and Cable w1 01650 61616 1 Fan cable W2 01660 61603 1 Disk drive cable W3 01660 61607 1 Jumper cable assembly orange W4 01660 61608 1 Jumper cable assembly white W5 54503 61606 1 Power supply cable W6 01664 61601 1 Front Panel Cable Extender 7 6 Replaceable Parts Replaceable Parts List 1664A Replaceable Parts Ref Agilent Des Part Oty Description Number W7 01650 61601 1 Monitor sweep cable Option 020 E5 01650 63202 1 RS 232 loopback connector H26 0380 1482 2 Hex standoff GPIB Cable H27 2190 0009 2 WIL 168 340 02 GPIB Cable H28 0380 1858 2 Jackscrew with lock RS 232 Cable MP34 1258 0141 1 Removable jumper W8 01650 61613 1 GPIB Cable W9 01660 61601 1 RS 232C Cable Power Cords W10 8120 1521 1 Power Cord United Kingdow 900 8120 0696 1 Power Cord Australia 901 8120 1692 1 Power Cord Europe 902 8120 2296 1 Power Cord Switzerland 906 8120 2957 1 Power Cord Denmark 912 8120 4600 1 Power Cord Africa 917 8120 4754 1 Power Cord Japan 918 Replaceable Parts Power Cables and Plug Configurations Power Cables and Plug Co
39. ARD KEYBOARD CABLE CONTINUITY OK REPLACE MAIN CIRCUIT __ ASSEMBLY REPLACE KEYBOARD aaa ASSEMBLY 01664B06 Troubleshooting Flowchart 5 Troubleshooting To use the flowcharts CHART 1 PERFORM DISK DRIVE SELF FEST PASS SELF SITES A REMOVE DISK DRIVE CABLE FROM DISK DRIVE Y CHECK FOR VOLTAGES AND SIGNALS SIGNALS AND VOLTAGES OK 01664B07 ASSEMBLY CHART 6 YES DISK DRIVE YES REPLACE MAIN CIRCUIT CABLE CONTINUITY 4 ASSEMBLY OK REPLACE DISK DRIVE ee M CABLE REPLACE DISK DRIVE END Troubleshooting Flowchart 6 5 8 CHART 1 PERFORM DATA ACQUISITION SELF TEST YES POSSIBLE CABLE PROBLEM PERFORM CABLE TEST DO ANY PODS FAIL TO ACQUIRE DATA YES Y NO REPLACE MAIN CIRCUIT ASSEMBLY NO TROUBLE FOUND EXCHANGE SUSPECT PROBE TIP ASSEMBLIES WITH KNOWN GOOD ASSEMBLIES Y REDO CABLE TEST FAILURE FOLLOW THE SUSPECT PROBE TIP ASSEMBLY EXCHANGE SUSPECT POD CABLE WITH KNOWN GOOD CABLE Y REDO CABLE TEST DO ANY PODS FAIL TO ACQUIRE DATA REPLACE MAIN CIRCUIT REPLACE PROBE TIP ASSEMBLY REPLACE SUSPECT CABLE ASSEMBLY Troubleshooting Flowchart 7
40. Activate the data channels that are connected according to the previous tables a Press the Format key b Select the field showing the channel assignments for one of the pods being tested Press the Clear entry key Using the arrow keys move the selector to the data channels to be tested then press the Select key An asterisk means that a channel is turned on When all the correct channels of the pod are turned on press the Done key Follow this step for the remaining pods Analyzer Format MACHINE 1 State Acquisition Mode Master Clock Full Channel 2k Memory SOMHzZ Jt Symbols Clock Inputs L Labels Pod A2 ECL Pod A1 ECL Master Clock Master Clock Labi Lab2 Lab3 Lab4 Lab 3 48 c Testing Performance To test the single clock multiple edge state acquisition Press the Trigger key Make sure pattern term a is A If not select the field next to a under the label Lab1 Type A then press the Select key Verify the test signal Check the clock period Using the oscilloscope verify that the clock period is 20 ns 0 ps or 250 ps a b In the oscilloscope Timebase menu select Sweep Speed 4 00 ns div Select Delay Using the oscilloscope knob position the clock waveform Channel 2 so that a rising edge appears at the left of the display In the oscilloscope Measure menu select Measure Chan 2 then se
41. Display RAM Keyboard Interface Disk Drive Controller Disk Drive Assembly Keypad amp Knob Interface Keypad and RPG Knob Assembly HP IB Interface Optional HP IB Connector RS 232 C Interface Optional RS 232 C Connector Centronix Interface Parallel Printer Port 01664B16 Theory of Operation The 1664A Logic Analyzer 1664A Theory CPU Located on the main circuit board the microprocessor is a Motorola 68EC020 running at 25 MHz The microprocessor controls all of the functions of the logic analyzer including processing and storing data displaying data and configuring the acquisition ICs to obtain and store data System Memory The system memory is made up of both read only memory ROM and random access memory RAM A single 128Kx8 EPROM is used as a boot ROM boot up requires operating system on disk loaded in the disk drive Four 1Mx4 DRAMS are configured to provide a 1Mx16 DRAM space On power up instructions in the boot ROM command the instrument to execute its boot routine which loads the operating system from disk The boot routine on disk includes power up operation verification of the instrument subsystems and entering the operating system The CPU searches for the operating system on disk The DRAM stores the instru
42. Enable the pulse generator channel 1 and channel 2 outputs with the LED off b In the oscilloscope Timebase menu select Delay Using the oscilloscope knob position the clock waveform so that the waveform is centered on the screen c Inthe oscilloscope Delta V menu set the Marker 1 Position to Chan 2 then set Marker 1 at 1 3000 V Set the Marker 2 Position to Chan 2 then set Marker 2 at 1 3000 V d Inthe oscilloscope Delta T menu select Start On Neg Edge 1 Select Stop On Pos Edge 1 e Ifthe pulse width is outside of the limits adjust the pulse generator channel 2 width and select the oscilloscope Precision Edge Find until the pulse width is within limits 3 42 Testing Performance To test the multiple clock multiple edge state acquisition 9 Using the Delay mode of the pulse generator channel 1 position the pulses according to the setup time of the setup hold combination selected 0 0 ps or 100 ps a Inthe oscilloscope Delta V menu set the Marker 1 Position to Chan 1 then set Marker 1 at 1 3000 V Set the Marker 2 Position to Chan 2 then set Marker 2 at 1 3000 V b In the oscilloscope Delta T menu select Start On Pos Edge 1 Select Stop on Neg Edge 1 c Adjust the pulse generator channel 1 Delay then select Precision Edge Find in the oscilloscope Delta T menu Repeat this step until the pulses are aligned according to the setup time of the setup hold combination selected 0 0 ps or 100 ps aN e
43. L 377 507 02 BNC trigger ports H21 0515 1031 4 MSFH M3 6 T10 accessory pouch H22 0515 2306 2 Screw Sems M3 X0 5X10mm Cable Retaining Screw H23 2510 0332 4 SCR MACH 8 32 Fan H24 1252 2218 2 Cable Retaining Clip 20 pin connector Monitor sweep cable Replaceable Parts Replaceable Parts List 1664A Replaceable Parts Ref Agilent Des Part Oty Description Number H25 1252 2220 1 Cable Retaining Clip 34 pin connector Disk drive cable MP1 01660 61606 1 Intensity adjustment assembly MP2 01660 01203 1 Bracket disk drive MP3 3160 0092 1 Fan guard MP4 01664 00201 1 Rear panel MP5 54501 62702 1 Line filter cable assembly MP6 01660 01202 1 Handle plate MP7 01650 01202 1 Ground bracket MP8 01660 60001 1 Cabinet assembly MP9 01660 04102 1 Cover assembly MP10 54542 44901 1 Handle vinyl grip MP11 35672 21703 2 Strap retainer MP12 35672 45004 2 Handle end cap MP13 5041 8801 2 Foot MP14 1460 1345 2 Tilt Stand MP15 01660 40501 4 Rear foot MP16 5041 8822 2 Non skid foot MP17 01660 45401 1 Circuit board insulator MP18 01660 01201 1 Circuit board mounting plate MP19 01660 84501 1 Accessory pouch MP20 01660 40502 1 Trim strip MP21 01664 94301 1 ID label 1664A MP22 01660 94302 1 Line switch label MP23 01660 41901 1 Elastomeric keypad MP24 01660 47401 1 RPG knob MP25 01660 60002 1 Assembled keyboard panel and label 01660 45201 0 Keyboard panel replacement 01660 94303 0 Keyboard label replacement MP26 01
44. Mode Full Channel 2k Memory 50MHz JI Symbols Master Clock EDGES B k Grr Setup Hold 3 32 12 13 14 Testing Performance Press the blue shift key then press the Run key If 2 4 acquisitions are obtained without the Stop Condition Satisfied message appearing then the test passes Press Stop to halt the acquisition Record the Pass or Fail results in the performance test record Test the next clock a Press the Format key then select Master Clock b Turn off and disconnect the clock just tested c Repeat steps 11 12 and 13 for the next clock edge listed in the table in step 10 until all listed clock edges have been tested Test the next setup hold combination a Inthe logic analyzer Format menu press Master Clock b Turn off and disconnect the clock just tested c Repeat steps 1 through 14 for the next setup hold combination listed in step 1 on page 3 29 until all listed setup hold combinations have been tested When aligning the data and clock waveforms using the oscilloscope align the waveforms according to the setup time of the setup hold combination being tested 0 0 ps or 100 ps 3 33 To test the multiple clock multiple edge state acquisition Testing the multiple clock multiple edge state acquisition verifies the performance of the following specifications e Minimum master to master clock time e Maximum state acquisition speed e Setup Hold time for multiple
45. NIT SELECTIN GND 8 17 DECLARATION OF CONFORMITY according to ISO IEC Guide 22 and EN 45014 Manufacturer s Name Agilent Technologies Manufacturer s Address 1900 Garden of the Gods Road Colorado Springs CO 80901 U S A Declares That the product Product Name Logic Analyzer Model Number s 1664A Product Options All Conforms to the following Product Specifications Safety IEC 348 HD 401 UL 1244 CSA C22 2 No 231 Series M 89 CISPR 11 1990 EN 55011 1991 Group 1 Class A TEC 801 2 1991 EN 50082 1 1992 4 KV CD 8 kV AD IEC 801 3 1984 EN 50082 1 1992 3 V m TEC 801 4 1988 EN 50082 1 1992 1 kV Supplementary Information The product herewith complies with the requirements of the Low Voltage Directive 73 23 EEC and the EMC Directive 89 336 EEC Colorado Springs Sept 16 1994 John K Meher Manager European Contact Your local Agilent Technologies Sales and Service Office or Agilent Technologies GmbH Department ZQ Standards Europe Herrenberger Strasse 130 71034 Boblingen Germany FAX 49 7031 143143 Copyright Agilent Technologies 1987 2000 All Rights Reserved Reproduction adaptation or translation without prior written permission is prohibited except as allowed under the copyright laws Document Warranty The information contained in this document is subject to change without notice Agilent Technologies makes no warranty of any kind with reg
46. O unessione Al ri e A2 K Testing Performance To test the time interval accuracy 2 Set up the Format menu a Press the Format key Select Timing Acquisition Mode then select Transitional Full Channel 125 MHz b Select the field to the right of the Pod 1 field then select ECL c Select the field showing the channel assignments for Pod 1 Deactivate all channels by pressing the Clear entry key Using the arrow keys move the selector to Channel 0 Press the Select key to put an asterisk in the channel position activating the channel then press the Done key Pnalyzer Format MACHINE 1 a Timing Acquisition Mode Symbol Transitional Full Channel 125 MHz gaong Clock Inputs Pod A2 L Labels Labi Lab2 Lab3 Lab4 Labs Lab6 Lab Lab 3 Press the Trigger key Select Modify Trigger then Clear Trigger and All from the pop up menus Analyzer Trigger MACHINE 1 Print Run Modify Sequence Level Timing Sequence Le Arming Control TRIGGER on a gt 6 ns Replace Sequence Level icquisition Control Delete Sequence Level Add Sequence Level Modify Trigger Clear Trigger Break Down Macros Edgel Cancel Edge2 3 56 Testing Performance To test the time interval accuracy 4 Set up the Waveform menu a Press the Waveform key b Move the cursor to the sec Div field
47. Panel e Cover e Disk Drive e Power Supply Disconnect the GPIB and RS 232C cables from the Main Circuit board Disconnect the front panel cable from the Main Circuit board Disconnect the monitor board cable from the Main Circuit board Slide the board out the rear of the instrument Reverse this procedure to install the Main Circuit board Check that the following assemblies are properly installed before installing the Main Circuit board e Monitor e Front Panel e Switch Actuator 6 7 CAUTION Replacing Assemblies To remove and replace the switch actuator assembly To remove and replace the switch actuator assembly Using previous procedures remove the following assemblies e Handle e Rear Feet e Cover e Disk Drive e Power Supply e Main Circuit board Make sure the power switch is in the off position Disconnect the switch actuator from the line filter a Slide the clamp off of the outer casing far enough to release the switch actuator assembly If the wire in the switch actuator is bent the complete assembly must be replaced Refer to chapter 5 Replaceable Parts for the part number b Without bending the wire gently pry the nipple out of the switch plunger c Slide the cable out of the switch assembly Nipple Outer Casing Line Filter Switch Mounting Chassis Switch Plunger 0166029 Cable Clamp Remove the switch actuator assembly from the front of the cabinet To remove
48. Performance To test the single clock single edge state acquisition c Inthe oscilloscope Measure menu select Measure Chan 2 then select Period Ifthe period is more than or equal to 20 000 ns go to step 4 If the period is less than 20 000 ns but greater than 19 75 ns go to step 3 d Inthe oscilloscope Timebase menu add 10 ns to the delay e Inthe oscilloscope Measure menu select Period If the period is more than or equal to 20 000 ns decrease the pulse generator Chan 2 Doub in 100 ps increments until one of the two periods measured is less than 20 000 ns but greater than 19 75 ns Check the data pulse width Using the oscilloscope verify that the data pulse width is 3 50 ns 0 ps or 100 ps a Enable the pulse generator channel 1 and channel 2 outputs Leave channel 2 output disabled b In the oscilloscope Timebase menu select Sweep Speed 1 00 ns div c Select Delay Using the oscilloscope knob position the data waveform so that the waveform is centered on the screen d Inthe oscilloscope Delta V menu set the Marker 1 Position to Chan 1 then set Marker 1 at 1 3000 V Set the Marker 2 Position to Chan 1 then set Marker 2 at 1 3000 V e Inthe oscilloscope Delta T menu select Start On Pos Edge 1 Select Stop on Neg Edge 1 f Select Precision Edge Find g Ifthe pulse width is outside the limits adjust the pulse generator channel 1 width and select the oscilloscope Precision Edge Find until the pulse widt
49. Position to Chan 2 then set Marker 2 at 1 3000 V In the oscilloscope Delta T menu select Start On Pos Edge 1 Select Stop On Neg Edge 1 If the pulse width is outside of the limits adjust the pulse generator channel 2 width and select the oscilloscope Precision Edge Find until the pulse width is within limits ni pi ee i ed Check the clock period Using the oscilloscope verify that the clock period is 20 ns 0 ps or 250 ps a b In the oscilloscope Timebase menu select Sweep Speed 4 00 ns div Select Delay Using the oscilloscope knob position the clock waveform so that a rising edge appears at the left of the display 3 38 c d e Testing Performance To test the multiple clock multiple edge state acquisition In the oscilloscope Measure menu select Measure Chan 2 then select Period If the period is more than or equal to 20 000 ns go to step 4 If the period is less than 20 000 ns but greater than 19 75 ns go to step 3 In the oscilloscope Timebase menu add 10 ns to the Delay In the oscilloscope Measure menu select Period If the period is more than or equal to 20 000 ns decrease the pulse generator Chan 2 DOUB in 100 ps increments until one of the two periods measured is less than 20 000 ns but greater than 19 75 ns Check the data pulse width Using the oscilloscope verify that the data pulse width is 4 450 ns 50 ps or 100 ps a b In the oscilloscope Timebase menu s
50. Sequence Levels menu d Select the field next to the pattern recognizer a under the label Lab1 Type 000A then press Select Analyzer Trigger MACHINE 1 Run While storing no state TRIGGER on State Sequence Levels a 1 time Store anystate Timer 1 Arming Control Acquisition Control Count Time Modify Trigger 3 36 Testing Performance To test the multiple clock multiple edge state acquisition Connect the logic analyzer 1 Using the 6 by 2 test connectors connect the logic analyzer clock and data channels listed in the following table to the pulse generator Install a BNC cable between the pulse generator channel 2 output and the 6x2 test connector with the logic analyzer clock leads 2 Using SMA cables connect channel 1 channel 2 and trigger of the oscilloscope to the pulse generator Connect the 1664A Logic Analyzer to the Pulse Generator Testing Combination Connect to Agilent 8131A Channel 1 Output Pod 1 channel 3 Pod 2 channel 3 Connect to Agilent 8131A Channel 1 Output Pod 1 channel 11 Pod 2 channel 11 Connect to Agilent 8131A Channel 2 Output J clock K clock 3 Activate the data channels that are connected according to the previous table a Press the Format
51. V GPIB Test The GPIB test performs a write read operation to each of the registers of the GPIB IC A test pattern is written to each register in the GPIBIC The pattern is then read and compared with a known value The GPIB test will return a valid Pass or Fail status even if option 020 is not installed Passing the GPIB test implies that the read write registers in the GPIB IC can store a logical 1 or a logical 0 and that the GPIB IC is functioning properly Incoming and outgoing GPIB information will not be corrupted by the GPIB IC RS 232C Test This test checks the basic interface functions of the RS 232C port Both internal and external portions of the port circuitry are tested In order for the RS 232C test to pass option 020 must be installed and the RS 232C loopback connector must be installed on the RS 232C connector HIL Test The HIL test exercises both the HIL circuitry internal to the logic analyzer and the HIL interface between the logic analyzer and external keyboard if an external keyboard is connected First a read write operation is performed to each of the registers of the HILIC A test pattern is written to each memory location read and compared with a known value Second if an external keyboard is connected to the HIL port the keyboard controller that resides in the keyboard is polled by the microprocessor A test pattern is sent to the keyboard controller and returned to the microprocessor by the keyboard
52. _032 8Sep94 151 530432 HP1664 Analyzer Software V01 PHD DOS Disk Space bytes Total 1474560 Free 418816 3 Select the box labeled Load Test System then press the select key Insert the disk containing the performance verification tests self tests into the disk drive normally the same as the boot disk 4 Select the box labeled Continue and press the Select key After the test files have been loaded and Analy menu is displayed You can run all the analyzer tests at one time by selecting All Analyzer Tests To see more details about each test you can run each test individually 5 Select the Chip 5 Tests menu and press the Select key Data Input Inspection Board Tests status PASSED Chip 5 Tests All Analyzer Tests status PASSED status TESTED Troubleshooting To run the self tests 6 Select Run then select Single The test runs one time then the screen shows the results When the test is finished select Done To run a test continuously select Repetitive Select Stop to halt a Run Repetitive Chip 5 Tests communication memory encoder resources sequencer clock generator i m failures This test checks the internal operation of the specified state timing acquisition chip and its interchip communication lines 7 Select Board Tests then select Run When the Board Tests are finished select Done Board test This test checks the clock generat
53. a channels listed in the following table to the pulse generator Install a BNC cable between the pulse generator channel 2 output and the 6x2 test connector with the logic analyzer clock leads 2 Using SMA cables connect the oscilloscope to the pulse generator channel 1 Output channel 2 Output and Trig Output Connect the 1664A Logic Analyzer to the Pulse Generator Testing Connect to Connect to Combination Agilent 8131A Agilent 8131A Channel 1 Output Channel 1 Output 1 Pod 1 channel 3 Pod 1 channel 11 Pod 2 channel 3 Pod 2 channel 11 L Connect to Agilent 8131A Channel 2 Output J clock 3 Activate the data channels that are connected according to the previous table a Press the Format key b Select the field showing the channel assignments for one of the pods being tested then press the Clear entry key Using the arrow keys move the selector to the data channels to be tested then press the Select key An asterisk means that a channel is turned on When all the correct channels of the pod are turned on press the Done key Follow this step for the remaining pods Analyzer Format MACHINE 1 State Acquisition Mode Master Clock Full Channel 2K Memory 50MHz Jt Symbols Clock Inputs Pod A2 ECL Pod A1 ECL Master Clock Master Cl
54. any assistance contact your nearest Agilent Technologies Sales Office Certification Agilent Technologies certifies that this product met its published specifications at the time of shipment from the factory Agilent Technologies further certifies that its calibration measurements are traceable to the United States National Institute of Standards and Technology to the extent allowed by the Institute s calibration facility and to the calibration facilities of other International Standards Organization members About this edition This is the first edition of the Agilent Technologies 1664A Logic Analyzer Service Guide Publication number 01664 97005 Printed in USA Edition dates are as follows Second edition January 2000 First edition August 1994 New editions are complete revisions of the manual Update packages which are issued between editions contain additional and replacement pages to be merged into the manual by you The dates on the title page change only when a new edition is published A software or firmware code may be printed before the date This code indicates the version level of the software or firmware of this product at the time the manual or update was issued Many product updates do not require manual changes and conversely manual corrections may be done without accompanying product changes Therefore do not expect a one to one correspondence between product updates and manual upda
55. ard to this material including but not limited to the implied warranties or merchantability and fitness for a particular purpose Agilent Technologies shall not be liable for errors contained herein or for incidental or consequential damages in connection with the furnishing performance or use of this material Complete product warranty information is given at the end of this manual Safety This apparatus has been designed and tested in accordance with IEC Publication 348 Safety Requirements for Measuring Apparatus and has been supplied in a safe condition This is a Safety Class I instrument provided with terminal for protective earthing Before applying power verify that the correct safety precautions are taken see the following warnings In addition note the external markings on the instrument that are described under Safety Symbols Warning Before turning on the instrument you must connect the protective earth terminal of the instrument to the protective conductor of the mains power cord The mains plug shall only be inserted in a socket outlet provided with a protective earth contact You must not negate the protective action by using an extension cord power cable without a protective conductor grounding Grounding one conductor of a two conductor outlet is not sufficient protection e Only fuses with the required rated current voltage and specified type normal blow time delay etc
56. asure the number of tagged states between one state and trigger or between two states Patterns The X and O markers can be used to locate the nth occurrence of a specified pattern from trigger or from the beginning of data The O marker can also find the nth occurrence of a pattern from the X marker Statistics X and O marker statistics are calculated for repetitive acquisitions Patterns must be specified for both markers and statistics are kept only when both patterns can be found in an acquisition Statistics are minimum X to O time maximum X to O time average X to O time and ratio of valid runs to total runs Auxiliary Power Power Through Cables 1 3 amp at 5 V maximum per cable Operating Environment Temperature Instrument 0 C to 55 C 32 F to 131 F Probe lead sets and cables 0 C to 65 C 32 F to 149 F Humidity Instrument probe lead sets and cables up to 95 relative humidity at 40 C 4122 F Altitude To 4600 m 15 000 ft Vibration Operating Random vibration 5 to 500 Hz 10 minutes per axis 0 3 g rms Non operating Random vibration 5 to 500 Hz 10 minutes per axis 2 41 g rms and swept sine resonant search 5 to 500 Hz 0 75 g 0 peak 5 minute resonant dwell at 4 resonances per axis 4 Dimensions 17 4 442mm SSS C OE O 000g g E 200g Be j a ooo o pessoas
57. ata channels and the J clock channel at a logic high Analyzer Format MACHINE 1 Timing Acquisition Mode Conventional Full Channel 250 MHz Clock Inputs Pod A2 lt Labels 3 Using the Modify down arrow on the function generator decrease offset voltage in 1 mV increments until all activity indicators for pod 1 show the channels at a logic low Record the function generator voltage in the performance test record analyzer Format MACHINE 1 Timing Acquisition Mode Conventional Full Channel 250 MHz Clock Inputs Pod A2 lt Labels Fa 3 10 Testing Performance To test the threshold accuracy 4 Using the Modify up arrow on the function generator increase offset voltage in 1 mV increments until all activity indicators for pod 1 show the channels at a logic high Record the function generator voltage in the performance test record Anatyzer Format MACHINE 1 Timing Acquisition Mode Symbol Conventional Full Channel 250 MHz canoe Clock Inputs p Labels Labi fe ASSIS dot dk ted kee ote Lab2 Lab3 Lab4 Labs Lab6 Lab Lab Testing Performance To test the threshold accuracy Test the ECL threshold 1 Select the field to the right of Pod 1 then select ECL in the pop up menu 2 On the function generator front
58. attern read and compared with known values Passing the memory test implies that the acquisition IC RAM is functioning and that each memory location bit can hold either a logical 1 or logical 0 Encoder Test The encoder in the FISO front end is tested and verified using a walking 1 and walking 0 pattern The walking 1 and 0 is used to stimulate all of the encoder output pins which connect directly to the FISO memory cells Additionally the post store counter in each of the acquisition ICs is tested Passing the encoder test implies that the FISO encoder is functioning and can properly route the acquired data to the acquisition memory FISO RAM Also passing this test implies that the post store counter on the acquisition ICs is functioning Theory of Operation Analyzer Tests Analy PV Resource Test The pattern range edge and glitch recognizers are tested and verified First the test register is verified for correct operation Next the pattern comparators are tested to ensure that each bit in the recognizer memory location as well as the logic driver receiver are operating The edge and glitch pattern detectors are then verified in a similar manner The range detectors are verified with their combinational logic to ensure that the in and out of range conditions are recognized Passing the resource test implies that all of the pattern range edge and glitch resources are operating and that an occurrence of the patt
59. board circuit board align with the pins on the front panel To remove and replace the intensity adjustment Using previous procedures remove the following assemblies e Handle e Rear Feet e Cover e Rear Panel Disconnect the intensity adjustment cable from the CRT driver board Using a nut driver remove the hex nut attaching the intensity adjustment to the chassis Slide the intensity adjustment assembly toward the front and up out of the instrument Reverse this procedure to install the intensity adjustment When installing the intensity adjustment check that the keying tab on the adjustment aligns with the keying hole in the chassis 6 10 WARNING ao Ao fF WO DW R Replacing Assemblies To remove and replace the monitor To remove and replace the monitor Using previous procedures remove the following assemblies e Handle e Rear Feet e Cover e Disk Drive e Power Supply e Main Circuit board e Rear Panel Hazardous voltages exist on the CRT and the CRT driver board To avoid electrical shock disconnect the power from the instrument before performing the following procedures After disconnecting the power wait at least three minutes for the capacitors to discharge before servicing the instrument Disconnect the cable from the rear of the CRT Disconnect the yoke cable and intensity cable from the CRT driver board Disconnect the high voltage lead from the bell of the CRT Slide the
60. chapter 1 Note the noncondensing humidity limitation Condensation within the instrument can cause poor operation or malfunction Provide protection against internal condensation The logic analyzer will operate at all specifications within the temperature and humidity range given in chapter 1 However reliability is enhanced when operating the logic analyzer within the following ranges e Temperature 20 C to 35 C 68 F to 95 F e Humidity 20 to 80 noncondensing Storage Store or ship the logic analyzer in environments within the following limits e Temperature 40 C to 75 C e Humidity Up to 90 at 65 C e Altitude Up to 15 300 meters 50 000 feet Protect the logic analyzer from temperature extremes which cause condensation on the instrument To inspect the logic analyzer Inspect the shipping container for damage If the shipping container or cushioning material is damaged keep them until you have checked the contents of the shipment and checked the instrument mechanically and electrically Check the supplied accessories Accessories supplied with the logic analyzer are listed in Accessories in chapter 1 Inspect the product for physical damage Check the logic analyzer and the supplied accessories for obvious physical or mechanical defects If you find any defects contact your nearest Agilent Technologies Sales Office Arrangements for repair or replacement are made at Agilent Technologies op
61. cified patterns is less than or greater than a specified value or within or not within a specified range Indicators Activity Indicators Provided in the Configuration and Format menus for identifying high low or changing states on the inputs Markers Two markers X and O are shown as vertical dashed lines on the display Trigger Displayed as a vertical dashed line in the Timing Waveform display and as line 0 in the State Listing display Data Entry Display Labels Channels may be grouped together and given a 6 character name Up to 126 labels in each analyzer may be assigned with up to 32 channels per label Display Modes State listing State Waveforms Chart Compare Listing Compare Difference Listing Timing Waveforms and Timing Listings State Listing and Timing Waveforms can be time correlated on the same displays Timing Waveform Pattern readout of timing waveforms at X or O marker Bases Binary Octal Decimal Hexadecimal ASCII display only Two s Complement and User defined symbols Symbols 1 000 maximum Symbols can be downloaded over RS 232 or GPIB 1 5 General Information Supplemental Characteristics Marker Functions Time Interval The X and O markers measure the time interval between a point on a timing waveform and the trigger two points on the same timing waveform two points on different waveforms or two states time tagging on Delta States state analyzer only The X and O markers me
62. clock multiple edge state acquisition e Minimum clock pulse width This test checks data using multiple clocks at three selected setup hold times Equipment Required Equipment Critical Specifications Recommended Model Part Pulse Generator 100 MHz 3 5 ns pulse width lt 600 ps rise time Agilent 8131A option 020 Digitizing Oscilloscope gt 6 GHz bandwidth lt 58 ps rise time Agilent 54121T Adapter SMA m BNC f Agilent 1250 1200 SMA Coax Cable Oty 3 18 GHz bandwidth Agilent 8120 4948 BNC Cable BNC m m 48 in gt 2 GHz bandwidth Agilent 8120 1840 Coupler BNC m m Agilent 1250 0216 BNC Test Connector 6x2 Qty 4 Set up the equipment Turn on the equipment required and the logic analyzer Let them warm up for 30 minutes before beginning the test if you have not already done so Set up the pulse generator a Set up the pulse generator according to the following table Pulse Generator Setup Channel 1 Channel 2 Period Delay 0 ps Doub 20 0 ns 40 ns Width 4 5 ns Width 3 5 ns High 0 9 V High 0 9 V Low 1 7 V Low 1 7 V b Disable the pulse generator channel 2 COMP with the LED off 3 34 Testing Performance To test the multiple clock multiple edge state acquisition 3 Set up the oscilloscope Oscilloscope Setup Time Base Display Delta V Delta T Time Div 1 00 ns div avg V markers on T markers on of avg 16 marker 1 position Chan 1 start on Pos Edge 1 s
63. controller The test pattern is then compared with a known value Passing the HIL test implies that the read write registers in the HIL IC can store a logical 1 or a logical 0 and that the HIL IC is functioning properly Also passing the HIL test implies that the HIL pathway to the external keyboard is functioning and that the keyboard controller can communicate with the microprocessor in the logic analyzer Incoming HIL information from the external keyboard will not be corrupted by the pathway between the keyboard controller and microprocessor Disk Test The disk test exercises the disk controller circuitry by performing a read write on a disk Hither an LIF formatted disk with 20 sectors available space or a DOS formatted disk with 5K available space is required and should be inserted in the disk drive When the disk test is executed the disk is checked sector by sector to find any bad sectors If no bad sectors are found a test file is created on the disk and test data is written to the file Then the file is read and the test data is compared with known values At the conclusion of the test the test file is erased Passing the disk test implies that the disk controller circuitry in the logic analyzer and the disk read write circuitry in the disk drive are functioning properly The disk drive can read and write to a LIF or DOS formatted disk and the data will not be corrupted by the disk drive circuitry 8 11 Theory of Op
64. creen dual marker 2 position Chan 1 stop on Neg Edge 1 Channel Channel 1 Channel 2 Display on on Probe Atten 20 00 20 00 Offset 13V 13V Volts Div 400 mV 400 mV Set up the logic analyzer 1 Set up the Configuration menu a Press the Config key b Assign all pods to Machine 1 To assign pods select the pod fields then select Machine 1 c Inthe Analyzer 1 box select the Type field then select State Analyzer Configuration Analyzer 1 Analyzer 2 Name MACHINE 1 Type Type Coot Unassigned Pods Alt J7 A2 K 3 35 Testing Performance To test the multiple clock multiple edge state acquisition Set up the Format menu a Press the Format key Select State Acquisition Mode then select Full Channel 4K Memory 50MHz b Select the field to the right of each Pod field then select ECL Analyzer Format MACHINE 1 State Acquisition Mode Master Clock Full Channel 4k Memory SOMHzZ Jt R un Symbols Clock Inputs L Labels Pod A2 TTL Master Clock S i Pod Al TTL Master Clock T 9 Labi Set up the Trigger menu a Press the Trigger key Select Clear Trigger then select All b Select the Count Off field then select Time in the pop up menu Select Done to exit the menu c Select the field labeled 1 under the State Sequence Levels Select the field labeled anystate then select no state Select Done to exit the State
65. ctable Pass Fail Glitch 3 5 ns Pod 1 Pod 2 Performance Test Record continued Test Settings Results Single Clock Pass Fail Pass Fail Single Edge Acquisition Setup Hold Time 3 5 0 0 ns Jt J4 KT KL Setup Hold Time 0 0 3 5 ns Jt JL KT KL Setup Hold Time 1 5 2 5 ns Jt Jd KT KL Multiple Clock Multiple Edge Acquisition Pass Fail Pass Fail Setup Hold Time 4 5 0 0 ns JT4KT JA K Setup Hold Time 0 0 4 5 ns JT4KT JA K Setup Hold Time 2 0 2 5 ns JT4KT JA K Single Clock Multiple Edge Acquisition Pass Fail Setup Hold Time 4 0 0 0 ns Jt Kt Setup Hold Time 0 0 4 0 ns Jt Kt S25 Setup Hold Time 2 0 2 0 ns Jt Kt Time Interval Measured Accuracy min X 0 94 99 95 00 us max X 0 95 00 95 01 us avg X 0 94 99 95 01 us 3 60 Logic analyzer calibration 4 2 To adjust the CRT monitor alignment 4 3 To adjust the CRT intensity 4 5 Calibrating and Adjusting Calibrating and Adjusting This chapter gives you instructions for calibrating and adjusting the logic analyzer Adjustments to the logic analyzer include adjusting the CRT monitor assembly To periodically verify the performance of the analyzer refer to Testing Performance in chapter 3 Logic analyzer calibration The logic analyzer circuitry of the 1664A Logic Analyzer does not require an operational accuracy calibration To test the logic analyzer circuitry against specification
66. d 1 under the State Sequence Levels Select the field labeled anystate then select no state Select Done to exit the State Sequence Levels menu d Select the field next to the pattern recognizer a under the label Lab1 Type 000A then press Select Analyzer Trigger MACHINE 1 TRIGGER on State Sequence Levels While storing no state a 1 time Store anystate Timer Arming pape Control Acquisition Control Count Time Modify Trigger 3 47 Testing Performance To test the single clock multiple edge state acquisition Connect the logic analyzer 1 Using the 6 by 2 test connectors connect the logic analyzer clock and data channels listed in the following table to the pulse generator Install a BNC cable between the pulse generator channel 2 output and the 6x2 test connector with the logic analyzer clock leads Using SMA cables connect channel 1 channel 2 and trigger of the oscilloscope to the pulse generator Connect the 1664A Logic Analyzer to the Pulse Generator Testing Combination Connect to Agilent 8131A Channel 1 Output Pod 1 channel 3 Pod 2 channel 3 Connect to Agilent 8131A Channel 1 Output Pod 1 channel 11 Pod 2 channel 11 Connect to Agilent 8131A Channel 2 Output J clock 3
67. e System System Test Single Disk Test NOTE This test requires a formati LIF or DOS that is not write p Cancel and has at least 20 blocks or 50 free space temporary file The test checks for a DOS or LIF disk format reads the entire media and performs a wWrite read test of known patterns to a 5 25 Troubleshooting To test the disk drive voltages 6 Check for the following voltages and signals using an oscilloscope Disk Drive Voltages Pin Signal Description Pin Signal Description 1 NC 2 Disk Change 3 NC 4 High Density 5 NC 6 NC 7 5V 8 Index 9 5V 10 Drive Select 11 5V 12 NC 13 Ground 14 NC 15 Ground 16 Motor On 17 Ground 18 Direction 19 Ground 20 Step 21 Ground 22 Write Data 23 Ground 24 Write Gate 25 Ground 26 Track 00 27 Ground 28 Write Protect 29 Ground 30 Read Data 31 Ground 32 Side Select 33 Ground 34 Ready BOTTOM OF DISK DRIVE PIN 34 01660E 32 7 Select Stop and turn off the logic analyzer Remove the power cable 8 Disconnect the disk drive cable and re install the disk drive in the logic analyzer 9 Reconnect the disk drive cable and install the cover on the logic analyzer Troubleshooting To perform the BNC test To perform the BNC test Equipment Required Equipment Critical Specification Recommended Model Part Digitizing Oscilloscope 100 MHz Bandwidth Agilent 54600A BNC Shorting Cap 1250 007
68. e glitch capture Test the glitch capture on the connected channels Set up the Format menu a Press the Format key b Select the field to the right of the pod then select ECL in the pop up menu Use the arrow keys to access pods not shown on the screen select the Pods field and push Select c Select Timing Acquisition Mode then select Glitch Half Channel 125 MHz Turn on the channels that correspond to the channels being tested The channels being tested are the channels connected to the pulse generator in Connect the logic analyzer a Select the pod field then select one of the two pods in the pop up Move the cursor to the channel assignment field of the pod and press the Clear entry key until all channels of the pod are assigned all asterisks Press the Done key b Turn on the clock data channels that correspond to the clocks being tested Turn off the data channels and clock data channels that are not being tested Analyzer Format MACHINE 1 Timing Acquisition Mode Glitch Half Channel 125 MHz Symbols Clock Inputs Pod Al L Labels Testing Performance To test the glitch capture 3 Set up the Trigger menu a Press the Trigger key b Select Modify Trigger then Clear Trigger then select All in the pop up menus Analyzer Trigger MACHINE 1 Print Modify Sequence Level Arming Control Timing Sequence Le C TRIGGER on a g
69. ear feet from the instrument to remove them Press the locking tab on the bottom feet then remove them Remove the tilt stand from the bottom front feet by lifting the stand up and out of the foot Reverse this procedure to install the feet and tilt stand To remove and replace the cover Disconnect the logic analyzer cables from the rear panel Using the previous procedures remove the handle and the four rear feet Remove the seven screws from the front molding then slide the molding forward to remove it Remove the cover To remove the cover set the instrument upright and facing toward you Slide the chassis toward the front out of the cover and set it on a static safe work area Reverse this procedure to install the cover Check that all assemblies are properly installed before installing the cover When installing the chassis in the cover check that the tabs located at the bottom rear of the cover align with the holes in the rear panel 6 5 ao kr WwW N Replacing Assemblies To remove and replace the disk drive To remove and replace the disk drive Using previous procedures remove the following assemblies e Handle e Rear Feet e Cover Disconnect the disk drive cable from the rear of the disk drive Remove the two screws that attach the disk drive bracket to the power supply Slide the disk drive toward the rear of the instrument then lift it up and out Remove the disk drive bracket To
70. ecifications 100 MHz 3 5 ns pulse width lt 600 ps rise time gt 6 GHz bandwidth lt 58 ps rise time Accuracy lt 5 107 x frequency DC offset voltage 6 3 V 0 1 mV resolution 0 005 accuracy BNC m f f BNC m m 48 inch gt 2GHz bandwidth 18 GHz bandwidth SMA m BNC f SMA f BNC m BNC m m gt 100 MHz Bandwidth T Troubleshooting Recommended Use Model Part Agilent 8131A Option 020 P T Agilent 54121T P Agilent 3325B Option 002 P Agilent 3458A Agilent 11001 60001 Agilent 1250 0781 Agilent 8120 1840 Agilent 8120 4948 Agilent 1250 1200 Agilent 1250 2015 Agilent 1250 0216 Agilent 54006A par a 4 S9 Agilent 54600A Agilent 1250 0074 Agilent 1251 2277 United Detector 351 8710 1300 nie i e Instructions for making these test connectors are in chapter 3 Testing Performance 1 8 To inspect the logic analyzer 2 2 Ferrites 2 3 To apply power 2 4 To operate the user interface 2 4 To set the line voltage 2 4 To degauss the display 2 5 To clean the logic analyzer 2 5 To test the logic analyzer 2 5 Preparing for Use Preparing For Use This chapter gives you instructions for preparing the logic analyzer for use Power Requirements The logic analyzer requires a power source of either 115 Vac or 230 Vac 22 to 10 single phase 48 to 66 Hz 200 Watts maximum power Operating Environment The operating environment is listed in
71. ect key At the pop up menu select Not Equal Press Done e Move the cursor to the Reference Listing field and select The field should toggle to Difference Listing Press the blue shift key then press the Run key If 2 4 acquisitions are obtained without the Stop Condition Satisfied message appearing then the test passes Press Stop to halt the acquisition Record the Pass or Fail results in the performance test record 3 52 Testing Performance To test the single clock multiple edge state acquisition 6 Test the next clock a Press the Format key then select Master Clock b Turn off and disconnect the clock just tested c Repeat steps 3 and 5 for the next clock listed in the table in step 3 until all listed clock edges have been tested 7 Test the next setup hold combination a Press the Format key then select Master Clock and turn off the clock just tested b Repeat steps 1 through 7 for the next setup hold combination listed in step 1 until all listed setup hold combinations have been tested When aligning the data and clock waveforms using the oscilloscope align the waveforms according to the setup time of the setup hold combination being tested 0 0 ps or 100 0 ps To test the time interval accuracy Testing the time interval accuracy does not check a specification but does check the following e 125 MHz oscillator This test verifies that the 125 MHz timing acquisition synchronizing oscilla
72. ect polarity of the fan cable To remove and replace the line filter Using previous procedures remove the following assemblies e Handle e Rear Feet e Cover e Disk Drive e Power Supply e Rear Panel Unsolder the ground wire from the lug on the rear panel Disconnect the line filter cable from the power supply Remove the two screws attaching the line filter to the rear panel Slide the line filter assembly out toward the rear Reverse this procedure to install the line filter 6 12 Replacing Assemblies To remove and replace the optional GPIB and RS 232C cables To remove and replace the optional GPIB and RS 232C cables Using previous procedures remove the following assemblies Handle Rear Feet Cover Disk Drive Power Supply Rear Panel Disconnect interface cables from the main circuit board Remove the two hex standoffs connecting the GPIB cable then slide the GPIB cable forward and out of the rear panel Remove the two hex standoffs connecting the RS 232C cable then slide the RS 232C cable forward and out of the rear panel Reverse this procedure to install the GPIB and RS 232C cables CAUTION Replacing Assemblies To return assemblies To return assemblies Before shipping the logic analyzer or assemblies to Agilent Technologies contact your nearest Agilent Technologies sales office for additional details Write the following information on a tag and attach it to the
73. ed into three functional groups according to function Eight signal lines called data lines are in the first functional group The data lines are used to transmit data in coded messages These messages are used to program the instrument function transfer measurement data and coordinate instrument operation Input and output of all messages in bit parallel byte serial form are also transferred on the data lines A 7 bit ASCII code normally represents each piece of data Data is transferred by means of an interlocking Handshake technique which permits data transfer asynchronously at the rate of the slowest active device used in that transfer The data byte control lines coordinate the handshaking and form the second functional group The remaining five general interface management lines third functional group are used to manage the devices connected to the GPIB This includes activating all connected devices at once clearing the interface and other operations The following figure shows the connections to the GPIB connector located on the rear panel a DIa 1 13 ores DIa 2 14 p10 DIO3 3 15 D107 oraa a 16 ree EOI 5 17 REN pav 6 18 P O TWISTED PAIR WITH 6 nRFD 7 19 P O TWISTED PAIR WITH 7 npac 8 2a P O TWISTED PAIR WITH 8 SHOULD BE GROUNDED IFC BCL 21 evo TwisteD parr with o NEAR TERMINATION CF ey PAIR SRQ 18
74. elect Sweep Speed 1 00 ns div Select Delay Using the oscilloscope knob position the data waveform so that the waveform is centered in the screen In the oscilloscope Delta V menu set the Marker 1 Position to Chan 1 then set Marker 1 at 1 3000 V Set the Marker 2 Position to Chan 1 then set Marker 2 at 1 3000 V In the oscilloscope Delta T menu select Start On Pos Edge 1 Select Stop on Neg Edge 1 If the pulse width is outside of the limits adjust the pulse generator channel 1 width and select the oscilloscope Precision Edge Find until the pulse width is within limits 3 39 Testing Performance To test the multiple clock multiple edge state acquisition Check the setup hold with single clock edges multiple clocks 1 Select the logic analyzer setup hold time a Inthe logic analyzer Format menu select Master Clock b Select and activate any two clock edges c Select the Setup Hold field and select the setup hold to be tested for all pods The first time through this test use the top combination in the following table Setup Hold Combinations 4 5 0 0 ns 0 0 4 5 ns 2 0 2 5 ns d Select Done to exit the setup hold combinations Analyzer Format MACHINE 1 Run State Acquisition Mode Full Channel 2K Memory SOMHz TORES 0 5 4 0 ns Symbols 4 0 0 5 ns 0 0 4 5 ns 3 5 1 0 ns ds A1 A2 3 0 1 5 ns leet 2 5 2 0 ns 2 0 2 5 ns 1 5 3 0 ns 1 0 3 5 ns
75. ence Level Modify Trigger Clear Trigger C a aan Ks Cancel 6 Set up the Listing menu a Press the List key b Select the field to the right of Base then select Binary Analyzer Trigger MACHINE 1 Run While stor te Control TRIGGER on Octal Acqui on Control Store Count eee Care Hex Modify Trigger Lepr 5 30 Troubleshooting To test the logic analyzer probe cables 7 Using four 6 by 2 test connectors four BNC Couplers and four SMA m BNC f Adapters connect the logic analyzer to the pulse generator channel outputs To make the test connectors see chapter 3 Testing Performance a Connect the even numbered channels of the lower byte of the pod under test to the pulse generator channel 1 Output and J clock b Connect the odd numbered channels of the lower byte of the pod under test to the pulse generator channel 1 Output c Connect the even numbered channels of the upper byte of the pod under test and the clock channel to the pulse generator channel 2 Output d Connect the odd numbered channels of the upper byte of the pod under test to the pulse generator channel 2 Output 8 On the logic analyzer press Run The display should look similar to the figure below Analyzer Listing MACHINE 1 Markers Acquisition Time off 23 Jul 1992 12 58 54 Label gt Labi Base gt Binary
76. ent 3 8 Set up the logic analyzer 3 9 Connect the logic analyzer 3 9 Test the TTL threshold 3 10 Test the ECL threshold 3 12 Test the User threshold 3 13 Test the User threshold 3 14 Test the 0 V User threshold 3 15 Test the next pod 3 16 To test the glitch capture 3 17 Set up the equipment 3 17 Set up the logic analyzer 3 18 Connect the logic analyzer 3 18 Test the glitch capture on the connected channels 3 20 Test the next channels 3 22 To test the single clock single edge state acquisition 3 23 Set up the equipment 3 23 Set up the logic analyzer 3 24 Connect the logic analyzer 3 26 Verify the test signal 3 27 Check the setup hold combination 3 29 Contents To test the multiple clock multiple edge state acquisition 1 34 Set up the equipment 1 34 Set up the logic analyzer 1 35 Connect the logic analyzer 1 37 Verify the test signal 1 38 Check the setup hold with single clock edges multiple clocks 1 40 To test the single clock multiple edge state acquisition 1 45 Set up the equipment 1 45 Set up the logic analyzer 1 46 Connect the logic analyzer 1 48 Verify the test signal 1 49 Check the setup hold combination 1 51 To test the time interval accuracy 1 54 Set up the equipment 1 54 Set up the logic analyzer 1 55 Connect the logic analyzer 1 57 Acquire the data 1 58 Performance Test Record 3 59 4 Calibrating and Adjusting Logic analyzer calibration 4 2 Set up the equipment 4 2 To ad
77. eration System Tests System PV Perform Test All Selecting Perform Test All will initiate all of the previous functional verification tests in the order they are listed The failure of any or all of the tests will be reported in the test menu field of each of the tests The Perform All Test will not initiate the Front Panel Test or the Display Test Front Panel Test A mock up of the logic analyzer front panel is displayed on the CRT when the Front Panel Test is initiated The operator then pushes each front panel button and turns the RPG rotary pulse generator knob to toggle the corresponding fields from light to dark on the front panel mock up Successively pushing any front panel key will cause the corresponding field to toggle back and forth between light and dark An exception is the Done key Pressing the Done key a second time will cause an exit of this test The Front Panel Test passes when all of the key fields in the front panel mock up on the CRT can be toggled by pressing the corresponding front panel key and the two RPG fields can be toggled by turning the knob The Front Panel Test is not called when Perform Test All is selected Display Test When initiated the display test will cause three test screens to be displayed sequentially The first test screens is a test pattern used to align the CRT The second two screens verify correct operation of the color palette by displaying first a full bright screen and then a half brigh
78. ern edge or glitch of interest is recognized Also passing this test implies that the range recognizers will detect and report in and out of range acquisition data to the sequencer or storage qualifier The drivers and receivers at the recognizer input and output pins of the acquisition IC are also checked to be sure they are functioning Sequencer Test The sequencer the state machine that controls acquisition storage is tested by first verifying that all of the sequencer registers are operating After the registers are checked the combinational logic of the storage qualification is verified Then both the occurrence counter and the sequencer level counter are checked Passing the sequencer test implies that all 12 available sequence levels are functioning and that all possible sequence level jumps can occur Also passing this test implies that user defined ANDing and ORing of storage qualified data patterns will occur and that the occurrence counter that appears at each sequence level is functioning Clock Generator Test The master clock generator on the acquisition ICs is tested by first checking the operation of the clock optimization circuit The state acquisition clock paths are then checked to ensure that each state clock and clock qualifier are operating by themselves and in all possible clock and qualifier combinations The timing acquisition optimization circuit is then operationally verified Finally the timing acquisition frequenc
79. for pod 1 should show all data channels and the J clock channel at a logic high 3 Using the Modify down arrow on the function generator decrease offset voltage in 1 mV increments until all activity indicators for pod 1 show the channels at a logic low Record the function generator voltage in the performance test record Analyzer Format MACHINE 1 Timing Acquisition Mode Conventional Full Channel 250 MHz L Labels Symbols Clock Inputs Labi Lab3 Lab4 Labs Lab6 4 Using the Modify up arrow on the function generator increase offset voltage in 1 mV increments until all activity indicators show the channels at a logic high Record the function generator voltage in the performance test record Analyzer Format MACHINE 1 Timing Acquisition Mode Conventional Full Channel 250 MHz Symbols Clock Inputs _ Labels Labi Lab3 Lab4 Labs Lab6 Testing Performance To test the threshold accuracy Test the User threshold 1 Move the cursor to the field to the right of Pod 1 Type 6 00 then use the left and right cursor control keys to highlight V Press the Select key 2 On the function generator front panel enter 6 282 V 1 mV DC offset Use the multimeter to verify the voltage The activity indicators for pod 1 should show all data channels and the J clock channel a
80. fuse is installed See also To set the line voltage on this page Connect the power cord to the instrument and to the power source This instrument is equipped with a three wire power cable When connected to an appropriate ac power outlet this cable grounds the instrument cabinet The type of power cable plug shipped with the instrument depends on the country of destination Refer to chapter 7 Replaceable Parts for option numbers of available power cables and plug configurations Turn on the instrument power switch located on the front panel To operate the user interface To select a field on the logic analyzer screen use the arrow keys to highlight the field then press the Select key For more information about the logic analyzer interface refer to the Agilent Technologies 1660 Series Logic Analyzer User s Reference To set the GPIB address or to configure for RS 232C refer to the Agilent Technologies 1660 Series Logic Analyzer User s Reference To set the line voltage When shipped from the factory the line voltage selector is set and an appropriate fuse is installed for operating the instrument in the country of destination To operate the instrument from a power source other than the one set perform the following steps LINE FILTER SWITCH ASSEMBLY Preparing for Use To degauss the display 1 Turn the power switch to the Off position then remove the power cord from the instrument 2 Remo
81. generator decrease offset voltage in 1 mV increments until all activity indicators for pod 1 show the channels at a logic low Record the function generator voltage in the performance test record Analyzer Format MACHINE 1 Timing Acquisition Mode Conventional Full Channel 250 MHz L Labels Symbols Clock Inputs Labi Lab3 Lab4 Labs Lab6 4 Using the Modify up arrow on the function generator increase offset voltage in 1 mV increments until all activity indicators for pod 1 show the channels at a logic high Record the function generator voltage in the performance test record Analyzer Format MACHINE 1 Timing Acquisition Mode Conventional Full Channel 250 MHz Symbols Clock Inputs L Labels Labi Lab3 Lab4 Labs Lab6 Testing Performance To test the threshold accuracy Test the next pod 1 Using the 17 by 2 test connector and probe tip assembly connect the data and clock channels of pod 2 to the output of the function generator 2 Start with Test the TTL threshold on page 3 10 substituting pod 2 for pod 1 To test the glitch capture Testing the glitch capture verifies the performance of the following specification e Minimum detectable glitch This test checks the minimum detectable glitch on sixteen data channels at a time Equipment
82. gh ON 3 V to 25 V Low OFF 3 V to 25 V Signal from Mainframe High ON 12 V Low OFF 12 V Signal from Mainframe Always High ON 12 V Centronix The logic analyzer interfaces with Centronix parallel printer communication lines through a standard 25 pin D connector The logic analyzer is compatible with Centronix protocol BUSY is used to indicate when data can be transfered from the logic analyzer to the printer DATASTROBE is used to synchronize data transmissions Pin outs of the Centronix connector are listed in the following table Centronix Signal Definitions Pin Number oon oaoa A UU Nel Oo 12 Function Synchronous signal that is used for data transfer Logic analyzer data LSB Logic analyzer data Logic analyzer data Logic analyzer data Logic analyzer data Logic analyzer data Logic analyzer data Logic analyzer data MSB Signal used to indicate that data has been received Signal used to indicate that the printer is busy Signal used to indicate that the printer is out of paper Signal that indicates that the printer is on line Signal used to select the autofeed function Signal that indicates command or data error Signal used to initialize the printer Signal used to select the direction of the bi directional bus Ground Centronix Standard STROBE DATAO DATA1 DATA2 DATA3 DATA4 DATAS DATA6 DATA7 ACKNLG BUSY PERROR SELECT AUTOFD FAULT I
83. h density connector Sixteen single ended data channels and one single ended clock data channel are passed to the circuit board per pod If the clock data channel is not used as a state clock in state acquisition mode it is available as a data channel The clock data channel is also available as a data channel in timing acquisition mode Two clock data channels are available as data channels and all clock data channels available can be assigned as clock channels The cables use nichrome wire woven in polyarmid yarn for reliability and durability The pods also include one ground path per channel in addition to a pod ground The channel grounds are configured such that their electrical distance is the same as the electrical distance of the channel The probe tip assemblies and termination modules connected at the end of the probe cables have a divide by 10 RC network that reduces the amplitude of the data signals as seen by the circuit board This adds flexibility to the types of signals the circuit board can read in addition to improving signal integrity The terminations on the circuit board are resistive terminations that reduce transmission line effects on the cable The terminations also improve signal integrity to the comparators by matching the impedance of the probe cable channels with the impedance of the signal paths of the circuit board All 17 channels of each pod are terminated in the same way The signals are still reduced by a factor
84. h is within limits Testing Performance To test the single clock single edge state acquisition Check the setup hold combination 1 Select the logic analyzer setup hold time a Inthe logic analyzer Format menu select Master Clock b Select the Setup Hold field then select the setup hold combination to be tested for all pods The first time through this test use the top combination in the following table Setup Hold Combinations 3 5 0 0 ns 0 0 3 5 ns 1 5 2 0 ns c Select Done to exit the setup hold combinations Anatyzer Format MACHINE 1 Run State Acquisition Mode Symbol Full Channel 2K Memory 50MHz J 3 5 0 0 ns ymbors 3 0 0 5 ns 2 5 1 0 ns ds A1 A2 2 0 1 5 ns laine 1 5 2 0 ns 1 0 2 5 ns 0 5 3 0 ns 0 0 3 5 ns 2 Disable the pulse generator channel 2 COMP with the LED off 3 Using the Delay mode of the pulse generator channel 1 position the pulses according to the setup time of the setup hold combination selected 0 0 ps or 100 ps a Inthe oscilloscope Delta V menu set the Marker 1 Position to Chan 1 then set Marker 1 at 1 3000 V Set the Marker 2 Position to Chan 2 then set Marker 2 at 1 3000 V b In the oscilloscope Delta T menu select Start on Pos Edge 1 Select Stop on Pos Edge 1 3 29 Testing Performance To test the single clock single edge state acquisition c Adjust the pulse generator channel 1 Delay then
85. ic analyzer has acquired at least 100 valid runs touch Stop The Min X O field in the logic analyzer Pattern Statistics menu should read 94 99 95 00 us The Max X O field should read 95 00 95 01 us The Avg X O field should read 94 99 95 01 us Record the results in the performance test record Analyzer Waveform MACHINE 1 Laca Control Gy Accumulate Valid runs Min X 0 Max X O Avg X 0 off 100 of 100 94 99 us 95 01 us 95 00 us i sec Div Delay Markers x to Oo Reset 2 00 us 0 sj Statistics 95 000 us Statistics 3 58 Performance Test Record Performance Test Record 1664A Logic Analyzer Serial No Work Order No Recommended Test Interval 2 Year 4000 hours Date Recommended next testing Temperature Test Settings Results Self Tests Pass Fail Threshold 100 mV 3 of Accuracy threshold setting Limits Measured Pod 1 TTL 145 mV TIL VL 1 355 V TTLVH 1 645 V ECL VL 1 439 V ECL 139 mV ECLVH 1 161 V User VL 6 280 V User 280 mV 7 User VH 5 720 V User VL 5 720 V User VH 6 280 V User 280 mV 0 V User VL 100 mV 0 V User VH 100 mV 0 V 100 mV Pod 2 TTL 145 mV TIL VL 1 355 V TTLVH 1 645 V ECL VL 1 439 V ECL 139 mV ECL VH 1 161 V User VL 6 280 V User 280 mV User VH 5 720 V i User VL 5 720 V User VH 6 280 V User 280 mV 0 V User VL 100 mV 0 V User VH 100 mV 0 V 100 mV Glitch Capture Minimum Dete
86. ield to the right of each pod then select ECL in the pop up menu Analyzer Format MACHINE 1 State Acquisition Mode Master Clock Full Channel 4k Memory SOMH2 Jt Pod A2 TTL Testing Performance To test the single clock single edge state acquisition Symbols Clock Inputs iL ei Labels Master Clock Pod At TTL Master Clock Labi taz Lab3 Lab4 Labs Lab6 Lab Lab 3 Set up the Trigger menu a Press the Trigger key Select Modify Trigger then Clear Trigger then select All in the pop up menus b Select Count Off Press Select again then select Time in the pop up menu Select Done to exit the menu c Select the field labeled 1 under the State Sequence Levels Select the field labeled anystate then select no state Select Done to exit the State Sequence Levels menu d Select the field next to a under the label Lab1 Type 000A then press the Select key Analyzer Trigger MACHINE 1 While storing no state TRIGGER on State Sequence Levels a 1 time Store anystate Arming ite Control Timer M2 Acquisition Control Count Time Modify Trigger 3 25 Testing Performance To test the single clock single edge state acquisition Connect the logic analyzer 1 Using the 6 by 2 test connectors connect the logic analyzer clock and dat
87. ignal being routed to the test input pin of all of the comparators Consequently the activity indicators are read to see if they show activity on all channels of all of the pods Chip Tests During the Chip Tests six tests are performed on the acquisition ICs The tests are the Communications Memory Encoder Resource Sequencer and Clock Generation Tests Communications Test The communications test verifies that communications pipeline between the various subsystems of the IC are operating Checkerboard patterns of 1s and 0s are routed to the address and data buses and to the read write registers of each chip After verifying the communications pipelines the acquisition clock synchronization signals that are routed from IC to IC are checked Finally the IC master clock optimization path is checked and verified Passing the communications test implies that the communications pipelines running from subsystem to subsystem on the acquisition IC are functioning and that the clock optimization circuit on the IC is functioning Also passing this test implies that the acquisition clock synchronization signals are functioning and appear at the synchronization signal output pins of the acquisition IC Memory Test Acquisition RAM is checked by filling the IC RAM with a checkerboard pattern of 1s and 0s then reading each memory location and comparing the test pattern with known values Then the IC RAM is filled with an inverse checkerboard p
88. ion circuits on the board and the data and clock comparators CE failures ie 8 Select Data Input Inspection All lines should show activity Select Done to exit the Data Input Inspection Analy PY Pod A2 tttttttttttttttt Kt Pod Al ttttttttttttttt It All lines should show activity Any lines Without activity are not functioning correctly and should not be used in a measurement 9 Select Analy PV then select Sys PV PV in the pop up menu and press the Select key Troubleshooting To run the self tests 10 Select the Printer Controller field next to Sys PV Select System Test and press the Select key to access the system tests You can run all tests at one time by running All System Tests To see more details about each test you can run each test individually This example shows how to run an individual test Co Pasar __ Disk Printer Controller Utilities Exit Test 34 Channel Communications 50 MHz STATI 500 MHz TIMI HPIB Printer Setup a RS 232C 11 Select ROM Test The ROM Test screen is displayed Sys PV System Test ROM Test failures o o This test checks the system mainframe ROM The test computes a checksum for the ROM and compares it to a known stored value Done 12 Select Run then select Single To run a test continuously select Repetitive Select Sto
89. ip d Solder the ground tab of the BNC connector to the center pin of the other row on the Berg strip Jumpers 2 17x2 Berg Strip BNC Panel Mount Connector 16550E05 3 7 To test the threshold accuracy Testing the threshold accuracy verifies the performance of the following specification e Clock and data channel threshold accuracy These instructions include detailed steps for testing the threshold settings of pod 1 After testing pod 1 connect and test pod 2 To test pod 2 follow the detailed steps for pod 1 substituting the pod 2 for pod 1 in the instructions Each threshold test tells you to record the voltage reading in the performance test record located at the end of this chapter To check if each test passed verify that the voltage reading you record is within the limits listed on the performance test record Equipment Required Equipment Critical Specifications Recommended Model Part Digital Multimeter 0 1 mV resolution 0 005 accuracy Agilent 3458A Function Generator DC offset voltage 6 3 V Agilent 3325B Option 002 BNC Banana Cable Agilent 11001 60001 BNC Tee Agilent 1250 0781 BNC Cable Agilent 8120 1840 BNC Test Connector 17x2 Set up the equipment Turn on the equipment required and the logic analyzer Let them warm up for 30 minutes before beginning the test Set up the function generator a Set up the function generator to provide a DC offset voltage at the Main Signal out
90. just the CRT monitor alignment 4 3 To adjust the CRT intensity 4 5 5 Troubleshooting To use the flowcharts 5 2 To check the power up tests 5 15 To run the self tests 5 16 To test the power supply voltages 5 21 To test the CRT monitor signals 5 23 To test the keyboard signals 5 24 To test the disk drive voltages 5 25 To perform the BNC test 5 27 To test the logic analyzer probe cables 5 28 To test the auxiliary power 5 32 6 Replacing Assemblies To remove and replace the handle 6 5 To remove and replace the feet and tilt stand 6 5 To remove and replace the cover 6 5 To remove and replace the disk drive 6 6 To remove and replace the power supply 6 7 vi Contents To remove and replace the Main Circuit board 6 7 To remove and replace the switch actuator assembly 6 8 To remove and replace the rear panel assembly 6 9 To remove and replace the front panel and keyboard 6 10 To remove and replace the intensity adjustment 6 10 To remove and replace the monitor 6 11 To remove and replace the handle plate 6 11 To remove and replace the fan 6 12 To remove and replace the line filter 6 12 To remove and replace the optional GPIB and RS 232C cables 6 13 To return assemblies 6 14 7 Replaceable Parts Replaceable Parts Ordering 7 2 Exploded View 7 3 Replaceable Parts List 7 4 Power Cables and Plug Configurations 7 8 8 Theory of Operation Block Level Theory 8 3 The 1664A Logic Analyzer 8 3 The Logic Acqui
91. key b Select the field showing the channel assignments for one of the pods being tested Press the Clear entry key Using the arrow keys move the selector to the data channels to be tested then press the Select key An asterisk means that a channel is turned on When all the correct channels of the pod are turned on press the Done key Follow this step for the remaining pods Analyzer Format MACHINE 1 State Acquisition Mode Master Clock Full Channel 2K Memory SOMHz JU Jt Symbols Clock Inputs Master Clock L Labels Pod A2 ECL Pod A1 ECL Master Clock Labi Lab2 Lab3 Lab4 Lab Lab 3 37 Testing Performance To test the multiple clock multiple edge state acquisition c Press the Trigger key Make sure pattern term a is A If not select the field next to a under the label Lab1 Type A then press the Select key Verify the test signal Check the clock pulse width Using the oscilloscope verify that the clock pulse width is 3 50 ns 0 ps or 100 ps a b Enable the pulse generator channel 1 and channel 2 outputs with the LED off In the oscilloscope Timebase menu select Delay Using the oscilloscope knob position the clock waveform so that the waveform is centered on the screen In the oscilloscope Delta V menu set the Marker 1 Position to Chan 2 then set Marker 1 at 1 3000 V Set the Marker 2
92. l amount This amount is the difference in price between a new assembly and that of the exchange assembly For orders not originating in the United States contact your nearest Agilent Technologies Sales Office for information To return assemblies in chapter 6 Replaceable Parts Exploded View Exploded View 01664E11 Exploded view of the 1664A logic analyzer 7 3 Replaceable Parts Replaceable Parts List Replaceable Parts List The replaceable parts list is organized by reference designation and shows exchange assemblies electrical assemblies then other parts The exploded view does not show all of the parts in the replaceable parts list Information included for each part on the list consists of the following e Reference designator e Agilent Technologies part number e Total quantity included with the instrument Qty e Description of the part Reference designators used in the parts list are as follows e A Assembly e E Miscellaneous Electrical Part e F Fuse H Hardware e MP Mechanical Part W Cable Replaceable Parts Replaceable Parts List 1664A Replaceable Parts Ref Agilent Des Part Oty Description Number Exchange Board 01664 69501 Exchange main circuit assembly Replacement Parts Al 01664 66501 1 Main circuit assembly A2 01660 66502 1 Board assembly keyboard A3 01660 61901 1 Switch actuator A4 01660 61605 1 Probe Cable A5 01650 61608 2 P
93. lect Width If the positive going pulse width is more than 20 000 ns go to step d If the pulse width is less than or equal to 20 000 ns go to step 2 In the oscilloscope Measure menu select Width If the negative going pulse width is less than or equal to 20 000 ns but greater than 19 75 ns go to step 2 Decrease the pulse generator Period in 100 ps increments until the oscilloscope Measure Width or Measure Width reads less than or equal to 20 000 ns but greater than 19 75 ns i g i i H i Lal A DANNIN Coe Ne Ae Porta rea neaeB hi a f l 3 49 Testing Performance To test the single clock multiple edge state acquisition Check the data pulse width Using the oscilloscope verify that the data pulse width is 4 000 ns 0 ps or 100 ps a Inthe oscilloscope Timebase menu select Sweep Speed 1 00 ns div b Select Delay Using the oscilloscope knob position the data waveform Channel 1 so that the waveform is centered on the screen c Inthe oscilloscope Delta V menu set the Marker 1 Position to Chan 1 then set Marker 1 at 1 3000 V Set the Marker 2 Position to Chan 1 then set Marker 2 at 1 3000 V d Inthe oscilloscope Delta T menu select Start On Pos Edge 1 Select Stop on Neg Edge 1 Select Precision Edge Find e Ifthe pulse width is outside of the limits adjust the pulse generator channel 1 width and select the oscilloscope Precision Edge Find until the pulse width is within limits
94. ment configuration acquired data to be processed and any inverse assembler loaded in the instrument by the user CRT Controller and Display RAM A Brooktree BT476KPJ66 RAMDAC color palette and a National Semiconductor LM1882CM video frame generator control the CRT One of the RGB outputs of the color palette provides the eight shade grey scale display The video frame generator provides the horizontal and vertical synchronization timing signals The display RAM is made up of two 256Kx4 DRAMS configured as 256K x8 and stores all of the pixel information used by the color palette A serial address counter and an address multiplexer control the DRAM addressing At the conclusion of each video frame the vertical sync signal from the video generator resets the serial address counter and a new frame is generated Disk Drive Controller The disk drive controller consists of a single floppy drive controller IC The floppy drive controller provides all signals to the disk drive including read and write data read and write signals write gate and step signal The floppy drive controller also reads status signals from the disk drive including a track 00 signal disk ready and disk change signal Keypad and Knob Interface The front panel keypad is scanned directly from the microprocessor address bus during the video blanking cycle of the CRT When a front panel key is pressed the associated address bits are fed to the data bus through the pressed key a
95. n 10 Select the clocks to be tested a Select the clock field to be tested then select J KJ as the clock edges b Select Done to exit the Master Clock menu Pnalyzer Format MACHINE 1 Run State Acquisition Mode Full Channel 2K Memory SOMH2 JI Symbols Master Clock EDGES JG qa Setup Hold 3 43 11 12 Testing Performance To test the multiple clock multiple edge state acquisition Press the blue shift key then press the Run key If 2 4 acquisitions are obtained without the Stop Condition Satisfied message appearing then the test passes Press Stop to halt the acquisition Record the Pass or Fail results in the performance test record Test the next setup hold combination a Inthe logic analyzer Format menu select Master Clock b Turn off and disconnect the clocks just tested c Repeat steps 1 through 12 for the next setup hold combination listed in step 1 on page 3 40 until all listed setup hold combinations have been tested When aligning the data and clock waveforms using the oscilloscope align the waveforms according to the setup time of the setup hold combination being tested 0 0 ps or 100 ps hen continue through the complete test 3 44 To test the single clock multiple edge state acquisition Testing the single clock multiple edge state acquisition verifies the performance of the following specifications e Minimum master to master clock time
96. n Circuit also generates a four phase 100 MHz sample synchronization signal for the acquisition ICs operating in the timing acquisition mode The synchronizing signal keeps the internal clocking of the individual acquisition ASICs locked in step with the other ASICs at fast sample rates At slower sample rates one of the acquisition ICs divides the 100 MHz clock signal to the appropriate sample rate The slow speed sample clock is then used by all acquisition ICs Self Tests Description The self tests identify the correct operation of major functional areas in the logic analyzer The self tests are not intended for component level diagnostics Three types of tests are performed on the 1664A logic analyzer the power up self tests the functional performance verification self tests and the parametric performance verification tests The power up self tests are performed when power is applied to the instrument The functional performance verification self tests are run using a separate operating system the performance verification PV operating system The PV operating system resides on a separate disk that must be inserted in the disk drive when running the functional performance verification self tests The system and analyzer tests are functional performance verification tests Parametric performance verification requires the use of external test equipment that generates and monitors test data for the logic analyzer to read The
97. n Edge Find NOTE Testing Performance To test the single clock multiple edge state acquisition c Adjust the pulse generator channel 2 Delay then select Precision Edge Find in the oscilloscope Delta Tmenu Repeat this step until the pulses are aligned according to the setup time of the setup hold combination selected 0 0 ps or 100 ps If the rising clock edge does not appear on the oscilloscope display then add 20 0 ns to the oscilloscope Timebase Delay i Select the clock to be tested a Inthe Master Clock menu select the clock field to be tested then select the clock edge as indicated in the table The first time through this test use the top clock and edge in the following table Clocks Jt Kt b Select Done to exit the Master Clock menu If a Compare file was not created during the single clock single edge test then the first time through this test create a Compare file a Press Run The display should show a checkerboard pattern of alternating A and 5 Scroll through the display to verify b Press the List key In the pop up menu use the RPG knob to move the cursor to Compare Press Select c Inthe Compare menu move the cursor to Copy Listing to Reference then press the Select key d Move the cursor to Specify Stop Measurement and press the Select key Press Select again to turn on Compare At the pop up menu select Compare Move the cursor to the Equal field and press the Sel
98. n the screen a Press each key on the front panel The corresponding key on the screen will change from a light to a dark color Test the knob by turning it in both directions b Note any failures then press the Done key a second time to exit the Front Panel Test The status of the test changes from Untested to Tested 11 12 13 Testing Performance To perform the self tests Select the Display Test A white grid pattern is displayed These display screens are not normally used but can be used to adjust the display Refer to chapter 4 Calibrating and Adjusting for display adjustments a Select Continue and the screen changes to full bright b Select Continue and the screen changes to half bright c Select Continue and the test screen shows the Display Test status changed to Tested Sys PY System Test ROM Test Disk Test status PASSED status PASSED RAM Test status PASSED HP IB Test Front Panel Test status PASSED status TESTED RS 232C Test Display Test status FAILED status TESTED HIL Test All System Tests status PASSED status TESTED Record the results of the tests on the performance test record at the end of this chapter To exit the test system press the System key then select Exit Test in the pop up menu and press the Select key Reinstall the disk containing the operating system then select Exit Test System and press the Select key 3 5
99. nalyzer ill In This Book This book is the service guide for the 1664A Logic Analyzers and is divided into eight chapters Chapter 1 contains information about the logic analyzer and includes accessories specifications and characteristics and equipment required for servicing Chapter 2 tells how to prepare the logic analyzer for use Chapter 3 gives instructions on how to test the performance of the logic analyzer Chapter 4 contains calibration instructions for the logic analyzer Chapter 5 contains self tests and flowcharts for troubleshooting the logic analyzer Chapter 6 tells how to replace assemblies of the logic analyzer and how to return them to Agilent Technologies Chapter 7 lists replaceable parts shows an exploded view and gives ordering information Chapter 8 explains how the logic analyzer works and what the self tests are checking iv Table of Contents 1 General Information Accessories 1 2 Specifications 1 3 Characteristics 1 3 Supplemental Characteristics 1 4 Recommended Test Equipment 1 8 2 Preparing for Use To inspect the logic analyzer 2 2 Ferrites 2 3 To apply power 2 4 To operate the user interface 2 4 To set the line voltage 2 4 To degauss the display 2 5 To clean the logic analyzer 2 5 To test the logic analyzer 2 5 3 Testing Performance To perform the self tests 3 3 To make the test connectors 3 6 To test the threshold accuracy 3 8 Set up the equipm
100. nd look for an appropriate response on the display If the display responds as if the key were pressed replace the elastomeric keypad If the display does not respond as if the key were pressed replace the keyboard Check the RPG connector The RPG connector has a TTL pulse on pins 22 and 24 when the knob is being turned Pin 20 of the connector is 5 V WARNING Troubleshooting To test the disk drive voltages To test the disk drive voltages Refer to chapter 6 Replacing Assemblies for instructions to remove or replace covers and assemblies This procedure is to be performed by service trained personnel aware of the hazards involved such as fire and electrical shock Equipment Required Equipment Critical Specification Recommended Model Part Digitizing Oscilloscope gt 100 MHz Bandwidth Agilent 54600A Turn off the instrument then remove the power cable Remove the instrument cover and the disk drive Reconnect the disk drive cable to the rear of the disk drive Turn the disk drive over so that the solder connections of the cable socket are accessible Connect the power cable insert the operating system disk then turn on the instrument Insert the disk that contains the functional performance verification software and enter the test operating system In the Sys PV menu select the Disk test Insert a disk that has enough available bytes to run the test in the disk drive then select Run Repetitiv
101. nd read by the microprocessor The rotary pulse generator RPG knob is part of the HIL circuitry Pulses and direction of rotation information are directed to an RPG interface IC and then to the HIL loop The microprocessor then reads and interprets the RPG signals and performs the desired tasks Theory of Operation The 1664A Logic Analyzer External Keyboard Interface Agilent proprietary ICs make up the external keyboard interface The ICs establish a link with the controller IC on the external keyboard The keyboard signals are routed through the acquisition circuit board to the CPU board The microprocessor then reads and interprets the external keyboard and mouse information and performs the desired tasks Centronix Interface The instrument parallel printer interface is compatible with industry standard Centronix protocol The interface consists of a controller and drivers receivers The controller conditions parallel data from the microprocessor for transmission At the same time the controller also receives status information for the microprocessor Data flow status and handshaking control are also provided by the controller Optional GPIB Interface The instrument interfaces to GPIB as defined by IEEE Standard 488 2 The interface consists of an GPIB controller and two octal drivers receivers The microprocessor routes GPIB data to the controller The controller then buffers the 8 bit GPIB data bits and generates the bus ha
102. ndshaking signals The data and handshaking signals are then routed to the GPIB bus through the octal line drivers receivers The drivers receivers provide data and control signal transfer between the bus and controller Optional RS 232C Interface The instrument RS 232C interface is compatible with standard RS 232C protocol The interface consists of a controller and drivers receivers The controller serializes parallel data from the microprocessor for transmission At the same time the controller also receives serial data and converts the data to parallel data characters for the microprocessor The controller contains a baud rate generator that can be programmed from the logic analyzer front panel for one of eight baud rates Other RS 232C communications parameters can also be programmed from the logic analyzer front panel The drivers receivers interface the instrument with data communications equipment Slew rate control is provided on the ICs eliminating the need for external capacitors CRT Monitor Assembly The CRT Monitor Assembly consists of a monochrome CRT and a monitor driver board The monitor driver board provides the biasing and control signals for the CRT Pixel information is stored in the display RAM on the CPU board and is routed to the monitor driver board through the acquisition board and the sweep cable Disk Drive The disk drive assembly is a high density disk drive that formats double sided double density or high densi
103. nfigurations This instrument is equipped with a three wire power cable The type of power cable plug shipped with the instrument depends on the country of destination The W10 reference designators table previous page show option numbers of available power cables and plug configurations Block Level Theory 8 3 The 1660 Series Logic Analyzer 8 3 The Logic Acquisition Circuitry 8 6 Self Tests Description 8 9 Power up Self Tests 8 9 System Tests System PV 8 10 Analyzer Tests Analy PV 8 13 GPIB 8 15 RS 232C 8 16 Centronix 8 17 Theory of Operation Theory of Operation This chapter tells the theory of operation for the logic analyzer and describes the self tests The information in this chapter is to help you understand how the logic analyzer operates and what the self tests are testing This information is not intended for component level repair 8 2 Block Level Theory The block level theory is divided into two parts theory for the logic analyzer and theory for the main circuit board A block diagram is shown with each theory The 1664A Logic Analyzer Power Supply The 1664A logic analyzer Main Circuit Board Monitor Assembly CPU ssayddv viva HIL External Keyboard Connector CRT Controller System Memory RAM amp ROM
104. ng charges to return the product to the Buyer However the Buyer shall pay all shipping charges duties and taxes for products returned to Agilent Technologies from another country Agilent Technologies warrants that its software and firmware designated by Agilent Technologies for use with an instrument will execute its programming instructions when properly installed on that instrument Agilent Technologies does not warrant that the operation of the instrument software or firmware will be uninterrupted or error free Limitation of Warranty The foregoing warranty shall not apply to defects resulting from improper or inadequate maintenance by the Buyer Buyer supplied software or interfacing unauthorized modification or misuse operation outside of the environmental specifications for the product or improper site preparation or maintenance No other warranty is expressed or implied Agilent Technologies specifically disclaims the implied warranties or merchantability and fitness for a particular purpose Exclusive Remedies The remedies provided herein are the buyer s sole and exclusive remedies Agilent Technologies shall not be liable for any direct indirect special incidental or consequential damages whether based on contract tort or any other legal theory Assistance Product maintenance agreements and other customer assistance agreements are available for Agilent Technologies products For
105. nterrupts generated by pressing a front panel key or receiving an GPIB or RS 232C command System Tests System PV The system tests are functional performance verification tests The following describes the system tests ROM Test The ROM test performs several checksum tests on various read only memory elements including the system ROM Passing the ROM test implies that the microprocessor can access each ROM memory address and that each ROM segment provides checksums that match previously calculated values RAM Test The RAM test performs a write read operation in each memory location in system dynamic RAM DRAM The video RAM in the display subsystem and the acquisition RAM in the data acquisition subsystem are not tested as part of the RAM test and are tested elsewhere At each DRAM memory location the code that resides at that location is stored ina microprocessor register A test pattern is then stored at the memory location read and compared An inverse test pattern is then stored read and compared The original code is then restored to the memory location This continues until all DRAM memory locations have been tested The static RAM in the real time clock chip is also tested in a similar fashion Passing the RAM test implies that all RAM memory locations can be accessed by the microprocessor and that each memory location can store a logical 1 or a logical 0 8 10 Theory of Operation System Tests System P
106. o turn on Compare At the pop up menu select Compare Move the cursor to the Equal field and press the Select key At the pop up menu select Not Equal Press Done e Move the cursor to the Reference Listing field and select The field should toggle to Difference Listing Analyzer l Compare MACHINE 1 Find Error Compare Specify Stop Difference listing 0 Full Measurement Mask gt Label gt Labl Time Base gt Hex Relative Press the blue shift key then press the Run key If 2 4 acquisitions are obtained without the Stop Condition Satisfied message appearing then the test passes Press Stop to halt the acquisition Record the Pass or Fail results in the performance test record Test the next clock a Press the Format key then select Master Clock b Turn off and disconnect the clock just tested c Repeat steps 4 6 and 7 for the next clock edge listed in the table in step 4 until all listed clock edges have been tested Enable the pulse generator channel 2 COMP with the LED on Check the clock pulse width a Enable the pulse generator channel 1 and channel 2 outputs b Inthe oscilloscope Timebase menu select Delay Using the oscilloscope knob position the clock waveform so that the waveform is centered on the screen c Inthe oscilloscope Delta V menu set the Marker 1 Position to Chan 2 then set Marker 1 at 1 3000 V Set the Marker 2 Position to Chan 2 then set Marker 2 at
107. ock Labels c Testing Performance To test the single clock single edge state acquisition Press the Trigger key Make sure pattern term a is A If not select the field next to a under the label Lab1 Type A then press the Select key Verify the test signal Check the clock pulse width Using the oscilloscope verify that the clock pulse width is 3 50 ns 0 ps or 100 ps a b Enable the pulse generator channel 1 and channel 2 outputs In the oscilloscope Timebase menu select Delay Using the oscilloscope knob position the clock waveform so that the waveform is centered on the screen In the oscilloscope Delta V menu set the Marker 1 Position to Chan 2 then set Marker 1 at 1 3000 V Set Marker 2 Position to Chan 2 then set Marker 2 at 1 3000 V In the oscilloscope Delta T menu select Start On Pos Edge 1 Select Stop on Neg Edge 1 If the pulse width is outside the limits adjust the pulse generator channel 2 width and select the oscilloscope Precision Edge Find until the pulse width is within limits Check the clock period Using the oscilloscope verify that the clock period is 20 ns 0 ps or 250 ps a b In the oscilloscope Timebase menu select Sweep Speed 4 00 ns div Select Delay Using the oscilloscope knob position the clock waveform so that a rising edge appears at the left of the display 3 27 Testing
108. of 10 Comparators Two proprietary 9 channel comparators per pod interpret the incoming data and clock signals as either high or low depending on where the user programmable threshold is set The threshold voltage of each pod is individually programmed and the voltage selected applies to the clock channel as well as the data channels of each pod Each of the comparator ICs has a serial test input port used for testing purposes A test bit pattern is sent from the Test and Clock Synchronization Circuit to the comparator The comparators then propagate the test signal on each of the nine channels of the comparator Consequently all data and clock channel pipelines on the circuit board can be tested by the operating system software from the comparator Acquisition The acquisition circuit is made up of a single Agilent Technologies proprietary ASIC Each ASIC is a 34 channel state timing analyzer and one such ASIC is included for every two logic analyzer pods All of the sequencing pattern range recognition and event counting functions are performed on board the IC In addition to the storage qualification and counting functions the acquisition ASICs also perform master clocking functions All six state acquisition clocks are fed to each IC and the ICs generate their own sample clocks Every time you select RUN the ICs individually perform a clock optimization before data is stored Theory of Operation The Logic Acquisition Circui
109. ollowing steps to create one For subsequent passes through this test skip this step and go to step 6 a Press Run The display should show a checkerboard pattern of alternating As and 5s Verify the pattern by scrolling through the display b Press the List key In the pop up menu use the RPG knob to move the cursor to Compare Press Select c Inthe Compare menu move the cursor to Copy Listing to Reference then select Execute from the pop up menu and press the Select key d Move the cursor to Specify Stop Measurement and press the Select key Press Select again to turn on Compare At the pop up menu select Compare Move the cursor to the Equal field and press the Select key At the pop up menu select Not Equal Press Done e Move the cursor to the Reference Listing field and select The field should toggle to Difference Listing Analyzer l Compare MACHINE 1 Find Error Compare Specify Stop Difference listing 0 Full Measurement Mask gt Label Lab1 Time Base gt Hex Relative 1 2 3 4 5 6 7 6 9 10 11 12 13 14 15 Press the blue shift key then press the Run key If 2 4 acquisitions are obtained without the Stop Condition Satisfied message appearing then the test passes Press Stop to halt the acquisition Record the Pass or Fail results in the performance test record Enable the pulse generator channel 2 COMP with the LED on Check the clock pulse width a
110. owcharts Start your troubleshooting at the top of the first flowchart 5 2 REPLACE FAILED MODULE ACCORDING TO POWER UP SELF TEST PROCEDURE PERFORM POWER UP SELF TEST CHART 2 IS CRT DISPLAYING ANY THING POWER OK IS CRT DISPLAY CORRECT CHART 4 DO SELF TESTS PASS DOES FRONT PANEL KEYBOARD WORK CHART 5 DOES DISK DRIVE WORK CHART 6 SUPPLY VOLTAGES Troubleshooting To use the flowcharts CHART 1 CHART 3 DOES LOGIC ACQUISITION FUNCTION CHART 7 DOES PRINT FUNCTION CHART 8 DOES HIL FUNCTION CHART 9 DOES EXTERNAL TRIGGERING FUNCTION CHART 10 DOES RS 232 C x FUNCTION CHART 11 requires option 020 Troubleshooting Flowchart 1 DOES GP IB FUNCTION CHART 12 01664802 Troubleshooting To use the flowcharts CHART 1 TURN POWER OFF AND CHECK FUSE POSITION RATING AND OPERATION NO REPLACE FUSE CHART 2 REMOVE TOP COVER AND CHECK FAN CONNECTION IS FAN CABLE CONNECTED RESEAT FAN CABLE ON CONNECTOR TURN ON POWER AND CHECK POWER SUPPLY A VOLTAGES POWER OK REMOVE FAN CABLE AND CHECK VOLTAGES SUPPLY VOLTAGES G CHART 3 IS FAN VOLTAGE OK REPLACE FAN
111. p to halt a repetitive test Sys PV System Test ROM Test Repetitive This test checks the system mainf The test computes a checksum for Cance and compares it to a known stor Done 5 18 For a Single run the test runs one time and the screen shows the results Sys PY System Test ROM Test runs 1 failures This test checks the system mainframe ROM The test computes a checksum for the ROM and compares it to a known stored value Done Troubleshooting To run the self tests 13 To exit the ROM Test select Done Note that the status changes to Passed or Failed Sys PY System Test ROM Test status PASSED RAM Test status UNTESTED Disk status Test UNTESTED t IB Tes status UNTESTED Front Panel Test status UNTESTED RS 232C Test status UNTESTED Display Test status UNTESTED HIL Test status UNTESTED All System Tests status UNTESTED 14 Install a formatted disk that is not write protected into the disk drive If option 020 is installed connect an RS 232C loopback connector onto the RS 232C port Run the remaining System Tests in the same manner If option 020 is not installed in the 1664A the RS 232C test will return a FAILED status Select the Front Panel Test 15 16 A screen duplicating the front panel appears on the screen a Press each
112. part to be returned e Name and address of owner e Model number e Serial number e Description of service required or failure indications Remove accessories from the logic analyzer Only return accessories to Agilent Technologies if they are associated with the failure symptoms Package the logic analyzer You can use either the original shipping containers or order materials from an Agilent Technologies sales office For protection against electrostatic discharge package the logic analyzer in electrostatic material Seal the shipping container securely and mark it FRAGILE 6 14 Replaceable Parts Ordering 7 2 Exploded View 7 3 Replaceable Parts List 7 4 Power Cables and Plug Configurations 7 8 Replaceable Parts See Also Replaceable Parts This chapter contains information for identifying and ordering replaceable parts for your logic analyzer Replaceable Parts Ordering Parts listed To order a part on the list of replaceable parts quote the Agilent Technologies part number indicate the quantity desired and address the order to the nearest Agilent Technologies Sales Office Parts not listed To order a part not on the list of replaceable parts include the model number and serial number of the module a description of the part including its function and the number of parts required Address the order to your nearest Agilent Technologies Sales Office Direct mail order system
113. put b Disable any AC voltage to the function generator output and enable the high voltage output c Monitor the function generator DC output voltage with the multimeter 3 8 Testing Performance To test the threshold accuracy Set up the logic analyzer 1 Press the Config key Assign all pod fields to Machine 1 To assign the pod fields select the pod fields then select Machine 1 in the pop up menu 2 Inthe Analyzer 1 box select the Type field Select Timing in the pop up menu Analyzer Configuration Analyzer 1 Analyzer 2 Name MACHINE 1 Type Type Con Unassigned Pods Al J A2 K Connect the logic analyzer 1 Using the 17 by 2 test connector BNC cable and probe tip assembly connect the data and clock channels of pod 1 to one side of the BNC Tee 2 Using a BNC banana cable connect the voltmeter to the other side of the BNC Tee 3 Connect the BNC Tee to the Main Signal output of the function generator MAIN SYNC Oax SIGNAL OUT 3 9 Testing Performance To test the threshold accuracy Test the TTL threshold 1 Press the Format key Select the field to the right of Pod 1 then select TTL in the pop up menu 2 On the function generator front panel enter 1 647 V 1 mV DC offset Use the multimeter to verify the voltage The activity indicators for pod 1 should show all d
114. remove the disk drive bracket remove the four screws that attach the disk drive bracket to the disk drive Reverse this procedure to install the disk drive Check that the following assemblies are properly installed before installing the disk drive e Monitor e Front Panel e Switch Actuator e Main Circuit Board e Power Supply 6 6 WARNING ao Oo AUN Replacing Assemblies To remove and replace the power supply To remove and replace the power supply Using previous procedures remove the following assemblies e Handle e Rear Feet e Cover e Disk Drive Hazardous voltages exist on the power supply To avoid electrical shock disconnect the power from the instrument before performing the following procedures After disconnecting the power wait at least three minutes for the capacitors to discharge before servicing the instrument Lift the PCB locking pins out of the chassis Slide the power supply out far enough to reach the power supply cables then disconnect them from the power supply Slide the power supply the rest of the way out the side of the instrument Reverse this procedure to install the power supply Check that the following assemblies are properly installed before installing the power supply e Monitor e Front Panel e Switch Actuator e Main Circuit Board To remove and replace the Main Circuit board Using previous procedures remove the following assemblies e Handle e Rear
115. robe tip assembly A6 0950 2261 1 Power supply A7 0950 2169 1 Disk drive A8 2090 0304 1 Monitor assembly A9 3160 0829 1 Fan tubeaxial A10 1150 1922 1 Three button mouse E1 5959 9333 Replacement probe leads 5 per package E2 5959 9334 Replacement probe grounds 5 per package E3 5959 9335 Replacement pod grounds 5 per package E4 5090 4356 Grabber kit assembly 20 grabbers per package F1 2110 0055 1 Fuse 4 A 250V H1 1400 0611 1 Clamp cable H2 01660 09101 1 Ground spring H3 01650 46101 2 Locking pin PCB H4 01660 67601 2 BNC connector assembly H5 0515 1363 10 MS 3 0 5TH T10 disk drive handle plate H6 0515 0680 2 MS 3 0 6 PH T10 rear panel to HIL connector H7 0380 1858 2 Jackscrew with lock printer port to rear panel H8 0515 0430 11 MS M3 0X0 5X6MM PH T10 main circuit assembly rear panel to chassis RS 232C GPIB cover plate H9 0515 2349 5 MS M3 0X0 50X14MM LG trim strip cover to cabinet H10 0515 1035 2 MSFH M3 8 T10 line filter H11 0515 1103 2 MSFH M3 10 T10 trim strip cover to cabinet H12 0515 0664 4 MSPH M3 12 SMS10 rear feet to cabinet H13 2950 0072 1 NUTH 1 4 32 062 intensity adjustment H14 2950 0001 2 NUTH 3 8 32 093 BNC trigger ports H15 0535 0056 3 NUT HEX monitor assembly H16 0515 0382 3 SM ASSY M4X0 7 12MM LG monitor assembly handle H17 0515 1349 4 SM M3X0 5 30MM LG front panel assembly H18 3050 0010 4 WFL 147 312 03 rear feet H19 2190 0027 1 WIL 256 478 02 intensity adjustment H20 2190 0016 2 WI
116. s full calibration refer to chapter 3 Testing Performance Set up the equipment Turn on the logic analyzer Let it warm up for 30 minutes if you have not already done so 4 2 WARNING To adjust the CRT monitor alignment Do not touch the CRT monitor sweep board High voltages exist on the sweep board that can cause personal injury Equipment Required Equipment Critical Specification Recommended Model Part Alignment Tool 1 8710 1300 Turn off the logic analyzer then disconnect the power cord Remove the cover Refer to chapter 6 Replacing Assemblies for instructions to remove the cover Connect the power cord insert the operating system disk into the disk drive then turn on the logic analyzer Insert the disk containing the functional performance verification tests normally the same disk into the disk drive then load the functional performance verification operating system into the logic analyzer refer to Chapter 3 To Perform Self Tests 4 3 Calibrating and Adjusting To adjust the CRT monitor alignment 4 Enter the Sys PV tests then enter the Display Test A grid pattern should appear b ie 5 Ifthe display is tilted rotated adjust the CRT yoke by rotating it to straighten the display
117. se width Agilent 8131A Option 020 lt 600 ps rise time Adapter Qty 4 SMA m BNC f Agilent 1250 1200 Coupler Qty 4 BNC m m Agilent 1250 0216 6x2 Test Connectors Qty 4 Turn on the equipment required Insert the operating system disk and turn on the logic analyzer Set up the pulse generator a Set up the pulse generator according to the following table Pulse Generator Setup Channel 1 Channel 2 Period Delay 0 ps Delay 0 ps 100 ns Dty 50 Dty 50 High 3 00 V High 3 00 V Low 0 00 V Low 0 00 V b Enable the pulse generator channel 1 and channel 2 outputs with the LEDs off Set up the logic analyzer Configuration menu a Press the Config key b Inthe Analyzer 1 box select the field to the right of Type then select State Analyzer Configuration Cance Analyzer 1 Analyzer 2 Name MACHINE 1 Type Type Coot Unassigned Pods Alt Kig A2 K 5 28 Troubleshooting To test the logic analyzer probe cables 4 Set up the Format menu a Press the Format key b Move the cursor to the field showing the channel assignments for the pod under test Press the Clear Entry key until the pod channels are all assigned all asterisks Press the Done key analyzer Format MACHINE 1 Run State Acquisition Mode Master Clock Full Channel 4k Memory SomHz Jt Symbols Clock Inputs Pod A2 EcL J Poa ar Master Clock Master Clock a p Labels
118. sition Circuitry 8 6 Self Tests Description 8 9 Power up Self Tests 8 9 System Tests System PV 8 10 Analyzer Tests Analy PV 8 13 GPIB Optional 8 15 RS 232C Optional 8 16 Centronix 8 17 Contents viii Accessories 1 2 Specifications 1 3 Characteristics 1 3 Supplemental Characteristics 1 4 Recommended Test Equipment 1 8 General Information General Information This chapter lists the accessories the specifications and characteristics and the recommended test equipment Accessories The following accessories are supplied with the 1664A Logic Analyzers Accessories Supplied Part Number Qty Probe tip assemblies 01650 61608 2 Probe cables 16550 61601 1 Grabbers 20 per pack 5090 4356 2 Probe ground 5 per pack 5959 9334 2 User s Reference 01660 90904 1 Accessories Pouch 01660 84501 1 HIL Mouse A2838A 1 Accessories Available Other accessories available for the 1664A Logic Analyzer are listed in the Accessories for Agilent Logic Analyzers brochure The table below lists additional documentation that is available from your nearest Agilent Technologies sales office for use with your logic analyzer Accessories Available Part Number Demo Training Kit E2433 60007 Programming Reference 01660 90933 Service Guide 01664 97005 1 2 General Information Specifications Specifications The specifications are the performance standards against which the product is tested Ma
119. stall the rear panel Check that the following assemblies are properly installed before installing the rear panel e Monitor e Main Circuit Board When installing the rear panel check that the connectors on the main circuit board are lined up with the corresponding holes in the rear panel 6 9 Replacing Assemblies To remove and replace the front panel and keyboard To remove and replace the front panel and keyboard Using previous procedures remove the following assemblies e Handle e Rear Feet e Cover e Disk Drive e Power Supply e Main Circuit board Remove the four screws connecting the front panel Slide the front panel assembly out the front of the instrument Slide the spacers out the front of the instrument to remove them Be careful not to lose the copper ground strips on the spacer When installing the spacer insert the pins of the spacer in the appropriate holes in the chassis You can hold the spacer in place while installing the front panel by holding it with your finger through the disk drive mounting slot in the chassis Remove the RPG knob by pulling the knob off the RPG shaft Disassemble the front panel assembly by lifting the keyboard circuit board away from the front panel Lift the elastomeric keypad out of the front panel Reverse this procedure to assemble and install the front panel assembly When assembling the front panel check that the holes in the elastomeric keypad and the key
120. t 6 ns Replace Sequence Level equisition Control Delete Sequence Level Add Sequence Level Modify Trigger Clear Trigger Break Down Macros Edgel Cancel Edge2 4 Using the Precision Edge Find in the Delta T menu of the oscilloscope verify that the pulse widths of the pulse generator channels 1 and 2 are 3 450 ns 50 ps or 100 ps If necessary adjust the pulse widths of the pulse generator channels 1 and 2 Sr SSI URGE Tis Tale OEE SER Pema enter se om 5 Set up the Waveform menu to view all the channels a Select one of the Glitch labels then select Delete All in the pop up menu b Select All then select continue c Press the Select key then select Insert in the pop up menu d Press the Select key then select Sequential in the pop up menu 3 21 Testing Performance To test the glitch capture 6 On the logic analyzer press the Run key The display should be similar to the figure below Analyzer Waveform MACHINE 1 aca Control Accumulate Current Sample Period 6 000 ns off Next Sample Period 8 000 ns pma sec Div Delay Markers Acquisition Time 100 ns 0 s off 23 Aug 1993 13 57 50 7 On the pulse generator enable Channel 1 and Channel 2 COMP with the LED on 8 On the logic analyzer press the Run key The display should be similar to the figure below Record Pass or Fail in the performance test record anaiyzer
121. t A grid pattern should appear Press the front panel Select key The display should show a full bright test screen 5 Turn the rear panel intensity adjustment to full bright 6 Place the light power meter against the display at center screen Calibrating and Adjusting To adjust the CRT intensity LOW BRIGHT SUBBRIGHT FOCUS CONTRAST V LIN V SIZE V HOLD H HOLD 01660E22 WARNING Do not touch the CRT monitor sweep board High voltages exist on the sweep board that can cause personal injury 7 The light power meter should read 137 154 cd m If the measurement is out of this range use the adjustment tool to adjust the Contrast potentiometer on the monitor driver board 8 Press the front panel Select key The display should show a half bright test screen 9 Place the light power meter against the display at center screen The light power meter should read 5 27 cd m If the reading is not correct try adjusting the contrast in step 7 closer to the limit 10 Press the front panel Select key The logic analyzer should exit the Display Test 11 Place the light power meter against the display at center screen Adjust the rear panel intensity adjustment until the light power meter reads 45 55 cd m 12 Exit the functional performance verification tests 13 Turn off the instrument then remove the power cord Install the cover on the instrument 4 6
122. t a logic high 3 Using the Modify down arrow on the function generator decrease offset voltage in 1 mV increments until all activity indicators for pod 1 show the channels at a logic low Record the function generator voltage in the performance test record Analyzer Format MACHINE 1 Timing Acquisition Mode Conventional Full Channel 250 MHz Symbols Clock Inputs Pod A2 Pod Al 6 00 L Labels zm 4 Using the Modify up arrow on the function generator increase offset voltage in 1 mV increments until all activity indicators for pod 1 show the channels at a logic high Record the function generator voltage in the performance test record Analyzer Format MACHINE 1 Cance Timing Acquisition Mode Conventional Full Channel 250 MHz Symbols Clock Inputs Pod A2 Pod Al 6 00 L Labels z Labi Lab2 Lab3 Lab4 Labs Lab6 Lab oml Lab 3 14 Testing Performance To test the threshold accuracy Test the 0 V User threshold 1 Move the cursor to the field to the right of Pod 1 Type 0 then press the Select key 2 On the function generator front panel enter 0 102 V 1 mV DC offset Use the multimeter to verify the voltage The activity indicators for pod 1 should show all data channels and the J clock channel at a logic high 3 Using the Modify down arrow on the function
123. t screen The pass or fail status of the display test is determined by the operator The Display Test passes when all three test screens are displayed according to chapter 4 Calibrating and Adjusting The display test is not used when Perform Test All is selected 8 12 Theory of Operation Analyzer Tests Analy PV Analyzer Tests Analy PV The analyzer tests are functional performance verification tests There are three types of analyzer tests the Board Test the Chip Test and the Data Input Inspection The following describes the analyzer self tests Board Test The Board Test functionally verifies the two oscillators and the 9 channel comparators on the circuit board First the oscillators are checked using the event counter on one of the acquisition ICs The event counter will count the number of oscillator periods within a pre determined time window The count of oscillator periods is then compared with a known value The comparators are then checked by varying the threshold voltage and reading the state of the activity indicators The outputs of the octal DAC are set to the upper voltage limit and the activity indicators for all of the pod channels are read to see if they are all in a low state The octal DAC outputs are then set to the lower voltage limit and the activity indicators are read to see if they are in a high state The DAC outputs are then set to 0 0 V allowing the comparators to recognize the test s
124. t up the equipment Turn on the equipment required and the logic analyzer Let them warm up for 30 minutes before beginning the test if you have not already done so Set up the pulse generator a Set up the pulse generator according to the following table Pulse Generator Setup Channel 1 Channel 2 Period Delay 0 ps Doub 20 0 ns 40 ns Width 3 5 ns Width 3 5 ns High 0 9 V High 0 9 V Low 1 7 V Low 1 7 V b Disable the pulse generator channel 2 COMP with the LED off 3 23 Testing Performance To test the single clock single edge state acquisition Set up the oscilloscope Oscilloscope Setup Time Base Display Delta V Delta T Time Div 1 00 ns div avg V markers on T markers on of avg 16 marker 1 position Chan 1 start on Pos Edge 1 screen dual marker 2 position Chan 1 stop on Neg Edge 1 Channel Channel 1 Channel 2 Display on on Probe Atten 20 00 20 00 Offset 13V 13V Volts Div 400 mV 400 mV Set up the logic analyzer Set up the Configuration menu a Press the Config key b Inthe Configuration menu assign all pods to Machine 1 To assign the pods select the pod fields then select Machine 1 in the pop up menu c Select the Type field in the Analyzer 1 box then select State Analyzer 1 Name MACHINE 1 2 Set up the Format menu a Press the Format key Select State Acquisition Mode then select Full Channel 4K Memory 50MHz b Select the f
125. ten read and compared After verifying correct operation of the VRAM the System RAM and real time clock RAM are tested ina similar fashion Passing the RAM test implies that the microprocessor can access each VRAM memory location and that each VRAM memory location can store a logical 1 or a logical 0 If the VRAM is functioning properly the logic analyzer can construct a correct undistorted display Passing the RAM test also implies that the memory locations of system RAM can be accessed by the microprocessor and the data in RAM is intact and that the memory locations inside the real time clock IC can store a logical 1 or a logical 0 Interrupt Test The Interrupt Test checks the microprocessor interrupt circuitry With all interrupts disabled from their source the microprocessor waits for a short period of time to see if any of the interrupt lines are asserted An asserted interrupt line during the wait period signifies incorrect functioning of the device generating the interrupt or the interrupt circuitry itself Those interrupts that can be asserted under software control are exercised to verify functionality Passing the Interrupt Test implies that the interrupt circuitry is functioning properly Passing the Interrupt Test also implies that the interrupt generating devices are also functioning properly and not generating false interrupts This means that the microprocessor can execute the operating system code and properly service i
126. tes The following list of pages gives the date of the current edition and of any changed pages to that edition All pages original edition
127. test fails check the test equipment set up check the connections and verify adequate grounding Ifa test still fails the most probable cause of failure would be the main circuit board Test Interval Test the performance of the logic analyzer against specifications at two year intervals or if it is replaced or repaired Performance Test Record A performance test record for recording the results of each procedure is located at the end of this chapter Use the performance test record to gauge the performance of the logic analyzer over time Test Equipment Each procedure lists the recommended test equipment You can use equipment that satisfies the specifications given However the procedures are based on using the recommended model or part number Before testing the performance of the logic analyzer warm up the instrument and the test equipment for 30 minutes 3 2 To perform the self tests The self tests verify the correct operation of the logic analyzer Self tests can be performed all at once or one at a time While testing the performance of the logic analyzer run the self tests all at once 1 Disconnect all inputs insert the boot disk then turn on the power switch Wait until the power up tests are complete 2 Press the System key Select the field next to System then select Test in the pop up menu then press the Select key Disk Load from file PYTEST_ Printer Controller
128. then use the RPG knob to dial in 2 00 us c Select the Markers Off field then select Pattern d Select the Specify Patterns field Select X entering 1 and O entering 1 Base gt Cen C D Stop measurement Clear Pattern Select Done to exit the Specify Patterns menu Move the cursor to the X pat field Type 1 then press Done Move the cursor to the O pat field Type 20 then press Done Select the Markers Patterns field then select Statistics Select Reset Statistics to initialize the statistics fields a mh o Connect the logic analyzer 1 Using a 6 by 2 test connector connect channel 0 of Pod 1 to the pulse generator channel 1 output 2 Using the SMA cable and the BNC adapter connect the External Input of the pulse generator to the Main Signal of the function generator 8131A Externat Channel 7 Channel 2 Input Output Output Output Output o o o O o J o aalan E la 7 galoo aan Q Dl o al a Baad istela Q 01660E20 Testing Performance To test the time interval accuracy Acquire the data Enable the pulse generator channel 1 output with the LED off 2 Press the blue key then press the Run key to select Run Repetitive Allow the logic analyzer to acquire data for at least 100 valid runs as indicated in the pattern statistics field When the log
129. tion without waiting for a claim settlement 2 2 Preparing for Use Ferrites Ferrites Ferrites are included in the 1664A accessory pouch for the logic analyzer cable When properly installed the ferrites reduce RFI emissions from the logic analyzer In order to ensure compliance of the 1664A Logic Analyzer to the CISPR11 Class A radio frequency interference RFD limits you must install the ferrite to absorb radio frequency energy Note Adding or removing the ferrite will not affect the normal operation of the analyzer Ferrite Installation Instructions Use the following steps to install the ferrite on the logic analyzer cable 1 Place the ferrite halves and spacer on the logic analyzer cable like a clamshell around the whole cable The ferrite should be 10 cm about 4 in from the the end of the cable shell as shown 10 cm Z 4 inches 2 Insert the clamps onto the ends of the ferrites The locking tab should fit cleanly in the ferrite grooves 01664E06 When properly installed the ferrite should appear on the logic analyzer cable as shown 4 inches 01664E04 2 3 CAUTION Preparing for Use To apply power To apply power Electrostatic discharge can damage electronic components Use grounded wriststraps and mats when performing any service to the logic analyzer Check that the line voltage selector located on the rear panel is on the correct setting and the correct
130. tor is operating within limits Equipment Required Equipment Critical Specifications Recommended Model Part Pulse Generator 100 MHz 3 5 ns pulse width lt 600 ps rise time Agilent 8131A Option 020 Function Generator Accuracy lt 5 10 x frequency Agilent 3325B Option 002 SMA Cable Agilent 8120 4948 Adapter BNC m SMA f Agilent 1250 2015 BNC Test Connector 6x2 Set up the equipment Turn on the equipment required and the logic analyzer Let them warm up for 30 minutes if you have not already done so Set up the pulse generator according to the following table Pulse Generator Setup Channel 1 Period Mode EXT TRIG Delay 0 ps 5 us TRIG Slope Positive Width 2 5 us THRE 1 0 V High 0 9 V Low 1 7 V COMP Disabled LED off 3 54 Testing Performance To test the time interval accuracy 3 Set up the function generator according to the following table Function Generator Setup Freq 200 000 0 Hz Main Function Square wave Amptd 3 000 V High Voltage Disabled LED Off Phase 0 0 deg DC Offset 0 0 V Set up the logic analyzer 1 Set up the Configuration menu a Press the Config key b Inthe Configuration menu assign Pod 1 to Machine 1 To assign Pod 1 select the Pod 1 field then select Machine 1 c Inthe Analyzer 1 box select the Type field then select Timing Analyzer Configuration d Pods Analyzer 1 Analyzer 2 Name MACHINE 1 Type Types C
131. try Clock optimization involves using programmable delays on board the IC to position the master clock transition where valid data is captured This procedure greatly reduces the effects of channel to channel skew and other propagation delays In the timing acquisition mode an oscillator driven clock circuit provides a four phase 100 MHz clock signal to each of the acquisition ICs For high speed timing acquisition 100 MHz and faster the sample period is determined by the four phase 100 MHz clock signal For slower sample rates one of the acquisition ICs divides the 100 MHz clock signal to the appropriate sample rate The sample clock is then fed to all acquisition ICs Threshold A precision octal DAC and precision op amp drivers make up the threshold circuit Each of the eight channels of the DAC is individually programmable which allows you to set the thresholds of the individual pods The 16 data channels and the clock channel of each pod are all set to the same threshold voltage Test and Clock Synchronization Circuit ECLinPS TM ICs are used in the Test and Clock Synchronization Circuit for reliability and low channel to channel skew Test patterns are generated and sent to the comparators during software operation verification The test patterns are propagated across all data and clock channels and read by the acquisition ASIC to ensure both the data and clock pipelines are operating correctly The Test and Clock Synchronizatio
132. ty disks in LIF or DOS format A disk drive controller on the CPU board controls the disk drive Signals are routed directly to the disk drive through the disk drive cable Power Supply A low voltage power supply provides all DC voltages needed to operate the logic analyzer The power supply also provides the 5 Vdc voltage to the probe cables to power logic analyzer accessories and preprocessors Unfiltered voltages of 12 V 12 V 5 V 5 2 V and 3 5 V are supplied to the acquisition board where they are filtered and distributed to the CPU board CRT Monitor Assembly and probe cables Theory of Operation The Logic Acquisition Circuitry The Logic Acquisition Circuitry Pods 1 amp 2 Test amp Clack Optimization Circuit COMPARATORS TERMINATION ADDRESS Connects to CPU Acquisition IC COMPARATORS POD2 x amp lt o raaa SRGRON SOOVMOUAWN O05 Melerelelerlelelerelolereleleralerelare Malerelelerlelelereloleleleleralereloye TERMINATION Clock amp Data Threshold 01664517 The Main Circuit Board Logic Acquisition Circuitry 8 6 Theory of Operation The Logic Acquisition Circuitry Main Circuit Board Logic Acquisition Theory Probing The probing circuit includes the probe cable and terminations The probe cable consists of two 17 channel pods which are connected to the circuit board using a hig
133. unded wriststraps and mats when performing any service to this logic analyzer Tools Required 10 TORX screwdriver 15 TORX screwdriver 1 Posidrive screwdriver 3 16 inch 5 mm nut driver 9 32 inch 7 mm nut driver Replacing Assemblies Exploded View Listing Al Main circuit board MP3 Fan guard MP32 Spacer A2 Keyboard MP4 Rear panel MP33 Label A3 Switch actuator MP5 Line filter A4 Probe cable MP6 Handle plate W1 Fan cable A5 Probe tip MP7 Ground bracket W2 Disk drive cable A6 Power supply MP8 Cabinet W3 Jumper cable orange A7 Disk drive MP9 Cover W4 Jumper cable white A8 Monitor assembly MP15 Rear feet w5 Power supply cable A9 Fan MP18 Mounting plate W6 Front panel cable MP19 Insulator W7 Monitor sweep cable H2 Ground spring MP20 Trim strip W8 GPIB cable H3 Locking pin MP21 Label w9 RS 232C cable H4 BNC connector MP22 Label H22 Cable retaining screw MP23 Elastomeric keypad MP24 RPG knob MP1 Intensity adjustment MP25 Keyboard panel MP2 Disk drive bracket MP26 Keyboard spacer 6 3 Replacing Assemblies I MP15 4 MP 33 01664E01 Exploded View of the 1664A 6 4 A Ne Replacing Assemblies To remove and replace the handle To remove and replace the handle Remove the two screws in the endcaps then lift off the handle To remove and replace the feet and tilt stand Remove the screws connecting the four rear feet to the instrument Separate the r
134. unt 4 29 x 10 Timing Analysis Sample Period Accuracy 0 01 of sample period Channel to Channel Skew 2 ns typical Time Interval Accuracy sample period channel to channel skew 0 01 time reading Triggering Sequencer Speed 125 MHz maximum State Sequence Levels 12 Timing Sequence Levels 10 Maximum Occurrence Counter Value 1 048 575 Pattern Recognizers 10 Maximum Pattern Width 34 channels Range Recognizers 2 Range Width 32 bits each Timers 2 Timer Value Range 400 ns to 500 seconds Glitch Edge Recognizers 2 timing only Maximum Glitch Edge Width 34 channels Maximum state clock rate with time or state tags on is 50 MHz When all pods are assigned to a state or timing machine time or state tags halve the memory depth General Information Supplemental Characteristics Measurement and Display Functions Displayed Waveforms 24 lines maximum with scrolling across 96 waveforms Measurement Functions Run Stop Functions Run starts acquisition of data in specified trace mode Stop In single trace mode or the first run of a repetitive acquisition Stop halts acquisition and displays the current acquisition data For subsequent runs in repetitive mode Stop halts acquisition of data and does not change the current display Trace Mode Single mode acquires data once per trace specification Repetitive mode repeats single mode acquisitions until Stop is pressed or until the time interval between two spe
135. ve the fuse module by carefully prying at the top center of the fuse module until you can grasp it and pull it out by hand 3 Reinsert the fuse module with the arrow for the appropriate line voltage aligned with the arrow on the line filter assembly switch 4 Reconnect the power cord Turn on the instrument by setting the power switch to the On position To degauss the display If the logic analyzer has been subjected to strong magnetic fields the CRT might become magnetized and display data might become distorted To correct this condition degauss the CRT with a conventional external television type degaussing coil To clean the logic analyzer With the instrument turned off and unplugged use mild soap and water to clean the front and cabinet of the logic analyzer Harsh soap might damage the water base paint To test the logic analyzer e If you require a test to verify the specifications start at the beginning of chapter 3 Testing Performance e If you require a test to initially accept the operation perform the self tests in chapter 3 e Ifthe logic analyzer does not operate correctly go to the beginning of chapter 5 Troubleshooting 2 5 2 6 To perform the self tests 3 3 To make the test connectors 3 6 To test the threshold accuracy 3 8 To test the glitch capture 3 17 To test the single clock single edge state acquisition 3 23 To test the multiple clock multiple edge state
136. ximum State Speed Minimum State Clock Pulse Width Minimum Master to Master Clock Time Minimum Glitch Width Threshold Accuracy Setup Hold Time Single Clock Single Edge Single Clock Multiple Edges Multiple Clocks Multiple Edges 50 MHz 3 5 ns 20 0 ns 3 5 ns 100 mV 3 of threshold setting 0 0 3 5 ns through 3 5 0 0 ns adjustable in 500 ps increments 0 0 4 0 ns through 4 0 0 0 ns adjustable in 500 ps increments 0 0 4 5 ns through 4 5 0 0 ns adjustable in 500 ps increments Specified for an input signal VH 0 9 V VL 1 7 V slew rate 1 V ns and threshold 1 3 V Characteristics These characteristics are not specifications but are included as additional information Maximum State Clock Rate Maximum Conventional Timing Rate Maximum Transitional Timing Rate Maximum Timing with Glitch Rate Memory Depth Channel Count For all modes except glitch Full Channel Half Channel 50 MHz 50 MHz 250 MHz 500 MHz 125 MHz 250 MHz N A 125 MHz 4K 8K 34 17 1 3 General Information Supplemental Characteristics Supplemental Characteristics Probes Input Resistance 100 kQ 2 Input Capacitance 8pF Minimum Voltage Swing 500 mV peak to peak Threshold Range 6 0 V adjustable in 50 mV increments State Analysis State Clock Qualifiers 6 Time Tag Resolution 8 ns or 0 1 whichever is greater Maximum Time Count Between States 34 seconds Maximum State Tag Co
137. y divider for slower timing sample rates is checked Passing the clock generator test implies that each acquisition IC can generate its own master clock whether the clock is generated using a combination of external clocking signals state mode or internal sample clock signals timing mode Data Input Inspection The data input inspection allows a user to verify that all of the data and clock data pipelines are operational When the data input inspection test is selected a test signal is fed to the test input pins of all 9 channel comparators The test menu displays the activity indicators for all data and clock data channels which should show transitioning data signals on all channels The data input inspection is not an active part of the performance verification However the test is useful for identifying failed channels in order to temporarily work around the problem until the logic analyzer module can be sent to an Agilent Technologies service center for repair 8 14 GPIB Optional The General Purpose Interface bus GPIB is Agilent Technologies implementation of IEEE Standard 488 1978 Standard Digital Interface for Programming Instrumentation GPIB is a carefully defined interface that simplifies the integration of various instruments and computers into systems The interface makes it possible to transfer messages between two or more GPIB compatible devices GPIB is a parallel bus of 16 active signal lines divid
138. y service trained personnel aware of the hazards involved such as fire and electrical shock Loaded by the acquisition board Turn off the instrument then remove the power cable Remove the cover of the instrument Connect the power plug then turn on the instrument Check for the 5 V as indicated by the figure below Loaded by the added resistor Turn off the instrument then remove the power cable Remove the cover of the instrument and the disk drive assembly Remove the power supply far enough to disconnect the power supply cable from the acquisition board Bring the end of the cable up and out of the instrument Use the disconnected cable to load the supply and to make measurements Load the 5 00 V supply with a 2 Q 25 watt resistor a With a jumper wire connect one end of the resistor to one of the 5 00 V pins pins 1 through 4 on the supply cable b With another jumper wire connect the other end of the resistor to one of the ground pins pins 5 through 7 on the supply cable Connect the power plug then turn on the instrument Check for the 5 V as indicated by the figure below COM 5 00V 5 V ADJ 1660E23 5 21 Troubleshooting To test the power supply voltages Check for the voltages on the power supply cable using the values in the following table Signals on the Power Supply Cable

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