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1. VOLTAGE SELEGTOR DISPLAY OUTPUT BANK SELECT CONTROL AND BLINK CONTROL LCD BIAS GENERATOR Vss PCF8534A DISPLAY CLK RAM CLOCK SELECT BLINKER SYNG AND TIMING TIMEBASE POWER ON COMMAND WRITE DATA DATA POINTER AND OSG OSCILLATOR RESET DECODE CONTROL AUTO INCREMENT SCL INPUT I2C BUS SUBADDRESS SDA FILTERS CONTROLLER COUNTER SA0 Vpp AO Ai A2 001aah614 Fig 1 Block diagram of PCF8534A PCF8534A All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 3 of 52 NXP Semiconductors PC F8534A Universal LCD driver for low multiplex rates 6 Pinning information 6 1 Pinning ononmnrnre wo WO TMDANWN ri idoeme aAaere OLDO TODO N TK BHDGBDHDADBDDBDSDDDGZODDOGDOHS 2 2 RAISINS 28 5 slie lele s31 1 O 60 S10 32 2 59 S9 33 3 58 S8 S34 4 57 S7 35 5 56 S6 S36 6 55 S5 s37 7 54 S4 S38 8 53 S3 s39 9 52 S2 ee PCF8534AHL s41 11 50 So s42 12 49 Vicp S43 13 48 Vss S44 14 47 SAO 45 15 46 A2 S46 16 45 A1 847 17 44 AO S48 18 43 OSC s49 19 42 SYNC 50 20 41 VoD aiek blk elelee orsaaarse BERRRRRRREESE SEL LaB a Top view For mechanical details see Figure 25 Fig 2 Pin configuration for SOT315 1 PCF8534AHL PCF8534A All information provided in this document is subject to legal
2. IE BUS D PCF8534A Universal LCD driver for low multiplex rates Rev 6 25 July 2011 Product data sheet 1 General description The PCF8534A is a peripheral device which interfaces to almost any Liquid Crystal D isplay LCD with low multiplex rates It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 60 segments It can be easily cascaded for larger LCD applications The PCF8534A is compatible with most microcontrollers and communicates via the two line bidirectional C bus Communication overheads are minimized by a display RAM with auto incremented addressing by hardware subaddressing and by display memory switching static and duplex drive modes e PCF8534AHL 1 should not be used for new design ins Replacement part is PCF85134HL 1 2 Features and benefits AEC Q100 compliant PCF8534AH 1 for automotive applications Single chip LCD controller and driver Selectable backplane drive configurations static or 2 3 or 4 backplane multiplexing 60 segment outputs allowing to drive 30 7 segment numeric characters 15 14 segment alphanumeric characters Any graphics of up to 240 elements Cascading supported for larger applications 60 x 4 bit display data storage RAM Wide LCD supply range from 2 5 V for low threshold LCDs up to 6 5 V for high threshold twisted nematic LCDs Internal LCD bias generation with voltag
3. EXAMPLES a transmit two bytes of RAM data I s I s o 1110 ojAjojajo 1 A RAM DATA A RAMDATA alP LI _ b transmit two command bytes 0 1 1 1 0 OJAJO A 1 0 A COMMAND AJO 0 A COMMAND A P c transmit one command byte and two RAM date bytes S O0 1 1 1 0 OJAJO A 1 0 A COMMAND Ajo 1 A RAM DATA A RAM DATA A P mgl752 Fig 18 1 C bus protocol After acknowledgement the control byte is sent defining if the next byte is a RAM or command information The control byte also defines if the next byte is a control byte or further RAM or command data see Figure 19 and Table 17 In this way it is possible to configure the device and then fill the display RAM with little overhead MSB LSB 7 e6 5l4al3latito co RS not relevant mg 753 Fig 19 Control byte format Table 17 Control byte description Bit Symbol Value Description 7 CO continue bit 0 last control byte control bytes continue 6 RS register selection 0 command register data register 5 to0 z unused The command bytes and control bytes are also acknowledged by all addressed PCF8534A connected to the bus The display bytes are stored in the displ
4. 2 Vicp Sn Vsg ___ J Vicp Sn 1 Vss a Waveforms at driver VLCD VLcD 2 state 1 oV Vicp 2 Vicb VLCD Vicp 2 Vicp 2 VLCD b Resultant waveforms 013aaa208 at LCD segment Vstatet t Vsn t Vepo t Von ams 0 791Vicp Vstatea t Vsn t Vapi t Vott RMS 0 354V icp Fig 8 Waveforms for the 1 2 multiplex drive mode with 1 bias PCF8534A All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 13 of 52 NXP Semiconductors PCF8534A Universal LCD driver for low multiplex rates Fig 9 a Tf gt S O 0 LCD segments sr Vicos ee pf state 1 state 2 2Vicp 3 met Voos Oe N lt Q s p o Sn N lt E Q Q lt o Sn 1 lt lt O g a Waveforms at driver 2VLceD3 _ _ Vicp 3 state 1 OV Vicp 3 __ 2Vicp 3_ Vicp VLcb 2Vicp 3 Vicp 3 state 2 0 V Vicp 3 2Vicp 3_ _ VLCD b Resultant waveforms at LCD segment 013aaa209 Vstate1 t Vsn t Vepo t Von RMS 0 745Vicp Vstate2 t Vsn t Vsp t Vott aMs 0 333Vicp Waveforms for the 1 2 multiplex drive mode with 13 bias
5. PCF8534A All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 14 of 52 NXP Semiconductors PCF8534A Universal LCD driver for low multiplex rates 7 4 3 1 3 Multiplex drive mode When three backplanes are provided in the LCD the 1 3 multiplex drive mode applies as shown in Figure 10 BPO BP1 BP2 Sn Sn 1 Sn 2 state 1 state 2 Vicb 2VicpD 3 Vicp 3 Vss LCD segments e060 state 1 Vicb 2Vicp 3 Vicp 3 Vss state 2 O VicD 2Vicp 3 Vicp 3 Vss O0 VicD 2Vicp 3 Vicp 3 Vss Vicb 2VicpD 3 Vicp 3 Vss VLCD 2VLcp 3 VLep 3 Vss a Waveforms at driver Vicp 2Vicp 3 Vicp 3 OV Vicp 3 2Vicp 3_ VLCD VLeD 2VLcp 3 Vicp 3 0 V Vicp 3 2Vicp 3 VLCD b Resultant waveforms at LCD segment 013aaa210 Vstatet t Vsn t Vepo t Von ams 0 638Vicp Vstatea t Vsn t VBp1 t Voft Rms 0 333Vi cp Fig 10 Waveforms for the 1 3 multiplex drive mode with 1 bias PCF8534A All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 15 of 52 NXP Semiconductors PCF8534A Universal LCD driver for low
6. Universal LCD driver for low multiplex rates maximum peak temperature MSL limit damage level temperature minimum peak temperature minimum soldering temperature peak temperature time 001aac844 MSL Moisture Sensitivity Level Fig 30 Temperature profiles for large and small components For further information on temperature profiles refer to Application Note AN10365 Surface mount reflow soldering description 19 Abbreviations Table 28 Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model IC Integrated Circuit LCD Liquid Crystal Display MM Machine Model RAM Random Access Memory PCF8534A All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 48 of 52 NXP Semiconductors PC F8534A Universal LCD driver for low multiplex rates 20 References 1 AN10365 Surface mount reflow soldering description 2 IEC 60134 Rating systems for electronic tubes and valves and analogous semiconductor devices 3 IEC 61340 5 Protection of electronic devices from electrostatic phenomena 4 IPC JEDEC J STD 020D Moisture Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices 5 JESD22 A114 Electrostatic Discharge ESD Sensitivity Testin
7. C bus is for bidirectional two line communication between different ICs or modules The two lines are a Serial DAta Line SDA and a Serial CLock line SCL Both lines must be connected to a positive supply via a pull up resistor when connected to the output stages of a device Data transfer may be initiated only when the bus is not busy Bit transfer One data bit is transferred during each clock pulse The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal see Figure 14 data line change stable of data data valid allowed mba607 Fig 14 Bit transfer START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy A HIGH to LOW change of the data line while the clock is HIGH is defined as the START condition S A LOW to HIGH change of the data line while the clock is HIGH is defined as the STOP condition P The START and STOP conditions are illustrated in Figure 15 oH os START condition STOP condition mbc622 Fig 15 Definition of START and STOP conditions System configuration A device generating a message is a transmitter a device receiving a message is the receiver The device that controls the message is the master and the devices which are controlled by the master are the slaves The system configuration is shown in Figure 16 All information
8. the devices have to be stored at a temperature of 8 C to 45 C and a humidity of 25 to 75 For long term storage products deviant conditions are described in that document PCF8534A All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 31 of 52 NXP Semiconductors PCF8534A 11 Static characteristics Universal LCD driver for low multiplex rates Table 19 Static characteristics Vpop 1 8 V to 5 5 V Vss 0 V Vicp 2 5 V to 6 5 V Tamp 40 C to 85 C unless otherwise specified Symbol Parameter Supplies Vpp supply voltage Vicp LCD supply voltage lbp supply current Ipp itcp LCD supply current Logic Vi input voltage Vil LOW level input voltage Vin HIGH level input voltage Vpor power on reset voltage lot LOW level output current lou HIGH level output current IL leakage current Ci input capacitance I2C bus pins SDA and SCLI5 VI input voltage ViL LOW level input voltage Vin HIGH level input voltage lot LOW level output current IL leakage current Ci input capacitance PCF8534A Conditions foak 1536 Hz folk 1536 Hz on pins CLK SYNC OSC AO to A2 and SAO on pins CLK SYNC OSC AO to A2 and SAO Vor 0 4 V Voo 5 V on pins CLK and SYNC Vou 4 6 V Vpp 5 V on pin CLK V Voo or Vss on pins SAO AO to A2 and CLK V Vpp on pin
9. 73 to 76 output LCD backplane output 0 to 3 n c 34 to 37 not connected do not connect and do not use as feed through SDA 38 1 input output 1 C bus serial data input and output SCL 39 input 12C bus serial clock input CLK 40 input output external clock input and internal clock output Vpop 41 supply supply voltage SYNC 42 input output cascade synchronization input and output active LOW OSC 43 6 input enable input for internal oscillator AO to A2 44 to 46 7to9 input subaddress counter input 0 to 2 SAO 47 10 input 2C bus slave address input 0 Vss 48 110 supply ground Vicp 49 12 supply input of LCD supply voltage S0 to S30 50 to 80 13 to 43 output LCD segment output 0 to 30 1 All information provided in this document is subject to legal disclaimers The substrate rear side of the die is connected to Vss and should be electrically isolated NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 6 of 52 NXP Semiconductors PC F8534A Universal LCD driver for low multiplex rates 7 Functional description The PCF8534A is a versatile peripheral device designed to interface between any microcontroller to a wide variety of LCD segment or dot matrix displays see Figure 4 It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 60 segments The display configurations possible with the PCF8534A depend on the required number of active
10. Lep ONpolg LLOZ Aint sz 9 aey SJOIE OSIP Jeba 0 JOaIqNs S JUBWUNDOP SI UI PEpIAOI UONEUWOJU y cS 0 6L VWreS84Od pamasa syu Ily LLOZ Aa dXN LCD segments LCD backplanes display RAM filling order transmitted display byte rows static display RAM o rows backplane 4 outputs BP 1 rows SED display RAM multiplex rows backplane 1 outputs BP 2 1 3 rows display RAM o multiplex rows backplane p outputs BP S 2 1 4 N a rows display RAM multiplex rows backplane 1 outputs BP x data bit unchanged Fig 13 Relationship between LCD layout drive mode display RAM filling order and display data transmitted over the I2C bus columns display RAM address segment outputs s byte columns display RAM address segment outputs s byte1 columns display RAM address segment outputs s byte1 columns display RAM address segment outputs s byte1 byte2 byte3 byte4 byte5 MSB LSB poerEEGE MSB LSB BERBER cd MSB LSB DEROBEEe MSB LSB fa e eer al ele 001 aaj646 9 e41 X9 dIjNW MO 104 ABALIP A97 JesueAiuy Vvessad0d SJOJONPUODIWIIS dXN NXP Semiconductors PC F8534A 7 10 1 7 10 2 PCF8534A Universal LCD driver for low multiplex rates When display data is transmitted to the PCF8534A the display bytes received are stored in the display RAM in accordance with the selected LCD multiplex drive mode The data is stored as it arrives
11. Symbol Pad Coordinates Description X um um 28 41 1384 4 621 6 LCD segment output 29 42 1384 4 701 6 30 43 1384 4 781 6 31 44 896 5 1239 4 32 45 816 5 1239 4 33 46 736 5 1239 4 34 47 576 5 1239 4 35 48 496 5 1239 4 S36 49 416 5 1239 4 S37 50 336 5 1239 4 38 51 256 5 1239 4 39 52 176 5 1239 4 S40 53 96 5 1239 4 S41 54 16 5 1239 4 S42 55 63 5 1239 4 43 56 143 5 1239 4 S44 57 223 5 1239 4 S45 58 303 5 1239 4 S46 59 463 5 1239 4 S47 60 543 5 1239 4 S48 61 623 5 1239 4 S49 62 703 5 1239 4 S50 63 783 5 1239 4 S51 64 1384 4 935 S52 65 1384 4 855 S53 66 1384 4 775 54 67 1384 4 695 55 68 1384 4 615 S56 69 1384 4 535 S57 70 1384 4 375 58 71 1384 4 295 59 72 1384 4 215 BPO 73 1384 4 125 LCD backplane output BP1 74 1384 4 45 BP2 75 1384 4 35 BP3 76 1384 4 115 1 All coordinates are referenced in um to the center of the die see Figure 26 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 43 of 52 NXP Semiconductors PC F8534A Universal LCD driver for low multiplex rates REF REF C1 c2 REF F 001aai649 Fig 27 Alignment marks Table 24 Alignment mark locations Symbol X um Y um C1 1387 1190 C2 1335 1242 F 1345 1173 1 All coordinates are referenced in um to the ce
12. and depending on the current multiplex drive mode data is stored singularly in pairs triples or quadruples To illustrate the filling order an example of a 7 segment display showing all drive modes is given in Figure 13 The RAM filling organization depicted applies equally to other LCD types The following applies to Figure 13 e In static drive mode the eight transmitted data bits are placed into row 0 as one byte e In 1 2 multiplex drive mode the eight transmitted data bits are placed in pairs into row 0 and row 1 as two successive 4 bit RAM words e In 1 3 multiplex drive mode the eight bits are placed in triples into row 0 row 1 and row 2 as three successive 3 bit RAM words with bit 3 of the third address left unchanged It is not recommended to use this bit in a display because of the difficult addressing This last bit may if necessary be controlled by an additional transfer to this address But care should be taken to avoid overwriting adjacent data because always full bytes are transmitted see Section 7 10 3 e In 1 4 multiplex drive mode the eight transmitted data bits are placed in quadruples into row 0 row 1 row 2 and row 3 as two successive 4 bit RAM words Data pointer The addressing mechanism for the display RAM is realized using the data pointer This allows the loading of an individual display data byte or a series of display data bytes into any location of the display RAM The sequence commences with the i
13. authorization from national authorities Bare die All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions If there are data sheet limits not guaranteed these will be separately indicated in the data sheet There are no post packing tests performed on individual die or wafers NXP Semiconductors has no control of third party procedures in the sawing handling packing or assembly of the die Accordingly NXP Semiconductors assumes no liability for device functionality or performance of the die or 23 Contact information Universal LCD driver for low multiplex rates systems after third party sawing handling packing or assembly of the die It is the responsibility of the customer to test and qualify their application in which the die is used All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department 22 4 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners 2C bus logo is a trademark of NXP B V For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com PCF8534A All information provided in t
14. data sheet Qualification Product short data sheet Production This document contains data from the objective specification for product development This document contains data from the preliminary specification This document contains the product specification 1 Please consult the most recently issued document before initiating or completing a design 2 The term short data sheet is explained in section Definitions 3 The product status of device s described in this document may have changed since this document was published and may differ in case of multiple devices The latest product status information is available on the Internet at URL http www nxp com 22 2 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information Short data sheet A short data sheet is an extract from a full data sheet with the same product type number s and title A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information For detailed and full information see the relevant full data sheet which is available on request via the local NXP
15. for very high drive requirements Display RAM The display RAM is a static 60 x 4 bit RAM which stores LCD data A logic 1 in the RAM bit map indicates the on state Von rms Of the corresponding LCD element Similarly a logic O indicates the off state Vof Rms For more information on Vorn Rms and Vor RMs see Section 7 3 There is a one to one correspondence between e the bits in the RAM bitmap and the LCD elements e the RAM columns and the segment outputs e the RAM rows and the backplane outputs The display RAM bit map Figure 12 shows row 0 to row 3 which correspond with the backplane outputs BPO to BP3 and column 0 to column 59 which correspond with the segment outputs SO to S59 In multiplexed LCD applications the data of each row of the display RAM is time multiplexed with the corresponding backplane row 0 with BPO row 1 with BP1 and so on columns display RAM addresses segment outputs S 0 1 2 3 4 55 56 57 58 59 rows 0 display RAM rows backplane outputs BP 013aaa212 The display RAM bit map shows the direct relationship between the display RAM addresses and the segment outputs and between the bits in a RAM word and the backplane outputs Fig 12 Display RAM bit map All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 18 of 52 Jays
16. in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 40 of 52 NXP Semiconductors PCF8534A 15 Bare die outline Universal LCD driver for low multiplex rates Wire bond die 76 bonding pads 2 91 x 2 62 x 0 38 mm PCF8534AU ry gt m e E 63 44 DC l 000 CO OOCOOCCCOOCCO O00 s4 C e PC8534A 1 3 a j 5 o o L o 0 L 7 T o 11O C1 C1 EJ i c CL L 24 3 ee U UUUO0U OOO UUUUOOOOOUD 4 23 X 0 0 5 1 mm E scale P4 P3 DIMENSIONS mm are the original dimensions o UNIT A D E e Py Ppl P30 P max e F mm nom 0 38 2 91 2 62 0 06 0 05 0 10 0 09 a P4 gt min 0 08 Notes detail X 1 Pad size 2 Passivation opening 3 Marking code OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC JEITA PROJECTION ISSUE DATE PCF8534AU E 08 08 06 Fig 26 PCF8534AU die outline PCF8534A All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 41 of 52 NXP Semiconductors PCF8534A PCF8534A Universal LCD driver for low multiplex rates Table 23 Bonding pad locations Symbo
17. multiplex rates 7 4 4 1 4 Multiplex drive mode When four backplanes are provided in the LCD the 1 4 multiplex drive mode applies as PCF8534A shown in Figure 11 BPO BP1 BP2 BP3 Sn Sn 1 Sn 2 Sn 3 state 1 state 2 Fig 11 VLCD 2VLcp 3 Vicp 3 Vss VLCD 2VLcp 3 Vicp 3 Vss Vicb 2Vicp 3 Vicp 3 Vss VLCD 2VLcp 3 Vicp 3 Vss Vicb 2Vicp 3 Vicp 3 Vss Vicb 2Vicp 3 Vicp 3 Vss VLCD 2VLcp 3 Vicp 3 Vss VLCD 2VLcp 3 Vicp 3 Vss VLCD Nte Vicp 3 0 V Vicp 3_ 2Vicp 3_ VLCD Vicb 2Vicp 3 Vicp 3 0 V _ VLcep 3 2VLcp 3 VLcD eJ UL UL JUUUUL LCD segments a Waveforms at driver AE E b Resultant waveforms at LCD segment Oigaaeett Vstatet t Vsn t Vepo t Von ams 0 577Vicp Vstatea t Vsn t Vapi t Vott RMS 0 333Vicp Waveforms for the 1 4 multiplex drive mode with 1 bias All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 16 of 52 NXP Semiconductors PC F8534A 7 5 7 5 1 7 5 2 7 6 7 7 7 8 PCF8534A Universal LCD driver for low multiplex rates Oscillator The internal logic and the LCD drive signals of the PCF8534
18. provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 26 of 52 NXP Semiconductors PC F8534A PCF8534A 8 4 Universal LCD driver for low multiplex rates MASTER SLAVE MASTER MASTER TRANSMITTER oes TRANSMITTER ee alee TRANSMITTER RECEIVER RECEIVER RECEIVER SDA SCL mga807 Fig 16 System configuration Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited Each byte of 8 bits is followed by an acknowledge cycle e A slave receiver which is addressed must generate an acknowledge after the reception of each byte e A master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter e The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse set up and hold times must be considered e A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition Acknowledgement on the 1 C bus is illustrated in Figure 17 data output Bi X 7 by t
19. 0 3 us Cb capacitive load for each bus line 400 pF tw spike spike pulse width 50 ns 1 Typical output duty cycle 5 50 2 All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to Vi and V p with an input voltage swing of Vss to Vpp PCF8534A All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 34 of 52 NXP Semiconductors PC F8534A Universal LCD driver for low multiplex rates 0 7Vpp cae 0 3Vpp SYNC 0 7Vpp 0 3Vpp tpD SYNC_N gt m o e tpD SYNC_N SYNC_NL gt f 0 5 V BPO to BP3 2 and S0 to S59 Wop 5V 0 5V a tPD drv 001aah618 Fig 21 Driver timing waveforms SDA SCL tHD sTA e tHD DAT gt tHiGH tsu DAT SDA tsu sTA tsu sTo mga728 Fig 22 1 C bus timing waveforms PCF8534A All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 35 of 52 NXP Semiconductors PC F8534A Universal LCD driver for low multiplex rates 13 Application information 13 1 Cascaded operation Large display configurations of up to 16 PCF8534As can be recognized on the same I2C bus by using the 3 bit hardware subaddress AO A1 a
20. A are timed by the frequency fak It equals either the built in oscillator frequency fosc or the external clock frequency fok ext The clock frequency fek determines the LCD frame frequency ftr Internal clock The internal oscillator is enabled by connecting pin OSC to pin Vss In this case the output from pin CLK is the clock signal for any cascaded PCF8534A in the system External clock Pin CLK is enabled as an external clock input by connecting pin OSC to Vpp Remark A clock signal must always be supplied to the device Removing the clock may freeze the LCD in a DC state which is not suitable for the liquid crystal Timing The PCF8534A timing controls the internal data flow of the device This includes the transfer of display data from the display RAM to the display segment outputs In cascaded applications the correct timing relationship between each PCF8534A in the system is maintained by the synchronization signal at pin SYNC The timing also generates the LCD frame signal whose frequency is derived from the clock frequency The frame signal frequency is a fixed division of the clock frequency from either the internal or an external clock Table 6 LCD frame frequencies Operating mode ratio Frame frequency with respect to fc typical Unit folk 1536 Hz feik fa or 64 Hz Display register The display register holds the display data while the corresponding multiplex signals are generated Segm
21. CD supply voltage Vicp is on while the IC supply voltage Vpp is off or vice versa This may cause unwanted display artifacts To avoid such artifacts Vicp and Vpp must be applied or removed together Table 18 Limiting values In accordance with the Absolute Maximum Rating System IEC 60134 Symbol Vpop IDD VLeD DD LCD lss Vi Tsig Tamb Parameter supply voltage supply current LCD supply voltage LCD supply current ground supply current input voltage input current output voltage output current total power dissipation power dissipation per output HBM CDM electrostatic discharge voltage latch up current storage temperature ambient temperature Conditions iN 3 4 5 6 operating device Min 0 5 50 0 5 50 50 0 5 10 0 5 0 5 10 Max 6 5 50 7 5 50 50 6 5 10 6 5 7 5 10 400 100 3000 1000 200 150 85 Unit mA mA mA mA mA mW mW lt lt mA C C 1 Pins SDA SCL CLK SYNC SAO OSC and AO to A2 2 Pins SO to S59 and BPO to BP3 3 Pass level Human Body Model HBM according to Ref 5 JESD22 A114 4 Pass level Charged Device Model CDM according to Ref 6 JESD22 C101 5 Pass level latch up testing according to Ref 7 JESD78 at maximum ambient temperature Tamb max 6 According to the NXP store and transport requirements see Ref 9 NX3 00092
22. Cascaded PCF8534A configuration The SYNC line is provided to maintain the correct synchronization between all cascaded PCF8534A Synchronization is guaranteed after a power on reset The only time that SYNC is likely to be needed is if synchronization is accidentally lost for example by noise in adverse electrical environments or by defining a multiplex drive mode when PCF8534A with different SAO levels are cascaded SYNC is organized as an input output pin The output selection is realized as an open drain driver with an internal pull up resistor A PCF8534A asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times If synchronization in the cascade is lost it is restored by the first PCF8534A to assert SYNC The timing relationship between the backplane waveforms and the SYNC signal for the various drive modes of the PCF8534A are shown in Figure 24 The contact resistance between the SYNC on each cascaded device must be controlled If the resistance is too high the device is not able to synchronize properly this is applicable to chip on glass applications The maximum SYNC contact resistance allowed for the number of devices in cascade is given in Table 22 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 37 of 52 NXP Semiconductors PC F8534A Unive
23. OSC pin SCL pin SDA VoL 0 4 V Voo 5 V on pin SDA Vi Vpp or Vss Min 1 8 2 5 Vss 0 5 Vss 0 7Vpo All information provided in this document is subject to legal disclaimers Typ Max Unit 5 5 V 6 5 V 20 uA 60 uA Vpp 0 5 V 0 3Vpp V Vpp V 1 6 V mA mA 1 uA 1 uA 7 pF 5 5 V 0 3Vpp V 0 2Vpp V 5 5 V mA 1 uA 7 pF NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 32 of 52 NXP Semiconductors PC F8534A Universal LCD driver for low multiplex rates Table 19 Static characteristics continued Vpop 1 8 V to 5 5 V Vss 0 V Vicp 2 5 V to 6 5 V Tamp 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit LCD outputs Output pins BPO BP1 BP2 and BP3 Vep voltage on pin BP Cbpi 35 nF 4 100 100 mV Rep resistance on pin BP Vicp 5 V 5 1 5 10 kQ Output pins SO to S59 Vs voltage on pin S Csgm 35 nF 6 100 100 mV Rs resistance on pin S Vicp 5V BI 6 0 13 5 kQ 1 LCD outputs are open circuit inputs at Vss or Vpp external clock with 50 duty factor 1 C bus inactive 2 Not tested design specification only 3 The 1 C bus interface of PCF8534A is 5 V tolerant 4 Cpyp backplane capacitance 5 Outputs measured individually and sequentially 6 Csgm Segment capacitance PCF8534A All information provided in this document is subject to legal disclaim
24. Semiconductors sales office In case of any inconsistency or conflict with the short data sheet the full data sheet shall prevail Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer unless NXP Semiconductors and customer have explicitly agreed otherwise in writing In no event however shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet 22 3 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumu
25. an alternative bank and to be able to switch to it once it is assembled Input bank selector The input bank selector loads display data into the display data in accordance with the selected LCD drive configuration Display data can be loaded in row 2 in static drive mode or in rows 2 and 3 in 1 2 multiplex drive mode by using the bank select command see Table 14 The input bank selector functions independently to the output bank selector Blinking The display blinking capabilities of the PCF8534A are very versatile The whole display can blink at frequencies selected by the blink select command see Table 15 The blink frequencies are derived from the clock frequency The ratio between the clock and blink frequency depends on the blink mode selected see Table 9 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 22 of 52 NXP Semiconductors PC F8534A Universal LCD driver for low multiplex rates Table 9 Blink frequencies Blink mode Operating mode ratio Blink frequency with respect to feik typical Unit feik 1536 Hz off blinking off Hz l olink fet 2 Hz 2 Sotink et 1 Hz 3 fine deu 0 5 Hz An additional feature is for an arbitrary selection of LCD segments to blink This applies to the static and 1 2 multiplex drive modes and can be implemented without any communication overheads W
26. ay RAM at the address specified by the data pointer and the subaddress counter Both data pointer and subaddress counter are automatically updated PCF8534A All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 29 of 52 NXP Semiconductors PC F8534A Universal LCD driver for low multiplex rates The acknowledgement after each byte is made only by the AO A1 and A2 addressed PCF8534 lt A After the last display byte the 1 C bus master issues a STOP condition P Alternatively a START may be issued to RESTART I2C bus access 9 Internal circuitry VDD VDD SAO __ Vss Vss VDD CLK N SCL Vss VDD A Vss OSC Vss VDD SDA SYNC Vss Vss VDD AO A1 A2 7X Vicb Vss i VLeD BPO BP1 Vss BP2 BP3 if Vss Vicb S0 to S59 Vss 001aah615 Fig 20 Device protection diagram PCF8534A All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 30 of 52 NXP Semiconductors PCF8534A 10 Limiting values Universal LCD driver for low multiplex rates CAUTION Static voltages across the liquid crystal display can build up when the L
27. b4 b1 c7 c4 c1 d7 1 a6 a3 a0 b6 b3 bO c6 c3 co d6 2 a5 a2 b5 b2 c5 c2 d5 3 5 3 2 4 If the bit at position BP2 S2 would be written by a second byte transmitted then the mapping of the segment bits would change as illustrated in Table 8 Table 8 Entire RAM filling by rewriting in 1 3 multiplex drive mode Assumption BP2 S2 BP2 S5 BP2 S8 etc are connected to elements on the display Display RAM Display RAM addresses columns segment outputs Sn bits rows o hn 2 4 5 e 7 a 9 I backplane outputs BPn 0 a7 a4 a1 b7 b4 b1 c7 c4 c1 d7 d4 di e7 e4 1 a6 a3 a0 b6 b3 b0 c6 c3 c0 d6 d3 d0 e6 e3 2 a5 a2 b5 b2 c5 c2 d5 d2 e5 e2 3 n S eS S In the case described in Table 8 the RAM has to be written entirely and BP2 S2 BP2 S5 BP2 S8 and so on have to be connected to elements on the display This can be achieved by a combination of writing and rewriting the RAM like follows All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 21 of 52 NXP Semiconductors PC F8534A 7 10 4 7 10 4 1 7 10 4 2 7 11 PCF8534A Universal LCD driver for low multiplex rates e Inthe first write to the RAM bits a7 to a0 are written e Inthe second write bits b7 to bO are written overwriting bits a1 and a0 with bits b7 and b6 e Inthe third write
28. backplane outputs A selection of display configurations is given in Table 4 All of the display configurations given in Table 4 can be implemented in a typical system as shown in Figure 5 ooo 0000000000 000000000000000000000 000000000000000000000000000000000000000 000000 o 0000000000000000 000000000 00o ee e 000000000000000000000 dot matrix _ NII INI ca ll 7 segment with dot 14 segment with dot and accent 013aaa312 Fig 4 Example of displays suitable for PCF8534A Table 4 Selection of possible display configurations Number of Backplanes Icons Digits Characters Dot matrix 7 segment 14 segmenti2 Elements 4 240 30 15 240 4 x 60 3 180 22 11 180 3 x 60 2 120 15 7 120 2 x 60 1 60 7 3 60 1 x 60 1 7 segment display has eight elements including the decimal point 2 14 segment display has 16 elements including decimal point and accent dot PCF8534A All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 7 of 52 NXP Semiconductors PC F8534A 7 1 7 2 PCF8534A Universal LCD driver for low multiplex rates 60 segment drives PCO LCDPANEL PCF8534A PROCESSOR MICRO osc 4 backplanes CONTROLLER up to 240 elements A2 SA0 Vss Vss 001aah616 Fig 5 Typical system configuration The ho
29. bias configuration ol 1 bias 1 1 2 bias 1toO M 1 0 LCD drive mode selection 01 static one backplane 10 1 2 multiplex two backplanes 11 1 3 multiplex three backplanes ool 1 4 multiplex four backplanes 1 Default value 2 The possibility to disable the display allows implementation of blinking under external control 3 Not applicable for static drive mode Table 12 Load data pointer command bit description See Section 7 10 1 on page 20 Bit Symbol Value Description 7 0 fixed value 6to0 P 6 0 0000000 to 7 bit binary value 0 to 59 transferred to the 0111011 data pointer to define one of 60 display RAM addresses 1 Default value Table 13 Device select command bit description See Section 7 10 2 on page 20 Bit Symbol Value Description 7t03 11100 fixed value 2to0 Al2 0 O00 to 111 3 bit binary value 0 to 7 transferred to the subaddress counter to define one of eight hardware subaddresses 1 Default value PCF8534A All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 24 of 52 NXP Semiconductors PC F8534A Universal LCD driver for low multiplex rates Table 14 Bank select command bit description See Section 7 10 4 on page 22 Bit Symbol Value Description Static 1 2 multiplex 7to2 111110 fixed value 1 l input bank selection storage of arriv
30. bits c7 to c0 are written overwriting bits b1 and bO with bits c7 and c Depending on the method of writing to the RAM standard or entire filling by rewriting some elements remain unused or can be used But it has to be considered in the module layout process as well as in the driver software design Bank selector Output bank selector The output bank selector see Table 14 selects one of the four rows per display RAM address for transfer to the display register The actual row selected depends on the particular LCD drive mode in operation and on the instant in the multiplex sequence e In 1 4 multiplex mode all RAM addresses of row 0 are selected these are followed by the contents of row 1 2 and then 3 e In 1 3 multiplex mode rows 0 1 and 2 are selected sequentially e In 1 2 multiplex mode rows 0 and 1 are selected e In static mode row 0 is selected The SYNC signal resets these sequences to the following starting points e row 3 for 1 4 multiplex e row 2 for 1 3 multiplex e row 1 for 1 2 multiplex e row 0 for static mode The PCF8534 lt A includes a RAM bank switching feature in the static and 1 2 multiplex drive modes In the static drive mode the bank select command may request the contents of row 2 to be selected for display instead of the contents of row 0 In the 1 2 multiplex mode the contents of rows 2 and 3 may be selected instead of rows 0 and 1 This gives the provision for preparing display information in
31. controller 000 25 8 Characteristics of the I C bus 26 8 1 Bit ansSien s iccis Goda dees tirsir titra 26 8 2 START and STOP conditions 26 8 3 System configuration 26 8 4 Acknowledge e eee eee eee 27 8 5 I2C bus controller 0 2 0 0 2c ee eee 28 8 6 a 910 60 1c eee ea 28 8 7 I2C bus protocol 0000 c eee eee 28 9 Internal Circuitry 2 2 2 c eee eee 30 10 Limiting values 000 e eee eee 31 11 Static characteristics 32 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP B V 2011 All rights reserved For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 25 July 2011 Document identifier PCF8534A
32. d proper operation of the device at these or any other conditions above those given in the Recommended operating conditions section if present or the Characteristics sections of this document is not warranted Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale as published at http www nxp com profile terms unless otherwise agreed in a valid written individual agreement In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant conveyance or implication of any license under any copyrights patents or other industrial or intellectual property rights NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 50 of 52 NXP Semiconductors PCF8534A Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior
33. disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 4 of 52 NXP Semiconductors PCF8534A PCF8534A Universal LCD driver for low multiplex rates Fig 3 DOMRDArRODA HO TNANATOWDANO WM t wo yur vy vyvvyr vy a E OY DANNNN NNNDNNNDNNNNNN YN 33 32 31 S51 52 53 PCF8534A 1 a 355 aT ss 39 s26 S57 38 s25 S58 37 s24 S59 BPO 36 s23 BP1 35 s22 BP2 34 s21 BP3 33 s20 32 s19 SDA 31 s18 30 s17 29 s16 28 s15 27 S14 L 26 s13 7 25 s12 CLK 24 s11 ale go 222 2 2 PDN AA T gt 8 5 gt g D n Top view 001aai648 Viewed from active side For mechanical details see Figure 26 Pin configuration for the wire bond die PCF8534AU All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 5 of 52 NXP Semiconductors PCF8534A PCF8534A Universal LCD driver for low multiplex rates 6 2 Pin description Table 3 Pin description Symbol Pin Type Description SOT315 1 Wire bond die S31 to S59 1 to 29 44 to 72 output LCD segment output 31 to 59 BPO to BP3 30 to 33
34. e specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Limiting values Stress above one or more limiting values as defined in the Absolute Maximum Ratings System of IEC 60134 will cause permanent damage to the device Limiting values are stress ratings only an
35. e follower buffers Selectable display bias configurations static 1 2 or 13 Wide logic power supply range from 1 8 V to 5 5 V LCD and logic supplies may be separated Low power consumption 400 kHz I2C bus interface No external components required Display memory bank switching in static and duplex drive modes Versatile blinking modes Silicon gate CMOS process 1 The definition of the abbreviations and acronyms used in this data sheet can be found in Section 19 NXP Semiconductors PC F8534A Universal LCD driver for low multiplex rates 3 Ordering information 4 Marking Table 1 Ordering information Type number Package Name Description Delivery form Version PCF8534AHL 1U LQFP80 plastic low profile quad flat tape and reel SOT315 1 package 80 leads body 12 x 12 x 1 4mm PCF8534AU DA 1_ wire bond die 76 bonding pads chip in tray PCF8534AU 2 91 x 2 62 x 0 38 mm 1 Not to be used for new designs Replacement part is PCF85134HL 1 Table 2 Marking codes Type number Marking code PCF8534AHL 1 PCF8534AHL PCF8534AU DA 1 PC8534A 1 PCF8534A All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 2 of 52 NXP Semiconductors PC F8534A Universal LCD driver for low multiplex rates 5 Block diagram BPO BP1 BP2 BP3 S0 to S59 BACKPLANE OUTPUTS VLCD
36. ee 48 7 4 LCD drive mode waveforms 12 90 References ccceeeeeeeeueeees 49 7 4 1 Static drive mode 000000 ee 12 21 Revision history 49 7 4 2 1 2 Multiplex drive mode 13 ee are 8 ew ee Ene 7 4 3 1 3 Multiplex drive mode 15 22 Legal information 4 50 7 4 4 1 4 Multiplex drive mode 16 22 1 Data sheet status 50 75 Oscillator 2 cc ccccccccccccecceeee 17 22 2 De fiNITONS 2 220 eked a rasto ee a 50 7 5 1 Internal clock se accuse nananana 17 22 3 Disclaimers 6 e eee eee 50 7 5 2 External COCK pc atiue sek ates ences 17 22 4 Trademarks 6 66 eee eee eee 51 7 6 TIMIN sa a ole Oa A 17 23 Contact information 05 51 7 7 Display register eee eee e eee 17 24 Contents 0000 cece cece eee eeee 52 7 8 Segment outputs 0 00 eee 17 7 9 Backplane outputs 006 18 7 10 Display RAM 000 e eee ee eee 18 7 10 1 Data pointer 0 eee eee eee 20 7 10 2 Subaddress counter 2000 5 20 7 10 3 RAM writing in 1 3 multiplex drive mode 21 7 10 4 Bank selector 00 e eee eee eee 22 7 10 4 1 Output bank selector 22 7 10 4 2 Input bank selector 4 22 7 11 BIINKING 22icaedia went eedeiw ead wee ke de 22 7 12 Command decoder 0 0 00 23 7 13 Display
37. ee is designed such that on all PCF8534A the clock propagation delay from the clock source to all PCF8534A in the cascade is as equal as possible since otherwise synchronization artifacts may occur In mixed cascading configurations care has to be taken that the specifications of the individual cascaded devices are met at all times All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 39 of 52 NXP Semiconductors PCF8534A 14 Package outline Universal LCD driver for low multiplex rates LQFP980 plastic low profile quad flat package 80 leads body 12 x 12 x 1 4mm SOT315 1 DIMENSIONS mm are the original dimensions detail X A UNIT max Ay A2 A3 bp c 1 6 Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE SOT315 1 136E15 MS 026 SSK 00 9449 03 02 25 Fig 25 Package outline SOT315 1 LQFP80 PCF8534A All information provided
38. ent outputs The LCD drive section includes 60 segment outputs SO to S59 which should be connected directly to the LCD The segment output signals are generated based on the multiplexed backplane signals and with data resident in the display register When less than 60 segment outputs are required the unused segment outputs must be left open circuit All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 17 of 52 NXP Semiconductors PC F8534A 7 9 7 10 PCF8534A Universal LCD driver for low multiplex rates Backplane outputs The LCD drive section includes four backplane outputs BPO to BP3 which must be connected directly to the LCD The backplane output signals are generated in accordance with the selected LCD drive mode e In 1 4 multiplex drive mode BPO to BP3 must be connected directly to the LCD If less than four backplane outputs are required the unused outputs can be left open circuit e In 1 3 multiplex drive mode BP3 carries the same signal as BP1 therefore these two adjacent outputs can be tied together to give enhanced drive capabilities e In 1 2 multiplex drive mode BPO and BP2 respectively BP1 and BP3 carry the same signals and can also be paired to increase the drive capabilities e In static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel
39. ers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 33 of 52 NXP Semiconductors PC F8534A Universal LCD driver for low multiplex rates 12 Dynamic characteristics Table 20 Dynamic characteristics Vpop 1 8 V to 5 5 V Vss 0 V Vicp 2 5 V to 6 5 V Tamp 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Clock Internal output pin CLK fosc oscillator frequency Vpp 5 V 01 960 1536 3046 Hz External input pin CLK fcik ext external clock frequency Vpp 5 V 797 1536 3046 Hz telk H HIGH level clock time 130 us telk L LOW level clock time 130 us Synchronization input pin SYNC tpoisync_n SYNC propagation delay 30 ns tsYNC_NL SYNC LOW time 1 us Outputs pins BPO to BP3 and SO to S59 tPD drv driver propagation delay Vicp 5V 30 us 1 C bus timing Pin SCL fscL SCL frequency 400 kHz tLow LOW period of the SCL clock 1 3 us THIGH HIGH period of the SCL clock 0 6 us Pin SDA tsu DAT data set up time 100 ns tHD DAT data hold time 0 ns Pins SCL and SDA tBUF bus free time between a STOP and 1 3 us START condition tsu sTO set up time for STOP condition 0 6 us tHD STA hold time repeated START condition 0 6 us tsu sTA set up time for a repeated START 0 6 us condition tr rise time of both SDA and SCL signals 0 3 us ti fall time of both SDA and SCL signals
40. g Human Body Model HBM 6 JESD22 C101 Field Induced Charged Device Model Test Method for Electrostatic Discharge Withstand Thresholds of Microelectronic Components 7 JESD78 IC Latch Up Test 8 JESD625 A Requirements for Handling Electrostatic Discharge Sensitive ESDS Devices 9 NX3 00092 NXP store and transport requirements 10 SNV FA 01 02 Marking Formats Integrated Circuits 11 UM10204 2C bus specification and user manual 21 Revision history Table 29 Revision history Document ID Release date Data sheet status Change notice Supersedes PCF8534A v 6 20110725 Product data sheet PCF8534A_5 Modifications e Added design in and replacement part information e Changed description of Table 17 e Added Section 7 10 3 PCF8534A_5 20090806 Product data sheet PCF8534A_4 PCF8534A_4 20090716 Product data sheet PCF8534A_3 PCF8534A_3 20081110 Product data sheet PCF8534A_2 PCF8534A_2 20080604 Product data sheet PCF8534A_1 PCF8534A_1 20080423 Product data sheet PCF8534A All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 49 of 52 NXP Semiconductors PCF8534A 22 Legal information Universal LCD driver for low multiplex rates 22 1 Data sheet status Document status J 2 Product status 3 Definition Objective short data sheet Development Preliminary short
41. his document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 51 of 52 NXP Semiconductors PC F8534A Universal LCD driver for low multiplex rates 24 Contents 1 General description 0 00e00s 1 12 Dynamic characteristics 005 34 2 Features and benefits 00000eees 1 13 Application information 05 36 3 Ordering information 2 13 1 Cascaded operation 0 36 4 Marking esince niet chatted caked Yaa 2 14 Package outline 002 cece eee 40 5 Block diagram 000 cece eee eee 3 15 Bare die outline 0 cee eee eee 41 6 Pinning information 4 16 Handling information 05 44 6 1 PINNING es eiae ieinu EN Se ede ears dea ey 4 17 Packing information 00eeeeee 45 6 2 Pin description BUSe fe EI e et leven coer oe eure 6 18 Soldering of SMD packages Sg E N ieee 46 7 Functional description 0 0065 7 18 1 Introduction to soldering 46 7 1 Power On Reset POR 2 05 8 18 2 Wave and reflow soldering 46 7 2 LCD bias generator 0 0000 8 18 3 Wave soldering 20ee eee 47 7 3 LCD voltage selector 20005 9 18 4 Reflow soldering 20 00 47 7 3 1 Electro optical performance 10 19 Abbreviations 00000ceeee
42. in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 11 of 52 NXP Semiconductors PC F8534A Universal LCD driver for low multiplex rates 7 4 LCD drive mode waveforms 7 4 1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD Backplane and segment drive waveforms for this mode are shown in Figure 7 E Thr Vico LCD segments BPO Vss VicbD Sn Vss VicbD Sn 1 Vss a Waveforms at driver Vicp state 1 OV Vicp Vicp state 2 0ov Vicp b Resultant waveforms at LCD segment 013aaa207 Vstatet t Vsn t Vepo t Von ams Vicp Vstatea t Visn 1 t Vepo t Votf RMs 0 V Fig 7 Static drive mode waveforms PCF8534A All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 12 of 52 NXP Semiconductors PC F8534A Universal LCD driver for low multiplex rates 7 4 2 1 2 Multiplex drive mode When two backplanes are provided in the LCD the 1 2 multiplex mode applies The PCF8534A allows the use of 1 bias or 1 3 bias in this mode as shown in Figure 8 and Figure 9 pe Ti Vicp __ LCD segments be eo Vss ___ 4 VicD state 2 BP1 Vicb 2 X Vss
43. ing display data ol RAM row 0 RAM rows 0 and 1 1 RAM row 2 RAM rows 2 and 3 0 O output bank selection retrieval of LCD display data ol RAM row 0 RAM rows 0 and 1 1 RAM row 2 RAM rows 2 and 3 1 The bank select command has no effect in 1 3 or 1 4 multiplex drive modes 2 Default value Table 15 Blink select command bit description Section 7 11 on page 22 Bit Symbol Value Description 7t03 11110 fixed value 2 AB blink mode selection oi normal blinking 1 alternate RAM bank blinking 1toO BF 1 0 blink frequency selection ool off 01 10 11 1 Default value 2 Normal blinking is assumed when the LCD multiplex drive modes 1 3 or 1 4 are selected 3 Alternate RAM bank blinking does not apply in 1 3 and 1 4 multiplex drive modes 4 For the blink frequencies see Table 9 7 13 Display controller The display controller executes the commands identified by the command decoder It contains the status registers of the PCF8534A and coordinates their effects The display controller is also responsible for loading display data into the display RAM in the correct filling order PCF8534A All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 25 of 52 NXP Semiconductors PC F8534A Universal LCD driver for low multiplex rates 8 Characteristics of the I2C bus 8 1 PCF8534A 8 2 8 3 The
44. irection 9 18 Soldering of SMD packages 18 1 18 2 PCF8534A This text provides a very brief insight into a complex technology A more in depth account of soldering ICs can be found in Application Note AN10365 Surface mount reflow soldering description Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards PCBs to form electrical circuits The soldered joint provides both the mechanical and the electrical connection There is no single soldering method that is ideal for all IC packages Wave soldering is often preferred when through hole and Surface Mount Devices SMDs are mixed on one printed wiring board however it is not suitable for fine pitch SMDs Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder The wave soldering process is suitable for the following e Through hole components e Leaded or leadless SMDs which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered Packages with solder balls and some leadless packages which have solder lands underneath the body cannot be wave soldered Also leaded SMDs with leads having a pitch smaller than 0 6 mm cannot be wave soldered due to an increased p
45. ith the output bank selector the displayed RAM banks are exchanged with alternate RAM banks at the blink frequency This mode can also be specified by the blink select command In the 1 3 and 1 4 multiplex modes where no alternate RAM bank is available groups of LCD elements can blink by selectively changing the display RAM data at fixed time intervals The entire display can blink at a frequency other than the nominal blink frequency This can be effectively performed by resetting and setting the display enable bit E at the required rate using the mode set command see Table 11 7 12 Command decoder The command decoder identifies command bytes that arrive on the 12C bus The commands available to the PCF8534A are defined in Table 10 Table 10 Definition of commands Command Operation code Reference aa a 1 jo mode set 1 1 0 0 E B M 1 0 Table 11 load data pointer 0 P 6 0 Table 12 device select 1 1 1 0 0 A 2 0 Table 13 bank select 1 1 1 1 1 0 l O Table 14 blink select 1 1 1 1 0 AB BF 1 0 Table 15 PCF8534A All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 23 of 52 NXP Semiconductors PC F8534A Universal LCD driver for low multiplex rates Table 11 Mode set command bit description Bit Symbol Value Description 7to4 1100 fixed value 3 E display status ol disabled blank 2 1 enable 2 B LCD
46. l Pad Coordinates Description X um Y um SDA 1 1384 4 280 l2C bus serial data input and output SCL 2 1384 4 760 5 1 C bus serial clock input CLK 3 1384 4 945 external clock input and output Vpop 4 978 7 1238 supply voltage SYNC 5 829 3 1238 cascade synchronization input and output OSC 6 714 3 1238 enable input for internal oscillator AO 7 584 3 1238 subaddress counter input A1 8 454 3 1238 A2 9 324 3 1238 SAO 10 194 3 1238 I2C bus slave address input 0 Vss 11 64 3 1238 ground Vicp 12 68 7 1238 input of LCD supply voltage SO 13 173 7 1238 LCD segment output S1 14 253 7 1238 S2 15 333 7 1238 3 16 413 7 1238 S4 17 493 7 1238 S5 18 573 7 1238 S6 19 653 7 1238 S7 20 733 7 1238 S8 21 813 7 1238 S9 22 893 7 1238 S10 23 973 7 1238 S11 24 1384 4 841 12 25 1384 4 761 S13 26 1384 4 681 S14 27 1384 4 601 S15 28 1384 4 521 S16 29 1384 4 441 S17 30 1384 4 361 S18 31 1384 4 281 S19 32 1384 4 201 S20 33 1384 4 121 S21 34 1384 4 41 S22 35 1384 4 39 S23 36 1384 4 119 S24 37 1384 4 301 6 S25 38 1384 4 381 6 S26 39 1384 4 461 6 S27 40 1384 4 541 6 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 42 of 52 NXP Semiconductors PCF8534A PCF8534A Universal LCD driver for low multiplex rates Table 23 Bonding pad locations continued
47. lative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use in automotive applications This NXP Semiconductors product has been qualified for use in automotive applications The product is not designed authorized or warranted to be PCF8534A All information provided in this document is subject to legal disclaimers suitable for use in medical military aircraft space or life support equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for th
48. nd A2 and the programmable I2C bus slave address SAO Table 21 Addressing cascaded PCF8534A Cluster Bit SAO Pin A2 Pin A1 Pin AO Device 1 0 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 2 1 0 0 0 8 0 0 1 9 0 1 0 10 0 1 1 11 1 0 0 12 1 0 1 13 1 1 0 14 1 1 1 15 When cascaded PCF8534 lt A are synchronized they can share the backplane signals from one of the devices in the cascade Such an arrangement is cost effective in large LCD applications since the backplane outputs of only one device need to be through plated to the backplane electrodes of the display The other PCF8534A of the cascade contribute additional segment outputs but their backplane outputs are left open circuit see Figure 23 PCF8534A All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 36 of 52 NXP Semiconductors PC F8534A PCF8534A Universal LCD driver for low multiplex rates 60 segment drives PCF8534A CLK OSC BPO to BP3 open circuit LCD PANEL 60 segment drives HOST 4 SDA MICRO PROCESSOR MICRO CONTROLLER 4 backplanes PCF8534A 1 BPO to BP3 A2 SA0 Vss Vss 013aaa513 1 Is master OSC connected to Vss 2 Is slave OSC connected to Vpp Fig 23
49. nitialization of the data pointer by the load data pointer command see Table 12 Following this command an arriving data byte is stored at the display RAM address indicated by the data pointer The filling order is shown in Figure 13 After each byte is stored the content of the data pointer is automatically incremented by a value dependent on the selected LCD drive mode e In static drive mode by eight e In 1 2 multiplex drive mode by four e In 1 3 multiplex drive mode by three e In 1 4 multiplex drive mode by two If an 2C bus data access terminates early then the state of the data pointer is unknown Consequently the data pointer must be rewritten before further RAM accesses Subaddress counter The storage of display data is determined by the content of the subaddress counter Storage is allowed only when the content of the subaddress counter matches with the hardware subaddress applied to AO A1 and A2 The subaddress counter value is defined by the device select command see Table 13 If the content of the subaddress counter and the hardware subaddress do not match then data storage is inhibited but the data pointer is incremented as if data storage had taken place The subaddress counter is also incremented when the data pointer overflows All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 20 of 52 NXP Semicond
50. nter of the die see Figure 26 16 Handling information All input and output pins are protected against ElectroStatic Discharge ESD under normal handling When handling Metal Oxide Semiconductor MOS devices ensure that all normal precautions are taken as described in JESD625 A IEC 61340 5 or equivalent standards PCF8534A Product data sheet All information provided in this document is subject to legal disclaimers Rev 6 25 July 2011 NXP B V 2011 All rights reserved 44 of 52 NXP Semiconductors PC F8534A Universal LCD driver for low multiplex rates 17 Packing information A t D t F t B t y Y Oo x 001aai625 Fig 28 Tray details for PCF8534AU DA 1 PC8534A 1 001aai650 Fig 29 Tray alignment for PCF8534AU DA 1 PCF8534A All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 45 of 52 NXP Semiconductors PC F8534A Universal LCD driver for low multiplex rates Table 25 Tray dimensions Symbol Description Value A pocket pitch in x direction 5 5mm B pocket pitch in y direction 4 9mm C pocket width in x direction 3 08 mm D pocket width in y direction 2 79 mm E tray width in x direction 50 8 mm F tray width in y direction 50 8 mm N number of pockets x direction 8 M number of pockets y d
51. o address the PCF8534A The entire 1 C bus slave address byte is shown in Table 16 Table 16 1 C slave address byte Slave address Bit 7 6 5 4 3 2 1 0 MSB LSB 0 1 1 1 0 0 SAO RW The PCF8534A is a write only device and does not respond to a read access therefore bit 0 should always be logic 0 Bit 1 of the slave address byte that a PCF8534A will respond to is defined by the level tied to its SAO input Vss for logic 0 and Vpp for logic 1 Having two reserved slave addresses allows the following on the same I C bus e Up to 16 PCF8534A for large LCD applications e The use of two types of LCD multiplex drive The 1 C bus protocol is shown in Figure 18 The sequence is initiated with a START condition S from the I2C bus master which is followed by one of the available PCF8534A slave addresses All PCF8534A with the same SAO level acknowledge in parallel to the slave address All PCF8534A with the alternative SAO level ignore the whole C bus transfer All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 28 of 52 NXP Semiconductors PC F8534A Universal LCD driver for low multiplex rates slave address y control byte RAM command byte oko 9 S 0 1 1 1 0 OJA OJA 0 gt WHE L S P B
52. perating voltage Electro optical performance Suitable values for Von rms and Vottrms are dependent on the LCD liquid used The RMS voltage at which a pixel is switched on or off determines the transmissibility of the pixel For any given liquid there are two threshold values defined One point is at 10 relative transmission at Vih oft and the other at 90 relative transmission at Vth on See Figure 6 For a good contrast performance the following rules should be followed Von RMS 2 Vinton 4 Voff RMS lt Vin off 5 Von RMs and Vof RMs are properties of the display driver and are affected by the selection of a n see Equation 1 to Equation 3 and the Vicp voltage Vihott aNd Vtn on are properties of the LCD liquid and can be provided by the module manufacturer It is important to match the module properties to those of the driver in order to achieve optimum performance All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 10 of 52 NXP Semiconductors PC F8534A Universal LCD driver for low multiplex rates 100 4 90 c 5 n 2 e N Cc S ke o 2 amp v f4 10 4 Vth off Vth on Ves V OFF GREY ON SEGMENT SEGMENT SEGMENT 013aaa494 Fig 6 Electro optical characteristic relative transmission curve of the liquid PCF8534A All information provided
53. ransmitter _ not acknowledge iN ee data output by receiver acknowledge 4 SCL from a co ae co SaN fee master Ls S clock pulse for START acknowledgement condition mbc602 Fig 17 Acknowledgement of the I2C bus All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 27 of 52 NXP Semiconductors PC F8534A 8 5 8 6 8 7 PCF8534A Universal LCD driver for low multiplex rates I2C bus controller The PCF8534A acts as an 2C bus slave receiver It does not initiate 1 C bus transfers or transmit data to an 1 C bus master receiver The only data output from the PCF8534A are the acknowledge signals of the selected devices Device selection depends on the I2C bus slave address on the transferred command data and on the hardware subaddress In single device applications the hardware subaddress inputs AO A1 and A2 are normally tied to Vss which defines the hardware subaddress 0 In multiple device applications AO A1 and A2 are tied to Vss or Vpp using a binary coding scheme so that no two devices with a common I C bus slave address have the same hardware subaddress Input filters To enhance noise immunity in electrically adverse environments RC low pass filters are provided on the SDA and SCL lines I2C bus protocol Two 2C bus slave addresses 0111 000 and 0111 001 are used t
54. ratios are smaller Bias is calculated by ate where the values for a are a 1 for bias a 2 for 3 bias The RMS on state voltage Von rms for the LCD is calculated with Equation 1 a 2a n Von RMS Vico 2 1 Nnx 1 a where the values for n are n 1 for static drive mode n 2 for 1 2 multiplex drive mode n 3 for 1 3 multiplex drive mode n 4 for 1 4 multiplex drive mode The RMS off state voltage VotRms for the LCD is calculated with Equation 2 a 2a n Vofrrms Vico 2 2 nx 1 a Discrimination is the ratio of Von Rms to Vor Rms and is determined from Equation 3 PCF8534A All information provided in this document is subject to legal disclaimers Rev 6 25 July 2011 NXP B V 2011 All rights reserved 9 of 52 Product data sheet NXP Semiconductors PC F8534A 7 3 1 PCF8534A Universal LCD driver for low multiplex rates D Von RMS _ a 2a n 3 Vorms Na 2a n Using Equation 3 the discrimination for an LCD drive mode of 1 3 multiplex with VY bias is 3 1 732 and the discrimination for an LCD drive mode of 1 4 multiplex with V bias is 1 1 528 The advantage of these LCD drive modes is a reduction of the LCD full scale voltage Vicp as follows 1 3 multiplex Y bias Vi cp J6x V enms 2 449V Ams e 1 4 multiplex 1 bias V cp a 2 309 V AMS These compare with Vi cp 3V um Rms When Y bias is used Vicp is sometimes referred as the LCD o
55. robability of bridging The reflow soldering process involves applying solder paste to a board followed by component placement and exposure to a temperature profile Leaded packages packages with solder balls and leadless packages are all reflow solderable Key characteristics in both wave and reflow soldering are e Board specifications including the board finish solder masks and vias e Package footprints including solder thieves and orientation e The moisture sensitivity level of the packages All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 46 of 52 NXP Semiconductors PC F8534A Universal LCD driver for low multiplex rates e Package placement e Inspection and repair e Lead free soldering versus SnPb soldering 18 3 Wave soldering 18 4 PCF8534A Key characteristics in wave soldering are e Process issues such as application of adhesive and flux clinching of leads board transport the solder wave parameters and the time during which components are exposed to the wave Solder bath specifications including temperature and impurities Reflow soldering Key characteristics in reflow soldering are e Lead free versus SnPb soldering note that a lead free reflow process usually leads to higher minimum peak temperatures See Figure 30 than a SnPb process thus reducing the process window e Solder pa
56. rsal LCD driver for low multiplex rates Table 22 SYNC contact resistance Number of devices Maximum contact resistance 2 6000 Q 3to5 2200 Q 6 to 10 1200 Q 11 to 16 700 Q The PCF8534A can always be cascaded with other devices of the same type or conditionally with other devices of the same family This allows optimal drive selection for a given number of pixels to display Figure 22 and Figure 24 show the timing of the synchronization signals SYNC a static drive mode BPO 1 2 bias BPO 1 3 bias SYNG b 1 2 multiplex drive mode LI BPO 1 3 bias SYNC c 1 3 multiplex drive mode BPO 1 3 bias SYNG d 1 4 multiplex drive mode L mgl755 Fig 24 Synchronization of the cascade for various PCF8534A drive modes In a cascaded configuration only one PCF8534A master must be used as clock source All other PCF8534A in the cascade must be configured as slave such that they receive the clock from the master PCF8534A All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 38 of 52 NXP Semiconductors PC F8534A PCF8534A Universal LCD driver for low multiplex rates If an external clock source is used all PCF8534A in the cascade must be configured such as to receive the clock from that external source pin OSC connected to Vpp It must be ensured that the clock tr
57. st microcontroller maintains the 2 line 12C bus communication channel with the PCF8534A Biasing voltages for the multiplexed LCD waveforms are generated internally removing the need for an external bias generator The internal oscillator is selected by connecting pin OSC to Vss The only other connections required to complete the system are the power supplies pins Vpp Vss and Vicp and the LCD panel selected for the application Power On Reset POR At power on the PCF8534A resets to the following starting conditions All backplane and segment outputs are set to Vicp e The selected drive mode is 1 4 multiplex with 1 3 bias e Blinking is switched off e Input and output bank selectors are reset e The I2C bus interface is initialized e The data pointer and the subaddress counter are cleared set to logic 0 e Display is disabled Remark Do not transfer data on the 1 C bus for at least 1 ms after a power on to allow the reset action to complete LCD bias generator Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of three impedances connected in series between Vicp and Vss If the bias voltage level for the 1 2 multiplex drive mode configuration is selected the center impedance is bypassed by switch The LCD voltage can be temperature compensated externally using the supply to pin Vi cp All information provided in this document is subject to legal disclaimers NXP B V 2011 All righ
58. ste printing issues including smearing release and adjusting the process window for a mix of large and small components on one board e Reflow temperature profile this profile includes preheat reflow in which the board is heated to the peak temperature and cooling down It is imperative that the peak temperature is high enough for the solder to make reliable solder joints a solder paste characteristic In addition the peak temperature must be low enough that the packages and or boards are not damaged The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 26 and 27 Table 26 SnPb eutectic process from J STD 020C Package thickness mm Package reflow temperature C Volume mm lt 350 2 350 lt 2 5 235 220 22 5 220 220 Table 27 Lead free process from J STD 020C Package thickness mm Package reflow temperature C Volume mm lt 350 350 to 2000 gt 2000 lt 1 6 260 260 260 1 6 to 2 5 260 250 245 gt 2 5 250 245 245 Moisture sensitivity precautions as indicated on the packing must be respected at all times Studies have shown that small packages reach higher temperatures during reflow soldering see Figure 30 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 6 25 July 2011 47 of 52 NXP Semiconductors PC F8534A
59. ts reserved Product data sheet Rev 6 25 July 2011 8 of 52 PCF8534A Universal LCD driver for low multiplex rates NXP Semiconductors 7 3 LCD voltage selector The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration The operation of the voltage selector is controlled by the mode set command from the command decoder The biasing configurations that apply to the preferred modes of operation together with the biasing characteristics as functions of Vicp and the resulting discrimination ratios D are given in Table 5 Discrimination is a term which is defined as the ratio of the on and off RMS voltage across a segment It can be thought of as a measurement of contrast Table 5 Biasing characteristics LCD drive Number of LCD bias Von AMS Von RMS i Vn BMS mode Backplanes Levels COnfiguration Vran V V RMS static 1 2 static 0 1 00 1 2 multiplex 2 3 YW 0 354 0 791 2 236 1 2 multiplex 2 4 VW 0 333 0 745 2 236 1 3 multiplex 3 4 Va 0 333 0 638 1 915 1 4 multiplex 4 4 Vo 0 333 0 577 1 732 A practical value for Vicp is determined by equating Vot Rms with a defined LCD threshold voltage Vthyofty typically when the LCD exhibits approximately 10 contrast In the static drive mode a suitable choice is Vicp gt 3Vih otf Multiplex drive modes of 1 3 and 1 4 with 1 bias are possible but the discrimination and hence the contrast
60. uctors PC F8534A 7 10 3 PCF8534A Universal LCD driver for low multiplex rates In cascaded applications each PCF8534 lt A in the cascade must be addressed separately Initially the first PCF8534A is selected by sending the device select command matching the first hardware subaddress Then the data pointer is set to the preferred display RAM address by sending the load data pointer command Once the display RAM of the first PCF8534A has been written the second PCF8534 lt A is selected by sending the device select command again This time however the command matches the hardware subaddress of the second device Next the load data pointer command is sent to select the preferred display RAM address of the second PCF8534A This last step is very important because during writing data to the first PCF8534A the data pointer of the second PCF8534A is incremented In addition the hardware subaddress should not be changed while the device is being accessed on the C bus interface RAM writing in 1 3 multiplex drive mode In 1 3 multiplex drive mode the RAM is written as shown in Table 7 see Figure 13 as well Table 7 Standard RAM filling in 1 3 multiplex drive mode Assumption BP2 S2 BP2 S5 BP2 S8 etc are not connected to any elements on the display Display RAM Display RAM addresses columns segment outputs Sn bits rows o h eR Bb a4 5b bT Bbh b backplane outputs BPn 0 a7 a4 al b7

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