Motorola 68HC12B32 User`s guide
Contents
1. CPU datasheets A length of clock paths is critical and must be taken into consideration when designing the target During the emulation the distance between the crystal in the target and the CPU on the POD is furthermore increased therefore the impedance may change in a manner that the crystal doesn t oscillate anymore In such case a standalone crystal circuit oscillating already without the CPU must be built or oscillator used COP Internal COP must be disabled when using the emulator respectively while debugging STOP Instruction STOP instruction is completely supported by the emulator After the STOP instruction is being executed the CPU is stopped and the debugger displays HALTED status Note that the debug windows cannot be updated while HALTED status is displayed When the CPU is awaken either by interrupt or target reset the emulation execution proceeds normally Internal CPU Flash Note that internal FLASH is disabled during the emulation and cannot be used in any way Internal RAM Internal EEPROM If the CPU provides a capability to write to the internal RAM or EEPROM via memory window no specific programming sequence required the download file can be loaded to the internal RAM or EEPROM using the Target Download option The debugger downloads the code to the internal memory after reset via the CPU If the CPU requires some registers to be configured before the CPU is able to write into the EEPROM area the user m2. added to some signals Pull up pull down resistors are required to define the inactive state of signals like reset and interrupt inputs while the POD is not connected to the target Because of this the POD can operate as standalone without the target Final Target Application Test After the application is being more or less debugged and final application test is performed it is recommended to remove all breakpoints and to close all debug windows memory SFR watch to eliminate any possible influence of the emulator on the CPU execution There were cases where the target application has been behaving differently with the target CPU inserted or the POD connected If the debugger is configured to update some debug windows in real time the user may not be aware of that the CPU execution may be slightly disturbed However when the monitor access type is configured to update debug windows while the CPU is running the CPU execution is disturbed significantly depending on the necessary number of memory accesses to update opened debug windows There are cases when internal peripheral device requires read access of the particular register during the device configuration The user has had SFR window opened and the necessary read access was actually performed by the debugger and not by the application as it would be correct Therefore the application was working fine with the emulator but a standalone application didn t work correctly as the periphe
3. The signal connector can also have other markings like P1 U1 etc Please refer to the POD specific documentation for the signal connector name and signals present iSYSTEM August 2001 2 8 For every POD the following information is given e Ordering code If there are different speed versions of a POD the ordering code is modified by appending the speed in MHz 1C8 1020 16 for the 16 MHz 8031 POD e information on available speed versions and required Emulator access time e POD size and position of PINI on the target adapter relative to bottom left corner The memory range specifies the range of addresses that a POD can address If this specification is omitted the default IMB is assumed Note The In Circuit Emulator can emulate a processor or a microcontroller Beside the CPU additional logic is integrated on the POD The amount of additional logic depends on the emulated CPU and the type of emulation A buffer on a data bus is always used minimal logic and when rebuilding ports on the POD maximum logic is used As soon as a POD is inserted in the target instead of the CPU electrical and timing characteristics are changed Different electrical and timing characteristics of used elements on the POD and prolonged lines from the target to the CPU on the POD contribute to different POD characteristics Consequently signal cross talks and reflections occur capacitance changes etc Beside that pull up and pull down resistors are
4. ad Z SY S T EM Solutions for Embedded Systems Development V1 0 POD Hardware Reference Motorola 68HC12B32 POD rev F Thank you for purchasing this product from iSYSTEM This product has been carefully crafted to satisfy your needs Should any questions arise do not hesitate to contact your local distributor or iSYSTEM directly Our technical support personnel will be happy to answer all your technical support questions All information including contact information is available on our web site www isystem com Feel free also to explore our alternative products iSystem constantly yields for development and therefore certain pictures in this documentation may vary slightly from the actual product you received The differences should be minor but should you find more serious inconsistencies of the product with the documentation please contact your local distributor for more information This document and all documents accompanying it are copyrighted by iSYSTEM and all rights are reserved Duplication of these documents is allowed for personal use For every other case a written consent from iSYSTEM is required Copyright 2001 iSYSTEM GmbH All rights reserved All trademarks are property of their respective owners W 1 SY S T E M Solutions for Embedded Systems Development www isystem com iSYSTEM August 2001 1 8 X 1 SY M T EM Solutions for Embedded Systems Development POD Hardware Reference In C
5. ed Using the emulator the port registers Port Registers and Port Data Direction Registers belonging to the rebuilt ports must be mapped to the target when emulating the single chip mode The rebuilt ports have a 10kOhm pull up resistor array on the socket They can be removed if the target application programs these ports as non pull up outputs Simulated ports and pull up resistor sockets iSYSTEM August 2001 5 8 Whenever operating close to electrical limits and having problems with rebuilt ports please check pull up and pull down resistors They shouldn t be too strong neither too weak Check the voltage level Try to withdraw from voltage limits General HC12 Emulation Notes Clock When using the external clock the HC S 12 application doesn t start It works fine when I use internal clock There are two major issues the user must pay attention to A Also when using external clock the user must specify target clock frequency 2 ECLK in the Hardwara Emulation Options Vcc Clock tab like in the case when using internal clock It is required by the debugger to be able to synchronize with on chip BDM firmware which operates at CPU s system clock frequency tis not recommended to use a crystal in the target as a clock source during the emulation It is recommended that the oscillator is used instead Normally a crystal and two capacitors are connected to the CPU s clock inputs in the target application as stated in the
6. ircuit Emulation PODs The following elements of interest are located on all In Circuit emulation PODs e emulation CPU acts on behalf of target s CPU On some PODs you must use the same CPU on the POD as it is used on the target see your POD reference page In such cases remove the CPU from the POD and insert the CPU that you use in the target system in its place e red LED D3 lit when CPU is running e green LED D4 lit when Emulator is ready for emulation e a connector mostly marked ST3 contains signal lines some of which are hardware configuration lines such as bank select signals others you can use for signal generation pattern generator outputs Here are some common signals found on the signal connector commonly marked as ST3 e GND Ground e BPE External breakpoint input Active high e RESO RO Reset output Connect to target to reset peripherals e TRES TR Target reset input e AUXn AUX signal inputs same as inputs on Emulator trace Note On PODs that support synchronization between two or more Emulators currently only the HC S 12 Family see the Synchronization section in the Hardware User s Guide for more information AUXO and AUXI are cut short with Run Stop synchronization line and AUX2 AUX3 with RESET synchronization line You should use these pins to connect to other PODs or target CPUs e PATO2 Pattern generator output on 16 bit POD e OC4 6 Pattern generator output on 8 bit POD Note
7. ral device was not configured properly iSYSTEM August 2001 3 8 ad Z SY M T EM Solutions for Embedded Systems Development V1 0 POD Hardware Reference Motorola 68HC12 B32 POD rev F Ordering code IC20080 POD Speed MHz 8 Emulator Speed ns 65 Exchange CPU YES Before connecting the POD make sure you have read the technical notes on Motorola 68HC12 Family in the Hardware User s Guide 5 750 IN 95 25 mm MNT SN ce OO XXX XP ER USS n in 22h SO GL EGOS 5500000000000L NEAL GR9 G00 oooooooooo 2 0000000000 1 0 ou 1 oo 2595 Doo a oo 0625 O oo 1 oo 0596 Z oo oo 020 a oo oo 0999 N n 99 CPU oo 0996 M o 99 oo E 969o t A oo oo E 9999 N oo oo z 0695 H ee oo E og 020 O Q 25 o2 a 0 YX oooooooooo JO Dm 020 05 lt x 00000000000 c 9 N 0999 xtal o2 Nee 020 mR o D o Oo a NM a3 0599 0595 0909 o9o 2080 GR8 2000 GR7 0595 O 0 0 0 0 0 0 O O 0 0 0 0 0 0 0 0 0909 5 500 IN 134 62 mm POD Layout Emulated CPU 68HCI2BE32 iSYSTEM August 2001 4 8 Jumper Settings On this POD Vcc source and level selection is performed manually through jumper settings Jumper J2 Position Vcc source determines the source Jumper J2 settings Jumper J1 determines the Vcc level This setting is ignored if J2 is set to target source Jumper J1 settings If the internal Emulator clock i
8. ronization Connector J4 For more information please refer to the Synchronization of Two or More Emulators section of the Hardware User s Guide Target Adapters iSYSTEM offers various adapter solutions for this POD Please refer to the adapter documentation for more details iSYSTEM August 2001 7 8 POD Target Layout The POD target layout is T_QFP80 BEE o AJAD NAJO T_QFP80 Top POD view 0 550 IN 0 889 cm 0 550 IN 0 889 cm 80 62 o000000000 eo000000000 79 61 m 9004 E p 59 60 e E oo SQ 0 100 IN oo 9o e p 09 oo a 0 254 em 99 4g 41 29 42 7 21 39 9000000000 9000000000 22 40 1 600 IN 26 4 064 cm oR ge s S T_QFP80 Dimensions iSYSTEM August 2001
9. s used and a quartz is used in the target sometimes the CPU will not start after a reset In this case the connection between CPU XTAL and the Target XTAL must be broken The jumper J9 determines this setting Position Description Set CPU amp Target XTAL connected CPU amp Target XTAL disconnected Jumper J9 settings Electrical Differences and Rebuilt Ports In general when emulating the single chip mode some ports have to be rebuilt on the POD because original ports are used for emulation typically ports used as address and data bus in extended mode Special devices so called port replacement units provided already by the CPU vendor or other standard integrated circuits are used to rebuilt lost ports Rebuilt ports are logically 100 compatible with original CPU s ports but electrical characteristics may differ If special device port replacement unit is available electrical characteristics don t differ much and usually the user doesn t have to pay attention The differences may become relevant when standard integrated circuits are used and operating close to electrical limits e g when input voltage level is close to specified maximum voltage for low input level 0 or specified minimum voltage for high input level 1 When emulating the single chip mode original ports A B and E are used for the emulation and rebuilt by standard integrated circuits on the POD therefore electrical characteristics are chang
10. ust configure the necessary registers respectively using the initialization dialog Any sequence added in the initialization dialog is executed immediately after reset before the download is performed Executing the program in the internal RAM or EEPROM has some limitation depending on the emulation system The run stop and single step debug commands can be used in the internal RAM or EEPROM Note that single step can be performed in the disassembly window but not in the source window No breakpoints can be set in the internal memory area iSYSTEM August 2001 6 8 Checksum When performing any kind of checksum in the emulated code area note that all breakpoints must be removed before otherwise the results are distorted Note that the emulator forces breakpoint instruction on the data bus when executing the code at the address where breakpoint is set Slow Mode It is not recommended to debug the application running in slow mode due to a CPU flaw The Signal Connector A signal connector is available on the POD marked ST3 fo PAT PatemGeneraorOupa p UXO AUX Signal input ST3 Signal Connector Synchronization of Two or More Emulators When multiple emulators should operate synchronously the synchronization connector marked J4 must be used All the emulators that should operate synchronously must have connected together separately SR SYNC RESET pins SS SYNC STOP pins and GND ground pins Synch
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