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ispEXPERT Compiler User Manual

1. Output With Global Reset 10 Input s GZ OTA partil G2 015 Parti AND 2559 Parto G2 016 patro OUTPUTA ET XLDX GUTPUTB ET AND 2652 p rtl AND 2597 parto isoEXPERT Compiler User Manual 245 Compilation Report for the ispLSI 5000V 8000 Devices S201 parr 5 Fanout s GIDLE 150 GLP Osl GOL y TLS GDL Tos XOTCLE Product Term s Turbo Product Term s Macro Local Control Product Term s GLB Output Level s W ND MA G2 OI7 part0 D XLDX amp OUTPUTA E7 amp OUTPUTB E7 XLDX amp OUTPUTA E7 amp OUTPUTB E7 G2 QI4 partl amp G2 QI5 partO0 amp G2 QI6 partO0 amp AND 2652 partl amp AND 2539 partO0 amp AND 2547 part0 S XLDX amp G2 QI7 part G2 OI7 part0 C XCLKX G2 OIT part0 R XCDX G2 QI7 part0 PR XCDX 4 XSDX Global Reset Preset Signal Local Feedback G2 QI7 partl same as G2 QOI7 partO0 Local Feedback Has Same Logic as Previous Output 1 Fanout s 115 132 Output G3 QI1 partO0 with Global Reset used 4 Output With Global Reset 7 Input s OUTPUTA Eby OQUTPUIB Ely 63 010 parto YENX YCAIX XLDX GJ OIL parri 3 Fanout s GLOG 20 qhb29 D0y TOLIR Product Term s Turbo Product Term s Control Product Term s GLB Level s OF W A G3 OIl part0 D YLDX amp OUTPUTB El amp OUTPUTA EI YLDX amp OUTPUTB_El amp OUTPUTA El1 YCAIX amp YENX amp YLDX amp G3 QIO part0 5 IEDR wo o3 DIE perti GJ OL DarUD t YCLKX Go OIL P rt
2. Figure 5 21 Power Calculator Dialog Box MFR Not Available After you enter the estimated or actual frequency of your design in this dialog box and click OK the Power Calculator ICC Operation Estimate window appears Figure 5 19 At the bottom of this window is the Activity Factor slide bar which is scaled from 0 1 196 to 0 99 9996 As you move the slide bar to the right the ICC operation field increases with the level of activity For example in Figure 11 the ICC operation is 52 91 mA when the activity factor the average percentage of macrocells toggled at each clock of the design is 0 1 10 The easiest way to pre determine the activity factor of your design is to run pre route functional simulation to get an estimate of the percentage of macrocells in your design that are toggled at each clock isoEXPERT Compiler User Manual 191 Chaptere The Physical Viewer The Physical Viewer is a tool for viewing the implementation details of the ISOEXPERT Compiler graphically It helps increase your understanding of the implementation details It uses a functional block representation of the ispLSI device that shows the GLBs IOCs and Dedicated Control Input resources The Physical Viewer allows you to inspect the logical resource assignments signal path trace and functional logic of selected components The primary components of this tool include a Design Navigator Connectivity display Signal Path and Equation tracer and
3. Lattice sanana Semiconductor a a a a a a Corporation ISDBEXPERT Compiler User Manual Version 8 0 Technical Support Line 1 800 LATTICE or 408 428 6414 EXPERT UM Rev 8 0 1 Copyright This document may not in whole or part be copied photocopied reproduced translated or reduced to any electronic medium or machine readable form without prior written consent from Lattice Semiconductor Corporation The software described in this manual is copyrighted and all rights are reserved by Lattice Semiconductor Corporation Information in this document is subject to change without notice The distribution and sale of this product is intended for the use of the original purchaser only and for use only on the computer system specified Lawful users of this product are hereby licensed only to read the programs on the disks cassettes or tapes from their medium into the memory of a computer solely for the purpose of executing them Unauthorized copying duplicating selling or otherwise distributing this product is a violation of the law Trademarks The following trademarks are recognized by Lattice Semiconductor Corporation Generic Array Logic ISP ispANALYZER ispATE ispCODE ispDCD ispDOWNLOAD ispDS ispDS isoEXPERT ispGDS ispGDX ispHDL ispJTAG isoSmartFlow ispStarter ispSTREAM ispSVF ispTA ispTEST ispTURBO ispVECTOR ispVerilog ispVHDL ispVM Latch Lock LHDL pDS RFT Total ISP and Twin GLB are trademarks
4. isoEXPERT Compiler User Manual 83 Compiler Control Options Compiler Control Options The Compiler Control Options perform the following functions m Determine the flexibility given to the compiler to complete your design m Define the global objectives for design implementation m Allocate the physical device resources in support of specific Device Options m Produce a physical netlist of your design Usually you try to optimize your design for speed resource utilization or both You can begin compiling with strict parameters that optimize your design goals If the parameters are too restrictive for the available device resources a compilation failure may occur If this happens try sets of parameters that gradually decrease the restrictions until you are able to successfully compile your design If the compiler encounters an error or if it determines that your design is not routable the compile process ends Check messages in the report and log files Compiler Control Options can be specified from the command line in a parameter par file in the design source file or using the Design Manager If you specify a Compiler Control Option in more than one place the precedence for implementation is the Design Manager command line Parameter File and design description The Design Manager settings take precedence over all other input files To set Compiler Control Options 1 Select Tools Compiler Settings from the Design Manager T
5. C p 520 520D 9 709 700 9 70 8 70D 9 70870 EU O ae NENNEN FOO 2 0 Figure 5 13 Timing Matrix Table When paths in the Timing Matrix table are preceded by D the delay is to the data input of that register When paths are preceded by CLK the delay is to the CLK of that register isoEXPERT Compiler User Manual 185 Timing Explorer E Clock Frequency Table CNT4 C isptoolssispcompsE xamplesXE dif CH T 4 Frequency Table Source Source Destina Destina Clock P Freque GLB Levels Ei cik ao 1000 100 2 gt a GIO ql a as ql an TE TE o EE EEE EEE Figure 5 14 Clock Frequency Table v Set and Hold Table CHT4 C isptools ispcompiExamples EdiA CNT4 Mel Setup and Hold Table gg Eg le EE OC 0 1 OK 380 f 180 D an im CK 830 150 Figure 5 15 Setup and Hold Table isoEXPERT Compiler User Manual 186 Timing Explorer Dy Too Table CNT4 C isptools ispcomp ExamplestEdift CNT4 Film Tco Table Registe Source Destina Delay ns _ QB OK a 480 o0 CLK CO 1890 Qf OK Gi 1450 af OK CO 1900 Q2 OK G2 1450 Q2 OK CO 1900 AB OK G3 4590 Q3 CLK CO 1900 Figure 5 16 Tco Table Tpd Table CNT4 C isptoolsispcompsE xam fel E3 Tpd Table Delay ns 17 00 17 00 52 523 Figure 5 17 Tpd Table Pop Up Menus from the Tim
6. Calculates and highlights the design s shortest timing path in the Timing Matrix Table m Frequency Calculates and highlights the maximum design frequency in the Frequency Table From a signal category or signal name in the Signal Navigator tree you can select the following commands m Add Source Timing Tag Adds the highlighted signal to the sources in the Timing Matrix Table You need to select Show Timing Data to calculate values for this source m Add Destination Timing Tag Adds the highlighted signal to the destinations in the Timing Matrix Table You need to select Show Timing Data to calculate values for this destination m Frequency Adds the highlighted signal to the frequency table and shows the values for that signal Tco Path Displays the Tco Path Table with the Tco values for that signal m Setup and Hold Displays the Setup and Hold Table with the Setup and Hold values for that signal m pd Path Displays the T pd Table with the Tpd values for that signal isoEXPERT Compiler User Manual 184 Timing Explorer Timing Explorer Tables The following tables are available in the Timing Explorer They are displayed when you request that timing information from the ispEXPERT Compiler Results menu from the Physical Viewer or from within the Timing Explorer m Timing Matrix Table Figure 5 13 Clock Frequency Table Figure 5 14 Setup and Hold Table Figure 5 15 Tco Table Figure 5 16 Tpd T
7. Endpoint QU output port Name pin name type Delay Path GLB QIO QO reg 000 0 00 ORP ORP Bypass 2540 540 OO Tout OU 2 40 data arrival time 2 40 obtarbtposmL CLA input port Endpoint GLB OIS CEK edge triggered flip flop Name pin name type Delay Path GR pum 0 00 0 00 GRP 1410 Leto GLB A1 O30 Y 40 GLB OI3 CLK reg 0400 140 data arrival time 1 40 isoEXPERT Compiler User Manual Timing Analyzer Reports 260 6192 Report Timing Analyzer Reports since the cnt4 design does not use a 6000 family device the report shown is for a different design It is an example of a design mpt file Module Timing Report Design Name m sh01 1 Part Name ispLSI6192SM 70LM208 This report contains the internal timing characteristics and the path delays starting or ending at any module I O Module Information Primitive Name RGTRSO7 Instance Name REG 1 Functional Description Register Counter Timing Description Max Min in ns l External Timing 16 bit Timer Clock to Carry Out TO 16 bit 2 Internal Timing CLOCK to Carry OUL TC 16 bit Carry Ipn Count Hold Setup bo Clock Carry In Count Hold Hold to Glock Carry Iny Count Hold Lo Carry OUR TO Preload Setup to Clock Freload Hold to Clock Preset Setup to Clock Preset Hold to Clock Select to Parallel Data Out Select Setup to Clock Select Hold to Clock Enable Setup to Clock Enable Hold from Clock Reset to Data Out Reset Pulse Duration wP a TEmi
8. Enter or select the name of the Property File Parameter File Syntax NA Command Line Syntax prop file name isoEXPERT Compiler User Manual 145 Compiler Control Options Single PT Packing for Improved Routability The Single PT Function Packing for Routability compiler option specifies how Single PTs are mapped among the macrocells in the device This option is only valid for isoLSI 8000 devices Default is 0 Description An ispLSI 8000 device has 80 product terms that map to 20 macrocells Twenty of these product terms are Single Product Terms m When a value of 0 is specified the fitter tries to map the 20 Single PTs to one or more macrocells by sharing PTs between single PT and multiple PT functions m When a higher value of this option is specified 1 through 9 the fitter tries to spread the Single PTs among the 20 macrocells Increasing the value improves routability m When a value of 10 is specified the 20 Single PTs are mapped to their default original macrocells Design Manager Sequence Tools Compiler Settings Click Advanced Move the Single PT Function Packing for Routability slide bar from O to 10 Parameter File Syntax NA Command Line Syntax EO Glas isoEXPERT Compiler User Manual 146 Compiler Control Options Performing Batch Mode Timing Analysis You can use the TIMING ANALYZER option to run the Timing Analyzer as a batch mode process during the compiler process The default is ON
9. OL SC CLKX Output 1N419 8 Input s ENX PSX OTO0 DX CDX OL LOX CIX 1 Fanout T pcm Im indicates the specific GLB input as the signal destination in this case 3 Product Term s 1 GLB Level s S1N419 PSX D2X amp LDX amp CDX t OIO amp QI1 amp CIX amp ENX amp CDX amp LDX GLB glb02 A1 o Inputdis GLOSO OGLU Lofy ED CD Ely 101509 010 180 BOO DUX Larre DO DL 1915 ENO ENX 160 Sb GDS LUJ ES PS ELT 2 Dupuis ENODE START Olke XOINSO65 493 T Product Term s Output INODE START ENDAL ENX Pox DUX OITO ODS LDX CIX 1 Fanout s glb00 114 4 Product Term s 1 GLB Level s INODE START PSX DOX amp LDX amp CDX CIX amp ENX amp CDX amp LDX S QIO amp CDX amp LDX amp PSX Output SIN365 isoEXPERT Compiler User Manual 225 T SEDIDIDESUS ENX DIX 1 Fanout s GLU Sse 3 Product Term s 1 GLB Level s pex 010 OD EDX GE SIN365 PSX To DIX amp LDX amp BODX QIO amp CIX amp ENX amp LODX amp LDX GLB glb03 A5 r LINDE S QI2 16 GLBUS OL OIL dio FLO O07 SIN Goy Jw AGlool sol SINT ED HS ESOS FS TA 2 OUEPUENS Q12 O0 QIL OI 4 Product Term s output 912 S Topak sS PS Goss ux I 4 Fanout s GlIDbDOU IrIA4 GIBU L4 2 Product Term s 2 GLB Level s 1N419 gibo TTE 025 QI2 D QI2 amp CDX LDX amp S 1N419 O14 C CLRX PSX
10. Summary Only Longest Shortest C Summary amp Detailed C Maximum Number OK Cancel Figure 5 9 Timing Analyzer Path Selection Dialog Box NOTE You must select source and or destination nodes to perform path analysis e Inthe Analysis Path Criteria area you can specify that you want to calculate for All nodes Longest Shortest paths or Maximum Number value If you select all nodes the Timing Analyzer calculates the delays from all the source nodes that drive the destination nodes If you specify Longest Shortest only the longest and shortest path are calculated If you specify a maximum number the Timing Analyzer limits the delay calculation to that number Those delay values are printed in descending order NOTE Selecting All Sources may result in a long Timing Analyzer runtime e Use the Report type area to specify the type of Path Selection report to be generated The Summary Only selection generates the design spt file that contains a summary of the path selection information The Summary amp Detailed selection generates both a summary design spt and a detailed version design dpt of the path selection report The detailed report provides a complete path trace of each reported path e Click Select Source Nodes to display the Select Source Nodes dialog box Figure 5 10 Use the Show Nodes area to filter the nodes to be displayed in the list boxes Move the nodes between the Available Nodes and th
11. pins IOCs or Dedicated Control Inputs Refer to page 207 for descriptions of these property boxes You can display multiple property boxes at the same time isoEXPERT Compiler User Manual 195 Connectivity Window Connectivity Window The Connectivity window Figure 6 3 provides a block diagram showing how the design logic is implemented in the device and how data is propagated across GLBs IOGs and Dedicated Control Inputs The Connectivity window does not show the Global Routing Pool GRP or the Output Routing Pool ORP contents except when an ispL Sl 8000 device is used Then the routing pool information displays 99 AH AN al 11 Ha AA HE gt pe Es a s x E a es pe 5 Figure 6 3 Connectivity View You can select the GLB output pin IOC or Dedicated Control Input pin and the mode of display to control the information in the Connectivity window The following information is available from the connectivity window GLB IOC Dedicated Control Input and GLB output pin names and locations in the device Resource usage which GLB IOC Dedicated Control Input and GLB output pin block is actually used and how much of the block resources are used Individual views of GLBs IOCs Dedicated Control Inputs and GLB output pins Fan ins and fan outs for the selected IOG Dedicated Control Input and GLB Output pin Path if available between selected components Device n
12. Compiler Control Options Minimizing GLB Levels The Minimize GLB Levels for All Paths compiler option instructs the compiler to reduce the GLB levels on all paths in your design Default is HIGH Description During compilation the compiler automatically attempts to reduce GLB levels along the longest paths in your design This is done to decrease delays in and maximize the frequency of your implemented design Minimize GLB Levels for All Paths goes a step further and attempts to reduce the GLB levels along all paths in your design not just the longest paths This enables you to further reduce delays in your design which may increase maximum frequency even more m The HIGH reduction effort is valid for all ispLSI device families This option reduces GLB levels on the longest paths first then continues with all paths with a very high level of effort This option may require a large amount of CPU time and memory gm The LOW reduction effort is valid only for the ispLSI 5000V and 8000 device families Again like the HIGH effort it instructs the compiler to reduce the GLBs on the longest paths first and then to continue with all paths However it does it at a slightly lower effort due to the complexity and size of the ispL SI 5000V and 8000 device architectures Design Manager Sequence Tools Compiler Settings Click Advanced Select Minimize GLB Levels for All Paths Select Reduction Effort High or Low Parameter File Syntax
13. FE m Ug ki cella dios Lire Pidaci Tana Tuta Product Terri Vern ig Pang d bz dry lector 0110 Figure 5 19 Power Calculator Window The Power Calculator is accessed by selecting the Tools Power Calculator menu item from the ispEXPERT Compiler Design Manager This menu item is only enabled if you have selected an ispL SI 8000 device and have run a successful compilation of your design After you select the Tools gt Power Calculator menu item a dialog box appears to prompt you for the frequency of your design If you ran the Timing Analyzer during compilation the Power Calculator takes the frequency of the design from the Maximum Frequency Report as shown in Figure 5 20 Operating frequency i being used from the Maximum Frequency Espe Report Tou may either use this frequency OR enter a different value n Mhz Figure 5 20 Power Calculator Dialog Box MFR Available isoEXPERT Compiler User Manual 190 Power Calculation If the Timing Analyzer was not run or was unable to generate a Maximum Frequency Report for the Power Calculator to read a different dialog box appears Figure 5 21 so that you can enter an estimated frequency for your design or enter the maximum frequency of the target device hel aximum Frequency Report Mat Found Either the Timing Analyzer ens was not run ar this design has no registers Hun the timing analyzer OR enter an estimated Operating Frequency 110 Mhz
14. Figure 3 26 The ISDBANALYZER Window Due to resource constraints not all internal nodes are observable and not all observable nodes can be analyzed at the same time The ispANALYZER provides the capability to create multiple workspaces and to produce multiple JEDEC and SIM files for a compiled design You can create multiple workspaces that connect the nodes to different pins If you cannot observe two nodes because they both need to connect to the same pin you can set up two workspaces so you can observe the nodes separately When you compile the different workspaces a JEDEC file is created for each workspace The JEDEC and SIM file names are generated from the ISDANALYZER workspace name except when you are using the last compiled design and have not provided a workspace name In this case an prefix will be added to the design name so the original JEDEC and SIM files from the Compiler are not overwritten isoEXPERT Compiler User Manual 115 Analyzing Your Design ISDANALYZER Menus The ispANALYZER menus are described in this section Many of the menu items are the same as the menu items in ispEXPERT Only the menu items specific to the ISpANALYZER are described here File Menu The File menu has the following unique menu items m OpenispANALYZER Workspace Displays the Open Workspace dialog box so you can open an existing ispANALYZER workspace If you select Last Design Compilation the most recent design workspac
15. Megablock MB Naming Net Clock signals used to drive GLB registers Clock signals generated from a Clock GLB that go through the Clock Distribution Network to the global clocks The clocks used to drive either GLB or IOC registers globally Output enable signal from the GOE pin that can be used to enable any or all IOCs in the device A signal that resets all the registers in the device Interconnection location of the internal logic The GRP provides complete interconnectivity with fixed and predictable delays A GLB level macro that is predefined and cannot be edited Each I O Cell is directly connected to an I O pin and can be programmed for combinatorial input registered input latched input direct output 3 state output or bi directional I O Two clock signals IOCLKO and IOCLK1 that are used for clocking all of the IOG registers in the device The ispEXPERT Compiler software package that is used to implement designs in ispLSI devices through automatic partitioning An acronym for in system programmable Large Scale Integration Allows programming of a device on a PC board and requires no external programmer File in the format prescribed by the Joint Electronic Device Engineering Council GLB output pins Predefined reusable logic blocks that reduce the amount of time necessary to enter the equivalent Boolean equation A megablock consists of a group of eight Generic Logic Blocks GLBs Output Rout
16. NET NET NET NET net name net name net name net name net name net name net name net name net name net name SAP BAP DCE BCE SLP ELP SNP ENP SEE ELP path_name path_name path_name path_name path_name path_name path_name path_name path_name path_name Design Attributes ENDPROPERTY BNDPROPERIY ENDPROPERTY ENDPROPERTY ENDPROPERTY ENDPROPERTY ENDPROPERTY ENDPROPERTY ENDPROPERTY ENDPROPERTEY 292 Design Attributes Symbol Attributes Instance INST attributes are used to apply specific control on the instance of interest or they can be used to overwrite instance type SYM attributes If both an instance type SYM and an instance INST attribute are specified the instance INST attribute takes precedence See Figure B 14 for an example m OPTIMIZE Instance Syntax PROPERTY cell name INST instance name OPTIMIZE ON ENDPROPERTY Symbol Syntax PROPERTY cell name SYM OPTIMIZE ON ENDPROPERTY gm PROTECT Instance Syntax PROPERTY cell name INST instance_name PROTECT ENDPROPERTY Symbol Syntax PROPERTY cell name SYM PROTECT ENDPROPERTY gm REGTYPE Instance Syntax PROPERTY cell name INST instance name REGTYPE GLB IOC EITHER ENDPROPERTY Symbol Syntax PROPERTY cell name SYM REGTYPE GLB IOC EITHER ENDPROPERTY m RESERVE PIN Symbol Syntax PROPERTY cell_name SYM RESERVE_PIN pin_number ENDPROPERTY n NOTE RESERVE_PIN must be specified
17. Net S S S PRESERVE X 7 wm SAP EAP 1000 2000 3000 6000 All NN some NN seene ner 000 20006000 e000 DON NEN T NN ser nr o ewo isoEXPERT Compiler User Manual Applying Design Attributes Precedence of Design Attributes When several Design Attributes are used in a design they are all honored as long as they do not conflict or overlap If they conflict one or more of the Design Attributes will be ignored depending on the design If they overlap one Design Attribute can override other Design Attributes Table 2 2 groups Design Attributes in their order of precedence when relating to the same logic A Design Attribute with a higher precedence for example 1 overrides those with lower precedence for example 5 A Design Attribute with the same level of precedence will generally not override another unless they conflict Table 2 2 Design Attribute Precedence BFM LOCK LOCK BFM LOCK GRP LXOR2 OPENDRAIN OPTIMIZE OUTDELAY PRESERVE PROTECT PULL RESERVE PIN SLOWSLEW VOLTAGE XOR SNP ENP SCP ECP SLP ELP STP ETP CLK CRIT GROUP REGTYPE Design Attribute Syntax The following shows the general syntax used in this manual for Design Attributes attribute name attribute value An equal sign may or may not be needed in your design environment The exact syntax for a Design Attribute may change slightly within the different design entry environments supported by Lattice Semiconductor F
18. determines critical timing paths and evaluates maximum frequency of the design and setup hold requirements Path Analysis Paths normally start at primary input ports bidirectional ports or output pins of registers hereafter called the source nodes and end at primary output ports bidirectional ports data and clock pins of the registers hereafter called destination nodes There are four types of timing paths m Primary input to register A path begins at the primary input port or bidi port and ends at the data pin or clock pin of a register m Register to register A path begins at an output pin of a register and ends at a data pin or clock pin of a register m Register to primary output A path begins at an output pin of a register and ends at a primary output port or bidi port m Primary input to primary output A path begins at a primary input port or bidi port and ends at a primary output port or bidi port A Tpd path is a path that begins at a primary input port or bidi port and ends at a primary output port or bidi port and that does not have a register in the path A Tco clock to output path is a path that begins at a primary input and drives the clock pin of a register whose Q output ends at a primary output The Timing Analyzer calculates the delay of a path by tracing from the starting point of the path to its ending point cumulatively adding delays along the way The longest path is the path that ha
19. portRef AO portRef AO portRef AO portRef Al InstRef U4 net CO q instRef U6 Tost Ier UJ InstRef UIO A M joine portRef CO DOoBtBSF uz inst Ret US cell DESIGN D Ce lllype GENERIC view view 1 viewType NETLIST interface port 50 direction OUTPUT Por i cCureortron OUTPUT port BI direction JINPUTJ J3 Contents Instance BLOCK1 viewref view 1 cellref ADDF1 Instance BLOCK2 viewref view 1 cellref ADDF1 Figure B 17 EDIF File for DESIGN D isoEXPERT Compiler User Manual 305 Attribute Examples PROPERTY ADDF1 NET CI SCP VAR ENDPROPERTY PROPERTY ADDF1 NET CO ECP VAR ENDPROPERTY PROPERTY DESIGN D INST BLOCK1 VAR PATHA ENDPROPERTY PROPERTY DESIGN D INST BLOCK2 VAR PATHB ENDPROPERTY Figure B 18 Defining Parameterized Attributes in a Property File Multiple Property Identifiers In Figure B 19 the schematic shows two paths ending at NETC In the Property File in Figure B 20 NETA and NETB have been assigned the attribute SCP Start Critical Path NETC has been assigned the attribute ECP to specify the End Critical Path for PATH1 and PATH2 Instead of listing ECP PATH1 and ECP PATH2 separately the statement in the Property File uses a multiple value identifier for ECP In this case the identifiers are separated by a comma Multiple identifiers can also be separated by semicolons or colons If separate lines had been used for ECP in the
20. similar to using the BFM net attribute However if you are using a tristate bus the compiler cannot place logic into one BFM Refer to ispLSI 8000 Tristate Usage on page 282 for details isoEXPERT Compiler User Manual 50 Path Attributes Example In Figure 2 18 A the circuit does not use SCP ECP attributes The resulting two GLB level implementation is shown in Figure 2 18 B The compiler normally avoids a one level GLB implementation when it results in a large number of PTs The second circuit shown in Figure 2 19 A uses SCP ECP attributes and results in a one GLB level implementation Figure 2 19 B despite its use of more PTs and more GLB resources A two GLB level implementation uses logic resources more efficiently a one GLB level implementation is superior for speed critical applications OUT1 ZZZ ZZZ OUH Cho OUT2 A IN8 IN7 OUT1 a IN6 INA _ y D OUT2 IN5 IN1 Figure 2 18 A SCP ECP Not Used B Resulting Two GLB Level Implementation isoEXPERT Compiler User Manual 51 Path Attributes Ni SCP PATH1 2 N E ECP OATH OUT ee ot Ee C LM ML HEMDEN ML c dcl M M ELS NEC UMORE 1 ING IN5 IN4 a OUTI E d gt OUT2 IN8 ot rm ET fo ae Ks a nm nn i Figure 2 19 A SCP ECP Used B Resulting O
21. Assigns the signal to the dedicated clock line IOCLK1 not applicable for ispL SI 5000V devices Any register clocked by IOCLKO or IOCLK1 is automatically placed within an IOC not within a GLB if the input to the register is connected to a single fan out input pin If the register input comes from any combinational logic or multi fan out input pin the register must be placed in a GLB You will get a warning if you assign an IOC clock to the clock input of such a register y NOTE If the register reset input comes from any combinational logic the register must be placed in the GLB for isoLSI 1000 2000 3000 and 6000 devices If a register being clocked by IOCLKO or IOCLK1 does not satisfy all of the conditions listed above a warning message is issued by the compiler and the register may be moved to a GLB and the CLK attribute may be changed to CLKO CLK1 or CLK2 FASTCLK Assigns the signal to any of the dedicated CLK lines CLKO CLK1 CLK2 CLK3 IOCLKO or IOCLK1 at the discretion of the compiler This allows more partitioning flexibility Gated clocks when specified as FASTCLKs use the dedicated clock GLB and the clock distribution network where available isoEXPERT Compiler User Manual 36 Net Attributes m SLOWCLK Assigns the signal to a GLB PT clock Any register clocked by a SLOWCLK signal is automatically placed within a GLB not within an IOC Use this option to define a clock as a PT clock The CLK att
22. FOs BIS levels glb00 A2 Vp Uu Z COX Oe iL Uy d OTY Ie cR cla 2 GEBOT 23 Th ce ad S1N419 Og ta 3c 4 OI pos Aw OG gib02 Al 8 2 I S1N365 duc Lg p OG INODE START Ja e ao f GLDOSy 25 Tp Bg c QI1 Do lp CE 2 OQIZ Dy Map 2p 2 Maximum Level Trace Table The Maximum Level Trace table contains the following information m Number of GLB levels for the related GLB output name GLB name and number of inputs in the transitive fan in of the related GLB output m GLB Output Name for each GLB on the specified critical path This table provides a trace back for GLB outputs that have their GLB levels equal to the maximum GLB levels in the design The trace related to different GLB outputs are separated by blank lines For each GLB output the paths relating to the maximum level are reported in each section This information can be used to identify isoEXPERT Compiler User Manual 231 Maximum Level Trace GLB Level Compilation Report performance bottlenecks in the design GLB levels may be inaccurate if the design contains combinational loops The following is an example of the Maximum Level Trace table from the Post Route Implementation report g LHD glb02 glb03 epo cabo glb02 Name 7 Ins GLB Output Name Pin Assignments Table QIO INODE START SHE SIN419 OLI SIN365 The Pin Assignments table contains the following information for the compile and if performed the post compile update m Name of e
23. Figure 3 23 2 Click Read Pin File in the Import Pin Assignment field The Open Pin File dialog box appears 3 Choose the file name and path information for the pin file to be read in Click Open R WD T n M n qm w tom WW x us exe c E CAD unn ue d WH E ua ud had a 7 oat amp WOR KA Mk DER E wa un d ur un a n 5 BE E um NS mg InpL SI 2D EE TELTAN EN a venn me wa 9 oi e m mE Figure 3 23 Pin Locations Window The Assign Pin Locations window changes to reflect the settings in the selected pin file isoEXPERT Compiler User Manual 112 Post Compile Changes Changing Pin Attributes You can change the Pull Open Drain Slow Slew OutDelay Voltage and Turbo LowPower and device Speed attributes for specific pins in the fuse map file without recompiling the project You may update the pin attributes perform Timing Analysis and generate new output files If you changed the Security option from the Device Options dialog box Figure 3 8 or the UES from the UES dialog box Figure 3 20 prior to selecting this option you can also have these values reflected in your output files This menu item is enabled only when the existing compiler results are valid and the current device is the same as the device used in the last compilation To update the pin attributes in the fuse map file 1 Select Tools Post Compile Update The Post Compile
24. In Figure 5 1 the setup time hold time and delay from clock pin to output pin of each register is 10ns In this example the longest path delay from Q1 to D2 is 90ns the delay from C1 to Q1 of FF1 is 10ns and the setup time of FF2 is 10ns The calculation for minimum clock period would then be 10 90 10 110ns The frequency is then calculated as follows frequency 1 minimum clock period 17010 2 09M isoEXPERT Compiler User Manual 170 Timing Analysis Overview INT gt combinatorial OUT2 FF2 FF IN1 C1 C2 IN2 CLK gt combinatorial Figure 5 1 Frequency Calculation Example isoEXPERT Compiler User Manual 171 Timing Analysis Overview Setup and Hold Time Evaluation Timing analysis determines the setup and hold times for registers from the ports of a design by examining all destination registers and storing the longest and shortest delay paths between all ports connected to the D or CLK inputs of flip flops and latches Setup Time Setup time is the length of time a data signal must be stable before the active edge of a CLK see Figure 5 2 Setup time for primary input ports is calculated as follows setup time longest data path delay SNOP MO peto decay setup time of register Because of differences in the longest data path and the shortest clock path it is possible for setup time to be negative clock PL rn Setup Hold Figure 5 2 Setup and Hold Time Hold Time Hold time is the l
25. PROPERTY cell name SLOWSLEW Syntax PROPERTY cell name Design Attributes PIN pin name SLOWSLEW ON ENDPROPERTY PIN pin name VOLTAGE VCC VCCIO PINARRAY PINARRAY P INARRAY PINARRAY PINARRAY PINARRAY bus name bus name bus name bus name bus name bus name isoEXPERT Compiler User Manual CRED ENDPROPERTY LOCK pin number PULL UP JOPF HOLD OPENDRAIN ON OUTDELAY ON ENDPROPERTY SLOWSLEW ON ENDPROPERTY 290 Design Attributes VOLTAGE oyntax PROPERTY cell name PINARRAY bus name VOLTAGE VCC VCCIO ENDPROPERTY Net Attributes BFM oyntax PROPERTY cell name NET net name BFM BFM index ENDPROPERTY CLK oyntax PROPERTY cell name NET net name CLK CLKO CLKI CLK2 CLK3 IOCLKO IOCLKI1I IOCLKA2 FASTCLK SLOWCLK ENDPROPERTY GROUP oyntax PROPERTY cell name NET net name GROUP group name ENDPROPERTY PRESERVE oyntax PROPERTY cell name NET net name PRESERVE ENDPROPERTY XOR oyntax PROPERTY cell name NET net name XOR ON OFF ENDPROPERTY isoEXPERT Compiler User Manual 291 Path Attributes SAP EAP oyntax PROPERTY PROPERTY SCP ECP oyntax PROPERTY PROPERTY SLP ELP oyntax PROPERTY PROPERTY SNP ENP oyntax PROPERTY PROPERTY SIP ETP oyntax PROPERTY PROPERTY cell name cell name cell name cell name cell name cell name cell name cell name cell name cell name isoEXPERT Compiler User Manual NET NET NET NET NET NET
26. STRATEGY 132 summary 86 TIMING ANALYZER 147 TIMING FILE 143 Use Internal Tristate IO Driver 148 USE GLOBAL RESET 153 Y1 AS RESET 154 Compiler log 108 accessing 108 using 276 Compiler Report 214 216 accessing 109 Design Parameters 217 Design Specification 218 Fail to Fit Information 236 GLB and GLB Output Statistics 231 ispL SI 5000V 8000 Devices 237 Maximum Level Trace Table 231 Module 227 Pin and Clock Information 228 Pin Assignments Table 232 Post Route Design Implementation 222 Pre Route Design Implementation 234 Pre Route Design Statistics 220 Summary Statistics 231 Compiler Result importing 96 111 on Explore Matrix 101 Congestion of GLBs 198 Connecting pins 95 Connectivity views 195 198 Connectivity window 196 Analyzer 205 customizing 199 Fan In 202 Fan Out 202 opening additional 200 Path 203 Timing Path 204 Copy Edit 122 Create project 80 text file 121 isoEXPERT Compiler User Manual 329 CRIT 33 64 276 289 290 and resource utilization 269 and speed optimization 277 Critical paths 50 Customize Physical Viewer 200 Customizing a color 126 127 Cut Edit 122 D Daisy Chain Download 118 Dedicated Control Input information 210 Delete Edit 122 Design analyzing 18 115 entry 17 exploring 98 improving and revising 276 modifying 120 place and route 19 reports 214 resizing 269 statistics 212 Design Attributes 30 31 289 BFM 291 CLK 291 CRIT 289 290 GROUP 291 LOCK 289 290 LOCK BFM 28
27. XGOCOIO Partl GLOBE TGS 012 partly OLSEN GO OTIO parti OOF 39 Product Term s 39 Turbo Product Term s 0 GLB Control Product Terms Output TSI83 Regular Output 19 Inputs G9 018 Part0 BOLUX 9G O19 P rtU GJ cQITO parto G3 O16 partly GJ OIU partO0 G3 0115 parvo YENX YCALX Go OLS pared Gs 0I2 partu Gs OIIO purt0 Go QI4 partly GS 01 12 part G5 012 parti GJ OLIA Darty GOL party G3 OIT part0 G3_QI1_partl 1 Fanout s g1626 142 2 Product Term s l Turbo Product Tern Cs 0 Control Product Term s 1 GLB Level s TSI83 YCAIX amp YENX amp G3 QIO partO amp G3 QIIl parti amp DOGS OIN parto ww GS OILI cDartU amp TG3 OT9 parto amp 1G3 QI8 partO amp G3 QI14 partO amp G3 QI13 parto amp DGSOIIZ part amp GS Or part amp 65 012 part amp TG3S OIO partl amp G5 Old partl 165 013 parco amp GIOS partb S 2652 consi Dort 5 B6L0X Output AND 2549 part0 4 Regular Output 6 Dnpuris 23 010 parto YENX YCAIX YLDXN G3 OlZ parcl GS 0IL parti 1 Fanout s qib2901359 Product Term s Turbo Product Term s Control Product Term s GLB Level s FORE AND 2549 partO0 YCAIX amp YENX amp YLDX amp G3 QI0 partO0 amp UES IO parti 165 012 parcl Local Feedback AND 2549 partl same as AND 2549 partO0 Local Feedback Has Same Logic as Previous Output LL Fanout s glb27 14 Output GZ OL pare wath Global Reset used
28. it overrides the global OUTDELAY option By default the global OUTDELAY Design Attribute is set to OFF Design Manager Sequence Assign gt Pin Attributes gt OutDelay Move pins to the appropriate list Parameter File Syntax OUTDELAY ON OFF Command Line Syntax NA Using Pull up or Datahold The PULL device option specifies all external pins to use the device pull up or datahold feature The default value is UP Description PULL UP places active weak pull ups on all I O pins The PULL parameter has no effect on routing or resource utilization The settings for individual pins can be changed using the PULL Pin Attribute The PULL option in the Design Manager is a local pin attribute You can change the assignment of the attribute for individual pins or all pins By default the PULL device option is set to UP and the local PULL pin attribute overrides the global PULL option n NOTE The PULL on the ispEN RESET and TOE pins are always up isoEXPERT Compiler User Manual 159 Global Device Options The values for the PULL device option are UP HOLD OFF m UP instructs the compiler to pull up high Z pins UP applies to all I O pins including dedicated and control inputs m HOLD is used to support datahold control for all I O pins excluding dedicated control inputs for the ispL SI 5000V and 8000 device families m OFFindicates no pullup and no datahold UP and HOLD are mutually exclusive Both UP and HOLD can be tu
29. m Specify a name for a GND net or cell The default name is GND Bus Reconstruction m Specify whether Array Index Order is up or down m Specify whether the left or right bit is the Least Significant Bit Ground Floating Output Pins m This check box specifies that all floating output pins are to be grounded Property File m Specify the name of the Property File containing Design Attributes that is to be read in isoEXPERT Compiler User Manual 285 EDIF Property File Syntax EDIF Property File Syntax Figure B 2 contains the syntax definition for an EDIF Property File In the definitions IDENTIFIER is any valid cell pin instance net or property name Lattice semiconductor keywords are highlighted property file PROPERTY cell def object def property def ENDPROPERTY cell def IDENTIFIER object def pin def pin array def instance def net def symbol def pin def PIN INDENTIFIER pin array def PINARRAY INDENTIFIER instance def INST IDENTIFIER net def NET IDENTIFIER symbol def SYM property def property name property name property value property name IDENTIFIER property_value IDENTIFIER MULTI ID MULTI ID IDENTIFIER MMULBII ID IDENTIEIER MULTI ID IDENTIFIER MULTI ID IDENTIFIER Figure B 2 EDIF Property File Syntax Definition Syntax Definitions One or more property statements can be used in a Property File The general syntax for a single pro
30. of fan outs per net Distribution and average number of inputs per GLB Distribution and average number of outputs per GLB Number of Registers 221 Compilation Report Post Route Design Implementation Section The Post Route Design Implementation section summarizes resource usage in the design after successfully routing The report section provides information in the sections GLB equations pin and clock assignments summary statistics and timing analysis GLB Equations The GLB equations portion of the Post Route Implementation section contains the following information GLB information for each GLB including e GLB type and GLB name e Number and names of GLB inputs e Number and names of GLB outputs e Number of used product terms PTs GLB output information for each GLB including e Number of inputs relating to each GLB output their sources and their names e Number and names of fanouts on the output of each GLB e Number of GLB levels leading to the output of each GLB e A Boolean equation for each GLB output representing the implementation inside the GLB Post Route GLBs e GLB input and GLB output locations in the order of specified inputs and outputs e Number of GLB levels for a registered GLB output related to the maximum number of GLB levels of combinatorial logic generating data input clock input and reset input of the register The GLB equations portion uses the following symbols amp Indicates
31. or 2 5V output levels while the device logic and the output current driver are powered from 3 3V Voltage is supported for the ispL Sl 5000V device family Description The VOLTAGE device allows the output driver on any I O pin to drive either 3 3V or 2 5V output levels while the device logic and the output current drive are powered from 3 3V The values for the VOLTAGE pin attribute are VCC VCCIO m VCC sets the output driver on all I O pins to 3 3 volts m VCCIO sets the output driver on all I O pins to 2 5 volts By default the global VOLTAGE Device Option is set to VCCIO The VOLTAGE local Pin Attribute assigns the VOLTAGE attribute to individual pins it overrides the global VOLTAGE option See Setting Device Voltage on page 73 isoEXPERT Compiler User Manual 161 Global Device Options Design Manager Sequence Assign gt Pin Attributes gt Voltage Move pins to the appropriate list Parameter File Syntax VOLTAGE VOCIVOCIO Command Line Syntax NA Setting Device Security The SECURITY device option influences the device security cell programming However this option does not guarantee that the security cell is set or cleared because device programmer options also affect the security cell The default value is OFF Description SECURITY ON inserts a 1 in the G field of the JEDEC file to inform the device programmer that the device is to be secured Most device programmers require that another option be set
32. reg GLB QI2 DO reg 9 00 GLB QI1 00 reg GLB QI2 DO reg 9 00 GLB QI2 QO reg GLB QI2 DO reg 4 50 CLK Em GLB OTL CLK reg 1 20 D1 in GLB QI1 D0 reg 9 60 EN in GLB QI1 D0 reg 9 60 PS in GLB OI1 DO reg 9 60 Gb fan GLB QI1 D0 reg 9 60 ET fan GLB QI1 D0 reg 9 60 ED an GLB QI1 D0 reg 9 60 GLB QI10 00 reg GLB OI1 DO reg 9 00 GLB QI1 00 reg GLB QI1 D0 reg 4 25 0 CLK irn GLB OIO CLK reg d PO fin GLB QIO DO reg 9 60 EN in GLB OIO DO reg 9 60 PS in GLB QIO DO reg 9 60 GI TE GLB QIO DO reg 9 60 CT ana GLB QIO DO reg 9 60 ED fan GLB QIO DO reg 9 60 GLB QIO QO reg GLB QIO DO reg 9 00 isoEXPERT Compiler User Manual 254 Timing Analyzer Reports Selected Path Detailed Report Example The following detailed report is generated by the Timing Analyzer when All or Maximum Number is selected in the Analysis Path Criteria area of the Timing Analysis Path Selection dialog box If longest shortest is selected the report shows the longest and shortest paths only The output is a separate detailed report file design dpt To generate the detailed report see Running the Timing Analyzer on page 178 m Ina detailed report for each longest shortest path the first column lists all the points in a path from starting point to ending point the second column is the pin to pin delay value and the third column is the partial path delay value from the starting point to the current point
33. 0 LOCK 5 9 ENDPROPERIY The first item in the array out 2 is locked to pin 5 the second item in the array out 1 is not locked to a pin and the third item in the array out 0 is locked to pin 9 You can use a delimiter without a value to indicate an array item is not assigned PROPERTY casel PINARRAY out 2 0 OPENDRAIN OFF ON ON FENDPROPERTY The first item in the array out 2 has the OPENDRAIN attribute turned off and the second and third items in the array out 1 and out 0 have the OPENDRAIN attribute turned on Use similar syntax to assign other pin array attributes isoEXPERT Compiler User Manual 296 Attribute Examples Net and Path Attributes Net and path attributes are applied to the nets in your design Path attributes identify a set of paths as Asynchronous Paths No Minimize Paths LowPower Turbo or Critical Paths The following example illustrates the use of the attribute PRESERVE and the path attributes SAP and EAP In Figure B 6 the schematic shows the nets NETP and NETA as part of a circuit Figure B 7 is part of the EDIF file for the schematic in Figure B 6 Figure B 8 is an example of a Property File specifying the PRESERVE attribute to preserve NETP forcing the net to a GLB output The Property File also specifies NETA as the start of an asynchronous path and OUT as the end of the asynchronous path preventing the compiler from duplicating GLB outputs on that path In this example correspo
34. 1 1 2 The number of macrocells 2 The total number of occupied macrocells does not include macrocells that use GND VCC logic or macrocells that use input registers for ispL SI 5000V devices or backdoor input registers for ispLSI 8000 devices m Number of Available Macrocells The number of available macrocells is the total number of macrocells in the device less the number of occupied macrocells used by the design m Number of Turbo Product Terms If the LOW POWER device option is set to OFF this line displays the number of turbo product terms used by the design If the LOW POWER device option is set to ON and there are no STP ETP path attributes in the design the number of turbo product terms is zero 0 m Number of Occupied Product Terms The number of occupied product terms line is the number of product terms per macrocell multiplied by the number of occupied macrocells plus used GLB controls if any An ispLSI 5000V device has five 5 product terms per macrocell and five GLB controls per GLB An ispL Sl 8000 device has four 4 product terms per macrocell and two GLB controls per GLB m Number of Available Product Terms The number of available product terms is the number of product terms per macrocell multiplied by the number of available macrocells An isoLSI 5000V device has five 5 product terms per macrocell An ispL Sl 8000 device has four 4 product terms per macrocell This number does not include GLB contro
35. 122 Unlocking pins 97 Updating a project 120 Use Internal Tristate IO Driver 148 USE GLOBAL_RESET 153 and resource utilization 269 User electronic signature setting 106 User Settings on Explore Matrix 101 using 296 Utilization 208 210 of Dedicated Control Inputs 210 of GLBs 198 of IOCs 210 V Variables in macros 303 Property File 288 VCC name 82 Vendor selecting for EDIF reader 81 Verilog writer files 89 VHDL GLB Function 209 VHDL writer files 89 View isoSmartFlow 107 124 menu 309 314 317 320 322 Mode Bar Physical Viewer 201 Physical Viewer 197 198 201 Process Bar 124 Session Log 124 Status Bar 124 isoEXPERT Compiler User Manual 337 Tool Bar 124 Zoom Bar 124 Zoom Bar Physical Viewer 197 Zoom functions 124 Viewing Reports See Results W Window Workspace creating 116 defined 115 Writer settings 88 Y Y1 RESET 154 Y1 AS RESET 154 Z Zoom Bar opening closing 124 Physical Viewer 197 Zoom functions 96 197 isoEXPERT Compiler User Manual Index 338
36. 311 Tool Bar Icons IspEXPERT Compiler The following table shows the ispEXPERT Compiler icons lists their names and describes their function Table 3 1 ispExpert Tool Bar Icons Open Assign Pin Locations Pin Attributes Compiler Report Pin Layout Timing Matrix Explore Matrix isoEXPERT Compiler User Manual Opens an existing text file This could be a property file a pin file a report file a design file etc Equivalent to the File gt Open menu item saves the existing text file Equivalent to the File Save menu item Opens the Pin Locations window so design ports can be assigned to device pins Equivalent to Assign Pin Locations Opens the Pin Attributes window so pull up slow slew and open drain attributes can be assigned to pins Equivalent to Assign gt Pin Attributes Runs the ispEXPERT compiler Equivalent to Tools Compile Displays the compiler report design rpt Equivalent to View Compiler Report Displays the Pin Layout window showing the pin assignments after the design is compiled Equivalent to View Pin Layout Displays the Timing Matrix Table that shows the results of the Timing Analyzer Equivalent to View Selected Paths Timing Matrix Displays the explore matrix that shows the results of each compilation requested through the Explore tool Equivalent to View Explore Matrix Displays the Print dialog box to allow printing of th
37. 50 CLK CI AU CLK C2 2 0 Shortest Paths Source Destination Path Delay ns CLK Ci 20 CLK or 20 Q2 OUT 50 INZ pi 40 IN3 Da 50 INS OUT2 80 The example in Figure 5 7 is a very simple design however in a more complex design loops may exist If loops exist in a design all related loops are broken and the path delay calculation is done GLB Boundary Calculation The path delay of any signal that traverses from the primary input to the primary output of the device can be categorized into routing and logic delays The routing delay could be either GRP or GRP ORP Bypass and the logic delay is attributed to the delay in the GLB s Any given signal can have one or more GLBs in its path with GRP delays between each GLB Figure 5 8 shows a boundary calculation example GRP GLB Figure 5 8 Boundary Calculation Example OUTO GRP ORP GRP GLB isoEXPERT Compiler User Manual 177 isoOEXPERT Timing Analyzer ISDEXPERT Timing Analyzer The ispEXPERT Timing Analyzer performs the following functions Determines maximum frequency for clocking a design containing two or more flip flops and or latches It also lists the clock periods between all the internal register pairs and the frequencies along with the names of the signals that drive the clock inputs of those registers The frequency is provided only for those sets of registers that are driven by the same reference clock otherwise the field is left blank The c
38. 6 13 GLB Resources Dialog Box isoEXPERT Compiler User Manual 207 Obtaining Additional Information Utilization Shows the used and available resources of the selected GLB Figure 6 14 This information is only available for GLBs used in the design implementation You can also open the dialog box to this tab by selecting Design Usage from the right click pop up menu AT GLB Information Resources Utilization Internals Function Uzed Available Inputs from GAP Dedicated Inputs Of 03 M acracells 4 4 100 Combinational Registered Product Terme 14 20 70 Figure 6 14 GLB Utilization Dialog Box Internals Provides a pictorial description of the selected GLB Figure 6 15 It shows all the output pins of the GLB The output pins that are used as feedbacks have a circle inside The output pins that are registers have an X You can also open the dialog box to this tab by selecting Internals from the right click pop up menu A1 GLB Information Figure 6 15 GLB Internals Dialog Box isoEXPERT Compiler User Manual 208 Obtaining Aaditional Information m Function Shows the logic function equations for the GLB Figure 6 16 You can select either VHDL or Equation format as the HDL format The Equation format is Boolean similar to that in the Compiler report file You can also open the dialog box to this tab by selecting Function from the right click pop up menu The default HDL format is based on your
39. A significant amount of logic exists between the register and the tristate driver e Input sharing exists between functions e The function of the register is large more than 4 PTs and or wide total inputs is more than 44 e Pin locking is required that does not conform to the tristate bus architecture isoEXPERT Compiler User Manual 282 Appendix B EDIF Property File An EDIF Property File is used by the Lattice Semiconductor EDIF Reader to annotate Design Attributes to EDIF ports cells instances and nets You can use this file to control how the compiler utilizes the devices resources The attributes do not change the logic behavior of the design This appendix covers the following topics m Scope and Precedence Rules m EDIF Property File Syntax m Design Attributes m Attribute Examples isoEXPERT Compiler User Manual 283 Scope and Precedence Rules Scope and Precedence Rules If a design is implemented using Verilog or VHDL and the synthesized EDIF file does not contain Design Attributes a Property File can be used to add Design Attributes to control how the design is implemented into the logic resources of the target device If a design already contains Design Attributes such as those captured using schematic tools a Property File can be used to add to overwrite or modify the Design Attributes in the design An EDIF Property File is used by the Lattice EDIF reader only Any attributes in an EDIF file using prop
40. A2 IN2 Z20 GLB A2 POJAS GLB A2 PO Z0 GLB A2 PO xa A0 GLB A2 PO xa Z0 GER 2 XOU AT GLB A2 X30770 GRP COX iomux AO0 GRP COX iomux Z0 TOC 103 OBUFI AO IOC 103 OBUFI Z0 LOC 0 20 TOC OG XO0 data arrival time SeecupeOine CL uno pore Endpoint CO output port Point Name pin_name type IOC IO28 IBUFO XIO IOC 1028 IBUFO Z0 GRP CIX grp AO GRP CIX grp Z0 GLB A2 IN8 AO0 GLB A2 IN8 Z20 GLB A2 PO A2 GEB A2 P0720 GLB A2 PO xa A0 GLB A2 PO xa Z0 GLB 22 X30 AT GLB AZ x30 20 GRP COX iomux AO0 GRP COX iomux Z0 IOC 103 OBUFI AO TOC 103 OBUFI Z0 IOC CO A0O LOC EO XO0 data arrival time St rtpoint GLB QI0 00 edge triggered flip flop Endpoint CO output port Porxnc Name pin name type GLB QIO QO reg GRE O10 Ffb 240 GRP QIO ffb Z0 60 00 2 00 s HO OO 10 00 00 00 60 00 zd UO 30 00 30 2 C On OR C CO ON C L2 C5 5 C9 ODD O KO XO OY OY OY OW A BS I IND Sp gp RE RR CIS X OT Co isoEXPERT Compiler User Manual Timing Analyzer Reports 256 GLB A2 IN16 A0 GLB A2 IN16 Z0 GLB A2 P0O AO GLB A2 PO0O Z0 GLB A2 PO xa A0 GLB A2 PO xa Z0 GLB A2 X30 A1 GLB AZ X30 20 GRP COX iomux AO0 GRP COX iomux Z0 IOC 103 OBUFI AO IOC 103 OBUFI Z0 TOC EG AO LOC CO7 XO0 data arrival time 0 00 0 70 0 10 0 90 0 00 O60 dos d 1 4590 0 00 Le 90 2500 2890 0 00 53 90 0 60 4 50 0 00 4 50 dcs LO 54 60 0 00 24990 0 50 03 L0 0 00 bul 2 30 8 40 8 40 is
41. ANDing of signals indicates ORing of PTs indicates negation NOT at the input of a GLB means the XOR gate is hardwired in the GLB D indicates the D input of a flip flop C indicates the clock input of a flip flop CE indicates the clock enable of a flip flop PR indicates PT preset of the flip flop inside a GLB R indicates PT reset of the flip flop inside a GLB T indicates a T flip flop Names beginning with an underscore usually indicate an internal name for a net isoEXPERT Compiler User Manual 222 Compilation Report Any parenthesized terms in GLB equations represent an implementation through a PT sharing array GLB inputs may be represented as a parenthesized triplet of names The first entry represents the source of the signal the second entry is the signal name and the last entry is post route input location GLB outputs may be represented as a parenthesized pair of names The first entry is the signal name and the second entry is post route location The following dot extensions are used after GLB IOC or DI names to refer to specific input or output connections On or On where n 0 3 represents the specific GLB output as signal source O represents the IOC DI as signal source OE represents the specific GLB enable output as signal source m or Im where m 0 17 or m 0 23 represents the specific GLB input as signal destination IR represents connection to the IOG thr
42. Compiler User Manual 120 Using a Text File Using a Text File If you want to create open edit save search through or print a text file use the File menu to open the file and the Edit menu to access the ISpEXPERT text editor A CAUTION Do not edit internal project text files You may lose data Design changes should be made to the source design that was used during project creation Creating a Text File To create a text file using the ISDEXPERT text editor 1 Select File New from the Design Manager A standard text file window appears Figure 3 31 2 Type in your file contents Use the Edit menu pull down options to change the text The Edit menu contains the following functions Undo Cut Copy Paste Delete Clear Messages Find and Replace BP CHT4 par igpLSI2032 180LT48 OH OFF OF OH OFF Figure 3 31 Text Editor Window Saving a Text File To save a text file 1 Select File Save As from the Design Manager The Save As dialog box appears 2 Select or enter the file name and path information 3 Click OK The text file is named and saved to the specified directory Opening a Text File To open an existing text file 1 Select File Open from the Design Manager The Open dialog box appears 2 Select the file name and path information 3 Click OK The text file opens isoEXPERT Compiler User Manual 121 Using a Text File Editing a Text File To edit an open text file Select Edit gt
43. Design Manager or from locking statements in the source file Default is OFF Ignore Reserved Pins Instructs the compiler to ignore any reserved pins when making pin assignments Default is OFF Max GLB Inputs opecifies the maximum number of GLB inputs the compiler is allowed to use for each GLB Ranges and defaults are device dependent Max GLB Outputs opecifies the maximum number of GLB outputs the compiler is allowed to use for each GLB Ranges and defaults are device dependent Minimize GLB Levels for All Paths Instructs the compiler to reduce the GLB levels on all paths rather than only the longest paths Advanced Setting Perform Timing Analysis Runs Timing Analysis during the compilation step and generates the Frequency Setup and Hold Tpd and Tco reports Default is OFF Preserve XOR opecifies all user defined XOR gates on primary output nodes are to be preserved in isoLSI 5000V and 8000 devices isoEXPERT Compiler User Manual 86 Compiler Control Options Table 3 1 Compiler Control Options Continued Option scription 0 single PT Function Packing For Specifies how functions are mapped to PTs in Routability ispLSI 8000 devices Advanced Setting Strategy Area Delay Allows you to specify one of three No Logic Optimization optimization strategies AREA DELAY or NO OPTIMIZATION Default is DELAY Use Extended Routing Instructs the router to use a complete routing cycle in an attempt to route a de
44. Detailed Report Example on page 255 for an example This selection also creates a summary report 6192 Report design mpt lists the delays between all module I Os when the device in the design is in the ispLSI 6000 family See 6192 Report on page 261 for an example You can access each of the timing reports from the Results menu The reports are displayed in table format in the Timing Explorer To access timing reports select Results Clock Frequency Table to view the design mfr file as a Timing Explorer table Select Results gt Setup and Hold Table to view the design tsu file as a Timing Explorer table Select Results Tco Table to view the design tco file as a Timing Explorer tablet isoEXPERT Compiler User Manual 181 isoEXPERT Timing Analyzer Select Results Tpd Table to view the design tpd file as a Timing Explorer table Select Results Timing Reports gt Selected Path Summary to view the design spt file select Results Timing Reports Selected Path Detailed to view the design dpt file Select Results gt Timing Reports gt Selected Path Boundary to view the design gpt file Select Results gt Timing Reports gt 6192 to view the design mpt file If the Clock Frequency Report or the Setup and Hold Report is not present or if the Compiler Control settings changed since the report was generated the Timing Analyzer is rerun to obtain the latest report when you request report results You can a
45. File Print Displays the Find Object dialog box so you can search Equivalent to the Locate command in a pop up list Displays the About Physical Viewer dialog box showing the Physical Viewer version number Activates context sensitive help Equivalent to pressing F1 when the item is active Displays fan ins in the Connectivity window Equivalent to View gt Fan In Mode Displays fan outs in the Connectivity window Equivalent to View gt Fan In Mode Displays paths in the Connectivity window Equivalent to View Path Mode Displays timing paths in the Connectivity window Equivalent to View Timing Path Mode 318 Physical Viewer Table 3 3 Physical Viewer Tool Bar Icons os Wome mem Observable Nodes Displays ispANALYZER observable nodes in the Connectivity window Equivalent to View gt Analyzer Mode Zoom In Enlarges the device diagram in the Connectivity window Equivalent to View Zoom In Zoom Default Changes the size of the device diagram in the Connectivity window to the default zoom setting Equivalent to View Zoom Default Zoom Out Reduces the size of the device diagram in the Connectivity window Equivalent to View Zoom Out Zoom to Fit Changes the size of the device diagram so it fits in the Connectivity window Equivalent to View Zoom to Fit Zoom Area Enlarges a selection of the device diagram to fit into the Connectivity window Equivalent to View Zoom Area
46. IN3 FF2 IN3 FFI GLK GER IN1 IN2 LOZ Ol Destination OUTS OUTS OUTA OUTI FF2 FF2 FF2 EEL FEL FFI isoEXPERT Compiler User Manual DZ SD C2 e za P 1 5 Timing Analysis Overview Longest and Shortest Path Example Figure 5 7 is an example of a small design All the design objects are pin port net and instance Each instance has input pins and output pins Each net has a source node and destination node s For the example in Figure 5 7 the following information is assumed The longest path and the shortest path delay from IN1 to D1 are both 100 The longest path and the shortest path delay from IN2 to D1 are both 40 The longest and the shortest path delay from CLK to C1 are both 20 The longest and the shortest path delay from CLK to C2 are both 20 The longest and the shortest path delay from IN3 to D2 are both 50 The longest and the shortest path delay from Q1 to D2 are both 90 The longest and the shortest path delay from Q2 to OUT1 are both 30 The longest and the shortest path delay from IN3 to OUT2 are both 80 IN3 OUT FF2 IN Q1 combinatorial D2 ia lineal OUT1 IN2 CLK Fcombnatora Figure 5 7 Path Analysis Example isoEXPERT Compiler User Manual 176 Timing Analysis Overview For the previous example the timing analysis results would be the following Longest Paths Source Destination Path Delay ns INL D 100 epl D2 90 IN3 OUT 80 OZ OUT
47. Information appears in HDL format in the Path Tracer window the GLB Information Function dialog box and the GLB Pin Information Function dialog box In the Handling Timing and ispANALYZER Requests area you can select whether you want timing and isoANALYZER information displayed in a new window or in the active window When you specify a new window a new Connectivity window opens that contains the new timing or ispANALYZER information Check the Windows pull down to access additional Connectivity windows You can also use the check box to turn on and off the display of text in the Connectivity View When text is on the names of the GLBs IOGs and Dedicated Control Inputs are displayed in the Connectivity window These are more clearly visible when the device diagram is enlarged If the device diagram is very small this information is automatically turned off even when the check box is checked This information is in addition to the tip bubble that displays when you move your cursor over a node Customize Colore Other Options HDL Format Equation Handling Timing and ip NALYAER Requests Create a new window and display requests there C Display requests in the active window v Display Test in Connectivity Views tJ Default OF Cancel Apply Help Figure 6 6 Customize Dialog Box Other Options isoEXPERT Compiler User Manual 200 Connectivity Window Display Modes as You can select the d
48. Locations window to see the physical pin numbers that are available for locking Lock pins using either the Constraint Manager or the Assign Pin Locations window isoEXPERT Compiler User Manual 77 Chapter3 The Design Manager The ispEXPERT Design Manager provides a graphical interface that lets you read in EDIF and PLA design files set compiler control options assign pins and pin attributes compile the project perform timing analysis and generate netlists for functional and timing simulation The ispEXPERT Design Manager is project oriented Each project contains a design source file It may also include a property file parameter file or pin file The project also includes the settings for pin assignments and attributes device options and Compiler Control Options When you run the compiler timing analyzer and ISPDANALYZER the files and reports from these tools are included in the project directory You can generate netlists in a variety of formats These can be generated when the project is compiled or can be generated after compilation is performed This chapter contains the following sections Creating a New Project Opening a Project Compiler Control Options Using the Interfaces Menu opecifying a Device and Device Options Setting Pin Attributes Design Exploration Naming and Saving Design Settings Setting the User Electronic Signature Compiling Your Design Viewing the Pin Layout Changing the Pin Assignment Viewing
49. Output Ori gt Inputs PSX SINS6S 4 Fanout s GLH 15y ALDOL TS 2 Product Term s 2 GLB Level s CD O11 EDX a1509 116 OLR QT1 D QI1 amp CDX amp LDX amp 5 SIN365 QIl C CLKX PSX FLL CD Ou DX glb02 03 ie isoEXPERT Compiler User Manual GD SO Compilation Report 226 Compilation Report Module Section The module information section of the report is available when an ispL Sl 6000 device is used A sample of the module information follows Hardmacro Instances Instance Name Hardmacro Name amp 1131 XOR8 Module Memory and Register Counter Configurations Memory Module Configuration JANS ELERO B puo D Almost RBmpbys LI Almost Full 4 50 MEM mod0 FIFO4S07 EZ Lp EEGs EINING SLIZ S17 60 Ay AO LILO rOy amp LI22 SLL OO AL Lir CG LDO3 O72 GIA 2 225 Ake EB cO 00 gt 41122 SIT 1166 70 AT TON SCG LbpoT us 1122 SIT POG Al ATLSI5 4 g5502 005 GLITZ 2 SILT 66475 AL eke GLO L OG SLIT All LB Ol le ZN BLE gipU0 00 MOUTSX Al Lode EIFONRLITE O FIFOWRIIEX Al 13 FIFORESET OM FIFORESETX AAORE FIFOREAD OM FIFOREADX AXWL L5 OUUtDutis 41123 ADOO ADOS 161123 ADOL 20010 amp 1I23_ADO2 ADO11 amp 1123 ADO3 ADO12 amp 1123 ADO4 ADO13 amp 1123 ADO5 ADOIA amp 1123 ADO6 ADO15 amp 1123 ADO7 ADO16 amp 1123 ADO8 ADO17 Cleo BP B 61123 AN CG Oot EB By amp 1123 ALE ALE CONLTOL R
50. PIN Pin Attribute prevents package pins from being assigned during the compiler s pin locking process Synopsys The syntax for a PLA design file is PLSI PROPERIY RESERVE PIN pin number To reserve multiple pins in a PLA file you must include a separate PLSI PROPERTY statement for each pin The syntax for an EDIF Property File is PROPERTY cell name SYM RESERVE PIN pin number s ENDPROPERTY In an EDIF Property File RESERVE PIN must be specified at the top level source Refer to Syntax Definitions on page 286 for the definition of the cell name variable and for information on entering multiple pin numbers in an EDIF Property File Description During design entry you can reserve input output bidirectional and dedicated input pins in a PLA design file or in an EDIF Property File Clock OE programming and system pins cannot be reserved Because RESERVE PIN is assigned to physical not logical package pins it cannot be specified in a schematic design You must output your schematic to an EDIF file and use an EDIF Property File to specify the RESERVE PIN attribute Or you can reserve pins by using the Pin Attribute dialog box in the Design Manager You can reserve multiple pins during compilation However reserved pins severely constrain the compiler and your design may not route if you reserve too many pins Also do not set RESERVE PIN and LOCK attributes on the same pin The compiler cannot lock a package pin that ha
51. RESET ON The Y1 RESET pin is the Y1 clock input if Y1 AS RESET OFF This option applies only to ispL Sl 1016 E ispLSI 2032 E V VE 44 48 and 49 pin and ispLSI 2064V VE 44 pin devices and is ignored for all other devices You cannot lock a signal to the Y1 RESET input pin If Y1 AS RESET ON the Global Reset signal is automatically connected to the Y1 RESET pin and you will get an error if you try to lock a signal to this pin isoEXPERT Compiler User Manual 154 Global Device Options If Y1 AS RESET is set to OFF in ispLSI 1016 E 2032 E V VE 44 48 and 49 pin and 2064V VE 44 pin devices registers cannot be globally reset Specify any required reset signal as PT reset Design Manager Sequence Assign Device Select Y1 AS RESET Parameter File Syntax Yl AS RESET ON OFF Command Line Syntax NA isoEXPERT Compiler User Manual 155 Global Device Options Preserving XOR Gates The XOR Device Option preserves user defined XOR gates on primary output nodes during the logic optimization process for isoLSI5000V and 8000 designs This global option works in conjunction with the local XOR design attribute see Preserving XOR Gates on page 43 for more information Description During logic optimization the compiler expands all XOR gates in your design This XOR expansion enables the compiler to determine and remove unnecessary logic in the design The global XOR compiler option and the local XOR net att
52. Semiconductor Timing Libraries The output netlists include the following industry standard third party and Lattice Semiconductor formats EDIF EDIF format netlist and timing information for use with any EDIF compatible timing simulator SDF Standard Delay Format SDF for use with any OVI Open Verilog International compliant Verilog timing simulator LMC LMC format for board level simulation with Synopsys Logic Modeling Division models SIM SIM format netlist for timing analysis with the ispEXPERT Timing Analyzer default automatically created Verilog Verilog format netlist for use with any OVI compliant Verilog simulator VHDL VHDL format netlist for use with any VITAL compliant VHDL simulator Files are generated in VITAL non VITAL maximum delay and non VITAL minimum delay formats Viewlogic Viewlogic EDIF and wir timing format netlist for use with any Viewlogic simulator For the file extensions for these types of output netlist files refer to page 25 EDIF Verilog and VHDL netlist format files can also be generated using the Design Manager after a successful compilation See Netlist Output Files on page 88 for complete details on how to generate these output files isoEXPERT Compiler User Manual 22 ispEXPERT Output Fuse Map Generation Once the design routes the fuse map generation process reads the routed design information converts the physical layout of the design into device pr
53. The source files parameter pin or text are retained as are the pin locking statements all the Compiler Control Option settings and the Pin Design Attributes All other files are deleted A CAUTION If you use the Project Clean command the compiler output files will be deleted such as compiler log and compiler report files However the project setting files are retained You can select the setting files and rerun the compiler to obtain required results When you select Project Close from the Design Manager all your work up to that point is saved to the project directory The project closes You can delete a project only by deleting the entire directory isoEXPERT Compiler User Manual 119 Updating a Project Updating a Project The most common reason for updating a project is that the source design logic including attributes that affect compiler implementation has changed To update the current project select Project Update to display the Update Project dialog box The dialog box gives you the option of retaining the project settings If you are making changes to logic you will probably maintain the project settings If you retain the settings the project settings are saved internally and the current settings are applied after the new design file is read into the project You will be warned of any inconsistencies such as design pin name changes You may not want to retain the project settings if pin names or
54. a string in the Pin Name field For example type the letter A in the Pin Name field Only unassigned pins that begin with the letter A will appear in the list Likewise if you deselect output and bidirectional only the input pins beginning with A will appear in the unassigned list Select a pin from the Unassigned Pins list The pin is highlighted You can also use the space bar or the arrow keys to move around the list On the package view double click on the device pin to which you wish to lock the highlighted pin The pin changes to light blue for inputs bright yellow for outputs and pink for bidirectional pins the defaults Check the Status Bar for successful messages If you click on a pin in the Assigned Pins list the pin is highlighted in the package view isoEXPERT Compiler User Manual 96 Locking the Pins TIP You can assign pins by highlighting the pin name in the unassigned column Hold down the mouse button and drag the cursor to the pin in the layout When the pin tip displays release the mouse If you hold the Ctrl key down you can drag pin assignments from one device pin to another If you attempt to drag a port to a pin that is already assigned a warning dialog box will ask you to confirm the action Press Shift then click with the left mouse button to lock a pin The cursor changes to a plus sign when you make an allowable or legal assignment To see pin tips Press and hold the mouse on a
55. and device pins to restrict the displayed data m he Observable Node Router routes the observed internal node to the selected unused pin and updates the post route netlist and the design report m he Fuse Map and Timing Model Generator generates the fuse map JEDEC SIM and report files based on the updated post route netlist isoEXPERT Compiler User Manual 19 isoEXPERT Functions Observability Analyzer Identify internal nodes and unused pins Node Selector Select observed internal nodes Observable Node Router Route observable node to selected unused pin Fuse Map and Timing Model Generator Report generation Figure 1 3 isoANALYZER Design Flow Physical Viewer The Physical Viewer shows the design implementation details for a compiled project It shows how the design logic is implemented in the device using the GLB IOC and DI logic resources It also shows how data is being propagated between the logic resources by displaying point to point routing information at the GLB level Timing Analysis The ispEXPERT Timing Analyzer isp TA performs the following functions m Determines maximum frequency for clocking a design containing two or more flip flops and or latches It also lists the clock periods between all the internal register pairs and the frequencies along with the names of the signals that drive the clock inputs of those registers The frequency is provided only for those sets of registers that are driven by the
56. and 8000 Devices ispLSI 8000 Tristate Usage The ispEXPERT Compiler software supports the use of tristate buses in ispL Sl 8000 devices If you use a tristate bus in an ispLSI 8000 design the compiler will not be able to complete placement of user specified logic into one Big Fast Megablock e If you are using a tristate bus do not use the BFM net attribute e If you are using a tristate bus ECP cannot place logic into one BFM However the critical path function of ECP is still honored e f you are using a tristate bus ETP cannot place logic into one BFM However the turbo and critical path functions of ETP are still honored Support of the IOC driver for an internal tristate bus is provided This allows the external bus to extend to the on chip bus However using a tristate bus may constrain the router Buffers are inserted if PT resource and or GLB inputs are not sufficient to accommodate all the functions entirely A bus is divided into groups if the width of the bus exceeds 18 bits For example a 32 bit bus is divided into 18 bits and 14 bits and mapped to different regions The following are reasons to implement logic in an internal tristate bus e No logic exists between the register and the tristate driver e he function fan in cone of the register is small 4 PTs or less and narrow total inputs is less than 44 e Tristate outputs are not pin locked The following are reasons to implement logic in a mux e
57. at the top level source isoEXPERT Compiler User Manual 293 Attribute Examples Attribute Examples The following sections contain examples of how to use Property Files for pin attributes net and path attributes symbol block attributes parameterized attributes and attributes with multiple values Each example is representative of logic from a larger design and includes a schematic to clarify the use of the attributes Pin Attributes Pin attributes are applied to external pins in your design The example below illustrates the use of the LOCK attribute In Figure B 3 the schematic shows a flip flop with CLEAR and CLOCK inputs to the instance Figure B 4 is part of the EDIF file representing the schematic for DESIGN A Figure B 5 shows a Property File locking the CLOCK signal to pin 25 and the CLEAR signal to pin 42 DOUT is assigned the CRIT attribute to instruct the compiler to use the ORP bypass In this example corresponding cell and object identifiers are highlighted in the EDIF file and the Property File D D Q DOUT CLOCK gt CLEAR gt Figure B 3 DESIGN_A Schematic isoEXPERT Compiler User Manual 294 Attribute Examples cell rename DESIGN A 1 DESIGN A celllype GENERIC view view 1 viewType NETLIST interface port DOUT direction OUTPUT port CLOCK direction INPUT port CLEAR direction INPUT Figure B 4 EDIF File for DESIGN A PROPERTY DESIGN A PIN CLOCK LOCK 25 ENDPROPERTY PROPE
58. clearing messages 123 opening closing 124 Settings EDIF reader 81 retaining 120 saving from Explore Matrix 103 saving project 105 Setup and Hold Report 181 250 Setup and Hold Table Results menu 181 Setup path evaluation 172 Shape of pins changing 125 Signal Navigator 183 pop up menus from 184 Signals GND 82 VCC 82 Signature user electronic setting 106 Simulation guidelines 275 Single PT Funciton Packing for Routability 146 SLOWCLK 37 SLOWSLEW 33 73 92 161 290 SLP ELP 33 53 292 and resource utilization 270 SNP ENP 33 56 292 and resource utilization 270 Specification errors attribute and option names 268 duplicate names 268 keywords 268 Speed 157 Speed device 90 114 Speed optimization 277 Statistics Design 212 Device 212 Status Bar opening closing 124 Index STP ETP 33 54 292 and resource utilization 270 STRATEGY 132 and resource utilization 270 and speed optimization 277 string replacing 122 searching for 122 Summary Report 181 SYM 288 Symbol Attributes 33 58 299 LXOR2 58 OPTIMIZE 59 293 PROTECT 61 293 REGTYPE 62 293 RESERVE_PIN 69 293 syntax dpm 165 edif2laf 284 307 errors 266 Property File 286 timing analyzer 189 Syntax rules Property File 288 synthesis 18 System errors 266 T Tco calculation 174 report 181 251 table 181 Tco Table Results menu 181 Text file creating 121 editing 122 opening 121 pin assignment 96 printing 123 replacing a string 122 saving 1
59. designs REGTYPE REGTYPE restricts the placement of registers by specifying where to place a particular register either inside a GLB or inside an IOC USE GLOBAL RESET ON can improve routability of your design if all your registers and IOC latches are driven by a direct no logic reset signal LXOR2 The LXOR2 attribute restricts optimization of your design Remove unnecessary LXOR2 attributes to increase resource utilization XOR The XOR attribute has no effect on routing or utilization LOWPOWER The LOWPOWER compiler option has no effect on routing or utilization PULL The PULL pin attribute has no effect on routing or utilization SECURITY The SECURITY pin attribute has no effect on routing or utilization SLOWSLEW The SLOWSLEW pin attribute has no effect on routing or utilization USE GLOBAL RESET isoEXPERT Compiler User Manual 273 Improving Routability Table A 1 Design Attributes and Compiler Control Options Continued Design Attribute or Compiler Control How to Improve Routability and Option Device Resource Utilization OPENDRAIN The OPENDRAIN pin attribute has no effect on routing or utilization OUTDELAY The OUTDELAY pin attribute has no effect on routing or utilization VOLTAGE The VOLTAGE pin attribute has no effect on routing or utilization isoEXPERT Compiler User Manual 274 Design Simulation Design Simulation Lattice Semiconductor recommends that you simulate your design before and af
60. honor the design rule constraint and a warning message appears The effects of each attribute on implementation of the design device resource utilization and routing are described in Appendix A Design Rules and Tips Compiler Control Options Compiler Control Options define global objectives for the design implementation process These options control usage of device resources for making trade offs in achieving a desired level of balance among possibly conflicting objectives such as minimum delay maximum device resource utilization and device routability Design Attributes are honored when they do not conflict within Compiler Control Options and design rules Compiler Control Options determine how much flexibility the compiler has when implementing your design into the selected Lattice Semiconductor device The Compiler Control Options specify synthesis strategy partition and routing strategy output netlist format and more Compiler Control Options are described in detail in Chapter 4 Design Compilation Options The effects of each control option on routing device resource utilization and compiler efficiency are described in Appendix A Design Rules and Tips Design Rules Design rules are by products of a systematic and automatic design implementation as well as specifics of device architecture They identify conflicting Design Attributes and Compiler Control Options These rules have highest priority when ispEXPERT is
61. icon The Status Bar shows the number of Explore runs that have completed and the number that remain isoEXPERT Compiler User Manual 100 Design Exploration To examine the Explore Matrix results 1 Select Results Explore Matrix or the Explore Matrix icon from the Design Manager The Explore Matrix appears Figure 3 15 and Figure 3 16 The device name displays above the User Settings EE UU Ueo UE IL 1111 T heziz Effort Max Use Global Extended eem tovet_ ctom ctn out Reset moute rime Limit AREA Medium 15 4 Yes wa NoLimit AREA Medium 15 4 ves ma NoLimit AREA Medium 15 2 ves Wa NoLimit AREA Medium 15 2 ves wa NoLimit AREA Medium 8 4 ves mia NoLimit AREA Medium 8 4 ves ma NoLimit AREA medium 8 2 ves ma NoLimit AREA medium 8 2 ves ma NoLimit LB F2 r2 Fa F PR PR Fa E DELAY Medium 8 4 ves twa NoLimit Yes NIA Yes NIA Ix DELAY Medium 8 DELAY Medium 8 User Settings User Settings O OO Ignore Reserved Preserve Minimize Use Internal BFM Single PT NIA N A NIA NIA N A N A OMA NIA BIA Figure 3 15 Explore Matrix User Settings isoEXPERT Compiler User Manual 101 Design Exploration Compiler Results pir Rest Humber of Humber Humber of Maz GLE Max Successful Successful 8 2 mA 2 100MHz Successful Su
62. intended device you have the following four options Choose a larger device Reduce your design size remove some logic Optimize your design for device resource utilization Relax design constraints Optimizing for Resource Utilization The primary Compiler Control Options and Design Attributes that affect logic density and hence device area utilization are CRIT EFFORT LOCK RESERVE PIN LXOR2 MAX GLB IN MAX GLB OUT PRESERVE PROTECT SAP EAP SCP ECP SLP ELP SNP ENP and STP ETP STRATEGY If your primary consideration is placing the largest amount of logic into a particular device do the following Remove all PRESERVE attributes to allow the compiler to optimize your design better Use the USE GLOBAL RESET control option to allow the compiler to use the global reset pin instead of an I O pin not valid on ispLSI 5000V and 8000 devices Remove all CRIT attributes to allow the compiler to use the Output Routing Pool not valid on ispL Sl 5000V and 8000 devices Try different levels of EFFORT Remove all pin specifications LOCK to allow the compiler to choose pin locations Remove reserved pins or set the Compiler Control Option to Ignore Reserved Pins to allow the compiler to use all the package pins Remove all LXOR2 attributes to allow the compiler to decide on XOR usage when appropriate isoEXPERT Compiler User Manual 269 Improving Routability 8 Increase MAX GLB IN to allow the compiler to us
63. ispLSI part used for the design implementation You can use the Tools Design Navigator menu item or the Toggle Design Navigator icon to control whether the Design Navigator window displays The following information is available in the Design Navigator window m User Design name e Design instances and the device instance they were mapped to e External signals e Signal names that correspond to GLB input and output pins m Part device name e Device GLBs IOCs Dedicated Control Inputs and modules e GLB input and output pins Se Vesign Tree E User Design CNT4 Functional Blocks Fe glbO1 GLB A1 FH input output 1N365 F 1N419 F gI3IPIN E glbO0 parti GLB E gbO0 part GLB o E External Signals l Part ispLS12032 180LT 46 4 GLBs IOCs 4 D edicated Cantral lp Figure 6 2 Design Navigator Window isoEXPERT Compiler User Manual 194 Design Navigator Window The Design Navigator shows all pins in the design You can determine the GLB input pins that are used in the Design Navigator GLB input pins do not show in the Connectivity view When you are in the Design Navigator you can highlight any node except an input pin and select the Go to Connectivity View command from the right click pop up menu The node you highlighted in the Design Navigator will be highlighted in the Connectivity window By double clicking on a node you can display properties on any GLBs GLB output
64. modifying its name Use SAP EAP to prevent duplication of a particular net isoEXPERT Compiler User Manual 275 Improving a Working Design Improving a Working Design This section provides guidelines for making changes to a design that has already been compiled successfully Even minor changes can produce a very different layout after recompiling Therefore you need to understand the implications of your changes especially if your original design was difficult to compile The following guidelines are recommended m Make a copy of your working design before experimenting with changes If you recompile a working design without making changes it will have the same physical layout as before m Do not try to keep all pin assignments Locking the assigned pin numbers before recompiling severely restricts the compiler and may cause your design to be unroutable Assigning only a few pins provides a guideline for the compiler and depending on the amount of changes you made results in a very similar layout m Restrict the number of reserved pins Reserving pins severely restricts the compiler and may cause your design to be unroutabable m Usethe PRESERVE attribute with caution Removing PRESERVE restrictions can free some device resources but can also produce a very different layout m Apply the CRIT attribute carefully Since only two of the four outputs of a GLB in the ispLSI 1000 and ispL Sl 3000 device families can have CRIT attribute
65. netlist output formats before you compile since they may not be automatically generated The LMC format can only be generated by compiling the design The other outputs can also be generated using the Interfaces menu See Netlist Output Files on page 88 nterfaces I EDIF netlist E T M LME Cancel VHDL netlist Verilog netlist Figure 3 6 Interfaces Dialog Box 4 Click OK in the Interfaces dialog box The Interfaces dialog box closes 5 Click OK in the Compiler Settings dialog box to make the changes and close the dialog box isoEXPERT Compiler User Manual 85 Compiler Control Options Table 3 1 summarizes the Compiler Control Options Refer to Chapter 4 Design Compilation Options for additional information Table 3 1 Compiler Control Options Opkn scription Controls the number of GLBs placed in a single BFM in ispLSI 8000 devices Advanced Setting BFM Packing for Routability Carry Pin Direction Maintains user specified pin direction in any simulation output Default is OFF Case Sensitive Enables the compiler to treat identifiers such as pin names and net names as case sensitive or case insensitive Default is OFF Effort Low Medium High Provides different optimization options The larger the value the longer the runtime Default value is Medium Free All Pin Locks Instructs the compiler to ignore the pin locking attributes in your design whether they were locked with the
66. of Lattice Semiconductor Corporation E CMOS GAL ispGAL ispLSI Lattice Semiconductor Lattice Semiconductor Corp Lattice designs pDS pLSI Silicon Forest and UltraMOS are registered trademarks of Lattice Semiconductor Corporation Microsoft Windows is a registered trademark of Microsoft Corporation MS DOS is a trademark of Microsoft Corporation IBM is a registered trademark of International Business Machines Corporation UNIX is a trademark of UNIX Systems Labs Inc Sun 4 Sun Workstation SPARGstation and OpenWindows are registered trademarks of Sun Microsystems Hewlett Packard HP is a registered trademark of Hewlett Packard Inc APOLLO HP UX HP VUE Series 400 and Series 700 are trademarks of Hewlett Packard Inc Lattice Semiconductor Corporation 5555 NE Moore Court Hillsboro OR 97124 503 268 8000 January 2000 isoEXPERT Compiler User Manual 2 Limited Warranty Lattice Semiconductor Corporation warrants the original purchaser that the Lattice semiconductor software shall be free from defects in material and workmanship for a period of ninety days from the date of purchase If a defect covered by this limited warranty occurs during this 90 day warranty period Lattice Semiconductor will repair or replace the component part at its option free of charge This limited warranty does not apply if the defects have been caused by negligence accident unreasonable or unintended use modification or any causes n
67. of Macrocells for BackDoor Input For ispLSI 8000 devices only This line indicates the number of macrocells used by the design as backdoor input registers to a GLB Number of Occupied Macrocells The number of occupied macrocells line is the number of macrocells used by the design as resources including Product Term Sharing Array PTSA Because the PTSA may use adjacent cells N 3 to N 3 the number of occupied macrocells may be equal to or greater than the number of macrocells shown in line 1 of the section Example 1 A single GLB Design Output B partd B part0 A amp C E amp F Output G G D amp F C amp D Product term A amp C E amp F occupies one 1 macrocell In this example product term D amp F C amp D occupies two 2 macrocells because D amp F 1 and C amp D 1 are from two different macrocells The resulting PTSA uses two 2 macrocells Therefore the number of occupied macrocells 2 1 1 12 3 The number of macrocells 2 isoEXPERT Compiler User Manual 239 Compilation Report for the ispLSI 5000V 8000 Devices Example 2 Another single GLB Design output B parto B part0 A amp C 4 E amp F OL DL G G D amp F C amp D Product term A amp C E amp F occupies one 1 macrocell In this example product term D amp F 4 C amp D occupies one 1 macrocell because D amp F C amp D 1 use one PTSA which does not use adjacent cells Therefore the number of occupied macrocells
68. opens in default mode it shows the Design Navigator window on the left side of the screen and the Connectivity window on the right side of the screen The design implementation reflects the current ispEXPERT compiled project Figure 6 1 shows the Physical Viewer with the Design Tree expanded ORELLI RU DATA C wig 5171112 18B TAN Coarerliedy Viss 1 E HE ag NA 0 urna jp EB aH B a OE H B AV aju 1 all eg E 1 Figure 6 1 Physical Viewer Window The tool bar icons on the left side of the screen control the screen display The mode and zoom icons on the right side control the display modes and size of the diagram in the Connectivity window You can move the tool bars and move or resize the windows using standard Windows procedures From anywhere in the Physical Viewer click the right mouse button to display context sensitive pop up menus with commands appropriate to the location of the cursor isoEXPERT Compiler User Manual 193 Design Navigator Window Design Navigator Window The Design Navigator window contains a design tree depicting the design and device logic resource usage Figure 6 2 The Design Navigator has two sections of information User Design and Part The User Design information section contains the user defined external signals and the used functional blocks in the device The Part section displays all the GLBs IOCs Dedicated Control Inputs and GLB inputs and outputs regarding the
69. pin exists the compiler picks one of the pins If no input pins meet the above conditions the compiler issues a warning message and the attribute is ignored Figure 4 2 shows the global reset pin usage a Global Reset Pin Figure 4 2 Global Reset Pin Usage After the input pin is moved to the reset pin the input pin is cleared from the generated output netlist This can eliminate a high fan out net and improve routability of the design However this may require inversion of the reset signal outside the device depending on the polarity of the reset signal and the global reset pin isoEXPERT Compiler User Manual 153 Global Device Options All references to reset signals in this section may refer to either reset or preset signals in the ispLSI 5000V or ispL SI 8000 devices If you have USE GLOBAL RESET set to ON and Y1 AS RESET set to OFF an error message prompts you to change one of the statements for the ispLSI 1016 E 2032 E V VE 44 48 and 49 pin and 2064V VE 44 pin devices Design Manager Sequence Tools Compiler Settings Select Use Global Reset Parameter File Syntax USE GLOBAL RESET ON OFF Command Line Syntax Z Setting the Y1 RESET Pin The Y1 AS RESET option determines how the Y1 RESET pin is used on ispL Sl 1016 E isoLSI 2032 E V VE 44 48 and 49 pin and ispLSI 2064V VE 44 pin devices The default value is ON Description The Y1 RESET pin is a global reset input if YI AS
70. s 449 sb 00 350 gd 250 Timing Analyzer Reports 249 Timing Analyzer Reports Setup and Hold Report For setup and hold information the first column is the name of flip flop or latch The second column is the port name that drives the data pin of the flip flop or latch The third column is the port name that drives the clock pin of the flip flop or latch The fourth column is the setup value and the fifth column is the hold value The following is an example of a Setup and Hold Report design tsu setup and Hold Report Design Name CNT4 Part Name ispLSI2032E 180LT48 This report lists the setup hold requirements for all the boundary registers in the design Required Setup and Hold Register Name Data CLOCK Setup ns HOlLG mns GLB QI2 LD CLK CE 100 GELB QA PS CLK Sac ST GLB QI2 CD CLK Ceo BLOD GLB OIZ DZ CEK cert ze GlBBcOIL2Z EN CLK ono aro eee SLB QUA Cr CLK Duos Ee GLB_OT1 LD CER eo ep og GEB OLI PS GEK 8 50 sp GOB OTL C CLK odd 1 00 GEB OTI Dl CLK Ceo eee GLB QI 1 EN CLK Ceo OO GLB OIT CI CERK os eU GLB QIO LD CLK OG Er GLB QIO PS CLK Suo Eo GLB OIO CD CER Gr Es GLB_OTO DO Clik 8 50 zo GOB OTU EN CLK omens PES GLB QIO ST CLK Suo ESO GLB QI3 LD CER 4 00 e OU GLB QIS PS CERK 4 00 eT GBBGcOIS COD CLK 4 00 sug GLB QI3 EN CLK 4 00 cIS00 GLB QI3 D3 CLK 4 00 REPE GLEB OTs GI CLR 4 00 ep isoEXPERT Compiler User Manual 250 Timing Analyzer Reports Tco Report The following is an example of
71. section or page For example see Chapter 2 Design Attributes n NOTE Indicates a special note A CAUTION Indicates a situation that could cause loss of data or other problems TIP Indicates a special hint that makes using the software easier Indicates a menu option leading to a submenu option For example O C O mE D c File gt New isoEXPERT Compiler User Manual 14 Chapter1 Introduction The Lattice Semiconductor LSC design tool strategy for the isoLSI device families is to support a wide range of design environments The Lattice Semiconductor ispEXPERT Compiler software solution combines third party CAE tools for design entry and verification with the ispEXPERT Compiler software to offer a complete development solution on PC UNIX and HP workstation platforms This manual is designed to teach you how to use the Design Manager the graphical user interface GUI for the iSspEXPERT design solution tool It also describes how to manipulate your source input file by adding Design Attributes and Compiler Control Options This manual is procedural and task oriented to provide specific information about design manipulation and enhancement The ispEXPERT software uses architecture specific algorithms to synthesize a logic description into an ispLSI device Steps in the design compilation process include design optimization automatic logic partitioning and automatic placement and routing The
72. select either attributes or speed you can also specify whether you want to perform Timing Analysis and generate new output files If you previously updated security or the UES you can also have those updated by selecting the appropriate checkboxes Click OK to close the Actions dialog box Click Update to close the Post Compile Update dialog box and generate new files A dialog box asks you to confirm that the Update is to be performed vw Perform Timing Analysis v Generate Output Formats v Update Security IY Update UES Cancel Figure 3 25 Actions Dialog Box isoEXPERT Compiler User Manual 114 Analyzing Your Design Analyzing Your Design Use the ispANALYZER to connect observable nodes to output pins without repeating design entry compilation and verification steps To use the ISpANALYZER select Tools gt IspANALYZER from the ispEXPERT Design Manager The ISpANALYZER window opens and displays a window showing the observable nodes Figure 3 26 The device pins to which they can be connected are enabled for interaction Click on a device pin to connect it to an observable node e FETITET P1 B i c e CisptoolstispcompiExamplesjEdifCHNT 4 CNT4 Observable Node Mapper GLE Macracell Available Device Pins Name Name 15 1B 17 2 Physical Logical Al 01 INODE S1 02 1N419 03 1N365 Opening C isptools izpcomp Examplez Edif CNWT4 Project opened successfully Opening the Workspace CHT4
73. setting in the Customize dialog box A1 GLB Information 1NS65 glb01 03 1N415 gbl1 02 INDDE START glb01 01 Ola glb01 00 glbO1 12 DS glb01 11 CDA Figure 6 16 GLB Function Dialog Box Module Information You can obtain information about a module by double clicking on right clicking on a module in the Connectivity window and selecting Module Information from the pop up menu The Module Information dialog box Figure 6 17 shows the module configuration and the input and output connections of the module RAM MODULE Module Information 512x39 FIFO from B gt Inputs 51 118 gb03 81122 zz 03a 07 1 111 alb z amp 1I22 1l755 22 0 D 1a QU 1 1710 glbO00 1122 10 760 20 2 C1a 02 Figure 6 17 Module Information Dialog Box You can also access module IOC information by selecting the Module IOC Information command The IOC Information dialog box shown in Figure 6 18 displays isoEXPERT Compiler User Manual 209 Obtaining Aaditional Information IOC Information You can obtain information about an IOC by double clicking or right clicking on an IOG in the Connectivity window and selecting IOC Characteristics from the pop up menu The IOC information Figure 6 18 includes the usage the user design signal name the package pin location and whether the IOC bypasses the ORP 1018 IOC Information Utilization Device Infarmatian Usage 6 Input C Torr C reist C
74. similar logic changes have been made in the design source file or if you are reading in a new Property File with pin attributes If you do not retain settings all settings currently in the project are deleted and the project will reflect the information from the design source file If you read in a new Property File when you are updating any pin attributes set in the Design Manager will override the pin attributes in the Property File unless you turn off Retain Settings Update Project Select Design File Mame Directories C usptaals is E xamples E dit es C Cancel E gt jspiools E gt ispcomp E gt Examples Em Ei Drives EDIF Reader Settings C E List File Extension Project Type edn edt Retain Settings Iv Clean Project Device jispLS I2032 180LT 48 Select Device Figure 3 30 Update Project Dialog Box Select the new or changed design file Turn on Retain Settings to have the project settings carried over to this new or changed design Turn off Retain Settings to have all the settings you created for the project deleted For information on saving settings see Naming and Saving Design Settings on page 104 Turn on Clean Project to have the previous output files deleted see Cleaning A Project Directory on page 119 If you change the design source file and do not update your project you are prompted as to whether you want your project updated with the new design file isoEXPERT
75. the Create New Project dialog box The Design Manager reads in the design source file and creates the project A Project Create Status dialog box displays on your screen to tell you what activities are being performed As soon as the project is created the dialog box disappears The Design Manager window changes to include all the menu options Figure 3 3 The project name appears in the banner isoEXPERT Compiler User Manual 82 Opening a Project Once you create a project all the information related to the Device Control Options Compiler Control Options design compilation and Design Attributes is controlled from the Design Manager The information from the design source file that was used to set up the project initially is not used again allowing you to change these design options without complications Once you have an EDIF project open you can modify your Design Attributes using the Constraint Manager The Constraint Manager modifies or creates a Property File Opening a Project If you want to open an existing project use the Open command To open an existing project 1 Select Project Open or the Open icon from the Design Manager The Open Project dialog box appears 2 Choose the file and path information 3 Click OK The project opens and the Design Manager window changes to include all the menu options Only one ispEXPERT project can be open at a time Close the current project before opening another one
76. the compiling fails later in the process for instance during GLB packing or mapping it will output all of the information shown above isoEXPERT Compiler User Manual 236 Compilation Report for the ispLSI 5000V 8000 Devices Compilation Report for the ispLSI 5000V 8000 Devices The report format for an isoLSI 8000 device design is essentially the same as a report for an ispLSI 1000 2000 or 3000 device design but with some unique differences to reflect the architecture of the ispL Sl 8000 device Those differences are highlighted in this section using one small design and one large design The report for ispL SI 5000V devices is similar to the report format in this section Design Specification Section The Design Specification section summarizes the inputs into the program including global compiler and device options For an ispLSI 5000V 8000 device this includes LOWPOWER ON OFF as shown below Design Specification Design CNT4 Design Name Part ispLS18840 90LB432 4 ccc 1Lu4NA B Part Name PULL UP SECURITY OFF OPENDRAIN OFF Global Compiler Device Options SLOWSLEW OFF LOWPOWER ON Input and output pins include DATAHOLD if PULL HOLD is specified as a local pin attribute as shown below Input Pans Pin Name Pin Attribute CD DATAHOLD CI PULLUP CLK DATAHOLD DO DATAHOLD D1 PULLUP D2 DATAHOLD Input Pin Statistics D3 PULLUP EN DATAHOLD LD PULLUP PS DATAHOLD isoEXPER
77. the designer when the design is implemented The ispEXPERT software then attempts to synthesize your design subject to the given constraints namely design constraints and implementation objectives Design rule constraints reflect device architecture restrictions that must be met for a functional design Refer to the SP Encyclopedia for details on device architecture To effectively use ispEXPERT and to better achieve your design objectives you should be familiar with the following subjects m Lattice Semiconductor Device Architecture m Design Attributes m Compiler Control Options m Design Rules Lattice Semiconductor Device Architecture Each Lattice Semiconductor ispLSI device contains logic resources that ispEXPERT uses to partition place and route user specified logic in a design How ispEXPERT uses the logic resources of a device is impacted by the Design Attributes and Compiler Control Options isoEXPERT gives priority to design rule device architecture constraints to meet the requirements for a functional design Therefore the compiler occasionally ignores a user specified Design Attribute or Compiler Control Option to make optimum use of the logic resources of a device or to meet device constraints The logic resources that you can most easily manipulate are Generic Logic Blocks GLBs and I O Cells IOCs Figure 1 5 shows an example of a Lattice Semiconductor ispL Sl device and its logic resources isoEXPERT Compiler Us
78. the logic must be properly clustered and mapped into logic resources of IOCs and GLBs Using STRATEGY NO OPTIMIZATION by itself can result in some modification of logic and leads to one of many possible groupings of logic into GLBs which may not be what you expected Design Manager Sequence Tools Compiler Settings Select Strategy Area Delay No Logic Optimization Parameter File Syntax STRATEGY AREA DELAY NO OPTIMIZATION Command Line Syntax s al d n isoEXPERT Compiler User Manual 133 Compiler Control Options Controlling Routing Time The EXTENDED ROUTE option instructs the router to use a complete routing cycle in an attempt to route a design or to question the user if routing time is very long The default value is ON This option is not valid for the ispL SI 5000V and 8000 device families Description m Turning EXTENDED ROUTE ON instructs the router to continue until the design is fully routed or until routing fails m Turning EXTENDED ROUTE OFF instructs the router to question the user if routing time is very long You can continue or stop and relax some design constraints before trying to route again Design Manager Sequence Tools Compiler Settings select Use Extended Routing Parameter File Syntax EXTENDED ROUTE ON OFF Command Line Syntax E isoEXPERT Compiler User Manual 134 Compiler Control Options Controlling Pin Assignments The IGNORED FIXED PIN and PIN FILE Compiler Options impact
79. the replacement text is used 4 Click Find Next to begin the search 5 Click Replace or Replace All The first occurrence of the string is highlighted in the text window To keep finding the specified string click Find Next again Clearing the Session Log The Clear Messages menu item clears all messages in the Session Log Use Clear Messages carefully as you cannot undo or retrieve important interactive messages once they are cleared Printing In addition to printing text files you can also print the report tables and package views showing ispEXPERT processing results Check the Print icon to determine whether printing is available from the screen you have displayed To print Select File Print or the Print icon from the Design Manager A Print dialog box appears Make your selections and click OK Refer to your operating system manual for information on the Print and Print Setup menu items isoEXPERT Compiler User Manual 123 Optimizing Your Desktop Optimizing Your Desktop Changing the Screen Displays This section discusses several ways to make using the ispEXPERT tool easier to use If you find you need more room on your desktop you can change your desktop by closing screen areas thereby opening up more work space If an area is currently displayed the menu item has a check mark next to it You can also move the tool bar zoom bar and status bar Click the mouse on the icon margins inside the bar Drag it to th
80. the use of pin assignments Ignoring Fixed Pins The IGNORE FIXED PIN option instructs the compiler to either ignore or honor the pin locking attributes in your design The default value is OFF Description m When IGNORE FIXED PIN is ON the compiler ignores the pin locking attributes LOCK in your design Consequently the compiler treats all pins as free and allows the compiler to place I Os anywhere on the device without restriction This option is referred to as Free All Pin Locks in the Design Manager Compiler settings dialog box m When IGNORE FIXED PIN is OFF the compiler honors any LOCK attributes in your design Pin locking appears in the Design Manager Assign Pin Locations window All locks used in the design are set when a project is created and are ignored after that The Design Manager considers the remainder of the pins as free pins Design Manager Sequence Tools Compiler Settings Select Free All Pin Locks Parameter File Syntax IGNORE FIXED PIN ON OFF Command Line Syntax 1 isoEXPERT Compiler User Manual 135 Compiler Control Options Using a Pin File The PIN FILE option directs the compiler to read a pin file with pin assignments Design pins are then fixed to specific package pins according to the pin assignments in the pin file Description Any pin not specified in the pin file remains unaltered as assigned in the input netlist To ignore pin lockings in the input netlist before making pin assign
81. to your Timing Explorer tables Signal Navigator The Signal Navigator Figure 5 12 lists design signals in a tree format and groups them into four categories Inputs Outputs Bidirectional and Registers You can traverse the design in fan in or fan out mode click the right mouse button to select the mode You can expand the signal tree until the selected signal is a boundary signal or starts a loop E DESIGN LIST Fan in Mode El CNT4 E Inputs l Dutputs Er Bi tH RESET H 1N365 H LD H CD H PS NE p CD Bi directional El Registers E Guo HE CLE E RESET Bl CDX Figure 5 12 Signal Navigator isoEXPERT Compiler User Manual 183 Timing Explorer Pop up Menus from the Signal Navigator When you click the right mouse button within the Signal Navigator a number of commands are available depending on where the cursor is when you click the right mouse button From the Signal Navigator window you can select the following commands m Fan In Mode Changes the display to fan in mode m Fan Out Mode Changes the display to fan out mode m Hide Removes the Signal Navigator from the screen From the design name in the Signal Navigator tree you can select the following commands m Timing Matrix Table Displays the Timing Matrix Table for the design m Longest Timing Path Calculates and highlights the design s longest timing path in the Timing Matrix Table m Shortest Timing Path
82. will have the PROTECT attribute as well as all the instances under the macro itself The PROTECT Design Attribute prevents optimization of the specified combinational primitive during logic optimization of your design However the primitive can still be merged with similar gates or split during fitting into the GLB configuration PROTECT is assigned to the symbol or an instance of a symbol In Figure B 9 the schematic shows two instances MACRO A and MACRO Bina circuit called DESIGN C Figure B 10 and Figure B 11 are the schematics for MACRO A and MACRO B Figure B 12 is part of the EDIF file for the schematics in Figure B 9 Figure B 10 and Figure B 11 In this example corresponding cell and object identifiers are highlighted in the EDIF file and the Property File BLOCK1 BLOCK2 P1 P1 D1 P1 D1 DOUT P2 P2 P2 P3 P3 P4 P4 P5 P5 CLK MACRO A MACRO B P6 CLK Figure B 9 DESIGN C Schematic isoEXPERT Compiler User Manual 299 Attribute Examples P1 P2 X t US AND2 NE er E P4 t AND2 P5 gt Figure B 10 MACRO_A Schematic FD11 CLK Figure B 11 MACRO_B Schematic isoEXPERT Compiler User Manual 300 Attribute Examples cell MACRO A cGellTvpe GENERIC view view 1 viewType NETLIST interface possc DL qOUIOOCtrcom OUTPUT port PL drirectron INPUT port P2 direction INPUF port Bo rec ion INPUT Contents Instance U4 viewref view 1 cellref X
83. 0 9 00 CO Pour 0 00 PNIS data arrival time 2100 SLALO Cl nour Dore Endpoint CO oubput port Name pin name type Delay Path CT qa 0 00 0 00 GRP Laon T 30 GLB_A2 SO STO ORP ORP Bypass 3 90 9 00 CO our 0 00 9 00 data arrival time 9400 isoEXPERT Compiler User Manual 258 Startpoint GLB QIO QO0 edge triggered flip flop bndoornts CO output Pork Timing Analyzer Reports GLB QIO QO reg GRP GLB A2 ORP ORP Bypass CO out data arrival time Startpoint GLB Q12 00 edge triggered flip flop Endpoint CO output port GLB QI2 QO0 reg GRP GLB A2 ORP ORP Bypass CO out data arrival time Startpoint GLB Qr3 Q0 edge triggered flip flop Endpoint CO Output Pork GLB QI3 QO reg GRP GLB A2 ORP ORP Bypass CO out data arrival time Startpoint GLB QI3 QO edge triggered flip flop bndpormt OS Output POLL GLB QI3 QO reg ORP ORP Bypass COS Gut data arrival time Startpoint GLB QI2 0Q0 edge triggered flip flop Endpoint OZ output port isoEXPERT Compiler User Manual 259 Name pin name type Delay Path GLB QI2 QO0 reg 00 0 00 ORP ORP Bypass 34 90 934 90 O2 out 0400 390 data arrival time Su 90 St rtpoint GLIB QT1 00 edge triggered flip flop Endpouantt Ql output port Name pin name type Delay Path GLB QI1 00 reg 400 04 00 ORP ORP Bypass 3 90 34 90 oV peu 0400 3490 data arrival time 3490 Startpoint GIB 010 00 edge triggered flip flop
84. 0 ccc ee eee ees 56 ee ey hoe oo eo eee eee ed bo hoe ooo ee eG eee ed bo NER 58 Implementing an ExcluSive Or 0 0 eee rn 58 Optimizing Hard Macros EE 59 Preventing Optimization of Primitives llle 61 EE EE EEE er ee ee 62 Design Pin Attributes 6 ito ORES EES SE 6804S CAEEREREH RC EROR RR Re ER EES 64 Bypassing the Output Routing Pool 0 0 eee 64 LOCKINO ee FING bot oe ehh ee had sod oe bee heh NE NE 65 Locking a Signal to a Big Fast Megablock 0 aaan ccc eee 67 Locking a Signal to a Global Routing Plane 0 0 es 68 Reserving Package PING vic ini uew nnd dudes ve seem th adue ORE OH Oe oS whe Hd Od x CR 69 Local Device Attributes aca dca eae ee HCADIGE E Ron dX eR RE OR ERE AeA pL 4E THERE AERA 71 Using Device Open drain 0 6 eee rs 71 Using Output Buffer Delays 2 46 00 c0s hew sk eek ee Race xk do noe ka iR mon mg ees 71 Ung PUES DANON 3023 299 4 aot dcos 4i 49d d EAR Y EX EE EET PESE 72 Setting Slow Slew Hate 2 cece ee eee es m eee eee ee eee ee eee 73 Setting Device Voltage 1 ee ee ee eee eens 73 Constraint LL ous po eee E AUEAUEREAOR SEE RE oe 30 VAIYCRORE RUP dO 304 Fe ee Tb ee oe eS 74 Setting Attributes rM Ern 75 Using the Constraint Manager with the Design Manager llle 77 Chapter 3 The Design Manager 00c cee ce cece cece eeeeeee 78 Creating a New Project 0 0 cc ee eee eee eens 80 I a 16 0 acad ok dC ee
85. 00 ac ERA Ee don 156 Global Speed Power Control aaaea ee eee eee 157 Global Speed Power Control 2 esse w cece web eee eee ni 157 Using Device Open drain 0 eee e 158 Using Output Buffer Delays 0 0 00 Ir 159 Using Pull up or Datahold uaa aes i9 ede acko P9 e ERRARE RERO ARE SOR ede RECO d 159 Setting Slow Slew Rate 0 0 eee ee eee ees 161 Setting Device Vgs cae needed Gra 3 RAE Ra GE ee SEE SO HOES doe Eae adem ds 161 Setting Device Security 0 ee nr nere 162 Pre EM File uaa m da ORACLE donde d e AERCUEHE ERE NE RC 163 Parameter File Rules 6 5 cows kde der Rok dca 8 4e eR ee dedi 9 dd EN CA Re 163 Parameter File Example 0 0c ccc rn 164 Invoking the Compiler from the Command Line 0 0 00 ce ee 165 Command Syntax EEE ET 165 6 ee cached oe ee basen Ooo T T TIL TOT LTD 165 ETG EE EEE E EE ee EE TEET 166 101910 2 EEE EEE DEN EE E 167 Chapter 5 Timing Analysis 000 c ccc e cece eee eee anaes 168 Timing Analysis Overview 0 0 ce eee eee eens 169 FE EEE Lacu 46 439 od 1d ee EN ES 5 EE T Es 169 Frequency Calculation 024 ok ea Re Roe d wh OST REE AUR OEE mae ORE ERE EEE 170 Frequency Calculation Example 0 0 0 ee eee nes 170 Setup and Hold Time Evaluation 0 aa aaaea eee 172 ST Metan 172 i 3sN u MMC 172 Setup and Hold Time Example 00560 cence eee eet e eee Rn 173 TES EEE eres seh ee BANI ADR AOI bene ed yd N
86. 1 information 211 GLB utilization 198 Global Reset 153 Global reset 154 GND name 82 Go to Connectivity View 195 Grade 90 GROUP 33 39 291 H HDL Format specifying in Physical Viewer 200 Help Hex UES 106 Hold time path evaluation 172 I O Cell IOC 29 information 210 I O Pins design rules 278 Icon about 318 321 323 assign pin locations 95 112 312 compiler 107 312 316 compiler report 312 316 copy 323 cut 323 design navigator 194 explore matrix 101 312 fan in 202 318 fan out 202 318 find 122 find next 313 316 Frequency Table 185 321 locate 318 observable node mapper 316 observable nodes 205 319 open 312 316 323 open a project 83 paste 323 path 203 318 pin attributes 92 312 pin layout 110 312 save 312 316 323 save text file 121 Setup and Hold Table 185 321 signal navigator 321 Index stop 313 316 Tco Path Table 185 321 timing matrix 312 Timing Matrix Table 185 321 timing path 204 318 toggle device navigator 318 toggle mode bar 201 toggle view mode bar 318 toggle zoom bar 318 Tpd Table 185 321 undo zoom area 319 zoom area 319 zoom bar 197 zoom default 319 zoom in 319 zoom out 319 zoom to fit 319 Identifiers maximum characters 267 multiple 306 Property File 288 valid 267 IGNORE FIXED PIN 135 Import compiler pin results 111 pin file 112 Index ordering 82 Information on Project 118 INPUT FILE 137 INPUT FORM 137 INST 288 Interfaces 85 EDIF writer 88 EDIF wr
87. 14 320 322 Options 125 Paste 122 Replace 122 text file 122 Undo 122 EFFORT 132 ENDPROPERTY 288 Equation GLB Function 209 Errors reserved file names 266 specification 268 syntax 266 system errors 266 Example 4 bit counter 215 Explore append log file 99 calculate frequency 98 criteria 99 directory ispds run 100 matrix 101 settings 99 stopping 100 using 98 Explore Log append new results 99 Explore Matrix saving settings from 103 Explore matrix 101 N Explore Matrix display criteria 102 EXTENDED_ROUTE 134 F Fan In Mode 201 202 Fan Out Mode 201 202 FASTCLK 36 Feedbacks 208 File compiler log 108 editing text 122 input 25 ISOANALYZER 116 JEDEC 23 menu 309 314 317 320 322 Open 121 output 25 output netlist 89 pin assignment as text 96 report 23 reserved file names 266 Save As 121 selecting design 81 Filter explore matrix display 102 macrocell names 116 pin names 96 Find 122 icon 122 using search 122 Find Object 197 First Success during Explore 99 Free pins 97 Frequency calculation during Explore 98 calculation from Timing Viewer 184 Frequency Analysis Report 248 Frequency Table pop up menus from 187 Function 209 Fuse map generation 23 113 G Generic Logic Blocks GLBs 28 design rules 279 Function 209 Internals 208 Resource Information 207 Utilization 208 views in Connectivity window 198 GLB clocks 62 GLB congestion 198 GLB Pins isoEXPERT Compiler User Manual 33
88. 21 searching 122 Timing Analysis 20 frequency calculation 170 hold time 172 overview 20 path analysis 169 setup time 172 Timing Analyzer 178 Clock Frequency Report 181 QD QD isoEXPERT Compiler User Manual 336 Detailed Report 181 functions 178 invoking 189 Module Report 181 node selection 179 options 147 178 report files 181 Setup and Hold Report 181 summary Report 181 Tco Report 181 Tpd Report 181 Timing Analyzer Reports 6192 261 Frequency Analysis 248 Selected Path Boundary 258 Selected Path Detailed 255 selected Path Summary 253 oetup and Hold 250 Tco 251 Tpd 252 Timing Matrix Table 185 displaying timing path 204 pop up menus from 187 Timing Path Mode 204 Timing Path Report 188 Timing Paths displaying 188 Timing Report Results 182 Results menu 182 Timing Viewer accessing 183 213 adjust table columns 185 Clock Frequency Table 186 Signal Navigator 183 Timing Matrix Table 185 TIMING ANALYZER 147 TIMING FILE 143 Tips pin 97 TOE AS IO 152 Toggling LowPower path 53 Tool Bar opening closing 124 Physical Viewer 193 Tools Compile 107 Compiler Settings 84 Explore 100 Explore Settings 98 isSOANALYZER 115 116 ispDCD 118 Index menu 310 315 317 Path Tracer 206 Physical Viewer 117 Post Compile Update 113 Timing Analysis 180 Timing Analyzer Settings 189 Tpd calculation 174 Report 181 252 Table 182 Trial compilations 98 Turbo paths 54 Turbo settings 113 157 post compile 55 U Undo Edit
89. 279 N Names duplicate 268 NET 288 Net Attributes 33 35 297 BFM 35 291 CLK 36 291 GROUP 39 291 PRESERVE 4 SAP EAP 292 SCP ECP 292 SLP ELP 292 SNP ENP 292 STP ETP 292 XOR 43 156 291 Netlist output files 85 89 updating 113 Nets design rules 280 New File 121 Project 80 Node mapper 116 Nodes observable 115 No Minimize paths 56 Number of MAX GLB Levels during Explore 99 O Observable nodes 115 116 Open 40 291 2 isoEXPERT Compiler User Manual 333 File 121 Project 83 OPENDRAIN 33 71 92 158 289 290 Optimization design 268 for resource utilization 269 for routability 270 for speed 277 partitioner 41 OPTIMIZE 33 59 293 OUTDELAY 33 71 92 159 289 290 Output Enable design rules 279 Output netlist files 89 OUTPUT FORM 142 P Package type device 90 Package view 96 changing pin color and shape 125 PARAM FILE 144 Parameter File rules 163 use of 163 Parameterized Attributes 303 PART 145 Part numbers 145 Partitioning 18 Paste Edit 122 Path enumeration 175 hold time 172 setup time 172 Path Attributes 45 297 SAP EAP 45 47 SCP ECP 50 SLP ELP 53 SNP ENP 56 SIP ETP 54 Path Enumeration Report 181 Path Mode 201 203 Path Tracer 206 Physical Viewer 20 accessing 117 193 Connectivity window 196 Design Navigator 194 Module 209 Path Tracer 206 PIN 288 Pin Array Attributes 296 CRIT 290 LOCK 290 Index OPENDRAIN 290 OUTDELAY 290 PULL 290 SLOWSLEW 290 VOLTAGE 291 Pin ass
90. 6E 80LJ44 END This begins the 2nd set of parameters Part number defaults to the original part specified MAX GLB OUT 4 STRATEGY DELAY OUTPUT FORM VIEWLOGIC TIMING_FILE unique_name TIMING ANALYZER ON END The final two examples use default values for unspecified parameters Part number defaults to the original part specified MAX GLB IN 14 MAX GLB OUT 3 END New part specified PART ispLSI1032E 100LJ84 IGNORE FIXED PIN ON TIMING FILE unique name TIMING ANALYZER ON END If you are using a Parameter File the compiler stops at the first successful set of parameters or if an error occurs It is usually a good idea to place the most restrictive sets of parameters at the beginning of the file isoEXPERT Compiler User Manual 164 Invoking the Compiler from the Command Line Invoking the Compiler from the Command Line Use the dpm command to invoke the Design Process Manager which manages the individual functions of the compilation process Only one active compilation job can be running in a working directory at any given time Running more than one compilation job from the same directory may result in a system error You can run dpm commands from the command line in UNIX operating systems or from an MS DOS window in Windows 95 98 and Windows NT operating systems Command Syntax dom c e 1 2 3 low medium high i file name if edif laf pla viewlogic 1 m 2 68 En Lh 4 eo LL MAX
91. 9 LOCK GRP 289 OPENDRAIN 289 290 OPTIMIZE 293 OUTDELAY 289 290 PRESERVE 291 PROTECT 293 PULL 289 290 REGTYPE 293 RESERVE_PIN 293 SAP EAP 292 SCP ECP 292 SLOWSLEW 290 SLP ELP 292 SNP ENP 292 STP ETP 292 VOLTAGE 290 291 XOR 291 Design entry vendor 81 Design file Index selecting 81 Design flow 16 n Design Manager 17 overview 78 Design Navigator 194 Design Process Manager 165 dpm command 165 Design Rules 30 264 clocks 280 GLBs and Megablocks 279 global reset 279 I O pins 278 keywords 268 modules 279 nets 280 Output Enable 279 valid characters 266 valid identifiers 267 Design Settings naming and saving 104 Desktop changing message color 126 changing pin color and shape 125 changing the look 124 Detailed Report 181 188 Device architecture 26 design rules 278 changing speed grade 114 diagram 96 isoLSI example 26 selecting 81 90 Statistics 212 Device Control Options ISP 150 ISP EXCEPT Y2 151 LowPower 157 SECURITY 162 selecting 91 opeed 157 summary 91 Y1 AS RESET 154 Device programming 118 Device type 90 Directory cleaning 119 Explore 100 project 24 settings 104 Display area on screen 124 dpm command 165 isoEXPERT Compiler User Manual 330 Index E ECP 92 EDIF reader settings 81 writer settings 88 EDIF Reader attributes 307 edif2laf 307 file formats 307 Vcc and GND 307 Edit Clear Messages 123 Copy 122 Cut 122 Delete 122 Find 122 menu 309 3
92. AND 2652 02 OTIZ parto G2 OILZ party 2 QLIZ Darto G2 QLILI3 parto GZ OTI DAF G2 UTIS paruo G2 QIIA4 partO0 G2 QI14 partO0 G2 OILA parto isoEXPERT Compiler User Manual glb24 019 glb24 07 glb29 016 glb30 gGlLbs0 glb30 glb30 glb30 GlLps0 glb30 Gbps gqX1p50 Output Net Output Pin glb30 135 glb30 110 glb30 133 SUME Nom OI so S097 OD ULT TL OL GP gqip24 1052 GLD Iy qip24 SG pO glb2 glb2 glb3 Es FS A i do Net Source Destination 242 Compilation Report for the ispLSI 5000V 8000 Devices The internal tristate net section displays the tristate drivers and fanouts for each internal tristate net Tristate drivers are displayed in groups of three each group listing the driver s source pin net and output enable signal Tristate fanouts are displayed in groups of two each group listing the fanout s destination pin and output net which is the same as the name of the tristate net The following is an example from an internal tristate net section Internal Tristate Net 0 OUTPUTA EO 4 4 Tristate Net Name Source Net Output Enable 7 Tristate Driver s glb16 00 TSI211 BUF 2631 glb14 00 _BUF_2599 _BUF_2637 glb27 00 TSI215 BUF 2635 glb18 00 TSI213 BUF 2633 61519 00 TSI219 BUE 2632 91b19 00 TSI214 BUF 2634 glb20 00 TSI216 BUF 2636 2 Fanout s De
93. Attribute allows the output driver on any I O pin to drive either 3 3V or 2 5V output levels while the device logic and the output current driver are powered from 3 3V Voltage is supported for the ispL Sl 5000V device family Synopsis VOLTAGE VCC VCCIO Description The values for VOLTAGE are m VCC sets the output driver on an I O pin to 3 3 volts m VCCIO sets the output driver on an I O pin to 2 5 volts The VOLTAGE local Pin Attribute assigns the VOLTAGE attribute to individual pins it overrides the global VOLTAGE option By default the global VOLTAGE Device Option is set to VCCIO See Setting Device Voltage on page 161 isoEXPERT Compiler User Manual 3 Constraint Manager Constraint Manager The Constraint Manager allows you to set attributes in your project make changes to an EDIF Property File or create a new Property File You can set pin net symbol and instance attributes using the Constraint Manager You cannot set pin array attributes The RESERVE PIN symbol attribute cannot be set using the Constraint Manager The Constraint Manager is accessed by selecting Tools Constraint Manager from the ispEXPERT Compiler Design Manager ra ap PETN Compin Laszsaenrd Marge OM 14 Map 515 8 HP 1L EZ 2 Pin Attributes Tabla FULL SLOWS PEND DUTDELAY WOL TAGE SP WBeconan Hi Cay H PL Mai Figure 2 35 Constraint Manager Main Window with Input Pins Expanded The window on the left contain
94. Currently the Timing Analyzer assumes that all the starting points are available at time O m The starting point for a path can be one of the following e Primary input port The Timing Analyzer reports the input port name followed by in e Bidirectional port The Timing Analyzer reports the bidi port name followed by bidi e he output of a flip flop or latch The Timing Analyzer reports the instance name followed by a followed by the output pin name followed by inst primitive name m The ending point for a path can be one of the following e Primary output port The Timing Analyzer reports the output port name followed by out e Bidirectional port The Timing Analyzer reports the bidi port name followed by bidi e The data pin or clock pin of a flip flop or latch The Timing Analyzer reports the instance name followed by followed by the pin name followed by inst primitive name An example of a detailed report follows Timing Analysis Detailed Report Design Name CNT4 Part Name ispLSI2032E 180LT48 Ihis report contains the detailed listing of the selected paths with the individual gates and their delays Path Enumeration otertpornt EN input port Endpoint CO output port Point Name pin name type Delay Path IOC IO2 IBUFO XIO 0 00 0 00 isoEXPERT Compiler User Manual 255 IOC IO2 IBUFO Z0 GRP ENX grp AO GRP ENX grp Z0 GLB A2 IN2 A0 GLB
95. Cut Copy Paste Delete Undo from the Design Manager These functions all work according to Windows or UNIX standards Using Search and Replace With a text window open you can search for and if desired replace strings of text Use the Find Next icon to find a string of text To search for any information string 1 Click the Find Next icon or select Edit Find from the Design Manager The ae Find dialog box appears Figure 3 32 Find what Bind Hest Direction Cancel Match case C Up Down Figure 3 32 Find Dialog Box 2 Enter the desired search string information in the Find what field Click Match case to find only the strings that have the same upper and lower case characters as the Find what string 3 Click Up or Down in the Direction field 4 Click Find Next to begin the search The first occurrence of that string is highlighted in the text window To keep finding the specified string click Find Next again To replace an information string 1 Select Edit gt Replace from the Design Manager The Replace dialog box appears Figure 3 33 Heplace Find what Etre NE Replace with Replace Bepace gll Cancel Match case __Cancel_ Figure 3 33 Replace Dialog Box 2 Enter the desired search string information in the Find what field isoEXPERT Compiler User Manual 122 Using a Text File 3 Enter the desired replacement string in the Replace with field Click Match case so the case of
96. Description Running the Timing Analyzer as a batch mode process with the TIMING ANALYZER option automatically creates the Clock Frequency Setup and Hold Tco and Tpd reports m Setting TIMING ANALYZER ON results in running the timing analyzer during the compile process m Setting TIMING ANALYZER OFF results in the timing analyzer not running during the compile process This option does not provide as much control over the Timing Analyzer as the interactive Timing Analyzer from the Tools Timing Analyzer Settings and the Tools Timing Analysis menu items Design Manager Sequence Tools Compiler Settings Select Perform Timing Analysis Parameter File Syntax TIMING ANALYZER ON OFF Command Line Syntax Ca On Orr isoEXPERT Compiler User Manual 147 Compiler Control Options Using the Internal Tristate IO Driver The Use Internal Tristate IO Driver compiler option controls whether the IO driver from the GRP is used for the internal tristate bus This option is only valid for ispL Sl 8000 devices Default is OFF Description When this option is turned ON the compiler uses the IO driver from the GRP for the internal tristate bus This may result in less delay and a faster design However user constraints such as locking and quadrant clock and design complexity may prevent fitting of the design if the IO driver is used When this option is turned OFF the compiler does not use the IO driver from the GRP for the in
97. E 174 Tes oh hoo og 0 99 4 Os ee ee 174 B ee RE T PG ee ee EE ee ee ee ee 175 Longest and Shortest Path Example aauvavva ravn eee 176 SEE SST ET ENE 177 ISOEXPERT Timing Analyzer aaauuuvr vnr narr eee teens 178 Running the Timing Analyzer aauavn rv vn nr eens 178 Timing Analyzer Report Files PES 181 ispEXPEHRT Compiler User Manual 7 PO ENO RENERE EE ED 183 EE EV EE EEE ETE EA 183 Pop up Menus from the Signal Navigator 0 0 00 arr ees 184 Timing Explorer gt REE EEE Err os 8 oe eee 185 Pop Up Menus from the Timing Tables 0 0 ravn rv rann ees 187 INNO EE ENE 3 279 4 3 9 EE ERE d Po dea 188 Running the Timing Analyzer from the Command Line 2 0000 cee eee eee 189 Power Calculation 0 0 0 erae 190 Chapter 6 The Physical Viewer serere 192 Running the Physical Viewer 0 0 000 rns 193 Design Navigator Window 20 20 cc eee eens 194 Connectivity Window aaaea eee nn 196 Ose SVA ee aad a a RE ee ee ee ee RP ee es ee EN 198 Customizing the Connectivity Window llle 199 SDAY DOGOS EE PT 01111227 ETE ee ee ee ee 201 PU MN oe 55444444 TNT 206 Obtaining Additional Information 0 0 anaa aaa ne 207 ALD MOMA 5 ee EEE EEE NE ee ee ee a ee ee oe 207 Module Information 0 0 0 0 rn 209 GE us g oe eo G4 eee eee EEE EE EE ENE eee S 210 Dedicated Control Input Information 2 0 0 0 ce ee een
98. E hed ES OE OER OE EO 294 SE Soe kc dada dara 332 54 93 94 d da a e i 3 3 dos NR ee aae dac dar d gs 294 Pin Array FUNG Gn oie aqoa ai dede eed boni d aio dod oct ad qd c dei eee yen de ees 296 Net and Path Attributes 0 0 rn 297 Sea Eure c PENNE ISTIS I COTOCOT TIT EET 01 2 T EN 299 Parameterized Attributes llle rrr 303 Multiple Property Identifiers cc nint tI 306 EDIF Reader Command Line Syntax 0 0 0 0c eee ees 307 Appendix C Menu and Icon Reference 308 Leste Sete eee Lee AAN NEA op ard d odor ee 309 Pull Down SEE 04 3 3 4 9 3 ded DET PER EIOS Pra CR AR 309 SOCAL IONS aa 9 aes 332179 1991 933793 933 123 13 153499 ee FIXE FREE 3E 312 Per Le cea ded 9 4 93 X9 TESS EE SEE EE ETE NE 314 Bbc act EEE EEE EEE NE eer Rd EE dos 3 314 Tool Bar ICONS lille hrs 316 xl R7 TP ee EE ee ee ee NE ETE 317 Pull Down MBILIS uk ahora COREE AGE DS HE GEER Road de deed CAHSEE ESS 314 TOOL BAT SETTET EEE eee See ee eee 318 DU C a dh ee oh ee ee aes oh ee dee eee ame bon des eae 320 Pull Down MenuS 00 0c cc ee eee eee eee eee 320 pgs Reig cs PESTEN 321 Constraint Manager 1 ee eee eee eee eee 322 P ll Do own is cae doa ee Ree A eee ee ke SERGE EEE NE 322 ee REE 323 1 NE RR e ee eee 324 ispEXPERT Compiler User Manual 10 Preface The isoEXPERT Compiler software referred to as ispEXPERT is used to optimize partition place and rou
99. ERT Compiler User Manual LOCK 28 QO Ql Q2 Q3 jJ 9 CAO 215 Compilation Report Compilation Report When a design successfully routes the following report summaries appear in the design rpt file Design Parameters Describes the running environment Design Specification Summarizes the inputs and attributes in the design as specified by the designer Pre Route Design Statistics Summarizes resource usage in completed design Indicates the cause of the unsuccessful routing Design Implementation Statistics Summarizes partitioned design statistics and timing analysis at the end of successful routing If a design does not successfully route the following report summaries appear in the design rpt file Design Parameters Describes the running environment Design Specification Summarizes the inputs and attributes in the design as specified by the designer Pre Route Design Statistics Summarizes resource usage in completed design Indicates the cause of the unsuccessful routing Pre Route Design Implementation Summarizes partitioned design statistics before routing If a design does not fit a short description will be attached to the end of the Design opecification section of the compiler report To access the compiler report file 1 select Results Compiler Report or the Compiler Report icon from the Design Manager The report for the current project appears After you compile if you u
100. Fan Out Information Shows the fan outs for the selected GLB output pin IOC or Dedicated Control Input pin Fanin Information Selected Component Fanout Information 77i Macrocell Name 1N365 FIN 03 GH glbO0 part2 GLB 45 Instance Name ate BLB A1 I HDL Format Equation i ER Output pin 03 of GID glbDO partl GLB 42 I s m E Dein glbO1 drives signal NER OLPC 1N365 1N365 gb01 03 jalb01 17 CD Spor ni Pex Input pin I1 of glb01 albO1 19 D1X is driven by signal CDX jglb01 16 alb t IB glb01 13 n3 G0 GND IF3 PI4 P15 ft P16 l Exclusive OR Gate IP15 10 amp 111 amp 19 H P14 PO amp IT amp 138 16 amp 18 OH Gsm Inverted Signal Figure 6 12 Path Iracer Window Select a GLB output pin IOC or Dedicated Control Input from the Connectivity window before accessing the Path Tracer Select Tools Path Tracer to access the Path Tracer window or right click and select from the command pop up menu To access the Path Tracer from the Design Navigator use the right click pop up menu The selected component displays in the Selected Component section The Fan In and Fan Out information for the selected component displays in the appropriate sections You can double click on a component in the Fan In or Fan Out sections it moves to the Selected Component section The Fan In and Fan Out sections are updated to reflect the new selection The selected comp
101. Function 209 GLB Pin Information 211 selecting 200 Boundary Report 188 Bus reconstruction 82 C Calculate Frequency from Physical Viewer 213 Calculate frequency during Explore 98 during Timing Analysis 178 in Timing Viewer 184 Calculation of device power 190 CARRY PIN DIRECTION 131 Case Sensitivity in parameter files 163 PLA project 81 specifying 267 CASE SENSITIVE 131 isoEXPERT Compiler User Manual 328 Index Changing Connectivity window 199 package view 125 session log 126 Characters maximum number 267 valid 266 Clean Project 119 120 Clear Messages Edit 123 CLK 33 36 291 Clock design rules 280 GLB 62 IOC 62 Clock Frequency Report 181 Clock Frequency Table 186 Results menu 181 Clock to Output Report 181 Closing a project 127 Color changing in Physical Viewer 199 changing messages 126 changing pins on desktop 125 customizing 126 Commands dpm 165 edif2laf 284 307 ta 189 Compile design 107 from Explore Matrix 103 icon 107 ISDANALYZER 117 memory requirements 277 status window 108 terminating 107 Compiler Control Options 30 BFM Packing for Routability 130 CARRY PIN DIRECTION 131 CASE SENSITIVE 131 EFFORT 132 EXTENDED ROUTE 134 IGNORE FIXED PIN 135 INPUT FILE 137 INPUT FORM 137 MAX GLB IN 138 MAX GLB OUT 139 Minimize GLB Levels for All Paths 141 OUTPUT FORM 142 PARAM FILE 144 PART 145 PIN FILE 136 Property File 145 SECURITY 162 setting 84 single PT Function Packing for Routability 146
102. JLH COE ZZ TG 130 I1 141 GO indicates an IOC pin a p from the Global Routing Pool BAIX B42X B43X B44X B45X B46X B47X B48X B49X G2 q4D22 gloza GLb Oo EDS gos SELL gIpoos ope Oller gqIpos LOL OG PEEL Oly G2 OILO parto G2 OILI parto I40 ELD Y 195995 I32 Li I0 2o I40 124 GLDZ9 LAT gibZ4 1505 GLO EEG Oy GID2Z9 Esk glb24 124 IRS 31 G1H30 124 gIP2I LO Multiple Fanouts OF4B GO OEABX OE6A GO OEG6AX 2007 O0 00 OG OG QQ LOU glb18 glb29 IDET glb14 GLDd 5 glb12 glblo isoEXPERT Compiler User Manual GELDA L GLOS GLEN glb24 OUTPUTA_EO glb24 qipo2 1050 LASG WE o rio UG 190 115535 glb32 133 Multiple Sources 241 53 Our put Ss 15 Fast Interconnect Signal s Compilation Report for the ispLSI 5000V 8000 Devices BUE 2903 gl1b24 02 BUF 2804 91b24 03 BUF 2805 glb24 04 BUE 2900 1524 05 GJL BEREN GIS OL GZ IIS partos lbpoD 059y G2z QDL4 parce dglbo0DOll G2 OIL Part 91 p30 09 G2 OT party 91030060 GZ OLS parco GPL 018 G2 J016 Dare xLb20 0125 G2 Ol Dare gib500l 2 75 G2 018 p rt 0 G1PSU 05 FEIL WESS TORE GLO rOy TSIL23S ZqLDO5 02 TOLL y GLU OT Torbole GLB 02 DOSITI65 boos eo Ly AND 2539 AND 2547
103. L Unused External Signal Name Package Fin Location ORF Bupass C yes Ho Figure 6 18 IOC Information Dialog Box Dedicated Control Input Information You can obtain information about a Dedicated Control Input by double clicking or right clicking on a Dedicated Control Input pin in the Connectivity window and selecting Dedicated Control Input Characteristics from the pop up menu The Dedicated Control Input information Figure 6 19 includes device information whether the compiler used the Dedicated Control Input pin the external signal name and the package pin location YD Dedicated Control Input Information JO Utilization Device Information m C nsed External Signal Name CLE Package Pin Location 5 Figure 6 19 Dedicated Control Input Information Dialog Box isoEXPERT Compiler User Manual 210 Obtaining Aaditional Information GLB Pin Information Each GLB input and output pin has a property sheet that contains information on the utilization Figure 6 20 and function Figure 6 21 of the pin For GLB output pins you can access this information by double clicking or right clicking on an output pin in the Design Navigator or the Connectivity window and selecting Utilization Information from the pop up menu Since GLB input pins are not shown in the Connectivity window you must double click on an input pin in the Design Navigator 00 GLB Pin Information Utilization Function Instance Mame
104. Manager Compile or Explore tool runs on a UNIX platform a script file is generated in the working directory The compiler script file compile bat contains the command line compiler command with options that reflect the compiler and device settings The explore script file explore bat contains all Explore generated compiler commands If you turn on Append to Current Explore Log in the Explore Settings dialog box the Explore compiler commands will be added to the end of the existing file These script batch files can be run from the UNIX command line isoEXPERT Compiler User Manual 167 Chapters Timing Analysis The ispEXPERT software has a built in static Timing Analyzer isp TA that provides accurate pin to pin timing information for your design The Timing Analyzer calculates maximum clock frequency calculates chip boundary setup and hold requirements calculates Tpd and Tco path delays calculates GLB boundary delays and performs path enumeration The Timing Explorer provides an interactive method for viewing and querying timing information for the design This chapter contains the following information m Timing Analysis Overview m isoEXPERT Timing Analyzer m Timing Explorer isoEXPERT Compiler User Manual 168 Timing Analysis Overview Timing Analysis Overview The static timing analyzer enables you to evaluate the performance of the design after successful compilation The analyzer traces all the signal paths and their delays
105. NA Command Line Syntax mgl HIGH LOW isoEXPERT Compiler User Manual 141 Compiler Control Options Creating Netlists The OUTPUT FORM and TIMING FILE Compiler Options are used when creating output netlists Specifying the Format of an Output File The OUTPUT FORM option specifies the output netlist format to be generated for post route simulation Description The possible values are EDIF LMC VERILOG VHDL and VIEWLOGIC m EDIF Generates an EDIF 2 0 0 format netlist design edo file m LMC Generates a design 1mc file for board level simulation with Synopsys Logic Modeling Division models gm VERILOG Generates an SDF format netlist design sdf file as well as a Verilog format netlist design v1lo file for use with any Verilog compatible or SDF compatible simulator m VHDL Generates two generic VHDL format netlist files for maximum delay design vho and minimum delay design vhn anda VITAL VHDL format netlist design vto file for use with any VHDL compatible simulator m VIEWLOGIC Generates a Viewlogic wir file timing 1 anda design edo file to use with a Viewlogic simulator and a design sim file for board level simulation In a Viewlogic design environment the design sim file is placed in your current working directory and the timing 1 file is placed in your wir directory The Viewlogic edifneti and edifneto utilities must be present for this output option to work correctly This option can be used
106. NE 135 ed PES ENE 136 POSTINI ING WIDOT PIER PETE EE kd 4h oo 068 6444549445004 64465604051 137 Specifying the Name of an Input File 2 0 0 0 0 ee 137 Specifying the Format of an Input File llle 137 Controlling GLB Inputs and LO 00 REE 138 Specifying Maximum GLB Inputs nananana aaaea eee 138 Specifying Maximum GLB Outputs a na naana aaa Rx 139 Minimizing GLB Levels 0 cc nn 141 Eg et Ci ee ee ae ee PE ee ae ee ee CR ee 142 Specifying the Format of an Output File 2 0 0 ee ee 142 isoEXPERT Compiler User Manual 6 Specifying a Viewlogic Timing File Name 0 0 0 0 cee eee eee 143 Specifying a Parameter File n nnana aaaea n 144 Specifying a Part Number 2 16 sse ee raodo ee Sarr echoes P RR ood CRX bo ens 145 Specifying Property File sez ne dada Er see PEE OR dora ed aren beds 145 Single PT Packing for Improved Routability llli 146 Performing Batch Mode Timing Analysis llle 147 Using the Internal Tristate IO Driver lll hrhy 148 Global Device Options lille an 149 Using In System Programming Pins llle 150 Using the Y2 Pin as a Clock Input aes aea noe ORRCRCICROR OR CORRER tre 151 Using the TOE IO Shared Pin aavaa rann rann rn rne 152 Setting the Global Reset Pin 2c aana 153 Senna ihe THBESET PI aas s 9 6 013 awed Need de 154 Preserving XOR ET 4444644444054 445044 049409948 404
107. NOTE This Pin Layout window is not editable You cannot make changes to the pin assignments from this window isoEXPERT Compiler User Manual 110 Changing the Pin Assignment Changing the Pin Assignment After you study the pin layout you may find that the pins were not locked exactly as you specified during your pin assignment sessions You can edit the post compile pin layout from the Assign Pin Locations window ACAUTION If you import the pin layout from the compiled design the precompiled pin assignments that you made during your pin locking sessions will be lost unless you save the settings To modify the post compile pin layout 1 Select Assign Pin Locations or the Assign Pin Locations icon from the Design Manager The Assign Pin Locations window appears 2 Select Compiler Result in the Import Pin Assignment field The package view changes to show the post compile pin assignments 3 Change the pin assignments as necessary See Locking the Pins on page 95 for instructions on how to lock the pins 4 Recompile the design by selecting Tools Compile to generate netlists and reports Viewing the Output Netlist Results Once you compile your design or run an available netlist writer you may check the output netlist results using the Results menu To display the VHDL netlist file m Select Results gt VHDL Netlist Vital Compliant to display the VITAL compliant netlist m Select Results gt VHDL Ne
108. Name field d Type a GND name in the GND Name field Select a bus reconstruction preference if your EDIF file contains arrays Refer to the VHDL and Verilog Simulation User Manual for details Choose Array Index Ordering Up Down from the radio buttons Since the range of the indices is not implied in the array name you need to specify how the names should be created By default the index number goes from low to high However if you want to generate the names in descending order the Array Indexing Order should be set to Down Choose Least Significant Bit Left Right The EDIF file does not contain information on whether the array is arranged in descending or ascending order By default the ispEXPERT EDIF reader assumes the least significant bit of the members is the leftmost element of the expanded bits If the EDIF file being processed contains arrays with the LSB as the rightmost member you can set Least Significant Bit to Right e Turn on the Ground floating output pins check box to have all floating output pins connected to Ground f Enter a Property File name or click the Browse icon to browse for a Property File The Property File contains Design Attributes that you want to attach to this project design The Open dialog box appears Choose a file and click OK Refer to Appendix B EDIF Property File for information on creating a Property File Click OK The EDIF Reader Settings dialog box closes Click OK to close
109. OR2 cell MACRO B cellType GENERIC view view 1 viewType NETLIST interface cell DESIGN C cellType GENERIC view view 1 viewType NETLIST interface port DOUT direction OGUTPUTY port PL direction INPUT port P2 direction INPUT port CEK Gir ctioh INPUTIY contents Instance BLOCK1 viewref view 1 cellref MACRO A Instance BLOCK2 viewref view 1 cellref MACRO B Figure B 12 EDIF File Example for DESIGN C isoEXPERT Compiler User Manual 301 Attribute Examples In Figure B 13 MACRO B is always protected and instance U4 in MACRO A is protected In Figure B 14 Block2 in DESIGN C is protected and instance U4 in MACRO A is protected PROPERTY MACRO A INST U4 PROTECT ENDPROPERTY PROPERTY MACRO B SYM PROTECT ENDPROPERTY Figure B 13 Property File Example 1 PROPERTY MACRO A INST U4 PROTECT ENDPROPERTY PROPERTY DESIGN C INST BLOCK2 PROTECT ENDPROPERTY Figure B 14 Property File Example 2 isoEXPERT Compiler User Manual 302 Attribute Examples Parameterized Attributes A parameterized attribute is any attribute that contains a variable Parameterized attributes are required for any macro that contains a path attribute SAP EAP SCP ECP SLP ELP SNP ENP or STP ETP and can be used for CLK attributes if necessary Variables within parameterized attributes are identified by a preceding symbol They can contain alphanumeric and underscore characters and can be up to 127 charact
110. OsR XCDX GJ OIl P rtUsPR gt YSDX Local Feedback G3 OIl partl same as G3 OIl part0 Local Feedback Has Same Logic as Previous Output 1 Fanout s Suo sd isoEXPERT Compiler User Manual 246 GLB Name Compilation Report for the ispLSI 5000V 8000 Devices The following example is a partial sample of the GLB and GLB Output Statistics table for this design Note that the table includes number of Turbo Product Terms TurboPTs whether Turbo is ON LOWPOWER OFF or OFF LOWPOWER ON and how PTSA Bypass PTSABP is used 4 PT for bypass product terms and 1 PT for single product term for isoLSI 8000 devices or 5 PT for bypass product terms for ispLSI 5000V devices GLB and GLB Output Statistics s LOCACION GLB Output Name glb0 Number of Ma Number of Ma Number of Ma Number of Ma Number of Ma Number of Ma Pin Assignme Pin Name CLK OS Q1 Q2 GI CD D1 PS DS D2 EN QO DO LD XCDX 0 SBUF 21352 BUB 2738 BUB 2 159 BUF 2740 BUF 2742 BUF 2743 BUF 2744 BUE 2771 The Product Term Summary shows the number of macrocells that contain the specified number of Product Terms Groce lis with crocells with Groce Le with crocells with Groce lls with crocells with if 2 3 4 5 6 GLB Statistics TAS OI 8 5 Product Product Product Product Product Product 8 Fbks 8 Terms Terms Terms Terms Terms Terms Co 49 r0 CO CD GLB Output Statistics 8 do le OM w
111. Parameter File Syntax CASE SENSITIVE ON OFF Command Line Syntax e isoEXPERT Compiler User Manual 131 Compiler Control Options Controlling Optimization You can specify the optimization effort level using the EFFORT Compiler Option and the optimization strategy using the STRATEGY Compiler Option Setting Effort Levels The EFFORT option provides different optimization effort levels Description EFFORT has a range of low medium or high or 1 to 3 The larger the effort the larger the runtime and memory requirement While a higher effort level usually leads to better results this is not guaranteed Different effort levels should be tried to find the best result for a specific design The default value is 2 or Medium Design Manager Sequence Tools Compiler Settings Select Effort Low Medium High Parameter File Syntax EFFORT 112123 Command Line Syntax e 1 2 31l1ow mediuml high Choosing Optimization Strategies The STRATEGY option allows you to specify one of the following three optimization strategies gm AREA Maximum resource utilization m DELAY Maximum performance default m NOLOGIC OPTIMIZATION Bypasses the synthesis and optimization stage and maps your design directly into the ispL Sl architecture Description The following points are important to remember when you use the STRATEGY option m Forlogic level considerations DELAY offers the least number of logic levels m AREA optimizes
112. Path SNP ENP Specifies the Start and End of a No Minimize Path STP ETP Specifies the Start and End of a Turbo or speed Path Symbol Attributes LXOR2 Enforces direct implementation of a two input XOR OPTIMIZE Allows optimization of a hard macro PROTECT Prevents logic optimization of a primitive REGTYPE Specifies register location inside a GLB or IOC RESERVE PIN Prevents package pins from being assigned during the compilers pin locking process Pin Attributes CRIT Assigns specific output or bidirectional pins to use the ORP bypass LOCK Assigns device signal names to specific package pins LOCK BFM Assigns I O pins to a Big Fast Megablock BFM LOCK_GRP Assigns I O pins to a Global Routing Plane GRP OPENDRAIN Assigns open drain to specific output or bidirectional pins OUTDELAY Delays the output buffer by 0 5ns for selected output or bidirectional pins PULL Allows specific external pins to use the pull up or datahold function on the device SLOWSLEW Assigns slow slew rate to specific output or bidirectional pins VOLTAGE Specifies the output driver on an I O pin isoEXPERT Compiler User Manual 32 Applying Design Attributes Applying Design Attributes Design Attributes are applied to pins nets or symbols in your design as shown in Table 2 1 Table 2 1 Where to Place Attributes MX tomate Supported eves Placement Supported Devices XOR 5000V 8000 Net Net Net Net
113. Property File only the last one for example ECP PATH2 would be applied PA SCP PATH1 PC ECP PATH1 PATH2 p SCP PATH2 Figure B 19 DESIGN E Schematic PROPERTY DESIGN E NET NETA SCP PATHI ENDPROPERTY PROPERTY DESIGN E NET NETB SCP PATH2 ENDPROPERTY PROPERTY DESIGN E NET NETC ECP PATHI PATH2 ENDPROPERTY Figure B 20 Use of Multiple Identifiers in a Property File isoEXPERT Compiler User Manual 306 EDIF Reader Command Line Syntax EDIF Reader Command Line Syntax The edif2laf EDIF reader reads in Design Attributes from a Property File The following is an example of command line syntax to convert your EDIF netlist and read in a Property File edif2laf edif design edif prop design prp The resulting LAF file will be called design 1laf This LAF file can now be input to isSOEXPERT for compilation with Design Attributes The following are options that can be used with the edif2laf command File Formats and Naming m edif edif file name Specifies the name of the EDIF netlist file for edif2laf to read in m fname af file name Specifies a name for the output LAF file from edif2laf The default is the inout EDIF file name m fext laf file extension Specifies a different dot extension for the output LAF file from edif2laf The default dot extension is laf VCC and GND Handling B vcc vcc netor cell name Specifies a name for a Vcc net or cell The default name is VCC m gnd
114. ROPERTY statement and end with an ENDPROPERTY statement Keywords can be all uppercase or all lowercase The keywords for the Property File include e PIN e SYM e PINARRAY e PROPERTY e INST e ENDPROPERTY e NET Objects are case sensitive and must be entered as they appear in the EDIF netlist Attribute names and values can be uppercase or lowercase The and lt gt characters can be used in identifiers Variable names for parameterized attributes must start with the character If your EDIF writer renames a cell in your design use your original cell name in the Property File not the new EDIF cell name For example if you have a macro in your design called MACROA and the EDIF writer renames it to MACROA 1 use MACROA as the cell name in your Property File The following is an example of an EDIF renaming rename MACROA 1 MACROA However if your EDIF writer changes an object or signal in your design you must use the new object or signal name in your Property File For example if you have a signal called N5 in your design and your EDIF writer changes the signal name to N5 1 use the new name N5 1 in the Property File Multiple value IDentifiers MULTI IDs may be separated by commas colons or semicolons Ensure that there are no spaces between the multiple values isoEXPERT Compiler User Manual 288 Design Attributes Design Attributes Design Attributes control how your design is implemented int
115. RT Compiler User Manual 204 Connectivity Window select View gt Analyzer Mode or the Observable icon to display the information from the ISpANALYZER When you click on a macrocell that is listed in the ispANALYZER the assigned observable path displays as a solid line and other observable paths display as dotted lines You can remove an assignment by holding the Shift key while clicking the left mouse button on the IOC The solid line will change to a dotted line You can make a new assignment by holding the Shift key while clicking the left mouse button on the IOG Notice that the observable IOCs are highlighted gt gt Le L Le _ 9 EJ E UY Figure 6 11 Example of Connectivity Window in Analyzer Mode isoEXPERT Compiler User Manual 205 Path Tracer Path Tracer The Path Tracer provides a method for navigating the fan ins and fan outs in a design For example you can start from a known input signal and trace how the signal is propagating inside the device You can follow a signal from its source to its destination as well as from its destination to its sources The Path Tracer window Figure 6 12 has three sections m Fan In Information Shows the fan ins for the selected GLB output pin Dedicated Control Input pin or IOC m Selected Component Shows the selected GLB output pin Dedicated Control Input pin or IOC The equation shows how the GLB connects to outside signals m
116. RTY DESIGN A PIN CLEAR LOCK 42 ENDPROPERTY PROPERTY DESIGN A PIN DOUT CRIT ENDPROPERTY Figure B 5 Identifying Pin Attributes in a Property File In this Property File Figure B 5 note that the original design name DESIGN A is used not DESIGN A 1 preceded by RENAME in the cell construct isoEXPERT Compiler User Manual 295 Attribute Examples Pin Array Attributes Pin Array Attributes are assigned to bus array pins A property may be assigned to all the items in the array or to individual array elements The following examples show how pin array attributes are assigned PROPERTY casel PINARRAY out 2270 CRIT ENDPROPERIY All the items in the array out 2 out 1 and out 0 are assigned the CRIT attribute PROPERTY casel PINARRAY out 2 0 CRIT ON OFF ON ENDPROPERTY The first and third items in the array out 2 and out 0 are assigned the CRIT attribute out 1 is not assigned the CRIT attribute PROPERTY casel PINARRAY in 3 0 LOCK 3 2 ENDPROPERTY The first item in the array in 3 is locked to pin 3 and the second item in the array in 2 is locked to pin 2 The other two items in 1 and in 0 are not locked to pins If the number of values does not match the number of items in the array the matching starts from the left side The remaining items do not have the attribute assigned If there are more values than array items the remaining values on the right are ignored PROPERTY Casel PINARRAY oUut 2
117. Remove one or more attributes for implementation In this case the CRIT attribute is ignored by the compiler IN1 OUT CLK 0 CRIT CLK CLKO LOCK 40 FD11 IN2 OUT CRIT CLK 1 CLK CLK1 TORIS FD11 Figure 2 29 Conflicting Use of CRIT and LOCK Attributes in an ispLSI1032E 70LJ84 isoEXPERT Compiler User Manual 64 Design Pin Attributes Locking Package Pins The LOCK Design Attribute assigns design signal names to specific package pins Synopsis LOCK pin_name pin_number Description The LOCK attribute can be used to assign design signal names to specific package pins Any redundant input pins that are not driving logic after logic optimization are removed along with their associated LOCK attributes Certain combinations of the CRIT and LOCK attributes may cause a conflict resulting in a warning message and one or more of those attributes may be ignored see Figure 2 29 Also do not set RESERVE_PIN and LOCK attributes on the same pin The compiler cannot lock a package pin that has been reserved Example Figure 2 30 is an example of the correct use of the LOCK attribute CLK CLK2 LOCK 42 Figure 2 30 Correct Use of the LOCK Attribute Certain combinations of LOCK attributes may result in a non optimal design implementation Figure 2 31 A is an example of improper use of the LOCK attribute a single AND gate is locked to two different megablocks at the input and output sides Figure 2 31 B s
118. SERVE LOWPOWER SCP ECP SLP ELP STP ETP STRATEGY If your primary consideration is achieving the fastest possible design do the following 1 Specify STRATEGY DELAY to reduce the number of logic levels globally Try to keep the design at one level 2 Remove PRESERVE attributes wherever possible to allow the compiler to remove nets during optimization instead of forcing the nets to a GLB or IOC output 3 Specify CRIT to use the ORP bypass on the outputs that need to take out fast signals not valid on ispL SI 5000V or 8000 devices opecify SCP ECP to mark all appropriate paths as critical opecify LOWPOWER OFF to turn on all turbo bits opecify STP ETP to mark appropriate paths as turbo and critical paths Hemove SLP ELP from all paths so they are not considered Low Power Try different levels of EFFORT Oi OR Other Design Attributes can also be used to achieve faster speed Larger values of MAX GLB IN normally results in a wider logic and less GLB levels No minimize paths SNP ENP along with the PRESERVE attribute can also be used to closely duplicate implementation of a piece of logic in a certain way to meet specific design requirements Asynchronous paths SAP EAP can be used to correct timing problems caused by signal skew Design Runtime and Memory Requirements The ispEXPERT software typically requires a reasonable amount of runtime and memory This requirement is highly design dependent To improve runtime and me
119. SI 3000 and 6000 device families This takes advantage of the large number of inputs in the device for a minimum level implementation of logic Exercise caution when wide input logic exists in a design and a large MAX GLB IN value is used A large MAX GLB IN value can easily consume inputs common between GLBs ina Twin GLB 8000 and 6000 device families requiring some GLB outputs to remain unused This can result in an unfittable or unroutable design Specifying MAX GLB IN 68 results in maximum use of device resources in the ispL Sl 5000V device family This usually results in the minimum level implementation of any wide logic However it also causes an increase in placement and routing difficulties for the design Placement and routing may then take more time or may fail Specifying MAX GLB IN with a smaller value may increase routability Specifying MAX GLB IN 44 results in maximum use of device resources in the ispL Sl 8000 device family This usually results in the minimum level implementation of any wide logic However it also causes an increase in possibilities of routing failure specifying MAX GLB IN with a smaller value may increase routability isoEXPERT Compiler User Manual 138 Compiler Control Options MAX GLB IN does not limit inputs to GLBs that accommodate clock logic hard macros or protected logic n NOTE Use smaller values for MAX GLB IN to increase routability However this may also increase the levels of delay and
120. SPBEADJI eco DO sd0 Dur of edif lmc verilog vhdl viewlogic p part name prop edif property file qd r par file s a d Al t timing file ta off on y pin file z xor C mgl low high design name Definitions Each dpm option corresponds to a compiler option as shown in Table 4 1 Each compiler option is described earlier in this chapter beginning on page 131 Table 4 1 dpm Commands and Compiler Option Equivalents 2 onini if edif laf pla viewlogic me i cp 1 MAXSPREAD BFM PACKING FOR ROUTABILITY cg 0 10 SINGLE PT FUNCTION PACKING FOR ROUTABILITY USE INTERNAL TRISTATE IO DRIVER ON of edif Imc verilog vhdl OUTPUT FORM viewlogic p part name PART prop edif property file PROPERTY FILE isoEXPERT Compiler User Manual 165 Invoking the Compiler from the Command Line Table 4 1 dom Commands and Compiler Option Equivalents 4 BNENEDRWRE sjelen ini on Turn off XOR alow rh Examples dpm if edif i my design edn dpm if pla i adder pla dom i OI SL adder edn OE Verrlog OG FL dpm if edif i adder edn r unique name par dpm if edif 1 input edn of viewlogic t file name dom if pla i adder pla y adder ppn dpm a pla 1 adder pla r 7 aedgdercppn dom if viewlogic my design isoEXPERT Compiler User Manual 166 Invoking the Compiler from the Command Line Script Files When either the ispEXPERT Design
121. Select Tools IspEXPERT Physical Viewer to use the Physical Viewer with the current design Refer to Chapter 6 The Physical Viewer for details isoEXPERT Compiler User Manual 117 Downloading Your Design onto a Device Downloading Your Design onto a Device Once you have compiled your design successfully and are satisfied with the results you are ready to program the design onto a Lattice Semiconductor ispL Sl device The ISDEXPERT software on PC allows you to quickly and easily download your designs onto Lattice Semiconductor ISP devices If you are using a PC make sure you loaded the ISP Daisy Chain Download ispDCD software into the same directory as the isoOEXPERT software ispDCD is only available for PCs To download onto a Lattice Semiconductor ISP device from a PC Select Tools gt ispDCD from the Design Manager The ispEXPERT software automatically launches the ISP Daisy Chain Download application and its main window appears For instructions on how to download your designs onto programmable logic devices see the SP Daisy Chain Download User Manual Obtaining Project Information Select Project Information to display the Information dialog box This dialog box lets you look at the details of the current project that were obtained from the Create New Project and EDIF Reader Settings dialog boxes If you are working with a PLA design only the first half of the dialog box displays through the Design File Directory f
122. T Compiler User Manual 237 output Pins Pin Name CO QO Ql Q2 Q3 Compilation Report for the ispLSI 5000V 8000 Devices Pin Attribute PULLUP SLOWSLEW PULLUP OPENDRAIN DATAHOLD SLOWSLEW Output Pin Statistics PULLUP OPENDRAIN DATAHOLD SLOWSLEW Sections have also been added to show XOR Preserved Nets ispL Sl 5000V and 8000 devices and the Big Fast Megablock Assignment ispLSI 8000 devices XOR Preserved Nets Net Name S1N226 SINS LZ XOR Preserved ON OFF Net Attributes m Big Fast Megablock Assignment Net Name CO el 13 3 LD EN CLK OS SD SIN312 INODE_START BigFastMegablock 3 Net Attributes OY PR VER Re Iu A E Post Route Design Implementation Section The Post Route Design Implementation section summarizes resource usage in the design after successfully routing For an ispL Sl 5000V or 8000 device design this section provides information in the order of Big Fast Megablock inputs outputs and fast interconnect signals drivers and fanouts for internal tristate nets GLB equations for each Big Fast Megablock pin and clock assignments summary GLB statistics maximum level trace table and pin assignments The summary contains additional information showing total number of macrocells in the design number of macrocells for input registers ispL Sl 5000V number of macrocells for backdoor input registers ispLSl 8000 occupied and available macrocells and product terms If the LOW PO
123. T Undo Zoom Area Returns zoomed area to the previous t magnification Equivalent to View Undo Zoom Area isoEXPERT Compiler User Manual 319 Timing Explorer Pull Down Menus Print Print Preview Print Setup Exit pks PERT Timing Viewer File Pull down Menu Add Remove Sort Edit Pull down Menu w Tool Bar w Status Bar v Signal Navigator Timing Matris T able Frequency T able Setup and Hold T able Teo Path T able Tpd Table View Pull down Menu Menu and Icon Reference Window Cascade Tile Honzontallg Tile Vertically Arrange Icon Window Pull down Menu Help Help Topics About spEAPERT Timing Viewer Help Pull down Menu isoEXPERT Compiler User Manual 320 Tool Bar Icons Timing Viewer The following table shows the Timing Viewer icons lists their names and describes their function Table 3 4 Timing Viewer Tool Bar Icons os name mem Signal Navigator Timing Matrix Table Frequency Table Setup and Hold Table Tco Path Table Tpd Table isoEXPERT Compiler User Manual Displays the Print dialog box to allow printing of the active file Equivalent to File Print Turns on the display of the Signal Navigator if it has been closed or hidden Displays or activates the display of Timing Matrix Table Equivalent to View Timing Matrix Table Displays or activates the display of Frequency Table Equivalent to View Frequency Table D
124. This information is provided in the explore log report For information about the Explore function refer to Design Exploration on page 98 The ispANALYZER generates a report file and a log file The ispEXPERT software also generates a log file that lists all error messages warnings and informative messages that occurred during compilation isoEXPERT Compiler User Manual 23 ispEXPERT Output Project Files When you create a project in iSpEXPERT a directory is created for the project All the output files are contained within the directory Figure 1 4 shows the project directory structure Refer to Chapter 3 The Design Manager for more details on the files in the project directory Design Source Files Project Directory Explore S Setting Directory rojec i Files AEON ispds run Output Files Output Files Figure 1 4 Project Directory Structure isoEXPERT Compiler User Manual 24 ispEXPERT Output Generally files can be divided into input files and output files as follows Input files EDIF PLA Output files alg ISpANALYZER log file apt ISDANALYZER report file bat batch files created by Explore and Compile these files can be run from UNIX command line for batch processing dpt Detailed timing analysis report edo EDIF format netlist file for simulation gpt Boundary timing analysis report jed JEDEC file fo
125. Timing Viewer Objects can be selected either in the connectivity views or in the Design Navigator window The Physical Viewer shows the design implementation details for a successfully compiled project The design implementation details are characterized in two groups the usage of logic resources and the connectivity across those logic blocks It shows how the design logic is implemented in the device using the GLB IOC and Dedicated Control Input logic resources It shows how data is being propagated between the logic resources by displaying point to point routing information at the GLB level It also lets you graphically view and set isoANALYZER node connections The Physical Viewer provides access to the Timing Viewer so you can query for a variety of timing information and view it in tables You can control what information is displayed and how it is displayed by selecting view modes and by selecting the GLB GLB output pin IOC or Dedicated Control Input pin for which you wish to see information The Physical Viewer is described in the following sections of this chapter m Running the Physical Viewer Design Navigator Window Connectivity Window Path Tracer Obtaining Additional Information isoEXPERT Compiler User Manual 192 Running the Physical Viewer Running the Physical Viewer The Physical Viewer is accessed from the ispEXPERT Compiler Design Manager by selecting Tools ispEXPERT Physical Viewer When the Physical Viewer
126. Update dialog box Figure 3 24 displays Post Compile Update Pull Slow Slew Open Drain CutDelay Voltage Turba Speed Show Ping Fin Name v Input v Output v Bidirectional PulVaue Pull Off PulHold El Actions Update Cancel Help Figure 3 24 Post Compile Update Dialog Box 2 Click the tab corresponding to the attribute you wish to set Use the Show Pins area to filter the pin listings if necessary Click on the pin s you want to change 3 Use Add and Remove to move pins between the unassigned and assigned lists Pull Up Pull Off or Pull Hold to change the Pull attribute or Turbo On and Turbo Off to change the LowPower Turbo attribute for that specific pin for ispL SI 5000V and 8000 devices You can assign Turbo On to a signal to override a LowPower On setting Similarly a Turbo Off assignment overrides a LowPower Off setting Refer to Local Speed Power Control on page 53 for details on Turbo settings isoEXPERT Compiler User Manual 113 Post Compile Changes If you select the Speed tab other speed grades of the selected device display Select a different speed grade from the list Changing the speed grade only changes the sim output file that is used for Timing Analysis Design compilation implementation is unchanged Click Actions to display the Actions dialog box Figure 3 25 Check whether you want to update attributes update speed or update both When you
127. WER device option is set to OFF it also shows the number of turbo product terms The number of turbo product terms and control product terms is also included in the GLB descriptions The following examples are from a larger design with LOWPOWER OFF The following is an example of the Post Route Design Implementation summary showing information about macrocells GLBs IOCs GLB levels Big Fast Megablocks internal tristate nets product terms Big Fast Megablock tracks and GRP tracks in the design isoEXPERT Compiler User Manual 238 Compilation Report for the ispLSI 5000V 8000 Devices Post Route Design Implementation Number Number Number Number Number Number Number Number Number Number Number Number Number Number Number Number Number of OF OT Od apa GE OT OE apa GE OT Ode Or OF OF OE OT Macrocells 552 Macrocells for BackDoor Input 0 Occupied Macrocells 332 Available Macrocells 508 Nets SUE GLBs 33 TOCSS 296 Cone Low inputs 2 GLB Levels 5 Product Terms 700 Turbo Product Terms 700 Occupied Product Terms 1328 Available Product Terms 2032 BigFastMegablocks 9 Internal Tristate Nets 32 BigFastMegablock Tracks 402 GRP Tracks 150 The Post Route Implementation section includes Number of Macrocells for Input Register For ispLSI 5000V devices only This line indicates the number of macrocells used by the design as input registers to the Global Routing Pool GRP Number
128. WSLEW PULLUP SLOWSLEW PULLUP OPENDRAIN Pin Statistics T e Pin Attribute PULLUP PULLUP PULLUP LOCK 55 PULLUP LOCK 25 PFULLUP PULLUP PULLUP PULLUP PULLUP EULLUE Pin Statistics Pin Attribute PULLUP PULLUP PULLUP PULLUP PULLUP Pin Statistics Pin Number 2T 26 29 zi D Pin Statistics Tou tg isoEXPERT Compiler User Manual 219 Clock Nets Net Name CEK Preserved Nets Net Name SINS65 S1NA19 INODE START Asynchronous Paths Path Name PATH2 Critical Paths Path Name PATHA No Minimize Paths Path Name PATH3 Compilation Report Clock Specification Net Attributes CLKO Net Attributes Path Description Starting Net Ending Net D1 SIN365 4 Path Description Starting Net Ending Net DO 91N312 Path Description Starting Net Ending Net D2 S1N419 Pre Route Design Statistics Section The Pre Route Design Statistics section is generated after partitioning of the design is complete This report contains the following information Total number of GLBs used in the design Total number of IOCs used in the design Total number of internal nets in the design Break down of IOCs into types Utilization of physical resources in the device Distribution and average number of fanouts per net Distributio
129. a Tco Clock to Output Report design tco Ico Path Report Design Name CNT4 Part Name ispLSI2032E 180LT48 This report lists all the path delays from a primary input that drives the Clock input of a register whose Q output drives a primary output Ico Path Definition Tco Maximum delay from primary input to register clock_pin Maximum delay of register clock to Q Maximum delay from register Q output to primary output TOO Paths Register Source Destination Path Delay Name Reference Clock Primary Output ns GLB QI3 CLK CO 0430 GLB QI3 Cink Q3 4 50 GEB 012 CiK CO 1050 GLB QI2 Cink Q2 6 00 GEB QI 1 GEK CO LO 50 GLB XLI Cink Ol GU GLB QIO CLK CO TOU GLB QIO Cink QO 4 50 isoEXPERT Compiler User Manual 251 Timing Analyzer Reports Tpd Report The following is an example of a Tpd Path Enumeration Report design tpd Tpd Path Report Design Name CNT4 Part Name ispLSI2032E 180LT48 This report contains the path delays between the primary inputs and primary outputs of the design with no register in the path Tod Patis Source Destination Path Delay Input Output ns EN CO e 00 CT CO 900 isoEXPERT Compiler User Manual 252 Timing Analyzer Reports Selected Path Summary Report Example The following summary report design spt is generated by the Timing Analyzer When All or Maximum Number is selected in the Analysis Path Criteria area of the Timing Analysis Path Selection dialog box If Longest Shortes
130. aSr kikkri 270 Es ORRE EEE ENE RN 275 Improving a Working Design 1 0 ce ee rn 276 d ure mE ERE NT R 4S OEE EERE ERS 277 Design Runtime and Memory Requirements 0 0000 eee eee eee 277 LOSION FUIS EERSTE EEE EE ee ee 2 0 EG q au 49 3 4 640544444 34 o3 EERO Od eee es 278 Output Enable Signals EE 279 Gona eg EEE EE 279 Generic Logic Blocks and Megablocks ispLSI 1000 2000 and 3000 Devices 279 Modules ispLSI 6000 devices 0 0 nn ees 279 MB oad aoe en ba 4 se a Pt eee ee EE ae ee eee ee one ge se beeen 280 LU acm id ee E ee eh ROR Ee ee od oe SEE ee EX 280 Designing for isoLSI 5000V and 8000 Devices 0 0 00 281 Considerations for isoLSI 5000V Devices 0 0 00 ee eee 281 Considerations for ispLSI 8000 Devices 0 0 00 ce ee eee 281 ispLSI 8000 Tristate Usage 0 ees 282 Appendix B EDIF Property File 0 0 ccc cece eee 283 Scope and Precedence RuleS 0 ee ee eee ees 284 SA 0 EE a ae aa ee ere nee ee SE EEE EE ER EEE 284 EDIF Property AE EEE 286 Cea LEM EEE EEE EE 286 SJELEN EE 172 288 BS EE EE EE SEN REA RE EN ER 289 EG eo EEE EE EE EE E S 289 ispEXPERT Compiler User Manual 9 Pin Array Attributes Luar 4 240218 B2 4 3 RCRRURORROR ee Ac dr EERE REE EE ee eee UE d 290 agg ee ee eee ee ee EET ee ARS RR RN RC RO Rd 291 JE EE aua xd oh a e he 20937373 4 EE 292 EL aua d acida ada EGE EU He PE EE SEED bees os ee T 293 ADUE en EEE EE N
131. able Figure 5 17 You may wish to tile or cascade the tables for easier access You can agjust the column widths by moving the cursor to the line at the right side of the column heading and dragging it to change the column size Once the tables have been created you can move between the tables or redisplay a closed table using the View menu or the Timing Matrix Table Frequency Table Setup and Hold Table Tco Path Table and Tpd Table icons from the tool bar If you select these icons before requesting a table through a popup menu the table displays but it does not contain any data You can also close a table or the Signal Navigator by deselecting an icon or a menu item on the View menu Timing Matrix Table CNT4 ETE GT EXTES IDE TOR ELLE RECTA LEE Destinations x mm o on mm A20 BENE 1905 90 15 40 16 4 D 460460 460 Pee 6 40 15 4 D 4 60 46 m ETE 6 40 16 4 D 4 6044 600 9 109 100 9 109 100 680 1 90 1 90 16 30 1D p 5 2044 90D 9 705 200 9 705 200 9 70 40 1904 80 190 80 gt PS D 5 20 4 90D 9 905 200 9 70 5 20D 9 70 9 40 ED p 5 20 4 900 9 705 200 8 70 5 2 ya fo ENTE OoOo o om Q2 CO 8071 BEEN 90711 T e c EE ME Bi pp8970970 oe D 970970 Fa EN m 5205200 9 709 700 9 709 700 9 70 89 70 7 00 7 0 DSD 520520
132. ac bg abe fC M i mom p EN Figure 2 32 ispLSI 8000 Big Fast Megablock Architecture isoEXPERT Compiler User Manual 67 Design Pin Attributes Locking a Signal to a Global Routing Plane The LOCK GRP Pin Attribute assigns design pins to a specific Global Routing Plane GRP or to any GRP in an ispLSI 8000 design Synopsis LOCK GRP GRP index where GRP index is 0 through 5 Assigning a GRP index number is optional In the Constraint Manager the optional setting is ANY Description Each ispL Sl 8000 device contains six GRP tracks that interconnect the Big Fast Megablocks The six GRP tracks are numbered left to right 0 through 5 as shown in Figure 2 33 Garo OF UE F3 Ps ee B RB HH t TF Figure 2 33 ispLSI 8000 Global Routing Plane Architecture The LOCK_GRP Design Attribute can be used to assign design pins to a specific GRP For example LOCK GRP Signall 0 assigns the I O cell s1gna11 to GRP 0 Using LOCK GRP without an index number allows the compiler to assign the I O cell to any GRP in the device For example LOCK GRP signall instructs the compiler to assign the I O cell signa11 to a GRP but allows the compiler to select the GRP based on resource availability Any I O cells that are not locked to a specific GRP with the LOCK GRP attribute are assigned by the compiler at random isoEXPERT Compiler User Manual 68 Design Pin Attributes Reserving Package Pins The RESERVE
133. ach pin m Pin assignment for each pin m Type of pin and any pin Design Attribute assigned except LOCK Design Attribute The following is an example of the Pin Assignments table from the Post Route Implementation report Pin Assignments Post Compile Update Pin Name CO QO QUE Q2 Q3 CD CL CLK DO D1 D2 D3 EN LD PS XRESET Pin Assignment Pin Type Pin Attribute 13 Output PULLUP SLOWSLEW OPENDRAIN 25 Output PULLUP 34 Output PULLUP SLOWSLEW 33 Output PULLUP SLOWSLEW 9 Output PULLUP OPENDRAIN 10 Input SUBBUE il Input PFULLUP 5 Clock Tnput PULLUP DE Lnpu t PULLUP 2 Input PULEUP 40 Input PFULLUE 349 Input PULLUP Tp Input PFULELUP 41 Input GJSUBBUP 2 3 Input PFULLUP S Global Reset isoEXPERT Compiler User Manual 232 Compile Results Pin Assignments Pin Name CI Di CLK Q3 CD EN CO ES QO Q2 Ql DO D3 D2 LD Pin Assignment O N ES ld LS 2 3 25 93 34 55 50 40 47 Compilation Report Pin Type Pin Attribute bru BUBBUE LAP PULLUP Clock Input PULEUP output PULLUP Lnput PULGUYUP Inpude PULGUP Output SLOWSLEW PULLUP Taput PULLUP Outputs PUELUP Output SLOWSLEW PULLUP Output SLOWSLEW PULLUP Input PULLUP LINOUU PUELUYP TNPUt PUCLUP Input PULELUP isoEXPERT Compiler User Manual 233 Pre Route Design Implementation Section Pre Route OF Of Od Of OF Number Number Number Number Number Compilation Report The Pre Route De
134. age of IOC registers Do not lock outputs using the same output enable OE signal to different megablocks for the 1000 family of devices ispLSI 3256 devices and ispLSI 6192 devices This forces duplication on the OE signal and uses OE resources Do not lock two or more external inputs to the same GLB if they are from IOCs that are a multiple of 16 apart This forces the addition of a logic level For example pin 26 1 00 and pin 45 1 016 cannot supply signals to the same GLB in an ispLSI 1032E LJ84 device Do not lock two or more external outputs supplied by the same GLB to IOCs that are a multiple of 4 apart For example pin 26 IOO and pin 34 IO8 cannot receive signals from the same GLB in an ispLSI 1032E LJ84 device Do not lock signals to the ISP pins if you are using the ISP option Some dedicated inputs become unavailable for routing if the ISP option is enabled For an ispLSI 1016 ispL Sl 2032 or ispLSI 2064V 44 and 48 pin device selecting the ISP option causes some pins and dedicated inputs including Y2 to become unavailable for use by the compiler Do not reserve more pins than are required isoEXPERT Compiler User Manual 278 Design Rules Output Enable Signals m Do not use more than one OE signal per megablock for the 1000 family of devices isoLSI 3256 devices and ispL Sl 6192 devices m The OE signal must reside in the same megablock as the IOCs to which it is connected for ispLSl 1000 2000 and 3000 d
135. ain OutDelay Reserve Pin Slow Slew and Voltage The availability of these attributes is determined by the device being used The Pin Attributes are Summarized in Table 3 3 Table 3 3 Pin Attributes ete petat Deserpton 00 CRIT Off Assigns specific output or bidirectional pins to use the Output Routing Pool ORP bypass Use for GLB outputs that require the least possible delay OpenDrain Off Specifies output or bidirectional pins to use open drain feature OutDelay Off Delays output buffer by 0 5ns for selected output or bidirectional pins to minimize noise Specifies use of I O pin pull up or datahold features Heserve Pin Off Heserves the identified package pins and prevents them from being assigned by the compiler olow Slew opecifies slow slew rate for output and bidirectional pins Voltage VCCIO Sets the output driver on an I O pin to 3 3V or 2 5V To assign pin attributes using the Pin Attributes dialog box 1 Select Assign Pin Attributes or the Pin Attributes icon from the Design Manager The Pin Attributes dialog box appears with the Pull attribute displayed The Pull dialog box Figure 3 9 has one list box with the pin name and the current Pull setting The other dialog boxes Figure 3 10 have two list boxes The list box on the left shows the names of pins that do not have that attribute set The list box on the right shows the names of the pins that have the attribute set isoEXPERT Compiler User M
136. albi Signal Mame alg Register Output fe Ves Cos Feedback fe ver FG Humber of GLB Inputs ti H of Product Terms Used f Figure 6 20 GLB Pin Information Dialog Box Utilization 00 GLB Pin Information Utilization Function HOL Format Equation Ola glb01 O0 glb01 17 CDA glb01 10 LEX gib HESET RESET gib I5 Ds glb01 CLEO CLEA Figure 6 21 GLB Pin Information Dialog Box Function isoEXPERT Compiler User Manual 211 Obtaining Aaditional Information Statistics You can access design usage statistics Figure 6 22 and the device statistics Figure 6 23 by right clicking anywhere except on a GLB a macrocell an IOC or a Dedicated Control Input pin in the Connectivity View or in the top levels of the Design Navigator and selecting Utilization or Resources from the pop up menu Statistics Utilization EE No of External Pins Used No of GLBs Used 3 8 3 22 Mo of OCs Used 14 32 4 3 Ma af Dedicated Control Inputs Used 2 6 334 Ho of Macracells Used 8 32 25x Figure 6 22 Statistics Utilization Statistics Utilization Resources Part Mame ispLSl2032 190LT 48 Ma of External Pins No of GLBs Ma of IOCs Ma of Macracells No of Clocks Figure 6 23 Statistics Resource isoEXPERT Compiler User Manual 212 Obtaining Aaditional Information Observability Information for GLB Pins When you click on a GLB Pin in the Connectivity
137. ames for all the GLBs IOCs Dedicated Control Input pins and GLB output pins Actual and potential observability connections between the macrocell and an IOC Timing information that is available through queries isoEXPERT Compiler User Manual 196 3 lo e le D Connectivity Window Zn NOTE If your design uses an ispLSI 6000 device the modules are included in the diagram in the Connectivity window You may also open additional Connectivity windows to provide different views using the Window New Connectivity Window menu item The Connectivity windows can then be cascaded or tiled using the Window menu As you move the cursor over the GLB IOC Dedicated Control Input or GLB output pin its name and pin number display in a tip bubble You can locate nodes in the Connectivity window in two ways m When you click on a node in the Design Navigator select Go to Connectivity View to highlight the node in the Connectivity window m Use the Locate icon or the Locate Object command from a right click pop up menu to display the Find Object dialog box Figure 6 4 Use this dialog box to search for a signal or instance When it is found it will be highlighted in the Connectivity window Find Object Component to Search Locate by name v Match Case Cancel Search W Signal Name v Device Instance Names v Design Instance Names All Figure 6 4 Find Object Dialog Box The View menu and the Zoom Bar pr
138. and resource utilization 270 PULL 33 72 92 159 276 289 290 R Reader EDIF settings 81 Registers 208 REGTYPE 33 62 293 Replace Edit 122 Reports 214 251 4 bit counter example 215 6192 261 Clock Frequency 181 248 Compiler 216 Compiler ispLSI 5000V 8000 237 Detailed 181 Index files 23 Module 181 Selected Path Boundary 258 Selected Path Detailed 255 selected Path Summary 253 Setup and Hold 181 250 Summary 181 Tco 181 Tpd 181 252 RESERVE PIN 33 69 293 Reset design rules 279 global 154 Resistors open drain 158 pull up 159 slew rate 161 Resource information 207 Resource utilization optimization 269 Results Clock Frequency Table 181 compiler log 108 Explore Matrix 101 ispANALYZER 117 menu 311 315 Pin Layout 110 Setup and Hold Table 181 Tco Table 181 Timing Report 182 Tpd Table 182 Retain Settings 120 Routability optimizing for 270 Rules design 30 264 S SAP EAP 33 45 47 292 and resource utilization 270 oave As File 121 save As Setting for a project 104 oave Pin Assignments 96 Schematic capture vendor 81 SCP ECP 33 50 292 and resource utilization 270 and speed optimization 277 screen changing your desktop 124 Script files 167 isoEXPERT Compiler User Manual 335 search replace 122 SECURITY 162 276 select Setting project 105 selected Path Boundary Report 182 258 Selected Path Detailed Report 182 255 Selected Path Summary Report 182 253 session Log changing message colors 126
139. anual 92 Specifying Pin Attributes Pin Attributes Pull Slow Slew Open Drain CutDelay Voltage Reserve Fin Show Fins Fin Mame v Input Iv Output v Bidirectional PulVaue o CD H Pull Off Pull Hold b Pin Attributes Full Slow Slew Open Drain OutDelay Voltage Reserve Pin Show Fins Pin Name po T input I I Output v Bidirectional Open Drain OFF Open Drain ON Add All Fr Tenes Cancel spon Help Figure 3 10 Pin Attributes Dialog Box Other Attributes 2 Click the tab corresponding to the attribute you wish to set The screen shows the pin types lnput Output and Bidirectional that use the attribute The Show Pins area lets you limit the pins that display in the list boxes To filter or not show a particular type of pin deselect the box If you type a string into the Pin Name field the lists change to reflect the pin names that match the string you typed This area is not enabled when you select Reserve Pin isoEXPERT Compiler User Manual 93 Specifying Pin Attributes 3 Click a pin you want to change The pin is highlighted and the Add button is enabled For the Pull attribute the buttons Pull Up Pull Off or Pull Hold are used to assign the appropriate value for that pin 4 Click Add and the signal moves to the list on the right For the Pull attribute click on the button corresponding to the value you want to set 5 Click Apply
140. ared pin in an isoLSI 5000V device Description The TOE IO shared pin in the ispLSI 5000V device can be defined either as a TOE Test Output Enable or as a regular IO pin The default setting of OFF indicates the pin will be a TEST OE pin ON indicates the pin will be used as a regular I O pin You cannot lock to pin IOO unless you set TOE AS 10 to ON Design Manager Sequence Assign Device Select TOE AS IO Parameter File Syntax TOE AS IO ON OFF Command Line Syntax NA isoEXPERT Compiler User Manual 152 Global Device Options Setting the Global Reset Pin The USE GLOBAL RESET Compiler Option makes the global reset pin available for use by the compiler Default is ON This option is available for the 1000 2000 3000 and 6000 device families In the 5000V and 8000 device families this option is always ON and cannot be turned off Description When USE GLOBAL RESET is set to ON the compiler tries to move an input pin to the global reset pin under the following conditions m Allthe reset signals are driven by a common pin except in the ispL SI 5000V devices This pin is either unlocked or is locked to the global reset pin by the user This pin drives only PT reset signals and does not drive other logic This pin drives a buffer an inverter or a 2 input OR gate which drives asynchronous reset of all the registers If these conditions are satisfied the input pin is moved to the global reset pin If more than one such
141. b doc xk de GO La ue Og dE ON Da he doe hg OON ji x seo bye oe DS du de due c bep gs epe Og wing ON Lu Ge ue Che ON Pis lurborPilTs Ims POs 2 Ls bevels Turbo 4 PT Pr T PI LI E PI BBB PTSABP The last significant difference for an isoLSI 5000V 8000 device design report is in the pin assignments section where if PULL HOLD is specified as a local pin attribute it is displayed as DATAHOLD The following example is from the first smaller design to show pin assignments with DATAHOLD nts Pin Assignment A18 AJ2 AJ3 B2 B3 B4 C3 C4 G5 C6 D3 D4 D6 D7 E Pin Type Pin Attribute Clock Input DATAHOLD Output SLOWSLEW DATAHOLD Output SLOWSLEW DATAHOLD Output OPENDRAIN Inputs PBPULLUP Input DATAHOLD DLnput PULEUP Input DATAHOLD Input PUELUP Input DATAHOLD Input DATAHOLD Output OPENDRAIN Input DATAHOLD Input PFULLUP Global Reset isoEXPERT Compiler User Manual PULEUP PULEUP 247 Timing Analyzer Reports Timing Analyzer Reports This section shows the reports generated by the Timing Analyzer Frequency Analysis Report The following is an example of a Frequency Analysis Report design mfr Frequency Analysis Report Design Name CNT4 Part Name ispLSI2032E 180LT48 Ihis report contains the maximum frequency at which the design can be operated It also lists the path that determines the maximum frequency and the number of GLB levels Ihe remai
142. c for the vendor type in the name of the timing file to be generated You can save different versions of the wirelist file by entering different timing file names here The default is timing 1 Do not use the name of the design as the timing file name as that will overwrite your design 1 wir file 5 Click OK To run the EDIF writer Select Interfaces gt EDIF writer from the Design Manager The ispEXPERT software generates a design edo netlist file The vendor and file extension chosen in the EDIF Writer Settings dialog box determine the output netlist format for EDIF files To run the Verilog writer Select Interfaces gt Verilog writer from the Design Manager The ispEXPERT software generates a design wvlo netlist file To run the VHDL writer Select Interfaces gt VHDL writer from the Design Manager The ispEXPERT software generates B design vho netlist file for non VITAL Max Delay simulation B design vhn netlist file for non VITAL Min Delay simulation m design vto netlist file for VITAL compliant simulation isoEXPERT Compiler User Manual 89 Specifying a Device Specifying a Device You can change the device at any time when the project is open or being created You must recompile when you change the device You may want to change the device if you want to use a device other than the default or if you determine that the design would fit better in a different device To change a device 1 Select Assign gt Device f
143. case insensitive The keywords are XRESET and XTEST OE A keyword used in a design is converted to an internal name in the implemented design and may not be accessible in its original form Avoid using keywords as user specified names in a design Duplicate Names You should use unique names throughout your design instead of repeating names If a name is repeated in different contexts ispEXPERT may remove or modify the name before generating the correct output For example a particular name may not be used as an external pin name as well as an internal net name or instance name in schematic entry systems Reviewing the log and report files is the best method of identifying and correcting this situation Optimizing Your Design In general optimizing a design for speed delay usually implies using more logic resources Similarly optimizing a design for resource utilization usually implies lower speed These objectives are often contradictory there is a trade off between area optimization and delay optimization The time required to compile very large or dense designs can be significant In some cases you may need to maximize the efficiency of the compiler to minimize the time required to complete your design The remainder of this section provides guidelines for design optimization isoEXPERT Compiler User Manual 268 Optimizing Your Design Resizing your Design If the report files indicate that your design is too large for the
144. ccessful 8 2 mA 2 100MHz Successful Successful 8 Successful Successful 8 r2 2 100 MHz el Successful Buccessful 10 5 MA Successful Successtul 8 2 NA gt OT Fa le 23 PR Successful Successtul 8 2 Successful Buccessful 8 4 Successful Successful 8 Successful Ix Successful Successful Successful Successful Figure 3 16 Explore Matrix Compiler Results Figure 3 15 and Figure 3 16 represent the entire matrix for this particular Explore setting The matrix shows both the User Settings and the Compiler Results on one chart The number of occupied macrocells column is the number of macrocells used by an ispLSI 5000V or 8000 design as resources including Product Term Sharing Array PTSA If you print the matrix it may display in two sections depending on the page setup If the matrix is displayed while Explore is in process the Explore Matrix is updated to reflect the latest results each time a compile completes The Results Explore Display Criteria menu item displays the Explore Matrix Criteria dialog box Figure 3 17 so you can limit the results that display in the Explore Matrix to those that satisfy your criteria When you enter ranges for any of these compiler results into this dialog box and click OK the Explore Matrix immediately changes to reflect only the results that satisfy all of the selected criteria The From and To valu
145. ceeded However conflict may occur between pin locking and the use of the BFM attribute If the primary output pin of the function is locked in a different BFM substantial routing delay will be added to the path Example Figure 2 3 shows an example of the BFM attribute assigned to net D with an index value of 0 The entire function would then be mapped to BFM O A BFM 0 B D C Figure 2 1 BFM Design Attribute Assignment isoEXPERT Compiler User Manual 35 Net Attributes Assigning Device Clocks The CLK Net Attribute assigns device clocks to specific clock inputs of GLBs or IOCs Synopsis CLK CEKU CRT CLRZ T CLK TOCEKO TOOL FASTCLK SLOWCLK Description A clock signal is any net connected to the clock input of a register If you do not use a CLK attribute the compiler automatically determines whether nets should use dedicated clock resources or the slower product term PT clocks The CLK attribute can have the following values CLKO Assigns the signal to the dedicated clock line CLKO CLK1 Assigns the signal to the dedicated clock line CLK1 CLK2 Assigns the signal to the dedicated clock line CLK2 Any register clocked by CLKO CLK1 or CLK2 clock signals is automatically placed inside a GLB CLK3 Assigns the signal to the dedicated clock line CLK3 in an ispLSI 5000V device IOCLKO Assigns the signal to the dedicated clock line IOCLKO not applicable for ispL SI 5000V devices IOCLK1
146. cifying REGTYPE also implies which set of dedicated clocks the compiler can use for the register Any register clocked by IOCLKO or IOCLK1 is automatically placed within an IOC not within a GLB if the input to the register is connected to a single fan out input pin If the register input comes from any combinational logic or multi fan out input pin the register must be placed in a GLB You will get a warning if you assign an IOC clock to the clock input of such a register If the register reset input comes from any combinational logic the register must be placed in the GLB NOTE The compiler automatically places registers and assigns clock input pins for you The compiler attempts to place as many registers into IOCs as possible Use REGTYPE when you need to group registers into IOCs or GLBs for minimizing clock skew For example if you have an 8 bit bus you may want to place all of the bus registers in the same relative location All registers can be placed in GLBs or all registers can be placed in IOCs If you assign a dedicated clock pin to a clock the compiler automatically determines where to place the registers driven by the clock In this case the REGTYPE attribute is not required See the CLK net attribute for more information Example lf REGTYPE and CLK attribute values conflict you receive a warning message and the compiler makes the clock and register assignments For example the following combination of attribu
147. cros isoEXPERT Compiler User Manual 47 Path Attributes Example Figure 2 14 displays part of a schematic design Figure 2 15 shows a potential implementation at the end of the compilation process the compiler duplicated the register to improve routability Figure 2 16 specifies the register output as asynchronous thus the compiler would not duplicate the register resulting in an implementation similar to Figure 2 17 SIGNAL2 i IN 1 mr CLK1 1 gt SIGNAL3 a CLK22 Figure 2 14 Circuit Without SAP EAP Before Compilation IN1 IN OUT SIGNAL3 TF a CLK11 I E SIGNAL2 EE T SIGNAL1 CLK22 Figure 2 15 Circuit Without SAP EAP After Compilation isoEXPERT Compiler User Manual 48 Path Attributes SIGNAL2 d INT SAP PATH1 MI EAP PATH1 CLK11 SIGNAL3 es CLK22 Figure 2 16 Circuit Using SAP EAP Before Compilation SIGNAL2 IN1 15 CLK1 1 SIGNAL3 E CLK22 Figure 2 17 Circuit Using SAP EAP After Compilation isoEXPERT Compiler User Manual 49 Path Attributes Specifying Critical Paths The SCP and ECP Path Attributes identify the start and end of a Critical Path m The SCP Design Attribute specifies the Start of a Critical Path Each SCP attribute must have an associated ECP attribute with the same path name m The ECP Design Attribute specifies the End of a Critical Path and does not require a matching SCP attribute y NOTE The STP ETP path attributes also specify that a path is cr
148. ction Packing for Routability Packing option improves routability Minimize GLB Levels Reducing the GLB levels using the Minimize GLB for All Paths Levels for all Paths option may improve routability isoEXPERT Compiler User Manual 271 Improving Routability Table A 1 Design Attributes and Compiler Control Options Continued Design Attribute or Compiler Control Option How to Improve Routability and Device Resource Utilization CRIT The CRIT attribute restricts output routing Some combinations of CRIT and LOCK or CRIT and CLK can result in an infeasible design Remove unnecessary CHIT properties to improve routing SCP ECP Critical Path attributes restrict routing and can decrease resource utilization Remove unnecessary SCP ECP attributes to improve routing and resource utilization SAP EAP Asynchronous Path attributes prevent the router from duplicating GLB outputs thus decreasing routability Remove unnecessary SAP EAP attributes to improve routing SNP ENP No Minimize Path attributes restrict optimization of your design Remove unnecessary SNP ENP attributes to increase resource utilization STP ETP Turbo Path attributes restrict routing and can decrease resource utilization Remove unnecessary STP ETP attributes to improve routing and resource utilization PRESERVE The PRESERVE attribute restricts optimization of your design Remove unnecessary PRESERVE attributes to increase resource utilization SLP ELP LowPo
149. d 8000 device families m OFFindicates no pull and no datahold UP and HOLD are mutually exclusive Both UP and HOLD can be turned off but they cannot be turned on simultaneously The PULL Device Pin Attribute applies to I O pins The PULL local Pin Attribute assigns the PULL attribute to individual pins it overrides the global PULL option By default the global PULL Device Option is set to UP The cell name and pin number of pins with the PULL UP or PULL HOLD attributes are displayed in the Pin Assignments section of the Compiler Report as follows m PULL UP is displayed as PULLUP m PULL OFF is not displayed m PULL HOLD is displayed as DATAHOLD isoEXPERT Compiler User Manual 72 Local Device Attributes Setting Slow Slew Rate The SLOWSLEW Device Pin Attribute specifies individual external output or bidirectional pins will use slow slew rate Synopsis SLOWSLEW ON OFF Description The SLOWSLEW Device Pin Attribute can only be attached to output or bidirectional pins Slew rate control is supported for isoLSI 2000 3000 5000V 6000 and 8000 device families Check the SP Encyclopedia for detailed information about device architecture The SLOWSLEW local Pin Attribute assigns the SLOWSLEW attribute to individual pins it overrides the global SLOWSLEW option By default the global SLOWSLEW Device Option is set to OFF See Setting Slow Slew Rate on page 161 Setting Device Voltage The VOLTAGE Device Pin
150. decrease resource utilization Design Manager Sequence Tools Compiler Settings Move the Max GLB Inputs slide bar Parameter File Syntax MAX GLB IN 2 68 Command Line Syntax m 12 460 Specifying Maximum GLB Outputs The MAX GLB OUT option specifies the maximum number of GLB outputs the compiler is allowed to use for each GLB This applies to every GLB in your design Description The range and default settings for MAX GLB OUT are dependent on the family of device being used The values are 1000 2000 3000 6000 MAX GLB OUT has a range of 1 to 4 for the ispLSI 1000 2000 3000 and 6000 device families with a default value of 4 Specifying MAX GLB OUT 4 results in the maximum use of device resources However it also causes the placement and routing program to work harder and take more time and may result in an unroutable design Use a value of 2 or 3 to improve routability MAX GLB OUT has a value of 32 for the isoLSI 5000V device family MAX GLB OUT 32 results in the maximum use of device resources isoEXPERT Compiler User Manual 139 Compiler Control Options MAX GLB OUT has a value of 20 for the ispLSI 8000 device family MAX GLB OUT 20 results in the maximum use of device resources Design Manager Sequence Tools Compiler Settings Move the Max GLB Outputs slide bar Parameter File Syntax MAX GLB OUT 1 2 3 4 20 32 Command Line Syntax n 112131 4 20 32 isoEXPERT Compiler User Manual 140
151. ding ending point is ignored and a warning message appears However a path specification can include an ending point only in which case any combinational path leading to the specified ending point is considered to belong to the specified path Any path specification with duplicate starting and or ending points for the same path is flagged as an illegal specification Therefore always define multiple paths in a single path specification When path specifications overlap Asynchronous Path specifications override No Minimize Path specifications and Asynchronous Path and or No Minimize Path specifications override Critical Path Turbo Path and LowPower Path specifications involving the same logic The net attribute PRESERVE when used in conjunction with a path attribute impacts the implementation of logic independently For example a PRESERVE attribute applied in the middle of a Critical Path creates a GLB boundary at that point despite the fact that a more efficient implementation of logic could provide a more optimal implementation of the Critical Path Any path going through a register or a 3 state buffer is ignored Any part of a path going through a hard macro is also ignored Any starting or ending point of a path is interpreted as a soft boundary which allows similar gates to be merged over the boundary during the mapping process No global optimization however is performed over the starting or ending points A hard boundary can be def
152. directory with the same name as the settings If you are using a named setting your changes are saved to that setting subdirectory If you did not name the settings they are saved in the project directory isoEXPERT Compiler User Manual 104 Naming and Saving Design Settings To save changes to your existing design setting Select Project Save Setting from the Design Manager If you want to edit another setting in your project you can pick a named and saved setting from the list of settings To select a different setting 1 Select Project gt Select Setting from the Design Manager The Select Setting dialog box appears Figure 3 19 Select Setting Setting Marne Cancel Dee Figure 3 19 Select Setting Dialog Box 2 Choose a setting from the list The setting is highlighted The Do not use Setting Name check box lets you select the default unnamed setting You cannot select a setting name when this check box is active 3 Click OK To delete a setting name click Delete Click Cancel to close the box without loading the setting A CAUTION The names for the project settings should conform to standard OS directory name conventions and limitations Use 8 or fewer characters and no spaces for the name Failure to do so may cause loss of project setting data isoEXPERT Compiler User Manual 105 Setting the User Electronic Signature Setting the User Electronic Signature The ispEXPERT software allows
153. duct Term s Turbo Product Term s Control Product Terms GLB Level s FORE BUE 27609 ORSBX Internal Tristate Output TSI180 2 Inputis B53X YCAIX 1 Fanout s OUTPITSUESAD Product Term s Turbo Product Term s Control Product Term s GLB Level s e ON ND TSII80 B53X amp YCAIX B53X amp YCAIX If the GLB contains feedbacks the GLB equation displays the status of each output with or without Global Reset or Preset and each local feedback If a local feedback has unique logic it will be displayed If a local feedback has the same logic as an output the report will indicate which output has matching logic This is done to avoid repeating logic and to save you time and disk space The following is an example of a GLB with local feedbacks mE GLB Name Big Fast Megablock Number GLB Number GLB glb27 BigFastMegablock 0 lt 5 gt 56 Inputs BOLD ED BELIK L22 9 XBOldlo9 3o0l1 xX 1571 Belz eGo BOol2X LII ABOlS GO BolsxX 1560 QUIEUIA ET 20 YSD GO SBX FI OGIDZI OSES AND 29549 partly 14 0O BackDoor Input s TO Output S 75183 025495 AAND 2549 part0 DO s Go 2024 parto OlZ G3 SOLI pared Ub AG Or Darl Ql MG QI2 Dort Ola 652016 partu O6 ATSIC OA ToT OS STOI 5 QUI isoEXPERT Compiler User Manual 244 Compilation Report for the ispLSI 5000V 8000 Devices 6 Local Feedback s AND 2549 p rtl OSE 63 0124 parti OL2F Gov OL partly TTE
154. e Analyze Nodes lists using the Add All Add Remove and Remove All buttons isoEXPERT Compiler User Manual 179 isoOEXPERT Timing Analyzer Select Source Nodes Node Name Iv Input IY Bidirectional v Register Show Hodes Available Nodes Analyze Modes Add All Add Remon e GLB GIO 00 GLE 24 00 Remove el Cancel Figure 5 10 Select Source Nodes Dialog Box e Click Select Destination Nodes to display the Select Destination Nodes dialog box Figure 5 11 Use the Show Nodes area to filter the nodes to be displayed in the list boxes Move the nodes between the Available Nodes and the Analyze Nodes lists using the Add All Add Remove and Remove All buttons Select Destination Nodes Made Mame M Output Iv Bidirectional v Register Available Modes Analyze Nodes Add All Ada Benare Biene Cancel Figure 5 11 Select Destination Nodes Dialog Box 4 Select Tools gt Timing Analysis from the Design Manager The ispEXPERT jet moves showing that your instructions are processing To terminate the timing analyzer click the Stop icon When the process finishes the icon is disabled 5 Check the Session Log box for a successful message isoEXPERT Compiler User Manual 180 isoOEXPERT Timing Analyzer Timing Analyzer Report Files The following reports may be generated by the Timing Analyzer Clock Frequency Report design mfr shows the maximum frequency at which the design can o
155. e Ed KE E donando hehe de eee CE dod oes ene ae RR 83 Compiler Control LIONS nae chee ek CEA Sheed d ee ERE LESSEN OME CR OR OES 84 Using the Interfaces Menu 1 eee eee teens 88 SR cdg PETE dea ee ee ee eee EET OE 88 KS EGG td s oh oh on Ree hee ee oO eee NTE 88 Specifying a DEV CE et ee ee ee EEE ee 90 Specifying Pin Attributes o ov kee sewn cea eed EE OO Oe 4 EO 09309 8404 EN 92 Fe 1 Ga PETTEE iode dob oi rari Ee Oo e505 dead d 31 a es 95 Rosie GE COOP aa ee eee ee ee EEE er ee er ee re ee ee T 98 Naming and Saving Design Settings llli 104 Setting the User Electronic Signature 1 0 aana aaa aaa eee eee 106 Compiling Your Design s uasa vene dad REE 107 Viewing the Pin Layout a ac og G AG EEE ENA S babe ede ob xo Eo re ER 110 Changing the Pin Assignment 0 0 0 ccc ee n 111 ispEXPERT Compiler User Manual 5 Viewing the Output Netlist Results llli 111 Post Compile Changes PEER EE EN EE 112 ipe siis Pe gi EE TORT TIT TT 112 Changing Pin Attributes s sacando RE HEORRE E Rr a ho CERA GE dor deu y En Kx RA 113 Anand Your Desig sss acad rererere ETERA 115 EDANALTZEIR DISNUG auda 3494 2 4 2 dE Eo d 93 44 303 RAE NE A 116 zu 11 jj REE EEE EEE EE 116 Tools Menu anaunu navn eee ee eee nne 116 Peele Gl EEE EE NE EE NE ET 117 Using the Physical Viewer Li ease ur wee eee eee ede WERE Eee RRS ekke 117 Downloading Your Design onto a Device 1 ees 118 Obtaining Project Info
156. e GLB resources more extensively 9 Increase MAX GLB OUT to allow the compiler to use GLB resources more extensively 10 Remove all PROTECT attributes to allow the compiler to optimize your design better 11 Remove all path restrictions SAP EAP SCP ECP SLP ELP SNP ENP or STP ETP to allow the compiler to use any possible mapping scheme 12 Use hard macros in your design wherever possible not valid on ispL SI 5000V and 8000 devices 13 Use STRATEGY AREA Although these guidelines provide a good starting point for achieving a denser implementation of your design in an ispLSI part the methods employed by ISDEXPERT do not always produce optimum results and unexpected results may occur at times When you encounter unexpected results try different Design Attributes and Compiler Control Options Use caution when trying extreme values for Compiler Control Options or extensive use of one or more Design Attributes This may lead to a denser implementation of your design but may result in an unsuccessful routing Improving Routability Design Attributes and Compiler Control Options control device routing device resource utilization and compiler efficiency Choosing optimal values for routability is a trial and error process due to the complex nature of the compilation process and its dependency on the characteristics of the design The following sections focus on how to choose Design Attributes and Compiler Control Options to ach
157. e Options are summarized in Table 3 2 Refer to Chapter 4 Design Compilation Options for additional information Table 3 2 Device Options gt EN Informs the compiler ON that you want to reserve the ISP pins on an ispL Sl device for programming only Default is OFF ISP EXCEPT Y2 Allows the compiler to use the Y2 clock input for routing Not valid for all devices Default is OFF LowPower selects a lower power mode or a higher power faster speed mode This option is device dependent Default is ON for 8000 devices and OFF for 5000V devices Part Name opecifies the part name of the target device If not specified the default part name is used security Influences the device security cell programming This option does not guarantee the security cell is set or cleared because device programmer options also affect the security cell Default is OFF TOE AS IO The TOE IO shared pin on an ispL SI 5000V device can be defined as either a TOE Test Output Enable or a regular IO pin The default setting of OFF indicates the pin will be a TEST OE pin Y1 AS RESET The Y1 RESET pin is a global reset input when set to ON The Y1 RESET pin is the Y1 clock input if set to OFF This option is device dependent Default is ON isoEXPERT Compiler User Manual 91 Specifying Pin Attributes Specifying Pin Attributes You can assign pin attributes using the Design Manager The pin attributes that can be set are CRIT Pull Open Dr
158. e active file Equivalent to File Print 312 isoEXPERT Compiler Table 3 1 ispExpert Tool Bar Icons os name mem Find Next Searches for the next occurrence of the string specified in the Find or Replace dialog box Help Activates context sensitive help Equivalent to pressing F1 when the item is active otop Tool otops the existing process compile timing analyzer or explore isoEXPERT Compiler User Manual 313 Menu and Icon Reference ISDANALYZER Pull Down Menus Hew Ctrl M Open Ctrl Close Save Ctrl 5 ave As Ctrl Undo Ctrl Cut Ctrl Copp Ctr Paste Ctrl Delete Del Print Ctrl P Print Preview Options Print Setup Clear Messages Open ispaMAL TZEHR Workspace Close ispaMAL TZER Workspace Save IspaMAL TZER Workspace Save IspaMALYTZERH Workspace As Find Ctrl F Replace Chrl H Edit Pull down Menu TEN CHT 4 edo Return to 1gpEFERT Compiler Exit pE FERT Compiler File Pull down Menu w ToolBar w Status Bar v Process Bar W Session Log View Pull down Menu isoEXPERT Compiler User Manual 314 Menu and Icon Reference Tools Observable Node Mapper Made Mapper Settings MW nigor Cascade Tile Vertically Tile Horizontally ISBE FERT Physical Viewer Arrange Icons Split Llose All Window Pull down Menu IspLi Lii Tools Pull down Menu Interfaces Help EDIE writer EDIF writer settings Using Help Index Ve
159. e compiler updates the netlist used by the place and route process Process for determining placement and routing for a design A compiler control option that can change the normal operation of the software when specified differently from its default value This results in a different implementation of the design Rules that govern design entry for names and notations A network whose signal propagation delay is part of the critical path in the design oignals from the dedicated clock input pins that go through the clock distribution network to the global clocks Inputs that bypass the Global Routing Pool GRP and go directly to the GLBs These signals are megablock specific Electronically Erasable CMOS logic Electronic Design Interchange Format Input signals from lOs clocks or other GLBs to a GLB The number of destination inputs driven by a source signal A design file that contains a list of E7PROM fuse addresses used by the programming hardware to program the device Fuse map generation process creates the programming file that is used to program a device and is the last step in the design process The basic logic element in the ispL Sl architecture isoOEXPERT System User Manual 325 GLB Clocks GLB Generated Clocks Global Clocks Global OE Global Reset Global Routing Pool GRP Hard Macro Input Output Cell IOC Input Output IOC Clocks ispEXPERT ispLSI JEDEC File Macrocell Macros
160. e design with no register between them Figure 5 4 shows a T pd example IN seminat 3 7 OUT1 Figure 5 4 Tpd Example Tco Calculation The Tco calculation determines the path delays from a primary input that drives the clock input of a register whose Q output drives a primary output The Tco is calculated as ECO maximum delay from primary input to register clock pin maximum delay of register clock to Q maximum delay from register Q output to primary output see Ul Figure 5 5 shows a co example NI D Q _ gt OUT CLK CLOCK Figure 5 5 Tco Example isoEXPERT Compiler User Manual 174 Path Enumeration INA IN3 IN 1 IN2 CLK Timing Analysis Overview The process of identifying all the source nodes for any given destination node and the respective path delays is called path enumeration Typically there could be one or more paths between a pair of source destination nodes Path enumeration enables you to identify the paths on a given output node in detail in order to modify the design to meet timing constraints Figure 5 6 provides an example of path enumeration OUT3 combinatorial gt UR Fonbinar D2 Q2 OUT1 combinar Figure 5 6 Path Enumeration Example Based on this example the following paths are reported during path enumeration Source IN4 IN3
161. e new location For example the graphics in this manual show the process bar moved to the right of the tool bar rather than below it which is the default To turn on or off the display of the isoSmartFlow window Select View gt ispSmartFlow from the Design Manager The ispSmartFlow window displays or is removed To turn on or off the display of the tool bar Select View Tool Bar from the Design Manager The tool bar displays or is removed To turn on or off the display of the zoom bar select View Zoom Bar from the Design Manager The zoom bar displays or is removed If you have the zoom bar turned off it will still display when you open a window with a package view To zoom to a specific area of a package view select an icon or use View gt Zoom gt Zoom In Zoom Out Zoom to Fit from the menu bar The screen changes to reflect your new setting To turn on or off the display of the status bar The status bar is below the session log Select View Status Bar from the Design Manager The status bar displays or is removed To turn on or off the display of the process bar The process bar contains the Stop icon and the jet Select View Process Bar from the Design Manager The process bar displays or is removed To turn on or off the display of the session log Select View gt Session Log from the Design Manager The session log displays or is removed If this is turned on but the session log does not display grab the to
162. e opens If you select Analyzed Work File you can select any of your saved workspaces Close ispANALYZER Workspace Closes the current isoANALYZER workspace Save ISpANALYZER Workspace Saves the current ispANALYZER workspace Save ispANALYZER Workspace As Displays the Save Workspace As dialog box Enter the name for the workspace and click OK The workspace name cannot contain spaces Return to ispEXPERT Closes the ispANALYZER and returns to the ispEXPERT Design Manager If you close the ispANALYZER window instead of selecting this menu item you will exit both the ispANALYZER and ispEXPERT Tools Menu The Tools menu has the following menu items Observable Node Mapper Displays the Observable Node Mapper window if not displayed Node Mapper Settings Opens the Node Mapper Settings dialog box Use the Node Mapper Settings dialog box Figure 3 27 to filter the macrocell names You can select a combination of register nodes combinatorial nodes and macrocell names that begin with specified characters You cannot use wildcards in the Match Node Name field but you can enter as many characters as you need to correctly filter the macrocell names You can also specify whether you want the GLB field to display and whether you want to sort by physical or logical GLB name isoEXPERT Compiler User Manual 116 Using the Physical Viewer Hode Mapper Settings W Combinatorial Nodes Observable Nodes Only A
163. ed for a specific type of implementation objective You can determine which method works best for your design through the use of the STRATEGY attribute STRATEGY AREA tends to produce more routable designs than does STRATEGY DELAY If you select STRATEGY NO OPTIMIZATION neither strategy is applied EFFORT Try different EFFORT levels for best routability LOCK LOCK assigns design signal names to specific package pins However LOCK restricts optimal utilization of device resources Remove LOCK attributes wherever possible for better routability RESERVE PIN The RESERVE PIN pin attribute limits the package pins that can be used during compilation Select Ignore Reserved Pins in the Compiler Settings dialog box to determine whether the reserved pins are preventing a design from routing successfully BFM The BFM attribute impacts packing mapping and placement of the design within the ispL Sl 8000 device BFM Packing for The BFM Packing for Routability Compiler Control Routability Option impacts the number of BFMs into which your design is placed and may result in shorter routing delay However it may cause routing failure Use Internal Tristate IO Turning off the Use Internal Tristate IO Driver Compiler Driver Control Option provides more flexibility to the fitter to fit the design but uses more resources and may add extra delay for related paths Single PT Function Specifying a higher value for the Single PT Fun
164. edifneti and edifneto utilities must be present for this option to work correctly This option is used with OUTPUT_FORM VIEWLOGIC If you specify the name of the output file to be the same as the name of your design you Will get a warning when you run the compiler To avoid problem messages change the TIMING FILE value to a name other than your project name before you run the compiler Design Manager Sequence Interfaces EDIF writer settings Select extension select Viewlogic from vendor information and enter the timing file name Parameter File Syntax OUTPUT FORM VIEWLOGIC TIMING FILE unique name Command Line Syntax t file name isoEXPERT Compiler User Manual 143 Compiler Control Options Specifying a Parameter File The PARAM FILE option specifies the name of an optional Parameter File for the compiler to use for compilation specifications These options are used in place of the compiler control options and device control options Description The Parameter File contains alternate sets of compiler control options and device control options that can be used to run different iterations of your design You can create this file using an ASCII text editor or the ispEXPERT text editor The Parameter File name should have a par extension and must be different than the design name oee Using a Parameter File on page 163 for more information y NOTE Do not use PARAM FILE within a Parameter File This could cause a loop
165. ength of time a data signal must remain stable after the active edge of a CLK see Figure 5 2 Hold time for primary input ports is calculated as follows hold time clock path delay SHORCESE Qata pach delay hold time of register Because of differences in the longest clock path and the shortest data path it is possible for hold time to be negative isoEXPERT Compiler User Manual 172 Timing Analysis Overview Setup and Hold Time Example Figure 5 3 illustrates the setup and hold time calculation for primary input ports For this example the setup time and hold time of each register is 10 The longest and shortest path delay values are the same as those in Figure 5 7 setup and hold time for register FF1 is calculated as follows m The setup time of port IN1to port CLK is 100 20 10 90ns m The hold time of port IN1 to port CLK is 20 100 10 70ns m The setup time of port IN2 to port CLK is 40 20 10 30ns m The hold time of port IN2 to port CLK is 20 40 10 10ns Because there is no port that drives the data pin of register FF2 directly there is no setup time and hold time requirement for FF2 from primary input ports FFI FF2 IN1 C1 C2 IN2 CLK gt combinatorial Figure 5 3 Setup and Hold Time Example isoEXPERT Compiler User Manual 173 Timing Analysis Overview Tpd Calculation The Tpd calculation determines the path delays between the primary inputs and primary outputs of th
166. entation y 1 _ Run Compiler Correct the Error Try another strategy or effort value relax constraints use larger device or reduce logic Try another strategy or effort value relax constraints use larger device reduce logic or try other compiler control options Design Failed to Route Design Simulation Check simulation Unsatisfactory commands and input Try another strategy or mpe menanon effort value or use other Unsatisfactory design attributes Internal Error Call the Lattice Semiconductor Hotline No Design Implementation Satisfactory isoEXPERT Compiler User Manual 265 System Syntax and Specification Errors System Syntax and Specification Errors The most common problems occur because of problems with the installation of the software system errors or during design entry syntax or specification errors System Errors oystem errors are usually caused by corrupted files incorrect file protections incorrectly set environment variables or use of unsupported or unauthorized part names The PDSPLUS environment variable must point to the directory where the iSOEXPERT software is installed If a path variable is specified it should be set to point to the ispEXPERT executables directory The LM LICENSE FILE environment variable must point to the current license file Refer to the ispEXPERT Compiler Getting Started Manual for information on the installat
167. eport 2 cece ee eee eee rh ry 250 BO ea y ek be beeen eed EERE AE ee eee ee bees 251 ispEXPERT Compiler User Manual 8 lesda e l cua ey ee 33 9 3 3 9 90226 3 0 8088 CRUS CREE EUER C RCEORCUL RR Ae ROROORGR RR eee 252 Selected Path Summary Report Example llle 253 Selected Path Detailed Report Example 0 0 0 ccc eee 255 Selected Path Boundary Report Example 0 0 0 0 ccc ee ee ee 258 aede ee S T ae a ee a eee ee ee ITO OT TITIO ee ee ee ee ee 261 Appendix A Design Rules and Tips 0 00 cece cee eee 264 Design Problems 0 2 0 0 0 ce ee ee rra 264 System Syntax and Specification Errors 0 ees 266 EE uu 694 X02 3 9 39 3 3 3 94 EE EEE a ee 266 Reserved File Names 00 0c cc ee eee eee ees 266 SE EEE EEE EEE a eee eee NE 266 Valid Characters 2nuuvar vaar ee ee eee eens 266 Valid Identifiers and Text llli 267 Specification Errors and Problems 0 000 ec ee ee ee ees 268 Attribute and Option Names and Values 0 0 00 cece es 268 SE i a aad VS AUI NE ee ee ee ee ee ee eee ee 268 Duplicate MAING RE ENE EE D 7 07 115 55 1001 T2177 268 Optimizing Your DISSI 244 5044406058 645944604544 GEHE AR UE Y pad 04 Fue A dea 268 Resizing your Design 6 hh 269 Optimizing for Resource Utilization lll 269 improving 611 asasi eo iR ROC Een eR E ER e EUR ee RR ee ee 2 0 Soiree IOTER cle acea doe o dede ikeir ruS r
168. er Manual 26 Designing with ISpbEXPERT uf nenmpnna p i Le P E ELI EL HE Ja a i n e n i Ip n z BP Corp Furnes or ag di UNGE r y Figure 1 5 Logic Resources for an ispLSI 1032E Device isoEXPERT Compiler User Manual Ze Designing with ISpEXPERT Generic Logic Blocks GLB A Generic Logic Block GLB is the basic unit of logic for each device in the Lattice Semiconductor ispLSI families Each GLB contains global inputs dedicated inputs a programmable AND OR XOR array registers and outputs The ispEXPERT software partitions the logic of your design and maps it to the GLBs of the selected device Figure 1 6 is an example of a GLB Inputs From Dedicated Global Routing Pool Inputs N EE EET Product Term 0 1 2 3 456 7 8 9 10 11 12 13 14 15 16 17 Sharing Array D Registers MMM 4 PT Bypass Single PT AND Array Functions CLK 1 CLK 2 PT Clock PT Output Enable To Output Enable Mux Global RESET Control CLK 0 Figure 1 6 GLB Resources for the 1000 Family of Devices isoEXPERT Compiler User Manual 28 Designing with ISpEXPERT I O Cell IOC Each IOC connects directly to an I O pin and can be programmed for combinational input registered input latched input direct output 3 state output or bidirectio
169. er control options and device options determine how a design is compiled These sections describe the compiler control options and device options that can be used to accomplish the tasks listed Device control options are used in your design to determine availability and allocation of resources in the physical device This chapter includes the following sections m Compiler Control Options m Global Device Options m Using a Parameter File m Invoking the Compiler from the Command Line isoEXPERT Compiler User Manual 128 Compiler Control Options Compiler Control Options Compiler control options define objectives for the design implementation process Compiler control options can generally be assigned in three ways through the Design Manager in a Parameter File and as a command line option with the dpm command This section provides a description the Design Manager sequence the Parameter File syntax and the command line syntax for the following topics BFM Packing for Improved Routability Maintaining Pin Direction opecifying Case Sensitivity Controlling Optimization Controlling Routing Time Controlling Pin Assignments Identifying Input Files Controlling GLB Inputs and Outputs Minimizing GLB Levels Creating Netlists Specifying a Parameter File Specifying a Part Number Specifying a Property File Single PT Packing for Improved Routability Performing Batch Mode Timing Analysis Using the Internal IO Tristate Driver
170. er from the Command Line Running the Timing Analyzer from the Command Line The Timing Analyzer command line syntax runs the ispEXPERT Timing Analyzer and generates report files based on the options you select You may include as many of the options as you need in one command The syntax is te peu se FP td GESTA ta design The Timing Analyzer evaluates maximum frequency and setup hold requirements and calculates Tpd path delay values this is the default The reports generated are design mfr design tsu and design tpd f Performs maximum frequency calculation only The report generated is design mfr su Evaluates the setup hold requirements of all the boundary registers in the design The report generated is design tsu tpd Calculates Tpd path delays The report generated is design tpd tco Calculates Tco path delays The report generated is design tco isoEXPERT Compiler User Manual 189 Power Calculation Power Calculation The Power Calculator feature Figure 5 19 calculates the power dissipation of ispLSI 8000 devices in milliamperes mA based on the number of turbo product terms used in the device the number of non turbo product terms used in the device the number of macrocells used in the device the maximum frequency of the design and the Activity Factor defined as the average percentage of macrocells toggled at each clock of the design ICE Dperatren E 1 p le Pat number pple 11008 42
171. er report called design rpt provides information about the environment under which a design is being processed a description of the design and a description of the processed design This chapter contains the following sections m Example Design m Compilation Report e Design Parameters Section e Design Specification Section e Pre Route Design Statistics Section e Post Route Design Implementation Section e Pre Route Design Implementation Section Synthesis and Partitioning Statistics m Compilation Report for the isoLS 8000 Device Timing Analysis Reports e Clock Frequency Report e Setup and Hold Report e co Report e pd Report e Summary Report e Detailed Report e Boundary Report e 6192 Report The sections shown are parts of reports that have been fitted and routed successfully unless otherwise specified The reports are in the format that displays when the file is opened using the File gt Open menu item rather than the way the report displays using the appropriate Results menu option isoEXPERT Compiler User Manual 214 Example Design Example Design This chapter uses the reports from a 4 bit counter design The schematic for the 4 bit counter appears below LD DO ECP PATHI PRESERVE CAI EN CLK PS DI EAP PATH2 PRESERVE CLK FASTC B J cC i ENP PATH3 l PRESERVE QO li ES Q Cn 7 d m Wit EI of EE D3 ZE KE ES E FDTI me i umm es E i isoEXP
172. ers in length In Figure B 15 the schematic shows the path variable definitions applied to the symbol ADDF1 Figure B 16 is the schematic display of the parameterized path attributes Figure B 17 is part of the EDIF file for the schematics in Figure B 15 and Figure B 16 Figure B 18 shows a Property File defining the variable definitions and the parameterized attributes In this example corresponding cell and object identifiers are highlighted in the EDIF file and the Property File BLOCK1 AO SO BO Cl BLOCK2 A1 S1 B1 lt CO Figure B 15 Path Variable Definitions in DESIGN_D isoEXPERT Compiler User Manual 303 BO U3 Cl O i NV AND2 U10 XOR2 1 3 OR2 AND2 4 U2 1 Ut 1 U6 dy AND2 U8 1 U7 2 2 CO AND2 Figure B 16 Macro Definition for ADDF1 in DESIGN D isoEXPERT Compiler User Manual 2 a xm Attribute Examples 304 Attribute Examples cell ADDF1 ceJ dq Voce GENER EC view view 1 viewType NETLIST interface port ZO direction OUTPUT port CO T drrecUuron OUTPUT port AO direction INPUT port BO direction INPUT Dort CI direction SSNPUDS contents cellref ORS Cellrer INV cellref AND2 cellref AND2 viewref view 1 viewref view 1 viewref view 1 viewref view 1 instance U8 instance U4 instance U7 instance U6 A _ A NET CI joined portRef CI
173. erty constructs overwrites the system default Any attributes in the Property File overwrite those already in the EDIF file or the system default EDIF Reader The EDIF Reader is called by the Design Manager when a project using an EDIF design is created The EDIF Reader reads in Design Attributes from a Property File The default EDIF Reader settings can be set by selecting Interfaces EDIF reader settings You can set the EDIF Reader settings for the project you are creating by clicking the EDIF reader settings button on the Create New Project dialog box The EDIF Reader Settings dialog box is shown in Figure B 1 EDIF Header Settings Vendor v Load vendor specific setting Power and Ground Setting YCC GND Representation fe Met C Cell VEC Name vcc AND Mame GND Cancel Bus Reconstruction Array Index Ordering Up C Down Least Significant Bit Left 6 Right v Ground floating output pins Property File E Figure B 1 EDIF Reader Settings Dialog Box Vendor Select the name of the vendor of the third party design tool Turn on the Load vendor specific setting check box to have default settings for the vendor display in the form when you select the vendor isoEXPERT Compiler User Manual 284 EDIF Header Power and Ground Handling m Specify the type of representation for Vcc or GND in the input EDIF file The default representation is a net m Specify a name for a Vcc net or cell The default name is VCC
174. es are read in You can modify the EDIF Reader Settings using the EDIF Reader Settings button on the New Project dialog box or the Update Project dialog box these settings apply only to the project currently being created or updated If you access the EDIF Reader Settings dialog box through the Interfaces menu when a project is open the settings will reflect the open project Refer to page 81 for information on entering information into the dialog box Netlist Output Files The third party simulation tool you use for post compilation verification will determine the type of output netlist file you want If you want to generate another netlist file without rerunning the compiler you can use the Interfaces menu If you set the EDIF Writer Settings prior to opening a project the settings are defaults that display for all projects If you set the EDIF Writer Settings when a project is open the settings apply to that project only To set EDIF writer settings 1 Select Interfaces EDIF writer settings from the Design Manager The EDIF Writer Settings dialog box appears Figure 3 7 EDIF Writer Settings EDIF Qutput File Extension edd Vendor Information VIEWlogic B Timing File Name TIMING cancel Figure 3 7 EDIF Writer Settings Dialog Box 2 Set the EDIF output file extension The default is edo 3 Select the vendor information isoEXPERT Compiler User Manual 88 Using the Interfaces Menu 4 f you selected VIEWlogi
175. es can be the same value Max GLB Level Max Frequency Cancel Figure 3 17 Explore Matrix Display Criteria Dialog Box isoEXPERT Compiler User Manual 102 Design Exploration A right mouse button pop up menu is available within the rows of the Explore Matrix Each row in the Explore Matrix represents a separate Explore run Place the cursor in a row of the Explore Matrix and click the right mouse button The following commands can be used to save the settings for that particular Explore run m Save Setting Saves the options for the selected Explore run in the current setting m Save Setting amp Compile Saves the options for the selected Explore run in the current setting and runs the ispEXPERT Compiler using those settings m Save As Setting Displays the Save As Setting dialog box and saves the options for the selected Explore run in the specified setting m Save As Setting amp Compile Displays the Save As Setting dialog box and saves the options for the selected Explore run in the specified setting and runs the ISDEXPERT Compiler using those settings The Save As Setting dialog box is described in Naming and Saving Design Settings on page 104 isoEXPERT Compiler User Manual 103 Naming and Saving Design Settings Naming and Saving Design Settings After you make Design Attribute and Compiler Control Option changes lock pins and identify successful compilations using the Explore function you
176. eset Module Pin Positive RWL Module Pin Positive Almost Empty 11 Almost Fuld 50 Configuration 512X9 FIFO B to A isoEXPERT Compiler User Manual 227 Compilation Report Pin and Clock Information The Pin and Clock portion of the Post Route Implementation report contains the following information m O Input Output BIDI Registered Combinational type I O name and location of each pin Each I O is followed by a description of the I O source or destinations and connections A list of the global clocks and their types E representing the enable input of a 3 state or bidirectional IOC C representing the clock input of a registered input or bidirectional IOC G representing the enable input of a latched input or bidirectional IOC y NOTE If you are using an ispLSI 1032E device the IOCLKO and IOCLK1 will be used interchangeably in the clock assignment section of the report file isoEXPERT Compiler User Manual 228 Pin and Clock Example Compilation Report The following is an example of the Pin and Clock portion of the Post Route Implementation report Tip ED OT Output CDX 3 Fanout s SEO X EL OIDULrIi GINGER CADUC cl 1028 Output CIX 3 qJanoubts SED OZ doy xpEDOOSuElL2 oglbol loe CLOCK Top GER 30 Output CLKX 3 Fangut s CLDOU ChRO SqIDOlLl ChkR0 glp0s CLK OUT puC LOr 05 Input G1600 03 COX CO COX Input DU LOLS Output DUX 1 Fanout s CH ID02 I2 Lnpuu Dl 1029 Outp
177. esign for errors oynthesizes and partitions Places and routes Produces physical netlists Produces a JEDEC compatible device programming file Generates report and log files Performs observability analysis Design Analysis The Design Analyzer checks for Lattice design rule violations It is automatically invoked whenever a design is compiled The Design Analyzer checks that The design is specified only with valid Lattice primitives and or their derivatives Pins identify primary inputs outputs and bidirectional Os Pins have correct assertion input output or bidirectional No dangling nets are present No duplicate pin names are present Design attributes are used correctly Synthesis and Partitioning The ispEXPERT software uses Design Attributes and Compiler Control Options to synthesize and partition the design to fit into the given device without violating device architecture or design constraints The partitioner performs the following functions Optimizes logic equations by e Performing multi level logic optimization e Identifying XOR logic to take advantage of physical XOR gates in the device e Using XORs to reduce logic through function inversion where possible e Mapping parallel registers into a single register e Optimizing unused registers and inactive logic e Removing unused inputs Clusters the partitioned functions according to common clocks output enable OE signals reset signals and fixed pin propert
178. evices Global Reset Signal m The external reset and preset on ispLSI 8000 devices input automatically connects to every register in the device do not connect internal nets to the RESET pin not valid on isoLSI 5000V devices Generic Logic Blocks and Megablocks ispLSI 1000 2000 and 3000 Devices m Connect a maximum of two dedicated inputs to a single Generic Logic Block GLB m Do not lock dedicated inputs in two different megablocks if they are inputs to the same GLB m Do not use a locked dedicated input and a locked output from different megablocks for the same GLB m Do not use a locked dedicated input to generate an OE in one megablock to enable IOCs in a different megablock for the 1000 family of devices ispL Sl 3256 devices and ispL Sl 6192 devices m An IOC and its OE must be in the same megablock for the 1000 family of devices isoLSI 3256 devices and ispL Sl 6192 devices m A GLB can have no more than 18 inputs two of them dedicated input pins in the ispL Sl 1000 or ispL SI 2000 device families m A GLB can have no more than four outputs two of them can use the ORP bypass in the ispLSI 1000 or ispL Sl 3000 device families m Adedicated input cannot drive more than eight GLBs Modules ispLSI 6000 devices m Port A Data IOs in a RAM must use BIDI 3 state m Slew rate and pull up values must be the same for Port A Data IOs in a RAM and FIFO m Only one PTOE for each module block can be used I
179. f a Big Fast Macrocell to each other and to 24 Big Fast Megablock I O cells with optional registers The mathematics of logic developed by George Boole in the nineteenth century based on the rules and operations of logical functions rather than numbers AND NOT and OR are the primary operations of Boolean logic A button on some screens that opens a dialog box that list files or directories from which you choose Input to a counter that is used to connect the output from a previous stage Output from a counter that is used to connect the input to a subsequent stage An elementary unit of storage for data isoEXPERT System User Manual 324 Clock Distribution Network Clock GLB Command Compiler Configure Control Option Conventions Critical Net Dedicated Clock Input Signals Dedicated Input DI E CMOS EDIF Fan in Fan out Fuse map Fuse Map Generation Generic Logic Block GLB Interconnection location of the clock signals A GLB that can be used to generate global gated clocks to drive GLB or IOC registers A word or series of words used to carry out a directive A command is either selected from a menu or typed at a prompt The ispEXPERT software uses architecture specific methods to synthesize a logic description into a ispLSI device The compiler determines if the logic can fit into the assigned GLBs and IOCs It maps logic to the cells and provides input to the fuse map generation process Th
180. f the Data OUTs of a register are locked to MIOCs they must have the same phase either all inverted or all non inverted isoEXPERT Compiler User Manual 279 Design Rules Nets Each net in your design must have only one source Do not connect internal nets to the VCC and GND pins Do not use VDD or VSS as power sources These nets are not recognized as constants by the compiler m internal tri state nets and buffers are not supported on 1000 2000 3000 5000V and 6000 devices They are supported on 8000 devices Clock Usage m Lock clock signals only to a clock pin if they do not drive other logic m Try not to lock clock signals to I O pins m Do not lock a signal to the Y3 or Y4 pin if the signal is used as a data line m Donotlock a signal to the YO or Y1 or Y2 for the ispLSI 3000 device family pin if the signal clocks IOCs Y1 can connect to an IOC clock in an ispLSI 1016 part m Do not use a signal from an IOC as a fast clock unless it first passes through the dedicated clock GLB m Only one GLB per design can generate internal fast clock signals in 1000 devices A design can have a maximum of two GLB and two IOC clocks from the clock GLB where available m The clock GLB can only use locked dedicated inputs that belong to the same megablock as the clock GLB m design can have a maximum of five global clocks in the ispL Sl 1000 and ispL Sl 3000 device families and three global clocks in the ispL Sl 2000 device family Thi
181. ficant side effects that may result from extensive usage Use Design Attributes in localized areas of a design with specific implementation needs in mind such as timing or observability The Design Attributes described in this chapter control how your design is implemented into the logic resources of the target device Each Design Attribute you add places restrictions on the compiler by giving it less freedom to use available logic resources Apply these Design Attributes carefully to avoid overconstraining the compiler and possibly causing a routing failure Some design attributes are device dependent see Table 2 1 Check the SP Encyclopedia for additional details on the device architecture This chapter presents objectives you may need to accomplish and describes the Design Attributes that can be used isoEXPERT Compiler User Manual 31 The Design Attributes are functionally grouped as follows Net Attributes BFM Places the logic of a specified net into one Big Fast Megablock BFM CLK Assigns clock signals to specific clock lines GROUP Suggests a particular grouping of functions into GLBs PRESERVE Prevents removal of a net during logic optimization XOR Preserves user specified XOR gates during logic optimization Path Attributes SAP EAP Specifies the Start and End of an Asynchronous Path SCP ECP Specifies the Start and End of a Critical Path SLP ELP Specifies the Start and End points for toggling a Low Power
182. for device utilization and consequently may use more logic levels gm NOLOGIC OPTIMIZATION takes no logic level considerations isoEXPERT Compiler User Manual 132 Compiler Control Options Use STRATEGY DELAY during the first attempt in implementing a design This option gives you better levels of delay and optimums performance from your design Use STRATEGY DELAY and other design attributes such as SCP ECP to refine the implementation of a design STRATEGY AREA may lead to a more routable design especially if used with moderate values for MAX GLB IN and MAX GLB OUT attributes In this case the compiler may insert feed through buffers to resolve any user conflicts or to remove any routing congestion While STRATEGY AREA usually results in better resource utilization and STRATEGY DELAY usually results in better levels of delay these methods are not exact are highly design dependent and can potentially lead to unexpected results Try different alternatives to refine the design implementation such as using different global optimization strategies AREA and DELAY or making local refinements by trying different design attributes SCP ECP etc Use STRATEGY NO OPTIMIZATION when a design is manually optimized and you desire less change to user specified design structures This option value normally leads to a larger implementation of a design and should be avoided if possible STRATEGY NO OPTIMIZATION avoids any synthesis of logic However
183. ftware to use the Y2 clock input for routing which increases resource utilization Description If ISP EXCEPT Y2 is OFF you cannot use the Y2 input as a clock input pin in your design it is used only for ISP If ISP EXCEPT Y2 is ON the compiler may use the Y2 pin as a clock input pin you will need to externally multiplex the ISP SCLK signal and the Y2 clock input This option is valid only for the ispLSI 1016 E ispLSI 2032 E V VE 44 48 and 49 pin and ispLSI 2064V VE 44 pin devices and is ignored if you choose any other device The default value is OFF Design Manager Sequence Assign Device Select ISP EXCEPT Y2 Parameter File Syntax ISP EXCEPT Y2 ON OFF Command Line Syntax NA Example Figure 4 1 shows a typical Y2 clock multiplexing scheme for an ispLSl1016E device ISP SCLK lt La 3 Y2 SCLK Pin 33 User CLOCK 1 ISP Prog Enable ispEN Pin 13 ispLSI1016E LJ44 Figure 4 1 Typical Y2 SCLK Multiplexer isoEXPERT Compiler User Manual 151 Global Device Options In devices with 44 48 or 49 pins when the ISP JTAG mode is enabled ispEN BSCAN is LOW Y2 functions as SCLK TCK which is used to shift in programming information When the ISP JTAG mode is disabled ispEN BSCAN is HIGH Y2 can be used as a clock input to your design if ISP EXCEPT Y2 is set to ON Using the TOE IO Shared Pin The TOE AS O Device Option determines the use of the TOE IO sh
184. g Analyzer Reports 204 20 ZW s 18 dion 18 Ds lo 1 05 17 1 64 1 65 Loa 1e 40 40 00 00 00 00 00 00 00 lt 00 00 00 30 0 00 00 00 00 lt 00 00 00 2 00 00 00 00 00 200 00 00 00 00 00 00 00 LO 00 00 00 00 coU O CO N N N 1 O0 o o o o o o CO WO o WO o o CO o CO 0000 CO CO CO CO OO CO WO CO OO CO OO CO OO WO 40 40 90 90 90 90 90 90 90 20 50 50 60 60 263 Appendix A Design Rules and Tips This appendix contains information to help you complete a design that meets your objectives by identifying common design errors and problems design rules and design tips Design Problems If your design failed the compilation process use the report rpt and log 109 files to determine the cause and take corrective action In general a compilation failure is caused by the following conditions m here is a syntax or system error m The design is too large for the chosen device m The design with specified constraints and objectives is too complex to route successfully for the chosen device m Timing simulation results do not meet your design objectives The implementation of the design does not meet your design objectives m During the compilation process you receive an internal error message The diagram on the following page shows how to correct these design problems isoEXPERT Compiler User Manual 264 Design Problems Design Implem
185. g Analyzer Reports Max Min in ns 20 00 20 00 19400 10 00 2 00 0 00 12 00 0 00 15400 20 00 15400 0 00 15500 15 00 0 00 15 00 0 00 0 00 129400 25 00 20500 0 00 25500 Tofu 0 00 17 00 15400 0 00 14 00 0 00 00 00 00 00 Bp nd Source Destination Path Delay Name pin name type Name pin name type ns AO in RAM 0 BAO RAM2S07 28 40 isoEXPERT Compiler User Manual 262 RAM 0 BDO16 Al in AO in Al xm Al 2m Al in AL fan Al in A2 FEN KWD RST in GLB WRITE2 QO PGDFFR GLB _LOAD2 Q0 PGDFFR GLB LOAD2 00 PGDFFR RAM2S07 RAM 0 BDO17 RAM2S07 XDROLG bro XDROIY Hidi REG 1 013 REG 1 012 REG 1 011 REG 1 010 REG 1 08 REG 1 07 REG 1 06 REG 1 05 REG 1 04 REG 1 03 REG 1 02 REG 1 01 REG 1 00 REG 1 099 REG 1 015 REG 1 014 RGTRSO 7 RGTRSO7 RGIRSO J HRGRDERSO 7 RGTRSO7 BGIRSO0J7 RGTRS07 RGTRSO0J RGTRS07 RGTRS07 RGTRS0O7 RGTRSOJ RGTRS0O7 RGTRSO7 RGIRS 07 HRGURSO f Tr r3 r3 r3 r3 r3 rmm m RAM 0 BDO15 RAM2S07 RAM 0 BDO14 RAM 0 BDO13 RAM 0 BDO12 RAM2S07 l RAMZS07 RAMZS07 Li L LI LI LI Le RAM 0O BDO11 RAM2S07 RAM 0 BDO10 RAM2S07 RAM 0 BDO9 RAM2S07 RAM 0 BDO8 RAM2S07 RAM 0O BDO7 RAM2S07 RAM 0 BDO6 RAM2S07 RAM 0 BDO5 RAM2S07 RAM 0 BDO4 RAM2S07 RAM 0 BDO3 RAM2S07 RAM 0 BDO2 RAM2S07 RAM 0O BDO1 RAM2S07 RAM 0 BDOO RAM2S07 XRESET i
186. g the Pins 1 A After you create a project with the design source file from a CAE design environment and set Design Pin Attributes you may also wish to see or change the pin assignments before you compile To obtain the best placement and routing of your design do not lock pins before you compile unless absolutely necessary If some of your pin locking statements are in conflict a message warns you that certain pin locking statements cannot be retained To lock the pins 1 Select Assign Pin Locations or the Assign Pin Locations icon from the Design Manager The Assign Pin Locations window appears Figure 3 11 ip So a Di wo Cog OM SESE E get Fin Apap Carp Neel ies Pin Ariansen Figure 3 11 Assign Pin Locations Window The pin assignments that display after you create a project reflect the pin locking statements from the design source file Once the pin file is translated and read into the ispEXPERT tool the pin locking statements from the design source file are not used or referred to again Any pin assignments you make using the Design Manager take precedence over the source pin statements All unassigned pins are treated as free pins even if they were locked in the original design pin file isoEXPERT Compiler User Manual 95 Locking the Pins This window contains the following pin options e Show Pins Shows the input output and bidirectional pin types Includes the Pin Name field so
187. gates or split during the mapping stage of synthesis Inactive or parallel logic may be removed during optimization even though a PROTECT attribute is assigned A protected buffer will be implemented in one GLB level A protected inverter will be merged with the surrounding logic This attribute is especially effective for user defined and soft macros Example In Figure 2 26 PROTECT has similar impact to using a No Minimize Path The implementation will closely resemble the circuit shown in Figure 2 27 EN PROTECT Figure 2 26 Correct Use of the PROTECT Attribute isoEXPERT Compiler User Manual 61 Symbol Attributes Figure 2 27 Implementation Result After Using PROTECT Placing a Register The REGTYPE Symbol Attribute allows you to place a particular register either inside a GLB or an IOC REGTYPE is not supported in ispL Sl 2000 or 5000V devices Synopsis REGIYPE 2 node name GLB IOC EITHER Description REGTYPE GLB places the register inside a GLB and allows the compiler to use the following GLB clocks m CLKO m CLK1 m CLK2 m SLOWCLK PT Clock HEGTYPE IOC places the register inside an IOC and allows the compiler to use the following IOC clocks m IOCLKO m IOCLK1 REGTYPE EITHER allows isoEXPERT to place the register inside either a GLB or an IOG This is the default setting and has the same impact as not specifying the REGTYPE attribute isoEXPERT Compiler User Manual 62 Symbol Attributes ope
188. gn Manager sequence the Parameter File syntax and the command line syntax for the following topics Using In System Programming Pins Using the Y2 Pin as a Clock Input Using the TOE IO Shared Pin Setting the Global Reset Pin Setting the Y1 RESET Pin Preserving XOR Gates Global Speed Power Control Using Device Open drain Using Output Buffer Delays Using Pull up or Datahold Setting Slow Slew Rate Setting Device Voltage Setting Device Security isoEXPERT Compiler User Manual 149 Global Device Options Using In System Programming Pins The ISP In System Programming Device Option informs the software that you want to use the ISP pins on an ispL Sl 1000 or 2000 device for programming The default value is ON Description The ISP option requires four input pins Setting this option to OFF makes the four ISP pins SCLK SDI SDO and MODE available for routing as dedicated input pins and the router can then assign signals to these pins You can remove the ISP option to improve resource availability See the ISP Encyclopedia for device specific ISP pin numbers n NOTE See ISP EXCEPT Y2 on the next page for additional information concerning the use of ISP pins Design Manager Sequence Assign Device Select ISP Parameter File Syntax ISP ON OFF Command Line Syntax NA isoEXPERT Compiler User Manual 150 Global Device Options Using the Y2 Pin as a Clock Input ThelSP EXCEPT Y2 Device Option allows the so
189. gnd netor cell name Specifies a name for a GND net or cell The default name is GND m vcc gnd cell Specifies the type of representation for Vcc or GND in the input EDIF file The default representation is a net Attribute Handling m prop property file name Directs edif2laf to read in a Property File containing Design Attributes See the section EDIF Property File Syntax on page 286 for more information m gout Ground all floating output pins isoEXPERT Compiler User Manual 307 Appendix c Menu and Icon Reference This appendix provides reference information for the ispEXPERT Compiler Design Manager the ispANALYZER the Physical Viewer and the Timing Viewer m Pull Down Menus sections show the pull down menus These pull down menus also show the keyboard shortcuts and hot keys m ool Bar Icons sections provide tables describing each of the tool bar icons isoEXPERT Compiler User Manual 308 Menu and Icon Reference ispEXPERT Compiler Pull Down Menus Hew Oper Close Save Save As Print Print Preview Print Setup TEA EN T4 apt 2L LNHT4A edo BLA SENTA BLA SENTS ALM ASIMSM BLA SSDDER2Z Ctrl M trl L Chrl 5 trl 2 Ctrl P Exit pE SPERT Compiler File Pull down Menu Unda Ctrl Cut Ctrl Copy Ctr Paste Ctrl Delete Del Uptions Llear Messages Find Ctrl F Replace Ctrl H Edit Pull down Menu pS matt lov Tool Bar zoom Bar Sta
190. gt Copy Copies the text from the clipboard to the cursor location Equivalent to Edit gt Paste Displays the Print dialog box to allow printing of the active file Equivalent to File Print Displays the About ispEXPERT Compiler Constraint Manager dialog box showing the Constraint Manager version number Activates context sensitive help Equivalent to pressing F1 when the item is active isoEXPERT Compiler User Manual 323 Glossary Application Window Array Asynchronous Attribute Back Annotation Big Fast Megablock Big Fast Megablock Routing Pool BRP Boolean Browse Cascade In Cl Cascade Out CO Cell The window containing the work area and menu bar for an application The application window has its name at the top of the window The area occupied by the rows of modules and the routing interconnects Data that is not synchronous with a clock signal The next I O may start operation before the current one is finished The output responds immediately to a change in the input signal Design constraint data specified during logic entry The process of translating data generated by the ispEXPERT system to the CAE design environment Post route timing delay information is back annotated to the CAE simulator Architectural structure of the ispL Sl 8000 devices A Big Fast Megablock consists of 120 registered macrocells arranged in six groups GLBs of 20 Interconnects the six GLBs o
191. gure 2 8 Also if you specify STRATEGY NO OPTIMIZATION the redundant register is still removed during the optimization process Y Figure 2 8 Parallel Registers Reduced Figure 2 9 shows the parallel registers with PRESERVE or ECP attributes attached to both register outputs This prevents the removal of parallel registers during optimization and preserves the output nets PRESERVE Or ECP PRESERVE Or ECP Figure 2 9 Parallel Registers with PRESERVE Attributes isoEXPERT Compiler User Manual 42 Net Attributes Preserving XOR Gates The XOR Net Attribute preserves user specified XOR gates during the logic optimization process for isoLSI5000V and 8000 designs This local attribute works in conjunction the global XOR compiler option see Preserving XOR Gates on page 156 for more information Synopsis XOR ON OFF Description During logic optimization the compiler expands all XOR gates in your design This XOR expansion enables the compiler to determine and remove unnecessary logic in the design The global XOR compiler option and the local XOR net attribute allow you to preserve any or all XORs in your design When the global XOR compiler option is OFF all XOR gates in your design are expanded In this case you can preserve individual XOR gates by assigning the local XOR ON net attribute to the primary output node of the target XOR gate When the global XOR compiler option is ON default all XOR gates on
192. h attributes in an isoLSI 5000V or 8000 design m Ihe SLP Design Attribute specifies the Starting point to toggle a Low Power Path Each SLP attribute must have an associated ELP attribute with the same path name m Ihe ELP Design Attribute specifies the Ending point to toggle a Low Power Path and does not require a matching SLP attribute Synopsis SLPI pathl pathZs es PALLEN ELE pathl Path sep PACAN Description The SLP and ELP path attributes toggle the power setting of a specified path based on the global LowPower Device Option setting The default global LowPower setting for isoLSI 5000V devices is OFF Turbo on The default global LowPower setting for isoLSI 8000 devices is ON Turbo off isoEXPERT Compiler User Manual 53 Path Attributes When the global LowPower Device Option is OFF SLP and ELP instruct the compiler to turn ON LowPower turn off Turbo for the specified path When the global LowPower Device Option is ON SLP and ELP instruct the compiler to turn OFF LowPower turn on Turbo for the specified path SLP and ELP also specify the path is to be preserved similar to specifying the PRESERVE net attribute See Preventing the Elimination of Nets on page 40 Turbo Path Setting The STP and ETP Path Attributes identify the start and end of a Turbo Path in an ispL SI 5000V or 8000 design m The STP Design Attribute specifies the Start of a Turbo Path Each STP attribute must have an associated ETP attribu
193. have the compiler calculate the timing frequency information isoEXPERT Compiler User Manual 98 Design Exploration Turn on Append to Current Explore Log to have the explore results file appended to an existing log file If this is not selected previous results are erased from the log Use this feature carefully as it may lead to duplicate entries with different results If you change the device for the project and turn on Append to Current Explore Log a message displays telling you the Explore results will be lost if you continue When the device is changed the Explore Log contents are no longer valid and are erased to avoid confusion Click Advanced to access the Advanced Explore Settings dialog box Figure 3 13 with additional settings These correspond to the Advanced Compiler Settings Table 3 1 Advanced Explore Settings Minimize GLE Levels For AllPaths Use Internal Tristate I0 Driver Reduction Effort High Iv ON me I OFF M None BFM Packing Single PT Function Packing for Routability Cancel Figure 3 13 Advanced Explore Settings Dialog Box Click Explore Criteria to display the Explore Criteria dialog box Figure 3 14 This dialog box is used to specify that the Explore process should terminate when it meets specific conditions rather than going through all Explore cycles Eerie Citimi M Pirie a HULE joes Leer aan Ee T Heppa maler Than ar E zusd ba iL Fei Ecce Figure 3 14 Explore C
194. he Compiler Settings dialog box appears Figure 3 4 Compiler Settings Synthesis Strategy C Area amp Delay C No Logic Optimization OK Low High TE I v Lise Global Reset Effort Interfaces Partitioner amp Router Advanced Maxinum GLB Inputs Cary Pin Direction Masimum GLE Outputs l i Case Sensitive Free All Pin Locks Ignore Reserved Pins Timing Analyzer M Use Extended Routing Perform Timing Analysis Use Parameter File Only Parameter File Bronse Figure 3 4 Compiler Settings Dialog Box The Compiler Settings dialog box reflects the settings included in your input design file Make changes as needed The available settings may vary depending on the device you are using isoEXPERT Compiler User Manual 84 Compiler Control Options 2 Click Advanced to set additional options The Advanced Compiler Settings dialog box Figure 3 5 appears Advanced Compiler Settings Reduction Effort amp High Low v Use Internal Tristate I0 Driver BFM Packing amp User Selection Compact Spread Compiler Selection 0 Single PT Function Packing for Houtability gt Higher Packing Higher Routability cena Figure 3 5 Advanced Compiler Settings Dialog Box 3 Click Interfaces to specify the output netlist files you will want The Interfaces dialog box appears Figure 3 6 Select the desired output netlist s You should select the desired
195. hows the resulting implementation isoEXPERT Compiler User Manual 65 Design Pin Attributes a LOCK 25 7 moret PART ispLSI1032E 70LJ84 A o T 7 GLBe EN i 7 l iz ee ce sul o Le s uu PART ispLSI1032E 70LJ84 B Figure 2 31 A Improper Use of the LOCK Attribute B The Resulting Implementation isoEXPERT Compiler User Manual 66 Design Pin Attributes Locking a Signal to a Big Fast Megablock The LOCK BFM Pin Attribute assigns a design pins to a specific Big Fast Megablock BFM or to any BFM in an ispLSI 8000 design Synopsis LOCK BFM BFM index where BFM index is 0 through number of BFMs 1 Assigning a BFM index number is optional In the Constraint Manager the optional setting is ANY Description The LOCK BFM Design Attribute can be used to assign design pins to a specific BFM For example LOCK BEM S1gnall 0 assigns the I O cell signal1 to BFM 0 Using LOCK BFM without an index number allows the compiler to assign the I O cell to any BFM in the device For example LOCK BFM signall instructs the compiler to assign the I O cell signal1l to a BFM but allows the compiler to select the BFM based on resource availability I O cells that are not locked to a BFM with the LOCK BFM attribute are assigned by the compiler in random order Ew EM ED ec 1 Een lias Megaiiazkk Dea lia egaiiazk 5 oa rb bog dl kok T E 5 TN oa rb byg a ok E men Eag F
196. ice These two nets will be implemented as outputs of a single GLB However if you had set the Compiler Control Option MAX GLB IN to 5 this grouping would be ignored because the six inputs violate the specified maximum GLB input limit d GROUP GROUP 1 B D C E GROUP GROUP1 F H G Figure 2 3 Assigning GROUP Design Attribute to Nets isoEXPERT Compiler User Manual 39 Net Attributes Preventing the Elimination of Nets The PRESERVE Net Attribute is placed on nets and identifies nets that you do not want eliminated during the logic optimization process Zn NOTE You can also use the SLP and ELP path attributes to prevent the elimination of nets in isoLSI 5000V and 8000 designs See Low Power Path Toggle Setting on page 53 Synopsis PRESERVE 2 node name Description PRESERVE forces the net to a GLB output This is useful for debugging purposes where specific test points need to be preserved Design rules for using the PRESERVE Design Attribute include m PRESERVE assigns a net to a GLB output this may increase delay levels as well as the total required number of GLBs when used improperly m Apreserved net implemented as a GLB output may be duplicated by the compiler for successful routing Duplicated nets derive their names from the preserved net name and may not be available in the user specified form See the SAP EAP attribute description to avoid this duplication m Parallel logic is normally removed by the comp
197. ield Figure 3 28 shows an example of an Information dialog box for an EDIF project Information Project Mame NT4 Froject Type pF Project Directory Cisptools ispcomp Examples Edf Design File NT amp EDN Design File Directory C isptoolstispeomprExamplesve dt Vendor Property File Power and Ground Setting Bus Reconstruction CC GHD Representation Aag Index Ordering Up 6 Down fe Met C en Least Significant Bit eft 6 Right VCC Name GND Mame Figure 3 28 Information Dialog Box isoEXPERT Compiler User Manual 118 Cleaning A Project Directory Cleaning A Project Directory Once you obtain a successful compilation of your design you may wish to perform basic file management and clean up of your directories If you used the Save Settings options from the Project menu or ran the Tools Explore function and did multiple compiles you may have generated many output files in subdirectories To clean up your project directory 1 Close the project you want to clean 2 Select Project Clean from the Design Manager The Clean Project dialog box appears Figure 3 29 Clean Project Project Mame Directories L usplaals ispeompsE samples E dif Cancel E gt C Es isptonls E gt isocomp E gt Examples E gt Edif fa CNT4 Drives ic 1 m Figure 3 29 Clean Project Dialog Box 3 Select the project information 4 Click OK Most directories and files are deleted
198. ies Groups logic to fit within Generic Logic Blocks GLBs and I O Cells IOCs isoEXPERT Compiler User Manual 18 isoEXPERT Functions Placement and Routing Once the design is partitioned the placement and routing routine performs the following functions m Assigns I O pins m Interconnects GLBs and IOCs m Produces GLB and IOC placement information ISDANALYZER The ispANALYZER provides the ability to connect an observable node to output pins without repeating design entry compilation and verification steps The ispANALYZER manipulates the compiler output adds only the routing paths of the desired internal nodes and preserves the original implementation of the design The isoANALYZER recognizes internal nodes and resources available for incrementally adding new routing paths New JEDEC and SIM files are also generated The ispEXPERT compilation process includes observability analysis The results are available for the isoANALYZER so you can manipulate internal node connections and connect them to device pins The ispANALYZER design flow is shown in Figure 1 3 m The Observability Analyzer reads the post routed design netlist and ispLSI device file to identify available unused pins and internal nodes present in the compiled design It also recognizes unobservable nodes m The Node Selector lets you select the desired connectivity between the internal nodes and available external device pins You can also navigate design nodes
199. ieve the best overall results Optimizing for Routability If you determine that your design is not too large for the intended device but your design does not pass through the compiler because of routing or resource limitations your design is probably overconstrained and you need to relax some attributes or parameters to achieve a routable design Table A 1 lists Design Attributes and Compiler Control Options in order of their effectiveness in improving routability and resource utilization the most difficult ones for the compiler are listed first Use this table as a guideline to determine which attributes have the most impact on the compile process However these are only guidelines A thorough knowledge of the device architecture and of your design is your best tool for determining the best combination of Design Attributes and Compiler Control Options Some of the Compiler Control Options and Design Attributes are device dependent isoEXPERT Compiler User Manual 270 Improving Routability Table A 1 Design Attributes and Compiler Control Options Design Attribute or Compiler C Option PART ontrol How to Improve Routability and Device Resource Utilization This parameter determines device type and the resources available to your design Choose a larger device if your design is unroutable due to lack of resources SIRATEGY The ispEXPERT software has three methods that can be used to fit your design Each method is optimiz
200. ign Manager Sequence Tools Compiler Settings Click Advanced In the BFM Packing for Routability field use the slide bar to select the number of BFMs for packing your design Parameter File Syntax NA Command Line Syntax EOD ql isoEXPERT Compiler User Manual 130 Compiler Control Options Maintaining Pin Direction The CARRY PIN DIRECTION option maintains user specified pin directions in any simulation output Default is OFF Description m When CARRY PIN DIRECTION is ON the compiler attempts to maintain user specified pin directions for 3 state outputs into any simulation output netlist The 3 state outputs can be connected to external output pins or bidirectional pins m When CARRY PIN DIRECTION is OFF the compiler converts 3 state outputs to external output pins in any simulation output netlist Design Manager Sequence Tools Compiler Settings Select Carry Pin Direction Parameter File Syntax CARRY PIN DIRECTION ON OFF Command Line Syntax mmc Specifying Case Sensitivity The CASE SENSITIVE option enables the compiler to treat identifiers such as pin names and net names as case sensitive or case insensitive The default is OFF Description m Turning CASE SENSITIVE ON results in consideration of identifiers as case sensitive m Turning CASE SENSITIVE OFF results in consideration of identifiers as case insensitive Design Manager Sequence Tools Compiler Settings Select Case Sensitive
201. ignal If the selected signal is a primary input no timing information is available m Frequency Uses the selected signal as a clock signal and displays the frequency determined by the register pair controlled by the selected clock signal in the Frequency Table If the selected signal is not a clock signal or frequency cannot be determined a warning is issued When you right click anywhere else except on a GLB a macrocell an IOC or a Dedicated Control Input pin in the Connectivity View or in the top levels of the Design Navigator the Timing Viewer command cascades to show the following commands m Frequency Identifies the maximum frequency that the design can operate m Longest Timing Path Identifies and displays the timing data for the design s longest timing path m Shortest Timing Path Identifies and displays the timing data for the design s shortest timing path From the Timing Viewer you can display timing paths in the Physical Viewer Refer to Figure 6 10 for an example of the Connectivity window in Timing Path Mode Refer to Timing Explorer on page 183 for information on the Timing Viewer isoEXPERT Compiler User Manual 213 Chapter7 Design Reports The ispEXPERT software provides a Compiler Report File that tells you how your design fit into the Lattice Semiconductor device architecture The Timing Analyzer also generates a number of reports that provide information regarding the design The compil
202. ignment 95 removing 97 Pin Attributes 33 64 294 CRIT 64 289 ECP 92 LOCK 65 289 LOCK BFM 289 LOCK GRP 289 OUTDELAY 71 92 159 289 PULL 72 92 159 289 setting 92 SLOWSLEW 73 92 161 290 summary 92 TOE AS 10 152 updating 113 VOLTAGE 73 92 161 162 290 Pin File importing 96 112 Pin layout after compilation 110 Pin Locations oave Pin Assignments 96 Pin Tips 97 PIN FILE 136 PINARRAY 288 Pins assigning 96 changing color and shape 125 freeing 97 I O 29 I O designations 278 Y1 RESET 154 Placement and routing 19 Pop up menus Physical Viewer 207 Signal Navigator 184 Timing Tables 187 Post Compile Update Tools menu 113 Post Compile turbo settings 55 Post compile update Turbo 55 Power calculation 190 PRESERVE 33 40 276 291 and resource utilization 269 and speed optimization 277 isoEXPERT Compiler User Manual 334 Print File menu 123 Process Bar opening closing 124 Project Clean 119 Close 127 creating a 80 directory 104 Information 118 menu 310 New 80 Open 83 oave As Setting 104 Save Setting 104 Select Setting 105 Update 120 PROPERTY 288 Property File 145 284 307 cell definition 286 identifiers 288 instance definition 287 keywords 288 multiple values 288 306 net definition 287 object definition 287 pin array definition 287 pin definition 287 property definition 287 property value 287 selecting 82 symbol definition 287 syntax format 286 syntax rules 288 PROTECT 33 61 293
203. iler if its outputs are not preserved Use PRESERVE to prevent the compiler from removing parallel logic Example Figure 2 4 shows an example of assigning PRESERVE to net D In this example the AND and OR gates can be mapped into a single GLB but are mapped into two GLB outputs with net name D maintained as a GLB output name driven by the AND gate as a result of the PRESERVE attribute Net D is implemented inside a GLB if it is not preserved A PRESERVE B D D C Figure 2 4 Using the PRESERVE Attribute isoEXPERT Compiler User Manual 40 Net Attributes You can also use PRESERVE to assist the compiler in partitioning your design For example X1 X2 X3 X4 X5 X6 X7 X8 the logic in Figure 2 5 translates into 128 PTs in a sum of products form _ Figure 2 5 XOR Without PRESERVE Assigned By using PRESERVE on the Y1 and Y2 nets as shown in Figure 2 6 Y1 and Y2 are preserved and the number of PTs is reduced to eight for each first level exclusive or for a total of 18 PTs from the original 128 PTs PRESERVE PRESERVE Figure 2 6 XORs with PRESERVE Assigned Figure 2 7 is an example of parallel registers before the design is optimized gt V4 Figure 2 7 Parallel Registers without PRESERVE Attributes isoEXPERT Compiler User Manual 41 Net Attributes Without PRESERVE attributes a parallel register is generally removed during optimization resulting in the implementation shown in Fi
204. implementing a design Design rules range from syntactic limitations such as maximum allowable length of design identifiers to rules pertaining to ispL Sl architecture such as the maximum allowable number of global clocks used in a design isoEXPERT Compiler User Manual 30 Chapter2 Design Attributes Lattice Semiconductor specific Design Attributes affect how the compiler implements your design Using these attributes correctly is a key factor for successful compilation of your design When you assign Design Attributes the compiler takes them as suggestions rather than as literal assignments Although Design Attributes are generally used by the compiler as you assign them occasionally the compiler will not honor an assigned Design Attribute due to device constraints or resource usage conflicts Two common situations in which Design Attributes are rejected are when they are attached to an inactive element of your design or when conflicting Design Attributes are specified for example when a particular clock line is assigned as CLKO and IOCLKO A warning message or error message may be issued from the ispEXPERT software whenever it is necessary to ignore attributes in your design Warning messages are also issued when Design Attributes are applied that would result in a noticeable deviation from a more optimal implementation of the design Use Design Attributes conservatively to take advantage of their effectiveness and to avoid any signi
205. in the program The PARAM FILE option can be included in a PLA file Design Manager Sequence Tools Compiler Settings Turn on Use Parameter File Only and enter or select the Parameter File Parameter File Syntax NA Command Line Syntax r file name isoEXPERT Compiler User Manual 144 Compiler Control Options Specifying a Part Number Use the PART option to specify the part number of the device you wish to use Description When entering the PART number of the target device you must enter the part number exactly as shown in the Part Number column of the tables provided in the Supported Device List Design Manager Sequence Assign Device Select from list in Select New Device field Parameter File Syntax PART part number Command Line Syntax p part number Specifying a Property File An EDIF Property File can be used to assign or overwrite design attributes in an EDIF file during design compilation The PROPERTY FILE option identifies the Property File for the compiler to use Description If your design was created using a schematic or synthesis flow you can use an EDIF Property File to add Design Attributes to the output EDIF file from your design You can also use a Property File to overwrite Design Attributes in your EDIF file See Appendix B EDIF Property File You cannot specify a Property File in a Parameter File Design Manager Sequence Project gt New Click EDIF Reader Settings
206. in the programmer software to secure the device if the G field is set to 1 With the device security cell programmed ON you can reprogram the device but you cannot read its contents The security cell cannot be cleared except by erasing the entire device SECURITY OFF inserts a 0 in the G field of the JEDEC file which prevents the programmer from securing the device However many programmers have the capability to manually secure the device even if this value is set to OFF Design Manager Sequence Assign Device Select Security Parameter File Syntax SECURITY ON OFF Command Line Syntax NA isoEXPERT Compiler User Manual 162 Using a Parameter File Using a Parameter File The Parameter File contains alternate sets of compiler control options and device control options that can be used to run different iterations of your design You can create this text file using any ASCII text editor or the ispEXPERT text editor Using a Parameter File does not change settings in the Compiler Setting or Device Selection dialog boxes Only the Parameter File settings are used when the project is compiled the Compiler Settings and Device Options in the Design Manager are ignored When a Parameter File is used all relevant files and parameters are passed to the appropriate software modules by ispEXPERT so you can run the Physical Viewer Timing Analyzer and so forth Once a design is routed ispEXPERT merges the various report files i
207. ined by using the PRESERVE attribute in conjunction with a starting or ending point specification for the path in which case no gates are merged over the boundaries defined by the preserved starting or ending points Use a buffer when there are combinational loops and the whole loop is covered by path attributes In Figure 2 12 Path1 only relates to the net OUT and not to the path going through gates B C and D isoEXPERT Compiler User Manual 45 Path Attributes SAP Path1 EAP Path1 Figure 2 12 Path1 Relates to the Net OUT Only To correctly identify the logic on the loop modify the network as shown in Figure 2 13 In this case gates B C and D are all considered to be on Path1 SAP Path1 EAP Path1 Figure 2 13 Modify the Network to Identify the Logic isoEXPERT Compiler User Manual 46 Path Attributes Specifying Asynchronous Paths The SAP and EAP Path Attributes identify the start and end of an Asynchronous Path This attribute is not supported in ispL SI 5000V or 8000 devices m The SAP Design Attribute specifies the Start of an Asynchronous Path Each SAP attribute must have an associated EAP attribute with the same path name m The EAP Design Attribute specifies the End of an Asynchronous Path and does not require a matching SAP attribute Synopsis SAP path PEN de PACAN EAP S Dati pathy a PENN Description The compiler duplicates GLB outputs when necessary to improve routability If a GLB
208. ing Pools ORPs and I O Cells IOCs coupled together The various members of the ispLSI families are created by combining several megablocks on a single device Conventions that define the signal net names syntax entries and pin numbers A logic signal path between logic elements containing the source signal and destination isoOEXPERT System User Manual 326 Netlist Notation Output Enable OE Output Routing Pool ORP Partitioning Product Term PT Pull ups Report Files Router Soft Macro A tabular format report that contains the net name source and destination GLB locations and Fan out data Conventions that define the style and format for syntax entries Logic signal that enables the output of an IOC The Output Routing Pool connects the Generic Logic Blocks GLBs output to the I O Cells IOCs Dividing a design into functional blocks These blocks can be a few components or multiple circuits with numerous components The design is organized to meet the capabilities of the targeted device A term generated by one of the twenty AND gates within a GLB The inputs to the GLB are ANDed to produce the product term that can be used as a logic element a product term clock PT clock a product term reset PT reset or a product term output enable PTOE Allow the holding of floating inputs at a known state They are useful in debugging a design and reducing noise interference A method fo
209. ing Tables When you click the right mouse button from the signal name row or column headers in the Timing Matrix Table the following commands are available Sort Rearranges the table so the values in the column with the cursor are arranged from lowest to highest or in alphabetical order as appropriate Show Timing Data Shows the timing data for the entire row or column Add Signal When you select the command a dialog box displays so you can enter the name of a signal you want to add to the table Remove Signal When you select this command the signal name where the cursor is located is removed from the table When you click the right mouse button on a cell in the Timing Matrix Table the following commands are available Show Timing Data Shows the timing data for that cell Display Timing Path Cascades to show Longest Path Shortest Path and Both Paths Choose one of these options to have the path display in the Connectivity window of the Physical Viewer The Physical Viewer tool bar icon changes to show you are in Timing Mode Report Timing Path In a new window displays the timing path as a text report When you click the right mouse button on the signal name in the Frequency Table the Display Timing Path and Report Timing Path commands are available When you click the right mouse button on a cell in the Source Register or Destination Register columns in the Frequency Table the following additio
210. ing Your Design To access the compiler report Review the compiler report to obtain information about the completed compilation Use the Results Compiler Report menu item or the Compiler Report icon to display the compiler report You can display parts of the compiler report by clicking on the following buttons at the top of the display Parameter Displays the Design Parameters section Specification Displays the Design Specification section Implementation Displays the Post Route Design Implementation section or the Pre Route Design Implementation section if routing failed Level Trace Displays the Maximum Level Trace table GLB Statistics Displays the GLB and GLB Output Statistics table Statistics Displays the Pre Route Design Statistics section Full Displays the complete Compiler Report Refer to Chapter 7 Design Reports for sample compiler reports isoEXPERT Compiler User Manual 109 Viewing the Pin Layout Viewing the Pin Layout After you compile inspect the pin layout to see if it meets your design needs If the design did not route the pin layout window is not available To review the pin layout for your project after compilation select Results Pin Layout or the Pin Layout icon from the Design Manager The Pin Layout window appears and shows you the pin assignments the compiler made for your design Figure 3 22 ispL S 2032 150L 745 Figure 3 22 Pin Layout Window n
211. ion Reserved File Names A number of files are generated and maintained by the Design Process Manager DPM These files cannot be used as data files in the directory in which DPM is being run If this happens any such file may be removed or overwritten or a system error may occur Examples of such file names are design par design xpn and design ppn Either avoid using these names as your file names or separate the DPM run directory from your data files directory Syntax Errors oyntax errors are usually caused by incorrect spelling or unsupported options oyntactic problems must be corrected before your design can be properly processed by ispEXPERT Use the information provided by the log report to identify these errors and make corrections as required Valid Characters Design documentation information can be added to your design as comments without affecting the compiler When adding comments to your design source file use all of the following standard alphanumeric characters and symbols except the semicolon and new line characters a Z A Z 0 9 QHSN amp lt gt I VII space tab isoEXPERT Compiler User Manual 266 System Syntax and Specification Errors Identifier names in your design are restricted to the following characters E a BH A Z m 0 9 gm GE amp JV White space characters space and horizontal tabs can be used as separators Valid Identifiers and Text Identifiers are case insensit
212. isoEXPERT Compiler User Manual 129 Compiler Control Options BFM Packing for Improved Routability The BFM Packing for Routability compiler option allows you to pack or spread the logic GLBs in your design into one or more BFMs in an ispL Sl 8000 device Description Each Big Fast Megablock BFM in an ispL Sl 8000 device has six GLBs By default the compiler will pack a design into the GLBs of the device s BFMs depending on the resource utilization and complexity of the design Therefore the compiler may use more or less BFMs depending on the design If you want to pack more of your design into fewer BFMs or spread your design into more BFMs you can use the BFM Packing for Routability settings to decrease or increase the number of target BFMs For example if your design has 12 GLBs and you select setting 2 the compiler will attempt to place your design into two BFMs Likewise if your design has 12 GLBs and you select setting 4 the compiler will attempt to place your design into four BFMs However if your design has 13 GLBs and you select setting 2 the compiler will issue a warning because you attempted to exceed the capacity of two BFMs A lower setting may result in a shorter routing and timing delay However local congestion from the more compact GLB placement in each BFM may cause routing failure A higher setting may increase the probability of successful routing but may also result in longer routing and timing delays Des
213. ispEXPERT solution also supports design verification Design verification options include both functional and timing simulation Various combinations of graphical and text based functional and timing simulators are supported by third party CAE vendors Following design compilation ispEXPERT generates a JEDEC fuse map for device programming Lattice Semiconductor ispLSI devices can be programmed directly from a PC using an ispDOWNLOAD cable Lattice Semiconductor ispLSI devices can also be programmed using third party programmers If you want to download from a UNIX workstation contact your Lattice Semiconductor Sales Representative A diagram of the ispEXPERT process is shown in Figure 1 1 isoEXPERT Compiler User Manual 15 SCHEMATIC VERILOG HDL VHDL ABEL HDL OTHER HDLs Third Party Design Entry Synthesis and Compilation ispEXPERT Compiler EE Design Analysis E ispLSI Architecture Specific Synthesis and Partitioning Optimization and Mapping Placement and Routing File Pin Assignment Editor Design Explorer Physical Viewer gt EM Static Timing Analyzer and Timing Viewer File ispANALYZER Constraint Manager I Reports Programming Output Simulation Netlists Logic Models Figure 1 1 ispEXPERT Design Flow isoEXPERT Compiler User Manual 16 Third Party Design Entry Third Party Design Entry The ispEXPERT solution supports multiple third party CAE tools providing designers
214. isplay mode for the Connectivity window Use the View menu or turn on or off the icons corresponding to the modes Turn on and off the display of the View Mode Bar icons using the View Mode Bar or the Toggle Mode Bar icon The following modes can be used m Fan in Fan ins for the selected GLB output pin s Dedicated Control Input s IOC s GLBS or modules display m Fan out Fan outs for the selected GLB output pin s Dedicated Control Input s lOC s GLBS or modules display m Both fan in and fan out Fan ins and fan outs for the selected GLB output pin s Dedicated Control Input s IOC s GLBS or modules display m Path Available paths between the two selected components display Timing Path Mode Displays paths as requested from the Timing Viewer m Analyzer Mode Displays assigned and available paths from an observable node in the ispANALYZER m None Only the GLBs display without fan ins fan outs or paths Click on a GLB output pin Dedicated Control Input pin or IOC in the connectivity window to see the fan in and fan out information You can select multiple pins by holding down the Ctrl key as you click on pins Click on the GLB to see all fan in and or fan out information for that GLB You can select both fan in and fan out by selecting from the View menu or by clicking the icons Fan in and fan out information in the Connectivity view does not include the GLB input pin because the GLB in
215. isplays or activates the display of Setup and Hold Table Equivalent to View gt Setup and Hold Table Displays or activates the display of Tco Path Table Equivalent to View Tco Path Table Displays or activates the display of Tpd Table Equivalent to View Tpd Table Displays the About Physical Viewer dialog box showing the Physical Viewer version number Activates context sensitive help Equivalent to pressing F1 when the item is active 321 Menu and Icon Reference Constraint Manager Pull Down Menus Save Property Window Pull down Menu Save Property As Open Property Print Print Preview Print Setup Help Topics About pks PEAT Compiler Constraint Manager File Pull down Menu Help Pull down Menu Llear Cut Cirle Copy Ctrl C Paste Ctrl V Delete Del Edit Pull down Menu wv Toolbar w Statue Bar View Pull down Menu IspEXPERT Compiler User Manual 322 Constraint Manager Tool Bar Icons The following table shows the Constraint Manager icons lists their names and describes their function Table 3 5 Timing Viewer Tool Bar Icons os ume oseon Opens an existing Property File Equivalent to the File gt Open Property menu item Saves the existing Property File Equivalent to the File Save Property menu item Hemoves the highlighted text from the cell Equivalent to Edit Cut Copies the highlighted text to the clipboard Equivalent to Edit
216. iter settings 88 menu 310 315 Verilog writer 89 VHDL writer 89 Internals 208 IOC clocks 62 IOG Information 210 IOG Utilization 210 lOCLKs 36 ISP 150 option 278 pins 278 ISP EXCEPT Y2 151 ISOANALYZER 19 115 assigning nodes 205 compiler 117 displaying paths in Physical Viewer 205 File menu 116 overview 19 isoEXPERT Compiler User Manual 332 Results menu 117 Tools menu 116 ispDCD Tools 118 ispds run explore directory 100 isoSmartFlow 107 J JEDEC file 23 113 downloading 118 updating 113 K Keywords design rules 268 Property File 288 ENDPROPERTY 288 INST 288 NET 288 PIN 288 PINARRAY 288 PROPERTY 288 SYM 288 L Least Significant Bit 82 LOCK 33 65 276 289 290 and resource utilization 269 LOCK BFM 33 289 LOCK GRP 33 289 Locking pins 95 Log file compiler 108 Low power paths 53 LowPower 157 LXOR2 33 58 and resource utilization 269 M Macros using variables 303 Managing project directories 119 Match case during search 122 Matrix Explore 101 Max Frequency during Explore 99 MAX GLB IN 138 and resource utilization 270 Index MAX GLB OUT 139 and resource utilization 270 Maximum number of characters 267 Megablock design rules 279 Menus Constraint Manager 322 ispANALYZER 314 ispEXPERT Compiler 309 Physical Viewer 317 pop up 184 207 213 Timing Viewer 320 Messages changing color 126 Minimize GLB Levels for All Paths 141 Module information 209 Module Report 181 Modules design rules
217. itical If you specify STP ETP you do not need to also use SCP ECP See Turbo Path Setting on page 54 Synopsis SCP s patnl Patha i5 pull ECP pathl pathZ sser PAENN Description The SCP ECP Design Attribute performs two functions First it instructs the compiler to minimize the number of GLB levels in a given path Second it instructs the compiler to minimize the signal path delay within each GLB level by utilizing a product term bypass if possible You only need to apply SCP ECP properties to a representative subset of the related Critical Path starting and ending points If you do not know which Critical Path beginning or ending points to mark you can mark them all If SCP and ECP attributes relating to the same path are applied to the same net they are ignored A critical path implementation may not produce what you expect if applied to a wide input logic gate which is not directly mappable to the Lattice Semiconductor isoLSI architecture To achieve your desired implementation replace the wide input logic gate with several narrow input gates and apply SCP and ECP attributes opecify critical paths with embedded registers by specifying two separate critical paths a Critical Input Path to the register input and a Critical Output Path from the register output For ispLSI 8000 devices the compiler tries to place functions on the same critical path marked ECP into one BFM This results in enhanced timing performance
218. ive unless the CASE SENSITIVE option is set to ON Use either uppercase or lowercase characters in any combination except where specifically noted However all identifiers are modified to uppercase characters in output files such as the log and rpt files if the CASE SENSITIVE option is set to OFF To specify case sensitivity 1 Select Tools gt Compiler Settings from the Design Manager Check the Case Sensitive box 2 Click OK The maximum number of characters you can use in an identifier is Component names 31 Component pin names 31 Net names 255 External pin names 255 Path names 31 Design documentation comments 51 1 isoEXPERT Compiler User Manual 267 Optimizing Your Design Specification Errors and Problems opecification errors and problems occur when you misspell names or keywords or use reserved prefixes Attribute and Option Names and Values You must enter Design Attributes and Compiler Control Options names and values in the correct format as shown in Chapter 2 Design Attributes and Chapter 4 Design Compilation Options The compiler flags as errors or warnings improper spelling and misuse of the names and values Use the log 10g and report rpt files from the compiler to compare what you input versus what the program processed Keywords Keywords are reserved identifiers that cannot be used to name designs pins nodes constants sets macros or signals Keywords are
219. jects in the cell See Figure B 13 for an example m property def property name property name property value A property definition can be property name only or property name and property value e property name IDENTIFIER Any valid Design Attribute where IDENTIFIER is the name of the Attribute For example PROTECT If a Design Attribute does not have a value the Attribute name is immediately followed by the ENDPROPERTY keyword For example PROTECT ENDPROPERTY e property value IDENTIFIER MULTI ID Any valid value for a Design Attribute where IDENTIFIER is the value For example REGTYPE IOC where REGTYPE is the property name and IOC is the property value isoEXPERT Compiler User Manual 287 EDIF Property File Syntax e MULTI ID IDENTIFER MULTI ID IDENTIFIER MULTI ID IDENTIFIER l MULTI ID IDENTIFIER Multiple value IDentifiers for Design Attributes in a design Due to the overwriting nature of Design Attributes you must use a multiple identifier to add multiple attributes of the same name to the same object For example PROPERTY DESIGN E NET NEIC ECP PATH PATHZ ENDPROPERTY PROPERTY CNTA SYM RESERVE PIN 3 9714 15 ENDPROPERIY Multiple value IDentifiers MULTI ID may be separated by commas semicolons or colons Ensure there are no spaces between multiple values Syntax Rules When editing a Property File follow the syntax rules listed below Each line must begin with a P
220. llInternal Nodes Match Node Mame Iw Show GLB Names Sort by C Physical GLB Name Logical GLE Mame coe Figure 3 27 Node Mapper Settings Dialog Box Compile Generates a new jed sim and apt file reflecting the nodes and device pin connections m ispEXPERT Physical Viewer Opens the Physical Viewer tool m ispDCD Opens the ISP Daisy Chain Download software on PC platforms only Results Menu The following commands from the Results menu are unique to the ispANALYZER m Compiler Report Displays the ispANALYZER report that shows the net name the pin name the pin location and whether the net to pin routing is through the ORP or bypasses the ORP The report file shows the observable nodes that were routed by the ispANALYZER and the existing GLB outputs The external pin name is generated by adding an X prefix to the node name Compiler Log Displays the log created by the ispANALYZER compiler m Pin Layout Displays the package view showing how the pins were assigned during the compile process m JEDEC Displays the JEDEC file for the current workspace You can also view output netlist files that were created during the compile process Using the Physical Viewer Once you have successfully compiled your design you can use the Physical Viewer to view the design implementation You can also obtain timing information and connect observable nodes to output pins using the Physical Viewer
221. lock signal could be a primary input register Q output or a module I O It also lists the number of GLB levels for each path Calculates setup and hold time for boundary registers Calculates Tpd and Tco path delays Calculates GLB boundary delays Performs path enumeration by calculating path delays from all the source nodes to all the primary output nodes The delays listed are in descending order and the source nodes are primary inputs register Q outputs or module l Os To obtain path delays for the remaining destination nodes that include register inputs and module I Os use the Design Manager menus Running the Timing Analyzer Once the design has compiled successfully the Timing Analyzer can be run The Timing Analyzer uses the sim file generated by the ispEXPERT software as input The timing information for the device part in the sim file must exist to perform timing analysis To run the Timing Analyzer 1 select Tools Timing Analyzer Settings from the Design Manager 2 lurn on or off the following items to select the type of analysis you wish to run e Calculate Frequency e Calculate Setup Hold Time e Calculate Tpd e Calculate Tco isoEXPERT Compiler User Manual 178 isoOEXPERT Timing Analyzer 3 Select Tools gt Timing Analyzer Settings gt Select Paths to display the Timing Analyzer Path Selection dialog box Figure 5 9 Timing Analyzer Path Selection Node Selection Analysis Path Criteria Al
222. ls only logic equation and local macrocell control Product Terms Inputs for a Big Fast Megablock are displayed in groups of three each group listing the IOC GLB source pin input net and destination pin Outputs for a Big Fast Megablock are displayed in groups of two each group listing the output net and the output pin Fast interconnect signals show the connections within the Big Fast Megablock and are displayed in groups of three each group listing the net source pin and destination pin The following example is a partial sample of the inputs and outputs and fast interconnect signals for one Big Fast Megablock in the design isoEXPERT Compiler User Manual 240 BigFastMegablock 1 oo Inputs Compilation Report for the ispLSI 5000V 8000 Devices E Source Net Destination A60 BO A60X glb32 124 BO indicates an IOC pin A610 A611 A612 A613 A614 A615 BO i BO BO i BO BO BO A610X A611X A612X A613X A614X A615X GLO32 z IPS GOS Zin qL Zs g1032 103 140 from a Big Fast Megablock 14 Loo I41 13 qo B40 BO B40X glb22 18 B410 B411 B412 B413 B414 B LS B41 B42 B43 B44 B45 B46 B47 B48 B49 glb31 012 g1b31 016 g1b31 02 BO BO BO BO GO GO BO GO G0 GO GO GO GO GO GO B410X BALL B ILZX BAL SSX B414X Ba Lox Ge Zine CDL glb22 Ip 2s
223. lso open the report files using the File menu Use the scroll boxes the arrow keys or the Find function see Using Search and Replace on page 122 to quickly find any information You can open and edit or print any of these files Chapter 7 Design Reports contains examples of the report files as they appear using the File menu y NOTE To access a timing report that is disabled use the Tools gt Timing Analyzer Settings menu item to turn on generation of that report Rerun the Timing Analyzer isoEXPERT Compiler User Manual 182 Timing Explorer Timing Explorer The Timing Explorer provides an interactive method for viewing and querying timing information for the design The Timing Explorer is accessed through pop up menus in the Physical Viewer Refer to Timing Information on page 213 for information on accessing the Timing Explorer from the Physical Viewer Information is calculated in response to your query and the turn around time is fast Only the data you requested displays This section describes methods to use to obtain the timing information you need You can also access the Timing Explorer by displaying a Timing Analysis table using the Results menu of the Design Manager When you access the Timing Explorer in this way all available data is included in the requested table The Timing Explorer consists of the Signal Navigator and several tables Refer to the remainder of this section for details on adding data
224. ly informative and advantageous because you can select multiple settings of Compiler Control Options and examine the compiler results for the best possible implementation of your logic The Explore function keeps track of the results and stores them in a subdirectory of the project directory called ispds run To generate multiple compilations of one project 1 Select Tools Explore Settings from the Design Manager The Explore settings dialog box appears Figure 3 12 Explore Settings Synthesis s High mM No Logic Optimization Explore Criteria Use Global Reset I ON OFF Advanced Partitioner amp Router Timing Analyzer Mas Input Mas Output Extended Routing v Calculate Frequency 1 ON Append to Current Explore Lag 3 C OFF Pin Assignments W Use GUI PinLocks I Use Reserve Pins Iv Free All Pin Locks Ignore Reserve Fins Resource Limit C Limit Elapsed Time to Minutes Unlimited Figure 3 12 Explore Settings Dialog Box 2 Make your selections Hold the Shift key to select multiple choices of one Compiler Control Option The Resource Limit area lets you specify whether each Explore run should be allowed to take an unlimited amount of time or should be limited to the number of minutes or hours you specify If the run exceeds the amount of time you specified that Explore run will terminate with a message and the next run if any will begin Turn on Calculate Frequency in the Timing Analyzer field to
225. mapping of their logic into ispLSI device resources exercise caution when using hard macros with other Design Attributes Certain combinations such as applying CLK or CRIT attributes to the output of a hard macro can make a design infeasible in the specified form The ispEXPERT software usually resolves this by ignoring one or more of these attributes During optimization all or part of an inactive hard macro logic may be removed This may include any unused hard macro output as well as any inputs driven by a constant value isoEXPERT Compiler User Manual 59 Symbol Attributes Example Figure 2 25 is an example of using OPTIMIZE ON and OPTIMIZE OFF OPTIMIZEZON OPTIMIZE OFF SOFT MACRO HARD MACRO Figure 2 25 OPTIMIZE Attribute Usage A NOTE If you use a hard macro in an ispLSI 5000V or 8000 design it is treated as a soft macro isoEXPERT Compiler User Manual 60 Symbol Attributes Preventing Optimization of Primitives The PROTECT Symbol Attribute prevents optimization of the specified combinational primitive during logic optimization of your design PROTECT cannot be used on registers LXOR2s tri state buffers I O pins or hard macros Synopsis PROTECT node_name Description Assign PROTECT to a symbol or an instance of a symbol in your design to prevent optimization of the specified combinational primitive during logic optimization of your design The protected primitive may still be merged with similar
226. may have identified certain options you wish to retain You can name and save the settings that include those successful options into your project directory This option is convenient if you want to reuse or retrieve the settings for your project design The Constraint Manager attributes are also included in design settings Once you use a setting all compiler explore and analyzer results are located in a subdirectory with the same name as the setting To name and save your design settings 1 Select Project gt Save As Setting from the Design Manager The Save As setting dialog box appears Figure 3 18 Save As Setting Setting Marne e Do not use Setting Name OK Cancel Delete Figure 3 18 Save As Setting Dialog Box 2 Type a name into the Setting Name field The Do not use Setting Name check box lets you save the settings as the default unnamed settings You cannot enter a setting name when this check box is active 3 Click OK To delete a setting name click Delete Click Cancel to close the box without saving the settings The Save Settings functions are project specific and the settings for your current project are not available if you change projects When you use the Save Settings command and compile the project the ispEXPERT software creates a new project subdirectory within the project directory Consequently If you need to retrieve certain files for simulation look for them in the project sub
227. ments according to the pin file use IGNORE FIXED PIN ON You can create a pin file using any text editor Save the file as a ppn file A pin file consists of any number of lines each line conforming to the following syntax pin name pin direction pin number pin name is the external pin name m pin direction is IN OUT BIDI or SYS Lines with pin direction identified as SYS are ignored m pin number is the package pin number Design Manager Sequence Assign Pin Locations Click Pin File Select the desired file Parameter File Syntax PIN FILE file name Command Line Syntax y file name isoEXPERT Compiler User Manual 136 Compiler Control Options Identifying Input Files The INPUT FILE and INPUT FORM options identify name extension and format of the design source file Specifying the Name of an Input File The INPUT FILE option specifies an input file name and extension Description The input file is the design source file to be used by the compiler It can be an EDIF or PLA design Design Manager Sequence Project gt New Enter or select design file path name and extension Parameter File Syntax NA Command Line Syntax i file name Specifying the Format of an Input File The INPUT FORM option specifies the input netlist format Description The format of the design source file input netlist is specified using this command option The values for input netlist formats are edif o
228. mo Rod do ef Rd bet Shee ea ae 26 Lattice Semiconductor Device Architecture llle 26 yc eg Logie Blocks GLB e ewiew wu xa tiddi Yd RIXRRNSUAEXQqU EA XPLarECER A 28 Ee re 29 VESON DH iod xo dopE dE ee ee RERO OR ee ee do ee AA ee 30 compiler tone ls aus docs denen dab ooo ACE ER pct SOR bbe OR hehe ee 30 BE 0 MEER TETTE TOIT T OTI T TOT LOT TIT OP TT 30 Chapter 2 Design Attributes eseeeeeeeeeen eee 31 Applying Design Attributes visura tis er bierd ok eec XP ches bed 9dadx rara Rx ba 33 Precedence of Design Attributes nanana aaan 34 Design Attribute Syntax 0 has 34 NO AUNOU aad a WR Y 19d 392 dE EE NE EE en ee ee eee ee eee eee 35 Placing Logic into a Single BFM 0 0 0 ccc rn 35 Assigning Device OE EE oes pa Gerd ee 44s a eee aa 36 ispEXPERT Compiler User Manual 4 Grounna GLE CUIUS EE EERE 39 Preventing the Elimination of Nets n naana naaa aaa 40 Preserving XOR Gales 4c ise ko Ae p oe dia o CEDAR I e e os RC das 43 EE EE SE eee ee eee Eae dod 3 Kr Rr aca dci d d 45 Specifying Asynchronous Paths llle 47 Specifying Critical Paths uua duod 9d ub dRWeRE ques ENE Eds RO 50 Local Speed Power Control ce eee eens 53 Low Power Path Toggle Setting 0 0 ee eee 53 THUS eg aa a ob 4 kee EE EE oases ee ee eee ox 54 Post Compile Turbo Settings 0 0 0 ccc tee eee eens 55 Specifying a No Minimize Path 0 0 0
229. mory requirements of your design use a lower EFFORT level isoEXPERT Compiler User Manual 277 Design Rules Design Rules The following sections describe design rules that you should observe in your design to make it conform better to the Lattice Semiconductor device architecture The iSOEXPERT software conforms to these rules by modifying the user netlist or relaxing the constraints automatically Warnings may be issued if the compiler changes your design significantly to conform to these design rules If the resulting netlist does not meet your requirements use Design Attributes and Compiler Control Options to direct the compiler toward your implementation objectives Sometimes the netlist cannot be mapped or routed if it is too complex or overconstrained A thorough knowledge of the design rules and device architecture is needed to concisely direct the compiler I O Pin Designations All Devices Minimize the use of locked pins on initial design implementations This provides the partitioner and router maximum freedom in partitioning and routing the design Do not lock two signals to the same pin Do not lock data I O pins to clock signals unless you are using the Y2 Y3 shared pins on an ispL Sl 5000V device I O pins that lead to logic that was eliminated during logic optimization are removed from the design ispLSI 1000 2000 3000 and 6000 Devices Only lock non registered inputs to the dedicated input pins to improve us
230. n GLB C1 Q0 PGDFFR GLB C3 Q0 PGDFFR GLB C5 00 PGDFFR GLB C7 Q0 PGDFFR X2 Lx RAM 0 BA1 RAM2S07 REG 1 S1 RGTRSO7 REG 1 S2 RGTRSO7 REG 1 PL3 REG 1 PL2 REG 1 PL1 REG 1 PLO RGIRSO RGTRSO7 RGTRSO RGTRSO7 REG 1 80 RGTRSOT REG 1 PTRST RGTRSOT REG 1 IEN RAM 0 BWL RAM 0 BCS RGTRSU RAM25S07 RAM25S07 XDROLG Hidi XDROIY Hidi RAM 0 BDI16 RAM 0 BDI17 RAM 0 BDI13 RAM 0 BDI12 RAM 0 BDI11 RAM 0 BDI10 RAM 0 BDI8 RAM 0 BDI7 RAM 0 BDI6 RAM 0 BDI5 RAM 0 BDI4 RAM 0 BDI3 RAM 0 BDI2 RAM 0O BDI1 RAM 0 BDIO RAM 0 BDI9 RAM2S07 RAM2S07 RAM2S07 RAM2S07 RAM2S07 RAM2S07 RAM2S07 RAM2S07 RAM2S07 RAM2S07 RAM2S07 RAM2S07 RAMZS07 RAMZS07 RAMZS07 RAMZS07 P T r3 r3 rr rmm m RAM 0O BDI15 RAM2S07 RAM 0O BDI14 RAM2S07 REG H IDIS REG 1 ID14 REG 1 T1D13 REG 17 1D12 REG 1 ID11 REG 1 ID10 REG 1 ID9 REG 1 ID8 REG 1 ID7 REG 1 ID6 REG 1 ID5 REG 1 ID4 REG 1 ID3 REG 1 ID2 REG 1 ID1 REG 1 IDO REG 1 RST REG 1 CHO REG 1 CH1 REG 1 CH2 REG 1 CH3 REG 1 CKO RGTRSO7 RGTRSO7 RGTRSO7 RGTRSO7 RGTRSO7 RGTRSO7 RGTRSO7 RGTRSO7 RGTRSO7 RGTRSO7 RGTRSO7 RGTRSO7 RGTRSO7 RGTRSO7 RGTRSO7 r 31 r1 r3 r3 r3 r3 RGIRSO7 RGIRSO7 RGTRSO07 RGTRS07 EOLROU RGIRSOJ RGTRS07 T 1 r3 r3 r3 r3 r3 mr mmm rcr mmm rm isoEXPERT Compiler User Manual Timin
231. n Implementation Number of Macrocells 8 Number of GLBs 4 Number of IOCs 14 Number of Dis Number of GLB Levels 2 GLB glb00 A2 GLB input name triplets T Bou OS gp 00 010 SEO GINO OL Ql 3239 Co LDU 90 Qro Wy VGlbOLAO0s QS Tolz 9001 NODE START 245 CX OLX Ghd GEN ENX L2 2 OMEPUt S OTO QU COX 93 GLB output name pairs t 2 Product Term s Output QIO 1 4 1 2 Tnoul 5 INODE START Fanout s IR indicat ti indicates connection 102 415 Io ELG TOO Toy DOVER se BL re to the IOC through the GLB Level s ORP QIO D INODE START QIO C CLKX Output COX GLB GglLPUL y JInpurd4s ENX QU QUII 012 Clix QIS 1 Fanout s EOLER 1 Product Term s 1 GLB Level s COX OIO C OIL amp O12 amp QIS amp CIX ENX A3 Job SPEDULOCS GLOD ODD Toly 8 bb vod XII 15 100500 012 i GLDUL 00 Olay LIO Web XDX Jl EO CIX Leys 42305 D2X EO aO DX Ido ENO ENG 120 BD EDK 10 PSSO Po LET 2 QUUDUC SJ isoEXPERT Compiler User Manual 224 Compilation Report OILS Q0 SINAIS 01 Je Product Term s Output Qr 10 Inputs ENG luxe Dox 010 CP Ol Ly 1006 GLa CIX 013 3 Fanout s GIDOOU IO cIDOIXEl6 OSJLIR 4 Product Term s 1 GLB Level s QI3 D PSX KD amp LPM uw PODX Implemented QIO amp OI1 amp QI2 amp CIX amp ENX amp CDX amp LDX through Product Term 5013 S CDX o TLDX we UP Sx Sharing Array
232. n and average number of inputs per GLB Distribution and average number of outputs per GLB List of output enable nets and their fanouts isoEXPERT Compiler User Manual 220 Pre Route Compilation Report The following is an example of the Pre Route Design Statistics section of the report Design Statistics Number Number Number Number Number Number Number Number Number Number Number Number Number Number Number Number Of of OF OF OL OF Of Of OE OF of of OF of of of Macrocells GLBs TOS Nets Free Free Free Free Locked Locked Locked Locked Locked INPUTS Outputs Ihree States BiG Ss Input IOCS Diss Output s Three States Bidi s CRIT Gutpuls Global OES External Clocks GLB Utilization T O Utilization Net Utilization Nets with Fanout of Nets with Fanout of Nets with Fanout of OUE OE oJ 0 OUt Of 32 1959 Out Ot 64 1265 A Ww e Average Fanout per Net GLBs with GLBs with de Chace ys o Hnput6e GLBs with 11 Input s Average Inputs per GLB GLBs with 2 QUEIDULE CS 2 Average Outputs per GLB Number of GLB Registers Number of IOC Registers isoEXPERT Compiler User Manual Oo NM do O O ID N O O OD PH p p Mu 24 2 00 Total Number of Macrocells GLBs IOCs and Nets Breakdown of IOCs into types Utilization of physical resources in the device Distribution and average number
233. nal I O The ispEXPERT software checks each pin for connectivity and tries to honor pins locked by the user Figure 1 7 is an example of the logic resources available in an IOG for the 1000 family of devices From OE MUX Voc Output Enable Active Pull Up From Output Routing Pool From Output Routing Pool Bypass To Global Routing Pool IOCLK 0 IOCLK 1 From Global B E M RESET Represents an E CMOS Cell Figure 1 7 IOC Resources for the 1000 Family of Devices isoEXPERT Compiler User Manual 29 Designing with ispBEXPERT Design Attributes When you create your design you can use Design Attributes to control how the compiler analyzes synthesizes partitions places and routes your design using the physical resources of a selected Lattice Semiconductor device The attributes specify pin assignment register placement clock usage and so on These attributes are described in detail in Chapter 2 Design Attributes Design Attribute constraints represent design goals and restrictions that you want but that may not be critical to the successful operation of a design The ispEXPERT software attempts to meet both design rule and Design Attribute constraints but gives priority to design rule constraints as they are required for functional designs In cases where a Design Attribute constraint contradicts a design rule constraint either the Design Attribute constraint is relaxed or the netlist is automatically modified to
234. nal commands are available isoEXPERT Compiler User Manual 187 Timing Explorer m Setup and Hold Table Displays the setup and hold values of the selected register in the Setup and Hold Table m Tco Table Displays the Tco data of the selected register in the Tco Table From a cell in the Register column of the Setup and Hold Table you can access the Tco Table and it will contain a value for the highlighted register From a cell in the Register column of the Tco Table you can access the Setup and Hold Table and it will contain a value for the highlighted register Timing Path Report When you select the Report Timing Path command the Timing Path Information Window Figure 5 18 displays The report information varies depending on the table you were in when you requested the report The boundary report displays when you access the Timing Path Report Click the Detailed Report button to switch to the detailed report When the detailed report displays click the Boundary Report button to switch back to the boundary report Click the Display Path button to display the path in the Connectivity window of the Physical Viewer liming Path Information Boundary Report Point to Point Delay Path Startpoint O13 Endpoint Q3 data arrival time Shortest Path Hame Q3 Q3 data arrival time Detailed Report Figure 5 18 Timing Path Information Window isoEXPERT Compiler User Manual 188 Running the Timing Analyz
235. nd Mentor Graphics Design Manual isoEXPERT Compiler and Synopsys Design Manual IspEXPEHT Compiler and Synplicity Design Manual IspEXPEHT Compiler and Viewlogic Design Manual isoEXPERT Compiler User Manual 13 Documentation Conventions Documentation Conventions This user manual follows the documentation conventions listed in the following table Convention Definition and Usage Italics Italicized text represents variable input For example design 1 This means you must replace design with the file name you have used for all the files relevant to your design Valuable information may be italicized for emphasis Book titles also appear in italics The beginning of a procedure appears in italics For example To open a project Bold Valuable information may be boldfaced for emphasis Commands are shown in boldface For example 1 Type dpm at the command line Courier Pont Monospaced Courier font indicates file names syntax text that the system displays and reports For example set path Spath SLATTICE Bold Courier Bold Courier font indicates text you type in response to system prompts For example dpm i file name s a l Vertical bars indicate options that are mutually exclusive you can select only one For example CLK CLKO CLK1 CLK2 Titles of chapters or sections in chapters in this manual are shown in quotation marks and bold blue underscored type indicate jumps to the specified chapter
236. nding cell and object identifiers are highlighted in the EDIF file and the Property File 4 Ul OUT Figure B 6 DESIGN B Schematic isoEXPERT Compiler User Manual 297 Attribute Examples cell DESIGN B cellType GENERIC view view 1 viewType NETLIST interface port OUT direction OUTPUT port EN direction INPUT port IN direction INPUT contents Instance U1 viewref view 1 cellref AND2 Instance U2 viewref view 1 cellref AND2 Instance U3 viewref view 1 cellref AND2 Instance U4 viewref view 1 cellref OR3 net OUT joined portRef OUT portRef ZO instanceRef U4 portRef AO instanceRef U6 net NETA joined portRef ZNO instanceRef U6 portRef A1 instanceRef U2 portRef A2 instanceRef U3 net NETP Figure B 7 EDIF File for DESIGN_B PROPERTY DESIGN B NET NETA SAP PATH ENDPROPERTY PROPERTY DESIGN B NET OUT EAP PATHI ENDPROPERTY PROPERTY DESIGN B NET NETP PRESERVE ENDPROPERTY Figure B 8 Specifying Net and Path Attributes in a Property File isoEXPERT Compiler User Manual 298 Attribute Examples Symbol Attributes oymbol attributes are applied to the instances of symbols in your design If an attribute is used as a symbol SYM attribute all the instances of the symbol instance type will have the assigned attribute This example shows how a symbol SYM attribute PROTECT is used Figure B 13 In this case any instantiation of the cell MACRO B
237. ne GLB Level Implementation isoEXPERT Compiler User Manual 52 Path Attributes Local Speed Power Control The SLP ELP and STP ETP path attributes are used to control device speed and power for isoLSI 5000V and 8000 devices These work in conjunction with the LOWPOWER Device Option refer to Global Speed Power Control on page 157 and the Turbo Update Pin Attribute refer to Post Compile Changes on page 112 The ispLSI5000V and ispLSI8000 device families have two fuse selectable speed power trade off settings The fast or high speed setting operates the associated sense amps at their normal full power consumption If you have portions of logic that can tolerate longer propagation delays you can select the slower low power mode which decreases the power to the associated sense amps In the isoLSI5000V device family each block of five product terms has its own dedicated high speed low power control fuse In the ispLS18000 device family each block of four product terms has its own dedicated high speed low power control fuse During design entry you can selectively control the speed power fuse in an ispL Sl 5000V or 8000 device by assigning SLP ELP or STP ETP to paths that lead to the product term block These attributes work in conjunction with the global LOWPOWER Device Option Low Power Path Toggle Setting You can toggle a LowPower path to be LowPower ON Turbo OFF or LowPower OFF Turbo ON by using the SLP and ELP pat
238. ng Delay Added for Reg Counter Out to MIO Delay Added for Reg Counter Out to GRP Delay Added for MIO to Reg Counter Delay Added for GRP to Reg Counter Primitive Name RAM2S07 Instance Name RAM 0 isoEXPERT Compiler User Manual LZ owt OO 18 00 18 00 60 00 00 60 00 60 00 14 60 1 60 0 00 1 60 0 00 12 00 12500 Own ONO 0 N 00 00 00 00 Em he 261 Functional Description 256x18 dual port RAM B Timing Description l External Timing Read Cycle Time Addresss Access Time Chip Select Access Time Global OE Access Time Output Hold from Address Change OE Pin to Output Enable OE Pin to Output Disable Chip Select to Output Enable Chip Select to Output Disable Write Cycle Time Addresss Valid to Write End Addresss Setup to Write Start Chip Select to End of Write tow Write Pulse Width Write Recovery Time Data Valid to Write End Data Hold from Write End RW High to Output Enable RW Low to Output Disable 2 Internal Timing Read Cycle Time Addresss Access Time Output Hold from Address Change Write Cycle Time Addresss Valid to Write End Addresss Setup to Write Start Chip Select to End of Write tcw Write Pulse Width Write Recovery Time Data Valid to Write End Data Hold from Write End O P omncs Delay Added for Memory Out to MIO Delay Added for Memory Out to GRP Delay Added for MIO to Memory Delay Added for GRP to Memory Module Path Report Module Paths Timin
239. ning LI C Information Reset Cancel opal Help Figure 3 35 Options Dialog Box Message Color 2 Use the radio buttons at the far right to select a message type error warning or information 3 Click any color on the grid to change the color of that message type If you want to restore the default settings click Reset Click Apply to change the colors without closing the dialog box To customize a color 1 Click one of the boxes in the Customized Color field in the Pin Color amp Shape or Message Color dialog box 2 Click Color The Color dialog box appears Figure 3 36 Basic colors Define Custom Colors gt gt Cancel Figure 3 36 Color Dialog Box 3 Click a basic color from the grid Click OK The color you chose appears in the Customized Colors field of the Pin Color amp Shape or Message Color dialog box isoEXPERT Compiler User Manual 126 Closing a Project To create additional custom colors 1 Click a box in the Custom Colors field of the Color dialog box and click Define Custom Colors An additional color palette appears that includes Hue Saturation and Luminosity and RGB settings Figure 3 37 Basic colors MILL STE EH 11 MERETI 11 mum n n Es r E EN FC EH ES EH TL BI LEON LEO EN EN RN Hue 73 Fed Sat fiso FO Greer 255 Define Custom Colors gt gt Colors alid Lum 240 Blue 255 Cancel Add to Custom Colors Figure 3 37 C
240. ning internal register paths and their frequencies are also listed if the source and the registers are driven by the same reference clock Maximum Operating Frequency 100 MHz Ihe clock period is 10 00 Clock period path delay clock to output delay setup time path delay 9 00 clock to output delay 0 70 setup time Qu S0 Ihe following path determines the frequency Startpoint GLB QIO QO edge triggered flip flop Endpoint GLB QIO DO edge triggered flip flop No of GLB Levels Z2 Internal Register Paths and Frequencies Source Source Destination Destination Clock Frequency of GLB Reference Register Reference Register Period MHz Levels GLOCK Name Crock Name ns CLK GLB QI0 QO CLK GLB QIO DO 1o D 100 Z CERK GLB QT3700 CLK GLB QI3 DO Dit hoz T CLK GLB_QI0 Q0 CIR GLB Q13 D0 Sus DU 182 1 CLK GLB QI1 00 GER GLB Q13 D0 Sal 182 CLK GLB QI2 Q0 CUK GLB 013 PO Sad D 182 il CLK GLB QIO0 QO GEK GLB QI2 DO 10 00 100 2 CLK GLB_QI1 Q0 CLK GLB QI2 DO LOSUO 100 2 CLK GLB QI2 Q0 GEK GLB QI2 DO Eis t Lo dl CLK GLB QIO0 QO CLK GLB QI1 DO 10 DO 100 2 CLK GLB_QI1 Q0 CLK GLB_QI1 D0 5e 1092 T CLK GLB_QI0 Q0 CLK GLB QIO DO 10500 100 2 isoEXPERT Compiler User Manual 248 Information for flip Lop Global reset to output delay Clock to output delay User reset to output delay Data to output delay Setup time Hold time Pulse width time isoEXPERT Compiler User Manual Oe INO CX CO poc pr 109
241. ning the file from the Results menu You can also move the cursor to a process block and click the right mouse button to display the Results commands that are available for that step of the compilation Use the View ispSmartFlow menu item to turn on or off the display of the isoSmartFlow window isoEXPERT Compiler User Manual 107 Compiling Your Design Figure 3 21 shows an example of the ispSmartFlow window An existing isoSmartFlow reflects the last compile status if it exists or the compile settings when the project opens The color of the processes boxes tells the status of the compile as follows Gray Compile has not been done Tan A compile is occurring and this is the current process Blue Process completed successfully Hed Process did not complete because of an error EE CNT4 ispSmartFlow Compile Synthesis amp Optimization Bit Stream Generation Timing Modal Gene ration bservbility Frnalyzer Figure 3 21 ispSmartFlow Window Check the compiler log for a detailed history of the processes that were run and any errors or warnings The compiler log is similar to the Session Log except it only contains information about the processes that occurred during the compilation To access the compiler log Select Results Compiler Log from the Design Manager or double click on the Log icon in the ispSmartFlow window The Compiler Log appears in a text file window isoEXPERT Compiler User Manual 108 Compil
242. nto a report design rpt andalog file design log containing messages warnings or errors issued by the ispEXPERT processes Parameter File Rules The following rules apply to Parameter Files Each statement consists of an option name followed by the option value Each statement in the file is on a separate line Each set of parameters is terminated by an END statement You can have an unlimited number of parameter sets in a file The symbol at the beginning of a line specifies comments Unspecified options are replaced with default values or values from a design source file m he part number specified in the design source file is assumed unless a part number is explicitly defined in each parameter set m he statements can use any mixture of uppercase and lowercase characters The compiler will stop after running a successful set of parameters or if an error occurs Any output generated corresponds to this successful run or the latest run m When two different part names relating to different packages are used in one Parameter File any pin lockings can be ignored by turning on the IGNORE FIXED PIN option m There is no between any attribute name and value The Parameter File name should have a par extension and must be different than the design name isoEXPERT Compiler User Manual 163 Using a Parameter File Parameter File Example The following is an example of a Parameter File MAX GLB IN 12 PART ispLSI101
243. o optimize designs for delay area or routability Appendix B EDIF Property File Provides the EDIF Property File syntax Appendix C Menu and Icon Reference Shows the menus and tool bar icons for the ispEXPERT Compiler Design Manager the ispANALYZER the Physical Viewer and the Timing Viewer Related Documentation In addition to this user manual the following documentation is useful when using the Lattice Semiconductor ispEXPERT compiler software m isoEXPERT Compiler Getting Started Manual isoEXPERT Compiler Release Notes ISP Encyclopedia ISP Daisy Chain Download User Manual PC only Macro Library Reference Manual 5K 8K Macro Library Supplement VHDL and Verilog Simulation User Manual These manuals as well as the interface manuals listed below are located in the manuals directory on the CD ROM The SP Encyclopedia is located in the databook directory These documents can be downloaded to a local drive or accessed on the CD ROM The ispEXPERT Help menu also provides access to the manuals Third Party Interface Manuals Use the ispEXPERT Compiler software to compile designs from many third party CAE environments The following is a list of manuals that Lattice Semiconductor provides as support to the various third party interfaces Altera to Lattice Semiconductor Design Conversion Application Notes IspEXPERT Compiler and Cadence Design Manual isoEXPERT Compiler and Exemplar Logic Design Manual isoEXPERT Compiler a
244. o the logic resources of the target device Each Design Attribute you add places restrictions on the compiler by giving it less freedom to use available logic resources Apply these Design Attributes carefully to avoid overconstraining the compiler and possibly causing a routing failure The following pages provide the syntax for using each Design Attribute in a property file Refer to Chapter 2 Design Attributes for detailed descriptions of the Design Attributes and the devices for which they are valid Pin Attributes m CRIT oyntax PROPERTY cell name PIN pin name CRIT ENDPROPERTY m LOCK oyntax PROPERTY cell name PIN pin name LOCK pin number ENDPROPERTY m LOCK oyntax PROPERTY cell name PIN pin name LOCK BFM BFM index ENDPROPERTY m LOCK GHRP oyntax PROPERTY cell name PIN pin name LOCK GRP GRP index ENDPROPERTY m PULL Syntax PROPERTY cell name PIN pin name PULL UP OFF HOLD ENDPROPERTY m OPENDRAIN oyntax PROPERTY cell name PIN pin name OPENDRAIN ON ENDPROPERTY m OUTDELAY oyntax PROPERTY cell name PIN pin name OUTDELAY ON ENDPROPERTY isoEXPERT Compiler User Manual 289 SLOWSLEW oyntax PROPERTY cell name VOLTAGE oyntax PROPERTY cell name ENDEROPERIY Pin Array Attributes CRIT syntax PROPERTY cell name LOCK oyntax PROPERTY cell name ENDPROPERTY PULL oyntax PROPERTY cell name ENDPROPERTY OPENDRAIN Syntax PROPERTY cell name KENDPROPERLY OUTDELAY Syntax
245. oEXPERT Compiler User Manual Timing Analyzer Reports 25 Timing Analyzer Reports Selected Path Boundary Report Example The following boundary report design gpt is generated by the Timing Analyzer when Maximum Number is selected in the Analysis Path Criteria area of the Timing Analysis Path Selection dialog box If Longest Shortest is selected the report shows the longest and shortest paths only Select Summary amp Detailed in the Report Type area to automatically generate the boundary report The boundary report contains the delays of paths that have been selected in the Timing Analyzer Path Selection dialog box in terms of GLB General Logic Block and routing delays General Output Routing Pool The boundary report indicates the GLBs through which the signal traverses with their respective delays and the routing delays between them The routing delays are indicated by GRP or ORP ORP Bypass under the first column The GLB is identified by its name in the device in which the design is implemented An example of a Selected Path boundary report follows Timing Analysis Detailed Report Design Name CNT4 Part Name ispLSI2032E 180LT48 This report contains the delays of selected paths in terms of GLB and GRP ORP ORP Bypass routing delays Path Enumeration Startpoint EN input port Endpoint CO output POE Name pin name type Delay Path EN in 0 00 0 00 GRP kyot 1330 GLB_A2 3580 SD ORP ORP Bypass 3 9
246. ogramming information and generates a fuse map in standard JEDEG format The JEDEC device programming file can be downloaded to an ispLSI device using an ispDOWNLOAD cable or any device programmer that accepts JEDEC fuse maps and Lattice ispL Sl devices Additionally the integrated isoVM provides an open programming application that allows programming of all ISP devices through the use of Virtual Machine Files VMF Since the VMF format contains the fuse map data plus the algorithm needed to program devices using this format is a faster and more universal method than using the standard JEDEC file format With the ispVM tool you can m Build and save VMF files from JEDEC files and download the VMF files directly from your system m Convert SVF files to VMF files and download them directly from your system For a list of Lattice Semiconductor compatible programmers and further information on device programming options from PC platforms see the ISP Daisy Chain Download User Manual For device programming from Solaris or HP UX platforms contact your local Lattice Semiconductor sales representative Reports The EXPERT Compiler software provides a compiler report file that shows how your design fits into the Lattice Semiconductor device architecture A variety of timing report files may also be generated refer to Chapter 7 Design Reports The Explore tool may be used to determine the best possible placement and routing of your design
247. olor Palette Dialog Box 2 Click the basic color closest to the color you want to create 3 Move the crosshair cursor to the color you desire 4 Slide the bar triangle to the solid color you desire The values in all the color fields change to reflect the setting Alternately you can change the Red Green Blue and Hue Saturation Lumination values 5 Click Add to Custom Colors The new color appears in the box you highlighted Click OK to return to the Options dialog box The color you chose appears in the Customized Color field and that color appears as the color you will see for the pin or message type you chose Closing a Project When you close a project your work is saved to the project directory and subdirectories This includes all the pin locking settings Compiler Control Option settings Pin Attributes timing analysis data the Explore compilation files all the simulation output files the compiler log and report files isoANALYZER information and the JEDEC file for downloading Be sure all compile and Explore processes have completed before attempting to close a project To close a project Select Project Close from the Design Manager A dialog box appears asking if you want to save the changes to the project Click Yes to save the project changes in the project directory Click No to close the project without saving the changes isoEXPERT Compiler User Manual 127 Chapter4 Design Compilation Options Compil
248. olumn is highlighted Click the right mouse button to display the list of values Select a value it is entered for all the pins signals currently in the table You can then change individual values if desired With the column highlighted place the cursor in the attribute name and click the right button Select Sort to sort based on the values for that attribute You can also assign nonadjacent cells within an attribute by holding down the Ctrl key and using the left mouse button to select the cells you want to assign isoEXPERT Compiler User Manual 5 Constraint Manager To assign a variable to an attribute 1 Double click on the signal or pin name in the design browser The appropriate property table displays with the signal or pin name highlighted Notice the characters before the signal or pin name in the Design Browser turn from green to blue when it is added to the property table 2 Click the cursor in the table cell for the attribute you wish to assign Click the right mouse button 3 Select Edit The cursor changes position and you can type any value into the cell When you are in edit mode you can click the right mouse button to access edit commands Undo Cut Copy Paste Delete and Select All The Constraint Manager does not check the validity of data entered into the cell using the Edit command When you type in a value using the Edit command be sure the entire value is in either all upper case or all lower ca
249. on use the Delay setting Do not lock clock signals To implement arithmetic functions use 5K or 8K macros to take advantage of architecture mapping Considerations for ispLSI 5000V Devices The following guideline should be considered specifically when designing for ispL Sl 5000V devices By default an OE signal will map to a PTGOE Product Term Global Output Enable If the ECP path attribute is specified on the OE net the OE signal will map to a PTOE Product Term Output Enable Mapping to a PTGOE incurs a significantly longer delay than mapping to a PTOE However mapping to a PTOE consumes macrocell resources Considerations for ispLSI 8000 Devices The following guidelines should be considered specifically when designing for ispL Sl 8000 devices Do not lock the inputs or outputs of the internal tristate bus Set the MAX GLB input to 42 or below Max GLB inputs set to 44 may cause some local routing congestion Refrain from using quadrant clocks Quadrant clock usage induces IOC register grouping by clock and constrains the partitioning Do not lock to a quadrant clock doing so restricts the partitioner Do not mix IOCCLK and GLB EN or GLB clocks If both clock and clock enable are local one must come from PT80 and the other from a local PT clock clock enable A T flip flop function is mapped by using the internal feedback for a D flip flop function isoEXPERT Compiler User Manual 281 Designing for ispLSI 5000V
250. onent is highlighted in all open Connectivity windows and the fan ins and fan outs are updated in the Connectivity windows You can turn on and off the check boxes in the Selected Component section to filter the register input information in the fan in section isoEXPERT Compiler User Manual 206 Obtaining Aaditional Information Obtaining Additional Information Additional information is available on GLBs GLB output pins Dedicated Control Input pins Modules IOCs and Module IOCs You can also query timing information for the design or for signals You can compute observability for GLB output pins You can double click on an item from the Connectivity window or Design Navigator window You can also use the right mouse button to bring up a context sensitive window with available commands Input GLB pins can only be accessed from the Design Navigator window Information that can only be accessed through these methods is described in this section GLB Information You can obtain information about a GLB by double clicking or right clicking on a GLB and selecting Device Characteristics from the pop up menu The GLB information dialog box displays Four tabs are available m Resources Shows the resources of the GLB Figure 6 13 This information is the same for all the GLBs in the device A1 GLE Information Resources Utilization Internal Function Inputs from GAP Dedicated Inputs Macrocells Product Terms Figure
251. onflicts are resolved by the Design Manager settings If you used the Project Save Setting option you can retrieve your original pin assignments In this way you can retain several settings of the pin assignments Otherwise once the compiler runs all unassigned pins are treated as free pins and your pin assignments may be lost To compile your design Select Tools Compile or the Compile icon or the Compile button in the isoSmartFlow window The ispEXPERT jet moves showing that your instructions are processing The isoEXPERT software uses the Design Attributes Compiler Control Options and pin assignments to fit your design into the device according to your design constraints and the device architecture To terminate the compile process click the Stop icon When the process is finished the icon is disabled The compile process generates several types of files See ispEXPERT Output on page 22 for the specific files These files are regenerated each time you invoke the compiler If you chose Free All Pin Locks from the Compiler Settings dialog box the compiler will ignore the pin locking sessions you performed using the Assign Pin Locations window and any pin locking specifications from a pin source file During the compile the isoSmartFlow window shows the compile processes currently being performed You can double click on the compiler report icon or the compiler log icon to display the results this is the same as ope
252. or bidirectional pins The OPENDRAIN option is supported for isoLSI 2000V 2000E 5000V and 8000 devices Check the SP Encyclopedia for detailed information about device architecture The OPENDRAIN local Device Pin Attribute assigns the OPENDRAIN attribute to individual pins it overrides the global OPENDRAIN option By default the global OPENDRAIN Device Option is set to OFF Using Output Buffer Delays The OUTDELAY Device Pin Attribute delays the output buffer by 0 5ns for individual output or bidirectional pins on an ispL SI 5000V device Synopsis OUTDELAY ON OFF Description Used with the global OUTDELAY device option this feature enables staggering of output buffers to help minimize noise on the device See Using Output Buffer Delays on page 159 The OUTDELAY local Pin Attribute assigns the OUTDELAY attribute to individual pins it overrides the global OUTDELAY option By default the global OU TDELAY Design Attribute is set to OFF isoEXPERT Compiler User Manual 71 Local Device Attributes Using Pull up or Datahold The PULL Design Attribute specifies individual external pins will use the device pull up or datahold feature Synopsis PULL UP HOLD OFF Description m UP instructs the compiler to pull up high Z pins UP applies to all I O pins including dedicated and control inputs m HOLD supports datahold control for all I O pins excluding dedicated control inputs for the ispL SI 5000V an
253. or schematic entry applications see the appropriate online ispEXPERT Compiler and third party vendor design manual for the proper syntax for your design environment For other design flows especially VHDL or Verilog HDL see Constraint Manager on page 74 and Appendix B EDIF Property File isoEXPERT Compiler User Manual 34 Net Attributes Net Attributes The Design Attributes described in this section can be applied to the nets in your design Placing Logic into a Single BFM Use the BFM Net Attribute to place timing critical logic into a single Big Fast Megablock BFM in an ispLSI 8000 device Synopsis BFM BFM index where BFM index is 0 through number of BFMs 1 For example the ispLSI 8840 device has seven BFMs Therefore the correct index numbers for an ispLSI 8840 device would be 0 through 6 Refer to the SP Encyclopedia for specific information on the ispLSI 8000 device architecture Description A Big Fast Megablock consists of 120 registered macrocells and a Global Routing Plane interconnecting the BFMs The 120 registered macrocells are arranged in six groups of 20 Each group of 20 is referred to as a Generic Logic Block or GLB The capacity then of a BFM is 120 registered macrocells 144 I O connections and six GLBs When you assign the BFM design attribute to a net the entire function from the primary inputs to the output will be mapped to the designated BFM if the BFM capacity is not ex
254. ot related to defective materials or workmanship To receive service during the 90 day warranty period contact Lattice Semiconductor Corporation at Phone 1 800 LATTICE Fax 408 944 8450 E mail applications latticesemi com If the Lattice Semiconductor support personnel are unable to solve your problem over the phone we will provide you with instructions on returning your defective software to us The cost of returning the software to the Lattice Semiconductor Service Center shall be paid by the purchaser Limitations on Warranty Any applicable implied warranties including warranties of merchantability and fitness for a particular purpose are hereby limited to ninety days from the date of purchase and are subject to the conditions set forth herein In no event shall Lattice semiconductor be liable for consequential or incidental damages resulting from the breach of any expressed or implied warranties Purchaser s sole remedy for any cause whatsoever regardless of the form of action shall be limited to the price paid to Lattice Semiconductor for the ispEXPERT software The provisions of this limited warranty are valid in the United States only Some states do not allow limitations on how long an implied warranty lasts or exclusion of consequential or incidental damages so the above limitation or exclusion may not apply to you This warranty provides you with specific legal rights You may have other rights which vary from s
255. ough ORP as signal destination ID represents connection to the IOC through ORP bypass as signal destination OEe where e 0 or 1 represents the IOC enable input as signal destination If global reset is used the user defined global reset signal is reported with the logic of the equation in which it is used If the design has a user defined reset signal it is reported with the reset or preset logic If product term reset and global reset are used the equation is Q tput RsEpolarity global reset sTOQnal product term reset logic If product term preset and global reset are used the equation is output PR polarity global reset signal product term preset logic If only global reset is used the equation for global reset is output R polarity global reset signal If only global reset is used the equation for global preset is output PR polarity global reset signal For the ispLSI 1000 2000 and 3000 device families polarity is always If the design does not have a user defined global reset signal and global reset is used in the equation the following information is reported If no product term reset is used Global Reset Used If product term reset is used output R lt product term reset logic isoEXPERT Compiler User Manual 223 Compilation Report GLB Equations Example The following is an example of the GLB equations portion of the Post Route report Post Route Desig
256. output is part of an asynchronous path its duplication may be undesirable Asynchronous Path specifications prevent the compiler from optimizing logic and duplicating GLB outputs that are located on any path connecting the starting and ending points of the path This design attribute is not supported for the isoLSI 5000V and 8000 devices If SAP and EAP are applied to the same net that net is not duplicated by the compiler if it is implemented as a GLB output Use the PRESERVE attribute to force the compiler to implement that net as a GLB output The following are rules for using SAP EAP Design Attributes m Allowing the compiler to duplicate outputs gives the router more flexibility and can prevent routing problems Using SAP EAP may unnecessarily overconstrain the compiler m Merging similar gates at SAP EAP boundaries that do not have the PRESERVE attribute may cause the output of the resulting gate to be duplicated by the compiler Use PRESERVE to prevent merging similar gates and net duplication m lfanetwith SAP EAP is driven by a signal inversion the net may disappear due to forward or backward merging of the signal inversion over the net Use PRESERVE to prevent merging of a signal inversion over a net with SAP EAP attributes Any buffer on an asynchronous path is implemented as a single GLB level Use caution in specifying asynchronous paths through library macros that have embedded buffers such as input and output buffering ma
257. ovide options for changing the size of the device diagram in the Connectivity window Use View Zoom Bar or the Zoom Bar icon to turn on and off the display of the Zoom Bar Select View gt Zoom In or press F7 to enlarge the diagram Select View Zoom Out or press F8 to decrease the size of the diagram Select View Zoom Default to return the diagram to the default size Select View Zoom To Fit or press F10 to size the diagram so it fits into the Connectivity window isoEXPERT Compiler User Manual 197 Connectivity Window Select Zoom gt Zoom Area or press F9 to zoom a small area of the device diagram When you select this option drag the cursor to identify the area that displays in the Connectivity window Select View Undo Zoom Area to return the device diagram to the previous zoom level after a Zoom Area has been performed Connectivity Views You can display the GLBs in the Connectivity window in three views The information in the views is color coded The colors and the percentages for the congestion and usage levels can be changed in the Customize dialog box Figure 6 5 Select the appropriate command from the View menu to access the Connectivity views m View gt Congestion Shows whether the GLBs are congested or not congested based on the congestion cut off level specified in the Customize dialog box Congestion is determined by adding the number of input pins used in the GLB and all the fan ou
258. own Refer to Specifying a Device on page 90 for information on selecting a device Click EDIF Reader Settings The EDIF Reader Settings dialog box appears Figure 3 2 The settings you specify are applicable only to this project EDIF Header 5 etings z Vendor IM Load vendor specific setting Power and Ground Setting VEC GNO Representation fe Met C Call WCC Name VCC GND Name END Bus Reconstruction Array Index Ordering fe Up Down Least Significant Bit Left Right I Ground floating output pins Property File EI Figure 3 2 EDIF Reader Settings Dialog Box a In the Vendor field specify the vendor of the software used to create the design If you choose Altera from the Vendor pull down menu the EDIF Header Settings dialog box displays additional fields For complete information on how to use the an EDIF file from an Altera tool see the Altera to Lattice Semiconductor Design Conversion Utility Application Notes Whenever the Load Vendor specific settings check box is on and you change the vendor default settings for the selected vendor are loaded If you do not want to change the default settings deselect this check box before selecting a vendor After selecting the vendor you can change settings as needed Cancel isoEXPERT Compiler User Manual 81 Creating a New Project b Set the VCC GND Representation to Net or Cell depending on your design specification c Type a VCC name in the VCC
259. p edge of the Session Log at the bottom of your screen and pull it up to make it visible isoEXPERT Compiler User Manual 124 Optimizing Your Desktop Changing the Pin Color and Shape and Message Color You can change the look of the pins in your design You can also change the colors of the messages that display in the session log To change pin color or pin shape 1 select Edit Options Click on the Pin Color amp Shape tab to display the dialog box shown in Figure 3 34 Use the radio buttons in the center to select a pin type input output or bidirectional Click any color on the grid to change the color of that pin type You can also customize colors as described on the next page Pin Color amp Shape Message Calo Pin Shape Customized Calor a 000D T Round Rectangle Ellipse 9 EE Bidirectional As Reset Cancel pipa Help Figure 3 34 Options Dialog Box Pin Color amp Shape Click on 3D Round Rectangle or Ellipse to change the pin shape for PGA BGA package devices If you want to restore the default settings click Reset Click Apply to change the colors without closing the dialog box isoEXPERT Compiler User Manual 125 Optimizing Your Desktop To change message colors 1 Select Edit gt Options Click on the Message Color tab to display the dialog box in Figure 3 35 Pin Color amp Shape Message Color Customized Color ODD ee DB L C War
260. perate and indicates the number of GLB levels It aso lists all the registered paths in the design and their corresponding frequencies See Frequency Analysis Report on page 248 for an example setup and Hold Report design tsu shows the setup hold requirements of all the boundary registers in the design See Setup and Hold Report on page 250 for an example Tco Report design tco lists all the path delays from a primary input that drives the clock inputs of the registers whose Q output drives a primary output See Tco Report on page 251 for an example Tpd Report design tpd lists all the path delays between the primary inputs and the primary outputs of the design See Tpd Report on page 252 for an example selected Path Summary Report created when Summary Only is selected generates the design spt file which contains only summary information for the paths selected in the Path Selection dialog box See Selected Path Summary Report Example on page 253 for an example Selected Path Boundary Report design gpt is created when the Timing Analyzer runs It details the signal as it traverses through different GLB boundaries See Selected Path Boundary Report Example on page 258 for an example Selected Path Detailed Report created when Summary amp Detailed is selected generates a detailed version design dpt of the timing analysis report It provides a complete path trace of each selected path See Selected Path
261. perty statement Is PROPERTY cell def object def property def ENDPROPERTY m cell def IDENTIFIER A cell definition where IDENTIFIER is any valid cell name taken from the EDIF file to be read in with the Property File using the EDIF reader Read the EDIF file in any text editor to identify cell names in the design In a hierarchical design cell names can be top level design names or macro names isoEXPERT Compiler User Manual 286 EDIF Property File Syntax m object def pin def l pin array def instance def net def symbol def An object definition can be a pin def pin definition a pin array def pin array definition an instance def instance definition a net def net definition or a symbol def symbol definition e pin def PIN IDENTIFIER A pin definition where IDENTIFIER is any valid pin name preceded by the keyword PIN e pin array def PINARRAY IDENTIFIER A pin array definition where IDENTIFIER is any valid array name preceded by the keyword PINARRAY e instance def INST IDENTIFIER An instance definition where IDENTIFIER is any valid instance identifier preceded by the keyword INST e net def NET IDENTIFIER A net definition where IDENTIFIER is any valid net identifier preceded by the keyword NET e symbol def SYM A symbol definition where any valid symbol name is preceded by the keyword SYM n NOTE The SYM property is assigned to the current cell unlike others that are assigned to ob
262. pilation trial results Running the ispEXPERT compiler Using the ispANALYZER Using the Static Timing Analyzer isoTA Using the Timing Viewer Using the Physical Viewer Understanding log and report files Design rules and tips Parameter File syntax Property File syntax Command line syntax Where to Look for Information Chapter 1 Introduction Provides an overview of ispEXPERT and its design flow Chapter 2 Design Attributes Describes how Design Attributes can be used to specify design constraints Chapter 3 Design Compilation and Control Provides information on using the IispEXPERT Design Manager Chapter 4 Design Compilation Options Describes each Compiler Control Option and provides the Design Manager sequence the parameter file syntax and the command line syntax Also describes a Parameter File and the Design Process Manager dpm Chapter 5 Timing Analysis Provides information on using the Timing Analyzer iso TA and the Timing Viewer Chapter 6 Physical Viewer Describes the Physical Viewer and its relationship to the Timing Viewer and the information it provides Chapter 7 Design Reports Explains the different sections that make up the post route and pre route compiler report files and provides examples of timing reports isoEXPERT Compiler User Manual 12 Helated Documentation Appendix A Design Rules and Tips Describes device dependent design rules and user tips t
263. pile update Pin Statistics A listing of each input output and bidi pin by pin name pin number and the pin attribute assigned if any oymbol Attributes A list of attributed symbol instances in the design grouped by symbol attribute name Net Attributes A list of attributed nets grouped by net attribute name Path Descriptions The path name type Critical Asynchronous or No Minimize starting point and ending point See Chapter 2 Design Attributes for more information about paths The following is an example of a Design Specification section Design Specification Design CNT4 Part ispbh512032E 110L5I49 ISP ON ISP EXCEPT Y2 OFF PULL UP DEDE Mia Device Options Yl AS RESET ON OPENDRAIN OFF S LOWSLEW OFF Number of Critical Pins Number of Free Pins 11 Number of Locked Pins 4 IOC Statistics Number of Reserved Pins 0 Input Pins Post Compile Update Pin Name CD CI CLK Pin Attribute PULLUP PULLUP Pin Statistics PULLUP isoEXPERT Compiler User Manual 218 DO D1 D2 D3 EN LD PS Output Pins Post Compile Update Pin Name CO QO Q1 Q2 Os Input Pins Pin Name CD CI CLK DO BEN D2 D3 EN LD PS Output Pans Pin Name CO QO Ql Q2 Q3 Reserved Pins Cell Name IO14 LOLS LOT TOLI IOl0 Compilation Report EULBUP PULEUP EULBUP PULLUP PULEUP PULLUP PULEVUP Pin Statistics Pin Attribute PULLUP SLOWSLEW OPENDRAIN PULEUP PULLUP SLO
264. pin to see Pin Tips a bubble box that displays the pin name cell name and pin assignment for that pin To see all the pins hold the left mouse button down and move the cursor slowly over each pin To remove a pin assignment Double click on the pin in the package view The pin returns to the Unassigned Pins list To free pins by type Click the Free Pins Input Output Bidirectional or All buttons Those pins return to the Unassigned Pins list The pin locking session is saved to the project directory when you select Project gt Close or Project Save As Setting from the Design Manager menu If you use the Save Setting options the pin assignments are saved to the project subdirectories For information on how to use this option see Naming and Saving Design Settings on page 104 You can also lock pins using the Constraint Manager You may want to look at the Assign Pin Locations window to see the physical pin numbers that are available for locking Either lock pins using the Constraint Manager or close the Constraint Manager and lock the pins using the Assign Pin Locations command isoEXPERT Compiler User Manual 97 Design Exploration Design Exploration Once you select a device and make pin assignments you can perform compilation trial runs to identify compilation qualifications of your design You can generate multiple design compilations and examine the results using the Explore function It can be extreme
265. pins In this example IO3 and pin 00 in GLB A5 were the selected pins If you select more than two pins the path will be between the last two pins selected Paths that cross a register do not display However if a selected destination point is an output register a path that crosses the register that contains the destination point will display For example you can select a clock signal and an output register and all possible paths between these two points will display 99 m al al HE HA aa mr C EP d fee e 5 Figure 6 9 Example of Connectivity Window in Path Mode isoEXPERT Compiler User Manual 203 Connectivity Window select View gt Timing Path Mode or the Timing Path icon to display timing paths The Physical Viewer automatically switches to Timing Path Mode when you select the Display Timing Path command from the pop up menu in the Timing Matrix Table If the longest timing path displays it is shown in red If the shortest timing path displays it is shown in green Paths that cross a register do not display However if a selected destination point is an output register a path that crosses the register that contains the destination point will display For example you can select a clock signal and an output register and all possible paths between these two points will display EE HA GH d MU HE Ub Figure 6 10 Example of Connectivity Window in Timing Path Mode isoEXPE
266. primary output nodes in your design are preserved You can allow the compiler to expand individual XOR gates by assigning the local XOR OFF net attribute to the output node of the target XOR gate When the global XOR compiler option is ON and you have an XOR gate that you want to preserve that is not on a primary output node for example in the middle of a feedback loop assign XOR ON to the primary output node of that XOR gate as well Example In Figure 2 10 the global XOR is OFF and a local XOR attribute has been assigned to the output node X of the last XOR gate The target XOR will be preserved as shown X1 X2 X X5 D X7 X8 Figure 2 10 XOR Gate Implementation with XOR Attribute Assigned isoEXPERT Compiler User Manual 43 Net Attributes In Figure 2 11 global XOR is OFF and a local XOR attribute was not assigned to the output node X of the last XOR gate The implementation results in the XOR being expanded to the AND and OR gate level Figure 2 11 XOR Gate Implementation without XOR Attribute Assigned isoEXPERT Compiler User Manual 44 Path Attributes Path Attributes Path Attributes can be used to identify a set of paths as Asynchronous Paths Critical Paths Low Power Paths No Minimize Paths or Turbo Paths Each path identifies a single net as the starting point of the path and a corresponding single net as the ending point of the path Any starting point path specification that does not have a correspon
267. put pin is not shown in the Connectivity view You can see the GLB input pins in the Design Navigator or the Path Tracer isoEXPERT Compiler User Manual 201 Connectivity Window Select View Fan In Mode or the Fan In icon to see signals that drive the selected IO Dedicated Control Input or other GLB output pin These signals could be coming from other IOCs Dedicated Control Input pins or GLB output pins Figure 6 7 Click on the pins for which you wish to see fan in information UU Hl B Figure 6 7 Example of Connectivity Window in Fan In Mode Select View gt Fan Out mode or the Fan Out icon to see the IOCs Dedicated Control Input pins and GLB output pins the currently selected component drives Figure 6 8 Click on the GLB output pin Dedicated Control Input pins or IOC for which you wish to see fan out information BB Al Al amp HH Ha aa we E E EE EP EJ EI 5 es Figure 6 8 Example of Connectivity Window in Fan Out Mode Both Fan In and Fan Out can be on at the same time Selecting any other mode turns off Fan in and or Fan out modes isoEXPERT Compiler User Manual 202 Connectivity Window select View gt Path Mode or the Path icon to show the path between two GLB pins Dedicated Control Input pins or IOCs Figure 6 9 Select the GLB pins Dedicated Control Input pins or IOCs you want to see the path between by holding down the Ctrl key and clicking on the
268. r device programming log Log file containing processing error and information messages 1mc Simulation file for Logic Modeling Corp mfr Clock Frequency report file mpt Module timing report file ppn Post route pin file rpt Compiler report file containing design parameters design specifications pre route design statistics and post route design statistics sdf Standard Delay Format netlist file for back annotation with conditional delays sim Default timing simulation file spt Summary timing analysis report tco co report file tpd Tpd report file tsu Setup and Hold report file who VHDL non VITAL format netlist file for timing simulation with maximum delays vhn VHDL non VITAL format netlist file for timing simulation with minimum delays vlo Verilog format netlist output file for simulation xpn Pin file generated during compilation vsf Standard Delay Format netlist file for back annotation without conditional delays vto VHDL VITAL format netlist file for timing simulation vxf Cross reference file for VHDL output files isoEXPERT Compiler User Manual 25 Designing with ISpEXPERT Designing with ispEXPERT The ispEXPERT software uses Design Attributes to specify design constraints for the selected Lattice Semiconductor device The Compiler Control Options define the parameters of the synthesis process and the objectives of
269. r pla For Viewlogic EDIF design files the viewlogic value should be used when using the dpm command Design Manager Sequence Project gt New select a value in the Project Type field Parameter File Syntax NA Command Line Syntax 1f Format where format IS edif pla viewlogic isoEXPERT Compiler User Manual 137 Compiler Control Options Controlling GLB Inputs and Outputs The MAX GLB IN and MAX GLB OUT Compiler Options specify the maximum number of GLB inputs and outputs the compiler can use for each GLB Specifying Maximum GLB Inputs The MAX GLB IN option specifies the maximum number of GLB inputs the compiler is allowed to use for each GLB This applies to every GLB in your design Description The range and default settings for MAX GLB IN are dependent on the device family being used The values are 1000 2000 2 to 18 3000 6000 2 to 24 5000V 34 to 68 68 8000 22 to 44 Specifying MAX GLB IN 18 results in the maximum use of device resources in the isoLSI 1000 and 2000 device families This usually results in the minimum level implementation of any wide logic However it also causes an increase in placement and routing difficulties for the design Placement and routing may then take more time or may fail Specifying MAX GLB IN 12 to 14 may produce results similar to specifying MAX GLB IN 18 but requires less time to route Specifying MAX GLB IN 24 results in the maximum use of device resources in the isoL
270. r supplying information to users covering Design Analysis GLB Hesources External Pins and Routing An automated tool that uses the device files and design files to place design components GLBs and IOGs and route the interconnections The Router reads design constraint data specified during logic entry from the design netlist Predefined blocks of logic consisting of macros and primitives that can be edited Mapping placement and routing is not predetermined for soft macros isoEXPERT System User Manual 327 Numerics 6192 report 182 261 A Analyzer Mode 205 Append to current Explore Log 99 Arrays 82 296 ASCII UES 106 Assign Device 90 menu 310 Pin Attributes 92 Pin Locations 95 UES 106 Assign pin locations 95 Asynchronous Paths 47 Asynchronous paths 45 Attributes 296 applying 33 BFM 35 CLK 36 CRIT Y net 291 297 OPENDRAIN 71 OPTIMIZE 59 OUTDELAY 71 parameterized 303 path 292 297 pin 289 294 pin array 290 precedence 34 PRESERVE 40 PROTECT 61 PULL 72 REGTYPE 62 RESERVE PIN 69 SAP EAP 45 47 SCP ECP 50 SLOWSLEW 73 SLP ELP 53 Index SNP ENP 56 SIP ETP 54 symbol 293 299 syntax 34 updating pin 113 VOLTAGE 73 XOR 43 156 B Bar Mode Physical Viewer 201 Process 124 otatus 124 Tool 124 Tool Physical Viewer 193 Zoom 124 Zoom Physical Viewer 197 Batch compiling 98 Batch files 167 BFM 33 35 291 BFM Packing for Routability 130 Binary UES 106 Boolean Equation GLB
271. re supported by the Lattice macro libraries This attribute is not supported for ispL SI 5000V and 8000 devices Synopsis OPTIMIZE ON OFF Description A soft macro is a predefined netlist of a particular logic function A macro may also be pre mapped to the ispL Sl architecture for optimal resource utilization or performance ouch a pre mapped representation of a macro is a hard macro The default for hard macros that can use the OPTIMIZE Design Attribute is OPTIMIZE OFF which instructs the compiler not to optimize them not to make them soft They are treated as black boxes which are pre mapped in the ispL Sl architecture To change these hard macros to soft macros add the OPTIMIZE ON attribute to each applicable macro instance This tells the compiler to use the netlist of that macro and optimize it with the rest of your design All other macros are soft only including any user created macros To change an optimized soft macro back to its original hard macro state change OPTIMIZE ON to OPTIMIZE OFF This can only be done on soft macros that are also available in hard macro form Every hard macro in the macro library has an equivalent soft macro but there are some soft macros that do not have equivalent hard macros If you attempt to specify OPTIMIZE OFF on a soft macro that does not have a corresponding hard macro an error occurs See the Macro Library Reference Manual for more details Because hard macros require predefined
272. ribute allow you to preserve any or all XORs in your design When the global XOR compiler option is OFF all XOR gates in your design are expanded In this case you can preserve individual XOR gates by assigning the local XOR ON net attribute to the primary output node of the target XOR gate When the global XOR compiler option is ON default all XOR gates on primary output nodes in your design are preserved You can allow the compiler to expand individual XOR gates by assigning the local XOR OFF net attribute to the output node of the target XOR gate When the global XOR compiler option is ON and you have an XOR gate that you want to preserve that is not on a primary output node for example in the middle of a feedback loop assign XOR ON to the primary output node of that XOR gate as well Design Manager Sequence Tools Compiler Settings Select Preserve XOR Parameter File Syntax XOR ON OFF Command Line Syntax xor turns OFF global XOR isoEXPERT Compiler User Manual 156 Global Device Options Global Speed Power Control The LOWPOWER device option is used to control device speed and power for ispLSl 5000V and 8000 devices This option works in conjunction with the SLP ELP and STP ETP path attributes refer to Local Speed Power Control on page 53 and the Turbo Update Pin Attribute refer to Post Compile Changes on page 112 Global Speed Power Control The LOWPOWER Device Option is accessed through the Assign g
273. ribute should be attached to a net leading directly to the clock input of one or more registers Any intervening logic gates except simple buffers and inverters disable the relationship between the CLK attribute and the clock signal and any registers driven by such a signal Any registers with clock reset or data inputs driven by constants GND or VCC and whose outputs cannot be toggled are removed and their outputs may be replaced by the constant GND Any clock attribute attached to the clock inputs of these registers is ignored Table 2 3 shows the precise outputs you can expect from the compiler Table 2 3 Expected Compiler Results was Gb v Remove Register Remove Register CLK_EN Remove Register RST PRESET Remove Register Any clock attribute applied to a clock signal that is driving both GLB and IOC registers split clock should completely describe the desired clock line usage Certain combinations of CLK attributes may be acceptable within the constraints of the specified Lattice Semiconductor device when separated by commas For example CLR CLR LOCLAD FASTCLK see the SP Encyclopedia for more information on legal combinations for each LSC device All Lattice Semiconductor devices have dedicated clock pins that can help increase the operating speed of the part For more information on dedicated clock pins see the SP Encyclopedia isoEXPERT Compiler User Manual 37 Net Attributes Example Figure 2 2
274. riteria Dialog Box Turn on and specify a value for Number of Max GLB Levels Less Than or Equal to When a compilation completes that has a GLB level at or below the value specified Explore stops Turn on and specify a value for Max Frequency Greater Than or Equal to When a compilation completes that has a maximum frequency at or above the value specified Explore stops You can specify either or both of these options Click First Success if you want the compiler to stop after it successfully compiles If this is turned on the other two options are automatically turned off Click OK to set the Explore Criteria options or Cancel to close the dialog box Click OK in the Explore Settings dialog box to set the Explore compile choices you chose or Cancel to close the box isoEXPERT Compiler User Manual 99 Design Exploration The Explore function works just like the compile process and generates the same files The Explore function changes only the options that are available in the Explore Settings dialog box not options such as device selection speed grade or pin attributes The Explore results go into a subdirectory called 1SDOS3 fr select Tools Explore from the Design Manager menu A message box displays showing the number of Explore runs that will be performed Click OK to start the exploration 7 The ispEXPERT jet moves showing that your instructions are processing To terminate the Explore process click the Stop
275. rk In the project directory do not create a text file using the same name as the project name project creation will fail Create Mew Project Select Design File Marne Directories C usptoalz is VE xamplessE dif Em C E gt isptools E gt ispcomp Drives fc List File Extension Project Type edn edf EDIF Device JispLSI5384 1 25LB388 Select Device Figure 3 1 Create New Project Dialog Box 2 Choose the directory and drive if applicable information where the design source file is located isoEXPERT Compiler User Manual 80 Creating a New Project Choose a project type The choices are EDIF and PLA When you change this field the List File Extension value changes You can also select in the List File Extension field to select a file with an alternate extension If you select a PLA project a Case Sensitive check box appears in the Create New Project dialog box Turn on this option to indicate the PLA design being read in is case sensitive If you chose an EDIF file type the EDIF Reader Settings button appears as shown in Figure 3 1 Choose a design file from the File Name list The Project Name field changes to show this file name Your design and project can have different names but it is recommended that you keep the default Choose the project directory This directory is where you want to store your projects Click Select Device if you want to select a device other than the default sh
276. rlag writer Menu Commands VHDL writer Software Introduction Manuals Interfaces Pull down Menu Manual Settings Error Messages Results License Agreement Compiler Report About sp NALTAER Compiler Log Pin Layout JED EL Help Pull down Menu VHDL Nethst k verlag Netlist EDIF Netlist Results Pull down Menu isoEXPERT Compiler User Manual 315 Tool Bar Icons ISDANALYZER The following table shows the ispANALYZER icons lists their names and describes their function Table 3 2 ispAnalyzer Tool Bar Icons os name mem Observable Node Mapper Compiler Compiler Report isoEXPERT Compiler User Manual Opens an existing text file This could be a property file a pin file a report file a design file etc Equivalent to the File gt Open menu item oaves the existing text file Equivalent to the File gt Save ispANALYZER Workspace menu item Displays the Observable Node Mapper dialog box Equivalent to Tools Observable Node Mapper Runs the ispANALYZER compiler Equivalent to Tools gt Compile Displays the compiler report Equivalent to View Compiler Report Displays the Print dialog box to allow printing of the active file Equivalent to File Print Searches for the next occurrence of the string specified in the Find or Replace dialog box Activates context sensitive help Equivalent to pressing F1 when the item is active Stops the curren
277. rmation auci do o reo dade des dox OR RR d 118 Cleaning A Project Directory anana ccc RII Rn 119 Vee ace e EEE EE 120 TE GE EEE ERE Ree Gee Eee dae as bo ae 121 HE AE REE EVE 54 64 ee es 121 Saving a Text 154 234253 9 2 93 9 3 030 9 Eee i IER ICI REOR Ghee Rees 121 Openmnga Tet Filo auus css qoa dos d o CHACO CRUS C RORCRC NAG Hd Rx ROO eS 121 ENIRO TEN S EEE ERE TETEN 122 Using Search and Replace 2 aaaea eee eens 122 Clearing the Session LOO asus esa uA Gee ee oe sob ERE SEH bees Ee eee ACE 123 Sys EEE QI ee ee eee ee ETE EE ee T 123 Optimizing Your EE lls a wanda een ee eee Forex d e404 RERO 3A ECR OR E GE YEAR 124 Changing the Screen Displays lille 124 Changing the Pin Color and Shape and Message Color 000 000 ee 125 Coso selhuy e aude h ects eee hese sree ke Fed Hh Eq POE Rd da diu dd EXE X ins 187 Chapter 4 Design Compilation Options esee 128 Compiler Control Options llle an 129 BFM Packing for Improved Routability llle 130 Pe FIN POON PTT TTL 131 Specifying Case Sensitivity llis n 131 Controlling Optimization suc acm cdam beg Ged ICE EEE caer POR EE e x RO CR 132 Setting Effort Levels uL iua de EE oe N 132 Choosing Optimization Strategies llle 132 Controlling Routing Time llle n 134 Controlling Pin Assignments anaa aaea 135 Peda ka a eee EE ie eee EC ee eer eee E
278. rned off but they cannot be turned on simultaneously The PULL UP or PULL HOLD device options are displayed in the Design opecification section of the Compiler Report as follows m PULL UP is displayed as PULL UP m PULL OFF is not displayed m PULL HOLD is displayed as DATAHOLD ON Design Manager Sequence Assign Pin Attributes Pull Move all pins to the appropriate list Parameter File Syntax PULL UP HOLD OFF Command Line Syntax NA isoEXPERT Compiler User Manual 160 Global Device Options Setting Slow Slew Rate The SLOWSLEW option specifies the slew rate for all output and bidirectional pins to in your design The default value is OFF Description SLOWSLEW ON places slow slew rates on all output and bidirectional pins The SLOWSLEW option has no effect on routing or resource utilization If SLOWSLEW OFF is specified the slew rate for individual pins can be changed by using the SLOWSLEW Design Attribute By default the global SLOWSLEW Device Option is set to OFF The SLOWSLEW local Pin Attribute assigns the SLOWSLEW attribute to individual pins it overrides the global SLOWSLEW option See Setting Slow Slew Rate on page 73 Design Manager Sequence Assign Pin Attributes Slow Slew Move all pins to the appropriate list Parameter File Syntax SLOWSLEW ON OFF Command Line Syntax NA Setting Device Voltage The VOLTAGE device option sets the output drivers on all I O pins to drive either 3 3V
279. rom the Design Manager The Device Selection dialog box appears Figure 3 8 Device Selection Cancel Device Options ispLsi1000 ispLSI200D Device 5384v Security M ISP Speed 125 F ISP EXCEPT Y2 D vi A5 RESET 8388 Bes TDE AS IO M PLEC M CPGA BGA LowPower M T FP M POFP p i JLEC I MOFP Grade Com OM Use Less Power OFF Increase Speed Figure 3 8 Device Selection Dialog Box 2 Use the Family and Package check boxes in the Device Filter area to change the select New Device pull down list at the top The currently selected device remains in the Select New Device list even if the selections in the Device Filter area would eliminate the current device This allows you to reselect the current device 3 Select an ispL Sl device from the Select New Device pull down list The oubselection values change to reflect the new device 4 Alternately you can choose from the Subselection list Be sure the Family check box for the device you want is turned on You can then select the following items ispl513000 ispLSIBODD M ispLSI5000 F ispl 518000 Device Speed Package Grade The Select New Device field will reflect the device that meets your requirements isoEXPERT Compiler User Manual 90 Specifying a Device 5 Select the Device Options Device options depend on the device architecture for the part and not all options are available for every part See the SP Encyclopedia The Devic
280. s to specify the ORP bypass you could cause the GLB logic to be specially grouped If device resources are very limited this could cause your design to become unroutable m Use moderation in making any changes to the Compiler Control Options MAX GLB IN MAX GLB OUT and so on These changes have a global effect and are likely to cause a very different layout of your design m To modify PULL SLOWSLEW OPENDRAIN OUTDELAY VOLTAGE or TURBO pin attributes you can use Tools Post Compile Update to change the JEDEC device programming file perform Timing Analysis and generate output netlist files without recompiling the project Improving a working design requires using the Design Attributes and Compiler Control Options to specify your design needs By default the compiler implements a globally optimized design The report file represents implementation of logic and the log file may include some warnings that can normally be ignored Designers who want to fine tune their design can use the report and log files to identify logic that must be implemented in certain ways to meet their specific needs These requirements need to be identified and specified for the compiler before a desirable implementation can be achieved isoEXPERT Compiler User Manual 276 Improving a Working Design Optimizing for Speed The primary compiler properties that affect speed input to output propagation delays are the following m CHIT EFFORT PRE
281. s 210 eC eee eee eee Se ee eee ee ee ee ED 211 oe Gadud ko eae hey eee Seas a hohe eee ee ep epee at bends C eee hee 212 Observability Information for GLB Pins 0 0 eee 213 ee FRERE a EESE TESTET ee ee eee ETE eid Chapter 7 Design Reports 0 000 cece cece cece eee enne 214 EUROS DEB EEE a RR ee en ee ee Y AREA RA 215 Compilation Report 2 nnana anaa oo 2 9 9725 83 FOE d de EG dos war ER dd s 6 a 216 Design Parameters Section lille 217 Design Specification Section eee rn nn nn 218 Pre Route Design Statistics Section llle 220 Post Route Design Implementation Section 0 0 0 ce eee 222 Oe cao 2 24210943 EEE Se OE RDIOS OR A OR ECCE DHESEOLACR E E d 4C 222 GLE Bore 19 EE Pp UE eed de RUE aes 224 Module Section 1 eee ee eee eens 227 Pin and Clock Information a Y ee ee ae UR RD Y ERES 228 Summary SIBUSIES Lu sao dee beaded eee ewe eww dad eeae en raris asses beans 231 Pre Route Design Implementation Section 0 0 ce ees 234 Fail to Fit Information 2 ogg eee oe hea he ee NE 236 Compilation Report for the ispLSI 5000V 8000 Devices 0 0 00 cee ee 23 Design Specification Section 0 060 cies eens 237 Post Route Design Implementation Section 0 0 0 cc eee 238 Timing Analyzer Reports ca cue oe s6 54644 64405 Seo be ho abode Ee dade dba eee ead s 248 Frequency Analysis Report 0 0 0 eee eee eee 248 Setup and Hold R
282. s a design browser that lists all the pins nets symbols and cells in the design The window on the right shows the attribute table that can be used to set attributes There are attribute tables to set pin attributes net attributes and symbol attributes When you expand the browser to show the Input Pins Output Pins and Bidirectional Pins you can add these pins to the Pin Attributes Table and assign pin attributes to them When you expand the browsers to show Cells you can assign Symbol attributes when you double click on Cells you can assign net attributes to the nets when you expand the Cells to the lowest level You can also assign net attributes to the signals in the Nets category If your EDIF design contains attributes or if you read in an EDIF Property File when you created your project or if you set pin attributes using the Design Manger those values display in the attribute tables If you make changes to the attribute tables the new values are reflected in your project You can create a Property File by selecting the File gt Save Property As menu item isoEXPERT Compiler User Manual 74 Constraint Manager You can open an existing Property File by selecting the File 2 Open Property menu item The values from the Property File being opened are reflected in the property tables You can save changes to the open file using File gt Save Property Setting Attributes This section describes the procedures for adding pins and
283. s been reserved isoEXPERT Compiler User Manual 69 Design Pin Attributes When you assign reserved pins you need to specify the package pin numbers In Figure 2 34 the package pin numbers are 1 through 48 as shown by the inside numbers on the pin diagram Figure 2 34 Package Pins Numbers Examples To reserve pins in a PLA property file use statements similar to the following PLSI PROPERTY RESERVE PIN 14 PLSI PROPERTY RESERVE PIN 26 To reserve pins in an EDIF Property File use statements similar to the following PROPERTY CNT4 SYM RESERVE PIN 26 ENDPROPERTY PROPERTY CNT4 SYM RESERVE PIN 3 9 14 15 ENDPROPERTY isoEXPERT Compiler User Manual 70 Local Device Attributes Local Device Attributes Device pin attributes control settings for features that influence the physical behavior of the device These features include but are not limited to voltage slew rate and open drain These device pin attributes can be set globally or locally local assignment overrides global assignment This section describes the usage of the local device pin attributes For descriptions of using global pin attributes see Chapter 4 Design Compilation Options Using Device Open drain The OPENDRAIN Device Pin Attribute specifies whether individual external output or bidirectional pins will use the open drain feature Synopsis OPENDRAIN ON OFF Description The OPENDRAIN Device Pin Attribute can only be attached to output
284. s limitation includes three GLB clocks and two I O clocks where available m Adesign can have a maximum of five external global clocks YO to Y4 in the isoLSI 3000 device family a maximum of four external global clocks in the ispL Sl 1000 device family except isoLSI 1016 and a maximum of three external global clocks in the ispLSI 2000 device family and ispLSI 1016 m AllispL Sl 1000 devices except the isoLSI 1016 have only one external global clock Y2 that supplies both GLBs and IOCs In the ispLSI 1016 both Y1 and Y2 can supply both GLBs and IOCs provided that Y1 and Y2 are not set to perform other functions m If you specify Y1 asa clock signal you get an error if Y1 AS RESET is ON Y1 AS RESET applies only to ispLSI 1016 2032 and 2064V 44 and 48 pin devices m Pin Y1 can drive IOCs only on the ispLSI 1016 other devices must use Y2 or Y3 to clock IOCs where IOC registers are available m Do not use internally generated clock signals as data lines Do not lock a clock signal to the Y3 pin if it is used in a module block for the ispL Sl 6192 devices m Do not use more than 5 clock signals for 8 banks of a register counter module the 6000 family of devices isoEXPERT Compiler User Manual 280 Designing for ispLSI 5000V and 8000 Devices Designing for ispLSI 5000V and 8000 Devices The following rules should be considered when creating designs for the ispL SI 5000V and 8000 device family For the Strategy Compiler Opti
285. s the largest delay from start point to end point The shortest path is the path that has the smallest delay from start point to end point y NOTE Paths starting from power Vcc or ground GND connections are not considered since these connections do not propagate transitions isoEXPERT Compiler User Manual 169 Timing Analysis Overview Frequency Calculation The performance of a circuit is usually measured by frequency The higher the frequency the faster the circuit The Timing Analyzer first examines the D inputs of all destination registers looking for the Q outputs of source registers If it finds a Q output the Timing Analyzer adds the propagation delay through the source register and the setup time for the register to the path delay time and stores the resulting value After the Timing Analyzer has examined all registers the maximum delay time of all values calculated will be the minimum clock period value This value in turn gives the maximum allowable clock frequency An accurate frequency calculation by the Timing Analyzer assumes the registers in the design are controlled by a single clock Frequency calculation may be skewed if the registers in the design are controlled by a gated clock No frequency calculation is done by the Timing Analyzer if either of the following conditions exists m Adesign has no register m Adesign has registers but it has only one register level Frequency Calculation Example
286. same reference clock otherwise the field is left isoEXPERT Compiler User Manual 20 isoEXPERT Functions blank The clock signal could be a primary input register Q output or a module I O It also lists the number of GLB levels for each path m Calculates setup and hold time and boundary register for flip flops and latches Calculates Tpd and Tco path delays m Performs path enumeration by calculating path delays to all the source nodes from all the primary output nodes The delays listed are in descending order and the source nodes are primary inputs register Q outputs or module l Os To obtain path delays for the remaining destination nodes which include register inputs and module I Os use the Design Manager menus Timing Viewer The Timing Viewer displays timing information in table format You can access the Timing Viewer after you perform Timing Analysis by displaying reports using the Results menu You can also access the Timing Viewer through the Physical Viewer You can request a variety of timing information for signals or registers You can also display timing paths in the Physical Viewer Connectivity window isoEXPERT Compiler User Manual 21 ispEXPERT Output ispEXPERT Output ispEXPEHT can create a variety of output formats for post compilation design analysis design verification and device programming Netlist Formats The compiler creates user specified netlists for use with third party simulators and Lattice
287. se characters To clear an existing value assigned to an attribute 1 Highlight a cell or column of cells containing attribute values 2 Click the right mouse button and select Clear All attribute values will be removed You can also clear non adjacent cells in all columns by holding down the Control key while selecting cells To delete attributes 1 Highlight a cell or column of cells containing attribute values 2 Select Edit Delete All attribute values are cleared from the cell or cells OR 1 Highlight a row corresponding to a signal or pin name 2 Select Edit Delete The row is removed from the property table and all attributes assigned to that signal or pin are deleted isoEXPERT Compiler User Manual 76 Constraint Manager Using the Constraint Manager with the Design Manager You can open the Constraint Manager once you created or opened a project in the ispEXPERT Compiler Design Manager The Constraint Manager will reflect the attributes included in the EDIF design file read in from a Property File optional or set using the Assign Pin Attributes dialog box As you make changes to the attributes using the Constraint Manager these new attribute values are used in the project Your design prp file is modified only if you open and save it using the Constraint Manager This section describes how the Constraint Manager interacts with the ispL Sl Compiler Design Manager as described in Chapter 3 The De
288. sed the default settings the compiler report files are created and saved in the project directory If you used the Project Save Setting feature the compiler result files are created and saved into the project subdirectories isoEXPERT Compiler User Manual 216 Design Parameters Section The Design Parameters section describes the running environment such as Compiler Control Options from the Design Manager command line or Parameter File The following is an example of a Design Parameters section Design Parameters CASE SENSTETVE ON EFFORT 2 IGNORE_FIXED_PIN OFF MAX GLB IN 15 MAX GLB OUT OUTPUT FORM EDIF OS VERSION Windows 95 PARAM FILE _CNT4 PIN FILF CNTA xP SIRATEGY AREA TIMING ANALYZER OFF USE GLOBAL RESET ON isoEXPERT Compiler User Manual 217 Compilation Report Design Specification Section The Design Specification section summarizes the inputs into the program This section of the report contains the following information Design The name of the design Part The part name of the target device for this design The part name reflects speed changes made in the Post Compile Update IOG Statistics The number of critical pins Critical Pins unlocked pins Free Pins and locked pins Locked Pins Post Compile Update Pin Statistics A listing of each input output and bidi pin by pin name pin number and the pin attribute assigned if any as a result of the post com
289. shows the assignment of a clock signal to the dedicated clock line CLK2 CLK CLK2 Figure 2 2 Assigning a Clock Signal to a Dedicated Clock Line isoEXPERT Compiler User Manual 38 Net Attributes Grouping GLB Outputs The GROUP Net Attribute identifies GLB outputs that are to be grouped during partitioning The GROUP attribute can be used with ispL Sl 1000 2000 3000 and 6000 devices Synopsis GROUP group_name Description Any net with the GROUP attribute is preserved in the resulting netlist Furthermore nets with GROUP attributes and with the same group names are grouped as GLB outputs of a single GLB where possible Such a GLB can still be split by the placement and routing process when necessary to improve routability The GROUP attribute is ignored if more than four nets with GROUP attributes have the same group names The GROUP attribute has the lowest precedence among Design Attributes therefore it will be ignored if it conflicts with any architectural constraints or any other Design Attributes Use the GROUP attribute carefully with other Design Attributes to guarantee a feasible grouping of logic after synthesis Refer to the report file from the compiler to see the implementation of logic after synthesis or to deduce the possible cause of a grouping violation Example Figure 2 3 shows an example of the GROUP attribute assigned to two nets net D and net H in a design using an ispLSI 1000 2000 or 3000 dev
290. sign ON or to question the user if routing time is very long OFF Default is ON Use Global Reset Allows the compiler to move a global register reset signal to the global reset pin Default is ON Cannot be turned off in 5000V and 8000 device families Use Internal Tristate IO Driver Controls whether the IO driver is used for the internal tristate bus for ispL Sl 8000 devices Advanced Setting Use Parameter File Only opecifies the name of a Parameter File for the Enter or select the Parameter File compiler to use The Parameter File name must be different than the design name and have a par extension Interfaces opecifies the output netlist format to be Select all desired Output Formats generated for post route simulation Device in displayed dialog box dependent values are EDIF LMC Verilog VHDL and Viewlogic isoEXPERT Compiler User Manual 87 Using the Interfaces Menu Using the Interfaces Menu The Interfaces menu provides tools to specify how EDIF input files are read and to specify how EDIF netlist files are to be created It also contains menu items to generate netlists EDIF Input Files The EDIF Reader Settings dialog box refer to Figure 3 2 is used to specify how the EDIF design file is to be read in Values set in this dialog box before opening a project are default values The Property File field is not available when you are setting defaults Whenever you create a new project these default valu
291. sign Implementation report is generated only if routing fails It contains partitioned design statistics at the time of the routing failure The cause of the routing failure is indicated after the list of output enable nets and before the Pre Route Design Implementation header The Pre Route Design Implementation report is similar to the Post Route Design Implementation report except the GLB IOC and the Input Output location information is not included The following is a portion of a Pre Route Design Implementation report Design Implementation Macrocells 4 GLBs 9 LOES SI DIES O GLB Levels 2 GLE Gl1b0 parti o Inpubtis 1N482 S1N518 LAF Q3 _LAF Q4 _LAF Q5 PIN CD PIN EN PIN LD L O0Uutputis LAF Q4 5 Product Term s Output LAF 04 8 Inputs 6 05 33 02 SING Gb bart s02 SlN518 TIK Hart Ol ALBAE O03 glibO partl O0 LAF 07 T Oglbl O0 LAE 05 CD 9 PIN OD ENZO PIN EN 10 0 PIN BD o Fanout s Gib 354 GIDU Part LeTo Globo Ppart2s L2 GB Dgrto9L2o OA IR 5 Product Term s 1 GLB Level s LAF Q4 D LAF Q4 amp PIN EN amp PIN LD amp PIN CD amp S1N518 amp LAF 03 KAP 05 PIN EN amp PIN LD 1 PIN CD amp ISI1INS1S8 amp t LAF 03 PIN LD amp PIN CD LAF Q4 C SIN482 amp PIN LD amp PIN CD LAF Q4 amp PIN ID amp BUF 1116 _LAF_Q4 amp LAF 05 amp PIN EN amp i t SEN CD isoEXPERT Compiler User Manual 234 Compila
292. sign Manager You may close the Constraint Manager at any time during your compiler session If you do not close the Constraint Manager it is automatically closed when you close a project All attribute values for the project are saved when the Constraint Manager is closed If the Constraint Manager is automatically closed when the project is closed the Constraint Manager opens automatically the next time you open or create a project It is not necessary to do a Project Update to read in a new Property File just open the Property File using the Constraint Manager When you read in a new Property File the attributes in the Property File overwrite the existing attributes for the project Attributes are saved as part of the project settings To test different Property Files or to set up different attributes name and save the project settings If the Constraint Manager is active and you select Assign Pin Attributes the Constraint Manager displays with the Pin Property Table active To set RESERVE PIN close the Constraint Manager before selecting Assign gt Pin Attributes If you change the device for your design the Constraint Manager will be reconfigured automatically to reflect the attributes for the new device To ensure the Property File is updated correctly open the Constraint Manager before you select the Assign gt Device menu item If you want to assign the LOCK attributes to pins you may want to look at the Assign Pin
293. signals to property tables and for assigning attribute values To add all the pins or signals to a table 1 3 Expand the area of the design browser Input Pins Output Pins Bidirectional Pins Cells or Nets Double click on the top level name Input Pins Output Pins Bidirectional Pins Cells Nets All the pins signals in that category will be added to the appropriate table Assign property values for individual signals pins or for all signals pins in the table To add an individual pin or signal to a table 1 3 Expand the area of the design browser Input Pins Output Pins Bidirectional Pins Cells or Nets Double click on the pin or signal name The pin or signal is highlighted in the property table Assign property values for individual signals pins To assign constant values to an attribute for individual signals or pins lis 3 Double click on the signal or pin name in the design browser The appropriate property table displays with the signal or pin name highlighted Notice the characters before the signal or pin name in the Design Browser turn from green to blue when it is added to the property table Move the cursor to the table cell for the attribute you wish to assign Click the right mouse button From the list of values select the value you need To assign constant values to an attribute for multiple signals or pins pru 2 qe Click on the attribute name in the table header The c
294. stination Pin Output Net eee lu g1b30 133 OUTPUTA EO g1b31 133 OUTPUTA EO Each Big Fast Megablock contains six GLBs that are interconnected by a Big Fast Megablock Routing Pool BRP These GLBs are numbered 0 to 5 During routing not all GLBs in a Big Fast Megablock may be used Each GLB equation lists the GLB name for the design the Big Fast Megablock to which it is assigned and the GLB number inside the Big Fast Megablock to which it corresponds The following is an example of a GLB equation for a Big Fast Megablock EN GLB Name Big Fast Megablock Number GLB Number GLB glb06 BigFastMegablock 5 lt 2 gt 9 Inputs B3360 BIS 159 dQBSdoGOBSZqX oak Boo sGOy B55X 12514 B56uGO B56X 129 Bod oGO B5TIX 150 1 8598 60 B99X 136 Eo9GO PL SD COESBOO0 OE5BN 229 LCAL GO YCAIX T12 0 BackDoor Input s o OUDDUL ES BURT ON ISI QUJcXCDSITUe6 0195 0 911525 Qc PSS Oy Oe y wISLbLZd 49dy ISIILITO O5 F I1S196 OG 0 Local Feedback s 15 Product Term s 15 Turbo Product Terms 0 GLB Control Product Terms isoEXPERT Compiler User Manual 243 Compilation Report for the ispLSI 5000V 8000 Devices If the GLB contains internal tristates the logic of each tristate and whether that tristate is an output or an output enable is displayed The following are examples of internal tristates for glbO6 Internal Tristate Output BUF 2769 p THPUL CS OEDBX 1 Fanout s glb06 0E0 Pro
295. t Device menu item in the ispEXPERT Compiler The LOWPOWER radio buttons in the Device Selection dialog box control whether a lower power mode ON or a faster speed mode OFF are used for the ispLSI 5000V and 8000 devices Description The LOWPOWER Device Option allows you to globally select a lower power mode or a faster higher power speed mode Default for the isoLSI 8000 device family is ON Default for the ispL Sl 5000V device family is OFF m LOWPOWER OFF turns on all of the Speed Power fuses on the device This setting operates the device at its normal full power consumption and decreases propagation delays y NOTE The LOWPOWER OFF setting is NOT recommended for the isoLSI8840 device m LOWPOWER ON turns off all of the Speed Power fuse product terms used on the device This decreases overall device power consumption but may increase propagation delays The LowPower settings are applied to Product Terms as Turbo On LowPower Off or Turbo Off LowPower On as shown in the Compiler Report Turbo settings are determined by the following guidelines m Product Terms are grouped the same as the macrocells Each group of Product Terms has one Turbo fuse that controls Turbo On and Turbo Off m Amacrocell output path is Turbo On if all groups of Product Terms are Turbo On otherwise Turbo Off is set m f Product Terms are shared by both a turbo path and a low power path Turbo has precedence isoEXPERT Compiler User Man
296. t Compile Update dialog box appears Select the Turbo tab to be able to change individual settings as shown in Figure 2 20 Post Compile Update Pull Slow Slew Open Drain OutDelay Voltage Turbo Speed Show Signals Signal Mame GLE Name GLB Loc 4 GIO 1N365 COX D D 0 j D D j 0 D 0 j 1N413 Actions Update Cancel Help Figure 2 20 Post Compile Update Turbo Settings The settings can be changed as follows You can change a macrocell output from Turbo On to Turbo Off e f no Product Term in this macrocell is shared with any other macrocell e f at least one group of Product Terms used in a macrocell is not shared by other Turbo macrocell outputs If all the Product Terms in a macrocell are shared by other macrocells that are set to Turbo On you cannot change the setting to Turbo Off it stays set as Turbo On You can always change a macrocell output from Turbo Off to Turbo On A macrocell output was originally set to Turbo Off but it was changed to Turbo On automatically when other outputs were updated This occurs when all Product Terms used in this macrocell are shared by other macrocell outputs that are already set to Turbo On or that you set to Turbo On isoEXPERT Compiler User Manual 55 Path Attributes Specifying a No Minimize Path Use the SNP and ENP Path Attributes to identify a No Minimize Path in your design This attribute is not supported in ispL Sl 5000V or 8000 de
297. t is selected the report shows the longest and shortest paths only To generate the summary report see Timing Analysis Overview on page 169 An example of a Selected Path summary report follows Path Enumeration Report Design Name CNT4 Part Name ispLSI2032E 180LT48 This report lists the source nodes for the destinaton nodes primary outputs D inputs and clock inputs of registers Path Enumeration Source Destination Path Delay Name pin name type Name pin name type ns EN in CO out S uU Ci an CO out 9 UU GLB QIO QO reg CO out 8 40 GLB QI1 QO reg CO out 8 40 GLB QI2 QO reg CO out 8 40 GLB QI3 QO reg CO out 8 40 GLB QI3 QO reg Q3 out 2 40 GLB QI2 QO reg O2 out 3 90 GLB QI1 QO reg OL out 3 90 CLB QIO QO reg QO out 2 40 CLK in GLB QI3 CLK reg 1 40 EN in GLB QI3 DO reg Ds d Ds arn GLB QI3 DO reg S10 PO fan GLB QI3 DO reg Fel CD xm GLB QI3 DO reg 5a 10 CI an GLB QI3 DO reg 5 0 LO lin GLB QI3 DO reg S10 GLB QI3 QO reg GLB QI3 DO reg 4 50 GLB QIO QO reg GLB QI3 DO reg 4 50 GLB QI1 QO reg GLB QI3 DO reg 4 50 GLB QI2 QO reg GLB QI3 DO reg 4 50 CLK in GhB OF OTRA reg 1 40 D2 iri GLB QI2 DO reg 9 60 EN in GLB QI2 DO reg 9 60 PS in GLB QI2 DO reg 9 60 isoEXPERT Compiler User Manual 253 Timing Analyzer Reports GD fan GLB QI2 DO reg 9 60 EX Dan GLB QI2 DO reg 9 60 LD Lan GLB QI2 DO reg 9 60 GLB QIO QO
298. t process 316 Menu and Icon Reference Physical Viewer Pull Down Menus Tools Customize Frint Ctrl F Print Preview w Design Navigator Path Tracer Timing Viewer Print Setup E xil Window Zoom ln F7 New Connectvity Window oor Lut Fo oor Default oon Toft F10 NOM Area F3 Undo oom Area Cascade Tile Horizontally Tile vertically Close All Information windows Arrange Icon Refresh F5 w 1 Lonnectiviby Sew Fan ln Made Fan Uut Mode Fath Made Timing Path Mode Analyzer Made Window Pull down Menu Congestion Help Topics GLE Utilization LI sed lLInused About ipt SPERAT Physical Viewer Tool Bar Help Pull down Menu Status Bar oor Bar Made Bar View Pull down Menu isoEXPERT Compiler User Manual 317 Tool Bar Icons Physical Viewer The following table shows the Physical Viewer icons lists their names and describes their function Table 3 3 Physical Viewer Tool Bar Icons os Wome Omen Toggle Device Navigator Toggle Zoom Bar Toggle View Mode Bar isoEXPERT Compiler User Manual Turns on and off the display of the Device Navigator window Equivalent to Tools Device Navigator Turns on and off the display of the Zoom Bar Equivalent to View Zoom Bar Turns on and off the display of the View Mode Bar Equivalent to View View Mode Bar Displays the Print dialog box to allow printing of the active file Equivalent to
299. tate to state Acknowledgments The ispEXPERT Compiler software is based on a Sequential Interactive System SIS developed by the Computer Aided Design CAD Research Group at the University of California Berkeley with significant enhancements and additions by Lattice Semiconductor Corporation IspEXPERT Compiler User Manual 3 Table of Contents ge TNT 11 What Is In this User Manual i42aaau 3 dx EROR e945 0999999 409 AG RO A RR CREER Y ad 12 Where to Look for Information aaa eee ene 12 Related Documentation bg a on Gee REEF EE 3 OE Od E AER 306 o wd Foe rb dex 13 Third Party Interface Manuals 0 00 cc eee IIR 13 Documentation Conventions 0 0 eee ee ee eee ees 14 Chapter 1 Introduction 0 ccc ee eee eens 15 TO Fay SE fc bd mad oe ee oe oe ne eae eee eee oe eee eee ee cere es 17 Ba 9 ENE 17 GE EEE 18 KE Je EG EERSTE EEE EEE EISNER 18 Synthesis and Partitioning llli 18 Placement and ROUN EN 19 Se gl D 19 Physical Viewer a prc ee ee eee EET EEE 20 eee FE TRE EEE PO 406k ede ghee ee ee eee di e a 20 WO VIGNO REE EE 21 NE FET lic fe ee er ee ee ee ee ee ee ee rs ee ee eee bj 22 ESTE GE EEE ES EAEE 22 Fuse Map Generation usa naesepessuxrXTRbERE GO Rc eo ERA DA POR e ed X ben de 23 HOD ee rr EE 4034 ee ee ee ee ee eS eee ee eee 23 x GNSS REESE heed des oN oe ease kde een ee ba yes ENE 24 Designing Sam ISpEX PERT au auae ar
300. te logic designs for the Lattice Semiconductor in system programmable Large Scale Integrated ispLSI devices This user manual describes the capabilities and use of the isoEXPERT software It is written for design engineers who understand system and logic design and the use of design automation software You should also understand how to perform basic procedures using your operating system This manual contains information to guide you through compilation and device programming It is the primary learning guide to help you use the software to design with Lattice Semiconductor ispLSI devices This manual shows screens captured in Windows 95 If you are using a workstation or a different Windows product the appearance of the screens may differ slightly some technical reference material is included in this user manual to provide you with background material However you should be familiar with the Lattice Semiconductor device architecture Read the Lattice Semiconductor ISP Encyclopedia to fully understand all the features of the Lattice Semiconductor devices isoEXPERT Compiler User Manual 11 What Is In this User Manual What Is In this User Manual This user manual contains information and procedures on the following topics Using Design Attributes to specify design constraints Using the Design Manager to lock pins and set pin attributes Using Compiler Control Options to specify design objectives Using the Explore function to determine com
301. te with the same path name m Ihe ETP Design Attribute specifies the End of a Turbo Path and does not require a matching STP attribute Synopsis SIP patnul patha e pato ETP pathl path2 pathN Description The STP and ETP Design Attributes perform two functions First when the global LowPower Device Option is ON STP and ETP instruct the compiler to turn off LowPower for the specified path and set the control fuse to high speed Turbo Second STP and ETP specify the path as a Critical Path that is it instructs the compiler to minimize the number of GLB levels in a given path and to minimize the signal path delay within each GLB level by utilizing a four product term bypass if possible This is similar to specifying SCP and ECP For more information about SCP and ECP see Specifying Critical Paths on page 50 For ispLSI 8000 devices the compiler tries to place functions on the same turbo path marked ETP into one BFM This results in enhanced timing performance similar to using the BFM net attribute However if you are using a tristate bus the compiler cannot place logic into one BFM Refer to ispLSI 8000 Tristate Usage on page 282 for details isoEXPERT Compiler User Manual 54 Path Attributes Post Compile Turbo Settings You can also change the Turbo settings for individual signals after your design successfully compiles Select the Tools Post Compile Update menu item in the Design Manager and the Pos
302. ter implementation by ispEXPERT The following are some points to remember when simulating your design oignals representing power and ground lines VCC and GND nets should be properly asserted before simulation begins if the simulator does not understand these signals as special nets XRESET is not required if the reset symbol is moved to the global reset pin using the USE GLOBAL RESET ON option Otherwise XRESET is required and should be toggled to low to globally reset all registers If you are using an ispL Sl 1016 2032 or 2064V 44 and 48 pin device with Y1 AS RESET set to OFF no global reset is available and registers can only be reset if the Product Term reset is defined for them XTEST OE should be set to high if an ispLSI 3000 5000V 6000 or 8000 device is used However if TOE AS IO is set to ON for an isoLSI 5000V device it is not necessary to set XTEST OE to high If you use a keyword as a user specified signal name or if you use a reserved prefix as part of a user specified signal name the name is changed by isSOEXPERT and is not available to the simulator in its original form Pin names are retained in a timing simulation netlist However internal names may not be accessible to a timing simulation netlist A PRESERVEd net name is available in a timing simulation netlist if it is not inactive and if it is not an internal name similar to an external pin name However the compiler may duplicate the PRESERVEd net thereby
303. ternal tristate bus Instead a buffer is inserted and the IO is directed to a GLB before driving the internal tristate This may result in more delay but allows for better routability with more complex designs Design Manager Sequence Tools Compiler Settings Click Advanced Select Use Internal Tristate IO Driver Parameter File Syntax NA Command Line Syntax uit to enable this option isoEXPERT Compiler User Manual 148 Global Device Options Global device options control settings for features that influence the physical behavior of the device These features include but are not limited to voltage slew rate and open drain These device attributes can be set globally or locally local assignment overrides global assignment This section describes the usage of global device options Global Device Options You can use the Design Manager to change the attributes on individual pins or on all pins see Specifying Pin Attributes on page 92 If you use the Design Manager to change the OPENDRAIN SLOWSLEW OUTDELAY OR VOLTAGE attributes on all pins this will also change the global setting in Design Specification section of the report file If you change the PULL UP or PULL HOLD attributes on all pins in the Design Manager the settings are displayed in the Pin Assignments section of the report file For descriptions of using local pin attributes see Chapter 2 Design Attributes This section provides a description the Desi
304. tes Figure 2 28 causes a warning because an IOC register cannot be clocked by a GLB clock REGIYPE LOC CLK CLK2 REGTYPE IOC D Q CLK CLK2 Figure 2 28 Conflicting REGTYPE and CLK Usage isoEXPERT Compiler User Manual 63 Design Pin Attributes Design Pin Attributes Design pin attributes control pin usage in your design during design compilation Before compilation you can use Compiler Settings in the Design Manager to specify whether fixed and reserved pins should be ignored or maintained when the design is compiled Bypassing the Output Routing Pool The CRIT Pin Attribute instructs the compiler to use the Output Routing Pool ORP bypass for ispL Sl 1000 2000 3000 and 6000 devices The CRIT attribute is not supported for the ispL SI 5000V and 8000 device families Synopsis CRIT Description Use CRIT for GLB outputs that require the least possible delay You can place CRIT only on output or bidirectional pins CRIT attributes placed on nets are ignored You may restrict routing and device resource utilization if you specify too many CRIT outputs Certain combinations of the CRIT and LOCK and or CRIT and CLK attributes may cause a conflict resulting in a warning message and one or more of those attributes may be ignored Example In Figure 2 29 the CRIT and LOCK attributes require the two registers to be placed in the same GLB but they require two different global clocks and cannot be placed into the same GLB
305. the Output Netlist Results Post Compile Changes Analyzing the Design Downloading Your Design onto a Device Cleaning Your Project Directories isoEXPERT Compiler User Manual 78 Updating a Project Using a Text File Optimizing Your Desktop Closing a Project isoEXPERT Compiler User Manual 9 Creating a New Project Creating a New Project The ispEXPERT software accepts standard input files from third party CAE tools The acceptable input files include EDIF and PLA TT2 When you use an EDIF file you should check the EDIF reader settings so the IispEXPEHRT software can read the file properly The EDIF reader settings can be set before a project is open by selecting Interfaces EDIF reader settings These settings are the defaults used for creating new projects When you create a new project click EDIF Reader Settings on the Create New Project dialog box to specify settings for this project The default settings display in the EDIF Reader Settings dialog box Change them as needed You can also specify a property file for the project To create a project 1 Select Project gt New from the Design Manager menu The Create New Project dialog box appears Figure 3 1 Each time you create a project the ispEXPERT software creates a subdirectory in the selected directory The subdirectory name is the project name The directories should have read and write permissions in case you are copying files or are using designs over a netwo
306. tion Report GLB GIDU Part2 o Inputis SENS UO LAE 00 LAF O4 EAF 05 SINGS SGEIINCOD PIN EN PIN SED L Output LAF Q3 6 Product Term s Output LAF Q3 8 Input s J160 DutboxOzy SINS 9160 Dert2s Ql LAF 0373 G USO part O0 LAR O04 y Glib 200 BARS 190500 S1g8995J5 ED Og PINCO CEN Oy PEN EN ED Oe BIN Hp 5 Fanout s Gib T2 GIBO partlco2zy GIBO parts Lie GIH Darts OS GR 6 Product Term s 2 GLB Level s isoEXPERT Compiler User Manual 235 Compilation Report Fail to Fit Information When the design does not fit the following section is attached to the end of the Design Specification section of the compiler report file ovnthesrs and Ppartr tioning Seat teres Number of Macrocells 4 Number of GLB 18 Number of Product Terms 209 Max number of GLB levels 4 Average number of inputs per GLB 12 6 Average number of outputs per GLB uL Average number of PTs per GLB 13 43 Number of GLBs 18 exceeds maximum number of available GLBs 16 in part ispLSI1016 80LJ44 Synthesis and partitioning completed unsuccessfully Design process management completed unsuccessfully There are two possible cases in the fail to fit situation The compiler exits very early in the process if it detects that the number of macrocells or the most optimistic estimation of the number of GLBs exceeds the available resource In this case it will output only the Number of Macrocells and Number of GLBs entries If
307. tlist gt Non VITAL Max Delays to display the non VITAL netlist that reflects maximum delays m Select Results gt VHDL Netlist gt Non VITAL Min Delays to display the non VITAL netlist that reflects minimum delays To display the Verilog netlist file select Results gt Verilog Netlist To display the EDIF netlist file select Results EDIF Netlist isoEXPERT Compiler User Manual 111 Post Compile Changes Post Compile Changes Once your design is compiled you can change the SIM or JEDEC file without recompiling the design Importing a Pin File You can also use a different pin file after you have successfully compiled your design The contents of the pin file are read and the pin assignments are made The pin file can come from several sources including one that is generated after you compile your design a text file that you create or any text file that you import for this purpose The text file that you originally used may not coincide with the project pin file after you perform compilation If you want to use a different pin file click the Pin File button in the Assign Pin Locations window Refer to page 136 for information on creating a pin file A CAUTION Ifyou import a pin file you will lose the previous pin assignments To import a pin file into your current project 1 Select Assign Pin Locations or the Assign Pin Locations icon from the Design Manager The Assign Pin Locations window appears
308. to make the changes to your design The dialog box remains open To remove a pin from the list on the right select the pin It is highlighted Click Remove It moves to the list on the left For the Pull attribute assign a different value Use Add All or Remove All to move all the pins between the lists Do not use these when you have multiple pins selected as these override your selection and move all pins If you assign an attribute to all the pins you have set a local attribute on all pins you cannot assign these attributes globally using the Design Manager If you select OK the dialog box closes and the changes are made to your design If you select Cancel the dialog box closes and the changes are not made to your design n NOTE Whatever changes you make by selecting Apply are made to the design even if you later select Cancel The dialog box for Reserve Pin lists the device I O pin names while the dialog boxes for the other attributes list the design pin names The Add All button is not enabled for Reserve Pin All the pin attributes except Reserve Pin can also be set using the Constraint Manager If you have the Constraint Manager open and select Assign Pin Attributes the Constraint Manager opens with the Pin Property Table displayed To use the Assign Pin Attributes dialog box close the Constraint Manager before selecting Assign Pin Attributes isoEXPERT Compiler User Manual 94 Locking the Pins Lockin
309. ts for all the used output pins of that GLB m View gt GLB Utilization Shows the GLBs in the device as high medium or low usage or not used based on the utilization cut off levels specified in the Customize dialog box Utilization is how much of the GLB resource based on available product terms is used gm View gt Used Unused Shows the used and unused GLBs in the device isoEXPERT Compiler User Manual 198 Connectivity Window Customizing the Connectivity Window You can select the colors that are used to display information in the Connectivity window Select Tools Customize to open the Customize dialog box Figure 6 5 In the Colors tab you can specify colors to distinguish between used and unused IOCs Dedicated Control Inputs and GLB pins For GLBs you can specify the colors and the percentages for the two utilization levels and the congestion level Customize Colors Other Options Functional Blacks GLE Utilization Level 4 E Utilization Level2 x 57 Unused L Low Medium TT High Congestion Cut off 50 Not Congested ES Congested E IOC Unused L Used L D edicated Cantral Input Unused L Used GLE Pin Unused L Used C Default Cancel Apply Help Figure 6 5 Customize Dialog Box Colors isoEXPERT Compiler User Manual 199 Connectivity Window select the Other Options tab to specify whether the HDL format is VHDL or Boolean Equation
310. ttributes assigned In the resulting implementation Figure 2 24 the gates on the No Minimize Path Path1 are maintained resulting in a glitch free latch function EN SNP Path1 Figure 2 23 Circuit Using SNP ENP Before Compilation Figure 2 24 Circuit Using SNP ENP After Compilation isoEXPERT Compiler User Manual 57 Symbol Attributes Symbol Attributes This section describes the following Design Attributes that are used as or assigned to symbols in your design m LXOR2 m OPTIMIZE gm PROTECT gm REGTYPE Implementing an Exclusive Or The LXOR2 Symbol Attribute enforces implementation of a two input exclusive or function using a hardware two input exclusive or Synopsis LXOR2 node name Description In schematic based applications specify this attribute through instantiation of a library primitive normally named LXOR2 In ABEL HDL environments you can achieve the same results by using an ABEL HDL ISTYPE XOR This removes any ambiguity in recognizing the exclusive or gate The LXOR2 is a Lattice Semiconductor primitive for 2 input XOR gates The limitation is one 2 input XOR gate per GLB output Check the SP Encyclopedia for the maximum number of LXORs allowed per device isoEXPERT Compiler User Manual 58 Symbol Attributes Optimizing Hard Macros The OPTIMIZE Symbol Attribute specifies a hard macro to be optimized as a soft macro and can only be used with design packages that a
311. tus Bar Process Bar Session Log Fataali View Pull down Menu isoEXPERT Compiler User Manual 309 Menu and Icon Reference Tools Compile Compiler Settings Constraint Manager Timing Analysis Timing Analyzer Settings k Froject Mew Ctrl F Open X Ctl F2 Update Llose Ctrl F Clean Ctrl F4 Information Save Setting ET E Explore Settings Fost Compile Update ISBEAFER T Physical Viewer Project Pull down Menu isp NALYTZER IspLI CD Tools Pull down Menu Save As Selling Select Setting Pin Locations Pin Attributes Interfaces EDIF reader settings EDIF writer EDIF writer settings Assign Pull down Menu Verlag writer VHDL writer Interfaces Pull down Menu IspEXPERT Compiler User Manual 310 Menu and Icon Reference ees Window Help Compiler Log Using Help Compiler Report Index Fini Layout Menu Commands Clock Frequency T able Setup and Hold T able ca Table Tpd Table Software Introduction Manuals Manual Settings Selected Paths Timing M atris Timing Reports Error Messages License Agreement WHOL Netlist Venlog Metlist EDIF Netlist About ispESFERT Compiler Help Pull down Menu Explore Matris Explore Display Criteria JEDEL Results Pull down Menu MW nigor Cascade Tile Vertically Tile Horizontally Arrange Icons Split Llose All Window Pull down Menu isoEXPERT Compiler User Manual
312. ual 157 Global Device Options Design Manager Sequence Assign Device Select LowPower Off or On Parameter File Syntax LOWPOWER ON OFF Command Line Syntax N A Using Device Open drain The OPENDRAIN device option specifies whether all external output or bidirectional pins will use the device open drain feature Description The OPENDRAIN device option affects output and bidirectional pins The OPENDRAIN device option is supported for ispL Sl 2000V 2000E 5000V and 8000 devices Check the SP Encyclopedia for detailed information about device architecture By default the global OPENDRAIN Device Option is set to OFF The OPENDRAIN local Device Pin Attribute assigns the OPENDRAIN attribute to individual pins it overrides the global OPENDRAIN option Design Manager Sequence Assign gt Pin Attributes gt Open Drain Move pins to the appropriate list Parameter File Syntax OPENDRAIN ON OFF Command Line Syntax NA isoEXPERT Compiler User Manual 158 Global Device Options Using Output Buffer Delays The OUTDELAY device option delays the output buffer by 0 5ns for all output and bidirectional pins for the ispL Sl 5000V device family Description Used with the local OUTDELAY pin attribute this feature enables staggering of output buffers to help minimize noise on the device See Using Output Buffer Delays on page 71 The OUTDELAY local Pin Attribute assigns the OUTDELAY attribute to individual pins
313. ut DIX l Panoutk Ss GAR ANR tip D2 10202 Output DAX 1 Fanout s COL Eo Input D3 IO20 Output D3X 1 Fanout s GALHO L d Input EN L02 Output ENX isoEXPERT Compiler User Manual 229 3 Fanout s gib0Z 1 Input ED 1027 Output LDX 3 Fa out s GLDOZ Tnput 825 TOLL Output PSX 3 Fanoutis GIHULL HL Output G0 XL Input glb00 00 O0 QIO Qutput OL ILI Inout 91P035 01 OL Ori Outpur OZ 1016 Input 191603 00 O2 QI2 output Qo 100 Input a160 L00 Q3 QI3 Clock Assignments Net Name CLKX 6 gibUD T2Z gin 12 0 glb01 I0 glb03 I15 11 glb01 I11 glb03 14 QIQ QI1 QI2 y Os Clock Assignment External CLKO isoEXPERT Compiler User Manual Compilation Report 230 Compilation Report Summary Statistics The Summary Statistics section of the Post Route Implementation report consists of three tables GLB and GLB Output Statistics Maximum Level Trace and Pin Assignments GLB and GLB Output Statistics Table The GLB and GLB Output Statistics table contains the following information m Name Location and Output Names for each GLB m Input Output and PT Statistics for each GLB m Inputs Fan outs PTs and Levels for each GLB output The following is an example of the GLB and GLB Output table from the Post Route Implementation Report GLB and GLB Output Statistics GLB Name Location GLB Statistics GLB Output Statistics GLB Output Name TARS QubES EIS ins
314. vices m The SNP Design Attribute specifies the Start of a No Minimize Path Each SNP attribute must have an associated ENP attribute with the same path name m The ENP Design Attribute specifies the End of a No Minimize Path and does not require a matching SNP attribute Synopsis SNET IDatHhl p wesp PACAN ENFPI IDparthl Pathy sue path Description The compiler does not optimize the logic on a No Minimize Path However similar gates may be merged and inactive or parallel logic may be removed or a wide input logic gate may be split during the mapping process Any buffer on a No Minimize Path is implemented in one GLB level Exercise caution when specifying No Minimize Paths through library macros with embedded buffers such as input and output buffering macros Any inverting buffer on a No Minimize Path is merged with the driving or driven logic when appropriate If SNP and ENP relating to the same path are applied to the same net they are ignored Example Figure 2 21 shows an example of a circuit without SNP ENP attributes assigned The implementation of this logic is displayed in Figure 2 22 which can potentially exhibit a glitch at the output node OUT OUT is implementing a latch function EN Figure 2 21 Circuit Not Using SNP ENP Before Compilation isoEXPERT Compiler User Manual 56 Path Attributes Figure 2 22 Circuit Not Using SNP ENP After Compilation Figure 2 23 is the same circuit with SNP and ENP a
315. wer Path attributes restrict routing and can decrease resource utilization Remove unnecessary SLP ELP attributes to improve routing and resource utilization PROTECT The PROTECT attribute restricts optimization of your design Remove unnecessary PROTECT attributes to increase resource utilization GROUP The GROUP attribute restricts optimization of your design Remove unnecessary GROUP attributes to increase resource utilization MAX GLB IN Remove unnecessary CLK properties to improve resource utilization In general limiting the usable GLB inputs and or MAX GLB OUT outputs increases routability at the expense of resource utilization isoEXPERT Compiler User Manual 272 Improving Routability Table A 1 Design Attributes and Compiler Control Options Continued Design Attribute or Compiler Control How to Improve Routability and Option Device Resource Utilization ISP The ISP option requires four I O pins Use ISP OFF to improve resource utilization and routability ISP EXCEPT Y2 This option allows the Y2 pin to be used as a clock input and can increase clock resource utilization Y1 AS RESET This option uses the Y1 pin as a reset input and decreases the available clock resources OPTIMIZE Use OPTIMIZE OFF default to select hard macros which are optimized for speed or resource utilization Hard macros require less time to compile Use OPTIMIZE ON to select soft macros which may provide better routing for some
316. window or Design Navigator the Compute Observability menu item displays The purpose of this menu item is to show the observable nodes from the ispANALYZER in the Physical Viewer When you click on an observable node a Connectivity Window displays in ispANALYZER mode The paths between the GLB output pin and the IOCs displays The assigned observable path displays as a solid line and other observable paths display as dotted lines Refer to Figure 6 11 for an example of the Connectivity window and an explanation of how to change the assigned path When you compute observability the ispEXPERT Compiler goes to the ISDANALYZER mode Timing Information You can obtain timing information from anywhere in the Design Navigator or a Connectivity window The timing information displays in either a Timing Matrix Table or a Clock Frequency Table The Timing Viewer command cascades to different options depending on where the cursor is when the command is selected When you click on a GLB a macrocell an IOG or a Dedicated Control Input pin the following commands may be available m Source Tag Identifies and displays in the Timing Matrix Table the longest and shortest delay from the selected signal to each possible destination If the selected signal is a primary output no timing information is available m Destination Tag Identifies and displays in the Timing Matrix Table the longest and shortest delay from each possible source to the selected s
317. with TIMING FILE to replace the timing 1 default file name with a different file name Design Manager Sequence Tools Compiler Settings Click Interfaces Select all desired Output Formats To specify a Viewlogic EDIF file using the Design Manager select Interfaces EDIF writer settings Specify Viewlogic for the Vendor and enter the name of the timing file Parameter File Syntax OUTPUT FORM EDIF LMC VERILOG VHDL VIEWLOGIC The OUTPUT FORM option can specify several output netlist formats by specifying the formats on the same line separated by commas For example OUTPUT FORM EDIE Me isoEXPERT Compiler User Manual 142 Compiler Control Options Command Line Syntax O Format To specify multiple output formats you must repeat this statement For example 0 EDIE E VEDL Specifying a Viewlogic Timing File Name When you compile your design you can direct ispEXPERT to generate a Viewlogic timing simulation wir file timing 1 anda design edo file with the OUTPUT FORM option Description The TIMING_FILE option allows you to replace the default name timing 1 witha different file name You can save several different versions of the wir file using different TIMING_ FILE file names and simulate the wir files at a later time with a Viewlogic simulator In a Viewlogic design environment the design sim file is placed in your current working directory and the timing file is placed in your wir directory The Viewlogic
318. with the capability to design in familiar CAE environments These third party CAE tools offer schematic capture hardware description language such as VHDL Verilog ABEL HDL as well as functional and timing simulators for design verification Once design entry is completed in the CAE environment the EDIF or PLA netlist file type can be imported into ispEXPERT Running ispEXPERT When you start iSpEXPERT the ispEXPERT Design Manager Figure 1 2 appears Remember ispEXPERT is not a design entry tool The ispEXPERT software provides design compilation synthesis partitioning placement and routing functions Figure 1 2 ispEXPERT Design Manager Window with an Open Project You must create or open a project to begin working Only basic menus are available until you open or create a project Once you do all the menu options display You can also invoke the ispEXPERT Compiler using the Lattice Semiconductor Design Process Manager DPM from the command line of your UNIX system or in a Windows MS DOS window You cannot mix command line invocation with the Design iln ind The ispEXPERT Design Manager is described in Chapter 3 The Design Manager The DPM commands are described in Chapter 4 Design Compilation Options isoEXPERT Compiler User Manual 17 isoEXPERT Functions ISDEXPERT Functions During the compilation process ispEXPERT automatically performs the following functions Analyzes the d
319. you can enter a string of characters that will filter the unassigned pins list e Free Pins Includes Input Output Bidirectional and All buttons The ISpEXPERT software will fit place and route your design more successfully if you free all the pins before you compile e Unassigned Pins Shows all the currently unassigned pins e Assigned Pins Shows all the currently assigned pins When you highlight an assigned pin the pin in the package view is also highlighted e Import Pin Assignment Group Includes the Compiler Result and Pin File buttons For detailed information on these two options see Changing the Pin Assignment on page 111 and Importing a Pin File on page 112 e Save Pin Assignments Saves the current pin assignment to a text file For information on how to use a text file see Using a Text File on page 121 e Package View Shows a convenient diagram of your device with system pins assigned to GND VCC clock etc Use the Zoom icons to adjust your package view or select the View Zoom menu item to zoom to the preset percentages If you want to change the color or shape that the pins appear in your package view select Edit Options System pins are shown in gray and reserved pins are shown in black these colors cannot be changed For complete instructions on how to set the pin colors and shapes check Changing the Pin Color and Shape and Message Color on page 125 Filter the lists by typing
320. you to set a personal user electronic signature UES in the JEDEC file and program it onto the device To set a personal UES 1 Select Assign UES from the Design Manager The UES dialog box appears Figure 3 20 2 Select Hex Binary or ASCII from the Data Type radio buttons Refer to the ISP Daisy Chain Download User Manual for details on data types 3 Type in a personal signature in the Signature field The Maximum Signature Size field displays the maximum number of characters for a signature of the selected data type and the Signature field accepts up to that number of characters The number of characters varies depending on the data type and the device 4 Click OK Data Type C Binary C ASCII Maximum Signature Size 10 Signature cancel Figure 3 20 UES Dialog Box When you download your design onto a device it will contain the UES isoEXPERT Compiler User Manual 106 Compiling Your Design Compiling Your Design After you examine the Explore matrix you can set the Compiler Control Options and Device Options you need to use to compile your design When you run ispEXPERT and compile your design the compiler places and routes the logic It honors the pin assignments included in your pin source file or assignments that you made using the Design Manager during your pin locking sessions if possible Remember once you begin using the Design Manager it takes precedence over all other design sources so any c

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