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1. Figure 25 Vivado Block Design View logiREF ZGPU ZC702 Project To access logicBRICKS IP cores user s manuals double click on the specific IP core s to open the GUI and click on the Documentation icon to open the document logicBRICKS Users Manuals contains all necessary information about the IP cores features architecture registers modes of operation etc Copyright Xylon d o o 2015 All Rights Reserved Page 29 of 41 m logiREF ZGPU ZC702 GPU Meres Reference Design Designed by XYLON User s Manual April 8 2015 Version v2 02 a 6 VIDEO OUTPUT CLOCKING Xylon s standard logiCVC ML Compact Multilayer Video Controller IP core supports display resolutions up to 2048 x 2048 For information about support for higher display resolutions please contact Xylon at info logicbricks com The logiREF ZGPU ZC702 reference design demonstrates the logiCVC ML IP core implemented in Zynq 7000 AP SoC programmable logic The logiCVC ML display controller drives inputs into an Analog Devices ADV7511 HDMI Transmitter which is configured to display the 1080p60 resolution 1920x1080 16 bit YCbCr 4 2 2 image on a regular PC monitor The ADV7511 HDMI Transmitter driver is integrated with the Xylon Framebuffer driver for the Linux OS ADV7511 HDMI Transmitter initialization is also provided for the bare metal applications see the softwareNSDK workspace zc702 board init application Xylo
2. 25920 kB logiCVC layer 3 768MB 32400 kB logiCVC layer 1 768MB 58320 kB logiCVC layer 0 768MB 84240 kB 1 GB Figure 24 logiREF ZGPU ZC702 Memory Layout MB pixels HxV pixels logiCVC 768 1023 2048 up to 1920x1080 logiBITBLT 0 1023 2048 Po logi3D 768 1023 2048 Po e y Table 2 logicBRICKS IP Cores Memory Addressing Copyright Xylon d o o 2015 All Rights Reserved Page 28 of 41 m logiREF ZGPU ZC702 GPU Meres Reference Design Designed by XYLON User s Manual April 8 2015 Version v2 02 a 5 3 Restoring Zynq 7000 Design from Xylon Deliverables Xylon provides all necessary design files and TCL scripts to enable full Vivado Design Suite 2014 4 project restore Full guidelines can be found in the vivado 2d3d hdmi create project html file The vivado 2d3d hdmi xpr file from your installation folder is the Vivado Design Suite project file that opens the project Open this file with the Vivado and explore the design Figure 25 In order to re implement or change the provided reference design please go to Xylon s web site www logicbricks com and acquire evaluation licenses for the logicBRICKS IP cores see chapter 4 GETTING LOGICBRICKS EVALUATION LICENSES logiREF ZGPU ZC702 aH PR w zZ Re e Tris Designed by XYLON s eeoqa
3. LU d E 2i he T ex It gt mmo a B LPLELLITTA mig bd 1m m i L gea d I Eu E i wi UM LLEGEEEE TI t I Fi B ur basd L ALEA y i st LET EN IE E i d ne Ve F ow r r n P us e 3 J L Wikaow as tys Joto SE Jt d Lr E ti s 2 v Uwe ee Mls A y EP CHI WP T 2413 it Si I e lt LI Bare TIDA a v ia soe qm a uc eure sAtrnus For full explanation of the ZC702 s features and settings please check the documentation Xilinx 7 3 Running Precompiled Demos from the SD Card Image To quickly start precompiled Linux demos make sure that you have the SD card with the precompiled image plugged in the board s slot and all jumpers setup as described in the previous paragraph To control the precompiled demos you can use four user push buttons positioned in the central part of the ZC702 board presuming the board s orientation from the Figure 30 use up and down buttons for iterations through examples left button for starting and right button for exiting the example the keyboard connected to the micro USB port O Copyright Xylon d o o 2015 All Rights Reserved in graphical menu use up and down arrows for iteration over examples enter key for starting selected example Q letter key for exiting the example in console outside of the graphical menu use the whole keyboa
4. amp Duff compositing operations between different graphics objects For 3D graphic acceleration there is the logi3D Scalable 3D Graphics Accelerator IP core designed to support the OpenGL ES 1 1 API a royalty free cross platform API for full function 2D and 3D graphics on embedded systems including consoles phones appliances and vehicles The memory subsystem is an essential part of any graphics based system It must ensure enough storage space for GUI elements and application code and a fast interface to assure enough memory bandwidth for a flicker free display output The ZC702 board includes four 8 bit DDR3 memories connected as one 1GB 32 bit memory module The memory is connected to the hard memory controller in the Zynq 7000 AP SoC Processor Subsystem PS 5 1 Design Customization The provided reference design can be customized in different ways Please note that any changes in the provided reference design require evaluation IP licenses for logicBRICKS IP cores The licensing process is described in the chapter 4 GETTING LOGICBRICKS EVALUATION LICENSES Possible design changes include Change logicBRICKS IP settings i e change number of graphics layers controlled by the logiCVC ML display controller IP core Remove some logicBRICKS IP cores i e remove all graphics accelerators and use only the logiCVC ML display controller IP core or remove the 3D acceleration and work with the 2D graphics only etc Add more in
5. Pixel layer or Color Lookup Table CLUT alpha blending mode can be independently set for each layer Packed pixel layer memory organization o RGB 8bpp 8bpp using CLUT 16bpp Hi color RGB 565 and True color 24bpp o YCbCr 16bpp 4 2 2 and 24bpp 4 4 4 Configurable CoreConnect PLBv4 6 Xylon XMB or ARM AMBA AXI4 memory interface data width 32 64 or 128 Programmable layer memory base address and stride oimple programming due to small number of control registers Support for multiple output formats Parallel display data bus RGB 12x2 bit 15 bit 16 bit 18 bit or 24 bit YCbCr 4 4 4 or 4 2 2 output format Digital Video ITU 656 PAL and NTSC LVDS output format 3 or 4 data pairs plus clock Camera link output format 4 data pairs plus clock DVI output format Supports synchronization to external parallel input Versatile and programmable sync signals timing Double triple buffering enables flicker free reproduction Display power on sequencing control signals Parametrical VHDL design that allows tuning of slice consumption and features set Copyright Xylon d o o 2015 All Rights Reserved Page 11 of 41 m logiREF ZGPU ZC702 GPU Meres Reference Design Designed by XYLON User s Manual April 8 2015 Version v2 02 a Available for Xilinx Vivado Design Suite and ISE XPS implementation tools More info http www logicbricks com Products logiCVC ML aspx Datasheet htto www logicbricks com Documentation Datasheets I
6. last year you cannot obtain evaluation license automatically In that case please fill form with request for additional evaluation license Subject Llegicvc ML IP Core Ev aluation Li ense IP Core logiC CA ML EVAL 1M Message Text FE woul ld li use your core with the ZedBoazd de opment kit Figure 18 Step 1 Licensing logicBRICKS Evaluation IP Cores Step 3 Evaluation logicBRICKS IP licenses are tied to your Ethernet MAC address or Sun Host ID Figure 19 and can be used on a single working station only Fill in this address and click on the Request License Key button You should get the confirmation message Figure 20 If you do not get the confirmation message please contact Xylon technical support support logicbricks com Copyright Xylon d o o 2015 All Rights Reserved Page 23 of 41 m logiREF ZGPU ZC702 GPU Meres Reference Design Xulon Designed by XYLOR User s Manual April 8 2015 Version v2 02 a Home Aboutus Products Markets Solutions logicBRICKS Downloads Documentation News amp E My logicBRICKS z or T xcd Obtain Evaluation License Change Password Xylon logicBRICKS A Graphics for Xilinx Zynq 7000 VALLES f Click to get reference designs for Xilinx ZC702 Evaluation Board AN Request Eval IP Core IP Core Activation Create Case Subscribe to Newsletter Downloads MAC Address You will be able to use evaluation license on one d
7. reference designs Unregistered users will be re directed to the User Login page The download link is automatically sent by an e mail which means that the registration process requires an access to the e mail account Xylon reference logicBRICKS designs can be downloaded as cross platform Java JAR self extracting installers 3 1 Registration Process Registration is very quick and simple If you experience any trouble during the registration process please contact Xylon Technical Support Service support logicbricks com Copyright Xylon d o o 2015 All Rights Reserved Page 15 of 41 m logiREF ZGPU ZC702 GPU Meres Reference Design Designed by XYLON User s Manual E April 8 2015 Version v2 02 a English Home L og In About us Products Markets e Step 1 logicBRICKS Downloads Documentation News amp Events ee If you are the registered logicBRICKS user please type in your Username and Password Unregistered users should click T SS on the Register button which will open the registration form About Aw D Xylon logicBRICKS Graphics for Xilinx Zynq Sy Click to gat reference designs for Xilinx 20702 Evatuation d Step 2 Unregistered users should fill in the w MCN registration form from the Figure 6 Please id aut take care on required form s fields Your o s Username is an actual e mail account used for communication with Xylon logicBRICKS E Xylon ac
8. the logiREF ZGPU ZC702 reference design Design clocking structures are not shown Please read the chapter 6 VIDEO OUTPUT CLOCKING and explore the design files to understand the clocking structure Graphics features like bitmaps operations alpha blending overlays rotations scaling LCD display control 3D rendering etc are supported by three separated logicBRICKS IP cores The logiCVC ML Compact Multilayer Video Controller IP core is an advanced display graphics controller for LCD and CRT displays which enables an easy video and graphics integration into embedded systems based on Xilinx programmable technology Though its main function is to provide flexible display control it also includes a level of hardware acceleration alpha blending panning buffering of multiple frames etc The logiCVC ML IP core can directly drive a common PC monitor Copyright Xylon d o o 2015 All Rights Reserved Page 25 of 41 m logiREF ZGPU ZC702 GPU TE BRIS Reference Design Designed by XYLON User s Manual April 8 2015 Version v2 02 a through the ADV7511 High Definition Multimedia Interface HDMI transmitter available on the ZC702 board The logiREF ZGPU ZC702 GPU reference design includes the 2D graphics accelerator that off loads the ARM dual core Cortex A9 Core processing system and increases graphics performance The logiBITBLT IP core supports fast copying moving up and down scaling image flipping alpha blending and Porter
9. will get an e mail with the download link for the selected reference design installation http www logicbricks com logicBRICKS Ref erence logicBRICKS Design Xylon Heference Designs Navigation Page aspx Figure 9 Registration Process Step 5 3 2 Installation Process Installation process is quick and easy Each logicBRICKS reference design can be downloaded as a cross platform Java JAR self extracting installer Please make sure that you have a copy of the JRE Java Runtime Environment version 6 or higher on your system to run Java applications and applets Double click on the installers icon to run the self installing executable to unpack and install the reference design on your PC At the beginning you will be requested to accept the reference design evaluation license Figure 10 For installation in Linux OS please follow instructions http www logicbricks com logicBRICKS Reference logicBRICKS Design Xylon Reference Designs Linux Installation aspx If you agree with the conditions from the evaluation license click NEXT and select the installation path for your logicBRICKS reference design Figure 11 The installation process takes several minutes It generates the directory structure described in the paragraph 3 3 Directory Structure Copyright Xylon d o o 2015 All Rights Reserved Page 17 of 41 m logiREF ZGPU ZC702 GPU Meres Reference Design Designed by XYLON User s Manual April 8 2015 TH Xy
10. 1 License On and subject to the nass a nonexcluai ma cf this Agree t Xylan h by grants Lx non trans nosna sublicenrsable personal revocable and roy a license to evaluate the SoC and FPGA IP cores softvere drevers software programs materials date and documentation identified in fibt A collectively the Licensed Materials solely for the purpose of e sting the Licensed Materials for use wth Xilinx SoC and FPGA device s and solely wthin Licensee s premises Licensee may install and use the Ucensed Materials at one 1 development seat at only one Licensee s site Use of the Licensed Materials for any other purpose or by any third party other than Licenzee is prohibited 2 Ownership The Licensed Materials are licensed not sold Except for the limited license granted in Section 1 above Licensee acknowledges that all intellectual property rights in and to the Licensed Materials and all copies thereof are and wil remain the sole property of Xylon or its supphers and that no additional rights are granted or conferred by implication estoppel or otherwise The Licensed Materials are protected by laws and nternabonal treaty provisions covering intellectual property and industrial rights 3 Restrictions Licensee shall not decrypt decompile reverse engineer disassemble or otherwise reduce to a home perceivable form the Licensed Materials delivered in non human dable form Licensee shall not hy
11. 15 All Rights Reserved Page 6 of 41 lodiREF ZGPU ZC702 GPU TE BRIS 9 Designed by XYLON User s Manual Reference Design Sulon April 8 2015 Version v2 02 a 1 2 1 1 2 2 Quick Evaluation with no HW and or SW Changes Download and install the logiREF ZGPU ZC702 reference design chapter 3 GET AND INSTALL THE REFERENCE DESIGN Setup the demo hardware and use the provided SD card image to run precompiled demo applications paragraph 7 2 Set Up the ZC702 for Use with Precompiled Linux Demos from the SD Card Develop Standalone and Linux Software no HW Changes Download and install the logiREF ZGPU ZC702 reference design chapter 3 GET AND INSTALL THE REFERENCE DESIGN setup the demo hardware paragraph 7 2 Set Up the ZC702 for Use with Precompiled Linux Demos from the SD Card Use the provided Zynq 7000 AP SoC as it is binaries Follow instructions for working with logicBRICKS standalone bare metal or Linux drivers please get the full instructions in the start html file from your installation root directory Develop software applications prior to the availability of the actual target system Full GPU Customization HW and SW Changes Download and install the logiREF ZGPU ZC702 reference design chapter 3 GET AND INSTALL THE REFERENCE DESIGN oetup the demo hardware paragraph 7 2 Set Up the ZC702 for Use with Precompiled Linux Demos from the SD Card Obtain logicBRICKS evaluation licenses from Xylon chapter 4
12. 32 formatted SD card setup the ZC702 Figure 30 plug in the SD card with precompiled demos and run Note there should be no linux sd directory on the SD card but only the contents of that directory The precompiled Linux graphics demo applications can be launched and controlled by on board push buttons or mouse and keyboard combination Qt graphics demos require use of the mouse to interact with the application and cannot be fully controlled by the push buttons oet up your ZC702 board as shown on the Figure 30 Table 4 Figure 29 set the jumpers Figure 29 insert the SD card in the J64 slot Rev 1 1 connect the power supply video cable HDMI and optional control devices serial cable to the USB UART or Ethernet cable optionally connect mouse and keyboard to the USB OTG Copyright Xylon d o o 2015 All Rights Reserved Page 34 of 41 m logiREF ZGPU ZC702 GPU Merks Reference Design Designed by XYLON User s Manual April 8 2015 Version v2 02 a Jumpers settings for the SD boot mode Board Rev B Jumper Setting Board Rev 1 1 Table 4 Jumpers Set Up for Booting from the SD Card el e2 e3 e4e 5 Ej E CTS 206 125 2213 Figure 29 ZC702 The Required Jumpers Setting Copyright Xylon d o o 2015 All Rights Reserved Page 35 of 41 BRICKS Designed by XYLON April 8 2015 logiREF ZGPU ZC702 GPU Reference Design User s Manual Sulon 8 Version v2 02 a ere k
13. A plugin general information and building instructions Xylon 3D graphics acceleration library binaries instructions for building 3D applications code examples Running Linux applications with the ZC702 board setup for the precompiled SD card image Copyright Xylon d o o 2015 All Rights Reserved Page 40 of 41 Reference Design Xulon Designed by XYLON User s Manual y April 8 2015 Version v2 02 a lodiREF ZGPU ZC702 GPU TE BRIS 9 9 REVISION HISTORY Version Date Author Approved by Note S OO June 15 2012 Z SafarZik Z Safarzik Initial October 5 2012 Z Safarzik Z Safarzik Updated chapter G Gali Introduction G Pantar Added chapters Get and Install the Reference Design Getting logicBRICKS Evaluation Licenses Video Output Clocking Quick Start Software Documentation V Durdek V Durdek Updated chapters 2 5 and 6 Added chapters 1 2 6 2 7 6 1 and 7 6 4 D Skugor R Kon urat Changes introduced regarding reference design porting to Vivado User s manual corrections performed 2 01 b Aug 12 2014 Z PleSiv ak R Kon urat Added Graphics Demo Preview chapter Added chapter dealing with read only permissions of the install directory Changed instructions on copying Linux binaries to the SD card Changed instructions on running demo applications Other minor updates and fixes Aug 28 2014 Z Ple amp iv a
14. CKS EVALUATION LICENSES Please note that the logiREF ZGPU ZC702 reference design installation provides you with everything needed to run the provided demo applications or to use change the provided software source code However if you wish to make any changes on the hardware design files such as to remove add or reconfigure some of the provided IP cores you have to obtain evaluation IP licenses from Xylon The following pages describe the procedure for getting and licensing evaluation logicBRICKS IP cores that takes several minutes to complete If you experience any trouble during this process please contact Xylon Technical Support Service support logicbricks com You must be logged in to the Xylon website using your logicBRICKS user name and password to get an access to evaluation logicBRICKS IP cores Unregistered users will be re directed to the User Login page Paragraph 3 1 Registration Process explains this simple registration procedure Step 1 Logged In users get the My logicBRICKS tab in the main www logicbricks com navigation menu Click on it and you will be directed to your main web page for communication with Xylon logicBRICKS Figure 15 Please select the Request Eval IP Core tab in the left menu Home Aboutus Products Markets Solutions logicBRICKS Downloads Documentation News amp Evei My logicBRICK S Ti My logicBRICKS Change Password eet MC Test our state of the art IP Core Activa
15. GETTING LOGICBRICKS EVALUATION LICENSES Use the provided Zynq 7000 AP SoC to add or remove more logicBRICKS IP cores and or third party IP cores or to change logicBRICKS IP settings through the GUI Implement new Zynq 7000 AP SoC design Develop software by following instructions listed in the start html file from your installation root directory 1 3 Xilinx Development Software The logiREF ZGPU ZC702 reference design and Xylon logicBRICKS IP cores are fully compatible with Vivado Design Suite 2014 4 Future design releases shall be synchronized with the newest Xilinx development tools Licensed users of the Xilinx tools can use their existing software installation for the logiREF ZGPU ZC702 evaluation Copyright Xylon d o o 2015 All Rights Reserved Page of 41 m logiREF ZGPU ZC702 GPU TE anes Reference Design Designed by XYLON User s Manual April 8 2015 Version v2 02 a 1 4 Graphics Demo Preview Please check Xylon s Video Gallery web pages http www logicbricks com logicBRICKS IP Library Video Galleries logicBRICKS Demos Xilinx ZC702 Video Clip aspx to preview the graphics demo applications provided with the logiREF ZGPU ZC702 installation for your ZC702 development kit Figure 2 Screenshots from Some Demos Provided with the Reference Design Copyright Xylon d o o 2015 All Rights Reserved Page 8 of 41 m logiREF ZGPU ZC702 GPU TERNOS Reference Design Designed by XYLON User s Manual A
16. LUTIONS ccceceeseeseeceeeeceeseeseeseeeueeeeeeseeses 32 TC irae E I 34 7 1 REOUIRED HARDWARE srasiaidenncsttuaumsieidanousotosmmuunadacostidandnsinednco saison tule eidanoieeraaneutiidaaeisadandusuneanse 34 7 2 SET UP THE ZC 702 FOR USE WITH PRECOMPILED LINUX DEMOS FROM THE SD CARD 34 7 3 RUNNING PRECOMPILED DEMOS FROM THE SD CARD IMAGE cccccceceeseceeseeeuseeeevaeeueeesaeeass 36 Ted WOOL OO SIN RR e E 37 Jac RUNNING SbD IDOIOJDDSteatebiacieruttive tuia AAE dit re een a ee 38 rS RNAn OI DEMO ADDO ERR A Am 38 7 4 CHANGE THE DEMO APPLICATIONS OR DESIGN NEW APPLICATIONS FROM SCRATCH 38 7 4 1 Xilinx Development Software cccccccccseececececeeeeeseeeeseeeeeseeeeseueesseeeeseueesseeeseeeessaeeesaes 38 7 4 2 Set Up Linux System Software Development Tools eeeeeeeeeeeesesesees 38 ras dE ig 8 086 ial TOO OE eee m 39 8 SOFTWARE DOCUMENTATION u ccccccecceccecceceeceecescesceeeeeeeseseeseuseuseuseeeeseuseuseuseueeseeseuseuseuees 40 Copyright Xylon d o o 2015 All Rights Reserved Page 3 of 41 m logiREF ZGPU ZC702 GPU TE BRIS Reference Design Sulon Designed by XYLON User s Manual April 8 2015 Version v2 02 a 8 1 SOFTWARE INSTRUCTIONS STANDALONE SOFTWARE ccececececcececececccccccececececacsceseaeavarecs 40 8 2 SOF
17. P logiCVC ML_hds pdf 2 3 2 logiBITBLT Bit Block Transfer 2D Graphics Accelerator This 2D graphics accelerator speeds up the most common GUI operations and off loads the processor The logiBITBLT transfers graphics objects from one to another part of system s on screen or off screen video memory and performs different operations during transfers such as ROP 2 raster operations bitmap scaling stretching and flipping Porter amp Duff compositing rules or transparency Supports Xilinx Zynq 7000 AP SoC and all Xilinx FPGA families Available SW drivers for Linux and Microsoft Windows Embedded Compact OS Supports move operations in positive and negative direction Supports 16 different ROP2 operations Integrated bitmap flipping and optional up down scaling Porter Duff composition with without global alpha Color keyed transparency source and destination Anti aliased 8 bit font expansion Pattern fill with 8x8 pixels patterns oolid fill with any of the supported color formats Supported color formats RGB8 ARGB8 RGB16 ARGB16 RGB24 and ARGB24 Control of pixel alpha blending factors ARM AMBA AXI4 and AXIA4 Lite bus compliant Memory layout configurable for big or little endianness Available for Xilinx Vivado Design Suite and ISE XPS implementation tools More info http www logicbricks com Products logiBI TBLT aspx Datasheet http www logicbricks com Documentation Datasheets IP logiBITBLT hds pdf 2 3 3 logi3D Scalable 3D G
18. S O1 X2 E BLENDER CONVERTER LVDS CLK LVDS CLKN peace ACCE ITU_CLK_IN PLLVCLK_LOCKED CONTROL INTERRUPT LVDS Camera link PARALLEL ITU656 DVI T EL Figure 26 logiCVC ML Architecture 6 2 Utility Clock Module Alongside graphics logicBRICKS IP cores Xylon has included a small utility clock module the logiCLK Programmable Clock Generator IP core to enable users to easily change display resolutions from the logiREF ZGPU ZC702 reference design Figure 27 Copyright Xylon d o o 2015 All Rights Reserved Page 31 of 41 m logiREF ZGPU ZC702 GPU TE BRIS Reference Design Designed by XYLON User s Manual April 8 2015 Version v2 02 a p gt RST OUT Bp LOCKED OSC CLK Bw CLKO PLLE2 BASE p gt CLK1 Bw CLK2 SPLB AXM Lite p gt CLK3 LL REGISTERS ibo B CLK5 p gt CLKO_DRP p gt CLK1 DRP DRP a INTERFACE B CLK2 DRP CLK DRP PLLE2 ADV gt CLK3 DRP p gt CLK4_DRP RST_N p gt CLK5_DRP DRP MODULE Figure 27 logiCLK Architecture The logiCLK clock generator IP core is designed to provide frequency synthesis clock network de skew and jitter reduction It has twelve independent fully configurable clock outputs Six clock outputs are dynamically reconfigurable by mean of the Dynamic Reconfiguration Port DRP The DRP gives the system designer access to the configuration and status registers of the PLL and behaves like a set of memory mapp
19. TWARE INSTRUCTIONS LINUX SOFTWARE ccececececcccececececccccccececeaeacsceteceauacseeneaeavanecs 40 9 REVISION HISTORY casio cece cee eects otto wee noe cane eon ennen donna eecececetenecesevesues 41 Copyright Xylon d o o 2015 All Rights Reserved Page 4 of 41 m logiREF ZGPU ZC702 GPU Meres Reference Design Designed by XYLON User s Manual April 8 2015 Version v2 02 a 1 INTRODUCTION Xylon s logicBRICKS library of IP cores optimized for Xilinx All Programmable devices includes several graphics logicBRICKS IP cores for full range implementation of 2D and 3D Graphics Processing Units GPU on Xilinx Zynq 7000 All Programmable SoC and FPGAs This user s manual describes Xylon s logiREF ZGPU ZC702 2D and 3D GPU reference design for Xilinx ZC702 Evaluation Kit This free and pre verified logicBRICKS reference design includes evaluation logicBRICKS IP cores and hardware design files prepared for Xilinx Vivado Design Suite It also includes the complete Linux OS image software drivers demo applications and documentation The offered evaluation hardware design is customizable logicBRICKS IP cores can be setup through Vivado IP Integrator IPI to support only required graphics features required by the application from small and efficient display control that uses just a fraction of programmable logic in the smallest Z 7010 Zynq 7000 AP SoC device up to the full 3D accelerated graphics engine The provided software drivers an
20. as parts of the Xylon reference designs http www logicbricks com logicBRICKS Reference logicBRICKS Design aspx Copyright Xylon d o o 2015 All Rights Reserved Page 10 of 41 lodiREF ZGPU ZC702 GPU TE BRIS 9 Designed by XYLON User s Manual Reference Design Sulon April 8 2015 Version v2 02 a opecific IP cores can be downloaded from Xylon s web shop http www logicbricks com Products IP Cores aspx 2 3 logicBRICKS IP Cores Used in This Design 2 3 1 logiCVC ML Compact Multilayer Video Controller The logiCVC ML IP core is an advanced display graphics controller for LCD and CRT displays which enables an easy video and graphics integration into embedded systems with Xilinx Zynq 7000 All Programmable SoC and FPGAs This IP core is the cornerstone of all 2D and 3D GPUs Though its main function is to provide flexible display control it also includes hardware acceleration functions three types of alpha blending panning buffering of multiple frames etc Supports all Xilinx FPGA families Supports LCD and CRT displays easily tailored for special display types 64x1 to 2048x2048 display resolutions Available SW drivers for Linux Android QNX and Microsoft Windows Embedded Compact OS Support for higher display resolutions available on request Supports up to 5 layers the last one configurable as a background layer Configurable layers size position and offset Alpha blending and Color keyed transparency
21. button Up arrow key south button Up arrow key West button Enter key East button Q letter key Following demos are available ISM HMI examples HMI demo 3D graphic examples Photo album Avio demo City flying City navigation Rotating portrait Cluster demo Menu Simple demo T graphic examples Dynamic scene Color animation Snake Same gane Weather anchor layout Qtperf Figure 31 logiREF ZGPU ZC702 Boot Up Graphics Menu Copyright Xylon d o o 2015 All Rights Reserved Page 3 of 41 m logiREF ZGPU ZC702 GPU TE BRIS Reference Design Designed by XYLON User s Manual April 8 2015 Version v2 02 a 7 3 2 Running 3D Demo Apps In the screen console type in mnt 3dDemo elf a mnt 3dDemo elf b mnt 3dDemo elf c mnt 3dDemo elf f starts Photo album demo Starts Avionics demo Starts City flying demo Starts Auto Instrument Cluster demo H SE He od These commands start the demo Control demos by keys A or D left right E select and Q quit In some demos you can also use keys W X R and F CTRL C key combination stops the demo 7 3 3 Running QT Demo Apps In the screen console type in opt qt examples declarative demos snake snake SABB runs with xylonqpa opt qt examples declarative demos snake snake SAFB runs with linuxfb Note SABB and SAFB are defined in config profile as export ABB platform xylonqpa fb dev fb3 plugin evdevmouse plugin evdevkeyboard export AFB platform
22. cepts only valid company e mail R accounts Step 3 cmm Register ntes SG Lene uL As soon as your registration form gets accepted by Xylon you get a confirmation message Please check your e mail to find a link that activates your logicBRICKS account If you do not get the confirmation message in several minutes please check your Spam Filter or Junk Mail Folder If you have not received the confirmation message please contact Xylon support Documentation News amp Events Figure 7 Registration Process Step 3 Copyright Xylon d o o 2015 All Rights Reserved Page 16 of 41 m logiREF ZGPU ZC702 GPU TY anes Reference Design Sulon Designed by XYLON User s Manual April 8 2015 Version v2 02 a Mies P NE sns Activate Account Graphics and m Video for Xilinx A 2yt 7 nor ip j About us 2D Xylon logicBRICKS Si 7 EIL Products i Graphics for Xilinx Zynq 7000 5 Markets Click to get reference designs for Xilinx 27702 Evaluation Boord Jf s x n Step 4 You have successfully activated your account Documentation News amp Events Click on the logicBRICKS web account activation link in the received e mail and you will get the confirmation status message Please login to proceed Step 5 As soon as you select an appropriate logicBRICKS reference design and installer for your operating system from the Downloads Navigation Page link bellow you
23. change the user permissions for C Program Files xylon directory and all of it s subdirectories right click on the C Program Files xylon directory and select Properties Under Security tab select Edit Select Users group in the list and check Full control checkbox in the Allow column 3 3 Directory Structure The Figure 14 gives a top level view of the directories and files included with the logiREF ZGPU ZC702 reference design for the ZC702 board development kit Table 1 explains the purpose of directories Copyright Xylon d o o 2015 All Rights Reserved Page 19 of 41 m logiREF ZGPU ZC702 GPU T CERRO Reference Design Sulon Designed by XYLON User s Manual April 8 2015 Version v2 02 a m INSTALLATION ROOT doc vivado_2d3d_hdmi hardware software m start html project Linux evaluation licenses pdf drivers logiBITBLT SW files C logiCLK SW Files scripts E C logiCVC SW Files EL m sw_services C fpga readme html xyl_oslib srcs mm logicbricks s B a CJ logiCVC ML IP XACT core create project html NE CJ logiBITBLT IP XACT core js C logi3D IP XACT core logiCLK IP XACT core src makeBin ready_for_download SDK_workspace Figure 14 Directory Structure Copyright Xylon d o o 2015 All Rights Reserved Page 20 of 41 m logiREF ZGPU ZC702 GPU Tanks Reference Design Sulon Designe
24. d by XYLON User s Manual April 8 2015 Version v2 02 a Directory Purpose This directory contains the start html page the jump start navigation page through the reference design Project documentation vivado 2d3d hdmi This directory contains the complete Vivado project and files necessary for regenerating project from TCL scripts data Designconstrintsfiles XDC O Z o project Vivadoprojectrelated directories hardware 00 o Standalone bare metal drivers for logicBRICKS IP cores with documentation and examples cores User s Manuals are stored in doc subdirectories xyl oslib Xylon OS abstraction library for Xilinx Xilkernel embedded kernel use in standalone non OS applications software CO T o a Navigation page through the software files and instructions for building binaries ps Linux kernel Linux kernel and device tree configuration files meine Mow emo gage n HDMI demo logi3D demo makeBin Utility scriptforcreatingbootbinfile ready for download Prepared binaries readyfordownload Xilinx SDK workspace folder for building bare metal applications Table 1 Explanation of Directories in logiREF ZGPU ZC702 Reference Design Copyright Xylon d o o 2015 All Rights Reserved Page 21 of 41 m logiREF ZGPU ZC702 GPU Merks Reference Design Designed by XYLON User s Manual April 8 2015 Version v2 02 a 4 GETTING LOGICBRI
25. d libraries include standard Linux Framebuffer driver Qt application framework and OpenGL ES 1 1 API otandard software drivers enable software developers to work fast and efficiently with popular graphic libraries widget toolkits and familiar development tools Xylon also supplies bare metal software drivers for non OS use Aside from the logicBRICKS software support for the Linux OS Xylon also provides software drivers for other popular operating systems running on the Zynq 7000 AP SoC Android QNX and Microsoft Windows Embedded Compact A number of Xilinx partners who provide BSPs Board oupport Package for different operating systems support Xylon logicBRICKS IP cores for graphics TO learn more about the available software support please visit ort aspx Figure 1 Xilinx ZC702 Development Kit Running 3D Graphics Video clip http www logicbricks com Archive logi3D Zyng ZC 702 aspx Copyright Xylon d o o 2015 All Rights Reserved Page 5 of 41 m logiREF ZGPU ZC702 GPU TE BRIS Reference Design Designed by XYLON User s Manual April 8 2015 Version v2 02 a 1 1 Design Deliverables 1 1 1 Hardware Design Files Configuration bitstream file for the programmable logic and the SDK export of the reference design that allows immediate start and software changes 7ZC702 reference design prepared for the Vivado Design Suite Xylon evaluation logicBRICKS IP cores logiCVC ML Compact Multilayer Vid
26. ed registers One dynamically configurable clock output is connected directly to the logiCVC ML IP core s VCLK input port It means that the VCLK clock frequency can be changed while design is running and consequently the pixel clock PIX CLK dynamically changes When the Xylon Linux Framebuffer driver is configured to use the logiCLK as a pixel clock generator the required pixel clock frequency is automatically adjusted for a particular video resolution through common clock framework connected to logiCLK CCF Linux device driver Desired pixel clock frequency is determined from the video mode and set accordingly To learn more about this IP core please read the datasheet http www logicbricks com Documentation Datasheets IP logiCLK hds pdf 6 3 Linux Framebuffer Changing Display Resolutions Linux Framebuffer is a standard Linux driver that abstracts the graphics hardware and allows application software to access it through a well defined interface Software designers can use it with no need to know anything about the underlying hardware IP cores in the Xilinx Zynq 7000 All Programmable SoC or FPGA device The Linux Framebuffer delivered with the logiREF ZGPU ZC702 reference design is adopted by Xylon to fully support the logiCVC ML display controller IP core Xylon Framebuffer driver is located in the Xilinx Linux Kernel github server The latest Framebuffer driver version is provided in this installation for instructions how to config
27. eeseeeeaes 12 2 3 4 logiCLK Programmable Clock Generator ccccccccecceceeceeseeeeceeeesseeeeseeeesaeeeeseeesaaeeesaes 13 2 4 LOGICBRICKS IP CORES FOR VIDEO PROCESSING cccce I meme memre mener ren nnns 14 3 GET AND INSTALL THE REFERENCE DESIQN eeceeeeeeeee nnne nune u nera n uaa 15 3 1 REGISTRATION PROCESS i nectvtetcaniciecatwatoniewuctannicntedsttineiested asta diodaamclesloskivatisiettakiatentoutudcamicinatadsiatenieasdantidaatedateres 15 3 2 INSTALLATION PROCESS isernia AAE EEAS 17 3 2 1 Filesystem Permissions of the Installed Directory Windows 7 uses 19 3 9 DIRECTORY I d eii cK TTE 19 GETTING LOGICBRICKS EVALUATION LICENSES eeeeeeeee eene nnne nnne nun rnnt 22 LOGIREF ZGPU ZC702 DESIQN 1 eeeeeeeeeeeeeeene ehe nh nnnm hunhenh saa k uana ases a sau asas ase n rau 25 5 1 DESIGN GUSTOMIZATION MR tm 26 5 2 MEMORY LAYOUT eases er eqn ce at tere esis Em 28 5 3 RESTORING ZYNQ 7000 DESIGN FROM XYLON DELIVERABLES c 0ececceceececeececeeceeeeceeeeeeeeess 29 6 VIDEO OUTPUT CLOCKING eis cere aces see ets steers sense canons ee Rasa EE EU 30 6 1 LOGICVC ML STANDARD DISPLAY RESOLUTIONS AND PIXEL CLOCK cccccceseeceseeeeseeeueees 30 6 2 UTILITY CLOCK MODULE cccececcecececcecececcececeusececeusececausecseauseceeausecseausacueaueacseausacseausaneeauss 31 6 3 LINUX FRAMEBUFFER CHANGING DISPLAY RESO
28. eo Controller logiBITBLT Bit Block Transfer 2D Graphics Accelerator logi3D Scalable 3D Graphics Accelerator logiCLK Programmable Clock Generator 1 1 2 Software logicBRICKS standalone bare metal drivers with driver examples Zynq FSBL sources and the Xilinx SDK project custom version for standalone applications Linux Framebuffer driver for the logiCVC ML IP core display controller IP core Qt5 XylonQPA plugin for 2D hardware acceleration logiBITBLT 2D graphics accelerator IP core HMI demo application that uses Qt application framework for GUI capabilities logi3D example sources and binaries OpenGL ES 1 1 library for the logi3D IP core may be provided on request 1 1 3 Binaries Precompiled SD Card image for the fastest demo startup First Stage Bootloader FSBL otandalone logiCVC ML and logiBITBLT examples Linux binaries Uboot devicetree dtb root file system uramdisk ulmage kernel with the Framebuffer driver for the logiCVC ML IP core OpenGL ES 1 1 simple example and Xylon 3D demo 1 2 Usage Modes The logiREF ZGPU ZC702 reference design can be used in different ways which are listed in this paragraph and thoroughly explained throughout this document Delivery is optional Product is based on a published Khronos specification and is expected to pass the Khronos Conformance Testing Process Current conformance status can be found at www khronos org conformance Copyright Xylon d o o 20
29. evelopment workstation Please enter your Sun Host ID workstation MAC address for MS Windows and Linux 00 00 00 00 00 00 platforms or Sun HostlD for Solaris platforms Home About us Products Markets Solutions logicBRICKS Downloads Documentation My logicBRICKS i a a Obtain Evaluation License Change Password Xylon logicBRICKS Request Eval IP Core Graphics for Xilinx Zynq 7000 IP Core Activation Create Case Subscribe to Newsletter Downloads License key will be created and send to your e mail address Figure 20 Step 3 Confirmation Message Step 4 You will get an e mail with the license key file and full instructions for setting up the license key and downloading the logicBRICKS IP core Please follow the provided instructions From Xylon License Key Generator To Cc Subject Xylon Core License Delivery ID 03512090617423596 Sent 6 9 2012 17 47 Attachments 03512090617423596 ip xap 349logicvcml eval flexlm lic 568 B Tipus THIS IS AN AUTOMATICALLY GENERATED EMAIL Please do not reply to this message Designed by XYLON All requests for support should be directed iweb download area This email contains the license s for the core s you requested It enables you tofuse the core s at the level authorized by the License Type indicated in the table at the bottom of this page You can download the evaluation IP core deliv You will need your log
30. ffset 1080 bits per pixel lt 32 gt type rgb transparency layer 5 layer 3 address lt 0x31950000 gt Figure 28 Video Mode Definitions An Excerpt from the Linux Copyright Xylon d o o 2015 All Rights Reserved dts Page 33 of 41 m logiREF ZGPU ZC702 GPU Mares Reference Design Designed by XYLON User s Manual April 8 2015 Version v2 02 a 7 QUICK START 7 1 Required Hardware A full evaluation of the provided reference design requires ZC702 development kit HDMI or HDMI to DVI video cable for 1024x768 capable monitor SD card min 256MB optional a keyboard USB Micro B cable or a control serial link USB UART or Ethernet between PC and the ZC702 board optional USB Micro B cable USB hub mouse and keyboard optional MINI USB cable for debug UART optional Ethernet cable for Telnet connection optional Xilinx JTAG Parallel cable USB for standalone application development The majority of provided demo applications can be controlled by on board push buttons and do not require keyboard and mouse connections The reference design has been tested on the ZC702 Rev 1 1 7 2 Set Up the ZC702 for Use with Precompiled Linux Demos from the SD Card Xylon provides Linux Qt and 3D demo binaries in the software ready for download linux sd directory of the delivery If you want to run the prepared demos copy the contents of the 1inux sd directory to the root directory on the FAT
31. git To get the latest version of Xylon logicBRICKS software drivers for Linux operating system please visit Xylon s git https github com logicbricks Copyright Xylon d o o 2015 All Rights Reserved Page 39 of 41 m logiREF ZGPU ZC702 GPU T CERRO Reference Design Designed by XYLON User s Manual April 8 2015 Version v2 02 a 8 SOFTWARE DOCUMENTATION Please use the start html file which is located in your logiREF ZGPU ZC702 installation directory section 4 Software Documentation or open directly software readme html file to find relevant documentation for using logiREF ZGPU ZC702 software deliverables This file contains links to software documents and instructions related to Standalone bare metal software linux software 8 1 Software Instructions Standalone Software FSBL instructions otandalone software drivers code and documentation and examples Zc 02 board init application HDMI initialization and pixel clock setting Building standalone applications Running standalone applications with the ZC702 board setup for standalone applications 8 2 Software Instructions Linux Software Xylon provides the Linux Framebuffer driver Qt5b XylonQPA plugin Qt HMI example and OpenGL ES 1 1 library driver for Linux Zynq tool chain Linux kernel and file system used for development and demonstrations of Xylon drivers are provisions of Xylon Linux kernel building instructions and dts files Qt5 XylonQP
32. iately start designing The IP s size and feature set can be easily adjusted through IP drag and drop IPI interface The logiCVC ML comes readya to use and with rich set of deliverables including SW driver documentation and an example design Higher resolutions are available on request Currently Xylon offers software drivers for use with Linux Android and Microsoft Windows Embedded Compact operating systems Status Production License Induded Vendor Xylon VLNV logicbricks com logicbricks logicvc 4 1 Repository d users dskugor hp_projects hp069 AL scratchpad hardware logicbricks src Figure 3 logicBRICKS IP Cores Imported into the Vivado IP Catalog Copyright Xylon d o o 2015 All Rights Reserved Page 9 of 41 m logiREF ZGPU ZC702 GPU T CERRO Reference Design Designed by XYLON User s Manual April 8 2015 Version v2 02 a Some of the latest logicBRICKS IP cores are provided in the Vivado compatible version only Please visit our web site or contact Xylon to learn more about the tools compatibility of the specific logicBRICKS IP core The Figure 3 shows logicBRICKS IP cores imported into Vivado Design Suite while the Figure 4 shows a typical logicBRICKS IP core s configuration GUI n i Re customize IP p 4 cox 2D Graphics Accelerator Bit Block Transfer 5 3 PE Documentation L IP Location Show disabled ports Component Name logibitblt 0 IP core license and version Registers interface Memo
33. in email and password for access to Xylo A full license allows you to use the core in Full Access mode yal jp download link NOTE A full license means that purchased or evaluation IP core can be fully implemented into the Xilinx FPGA The IP core licenses are attached to this e mail 03512090617423596 ip xap 349logicvcml eval flexlm lic NOTE You can alternatively download the license archive by clicking here You must access this downloads evaluation license by September 13 2012 After this date the license archive wil be removed from the website Figure 21 Step 4 E mail with logicBRICKS License and Download Instructions Copyright Xylon d o o 2015 All Rights Reserved Page 24 of 41 T logiREF ZGPU ZC702 GPU Merer Reference Design Designed by XYLON User s Manual April 8 2015 Version v2 02 a 5 LOGIREF ZGPU ZC702 DESIGN Xilinx Zynq 7020 Programmable Logic GigE Flash QSPI SD Card UART SPI CAN 12C Lo a aaa i e gt i 0 Intelligent Processors by ARM Processing System p E AXM Lite logiCVC ML m Video Controller eux AXIA HDMI DVI AXI4 AXI4 DISPLAY AXI4 logi3D logiBITBLT 3D Graphics 2D Graphics Accelerator Accelerator Processing system 7 AXI4 MIXED 3RD PARTY Figure 22 logiREF ZGPU ZC702 Reference FPGA Block Diagram Clock Generator Module and other utility IP cores are not shown The Figure 22 shows the simplified block diagram of
34. k R Kon urat Fixed numbering of images and references to images 2 02 a April 8 2015 D Skugor R Kon urat Changes regarding updated reference design IP core versions and Vivado version Hemoved DirectFB reference Added XylonQPA reference Other minor updates and fixes Copyright Xylon d o o 2015 All Rights Reserved Page 41 of 41
35. linuxfb fb dev fb3 plugin evdevmouse plugin evdevkeyboard 7 4 Change the Demo Applications or Design New Applications from Scratch 7 4 1 Xilinx Development Software The logiREF ZGPU ZC702 reference design and Xylon logicBRICKS IP cores are fully compatible with Xilinx development tools Vivado Design Suite 2014 4 Future design releases shall be synchronized with the newest Xilinx development tools Licensed users of Xilinx tools can use their existing software installation for the logiREF ZGPU ZC702 evaluation and modifications 7 4 2 Set Up Linux System Software Development Tools oet of ARM GNU tools are required to build the Linux software and applications The complete tool chain for the Zynq 7000 All Programmable SoC can be obtained from the Xilinx ARM GNU Tools wiki page http wiki xilinx com zyng tools Access to tools requires a valid registered Xilinx user login name and password Copyright Xylon d o o 2015 All Rights Reserved Page 38 of 41 m logiREF ZGPU ZC702 GPU T TERRE Reference Design Designed by XYLON User s Manual April 8 2015 Version v2 02 a 7 4 3 Set Up git Tools Git is a free Source Code Management SCM tool for managing distributed version control and collaborative development of software It provides the developer a local copy of the entire development project files and the very latest changes to the software Visit http wiki xilinx com using git to get instructions how to use Xilinx
36. logiREF ZGPU ZC702 Xylon logicBRICKS Graphics Processing Unit GPU Reference Design for Xilinx Zynq 7000 All Programmable SoC based ZC 702 Evaluation Kit User s Manual Version 2 02 a logiREF ZGPU ZC702 v2 02 a docx m logiREF ZGPU ZC702 GPU Meres Reference Design Xulon Designed by XYLON User s Manual y April 8 2015 Version v2 02 a Meres Designed by XYLON All rights reserved This manual may not be reproduced or utilized without the prior written permission issued by Xylon Copyright Xylon d o o logicBRICKS is a registered Xylon trademark All other trademarks and registered trademarks are the property of their respective owners This publication has been carefully checked for accuracy However Xylon does not assume any responsibility for the contents or use of any product described herein Xylon reserves the right to make any changes to product without further notice Our customers should ensure to take appropriate action so that their use of our products does not infringe upon any patents Copyright Xylon d o o 2015 All Rights Reserved Page 2 of 41 m logiREF ZGPU ZC702 GPU TE BRIS Reference Design Sulon Designed by XYLON User s Manual April 8 2015 Version v2 02 a 1 INTRODUCTION EMEN 5 1 1 DESIGN DELIV ERA BU ES eius niaren aaaea Eu breit iret cdi lle e e Re nic 6 tihi Hardware Design FICS sscssenessiebedessmedduesdUebed ese nei dues QUE ES Dind asc Rdolas i Diode
37. logicBRICKS Downloads Documentation News amp E My logicBRICKS m Evaluation License Commu tacens A Xylon logicBRICKS Graphics for Xilinx Zynq 7000 IP Core Activation WO Click to get reference designs for Xilinx ZC 702 Evaluation Board D N Create Case Request Eval IP Core Click to get the IP license key Subscribe to Newsletter Status Downloads logiCVC ML EVAL 1M Not Activated Obtain evaluation license key logiWIN EVAL 1M Not Activated Obtain evaluation license kev logiBITBLT EVAL 1M Not Activated Obtain evaluation license key Figure 16 Step 2 Selecting logicBRICKS IP Core for Licensing Home Aboutus Products Markets Solutions logicBRICKS Downloads Documentation News amp E My logicBRICK S s meer Evaluation Liens Change Password Xylon logicBRICKS Graphics for Xilinx amp Zynq 7000 IP Core Activation I cick to get reference designs for Xilinx ZC702 Evaluation Board S cM V Create Case Subscribe to Newsletter Request Eval IP Core Name Status Downloads logiCVC ML EVAL 1M Activated Already activated IP licenses logiWIN EVAL 1M Activated logiBITBLT EVAL 1M Activated Figure 17 Step 2 A List of Already Activated logicBRICKS IP Licenses logiU ART EVAL 1M Not Activated Obtain evaluation license key Your company can get one evaluation license per product per year If your company already used evaluation license in
38. n logicBRICKS IP cores and provided software can be used in many different hardware setups and with many different display types Therefore in order to be able to fully utilize the graphics provided with the reference design for the ZC702 board and to properly use logicBRICKS products in other hardware setups designers should understand the video clocking scheme implemented in the logiREF ZGPU ZC702 reference design 6 1 logiCVC ML Standard Display Resolutions and Pixel Clock For full information about setting up the display interface controlled by the logiCVC ML Compact Multilayer Video Controller IP core please refer to the IP core s User s Manual This chapter focuses on the pixel clock generation and control since it depends on the overall system s architecture to a great extent Table 3 shows required pixel clock s frequencies for several popular display resolutions Properly implemented display interface must respect the expected display signals timings which are based on the requested pixel clock Wrong pixel clock causes wrong timings on the display interface and as a consequence wrong or missing picture on the display It is visible from the table that graphic controller must be able to source different pixel clocks in order to support multiple display resolutions Table 3 Pixel Clock Common Video Resolutions Copyright Xylon d o o 2015 All Rights Reserved Page 30 of 41 m logiREF ZGPU ZC702 GPU TE BRIS Reference De
39. ntation tools More info http Awww logicbricks com Products logi3D aspx Datasheet htto www logicbricks com Documentation Datasheets IP logi3D hds pdf 2 3 4 logiCLK Programmable Clock Generator The logiCLK is a programmable clock generator IP core featuring twelve independent and fully configurable clock outputs While six clock outputs can working device The Dynamic Reconfiguration Port DRP interface gives be fixed by generic parameters prior to the implementation the other six clock ye outputs can be either fixed by generics or dynamically reconfigured in a system designers the ability to change the clock frequency and other clock parameters while the design is running by mean of a set of PLL registers Supports Xilinx Zynq 7000 All Programmable SoC 7 series and Spartan 6 FPGAs Provides 12 independent clock outputs that can be configured by generic parameters o 6 outputs can be dynamically configured through the DRP interface o 6 outputs can be configured by generics only Input clock frequency range depends on the used device s speed grade o Spartan 6 19 540 MHz o series 19 1066 MHz Output clocks frequency range o Spartan 6 3 125 400 MHz o 7 series 6 25 741 MHz Configurable ARM AMBA AXIA4 Lite and CoreConnect PLBv46 compliant registers interface ooftware support for Linux and Microsoft Windows Embedded Compact operating systems Available for Xilinx Vivado Design Suite and ISE XPS implementati
40. on logiREF 2GPU 2C702 Installation TS 0 ze lt TOPA e F By clicking Next you are accepting the following Tonos XYLON TECHNOLOGY EVALUATION LICENSE AGREEMENT FOR logi F ZGPU C702 REFERENCE DESIGN Designed by XYLON IMPORTANT UNLESS SUPERSEDED BY A SIGNED LICENSE AGREEMENT BETWEEN YOU AND XYLON THIS XYLON LICENSE AGREEMENT AGREEMENT 1 A LEGAL AGREEMENT BETWEEN YOU AND XYLON 0 0 0 PROVIDING YOU WITH THE LICENSE TO USE THE LICENSED MATERIALS UNDER THE TERMS AND CONDITIONS OF THIS AGREEMENT CAREFULLY READ THIS L OR OTMERWISE ACCE BEHALF OF 1 OTHER LEGAL ENTITY TO WHICH XYLON D O O A CROATIAN CORPORATION WITH AN OFFICE AT FALLEROVO SETALIST ZAGREB REPUBLIC OF CROATIA XYLON HAS 1 THE LICENSE O RIBED HEREIN IF YOU DO NOT AGREE TO ALL OF THE TERMS AND CONDITIONS O HIS AGREEMENT DO WOT CLICK THE ACCEPT OR AGREE BUTTON AND DO NOT ACCESS DOWNLOAD INSTALL OR USE THE LICENSED MATERIALS AS USED HEREIN THE EFFECTIVE DATE MEANS THE DATE ON WHICH LICENSEE CLICKS THE PT OR AGREE BUTTON IDENTIFIED ABOVE PURCHASES OR OTHERWISE ACCESSES DOWNLOADS INSTALLS OR USES THE LICENSED MATERIALS WHICHEVER OCCURS FIRST Noe CEMENT AGREEMENT BY CL SWHLOADEN INSTALLING OR USIN ING THE ACCEPT OR AGREE BUTTON THE LIC SOD MATERIALS YOU A fr ON ING NSEE TO BE BOUND BY THIS AGREEMENT LICENSEE OR YOU MEANS THE CORPORATION OR UE
41. on tools More info http www logicbricks com Products logiCLK aspx Datasheet http www logicbricks com Documentation Datasheets IP logiCLK hds pdf Copyright Xylon d o o 2015 All Rights Reserved Page 13 of 41 m logiREF ZGPU ZC702 GPU TE BRIS Reference Design Designed by XYLON User s Manual April 8 2015 Version v2 02 a 2 4 logicBRICKS IP Cores for Video Processing Xylon offers several logicBRICKS IP cores for video processing on Xilinx Zynq 7000 All Programmable SoC and FPGA programmable devices which can be used as extensions to Xylon 2D and 3D graphics engines or as key IP cores for video only embedded applications All logic BRICKS IP cores support ARM AMBA AXI4 on chip bus and can be easily mixed together or with Xilinx and third party IP cores logi VIEW Perspective Transformation and Lens Correction Image Processor Removes fish eye lens distortions and executes programmable transformations on multiple video inputs in a real time Programmable homographic transformation enables cropping resizing rotating transiting and arbitrary combinations Arbitrary non homographic transformations are supported by programmable Memory Look Up Tables MLUT More info htto www logicbricks com Products logiVIEW aspx Datasheet http www logicbricks com Documentation Datasheets IP logiVIEW hds pdf logiWIN Versatile Video Input Enables easy implementation of video frame grabbers Input video can be decoded
42. pothecate rent land time ahare assigna convey sell sublicense display distribute loan lease or Dope eor zoru ERE Tou Designed by KYLON Pack installation progress E userrkoncuratiDesignsToUpdatehpO69 A J scratchpad makeDeliverablessogiREF ZGPU 7C702 12261229 outp h files2 Overall installation progress M dE Oor Figure 12 Installation Process Step 3 Copyright Xylon d o o 2015 All Rights Reserved Duos oco RN a a mm Tous Des by KYLON Figure 11 Wien togiREF ZGPU ZC702 Tonus Designed by KYLON Select the estallabon path C Program Files x86 uytoniogREF 2GPU 2C702_ 150421 125 Browse Version v2 02 a Previous e Qo Installation Process Step 2 vi 19 Instaliation has completed successfully Figure 13 Installation Process Step 4 Page 18 of 41 m logiREF ZGPU ZC702 GPU TE BRIS Reference Design Designed by XYLON User s Manual April 8 2015 Version v2 02 a 3 2 1 Filesystem Permissions of the Installed Directory Windows 7 The reference design installed in the default path C Program Files xylon will inherit read only filesystem permissions from the parent directory This will block you in opening the hardware project file in Xilinx Vivado tools Therefore it is necessary to change the filesystem permissions for the current user to Full control preferably To
43. pril 8 2015 Version v2 02 a 2 LOGICBRICKS IP CORES 2 1 About logicBRICKS IP Library Xylon s logicBRICKS IP core library provides IP cores optimized for Xilinx FPGAs and Zynq 7000 All Programmable SoC logicBRICKS IP cores shorten development time and enable fast design of complex embedded systems based on Xilinx programmable devices The key features of the logicBRICKS IP cores are Compatibility with the Xilinx Vivado and ISE Design Suites logicBRICKS can be used in same ways as Xilinx IP cores and require no skills beyond general tools knowledge logicBRICKS users can setup IP core feature sets and programmable logic utilization through Xilinx implementation tools Graphical User Interface GUI Each logicBRICKS IP core comes with the extensive documentation reference design examples and can be evaluated on reference hardware platforms Xylon provides evaluation logicBRICKS IP cores to enable risk free evaluation prior to purchase Broad software support from bare metal software drivers to standard software drivers for different operating systems OS Standard software support allows graphics designers and software developers to use logicBRICKS in a familiar and comfortable way Xylon assures skilled technical support Alliance Partners Xylon ik 2D Graphics Accelerator Bit Block Transfer AXI4 j Induded logicbricks com logicbricks logibitblt 5 3 3f Audio 12S Transmitter Receiver AXI4 j Induded logicb
44. raphic Accelerator The logi3D Scalable 3D Graphics Accelerator IP core is a 3D Graphics Processing Unit GPU IP core developed for embedded systems based on the Xilinx Zynq 7000 All Programmable SoC The IP is designed to support the OpenGL ES 1 1 API specifications a royalty free cross platform API for full function 2D and 3D graphics on embedded systems including consoles phones appliances and vehicles Graphics Accelerator IP designed to support the OpenGL ES 1 1 API Common Profile Conformant to the AMBA AXIA bus specifications from ARM Compatible with popular operating systems Linux Android and Microsoft Windows Embedded Compact FPGA resource effective 3D acceleration Copyright Xylon d o o 2015 All Rights Reserved Page 12 of 41 lodiREF ZGPU ZC702 GPU TE BRIS 9 Designed by XYLON User s Manual Reference Design Sulon April 8 2015 Version v2 02 a ARM Cortex A9 CPU Core with NEON runs the geometry engine and optimizes the IP s size The logi3D can be used with different CPUs Hardware implemented 3D graphics algorithms Occlusion culling Gouraud shading MIP MAP level of the texture per pixel Texture filtering point sampling bilinear filtering and trilinear filtering Fog function per vertex Alpha Blending Full Screen Anti aliasing Parametrical VHDL design that allows tuning of slice consumption and features set Available for Xilinx Vivado Design Suite and ISE XPS impleme
45. rd to write commands directly to the screen console Page 36 of 41 m logiREF ZGPU ZC702 GPU TE BRIS Reference Design Designed by XYLON User s Manual April 8 2015 Version v2 02 a the mouse connected to the micro USB port for interacting with Qt examples Serial terminal program baud rate 115200 8N1 and USB UART connection to the ZC702 board telnet connection and Ethernet connection with the ZC702 board 7 3 1 BootUp Menu Your ZC702 board will eventually boot up to the graphical menu from which you can start different demo applications or switch to the Linux terminal To enter the graphical menu from the Linux console run the following command in the root of the filesystem Linux directory source profile If you want to prevent the ZC702 from entering graphical menu on the startup please rename config profile file on the SD card to any other name Please do not rename or remove init sh file from the SD card since it performs startup initializations required for applications to run properly Please note that graphical menu shows up only on the console on the monitor attached to your ZC702 kit If you control the ZC702 kit by a PC through a serial UART link the graphical menu is not available log iREF 2GPU reference design by Xylon Use fiue user buttons Clocated on the opposite end of zed power switch or corresponding keys on USB keyboard to choose which demo to run Actions to keys mapping North
46. real time scaled de interlaced cropped anti aliased positioned on the screen More info http www logicbricks com Products logiWIN aspx Datasheet http www logicbricks com Documentation Datasheets IP logi WIN hds pdf logilSP Image Signal Processing ISP Pipeline The logilSP Image Signal Processing Pipeline IP core is a full high definition ISP pipeline designed for digital processing and image quality enhancements of an input video stream in Smarter Vision embedded designs based on Xilinx Zynq 7000 All Programmable SoC and 7 Series FPGA devices More info http www logicbricks com Products logilSP aspx Datasheet http www logicbricks com Documentation Datasheets IP logilSP hds pdf Copyright Xylon d o o 2015 All Rights Reserved Page 14 of 41 m logiREF ZGPU ZC702 GPU T CERRO Reference Design Designed by XYLON User s Manual April 8 2015 Version v2 02 a 3 GET AND INSTALL THE REFERENCE DESIGN Xylon offers several logicBRICKS reference designs for different hardware platforms Short descriptions of all Xylon logicBRICKS reference designs can be found at http www logicbricks com logicBRICKS Reference logicBRICKS Design aspx A quick access to specific reference design is also possible through the main downloads navigation page http www logicbricks com logicBRICKS Reference logicBRICKS Design Xylon Reference Designs Navigation Page aspx Only registered logicBRICKS users can download logicBRICKS
47. ricks com logicbricks logii2s 0 0 3P Bitmap 2 5D Graphics Accelerator AXI4 j Induded logicbricks com logicbricks logibmp 0 0 3 12C Bus Master Controller AXI4 Production Induded logicbricks com logicbricks logii2c 0 0 Multilayer Video Contr wi4 Production Induded logicbricks com logicbricks logicvc 4 1 d 39 Perspective Transformation and Lens Correction Image Processor AXI4 AXI4 Stream Production Induded logicbricks com logicbricks logiview 0 0 F Scalable 3D Graphics Accelerator AXI4 Production Included logicbricks com logicbricks logi3d 1 5 3f SD Card Host Controller AXI4 Production Induded logicbricks com logicbricks logisdhc 0 0 Automotive amp Industrial r AXI Infrastructure BaseIP gt Basic Elements Communication amp Networking Debug amp Verification gt Digital Signal Processing gt Embedded Processing Details Name Multilayer Video Controller Version 4 1 Rev 2 Interfaces AXI4 Description The logiCVC ML IP core is an advanced display graphic controller that enables an easy video and graphics integration into embedded systems with the Xilinx Zyng 7000 AP SoC and FPGAs It can be used as a standalone graphics IP core or as a part of larger graphics systems along other Xylon logicBRICKS IP cores The logiCVC ML is a real plug and play IP core supported by the Xilinx Vivado IP Integrator IPI integrated software solution and designers familiar with this tool can immed
48. ry settings User set Operations Enable 8 bit anti aliased font expand operations Enable Pattern fill operations Enable Porter Duff operations Enable Global alpha in Porter Duff operations Enable Scale operations Implement bilinear scaling B Line size Scale step integer part Scale step fraction Enable Move with ROP in negative direction operations Yes Resources Internal buffers implementation BRAM Y Color format Implement support for a single color format No Select single color format ARGBS 4 Bought IP license available ox Cancel K Figure 4 Example of logicBRICKS IP Configuration GUI Click on the Documentation icon in the GUI opens the User s Manual of the logicBRICKS IP core 2 2 Evaluation logicBRICKS IP Cores Xylon offers free evaluation logicBRICKS IP cores which enable full hardware evaluation Imported into the Xilinx ISE Platform Studio XPS and Vivado Design Suite P parameterization through the tool GUI interface Bitstream generation lf you need to simulate logicBRICKS IP cores please contact Xylon The logicBRICKS evaluation IP cores are run time limited and cease to function after some time Proper operation can be restored by reloading the bitstream Besides this run time limitation there are no other functional differences between the evaluation and fully licensed logicBRICKS IP cores Evaluation logicBRICKS IP cores are distributed
49. s oe hdules i DE odi 6 NNAMESnUIINTMRR e 6 EMEN 6 1 2 JoGe MODE S aea e T ee ee ee eee ee eee ee 6 1 2 1 Quick Evaluation with no HW and or SW Changes ccccccseecceeceeseceeseeeeceessaeeeceesaeeeeees 7 1 2 2 Develop Standalone and Linux Software no HW Changes ccccseeccseeeeseeeeeseeeeseeeeens 7 1 2 8 Full GPU Customization HW and SW Changes cccceececseeeeseeeeeeeeeeseeeeseeeeseeeesaeeeees 7 1 3 XILINX DEVELOPMENT SOFTWARE 2 eccececceccececceceececeececeeceeneceececaeeeseeseeaeseeneceeseeeseeneseeneseenes 7 1 4 GRAPHICS DEMO PREVIEW sss ocexvicxosex ve vie eut este anes asi astonish nce ees ain eine ui econ 8 2 LOGICBRICKS IP CORES eeeeeeeeeeeeeeeeeeehenhnhu nhan ha sk sa oaa Rasa ss a4 sg IRR ua uas y sy sa aa sans aura R rau 9 2 1 ABOUT LOGICBRICKS IP LIBRARY eeeesee IH mnm m mnm reme rese nere nnne 9 2 2 EVALUATION LOGICBRICKS IP CORES eeesesen IH HII eme memne em mem re me nemen retenus 10 2 3 LOGICBRICKS IP CORES USED IN THIS DESIGN cccececeeceeceeeeceeeeceececeeeeseeeeeeeeeeneseeneseenes 11 2 3 1 logiCVC ML Compact Multilayer Video Controller cccccecceeeeecneeeeeeeeeeeeeeeeeeeaeeeeesaaeees 11 2 3 2 logiBITBLT Bit Block Transfer 2D Graphics Accelerator cccccccccsececeeeeseeeseeeeseeeeaes 12 2 3 3 logi3D Scalable 3D Graphic Accelerator ccccccceccceeeeceeeeseeeseeeeseeeeeeeseueeseeeseu
50. sign Designed by XYLON User s Manual April 8 2015 Version v2 02 a The logiCVC ML internal structure is shown on the block diagram on Figure 26 The VCLK clock signal controls all circuits inside the logiCVC ML IP core except the video memory subsystem AXIA related circuits and registers AXI4 Lite The VCLK clock signal frequency should be set equal to the pixel clock needed for specific display resolution Table 3 The pixel clock output PIX CLK is proportional to the VCLK clock input and to control bits in the DTYPE and CTRL registers please refer to the logiCVC ML User s Manual paragraph 10 2 Register Description A special clock module is requested outside of the logiCVC ML IP core to support the functionality of adjustable PIX CLK clock frequencies changeable display resolutions This reference design uses Xylon s auxiliary IP core the logiCLK Programmable Clock Generator IP core To learn more about this IP core please read the datasheet http www loaicbricks com Documentation Datasheets IP logiCLK hds pdf m 3 GPI 4 0 GPO 4 0 REGISTER EN_VDD INTERFACE Helene EN VEE EN V EN BLIGHT EXTERNAL PARALLEL INPUT clk ctrl data VIDEO MEMORY E CURR VBUFF 9 0 ACCESS BLOCK HSYNC E NEXT VBUFF 9 0 SYNC EE GENERATOR EE VSYNC SW 4 0 E FIFO BLANK E SW GRANT 4 0 CVC CURR VBUFF 9 0 EB VMEM Sore GENERATOR MULTILAYER OUTPUT RST ALPHA NN STANDARD VOU
51. stances of logicBRICKS IP cores i e add the second logiCVC ML IP core and drive two displays with different graphics content add the logiWIN IP core and process the video Add your own or third party IP cores to various combinations of logicBRICKS IP cores Copyright Xylon d o o 2015 All Rights Reserved Page 26 of 41 T logiREF ZGPU ZC702 GPU TE anes Reference Design Designed by XYLON User s Manual April 8 2015 Version v2 02 a Xilinx Zynqg 7020 Programmable Logic GigE Flash QSPI SD Card UART SPI CAN I2C nnn PR ej gt 6 Processing System l ni AXI4 Lite ADV7511 logiCVC ML AXIA HDMI i VCLK CLK IN DVI DISPLAY AXI4 CLOCKS Processing system 7 Figure 23 A Minimal Zynq 7000 AP SoC Display Controller Figure 23 shows an example architecture featuring only the logiCVC ML display controller IP core ouch a configuration provides no graphics acceleration in the programmable logic and all graphic contents must be fully drawn by the Processing System PS The consumption of programmable logic resources is minimal The Figure 27 shows clocking structure details please see the chapter 6 VIDEO OUTPUT CLOCKING Copyright Xylon d o o 2015 All Rights Reserved Page 27 of 41 m logiREF ZGPU ZC702 GPU Meres Reference Design Designed by XYLON User s Manual April 8 2015 Version v2 02 a 5 2 Memory Layout 0 MB logiBITBLT 768 MB logiCVC layer 2 768MB
52. tion hardware platforms Create Case MBE Subscribe to Newsletter JJO AND VIDEO SOURCES DES Downloads Welcome to logicBRICK S Registered Users Section Within this section you can View Data View and update your user data logicBRICKS profile Change Passwor d Change your logicBRICKS password ss and search the knowledge base Access an Knowledge Base The knowledge base is in preparation Figure 15 Step 1 My logicBRICKS Navigation Page Step 2 Select the evaluation logicBRICKS IP core and click on Obtain evaluation license key link Figure 16 If you are entitled to get the evaluation logicBRICKS IP core you will be immediately asked your Ethernet MAC ID number or Sun Host ID as described in the Step 3 Figure 19 If the evaluation logicBRICKS IP cores list looks differently from the one shown on Figure 16 for example as the list presented by the Figure 17 please fill in and submit the request form Figure 18 and allow us some time to process your request Scroll down to get to the request form For instructions how to find your Ethernet MAC or host ID please visit http www logicbricks com Documentation Article aspx articlelD KBA 01186 MOJXKD Copyright Xylon d o o 2015 All Rights Reserved Page 22 of 41 m logiREF ZGPU ZC702 GPU Meres Reference Design User s Manual Designed by XYLON April 8 2015 Sulon Version v2 02 a Home Aboutus Products Markets Solutions
53. ure driver and build the Linux kernel please See logiREF ZGPU ZC702 s INSTALLATION ROOT software Linux kernel readme txt ordownload User s manual document Copyright Xylon d o o 2015 All Rights Reserved Page 32 of 41 TF anes Designed by XYLON logiREF ZGPU ZC702 GPU Reference Design User s Manual Sulon April 8 2015 Version v2 02 a htto www logicbricks com Documentation Datasheets SW Xylon Linux FrameBuffer pdf Note that Xylon provides a Device Tree Source dts file with IP core configuration information specific to this reference design When using the Linux kernel with this reference design user must use the Xylon dts dtb files located in the software Linux kernel linux xlnx v2014 2 directory instead of the ones provided by Xilinx Figure 28 shows an excerpt from Xylon dts file logicvc 0 logicvc 40030000 compatible xylon logicvc 4 00 a reg lt 0x40030000 0x6000 interrupt parent amp ps7 scugic 0 interrupts lt 0 58 4 gt background layer bits per pixel 32 background layer type rgb hsync active low vsync active low size position pixel stride 2048 layer O1 address 0x338F4000 buffer offset 1080 bits per pixel lt 32 gt type rgb transparency pixel h layer 11 address 0x31FA4000 buffer offset 1080 bits per pixel 32 type rgb transparency layer 5 layer 21 address 0x30000000 buffer o

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