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CMX7032 and CMX7042 Version 2 Datasheet

1. CML s proprietary FirmASIC component technology reduces cost time to market and development risk with increased flexibility for the designer and end application FirmASIC combines Analogue Digital Firmware and Memory technologies in a single silicon platform that can be focused to deliver the right feature mix performance and price for a target application family Specific functions of a FirmASIC device are determined by uploading its Function Image during device initialization New Function Images may be later provided to supplement and enhance device functions expanding or modifying end product features without the need for expensive and time consuming design changes FirmASIC devices provide significant time to market and commercial benefits over Custom ASIC Structured ASIC FPGA and DSP solutions They may also be exclusively customised where security or intellectual property issues prevent the use of Application Specific Standard Products ASSP s Handling precautions This product includes input protection however precautions should be taken to prevent device damage from electro static discharge CML does not assume any responsibility for the use of any circuitry described No IPR or circuit patent licences are implied CML reserves the right at any time without notice to change the said circuitry and this product specification CML has a policy of testing every product shipped using calibrated test equipment to ensure compl
2. R_ AxData3 Checksum1high________________ 16 b9 R_ xData4 Checksumtlow________________zzz 16 BA R RSSI SO 16 BBB R RSS 16 BC_ Reserved S BD Reserved SO BE_ Reserved SO BF_ Reseved sco Reeva O OoOo o ooo S 16 LOA Ww Moes OSO 16 16 03 Reserved S 0 Reserved 2 05 R Stats2 S 16 C6 R IRQStatus S 16 C7 Reserved S 16 C9 R_ AuxADC Data 16 CA Reserved 222 16 CB Reserved S 16 cc Reserved S 16 CD Reserved S 16 16 SCF Reserved S All other C BUS addresses including those not listed above are either reserved for future use or allocated for production testing and must not be accessed in normal operation 2006 CML Microsystems Plc 44 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 8 Performance Specification 8 1 Electrical Performance 8 1 1 Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device Min Max Unit Supply DVpp DVss 0 3 4 5 V AVpp AVss 0 3 4 5 V RFVpp RFVss 0 3 4 5 V CPVpp RFVss 0 3 4 5 V Voltage on any pin to DVss 0 3 DVpp 0 3 V Voltage on any pin to AVss 0 3 AVpp 0 3 V Voltage on any pin to RFVss excluding CP Vpp 0 3 RFVpp V 0 3 Current into or out of any power supply pin excluding Vas 30 30 mA i e VDEC AVDD AVss DVop DVss CPV pp RFVpp or RFVss Current into or out of any other pin 20
3. 20 mA Voltage differential between power supplies DVpp and AVpp or CPVpp 0 0 3 V AVpp and CPVpp 0 0 3 V DVss and AVss or RFVss 0 50 mV AVss and RFVss 0 50 mV All Packages Min Max Unit Storage Temperature 55 125 C Operating Temperature 40 85 C Q1 Package 64 pad VQFN or Q3 Package 48 pad VQFN Min Max Unit Total Allowable Power Dissipation at Tamb 25 C 1410 mW Derating 14 mW C L9 Package 64 pin LQFP or L4 Package 48 pin LQFP Min Max Unit Total Allowable Power Dissipation at Tamb 25 C 668 mW Derating 6 mW C 8 1 2 Operating Limits Correct operation of the device outside these limits is not implied Notes Min Max Unit Supply Voltage DVDD DVss 3 0 3 6 V AVDD AVSS 3 0 3 6 V CPVDpD RFVss 3 0 3 6 V RFVDD DVss 1 2 25 2 75 V VDEC DVss 2 2 25 2 75 V Operating Temperature 40 85 C Clock Frequency 9 6 19 2 MHz Function Image size 24 46 kBytes Notes 1 The VDEC supply is automatically created from DVDD by the on chip voltage regulator 2 The RFVDD supply can be supplied from the VDEC supply if preferred 2006 CML Microsystems Plc 45 D 7032 42_FI1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 8 1 3 Operating Characteristics For the following conditions unless otherwise specified External components as recommended in Figure 2 Maximum load on digital outputs 30pF Clock Frequency 19 2MHz 20ppm Tamb 40 C to 85 C AVpp
4. e SysCLK2 AD b10 15 SysCLK2 R Pre CLK Output AE b11 15 384kHz 50MHz 9 6MHz Xtal or MainCLK 19 2MHZ Clock Figure 16 System Clock Generation The CMX7032 includes a 2 pin crystal oscillator circuit This can either be configured as a 9 6MHz xtal oscillator or the XTAL input can be driven by an externally generated 19 2MHz clock 7 11 Powersave The CMX7032 implements a comprehensive power saving scheme which will automatically enable the sections of the device that are required and return them to their power saved state when no longer needed In addition a user defined Sleep mode maybe enabled which allows the device to drop into power saving mode should a Receiver channel not detect any activity at the start of the AIS burst This feature should be used with care to ensure that any peripheral circuits are powered up again in time to receive the following burst correctly When an Rx channel enters or leaves Sleep mode an Rx State IRQ may be asserted which allows the host to powersave other external circuits under its control 2006 CML Microsystems Plc 43 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 7 12 C BUS Register Summary Table 11 C BUS registers ADDR Word Size 0 st eee 16 16 A9 R_ RxDataReadt _ ______ 16 SAA R RxDataRed2____ 16 16 16 16 16 AF Reserved 2222 BO Reserved SS 16 16 16 16 Ba R_ RFChannelStatus _____________ 8 16 16 16 Bg
5. timings subject to system throughput constraints 2006 CML Microsystems Plc 51 D 7032 42_F11 1 2 AIS Baseband IC with without RF Synthesizer 8 3 SPI Timing EPSCSN EPSCLK CMX7032 CMX7042 o lt tc gt _ _ 70 Vdd Y A __ 30 Vdd y ta gt P lt tos gt gt ty EPSO Figure 18 SPI Interface Timing Serial SPI Bus Interface Timing tck teL tCH tDOV tDoH tos DH tcLc tecH Notes Clock cycle time Clock low pulse width Clock high pulse width Out data valid time Out data hold time In data set up time In data hold time Chip select low to clock rising edge Clock falling edge to chip select high EPSI Notes lt tck t pov Min Typ 16 Max Unit Xtal Clock Periods Xtal Clock Periods Xtal Clock Periods ns ns ns ns Xtal Clock Periods Xtal Clock Periods 1 The serial SPI bus clock frequency is the CMX7032 internal Main Clock 16 frequency When the CMX7032 is first powered up the internal Main Clock is connected directly to the Reference Clock the clock source present on the CLOCK pin An EEPROM should be chosen which is compatible with these timings 2 Maximum 30pF load on each serial bus interface line 2006 CML Microsystems Plc 52 D 7032 42_F11 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 Index Area 1 c gt DIM MIN
6. without RF Synthesizer CMX7032 CMX7042 significant bit first At the end of the message the receive channel state changes from Receiving to either ldle or one of four error states below At the same time an Rx State Alert interrupt is flagged The four error conditions that the CMX7032 CMX7042 can detect in a received message in burst mode are e Message too long or missing end flag This indicates that the received message after bit de stuffing is too long to fit into the internal message buffer This condition could be caused by a missing or corrupted end flag e CRC mismatch This indicates that the received frame checksum does not match that calculated by the CMX7032 CMX7042 most probably as the result of one or more message bits being corrupted e New frame header found when message buffer full This happens if the internal message buffers are still in use when another message arrives This is caused by a failure of the host uC to read the received messages out quickly enough e End flag not on byte boundary This indicates that the received message after bit de stuffing is not a multiple of 8 bits Assuming that the message was transmitted correctly it is probably caused by an end flag being missed due to noise and a subsequent message s start flag being mis identified as the expected end flag or a bit error causing the bit de stuffer to fail If one of these four error conditions is detected in a received message the
7. 29 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 e Reset Rx1 data buffer pointer e Copy N bits 1 to 15 from Rx1 data buffer to Read Data register 0 e Increment the data buffer pointer e Reset Rx2 data buffer pointer e Copy N bits 1 to 15 from Rx1 data buffer to Read Data register 0 e Increment data buffer pointer DataBitResetNTx e Reset Tx data buffer pointer e Copy N bits 1 to 15 from Write Data register 0 to Txdata buffer e Increment data buffer pointer DACs 7 5 7 Modem Tasks and Codes Modem tasks transmit data on the MOD1 and MOD2 output pins or receive and recover data from the RxIN pins Modem tasks also coordinate data transfer between the Data Buffers and their respective Modems Note that for receive tasks a 1 or 2 at the end of the task name refers to the Rx channel which is being addressed Table 4 Modem Tasks Description No command takes no action Abort the ongoing modem task on Rx1 Rx2 or Tx ___ _ _ _ AAAAA4 4 2 2 2 __ _ _ A Rx Burst Wait for a training sequence then r Demodulate and store N words N is defined by Rx data count register ____Q_ ___ 44 4 q _ _ _ of data buffer Start on next slot clock next slot clock Se eaters buffer Start as soon as modulator i is free PRBS Transmit pseudorandom bit sequence RW Repeatecily transmit one word NA Ys Hardware Control 7 6 T
8. 63 Charge pump current low 63 Charge pump current temperature variation Charge pump current voltage variation Charge pump current sink to source match Supply Current 2006 CML Microsystems Plc 48 625 CMX7032 CMX7042 Max Unit Bits 90 VDD MQ _ pF 10 mV 4 LSB 3 LSB Bits 90 VDD kQ 4 LSB 1 LSB kQ uVrms 40 0 MHz 2 0 Vp p 8192 500 kHz 600 MHz 0 dBm 1048576 dBc Hz mA uA per C per V of ISET mA D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 Not including any current drawn from the device pins by external circuitry RF and Auxiliary circuits disabled Characteristics when driving the CLOCK XTAL pin with an external clock source Applies when utilising VB AS to provide a reference voltage to other parts of the system When using VBIAS as a reference VBIAS must be buffered VBIAS must always be decoupled with a capacitor as shown in Figure 4 Timing for an external input to the CLOCK XTAL pin With no external components connected After multiplying by gain of input circuit with external components connected Gain applied to signal at output of buffer amplifier DiscFB AltFB OR MicFB Design Value Overall attenuation input to output has a tolerance of OdB 1 0dB Power up refers to issuing a C BUS command to turn on an output These limits apply only if VBIAS is on and stable Small signal impedance at AVpp 3 3V an
9. 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 7 Detailed Descriptions 7 1 Clock Source The CMX7032 can be used with either a 9 6MHz xtal or a 19 2MHz oscillator The RFCLOCK should also be derived from this source to avoid the generation of unwanted spurious signals 7 2 Host Interface This section provides a general description of the C BUS serial interface protocol used to transfer data control and status information between the CMX7032 and its host C BUS is a serial interface similar to SPI that uses a simple transaction oriented command response protocol with addressing to access specific registers within the CMX7032 Each C BUS transaction consists of a single Register Address Command byte A C byte sent from the uC which may be followed by one or more data byte s sent from the uC to be written into one of the CMX7032 s Write Only Registers or one or more data byte s read out from one of the CMX7032 s Read Only Registers as illustrated in Figure 6 Data sent from the uC on the Command Data line is clocked into the CMX7032 on the rising edge of the Serial Clock input Reply Data sent from the CMX7032 to the uC is valid when the Serial Clock is high The CSN line must be held low during a data transfer and kept high between transfers The C BUS interface is compatible with most common UC serial interfaces and may also be easily implemented with general purpose uC I O pins controlled by a simple so
10. ACTIVATE_ ptr to C BUS B6 Send Block 3 Length ACTIVATE_len to C BUS B7 y Wait for C BUS C6 bit 0 to be set to 1 v Send 0001 to C BUS C8 v Wait for C BUS C6 bit O to be set to 1 y Verify Checksum values in A9 AA and B8 B9 note BOOTEN1 and Send Device Activation Code hi to C8 BOOTEN2 may be changed at this point if required y Wait for C BUS C6 bit O to be set to 1 y Vdd Send Device Activation Code lo to C8 y Wait for C BUS C6 bit O to be set to 1 BOOTEN1 y CMX7032 is now ready for use BOOTEN2 Figure 7 FI Loading from Host The download time is limited by the clock frequency of the C BUS with a 5MHz SCLK it should take less than 500ms to complete 7 3 2 FI Loading from EEPROM The FI must be converted into a format for the EEPROM programmer normally Intel Hex and loaded into the EEPROM either by the host or an external programmer The CMX7032 needs to have the BOOTEN pins set to EEPROM load and then on power on or following a C BUS General Reset the CMX7032 will automatically load the data from the EEPROM without intervention from the host controller 2006 CML Microsystems Plc 20 D 7032 42_F11 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 BOOTEN2 0 BOOTEN1 1 y Power up Reset CMX7032 v Wait for C BUS C6 bit 0 to be set to 1 y Verify C
11. Channel Control register B3 The step size comparison frequency is programmable to minimise the effects of phase noise this should be kept as high as possible This can be set as low as 2 5kHz for a reference input of 20MHz or less or up to 200kHz limited only by the performance of the phase comparator The frequency for each synthesizer is set by using two registers an R register that sets the division value of the input reference frequency to the comparison frequency step size and an N register that sets the division of the required synthesized frequency from the external VCO to the comparison frequency This yields the required synthesized frequency Fs such that Fs N R x Frer where Free is the selected reference frequency Other parameters for the synthesizers are the charge pump setting high or low e Since the set up for the PLLs takes 4 x RF Channel Data register writes it follows that while updating the PLL settings the registers may contain unwanted or intermediate values of bits These will persist until the last register is written It is intended that users should change the content of the RF Channel Data register on a PLL that is disabled powersaved or selected to work from the alternate register set Tx and Rx are alternate register sets There are no interlocks to enforce this intention The names Tx and Rx are arbitrary and may be assigned to other functions as r
12. DVpp CPVpp 3 0V to 3 6V RFVDD 2 25V to 2 75V Reference Signal Level 300mV pk pk with AVpp 3 3V Signal levels track with supply voltage so scale accordingly Signal to Noise Ratio SNR in bit rate bandwidth Input stage gain 0dB Output stage attenuation OdB DC Parameters Notes Min Typ Max Unit Supply Current 21 All Powersaved Config mode Dipp DVpp 3 3V VDEC 2 5V 8 100 uA Alpp AVpp 3 3V 4 20 uA RFlpp CPVpp 3 3V RFVpp 2 5V 4 20 UA Rx Mode 22 Dipp DVpp 3 3V Vpec 2 5V 14 4 TBD mA Albo AVpp 3 3V 5 8 TBD mA Rx Mode Sleep Enabled 22 Dipp DVpp 3 3V Vpec 2 5V 10 TBD mA Alpp AVpp 3 3V 1 8 TBD mA Tx Mode 22 Dipp DVpp 3 3V Vpec 2 5V 20 TBD mA Albo AVpp 3 3V 11 TBD mA Additional current for RF Synthesiser 23 Dipp DVpp 3 3V VDEC 2 5V 0 mA Alpp AVDD 3 3V a 0 mA RFlpp CPVpp 3 3V RFVpp 2 5V 2 0 4 5 mA Additional current for Auxiliary System Clock output running at 4MHz Dipp DVpp 3 3V Vpec 2 5V 250 uA Alpp AVpp 3 3V 300 uA Additional current for Auxiliary ADC Dipp DVpp 3 3V Vpec 2 5V 50 uA Alpp AVpp 3 3V 1 uA Additional current for each Auxiliary DAC Dipp DVpp 3 3V Vpec 2 5V 0 E mA Alpp AVpp 3 3V 200 uA CLK 25 Input Logic 1 10 DVpp Input Logic 0 30 DVpp Input current Vin DVpp 40 uA Input current Vi
13. Figure 14 Example RF Synthesizer COMPONENSS c ccccseeeseceeeeeeeeeeeeseeeeeeeceeaeseeeeeeeeseaaeseseeeeeessaaeeees 39 Figure 15 Single RF Channel Block Diagrama id 40 Figure 16 System Glock Generation id 43 Figures 7 OC BUS TIMING escitas aaa bas 51 Figure 18 SPI Interface Timing cccccccccssseeccccceeseeceecseueeeeeceeesseeesceaaeeeeeseaaseceessseaseceessagseseeessaageeeeeeaas 52 Figure 19 Mechanical outline for 64 pad VQFN package Q1 ooccccccccocccncccccocccnncnonancnononnnnconnnononnnnnnnos 53 Figure 20 Mechanical outline for 64 pin LQFP leaded package L9 ooooncccccccnnocnnccconnccnnnonanccnnnnononnnaos 53 Figure 21 Mechanical outline for 48 pad VQFN package Q3 occoooccncccccocccnncccnoccconcnonanccnnonnanconnconnncnnnnos 54 Figure 22 Mechanical outline for 48 pin LQFP leaded package L4 ccccconnccnccccconcconcccnancnncononnnonnnos 54 2006 CML Microsystems Plc 5 D 7032 42_F11 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 2 Block Diagram NS E 4 gt Mod 1 O P Transmit functions Tx GMSK gt gt Mod 2 O P HDLC NRZI GMSK ES Receive functions C RX1 in and GMSK NRZI HDLC Rx1 GMSK a decode decode decode AIS I put 1 VBias oO gr __ S 1 FSK C RX2 in mux q o GMSK NRZI HDLC Rx2 GMSK decode decode decode AIS VBias inputs Ca Spare DN VBias nena General Auxiliary functions Auxi
14. and Buffers for Tx Rx Tasks e Command register contains Data and Modem task fields as described above e Status register contains bits that indicate when tasks are complete which can interrupt the host Command Reg Free TBFREE R1BRDY R2BRDY TxDONE Rx1OVF Rx20VF Config Task Complete Data Task Complete O O O O O O OOO e Interrupt Mask Host write register to specify which status bit can cause an interrupt e Write Data registers 0 3 Contain data written from host uC to transmit via the Tx Modulator e Read Data registers 0 3 Contain data received from Rx Demod for host uC to read e Tx Data Buffer The Tx Data is double buffered which allows the host uC to write to the Tx Data Buffer while the modulator is simultaneously transmitting data it reads from the Tx Modem Buffer Each buffer is capable of holding one full 5 slot AIS message e Rx1 2 Data Buffer The demodulator writes data directly into these internal buffers There are two buffers per channel which are used alternately every time a new burst is detected This allows the host uC to read from one buffer while reception continues to fill the other Each buffer is capable of holding a full 5 slot AIS message 7 5 4 Write Data Registers An array of four 16 bit C BUS write registers form the Write Data C BUS registers The device reads and acts upon the content of these data write registers as instructed by the Data Task bits of the Command register while in
15. e User clock synthesizers generate two clocks for external use and eliminates an external clock synthesizer when needed to support peripheral devices e User selected method for loading a Function Image either from the host uC via C BUS or from an external serial EEPROM e Integrated 2 5V regulator can develop 2 5V from required 3 3V supply e Powersave facilities minimize total system power 6 2 AIS system formats The AIS system uses two basic channel access mechanisms Self Organising Time Division Multiple Access SOTDMA and Carrier Sensing Time Division Multiple Access CSTDMA The CMX7032 is compatible with both systems and offers additional features which simplify the implementation of CSTDMA The SOTDMA system is detailed in ITU M 1371 1 and IEC 61993 2 while the CSTDMA is detailed in IEC 62287 The CSTDMA system is used in the implementation of the Class B CS AIS This requires the Receiver to monitor the first part of a slot for an existing AIS transmission from another station before deciding to use the slot for its own transmission or aborting and selecting a different slot The SOTDMA system is used in the Class A and Base Station AIS as well as the Class B SOTDMA AIS standard The relevant International standards are 0 ITU M 1371 1 1 IEC 61993 2 Class A 2 IEC 62287 1 Class B CSTDMA 3 IEC 62287 2 Class B SOTDMA 4 IEC 62320 1 Base Station 5 IEC 62320 2 Aids to Navigation 2006 CML Microsystems Plc 16 D
16. equipment cost and size The CMX7042 is identical in functionality to the CMX7032 with the exception that the two on chip RF Synthesizers have been deleted which enables it to be supplied in a smaller package This document refers to both parts generically as the CMX7032 unless otherwise stated The CMX7032 CMX7042 devices utilise CML s proprietary FirmAS IC component technology On chip sub systems are configured by a Function Image this is a data file that is uploaded during device initialisation and defines the device s function and feature set The Function Image can be loaded automatically from an external EEPROM or from a host uController over the built in C BUS serial interface The device s functions and features can be enhanced by subsequent Function Image releases facilitating in the field upgrades This document refers specifically to the features provided by Function Image 1 1 This Datasheet is the first part of a two part document comprising Datasheet and User Manual the User Manual can be obtained by registering your interest in this product with your local CML representative 2006 CML Microsystems Plc 2 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 CONTENTS 1 DEDOS CUIDA veuuansdeucekat sosacesadencweatnssueatunnccendecses 2 2 Block Diagram seein cei sss asks ticaces ad 6 3 SIG Mal alli 7 4 Recommended External Components ccceeeeeeeceeenseeeeeseeeeessnseee
17. i CML Microcircuits COMMUNICATION SEMICONDUCTORS D 7032 42_F11 1 2 September 2006 DATASHEET CMX7032 CMX7042 AIS Data Processor Provisional Issue Marine AIS data processor designed for Limiter Discriminator based RF systems Features e Half Duplex GMSK and FSK Modem e AIS and DSC Data Format e Optimum Co channel and Adjacent channel Performance e Flexible Channel Configuration Two Simultaneous Rx One Tx e Supports Carrier Sensing Channel Access CSTDMA Operation e Low Profile 64 or 48 pad Leadless VQFN and 64 or 48 pin LQFP packages e Configurable by Function Image e Two RF synthesizers CMX7032 only e Two Auxiliary System Clock Generators e Low Power 3 0 to 3 6V Operation e Limiter Discriminator Rx Interface e Flexible Tx Interface and Q or two point modulation e Auxiliary ADC and DAC Functions 4x 10 bit DACs 2 x 10 bit ADCs Applications e Automatic Identification System AIS for Marine Safety e AIS Aids To Navigation AtoN e AIS Class B Transponders e AIS Rx only or Tx only Modules Tx Section es GMSK Message eee NRZI Encoder Buffer Encoder Rx Section E GMSK rl Message E NRZI Rx1 Decoder Buffer MO E Decoder Limiter Discriminator FSK Mesage Decoder Buffer Rx2 Limiter HDLC Discriminator GMSK Mesage Decoder Reset and ei ea A ceca y Power control AIS fs n Tranceiver GPIO CMX7032 TH Dual Clock Generat
18. operation by measuring the signal level at the start of a slot period and aborting the transmission if a level over a user defined threshold is found This fact is reported to the host in Status2 C BUS register C5 The CSTDMA threshold measurement window is setup by the Tx Sequence Config task using timing values based on the number of 24kHz tick increments from the rising edge of the SlotCLK pulse During this period if Tx_Status and CS ENA are both active the CMX7032 will measure the RSSI level of the appropriate channel set in C BUS Mode register C1 sample RSSI at 48k samples sec scale values to 0 128 apply the look up table values apply the CSTDMA_gain value accumulate values over the defined period compare the value with the value in the C BUS CS Threshold register C2 and abort the transmission if it is exceeded ii A Note that the same lookup table is used for both CSTDMA Threshold measurement as the RSSI measurement 7 4 9 RSSI Measurement RSSI can not be determined directly from the baseband signal output of a limiter discriminator device so the CMX7032 has two dedicated inputs one for each Rx channel for separate external analogue RSSI signals Suitable outputs are available on many limiter discriminator ICs e g Philips SA605 The ADCs sample the signals during a user defined window and apply an averaging algorithm and present the results in C BUS registers BA and BB The RSSI measurement windows are
19. transmit mode Generally they may be written at any time by the host uC with no effect on internal device operation When a Data task is issued the Data registers will be read by the device and so should not be modified by the host uC until the Data Task complete bit is set in the Status register Data tasks access the registers as a number of words 1 to 4 or as a number of bits 1 to 16 in A7 however if a bit format Data Task is used it must be the final data task issued in a multi data transfer from the host The next data task issued should be a DataWordReset or DataBitReset to re initialise the internal data buffer pointers a bit format task is usually used as the last transfer of a data block that is not a complete number of words in length Word format Bt 15 14 13 12 1 17 10 9 8 7 6 5 1 4131 21 1 0 Register A7 Data write from host uC to device word 1 MSB sent first E Bite F15 14 LS Tal e SEA Laa pea ta OA Register A8 Data write from host uC to device word 2 MSB sent first Bite 15 14 13 12 1 17 10 9 8 7 6 5 1 4131 2 1_ 0 Register B6 Data write from host uC to device word 3 MSB sent first ESB J15 14 13 12 AE OS LS 7 A ET O Register B7 Data write from host uC to device word 4 MSB sent first Bit format AB A EA ASA A AO ES Fre aE A a a ae Oe Register A7 Data write from host uC to device bits 0 15 bit 15 transmitted first 2006 CML Microsystems Plc 28 D 70
20. where a high frequency reference oscillator would not forgive a small phase error 2006 CML Microsystems Plc 41 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 RF Inputs The RF inputs are differential and self biased when not powersaved They are intended to be capacitatively coupled to the RF signal The signal should be in the range OdBm to 20dBm not necessarily balanced To ensure an accurate input signal the RF should be terminated with 500 as close to the chip as possible and with the and inputs capacitatively coupled to the input and ground keeping these connections as short as possible The RF input impedance is almost purely capacitative and is dominated by package and printed circuit board parasitics Guidelines for using the RF Synthesizers e RF input slew rate dv dt should be 14 V us minimum e The RF Synthesizer 2 5V digital supply can be powered from the VDEC output pin e RF clock sources and other different clock sources must not share common IC components as this may introduce coupling into the RF Unused ac coupled clock buffer circuits should be tied to a dc supply to prevent them oscillating By default the RF clock source is routed to the XTAL Oscillator input internally e It is recommended that the RF Synthesizers are operated with maximum gain Iset ie Iset tied to RFVss e The loop components should be optimised for each VCO 7 10 System Clock Synt
21. 0nF C20 10uF C25 10nF R7 See note 3 C8 100pF C26 10uF R8 100kQ C9 100pF X1 9 6MHz R9 See note 4 C12 100pF See note 1 R10 100kQ C14 100pF Resistors 5 capacitors and inductors 20 unless otherwise stated Notes 1 X1 can be a 9 6MHz crystal or a 19 2MHz external clock generator The tracks between the crystal and the device pins should be as short as possible to achieve maximum stability and best start up performance 2 R5 should be selected to provide the desired dc gain assuming C11 is not present of the input as follows GAINRyIN 100kQ R5 The gain should be such that the resultant output at the RxIN1FB pin is within the input signal range specified in 8 1 3 3 R7 should be selected to provide the desired dc gain assuming C13 is not present of the input as follows GAINRxIN2 100kQ R7 The gain should be such that the resultant output at the RxIN2FB pin is within the input signal range specified in 8 1 3 4 R9 should be selected to provide the desired dc gain assuming C15 is not present of the input as follows GAINSpareADC 100kQ R9 The gain should be such that the resultant output at the RxIN2FB pin is within the input signal range specified in 8 1 3 5 Care should be taken in connecting the output of the Limiter Discriminator device to the RxIN pins of the CMX7032 The format of the GMSK signal requires that the frequency response of the input circuits extends to below 10Hz however the variation
22. 1 MODULATE START Defines the startofdatamodulation ie 1 MODULATE_END Delay from the end of modulation based on the last data bit loaded into modem includes a 20 tick delay for the internal filters o i 1 1 RAMDAC_DOWN AuxDAC1 will start executing a Ramp down o 1 O O Tx OFF PinTxEnableisde asseted Table 6 Tx Sequence events When calculating the MODULATE_START timing value the delay through the CMX7032 CMX7042 s internal transmit filters and any external components must be taken into account to ensure that data bits appear on air at the correct time the filter delays are specified in section 8 1 4 The MODULATE_END event has an in built delay of 20 ticks to allow the last bit to make its way out of the transmit filter Allowance must be made for this built in delay as well as for the delay through any external components when calculating the timing of the transmit power down events A working example of how to set up a transmit event sequence is shown in Table 7 the order of events and delay timings shown are for illustrative purposes only 2006 CML Microsystems Plc 33 D 7032 42_F11 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 Insert 10 tick delay then start monitoring the chosen Rx CSTDMA_START 1 10 20 input for a signal which may cause an abort if CSTDMA enabled Insert 17 tick delay then start feeding data to the transmit modulator and filters this allows for the 20 tick storage e
23. 11 15 7 and the RAMDAC is set to its default values 312us this sequence approximates to the Class B CSTDMA timing with ideal hardware RAMDAC starts 20bits 50 ticks after SlotCLK Table 7 Example Tx Event Sequence Setup 7 6 6 Modulation Formats The CMX7032 CMX7042 can be configured to drive either a two point VCO amp Reference modulator or an I amp Q modulator by selecting the appropriate Config task see User Manual section 11 15 1 Typical Tx spectrum plots for both modes are shown below generated by modulating a signal generator with the outputs of MOD1 and MOD2 and then analysing the signal on a spectrum analyser Note that these plots represent the steady state transmission and so are shown with the Class A and Class B SOTDMA spectrum mask 70dBc The Class B CSTDMA standard specifies a slotted transmission with a mask at 60dBc 2006 CML Microsystems Plc 34 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 Marker 1 T1 RBW 1 88 dBm VBW 1 kHz 161 97596192 MHz SWT 150 ms Yi 1 0 Oll eee ee al MMMM 100 Center 161 9753006 MHz Span 60 kHz Center 161 975 MHz Span 60 kHz Date 29 AUG 2006 16 09 56 Date 30 AUG 2006 14 30 14 Delta 1 T1 RBW 1 kHz RF Att 20 dB 1 kHz RF Att 20 dB 7 4 17 AB VBW 1 kHz Mixer 20 dBm 1 kHz Mi
24. 11 Auxiliary ADCs The first Auxiliary ADC is dedicated to RSSI measurements at times specified by the host uC see Section 7 4 8 and User Manual 11 15 4 The second Auxiliary ADC is available for user functions The ADC runs continuously the input selected by the AuxADC Input Select bits in the C BUS Mode register C1 and the results of the conversion are presented in AuxADC Data C BUS register C9 This register also includes a bit field to indicate which input was selected when this conversion was executed The AuxADC input can be routed to either of the RxIN signals the SpareADC Input the RSSI inputs or the AuxADC inputs under host control In normal operation it is expected to be routed to one of the AuxADC Inputs 7 4 12 Auxiliary DACs The four Auxiliary DACs can be updated in any combination using the AuxDACWrite data task In addition DAC1 can be configured as a RAMDAC to output a series of values as part of the transmit timing sequence The values and the rate at which they change are set up using config mode task 7 4 13 Interrupt Operation The CMX7032 will issue an interrupt on the IRQN line when the IRQ bit bit 15 of the Status register and the IRQ Mask bit bit 15 are both set to 1 User Manual section 11 17 describes the situations which cause the IRQ bit to change from a 0 to a 1 The IRQN pin is an open collector output that requires an external pull up resistor 7 5 Operation of Tasks This section describes m
25. 32 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 7 5 5 Read Data Registers An array of four 16 bit C BUS read registers form the Read Data C BUS registers The device writes into these registers as instructed by the Data Task bits of the Command register while in receive mode The host uC can read these registers at any time except while a data task is in progress in which case the host uC should wait until the Data task complete bit is set in the Status register Data tasks access the registers as a number of words 1 to 4 or as a number of bits 1 to 16 in A7 however if a bit format Data task is used it must be the final data task issued in a multi data transfer to the host The next data task issued should be a DataWordReset or DataBitReset to re initialise the internal data buffer pointers a bit format task is usually used as the last transfer of a data block that is not a complete number of words in length Word format fe BE S A A AO e el A e a MO Bit 5 4 4 1 2 1 019 8 6 154 Se Te foo o Bt a A eS A eo Register B8 Data read from device to host uC word 3 MSB Rx first o Bt 15 14 13 12 1 Oe Or Ge re ae i sae he Tas a te Register B9 Data read from device to host uC word 4 MSB Rx first Bit format AO ERA EA AI A D A A Register A9 Data read from device to host uC bits 0 15 bit 15 received first 7 5 6 Data Tasks Data tasks are used to e Load data from the Write D
26. BSC y x B 7 00 BSC P C 0 80 1 00 i F 2 75 5 25 G 2 75 5 25 G1 0 225 4 J H 0 00 0 05 EN J 0 18 0 30 L 0 30 0 50 Top View M 0 75 P 0 50 T 0 20 Y 0 12 NOTE A amp B are reference data and do Y not include mold deflash or protrusions All dimensions in mm y Angles are in degrees Index Area 1 Index Area 2 C H y Exposed z E Se cu Metal Pad G lt 4 ZALIL al 9 M gt A Dot Dot Chamfer Index Area 1 is located directly above Index Area 2 Be tt Vi Index Area 2 ve ew 7 The underside of the package has an exposed metal pad which can be soldered to the pcb to enhance the thermal conductivity and mechanical strength of the package fixing Where advised an electrical connection to this metal pad may also be required Figure 21 Mechanical outline for 48 pad VQFN package Q3 Order as CMX7042Q3 DIM MIN TYP MAX x A 6 91 7 11 B 6 91 7 11 C 1 40 1 60 D 8 74 9 25 E 8 74 9 25 H 0 05 0 15 J 0 10 0 28 L 0 35 0 76 P 0 50 T 0 13 X 0 7 Y 11 13 NOTE A amp B are reference data and do not include mold deflash or protrusions All dimensions in mm Angles are in degrees Co Planarity of leads within 0 1mm Figure 22 Mechanical outline for 48 pin LQFP leaded package L4 Order as CMX7042L4 2006 CML Microsystems Plc 54 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 Ge gt Ini im ite Gi a palbl es Firm ASI C Maximum Fl About FirmASIC
27. BT 0 4 AIS Burst mode with full AIS frame formatting HDLC type o Bit stuffing o NRZI coding o Training sequence and start stop flag insertion o CRC generation AIS Raw mode for greater flexibility o Supports arbitrary data streams for user defined protocols Full support for the AIS Class B carrier sensing channel access scheme CS TDMA Full support for the AIS Class B Self organising TDMA access scheme 160 byte equivalent to 5 AIS slots Tx data buffer Flexible Tx Interface o Two point modulation outputs with independent gain and polarity controls o land Q modulation outputs for use with an l Q upconverter Rx Modem Functions Configurable modulation format o AIS 25kHz channel GMSK 9600bps 2 4kHz deviation BT 0 4 o DSC de emphasised FSK 1200bps Simultaneous reception of two AIS channels or one AIS and one DSC channel AlS Burst mode with full AIS frame formatting HDLC type o Frame sync recognition o Bit de stuffing o NRZI decoding o Training sequence and start stop flag detection o CRC checking AIS Raw mode for greater flexibility o Supports arbitrary data streams for user defined protocols DSC reception supported in raw mode Four 160 byte Rx data buffers can automatically store up to four 5 slot AIS bursts 2 per Rx channel Rx signal input gain and polarity controls Time of arrival reporting assists with timekeeping in the absence of GPS 100 600 MHz RF Synthesizers CMX7032 only Two Integer N synthesizers Fle
28. CMX7032 CMX7042 discards the message data If a message with no error is found the Rx1 channel state changes from Receiving to Idle causing an Rx State Alert interrupt the decoded message comprising the burst information three training sequence bytes start flag message payload CRC bytes and end flag is then copied to one of the CMX7032 CMX7042 s internal message buffers When its turn comes around to be read out it is copied to the Rx1 Data Buffer and an R1BRDY interrupt is generated At this point the host can issue Read Data tasks to read back the burst and its associated parameters Note a new message will only generate an R1BRDY interrupt when any previous message has been read out from the Rx1 Data Buffer in its entirety The Rx1 channel state will stay in d e until another RXB task is issued For any particular message the three received NRZI decoded training bytes in AIS burst mode will all be either 55 or AA depending on the configuration of the remote transmitter although the first few bits may be corrupted depending on the power up characteristics of the remote transmitter and local receiver circuits The host must read the Rx data buffers sufficiently quickly to avoid an overflow condition occurring This is only likely in a very heavily loaded AIS network The worst case would involve the reception of a 5 slot burst followed by a single slot and then a third burst in contiguous slots In this case the ho
29. Data Count register which is read whenever the RXR task is executed R1IBRDY bit will be set when the programmed number of words have been transferred The data can then be read back using Data Read tasks A new RXR task should then be executed if it is required to recover further data words It is the responsibility of the uC to perform all HDLC NRZI decoding CRC checking and end flag detection The demodulated byte stream continues even after the end of a message and in the absence of a received signal the data will then be indeterminate Reception can be halted by issuing an Abort1 task Bit ordering of the received data in AIS raw mode is the same as in Tx AIS raw mode i e the received bits are packed into words most significant bit first As the AIS message structure requires message bytes to be transmitted least significant bit first the uC must ensure that during the process of HDLC NRZI decoding that the resulting data are correctly reversed Depending on the configuration of the remote transmitter one of four different types of NRZI encoded training bytes may be received this situation arises because the AIS specification allows a transmitters NRZI encoder to start in either of its two quiescent states and the pre NRZI encoded training bytes can also be one of two different types 55 or AA Therefore for any particular message the three received training bytes in AIS raw mode will all be either 33 66 99 or CC although the firs
30. Done interrupt to be generated The associated Tx States are Tx aborted message too long This occurs if the internal message buffer is not big enough for the HDLC coded data should not happen in normal operation as the message buffer is big enough for a 5 slot message This condition requires the uC to issue a AbortTx task Tx aborted carrier sensed This occurs if the CSTDMA mechanism is enabled and the CS measurement has exceeded the CS Threshold The data is retained so that it can be re transmitted in a subsequent slot by issuing another TXB task should the host request it The slot selection should follow the rules given in the relevant international standard Tx aborted buffer not ready This occurs in burst mode if the internal data coding has not completed before the timing_start value expires 2006 CML Microsystems Plc 31 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 7 6 3 Transmit Example The following detailed example describes the process of loading and transmitting an AIS message in Burst mode Table 5 AIS Burst Transmit Example ef negro Task Reg Free Task Free bits are set 2 The host loads the first N typically 4 data words into the write data registers 0 1 The host issues a DataWordResetNTx Data Task 4 Device reads the command register amp notestasktypes 1 0 1 1 the first N data words of the data buffer The steps above may be repeated Us
31. SIClS cui AD aia r vee tio ae anu 28 130 Mead Data Regist Scania si 29 7 5 6 Data WASKS iii AA ADA A a 29 19 1 Modem Tasks and COJE Surmise cnnan N sera ace 30 FE TLPAMSIMISSION TOMA E 30 7 6 1 ERAS militas kS canaria DN RA TA AA ta 31 7 6 2 AlS Burst Mode Trans Mila A aes eee 31 7 6 3 Trans FIT XA Dl A AAA A 32 7 6 4 PAS Raw Mode Trains ieena n A A ees eee 32 7 6 5 Fransmitter TIMINI CONTO irc a A Si 32 7 6 6 Modulation Formal axes esate a L E 34 PT ECOD ON eor OA NA A 35 7 1 1 NS Burst Mode RECEIVE cia e N 35 7 7 2 AIS aw Mode RECEIVE iia odias 36 Tees SG RECEIVE ai N ene oe eles 37 2006 CML Microsystems Plc 3 D 7032 42_FI1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 7 7 4 Recone Example sn dial 38 Llao AX SVS E E pili old pilot oia 38 io Gontiguration Tasks and Odessa celia 39 A9 AF SyAamesizer GMX7032 ON listan licita 39 AlO System GIOCk Sy MIMesIZOrS uc deta 42 TiAl POWOIS Vosotros 43 Pata C BUS Register SUMMA erica dieran 44 8 Performance SpeciticalON A a 45 Sul Elecitical Peno Mancia id EE 45 8 1 1 Absolute Maximum RAtiNQS ccccooccccconnnccconnncononnnnnnnncnnonnnnnnonnnnnononnnnonnanannnnannnconanos 45 8 1 2 Operating LIM a cinco laico 45 8 1 3 Operating CNaracteriStlOs messier ea pico 46 8 1 4 Parametric Performante dario tia 50 de BUS IM ines 51 30 IMAN ei 52 TABLES Fabled Component V MES acid 12 Fable 2 BO TEN DIN States m
32. TYP MAX x A 9 00 BSC I B 9 00 BSC P C 0 80 1 00 i F 7 00 7 95 B G 7 00 7 95 4 G1 0 225 AJ H 0 00 0 05 J 0 18 0 30 L 0 30 0 50 Top View M 0 75 P 0 50 T 0 20 Y 0 12 NOTE A amp B are reference data and do not include mold deflash or protrusions All dimensions in mm G1 Angles are in degrees Index Area 1 Index Area 2 Exposed j Metal Pad G z E RRA Dot Dot Chamfer I DATAN Bo He AN Vi ANOS E L Index Area 1 is located directly above Index Area 2 Index Area 2 A The underside of the package has an exposed metal pad which can be soldered to the pcb to enhance the thermal conductivity and mechanical strength of the package fixing Where advised an electrical connection to this metal pad may also be required Figure 19 Mechanical outline for 64 pad VQFN package Q1 Order as CMX7032Q1 C gt DIM MIN TYP MAX x A 9 80 10 20 x B 9 80 10 20 C 1 40 1 60 D 11 80 12 20 E 11 80 12 20 H 0 05 0 15 J 0 17 0 27 L 0 45 0 75 P 0 50 T 0 09 0 20 X 0 qe Y 11 13 Y NOTE A amp Bare reference data and do not include mold deflash or protrusions All dimensions in mm Angles are in degrees Co Planarity of leads within 0 1mm T y e A Figure 20 Mechanical outline for 64 pin LQFP leaded package L9 Order as CMX7032L9 2006 CML Microsystems Plc 53 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 a DIM MIN TYP MAX x A 7 00
33. Vss AVDD DVpp TI T T T T Ir AVss AVss DVss DVss DVss Figure 2 CMX7032 Recommended External Components 2006 CML Microsystems Plc 10 D 7032 42 Fl1 1 2 AIS Baseband IC with without RF Synthesizer EPSI EPSCLK EPSO DVDD EPSCSN BOOTEN1 R1 BOOTEN2 DVss IRQN DVss VDEC SLOT CLOCK n c n c ri C24 T T C23 DVss DVss Rx1 Rx2 SpareADC CBUS ff C1 B a lt X1 x A E DVDD C2 O lt O 9 cla lt al lt alal a Sa Et al Z Sf 0 ziom ol alalelzlzl E Ol wn o Ole XL OlO xl x gt 48 47 46 1 2 3 4 5 6 7 8 13 14 SYSCLK1 DVss TxEnable 45 44 43 42 41 40 39 38 37 36 35 34 CMX7042L4 15 16 17 18 19 20 21 22 23 24 z al z al zix x SX Ol alz olo El 9 ait s s oj L S Sl av Fl a SS C12 AVDD CMX7032 CMX7042 DVss AUX DAC 4 AUX DAC 3 Aux AUX DAC 2 DAC AUX DAC 1 AVDD AUX ADC 2 Aux AUX ADC 1 ADC RSSI2 RSSI1 n c VBIAS C7 AVss R3 C8 AVss R4 C9 L AVSS DVD T T I I T I AVss AVss AVss DVss Figure 3 CMX7042 Recommended External Components 2006 CML Microsystems Plc 11 D 7032 42 Fl1 1 2 AVDD DVss DVss AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 Table 1 Component Values R1 100kQ C1 18pF C16 100pF C21 10nF R3 100kQ C2 18pF C17 10uF C22 10nF R4 100kQ C3 10nF C18 10nF C23 10uF R5 See note 2 C4 10uF C19 10nF C24 10nF R6 100kQ C7 10
34. ailable to the AuxADC All of these inputs are configured around an inverting op amp stage to facilitate gain and filtering adjustments In addition the Rx channel inputs are equipped with programmable gain stages for further level adjustments as required The Tx Modulation output signals may be configured to be suitable for two point modulation circuits or alternatively an Q upconverter Signal levels on both output pins MOD1 and MOD2 can be set to within 0 2dB using a Configuration Mode task 7 4 2 Operating Modes The CMX7032 operates in either o Configuration mode o Normal mode Configuration mode is used to set up various operating parameters of the CMX7032 subsystems e g Transmit format timing parameters etc following a power up or reset The modem section is disabled when the device is in Configuration mode Configuration mode uses dedicated tasks that are not valid whilst in Normal mode Normal mode is used when actively running the CMX7032 modem and other subsystems Normal mode uses dedicated tasks that are not valid whilst in Configuration mode 2006 CML Microsystems Plc 21 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 Enter config mode ECM is a Normal mode task that switches the device from Normal to Configuration mode Exit config mode EXIT CONFIG is a Configuration mode task that switches the device from Configuration to Normal mode 7 4 3 Modem and Data Units Th
35. ameters Notes Min Typ Max Unit AIS GMSK 9600bps 25kHz channel Bit rate accuracy 50 ppm BT 0 4 Storage time 1 8 bits Tx Buffer size 176 bytes Receive Parameters Notes Min Typ Max Unit AIS GMSK 9600bps 25kHz channel Bit rate accuracy 50 ppm BT 0 4 Storage time 2 8 bits Packet error rate PER limit 20 PER with 10dB co channel interference 3 20 PER with 10dB SNR 4 20 Rx Buffer Size burst mode 2 x176 bytes Rx Buffer Size raw mode 184 bytes DSC FSK 1200bps 6dB octave de emphasis Bit rate accuracy 50 ppm Sub carrier 1700 Hz Tx mark frequency 1290 1300 1310 Hz Tx space frequency 2090 2100 2110 Hz Storage time 2 TBD bits Bit error rate BER with 10dB SNR 4 1 Notes A Through GMSK FSK transmit filter 2 Through GMSK FSK receive filters 3 Measured at baseband to IEC 62287 1 4 Measured at baseband with simulated FM channel noise 2006 CML Microsystems Plc 50 D 7032 42_F11 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 8 2 C BUS Timing If 1 byte of data It 2 bytes of data CSN p xr tsu MH tC SOFF dl a AAN AA ANS cmabata 7 ejsfajsj2 1j0 7 sofsjajsfa rfo rjejsjafsjejafo tLoz e tuz e al tz el a ReplyData Hi z ljrjsjsjafsfajrfo jefslafafaj1 foj Level not important or undefined CK 70 Vdd 30 Vd
36. ata registers into Data Buffers while in normal or configuration modes e Load data from Data Buffers into the Read Data registers while in normal mode e Read write or operate subsystems by passing data using the Write Data and Read Data registers Table 3 Data Tasks Name SIS Desin NULL Null system task takes no action e Copy N words 1 to 4 from Rx1 data buffer to C BUS Read Data registers e Increment Rx1 data buffer pointer e Copy N words 1 to 4 from Rx2 data buffer to C BUS Read Data registers e Increment Rx2 data buffer pointer e Copy N words 1 to 4 from Write Data registers to Tx data buffer e Increment data buffer pointer e Reset Rx1 data buffer pointer to the top e Copy N words 1 to 4 from Rx1 data buffer to Read Data registers e Increment data buffer pointer e Reset Rx2 data buffer pointer e Copy N words 1 to 4 from Rx2 data buffer to Read Data registers e Increment data buffer pointer DataWordResetNTx e Reset Tx data buffer pointer e Copy N words 1 to 4 from Write Data registers to Tx data buffer e Increment the data buffer pointer e Copy N bits 1 to 15 from Rx1 data buffer to Read Data register 0 e Increment the data buffer pointer e Copy N bits 1 to 15 from Rx2 data buffer to Read Data register O e Increment data buffer pointer DataBitWriteNTx e Copy N bits 1 to 15 from Write Data register O to Tx data buffer e Increment data buffer pointer 2006 CML Microsystems Plc
37. d t SCIk RDH ReplyData Figure 17 C BUS Timing CmdData C BUS Timing Notes Min Typ Max Unit tese CSN Enable to SCIk high time 100 ns tesH Last SCIk high to CSN high time 100 ns tLoz SCIk low to ReplyData Output Enable 0 0 ns Time tHiz CSN high to ReplyData high impedance 1 0 us tesorr CSN high time between transactions 1 0 Us txt Inter byte time 200 ns tek SCIk cycle time 200 ns ten SCIk high time 100 ns teL SCIk low time 100 ns teps Command Data setup time 75 ns tcoH Command Data hold time 25 ns tros Reply Data setup time 50 ns tao Reply Data hold time 0 ns Notes 1 Depending on the command 1 or 2 bytes of COMMAND DATA are transmitted to the peripheral MSB Bit 7 first LSB Bit 0 last REPLY DATA is read from the peripheral MSB Bit 7 first LSB Bit 0 last 2 Data is clocked into the peripheral on the rising SerialCLK edge 3 Commands are acted upon at the end of each command rising edge of CSN 4 To allow for differing uC serial interface formats C BUS compatible ICs are able to work with SerialCLK pulses starting and ending at either polarity 5 Maximum 30pF load on IRQN pin and each C BUS interface line These timings are for the latest version of C BUS and allow faster transfers than the original C BUS timing specification The CMX7032 can be used in conjunction with devices that comply with the slower
38. d Tamb 25 C With respect to the signal at the feedback pin of the selected input port With the output driving a 20kQ load to AVpp 2 Denotes output impedance of the driver of the auxiliary input signal to ensure lt 1 bit additional error under nominal conditions Guaranteed monotonic with no missing codes Sine wave or clipped sine wave Separate dividers provided for each PLL External ISET resistor R31 0Q Internal ISET resistor 9k6Q nominally For optimum performance of the synthesizer subsystems a common master clock should be used for the RF Synthesizers and the baseband sections Using unsynchronised clocks is likely to result in spurious products being generated in the synthesizer outputs and in some cases difficulty may be experienced in obtaining lock in the RF Synthesizers 2006 CML Microsystems Plc 49 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 8 1 4 Parametric Performance For the following conditions unless otherwise specified External components as recommended in Figure 2 Maximum load on digital outputs 30pF CLK Frequency 19 2MHz 20ppm Tamb 40 C to 85 C AVpp DVpp CPVpp 3 0V to 3 6V RFVDD 2 25V to 2 75V Reference Signal Level 300mV pk pk with AVpp 3 3V Signal levels track with supply voltage so scale accordingly Signal to Noise Ratio SNR in bit rate bandwidth Input stage gain 0dB Output stage attenuation OdB Transmit Par
39. de where it spends most of its time asleep but wakes up at the start of each AIS slot and receives for long enough to determine whether a burst is present or not If no burst is received the CMX7032 will make a pair of RSSI measurements and then go back to sleep This power saving operation can be turned on and off using the Sleep Mode En bit in the Mode register C1 The CMX7032 will still respond to C BUS accesses when asleep but the latency between a task being issued and completed may be longer than normal The times to perform RSSI measurements go to sleep and wake up are configured by the host and all times are referenced to the SlotCLK signal The host should ensure that these timings result in the CMX7032 being awake in time to sample the next SlotCLK signal The timings are set up using the Sleep Timing Config task See User Manual section 11 15 8 for details If Sleep mode is not enabled then the demodulator will run continuously and update the Rx Data buffer whenever valid data is received 2006 CML Microsystems Plc 23 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 Rx Timing Received Burst X X O O O O YW 0 a Time Wait Training RSSI sequence Sleep if no burst received Measurement search Wake up in time for next slotclock Figure 10 Rx Burst Timing 7 4 8 CSTDMA Threshold Measurement The CMX7032 provides support for the CSTDMA mode of
40. e The loop filter components should be placed close to the VCO TXN RXN RF in detect Ref BEI le Divide by N counter CP supply CP out RF synthesiser clock o Divide by R counter set 1 XR Internal Clock T RX Figure 15 Single RF Channel Block Diagram The two RF synthesizers are programmable to any frequency in the range 100MHz to 600MHZ Figure 15 is a block diagram of one synthesizer channel The RF synthesizer clock is the same 9 6MHz or 19 2MHz clock as is used by the baseband circuitry The RF synthesizer clock is common to both channels The charge pump supply CP supply CPVpp is also common to both channels The RF in pins CPout Iset and RFVss pins are channel specific and designated as either RF1 RF1 CP1OUT ISET1 RFVSS or RF2 RF2 CP2OUT ISET2 RFVSS on the Signal List in section 3 The N and R values for Tx and Rx modes are channel specific and can be set from the host uC via the C BUS Various channel specific status signals are also accessible via C BUS The divide by N counter is 20 bits the R counter is 13 bits Typical external components are shown in Figure 14 Both synthesizers are phase locked loops PLLs of the same design utilising external VCOs and loop filters The VCOs need to have good phase noise performance although it is likely that the high division ratios used will result in the dominant noise source being the reference oscillator The phase detectors are of the phase frequency ty
41. e CMX7032 is logically divided into two main units which can accept and perform tasks separately o Modem Unit o Data Unit The Modem Unit is primarily responsible for processing Tx data from the internal Tx data buffer and presenting it on the MOD1 and MOD2 pins and processing the Rx input signals to recover the Rx data they represent and storing that data in the internal Rx data buffers The Data Unit is primarily responsible for transferring data between the internal data buffers or subsystems and the C BUS registers from where they can be accessed by the host uC When the device is in Normal mode the Command Register C8 is a 16 bit C BUS write register that contains task fields for both Data and Modem units A task is invoked by writing its code into the Data Task or Modem Task fields A single C BUS write transaction will change all Command Register fields Often the host will only want to issue either a Data or Modem task in which case it should ensure that the other task field is set to all zeroes corresponding to a null idle task Sometimes it is useful to issue Data and Modem tasks simultaneously in which case the Data task will always be completed before the Modem task is started Certain internal subsystems can be directly accessed and controlled via C BUS transactions without issuing a specific task command 7 4 4 Timing and Synchronisation An AIS transponder must keep track of both the current AIS slot number and the
42. e external clock source or 9 6MHz Xtal 19 2MHz input from the external clock source or 9 6MHz Xtal the external clock source or 9 6MHz Xtal XTALN The output of the on chip 9 6MHz Xtal oscillator inverter NC if 19 2MHz Clock used DVdd Digital 3 3V supply rail This pin should be decoupled to DVss by capacitors mounted close to the device pins oa joa COMMAND DATA C BUS Serial data input from the uC 2006 CML Microsystems Plc 8 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 Description C BUS A 3 state C BUS serial data output to the uC This output is high impedance when not sending data to the uC ee ee ee A ee PWR Digital Ground eT OO a E SYS CLK 2 OP Synthesized Digital System Clock Output 2 IP C BUS The C BUS chip select input from the uC A nes e ome se 1 EPS OP EEPROM Serial Interface SPI bus Output ss 2 ErsciK OP EEPROM Serial Interface SPI bus Clock ee enone ee ee EPSCSN OP EEPROM Serial Interface SPI bus Chip Select Serial Interface SPI bus EEPROM Serial Interface SPI bus Chip Select Select BOOTENT IP PD AG in conjunction with BOOTENZ2 to determine the operation of the bootstrap program BOOTEN IP PD Used in conjunction with BOOTEN1 to determine the operation of the bootstrap program Notes Exposed metal pad on the bottom of a VAFN package should not be connected IP Input PU PD internal pullup pulldown re
43. ed as one of the first four words of the Data Block This will give the time measured in 24kHz ticks between the rising edge of the last SlotCLK and the detection of the last bit of the start flag of the burst Tsync in ITU M 1371 1 7 4 6 Tx Timing The CMX7032 can be configured to perform a sequence of events when a TXB or TDBS task transmit burst is issued The events are start and end of modulation ramping the RAMDAC up and down asserting and releasing a digital output pin intended as a Tx Enable and CSTDMA sensing Each of 2006 CML Microsystems Plc 22 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 these can be configured to happen with specified delays from the rising edge of the SlotCLK The timings are set up with the config mode task Tx_Sequence See User Manual section 11 15 7 for details Tx Timing PA Ramp amp Modulation slot clock slot clock Tx Enable Time gt CS TDMA wall Sensing Figure 9 Tx Burst Timing If CSTDMA sensing has been enabled then the CMX7032 will measure the carrier level RSSI on the selected channel during the window specified in the transmit timing table If the user specified threshold is exceeded then the subsequent events RAMDAC Tx Enable and modulation will be cancelled The threshold is set using the CS_Threshold register C2 See User Manual section 11 12 for details 7 4 7 Rx Timing The CMX7032 has a power saving mo
44. ee pe LS SL delay in the Tx filters so that modulated data appears at the end of the RAMDAC ramp_up period tick 57 CSTDMA_END th Insert 10 tick delay then stop CSTDMA monitoring Assert the TxEnable line assuming not aborted Insert 3 tick delay then initiate the RAMDAC ramp up for RAMDACUE AIS the transmitted signal will be carrier only at this point At this point during a transmission the CMX7032 CMX7042 feeds the entire message to the transmit modulator bit by bit All subsequent transmit events are timed relative to the end of the last message bit indicated by the MODULATE_END event The 0 delay defines this reference point as the same as MODULATE_END the output of the final data bit to the RF circuits B in Figure 13 RAMDAC DOWN 7 0 o Initiate the RAMDAC ramp down immediately TX OFF Insert 7 tick delay to allow RAMDAC to fully ramp down e then release the TxEnable line Notes 1 Itis essential that the CSTDMA and MODULATE START events precede their associated END events otherwise undesirable results will be obtained 2 MODULATE_START must appear in the first group of timed events table entries 1 5 MODULATE_END must appear in the final group table entries 6 8 3 Itis feasible to place the RAMDAC_DOWN task before the MODULATE_END task if it is desired to continue modulation during the Ramp down period Assuming that the timing_start value has been set to 10 see User Manual section
45. eeeeeoeessseeeeeeeeeooesseeeeseeooeenees 10 5 PCB Layout Guidelines and Power Supply Decoupling cccoononconcncnnnccnnonanncnoncnnnnananannonnnnnnaaaas 13 6 General DESCTIDUO M ie as 15 AA a UE le Data aad fet UI nS at a 15 G22 ASS SIEM Oma aaa E aad as ia ees 16 7 Detailed Descrip Sitio 17 Pale OCK SUIS A AA A AAA NE 17 Tae A A A coma a tain naa saath voeee sist ous a a N 17 fa Funcion Image Load and ACUVA MO Misas A A E NE 19 7 3 1 FINLoadding trom Fost CONTO li tt da 19 7 3 2 Fi Loading Tom EE PROM orcs tsar eens AE E 20 FA SySiem Description and ASKS ic IA cesses essence ee ee 21 7 4 1 Signal QUIN A acai n a a e a 21 7 4 2 Operating Mode Serres n a a sean 21 7 4 3 Modem and Data UNIS Ei aSas 22 7 4 4 Timingand Syn CMON Salerni ae a N e aa 22 7 4 5 TMSA REPONN G cr A okie sins eee coins 22 7 4 6 A E E A 22 7 4 7 A cscs ste eel pentane cial sas N caps vei ae cassie acts Ae E E eee 23 7 4 8 CSTDMA Threshold Measurement ccccccecsssssseeeceeeesaeeseeceeeeeseeaeaeeeeeeeeessaaseeeeeeees 24 7 4 9 RSob Measurement acesi nna a a st A A 24 LATO ASS ECM aU a A A a ee 25 Td AMA ADOS A I e o 25 TAA AMA DASS ui tees a E e a aretoc A 25 TANS AMerup Opera Os A oss it 25 fa ODEON OF TASKS iu A AR A ee 25 7 5 1 Das Opera A St 26 13 2 FAX Task Operas A Ss 27 103 Registers and Buffers for Tx Rx T SkS ccccccscccccssseecceeseeecseseeeceesecesseeessasseessaaeees 28 7 5 4 Wit Dala IRCOI
46. equired They are independent sets of registers one of which is selected to command each PLL by changing the settings in the RF Channel Control register B3 For optimum performance a common master clock should be used for the RF synthesizers RF Clock and the baseband sections Main and Auxiliary System Clocks Using unsynchronised clocks can result in spurious products being generated in the synthesizer output and in some cases difficulty may be experienced with obtaining lock in the RF synthesizers Lock Status The lock status can be observed by reading the RF Channel Status register B4 and the individual lock status bits can subject to masking provide a C BUS interrupt The lock detector can use a tolerance of one cycle or four cycles of the reference clock not the divided version that is used as a Comparison frequency in order to judge phase lock An internal shift register holds the last three lock status measurements and the lock status bits are flagged according to a majority vote of these previous three states Hence one occasional lock error will not flag a lock fail At least two successive phase lock events are required for the lock status to be true Note that the lock status bits confirm phase lock to the measured tolerance and not frequency lock The synthesizer may take more time to confirm phase lock with the lock status bits than the time to switch from channel to channel The purpose of a 4 cycle tolerance is for the case
47. er C5 2 the Fl version code is reported in C BUS register C9 3 the two 32 bit Fl checksums are reported in C BUS register pairs A9 AA and B8 B9 4 the device waits for the host to load the 32 bit Device Activation Code to C BUS register C8 5 once activated the device initialises fully enters idle mode and becomes ready for use The checksums can be verified against the published values to ensure that the Fl has loaded correctly Once the FI has been activated the checksum product identification and version code registers are cleared and these values are no longer available If an invalid activation code is loaded the device will report the value DEAD in register A9 and become unresponsive to all further host commands including General Reset Both the Device Activation Code and the checksum values are available from the CML website Table 2 BOOTEN pin states BOOTEN2 BOOTEN1 C BUS Host load AAA E reserved TT EEPROM load O E No FI load O A 3 Note In the rare event that a General Reset needs to be issued without the requirement to re load the FI the BOOTEN pins must both be cleared to 0 before issuing the Reset command The Checksum values will be reported and the Device Activation code will need to be sent in a similar manner as that shown in Figure 8 There will not be any FI loading delay This assumes that a valid FI has been previously loaded and that Vdd has been maintained throughout the reset to preserve
48. erting input NES Rx1FB OP Rx1 input amplifier feedback NE Rx2IN IP Rx2 inverting input a 19 Rx2FB OP Rx2 input amplifier feedback 28 2 SpareADCFB OP Spare ADC input amplifier feedback NES SpareADCIN NN Spare ADC inverting input 30 22 AVss PWR Analog Ground 3 23 MODI OP Modulator 1 output 32 a MOD2 OOP Modulator 2 output Internally generated bias voltage of about AVdd 2 except when the device is in Powersave mode when VBIAS will VIAS discharge to AVss Must be decoupled to AVss by a capacitor mounted close to the device pins No other connections allowed Ca E ECETIA C a asen ie areca RSS input rom Unter Osoininaer asse ie areo RSS inout rom ner Disoiminaore Co e aoo e foero AUXADC2 Auxiliary ADC input 2 Analog 3 3V supply rail Levels and thresholds within the AVdd device are proportional to this voltage This pin should be decoupled to AVss by capacitors mounted close to the device pins so 3 Auxpact OP auxilayDACoutputi RAMDAC pat 3 auxmacz OP Auxiliary DAC output S e a as PWR Analog Groond a AuxDacs OP Auxiliary DAC output _ EE pos Par Dys PWR Dota Ground O Internally generated 2 5V supply voltage Must be decoupled to DVss by capacitors mounted close to the device pins No VDEC other connections allowed except for the optional connection oh RF Vdd XTAL XTAL CLOCK IP 19 2MHz 19 2MHz input from th
49. ftware routine The number of data bytes following an A C byte is dependent on the value of the A C byte The most significant bit of the address or data is sent first For detailed timings see section 8 2 2006 CML Microsystems Plc 17 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 C BUS Write CSN 2 SeiaCLK tT LC LE LU UU UU ee EU LU Ee LEU Cmd_data 716 5 4 3 2 1 0 MN 7 6 0o M7 fo IO SB LSB MSB See Note 1 See Note 2 M LSB MSB LSB Address Command byte Upper 8 bits Lower 8 bits Reply_data High Z state C BUS Read See Note 2 CSN NI EE SeiaCLK SUD UU Un ULE Ue Cmd_data 7 1 6 5 4 3 2 1 0 MSB LSB Address byte Upper 8 bits Lower 8 bits Reply data _________ _ 7 6 Jo 7 High Z state MSB LSB MSB LSB __ Data value unimportant _ Repeated cycles __ Either logic level valid Figure 6 C BUS Transactions 1 For Command byte transfers only the first 8 bits are transferred 2 For single byte data transfers only the first 8 bits of the data are transferred 3 The Cmd_data and Reply data lines are never active at the same time The Address byte determines the data direction for each C BUS transfer 4 The SerialCLK input can be high or low at the start and end of each C BUS transaction 5 The gaps shown between each byte on the Cmd_data and Reply_data lines in the above diagram are optional the host may insert gaps or concatenate the data as requi
50. hecksum values in A9 AA and B8 B9 note BOOTEN1 and Send Device Activation Code hi to C8 BOOTEN2 may be changed at this point if required y Wait for C BUS C6 bit 0 to be set to 1 at Vdd e Send Device Activation Code lo to C8 Jumper for programming Wait for C BUS C6 bit O to be set to 1 BOOTEN1 i EEPROM y if required CMX7032 is now ready for use BOOTENZ paa Figure 8 FI Loading from EEPROM The CMX7032 has been designed to function with Atmel AT25HP512 EEPROM devices however other manufacturers parts may also be suitable The time taken to load the FI is dependant on the clock Xtal source frequency but should be less than 500ms 7 4 System Description and Tasks This section describes the operation of main sections of the CMX7032 and the task oriented logical interface provided to the external host device 7 4 1 Signal Routing The CMX7032 provides processing capability for two simultaneous receive channels either two AIS or one AIS and one DSC or one Tx channel AIS The inputs to the two receiver channels are nominally allocated to the Rx1IN and Rx2IN pins of the device however they can be re allocated by the user by use of the Input Signal Routing C BUS register B1 The SpareADCIN pin can also be used as an input to the receivers if required By default the device will route Rx1IN to Rx channel 1 and Rx2IN to Rx channel 2 which leaves the SpareADCIN signal av
51. hesizers Two System Clock outputs SysCLK1and SysCLk2 are available to drive additional circuits as required These are digital phase locked loop PLL clocks that can be programmed via the System Clock registers with suitable values chosen by the user The System Clock PLL Configure registers SAB and AD control the values of the VCO Output divider and Main Divide registers while the System Clock Ref Configuration registers SAC and AE control the values of the Reference Divider and signal routing configurations The PLLs are designed for a reference frequency of 96kHz The System Clock output divider stages are designed so that it has an 1 1 Mark to Space ratio when an even divide number is selected 2006 CML Microsystems Plc 42 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 to RF Synthesiser Ref CLK selection SysCLK1 VCO LPF VCO 24 576 98 304MHz 49 152MHz typ Ref CLK div PLL div 1 to 512 1 to 1024 4 AC b0 8 SysCLK1 SysCLK1 AB b0 9 Ref Div 48 192kHz 96kKHz typ VCO op div os 1 to 64 o SysCLK1 AB b10 15 SysCLK1 Pre CLK Output AC b11 15 384kHz 50MHz SysCLK2 VCO VCO 24 576 98 304MHz 49 152MHz typ Ref CLK div PLL div 1 to 512 1 to 1024 4 AE b0 8 SysCLK2 SysCLK2 AD b0 9 Ref as 192kHz PY 96kHz typ VCO op div Pore 1 to 64
52. iance with this product specification Specific testing of all circuit parameters is not necessarily performed For FAQs see www cmlmicro com products fags For a full data sheet listing see www cmlmicro com products datasheets download htm For detailed application notes www cmlmicro com products applications MICML Microcircuits CML Microcircuits CML Microcircuits UK Ltd USA Inc Singapore Pte Ltd G SOMMUNIC ATION SEMICONDUCTORS COMMUNICATION SEMICONDUCTORS COMMUNICATION SEMICONDUCTORS Oval Park Langford 4800 Bethania Station Road No 2 Kallang Pudding No 218 Tian Mu Road Maldon Essex Winston Salem Road 09 05 06 Mactech West Tower 1 Unit 1008 CM9 6WG England NC 27105 USA Industrial Building Shanghai Kerry Everbright Singapore 349307 City Zhabei Shanghai 200070 China Tel 44 0 1621 875500 Tel 1 336 744 5050 Tel 65 6745 0426 Tel 86 21 6317 4107 800 638 5577 86 21 6317 8916 Fax 44 0 1621 875600 Fax 1 336 744 5054 Fax 65 6745 2917 Fax 86 21 6317 0243 Sales Sales Sales Sales sales Ocmlmicro com us sales cmlmicro com sg sales cmlmicro com cn sales cmlmicro com cn Technical Support Technical Support Technical Support Technical Support techsupport cmlmicro com us techsupport cmlmicro com sg techsupport cmlmicro com gg techsupport cmlmicro com 2006 CML Microsystems Plc 55 D 7032 42 FI1 1 2
53. ing DataWordWriteN tasks to load many words until the data buffer contains enough data to carry out the desired modem task 7 The host writes a TXB task to the command register to start the Tx process 0 When the transmit point arrives SlotCLK the Tx State changes to Tx in progress and the TxSequence is activated 11 The Tx Modem Buffer will gradually empty as the Tx Modulator continues transmitting 2 When the transmission ends the TxDone bit in the Status register will be set generating an interrupt if enabled The host should then check the Tx state bits in the Status2 register to see if transmission was successful Note that if CSTDMA mode is active and a carrier is sensed in the selected channel at the beginning of the requested transmit slot the transmission is aborted Tx State changes to Tx aborted carrier sensed this causes a TxDone interrupt to be generated however the data in the Tx Data Buffer is retained so the uC can choose to issue an AbortTx task and clear the Tx Data Buffer or reschedule the transmission in another slot 7 6 4 AIS Raw Mode Transmit In AIS raw mode transmit data is passed directly from the Tx Data Buffer to the GMSK modulator The uC must calculate the entire transmitted message including the training sequence HDLC processing start stop flags bit stuffing and CRC insertion and NRZI coding Note In AIS raw mode data words written to the CMX7032 are transmitted most significant bi
54. lator 716 1817 88 words y Data Task Complete TBFree C TxState D TxDone Figure 11 Tx Task Operation 2006 CML Microsystems Plc 26 D 7032 42_F11 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 7 5 2 Rx Task Operation Typical stages of Rx task operation are depicted in Figure 12 and occur as follows 1 A Modem task instructs the CMX7032 to transfer data from the Rx1 2 Modem to the Rx1 2 Data Buffer 2 The host writes the Command register specifying a Data task This results in transfer of up to 4 words from the Rx1 2 Data Buffer into the Read Data C BUS registers from where it can be read by the host uC 3 Steps 2 can be repeated with host uC reads of the Read Data registers to transfer a large block of data from the Rx1 2 Data Buffer to the host uC 4 Once the system is up and running any modem task may take some time to execute as it will need to wait for the data to be available from the modem Command Register Command Reg Free Data Task Modem Task Rx Data Buffer 88 words D demodulator Rx Data C Bus Buffer registers 88 words BIA 8 A RxState o gt E D Q r Rx Data Buffer 88 words demodulator Data Task Complete Rx Data Buffer 88 words Figure 12 Rx Task Operation 2006 CML Microsystems Plc 27 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 7 5 3 Registers
55. liary gt SYS CLK 1 SlotCLK gt purpose l O system clocks DAC 1 TH Aux DAC 1 di prone C DAC2 lt Aux DAC 2 o RF 1 P 1 Auxiliary Synthesiser lt DAC3 lt Aux DAC 3 DACs 1 gt Out CP1 E RF Synthesisers H Set 1 DAC4 Aux DAC 4 CMX7032 only ERA C Internal Signal is A gt Out CP2 RSSI 1 TE C ISet2 RSSI 2 TE Auxiliary C RFVdd AuxADC 105 multiplexed lt C CPVdd E ADCs CJ RFVss AuxADC 2L_ gt C_ RF Cik System Control Main Registers na EPSI gt Digital C gt Reply Data epscik dy EEPROM ds A cas SPI port EPCSN lt _ _ Serial Cik Boot Crystal Internal systems m Control oscillator control AVdd VBias AVss DVdd _ gt VDec DVss lt gt Boot En1 Boot En2 Clk Xtal L__ gt XtalN Figure 1 CMX7032 CMX7042 Block Diagram 2006 CML Microsystems Plc 6 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 3 Signal List CMX7032 CMX7042 Sianal i pi 9 Type Description Name C BUS A wire ORable output for connection to the Interrupt IRON Request input of the host Pulled down to VSS D when active and is high impedance when inactive An external pull up resistor R1 is required RF1 RF o 1 Negative Input A Ce E ees EA rr o roca pom pa O M ene sonar Pump ourensano The 2 5V positive supply rail for the RF synthesizers This RFVdd PWR should be decoupled to RFVss by a capacitor mounted close t
56. n DVss 40 uA C BUS Interface and Logic Inputs Input Logic 1 10 DVpp Input Logic O 30 DVpp Input Leakage Current Logic 1 or 0 1 0 1 0 uA Input Capacitance O O za 2006 CML Microsystems Plc 46 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer DC Parameters Notes C BUS Interface and Logic Outputs Output Logic 1 lop 120A Output Logic 1 loy 1mA Output Logic 0 lo 360uA Output Logic 0 lo 1 5mA Off State Leakage Current IRQN Vout DVpp REPLY_DATA output HiZ VBIAS 26 Output voltage offset wrt AVpp 2 lo lt 1A Output impedance AC Parameters Notes CLK Input High pulse width 31 Low pulse width 31 Input impedance at 19 2MHz Powered up Resistance Capacitance Powered down Resistance Capacitance Clock frequency Clock stability accuracy Clock start up from powersave VBIAS Start up time from powersave RxIN SpareADC input Input impedance 34 Input signal range 35 Input signal envelope Load resistance feedback pins Amplifier open loop voltage gain __ P 1mVrmsat100Hz J Unity gain bandwidth Programmable Input Gain Stage 36 Gain at OdB 37 Cumulative Gain Error wrt attenuation at 0dB J 37 Modulator Outputs MOD 1 MOD 2 Power up to output stable 41 Modulator Attenuators Attenuation at OdB 43 Cumulative Attenuation Error wrt attenuation at OdB J Output Impeda
57. n appropriate Data Task The first four words of the buffer contain the burst information Word1 A9 Burst length in bytes Word2 AA Time of arrival measured in 24kHz ticks from the SlotCLK Word3 B8 Value proportional to DC offset of Rx Input Word4 B9 reserved Note RXB tasks can only be issued when the Rx Raw bit is cleared to 0 e RxR1 2 Receive N Raw words on Rx1 Rx2 This causes the specified Rx channel to wait for a good training sequence and start flag then demodulate and store N words in its Data buffer N is specified in the Rx data count register Burst information is NOT recorded in Raw mode so there are an additional 4 words available in the Data Buffer compared with Burst mode operation Note RxR tasks can only be issued when the Rx Raw mode bit is set to 1 2006 CML Microsystems Plc 38 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 7 8 Configuration Tasks and Codes The device executes Configuration Tasks while in configuration mode See section 7 4 2 for a description of device operating modes and how to change between them and User Manual section 11 15 for more details on a particular task These tasks and their data are used to configure device subsystems Data required for the Config task is loaded into the device using a Data Task which can be executed at the same time as the Config task if it requires less than four words Table 10 C
58. nce Enabled 42 J Disabled 42 Output current range AVpp 3 3V Output voltage range 44 Load resistance Auxiliary Signal Inputs Aux ADC 1 to 4 Source Output Impedance 51 2006 CML Microsystems Plc 47 Min 19 19 125 CMX7032 CMX7042 Typ Max Unit 5 DVop DVop 10 DVpp 15 DVpp 10 uA 1 0 uA 1 0 uA 2 AVpp 22 kQ Typ Max Unit ns ns 150 kQ 20 pF 300 kQ 20 pF 19 2 MHz 20 ppm 400 ms 30 ms 1 MQ 90 VDD 2 2 Vp p kQ 60 dB 1 0 MHz 0 0 5 dB 0 1 0 dB 50 100 us 0 1 0 dB 0 0 6 dB 600 Q 500 kQ 125 uA AVop 0 5 V kQ 24 kQ D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer AC Parameters Notes Auxiliary 10 Bit ADCs Resolution Input Range Conversion time Input impedance Resistance Capacitance Zero error input offset to give ADC output 0 J Integral Non linearity Differential Non linearity 93 Auxiliary 10 Bit DACs Resolution Settling time to 0 5 LSB Output Range Output Impedance Integral Non linearity Differential Non linearity 93 Resistive load Noise output voltage in 30kHz bandwidth RF Synthesizer Phase Locked Loops CMX7032 only Reference Clock Input Frequency Level 61 Divide ratios R 62 RF Synthesizer Comparison frequency 64 Input frequency range Input level Divide ratios N Phase Noise Floor Charge pump current high
59. nent Values as per Table 1 It is important to protect the analog pins from extraneous inband noise and to minimise the impedance between the CMX7032 and the supply and bias de coupling capacitors The supply decoupling capacitors should be as close as possible to the CMX7032 It is therefore recommended that the printed circuit board is laid out with separate ground planes for the AVss RFVss and DVss supplies in the area of the CMX7032 with provision to make links between them close to the CMX7032 Use of a multi layer printed circuit board will facilitate the provision of ground planes on separate layers It is recommended that no connection be made to the central metal pad on Q1 Q3 VQFN packages Veias IS used as an internal reference for detecting and generating the various analog signals It must be carefully decoupled to ensure its integrity so apart from the decoupling capacitor shown no other loads should be connected If Veas needs to be used to set the discriminator mid point reference it must be buffered with an external high input impedance buffer The 2 5V Vpec output can be used to supply the 2 5V RFVpp to remove the need for an external 2 5V regulated supply Vpec can be directly connected to RFVpp 2006 CML Microsystems Plc 14 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 6 General Description 6 1 Overview Tx Modem Functions AIS 25kHz channel GMSK 9600bps 2 4kHz deviation
60. o the device pins 10 RFVss PWR The negative supply rail ground for the 2nd RF synthesizer e e CP20UT OP 2nd Charge Pump output wae ISET2 NN 2nd Charge Pump Current Set input The 3 3V positive supply rail for the RF charge pumps This CHARGE PUMP PWR should be decoupled to RFVss by a capacitor mounted close to the device pins a oe RF CLOCK Ka RF Clock Input common to both synthesizers CINE o e Reserved do not connect this pin ar pp no Reserved do not connect this pin Internally generated 2 5V digital supply voltage Must be decoupled to DVss by capacitors mounted close to the VDEC device pins No other connections allowed except for optional connection to RFVdd o o sorak e socors orsa O seres rorcomeawispn ane sere notoomect en a n ssaki or Synneszed Dita Sytem Cock ouput Ca u ows m poaceae ooo Ca o oo e peaa TxEnable OP Enable for external Tx hardware 1 To minimise crosstalk this signal should be connected to the same clock source as XTAL CLOCK input By default this is connected internally at power on alternatively this may be achieved by connecting the pin to the XTALN output when a 19 2MHz source is in use 2006 CML Microsystems Plc 7 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 CMX7032 CMX7042 Signal i i g Type Description Name oa 6 Rx1IN RA inverting input er inverting input inv
61. odem and data tasks Understanding their operation requires knowledge of the internal buffering of the CMX7032 Tx and Rx data is double buffered Each Tx or Rx channel has a Data Buffer The host uC accesses the C BUS registers and the modulator demodulator directly accesses the Data Buffers Tasks transfer data between the buffers and the C BUS registers 2006 CML Microsystems Plc 25 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 7 5 1 Tx Task Operation Typical stages of Tx task operation are depicted in Figure 11 and occur as follows 1 2 3 The host writes up to 4 words of data for transmission into the Write Data C BUS registers The host writes the Command register specifying a data task This results in transfer of the data from the Write Data registers into the Tx Data Buffer Steps 1 and 2 can be repeated to load the Tx Data Buffer with a large block of data A Modem task can then be used to instruct the Tx Modulate pump to transmit the data in the Data Buffer This causes the content of the Tx Data Buffer to be coded and CRC d if in burst mode and transmitted to the MOD1 and MOD2 output pins Once the system is up and running any modem task may potentially take some time to execute as it may have to wait for the previous task to complete Command Register Modem Task Command Reg Free Data Task C Bus registers BBAA y gt Tx Data Buffer modu
62. onfiguration Tasks Config Task description Section PNULL Dornothing IO Se Ea een Nene ism aa POS RSSL_ window Sets RSSI window timing and length 15 Reserved Reseved Tf S Reseved o S O Reseved O 7 9 RF Synthesizer CMX7032 only The CMX7032 includes two Integer N RF synthesizers each comprising a divider phase comparator and charge pump The divider has two sets of N and R registers one set can be used for transmit and the other for receive The division ratios can be set up in advance by means of C BUS registers Then a single C BUS command will change over from the transmit to the receive division ratios or vice versa enabling a fast turnaround External RF components are needed to complete the synthesizer circuit A typical schematic for one synthesizer with external components is shown in Figure 14 to Mixer RFVop CPVpp 50 ohm CPOUT CHARGE PUMP ISET R31 RFV 55 RFV 55 Figure 14 Example RF Synthesizer Components 2006 CML Microsystems Plc 39 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 R31 00 C31 820pF R32 18kO C32 8 2nF R33 18kO C33 680pF C34 1nF C35 1nF Resistors 5 capacitors and inductors 20 unless otherwise stated Note R31 is chosen within the range OQ to 30kQ and selects the nominal charge pump current It is recommended that C34 and C35 are kept close to the VCO and that the stub from the VCO to the CMX7032 is kept as short as possibl
63. onolito dis 19 Table 3 Data TASKS stasis ii i 29 Elo AS e 30 Tables AlS Burst rans mit Example rss dseita 32 Table 6 TX SCGQUCHCS A e et 33 Table 7 Example Tx Event Sequence Setup errr nne N N ANE 34 Table g TxXSPECcIUM Mask Si id 35 Table 9 AIS Burst Receive Example a 38 Fable tO Gontiquration Task taa 39 Table 11 C BUS TegisterS coccion dada decian dianas 44 FIGURES Figure 1 CMX7032 CMX7042 Block Diagram occcccccoccccnncccccccooonccnnnnnnnononanccnnnnnnononnnnnnnnnnnnnnnannnnnnnnnnnnnnnnnns 6 Figure 2 CMX7032 Recommended External Components ooooocncnnnncccccccnnncnnnnnnnnnnnnnncnnnnnononannnnnnnnnonononans 10 Figure 3 CMX7042 Recommended External Components ccoooooccccnnncccncnnnocccnnncnnnonnnnncnonnnnnonnnncnonnnnnnonnnaos 11 Figure 4 CMX7032 Power Supply Connections and De COUPlINQ ooooocccnnnccccccconnccnnnoconononanccnnnonononans ES Figure 5 CMX7042 Power Supply Connections and De COUPliNQ ooooccccnnnccccnononnccnnnnnnnononancnnnnnnnnnnans 14 Figur e 6 C BUS Trans acon tati acid 18 Foure 7 Filkoading Tom THOS iaa A e atebaahal Vadis 20 Figures Fl Loading from EE PRO Misas ada dida d bis 21 Figure 9 Tx B rst TIM iia ii adi 23 Elgure 10 Ex Burst MAINA sad 24 Figures dh TX Task Oper lO senere decos rlas 26 Figure T2 RX Task Noi 27 Figure 13 Typical AlS Transmission AA ee 33 2006 CML Microsystems Plc 4 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042
64. ors MET dl CMX7042 E Auxiliary Dual la ee Section e 2006 CML Microsystems Plc Generator Sample Timer Interrupt AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 1 Brief Description A highly integrated Baseband Signalling Processor IC the CMX7032 CMX7042 fulfils the requirements of the class B marine Automatic Identification System AIS transponder market The AIS system allows ships and base stations to communicate their position and other data to each other without the need for a centralised controller This allows vessels to see each other and take appropriate action to avoid collision and so improve marine safety The system uses a GMSK 9600 baud data link in the Marine VHF radio band The system requirements are defined in ITU M 1371 1 The CMX7032 CMX7042 is half duplex in operation comprising two parallel Limiter Discriminator Rx paths and one and Q or two point modulation Tx path The Rx paths are configurable for AIS or DSC operation the Tx for AIS only The device performs signal modulation demodulation with associated AIS functions such as training sequence detection NRZI conversion and HDLC processing flags bit stuffing de stuffing CRC generate check Integrated Rx Tx data buffers are also provided This greatly reduces the processing requirements of the host uC Provision of a number of auxiliary ADCs and DACs further simplifies the system hardware design reducing the overall
65. pe with a high impedance charge pump output requiring just passive components in the loop filter Lock detect functions are built in to each synthesizer and the status reported via C BUS A transition to out of lock can be detected and communicated via a C BUS interrupt to the 2006 CML Microsystems Plc 40 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 host uC This can be important in ensuring that the transmitter cannot transmit in the event of a fault condition arising Two levels of charge pump gain are available to the user to facilitate the possibility of locking at different rates under program control A current setting resistor R31 is connected between the ISET pin one for each PLL system and the respective RFVss This resistor will have an internally generated band gap voltage expressed across it and may have a value of 02 to 30kQ which in conjunction with the on chip series resistor of 9 6k 2 will give charge pump current settings over a range of 2 5mA down to 230uA including the control bit variation of 4 to 1 The value of the current setting resistor R31 is determined in accordance with the following formulae gain bit set to 1 R31 in Q 24 Icp 9600 gain bit cleared to 0 R31 in Q 6 lcp 9600 where Icp is the charge pump current in mA Note that the charge pump current should always be set to at least 230U A The gain bit refers to either bit 3 or bit 11 in the RF
66. ple e Cmd Reg Rx1B eseription C Meg DataTask RIBRDY The host should ensure that the R1BRDY Data Task and fe e 2 ee CmdReg Free bits are set l The host issues an RXB modem task to receive an AIS burst AO Note that the Rx Burst mode bit must be set 3 Device executes the modem task 4 Device waits for a training sequence and start flag then begins to demodulate and decode data The Rx state changes from Idle to receiving If the burst has a correct CRC the result is placed in the data buffer if not it is discarded An Rx state alert is issued and the Rx state changes from receiving to idle or an error condition 5 The host issues a DataWordResetNRx1 Data Task AAA Device reads the command register amp notes task types gt 0 Device carries out the data task by copying the first N data words of the data buffer into the Read Data registers The above 3 steps can be repeated Using DataWordN tasks to read many words out of the device 7 7 5 Rx Tasks e Abort Rx1 Rx 2 This causes the current task on the specified Rx channel to abort It also clears the modem buffer of the specified Rx channel e RxB1 2 Receive Burst on Rx1 Rx2 This causes the specified Rx channel to wait for a good training sequence and start flag then demodulate decode and store the burst in its data buffer See section 7 7 1 for a detailed discussion of AIS burst reception The recovered data can be read by the host issuing a
67. position within the slot This is principally to ensure that transmissions occur at the right time and that hardware is correctly switched between Rx and Tx but is also useful for scheduling when to take RSSI measurements when receivers can be powered down and when they should wake up again In an AIS Class A transponder the clock is synchronised with a 1Hz tick from a GPS unit In a Class B transponder the clock may be synchronised to the GPS tick or may be synchronised to the reception time of AIS bursts from a Class A transponder or Base Station Note that the latter scheme requires management by the host uC which must determine which received bursts are qualified to be used as a timing reference Whichever of these methods is used by the transponder the CMX7032 requires a SlotCLK input from the host uC This should be a pulse at least 50us long whose rising edge is aligned to the AIS SlotCLK An edge is required at the start of every AIS slot hence the frequency of this signal is 37 5Hz The CMX7032 has several features to assist the host uC with timing which are detailed below All of these features are based on the SlotCLK signal provided by the host to the CMX7032 s SlotCLK pin All timings are defined as a number of 24kHz ticks referenced to the rising edge of the SlotCLK signal 7 4 5 Time of Arrival Reporting When the CMX7032 has received a burst as the result of a RXB1 2 receive burst task the time of arrival is present
68. ransmission format The CMX7032 CMX7042 is capable of transmitting AIS data in either raw mode or burst mode AIS Carrier Sensing CSTDMA for Class B systems is supported In AIS raw mode data is passed directly from the Tx Data Buffer to the GMSK modulator so the uC will be responsible for sending any necessary training sequences and performing HDLC processing and NRZI coding In AIS burst mode the CMX7032 CMX7042 uses an internal message buffer to assemble an entire message up to 5 slots to which it automatically adds the training sequence start stop flags CRC bit stuffing and NRZI coding prior to transmission After setting up the appropriate registers transmission is initiated by issuing a Tx Burst or Tx Raw task 2006 CML Microsystems Plc 30 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 7 6 1 Transmit Tasks e AbortTx This causes the current task on the Tx channel to abort It also clears the Tx modem buffer e TXB Transmit AIS Burst This task can only be executed if the Tx Raw bit bit 5 in the command register is cleared to 0 This causes the CMX7032 to take the contents of the Tx Data buffer apply AIS data coding and transmit the resulting AIS message The transmit sequence will start on the next SlotCLK edge The following four transmit tasks can only be executed if the Tx Raw bit is set to 1 e TDBS Transmit Data Buffer on SlotCLK This causes the CMX7032 to transmi
69. ransmit sequence events are configured as a table of values that are loaded into the CMX7032 CMX7042 using a Config Task operation User Manual section 11 15 7 this operation must be performed before any transmissions are attempted Typically this will only need to be done once as part of an initialisation routine All timings are measured in units of ticks each of which lasts for 1 24000Hz 41 666us The transmit sequence consists of two initial setting values followed by a number of different event types These are e Initial delay from the SlotCLK edge e Active state of the TxEnable pin e Changes to the external hardware via the TxEnable pin typically used to turn the Tx on off and the AuxDAC1 ramp up down e Trigger for the start end of the CSTDMA sensing period if CSTDMA is enabled e Timing triggers for the start and end of the data modulation e Adummy event in case any of the above are not required in the application The transmit event sequence is programmed using a Config task see User Manual section 11 15 7 b3 b2 bi bO Eventid description SS O o po jo fo dummy Dornothing ss O O jo f1 CSTDMA_START Defines the start ofthe CSTDMA sensingwindow _ _ Jo o 1 O CSTDMAEND Defines the end ofthe CSTDMA sensingwindow o JO 1 f1 TxON__________ PinTxEnableisasserted________________ O Jo 1 o o RAMDAC UP AuxDACt will start executing a Rampup Z O 1 O
70. red 2006 CML Microsystems Plc 18 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 7 3 Function Image Load and Activation The Function Image Fl which defines the operational capabilities of the device may be obtained from the CML Technical Portal following product registration This is in the form of a C header file which can be included into the host controller software or programmed into an external EEPROM The maximum possible size of Function Image is 46 kbytes although a typical Fl will be less than this Note that the BOOTEN pins are only read at power on or following a C BUS General Reset and must remain stable throughout the Fl loading process Once the Fl load has completed the BOOTEN pins are ignored by the CMX7032 until the next power up or C BUS General Reset The BOOTEN pins are both fitted with internal 100k approx pull down resistors For C BUS load operation both pins should be pulled high by connecting them to Vaa either directly or via a 4k7 resistor see Table 2 For EEPROM load only BOOTEN1 needs to be pulled high in a similar manner however if it is required to program the EEPROM in situ from the host either a jumper to Vaa or a link to a host I O pin should be provided to pull BOOTENZ2 high when required see Table 2 Once the Fl has been loaded the CMX7032 performs these actions 1 the product identification code 7032 or 7042 is reported in C BUS regist
71. s in the incoming AIS signals from many different stations require that the input must rapidly follow the changes in DC and signal levels without de grading the signal seen at the RxIN pin 2006 CML Microsystems Plc 12 D 7032 42_F11 1 2 AIS Baseband IC with without RF Synthesizer 5 PCB Layout Guidelines and Power Supply Decoupling DVss DVss Ground Plane dp 0 gt a 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ca bei A eee ee ee eee RFVss RFVpp 2 5V RFVss r RFVpp I C23 C24 RFVsg RFVgg RFVgg CPVpp 3 3V PS CHARGE PUMP C26 c25 iaa RFVsg RFVsg I I i n 2 2 RFV ees G 3 e Ground Plane eae 1 f C28 Cy a DVss DVss DVss Alis DVss DVss G3 EXD a DVss VDEC AVss AVss AVDD AVDD C17 T C18 T C19 AVss AVss VBIAS I AVss AVss Ground Plane CMX7032 CMX7042 Figure 4 CMX7032 Power Supply Connections and De coupling 2006 CML Microsystems Plc Component Values as per Table 1 13 D 7032 42 Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 Notes 1 DVpp C20 C21 C22 1 Digital Ground Plane g L L L we DVss DVss DVss C3 gt gt Q o O O E A 36 10 2 4 AVDD AV ay a T C17 C18 C19 LE ol Bucs YDEC i a Ass AVss Ass 27 26 25 _ e O VBIAS SS N C7 AVss DVss Analogue Ground Plane Figure 5 CMX7042 Power Supply Connections and De coupling Compo
72. set up using the RSSI_Window config task using timing values based on the number of 24kHz tick increments from the rising edge of the SlotCLK plulse During this period if Tx_Status is not active the device will sample RSSI at 48k samples sec scale values to 0 128 apply the look up table values apply the RSSI_ gain value accumulate values over the defined period output values to C BUS registers AA 2006 CML Microsystems Plc 24 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 Note that the RSSI measurements on each RF channel run consecutively and that the C BUS registers are updated at the end of the RSSI_2 measurement window 7 4 10 RSSI Calibration The RSSI signal should be approximately logarithmically scaled i e a nearly linear relationship between voltage and signal strength in dBs In order to reduce the impact of noise the CMX7032 averages over several samples but to give a meaningful average the samples must first be anti logged In order to correct any non linearities in the RSSI response and to set an offset for the anti logging the host must supply calibration data The calibration data is a 128 entry table The entries correspond to equally spaced voltages from OV to 3 3V applied to the RSSI inputs To set up the table the host uses the Setup RSSI_ Calibration config task See section 7 8 for details The default values are shown in User Manual section 11 15 3 7 4
73. sistor OP Output TS OP 3 state Output PWR Power Supply Connection NC No Connection Functions with no associated pin number are not available in the CMX7042 2006 CML Microsystems Plc 9 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer 4 Recommended External Components DVDD DVss BOOTEN2 DVss BOOTEN1 EPSCSN EPSO R1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 IRQN RF1 RF1 RFVss _ RF1 CP1 OUT ISET 1 RFVpp RF2 RF2 RFVss CP2 OUT ISET 2 CHARGE PUMP RF CLOCK n c RFVss FV 2 5V DD 2 3 4 5 6 Y 8 9 RF2 CPVpp RFVgg 3 3V n c n c VDEC SLOT CLOCK CPVpp SYSCLK1 C26 T E C25 RFVss RFVss RFVpp DVss DVss C23 T T C24 RFVss RFVss Rx1 Rx2 SpareADC TL T EPSCLK EPSI n c ON 2 elz Ol cl af gt Sl x QO AT ad x kE DVss 27 C12 R6 es CBUS A _ z _ ep x o E O gt lt x O N x Q 3 E Q O Z Y Ol lt i gt O lt 09 4 Zi o Xx O aj ajl ul ep gt ep H O oOo OT ow C a v O Rx1 FB CMX7032L9 P1S Ala S g zQ els o o a S a AV 0 SS i R7 ro MOD 2 CMX7032 CMX7042 DVop C1 X1 L C2 C3 DYDD p C4 XTALN DVss XTAL CLK VDEG AUX DAC 4 AVop AUX DAC 3 ux AUX DAC 2 DAC AUX DAC 1 AVDD AUX ADC 2 AUX ADC 1 ae RSSI2 RSSI1 n c VBIAS T AVss R3 MOD 2 J E AVss R4 MOD 1 MA T A
74. st would need to read the entire 5 slot burst out of the Rx Data buffer during reception of the single slot burst such that the buffer is then available for the third burst in the sequence This is further compounded by the need to monitor both Rx channels Single slot AIS messages contain 168bits of data which can be read by the host in 3 C BUS RxData Read tasks The maximal length 5 slot message contains upto 840 bits which can be read by the host in 15 C BUS RxData Read tasks during the 26ms of a single slot This implies that the C BUS must be running at a speed greater than 128kHz 7 7 2 AIS Raw Mode Receive The operation of receive channel Rx1 in AIS raw mode is described below the operation of receive channel Rx2 in AIS raw mode is essentially identical to that of Rx1 but is controlled through its own set of tasks Note that both channels operate in either Raw or Burst mode it is not possible to select AIS Raw mode on one channel and AIS Burst mode on the other 2006 CML Microsystems Plc 36 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 In AIS raw mode the RxRAW bit in the Command register C8 must be set The CMX7032 CMX7042 then searches the Rx1 channel for a header training start flag sequence to detect the start of a message then transfers the three training bytes and the start flag to the Rx1 Data buffer The number of subsequent words transferred to the buffer is set by the value in the Rx
75. t few bits may be corrupted depending on the power up characteristics of the remote transmitter and local receiver circuits In AIS raw mode whenever an Rx1 state reset is performed by issuing an Abort1 task the channel state becomes dle This changes to Receiving when the first valid training sequence and start flag have been detected where it remains until another Rx1 state reset occurs In Raw mode a single Rx Data buffer is used however it is 4 words longer than the equivalent Burst mode buffer as it does not contain any burst information 7 7 3 DSC Receive Either the Rx1 or Rx2 channel can be configured for DSC reception The CMX7032 CMX7042 first applies 6dB octave de emphasis to the received signal then demodulates the resulting 1200 baud NRZ FSK data Only one of the channels at a time can be configured for DSC reception The received data is packed into 16 bit words for onward transmission to the uC The CMX7032 CMX7042 makes no attempt to perform dot pattern or data phasing detection those functions must be performed by the host uC No attempt is made to correctly align data it is simply packed into words most significant bit first as it arrives 2006 CML Microsystems Plc 37 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 7 7 4 Receive Example The following detailed example describes the process of receiving an AIS message in Burst mode on Rx channel 1 Table 9 AIS Burst Receive Exam
76. t first The AIS message structure however requires each message byte to be output least significant bit first The uC must therefore ensure that during the process of HDLC processing and NRZI coding that the resulting data bytes are correctly reversed 7 6 5 Transmitter Timing Control The CMX7032 CMX7042 can be configured to control the timing of transmission events whenever a Tx Burst Modem task is executed This includes the enabling of external RF circuits e g synthesisers and power amplifier as well as the time at which internal data modulation begins The flexibility of this timing control allows the CMX7032 CMX7042 to be simply adapted to the characteristics of the RF transmit circuits The control of the external RF transmit circuits is performed using the TxEnable pin and the AuxDAC1 ramping function 2006 CML Microsystems Plc 32 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 power SlotCLK SlotCLK modulation CS sense period Figure 13 Typical AIS Transmission A typical AIS transmission is shown in Figure 13 The CMX7032 CMX7042 starts timing relative to the rising edge of SlotCLK At the end of a transmission a sequence of power down actions is performed which are timed relative to the last message bit having been modulated shown as point B in Figure 13 In this way differences in message length due to bit stuffing are automatically accommodated The relative timings of the t
77. t the data buffer contents using AIS modulation No data coding is applied the Transmit Sequence will start on the next SlotCLK edge e TDB Transmit Data Buffer This causes the CMX7032 to transmit the data buffer contents using AIS modulation No data coding is applied The data will be transmitted as the modulator is available Transmit Sequence is ignored e PRBS Transmit pseudorandom bit sequence This task causes the CMX7032 to transmit an internally generated pseudorandom bit sequence The sequence is 511 bits in length but will repeat indefinitely until aborted using the Abort Tx task Transmit Sequence is ignored e TRW Transmit Repeated Word This task causes the CMX7032 to repeatedly transmit the first word currently in the data buffer Transmission will start immediately and will continue until an Abort Tx task is issued Transmit Sequence is ignored e HCT Hardware Control Task Allows manual control of ancilliary hardware functions 7 6 2 AIS Burst Mode Transmit In AIS burst mode the CMX7032 CMX7042 responds to a TXB task by performing bit stuffing NRZI encoding and the addition of training sequence start stop flags and CRC checksum as required by AIS Note in AIS burst mode the data words are automatically transmitted least significant bit first as required by the AIS specification A number of error conditions are checked for during AIS burst mode transmit each of which causes transmission to be aborted and a Tx
78. the data 7 3 1 FI Loading from Host Controller The FI can be included into the host controller software build and downloaded into the CMX7032 at power up over the C BUS interface The BOOTEN pins must be set to the C BUS load configuration the CMX7032 powered up and placed into Program Mode the data can then be sent directly over the C BUS to the CMX7032 Each time the device is powered up its Function Image must first be loaded and then activated These two steps assign internal device resources and determine all device features The device does not operate until the function image is loaded and activated 2006 CML Microsystems Plc 19 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 BOOTEN2 1 BOOTEN1 1 y Power up Reset CMX7032 Send Start Block 1 Address DB1_ptr to C BUS B6 Send Block 1Length DB1_len to C BUS B7 v Wait for C BUS C6 bit O to be set to 1 y Send 0001 to C BUS C8 gt A v Wait for C BUS C6 bit 0 to be set to 1 Send next data to C BUS C8 l Send Start Block 2 Address DB2_ptr to C BUS B6 Send Block 2 Length DB2_len to C BUS B7 y Wait for C BUS C6 bit 0 to be set to 1 v Send 0001 to C BUS C8 gt A y Wait for C BUS C6 bit 0 to be set to 1 Send next data to C BUS C8 p v Send Start Block 3 Address
79. xer 20 dBm 99 19839679 KHZ SWT 1 25 S Unit 1 25 Unit dBm Yil rr Al Tere el gt Center 161 975 MHz Span 500 kHz Center 161 975 MHz Span 500 kHz 29 AUG 2006 16 04 44 30 AUG 2006 14 29 11 amp Q wideband spectrum 2 point wideband spectrum lower trace shows un modulated signal generator Table 8 Tx spectrum masks 7 7 Reception The CMX7032 CMX7042 has two receive channels Rx1 and Rx2 which are capable of receiving AIS data in either raw mode or burst mode and either of which may be configured for DSC reception FSK 1200 baud The Rx1 and Rx2 channels can be configured and operated independently 7 7 1 AIS Burst Mode Receive The operation of receive channel Rx1 in AIS burst mode is described below the operation of receive channel Rx2 in AIS burst mode is essentially identical to that of Rx1 In AIS burst mode once an RXB1 task has been issued the Rx1 channel state changes to Receiving when a valid training sequence and start flag are detected The CMX7032 CMX7042 then performs NRZI decoding and bit destuffing on the received data stream and calculates the CRC checksum Note in AIS burst mode the data words are automatically reversed so that they are presented to the host most 2006 CML Microsystems Plc 35 D 7032 42 FI1 1 2 AIS Baseband IC with
80. xible design minimizes reference spurs for low phase noise results Charge pump o High low soft selectable current setting to speed large frequency channel changes o Nominal current user defined by external resistor value Lock detect 2006 CML Microsystems Plc 15 D 7032 42_Fl1 1 2 AIS Baseband IC with without RF Synthesizer CMX7032 CMX7042 Analog I O Functions e Auxiliary ADC system o Two 10 bit successive approximation ADCs with integrated sample and hold o One AuxADC is dedicated to RSSI measurement in a user defined window the other is available for general use e Ramping auxiliary DAC o DAC sequences through a user configured sequence of DAC output values to develop a specific rising falling DAC output signal This is useful for ramping an RF PA and can be configured to happen automatically at the start and end of a burst o Can operate as a general purpose DAC if desired e Three general purpose auxiliary DACs System Functions e All internal subsystems are controlled via a single serial host interface to reduce host uC pin count and simplify external host driver complexity e Transaction oriented command response logical host interface executes tasks supporting normal operation device configuration and functions to assist manufacturing calibration trimming of external circuits e Internal system clock derived from RF synthesizer reference oscillator and eliminates the need for additional XTAL or baseband clock oscillator

CMX7032 and CMX7042 Version 2 Datasheet

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