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1. psp o Threshold value THRESHOLD VALUE for the channel in Fig 2 5 Zero suppression Bit 8 of Bit Set 2 Register 1 The comparison is resumed in the following table Bit 8 of Bit Set 2 Register 1 ADC CONVERTED VALUE lt THRESHOLD VALUE x 2 O ADC CONVERTED VALUE lt THRESHOLD VALUE x 16 This feature is available from firmware releases 5 1 for earlier firmware releases the thresholds can be programmed only in 16 ADC counts steps as illustrated in Fig 2 4 NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 72 13 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 If the result of the comparison is true and the Bit 4 LOW THRESHOLD PROG of the Bit Set 2 Register is set to 0 data are skipped If the Bit 4 of the Bit Set 2 Register is set to 1 the true esult of the comparison is signalled by Bit 18 UNDERTHRESHOLD 1 in the loaded data 16 bit word The content of the Threshold Register includes also a KILL bit which allows to abort the memorisation of the datum even if it is higher than the threshold set in the register This bit can thus be used to disable some channels Refer to 4 39 for further details The threshold values are lost only after switching the board off a reset operation does not affect the threshold values 2 5 Overflow suppression The overflow suppression allows to
2. Example D BLOCK END 1 BERR_ENABLE 1 A Block Transfer readout of 34 words each event 34 words max allows the readout of one complete event as the EOB is encountered a BERR is generated N B Please note that according to the VME standard a Block Transfer readout can be performed with 256 read cycles maximum as a consequence a readout with a greater number of read cycles may require more BLT operations This limit is not due to the board itself but only to the VME standard if it is possible to disable or delay the timeout of the BUS Timer BTO x a Block Transfer readout with more than 256 read cycles can be performed as well Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 67 CAL Rs Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 5 7 Advanced Setting and Readout Modes NPO Chained Block Transfer CBLT and Multicast MCST operations allow to enhance the set and readout time of the 32 channels These operations allow accessing several boards at the same time CBLT operations are used for reading cycles only while MCST operations are used for write cycles only For further details on the CBLT MCST addressing mode please refer to 4 1 4 and 4 1 5 In order to perform CBLT and MCST operations the higher Base Address bits of all the involved modules i e bits 31 to 24 must be set in common to all boards v
3. 0 the sliding scale works normally default 1 the subtraction section of the sliding scale is dsabled test purposes only ALL TRG Allows to choose how to increment the event counter 0 event counter incremented only on accepted triggers 1 event counter incremented on all triggers default 4 26 Bit Clear 2 Register Base Address 0x1034 write only This register allows clearing the bits of the Bit Set 2 Register 4 25 A write access with a bit set to 1 resets that bit e g writing 0x4 to this register resets the CLEAR DATA bit A write access with the bits set to 0 does NOT clear the register content The structure of the register is identical to the Bit Set 2 Register 4 27 W Memory Test Address Register Base Address 0x1036 write only This register contains the address of the memory on which data can be written for the esteben efe z e s a sje iol memory test W TEST ADDRESS 10 0 Fig 4 27 W Memory Test Address Register N B The output buffer is a FIFO so the read address R Test Address Register must be different from the write address W Test Address Register 4 28 Memory Test Word_High Register Base Address 0x1038 write only NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 56 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 The Memory Test Word is a 32 bit word use
4. User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 remove the overload source switch the module off and then switch it on again 3 5 2 Switches PWR Type miniature flush plunger push button switch Function after the insertion of the board into the crate it allows to turn the board on off by pushing it with a pin please note that the switch is inactive if the board doesn t support live insertion Refer to 5 2 for the power ON procedure NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 72 25 CAEN Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 3 6 Internal hardware components The module is constituted by a motherboard with a piggy back board plugged into it see also Fig 1 2 where the functional blocks hosted on the piggy back board are pointed out In the following some hardware setting components located on the boards are listed Refer to Fig 3 4 and Fig 3 5 for their exact location on the PCB and their settings 3 6 1 Switches ROTARY SWITCHES TERM ON V775 Type 4 rotary switches Function they allow to select the VME address of the module Please refer to Fig 3 4 for their settings Type 14 DIP switches a couple positive and negative for each control signal Function they allow the insertion of the Bus termination on the relevant line The 110 Q termination
5. A write access to this dummy register causes a conversion for test purposes 4 36 Slide constant Register Base Address 0x106A read write COCO COD uGeoeEec DO oo Fig 4 34 Slide Constant Register This register contains a 8 bit value corresponding to the constant to which is set the sliding scale DAC when the sliding scale is disabled by means of the SLD_ENABLE bit of the Bit Set 2 Register refer to 8 4 25 4 37 AAD Register Base Address 0x1070 read only This register contains the value converted by the ADC of the Block A refer to the block diagram of Fig 1 2 NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 59 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 bsjrajsojr2jrro efe 7 6 5 4 8 2 iol BLOCK A CONVERTED VALUE 11 0 Fig 4 35 AAD Register 4 38 BAD Register Base Address 0x1072 read only This register contains the value converted by the ADC of the Block B Refer to the block diagram of Fig 1 2 BLOCK B CONVERTED VALUE 11 0 4 s3 12 10 of 2 7 6 5 4 8 2 iol Fig 4 36 BAD Register 4 39 Thresholds Memory Base Address 0x1080 0x10BE read write This register contains the low threshold and kill option for each channel The address is different for each channel V775 chO gt 0x1080 ch1 gt 0x1082 ch30 gt 0x10BC ch31 gt 0x
6. acquisition is stopped as the GATE not used MI Lett position board is BUSY GATE not used dot not visible NETO termination OFF VETO BUSY BUSY FCLR FCLR Fig 3 4 V775 Component Location component side NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 72 27 CAEN Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 3 6 3 Soldering pads S9 VEE S10 GND Function it allows to connect the second pin of the CONTROL connector to the VEE power supply 5 V No Soldering default the pin 2 of the CONTROL connector is not connected Soldering the pin 2 d the CONTROL connector is connected to VEE power supply 5 V Function it allows to connect the first pin of the CONTROL connector to the DIGITAL GROUND No Soldering default the pin 1 of the CONTROL connector is not connected Soldering the pin 1 of the CONTROL connector is connected to the digital ground Refer to Fig 3 5 for the exact location of these pads on the PCB and their settings C NPO 00102 97 V775x MUTx 10 10 onn All Soldering pad to connect the pint of the CONTROL connector to the DIGITAL GROUND S9 VEE Soldering pad to connect the p of the CONTROL connector to the VEE power supply 5V CT eg Fig 3 5 Components location soldering side Number of pages Page V775 REV 10 DOC 72 28 CAL Rs Doc
7. identify the type of word 010 gt header The bits 23 16 identify the crate number according to the content of the Crate Select Register see 4 30 The bits 13 8 contain the number of memorised channels Datum content The bits 31 27 contains the GEO address The bits 26 24 identify the type of word 000 gt datum The bits 20 16 bits 20 17 in the V775 N identify the number of the channel which the data are coming from The bit 14 is the VALID bit 1 gt the datum is valid 0 gt the datum is not valid it is actually possible to make the datum be written in the buffer even if it is not valid by using the bit 5 of the Bit Set 2 Register see 4 26 The bit 13 is the UNDERTHRESHOLD bit see 2 4 0 gt the datum is over the threshold fixed in the relevant register 1 gt the datum is under the threshold fixed in the relevant register it is actually possible to make the datum be written in the buffer even if it is under the threshold by using the bit 4 of the Bit Set 2 Register see 8 4 26 The bit 12 is the OVERFLOW bit see 2 5 0 gt ADC not in overflow condition 1 gt ADC in overflow it is actually possible to make the datum be written in the buffer even if it is out of range by using the bit 3 of the Bit Set 2 Register see 4 26 The bits 11 0 contain the converted datum EOB content The bits 31 27 contains the GEO address The bits 26 24 identify th
8. in the Test Event Write Register Base Address 0x103E These 32 data constitute the event to obtain as output of the 32 channels The 32 test data must be written in this FIFO in the same order as they will be read from the output buffer that is test datum for the channel 0 test datum for the channel 16 test datum for the channel 1 test datum for the channel 30 test datum for the channel 15 test datum for the channel 31 N B please note that the user must write at least and not more than 32 test words Actually since the words are written in a circular FIFO if the user writes less than 32 words some words will be not defined on the other hand if the user writes more than 32 words some words will be overwritten Set to 1 the Bit 6 TEST ACQ of the Bit Set 2 Register see 4 25 this action resets again the write pointer in the FIFO and releases the read pointer Send a set of COM input signals at each COM signal the data previously written in the FIFO will be transferred to the output buffer The data will be read via VME in the same order as they were written into the FIFO test data word for the channel 0 test data word for the channel 16 test data word for the channel 1 test data word for the channel 30 test data word for the channel 15 test data word for the channel 31 N B To operate in normal mode again the Bit 6 of the Bit Set 2 Register must be set again to 0 Filename Number of pages Page 00102 97 V77
9. the addressing mode A32 Data mode the data mode D16 D32 or D64 BOARD 1 BOARD 2 BOARD 3 BOARD 4 ee Switches Lower bytes of Address Lower Rotary Switches Upper bytes of Address Slots ee in the crate p2fsfelsfe z sfefrofrfrafsfafrstrefafrafreaoper Fig 4 4 MCST CBLT Addressing Example Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 72 34 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 In the following two software examples using the above mentioned procedures are listed Example of Access via Base Address vme_write 0xEE001004 OxAA A32 D16 set MCST Address 0xAA for board 1 vme_write 0xCC111004 OxAA A32 D16 set MCST Address 0xAA for board 2 vme_write 0xBC341004 OxAA A32 D16 set MCST Address 0xAA for board 3 vme_write 0xDD711004 OxAA A32 D16 set MCST Address 0xAA for board 4 vme write 0xEE00101A 0x02 A32 D16 set board 1 First vme_write 0xCC11101A 0x03 A32 D16 set board 2 Active vme_write 0xBC34101A 0x00 A32 D16 set board 3 Inactive vme_write 0xDD71101A 0x01 A32 D16 set board 4 Last vme_write 0xAA001006 0x80 A32 D16 set RESET MODE for all the boards Example of Access via geographical address vme_write 0x180016 OxAA A24 D16 set MCST Address 0xAA for board 1 vme_write 0x30001
10. v ve ve Y Y x5 Y Y 10 WO Y Y Y Ea Crate Select Y E Full Scale Range lt Y 10x1060 Read Write Di6 R Test Address 7 Y 0x1064 Writeony 1D16 swcomm JJ 10x1068 Write only 1D16 Slide Constant 0x106A Read Write Di6 JAAD Y Jooo Readonty DIS BAD TT Joozz Readony DIS Thresholds 0x1080 0x10BE Read Write Die not all bits are reset with the same type of RESET see the description of the relevant register for details Write access is allowed only in AMNESIA cases see 4 12 i e when there is no PAUX The ROM address map is from 0x8000 to OxFFFF refer to 4 40 NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 39 CAE Rl Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 Table 4 3 Address Map in CBLT operation Output Buffer 0x0000 0x07FF Read only D32 D64 Table 4 4 Address Map in MCST operations Basen TI 7777130 oe Interrupt Level 0x100A Interrupt Vector ADER High ADER Low Single Shot Reset Event Trigger Register Increment Event Increment Offset Bit Clear 2 W Memory Test Address Memory Test Word High Memory Test Word_Low Crate Select Event Counter Reset R Test Address SW comm NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 40 CAER Document type Title Revision date
11. 4 27 W MEMORY TEST ADDRESS REGISTER ccsccsssssssssescssessssessesessescssessescssesseecssescsecaseecsecassecsesecnecaesecaecaesecaeenens 55 4 28 MEMORY TEST WORD HIGH REGISTER cccsssssssssessessesessescscescescssescsscssecssescsscssescsecaesecaececsecaesecaeceesecaeenens 55 4 29 MEMORY TEST WORD LOW REGISTER ccccccsssssssssessesssscssesessesesscsseccsscsesecssesesscassecsecassecseecnscaesecaeseesecaeseens 56 4 30 CRATE SELECT REGISTER uns ker rie arien heter tea 56 4 31 TEST EVENT WRITE REGISTER c ccccscsccssssssessescssessesessesesscssescsscscsscssescsscsssecssesssecaseecsescassecsesecsecaesecaecaesecaeenens 56 4 32 EVENT COUNTER RESET REGISTER cscscscsssscssssssscssenesesessscsssnenecesssensssesecasssenesessscaesucneseesscneseusecasenssesessuene 57 NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 72 4 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 4 33 FULL SCALE RANGE REGISTER ua renser e a A R n e 57 4 34 R MEMORY TEST ADDRESS REGISTER srrervnvnervrenenererenenererenenererenenererenenerenenenerenenenererenenererenenerenenenerenenenerenene 58 ASI SS W COMM REGISTER hs r detec cores ae en wees 58 4 36 SLIDE CONSTANT REGISTER x sscscssecccossuccesonsvevvess siebecovcscussovguaveveuavevevavavevassvavecesessuevevsvavevesssivodess a i 58 437 NAD REGISTER ukers s ie renn eierens EE
12. 97 V775x MUTx 10 V775_REV10 DOC 73 57 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 A write access to this register allows the user to write a set of 32 data into a 32 word FIFO As the Bit6 TEST ACQ of the Bit Set 2 Register see 4 25 is set to 1 and the Acquisition Test Mode is consequently selected these data are directly written in the output buffer constituting an event which can be used to test the module and or the acquisition software Each 16 bit test word see the figure below contains a 12 bit value acting as the ADC converted value and an OV bit which indicates the possible overflow The 32 test data corresponding to the data from the 32 channels must be written in this FIFO in the same order as they are read from the output buffer that is test datum for the channel 0 test datum for the channel 16 test datum for the channel 1 test datum for the channel 30 test datum for the channel 15 e test datum for the channel 31 For further details on the use of this register in Acquisition Test Mode please refer to 5 5 2 N B please note that the user must write at least and not more than 32 test words Actually since the words are written in a FIFO if the user writes less than 32 words some words will be not defined on the other hand if the user writes more than 32 words some words will be overwritten gende re slusene
13. Acquisition Test Mode selected i e the data to be stored in the buffer are taken from an internal FIFO Test Event Write Register see 4 31 Allows to enable disable the sliding scale 0 the sliding scale is disabled and the DAC of the sliding scale is set with a constant value Slide Constant see 4 36 1 the sliding scale is enabled default Allows to select Common Start or Common Stop mode 0 Common Start mode 1 Common Stop mode Allows to enable disable the automatic increment of the readout pointer From firmware release 5 1 this bit STEP_TH allows to set the zero suppression threshold resolution see 2 4 for further details NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 55 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 0 the read pointer is not incremented automatically but only by a write access to the Increment Event or Increment Offset Registers see 4 23 1 the read pointer is incremented automatically default EMPTY PROG Allows to choose if writing the header and EOB when there are no accepted channels 0 when there are no accepted channels nothing is written in the output buffer default 1 when there are no accepted channels the Header and the EOB are anyway written in the output buffer SLIDE_SUB ENABLE Allows to change operation mode for the sliding scale
14. COM signals are converted into a voltage level by the TAC sections and then are multiplexed and converted by two fast 12 bit ADC modules Only the values that are above a programmable threshold see 2 4 do not cause overflow see 2 5 and are not killed see 2 4 will be stored in a dual port data memory accessible via VME In the following functional sections and operation principles of the module are described in some detail The block diagram of the module can be found in Fig 1 2 Operating mode description The Mod V775 can operate either in Common Start or Common Stop mode The operating mode can be selected via the bit 10 of the Bit set 2 register please refer to 4 25 TAC sections The module hosts 32 16 for the Mod V775 N TAC Time to Amplitude Conversion sections a TAC section converts the time interval between Start and Stop signals to a proportional voltage level a simplified block diagram is reported in Fig 2 1 A Start signal closes the switch SW1 thus allowing a constant current to flow through an integrator a Stop signal opens the switch SW1 again The constant current generates a linear ramp voltage which is stopped at an amplitude proportional to the time interval between Start and Stop pulses After digitisation the SW2 switch is closed by the CLEAR signal which allows the discharge of the capacitor C1 Both the COMMON and CLEAR signals are controlled by the CONTROL LOGIC section The timing of signals
15. Oxtt 0x00 0x03 BOARD ID MSB BOARD ID BOARD ID LSB Revision 0x804E 10x00 Serial MSB 0x8F02 10x00 Serial LSB 0x8F06 Jox02_ the example of content for the relevant register refers to the Mod V775AA serial number 2 hardware revision 0 Filename Number of pages V775 REV10 DOC 73 Page 61 CAL NI Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 5 Operating modes 5 1 Installation The V775 board must be inserted in a V430 VME 6U crate if the purchased version is equipped with a PAUX connector If the version does not have the PAUX connector it can be inserted into a standard VME 6U crate Refer to Table 1 1 for details on the various versions Please note that some versions of the board support live insertion extraction into from the crate i e it is possible to insert or extract them from the crate without turning the crate off Moreover it is possible to switch the board off by the relevant PWR switch see 3 5 2 without cutting the interrupt chain off A CAUTION ECL INPUTS ARE SUSCEPTIBLE TO DAMAGE FROM ESD ELECTROSTATIC DISCHARGE TO PREVENT THE RISK OF DAMAGING THE USER SHOULD NEUTRALIZE ANY STATIC ELECTRIC CHARGE BUILT UP ON THE BODY e g TOUCHING AN EARTHED OBJECT BEFORE HANDLING THE ECL CONNECTORS AM CAUTION ALL CABLES MUST BE REMOVED FROM THE FRONT PANEL BEFORE EXTRACTING THE BOARD FROM TH
16. RST Electrical specifications diff ECL input signal active high high impedance min width 10 ns Function clears the TAC sections resets the Multi Event Buffer status stops pending ADCs conversions and depending NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 72 22 CAEN Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 DRDY GATE COM VETO BUSY on the user s settings see PROG RESET 4 13 may clear the control registers Electrical specifications diff ECL input output signal high impedance Function indicates the presence of data in the output buffer of the board DATA READY status is also flagged by the bit 0 of the Status Register 1 when several boards are daisy chained the global OR and NAND of DATA READY signals can be read respectively on the DRDY and DRDY lines of the CONTROL bus and the status of the DRDY bidirectional line is flagged by the bit 1 of the Status Register 1 see 4 12 not used Electrical specifications diff ECL input signal active high high impedance min width 10 ns Function Common Start or Common Stop signal Electrical specifications diff ECL input signal active high high impedance Function inhibits the conversion of the detected signals Electrical specifications diff ECL output signal high impedance Function indicates that the boar
17. V775 16 32 Channel Multievent TDC 10 09 2004 10 e DR gt Data RESET e SR gt Software RESET e HR gt Hardware RESET If a register has a mark in these columns it means that the relevant RESET operation resets that register For further details on the RESET Logic please refer to 2 10 NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 72 37 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 Table 4 3 and Table 4 4 list register addresses offset in CBLT and MCST operations respectively The ROM address map is reported in Table 4 38 p 60 NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 38 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 Table 4 2 Address Map for the Model V775 Address 0x0000 0x0FFC SR E ES 16 E i 16 pam Bitsett 1 ve 7o Interrupt Level vo 0x100A Read Write l ee oe ESE Pp i ay Interrupt Vector Status Register1 Control Register1 ADER High ADER Low _ Single Shot Reset foxtoie Write only Dte MCST CBLT Ctrl Event Trigger Register Status Register2 KM g S i po EA EEE AE Ea ieee Event Counter_L Increment Event BitSet2 0 BitClear2 0x1034 0x1036 0x1038
18. data reset see 2 10 4 22 Increment Event Register Base Address 0x1028 write only A write access to this dummy register sets the readout pointer on the next event in the output buffer at the first address In particular if the bit 11 AUTO INCR of the Bit Set 2 Register is set to 0 see 4 25 the readout pointer is no more automatically incremented but it can be incremented via a write access to this register or to the Increment Offset Register see below 4 23 Increment Offset Register Base Address 0x102A write only A write access to this dummy register increments the readout pointer of one position next word same event if EOB is not encountered next event if EOB is encountered In particular if the bit 11 AUTO INCR of the Bit Set 2 Register is set to 0 see 4 25 the readout pointer is no more automatically incremented but it can be incremented via a write access to this register or to the Increment Event Register see above 4 24 Fast Clear Window Register Base Address 0x102E read write For the definition of the Fast Clear window refer to Fig 2 8 By writing a 10 bit number N to this register it is possible to set the Fast Clear window width Trc in the range 7 38 5 us 1 32 us steps according to the following relation Tro US N x Torock 7 US where Toock 1 32 us NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 53 CAER Document type
19. during data acquisition is shown in Fig 2 2 CHANNEL input TAC section output to MUX CONTROL LOGIC costant current generator COMMON input Fig 2 1 Simplified block diagram of the TAC section Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 72 10 CAE Rl Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 INPUT COMMON TAC section OUTPUT CLEAR CONVERSION BUSY WRITE MEM WE DRDY CONVERSION LOGIC STATE acquiring data settling digitiza time tion 600 ns 6us Fig 2 2 Signal conversion timing in Common Stop mode NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 72 11 CAL Rs Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 2 3 Analog to digital conversion The output of each TAC section is multiplexed by group of 4 channels and subsequently converted by two fast 12 bit ADCs each of which operates the conversion on a group of 16 channels Block A and Block B ADCs The ADCs conversion time is 5 7 us for the V775 and 2 8 us for the V775 N regardless the number of active channels see block diagram in Fig 1 2 The ADC section supports the sliding scale technique to reduce the differential non linearity see references 1 2 This technique see Fig 2 3 consists in a
20. memory refer to 4 39 If the module is not BUSY a COM signal causes the following 1 starts or stops the TAC depending on operating mode selection 2 increments the event counter according to the user s settings see 2 8 3 sets the BUSY output signal to 1 until the end of the conversion if the MEB is not full If neither RESET nor FAST CLEAR occur refer to 2 10 and 2 11 to abort the Time to Amplitude Conversion the control logic starts the following conversion sequence 1 The outputs of the TAC sections are multiplexed and sampled 2 The control logic checks if there are accepted data among the converted values according to the user s settings zero suppression overflow suppression and KILL option see 2 4 and 2 5 a if there are accepted data these are stored in the active event buffer together with a Header and an EOB b if there are no accepted data and the EMPTY PROG bit of the Bit Set 2 Register is set to 0 default setting see 4 25 no data will be written in the output buffer c if there are no accepted data and the EMPTY PROG bit of the Bit Set 2 Register is set to 1 see 4 25 the Header and EOB only will be written in the output buffer 3 The TAC sections and the BUSY is cleared and the module is ready for the next acquisition NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 64 CAL Rs Document type Title Revision date Revision User
21. must be inserted on the lines of the last board of the chain In order to insert the termination on a given line both the positive and the negative DIP switches must be set refer to Fig 3 4 Right position dot visible the termination is inserted on the relevant line Left position dot not visible the termination is not inserted 3 6 2 Jumpers J12 Function it allows to select board behaviour in response to a BUSY status Position A high data acquisition is stopped as soon as any of the boards on the CONTROL Bus is BUSY Position B low data acquisition is stopped as the board is BUSY independently from the status of the other boards on the CONTROL Bus Refer to Fig 3 4 for the exact location of the jumper on the PCB and its setting NPO 00102 97 V775x MUTx 10 Filename Number of pages Page V775 REV10 DOC 72 26 CAL NI Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 Rotary switches for VME address selection Base address bit lt 19 16 gt Base address bit lt 23 20 gt Base address bit lt 27 24 gt Base address bit lt 31 28 gt DIP switches for BUS termination insertion Jumper for TERM ON BUSY mode selection RST Position A EXTBSY RST ED Right position J12 E acquisition is stopped as any DRDY dot visible board on the Bus is BUSY Con termination ON Position B INTBSY COM J12 9
22. must thus be initialised NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 72 17 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 2 11 FAST CLEAR NPO The FAST CLEAR of the module can be performed via the relevant front panel signal see 3 4 2 A FAST CLEAR signal generated at any time within the FAST CLEAR window i e between the leading edge of the COMMON signal and the end of the programmable time value set in the Fast Clear Window Register see 4 24 aborts the conversion Its minimum width must be 10 ns N B since a FAST CLEAR operation implies a CLEAR CONVERSION cycle a new GATE signal is accepted only if it occurs at least 600 ns after the leading edge of the FAST CLEAR signal 7 39 us programmable COMMON CLEAR window Fig 2 8 Fast Clear window Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 72 18 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 3 Technical specifications 3 1 Packaging The Model V775 is housed in a 6U high 1U wide VME unit The board hosts the VME P1 P2 connectors and depending on the version the PAUX connector The version equipped with the PAUX connector V775 AA V775 NA requires the VME V430 backplane 3 2 Power requirements The power
23. parameters depending on the individual channel characteristics N B the MCST CBLT Address Register must NEVER be accessed in MCST mode since this can affect the CBLT and MCST operations themselves Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 74 69 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 APPENDIX A VME interface timing NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 74 70 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 A 1 VME Cycle timing in D16 D32 mode The figure below reports the Data Select DSO or DS1 Data Acknowledge DTACK VME cycle in D16 mode and relative timing The theoretical minimum duration of the VME cycle in D16 D32 mode is 120 60 ns 120 152 ns 60 92n DTACK DS Fig A 1 VME cycle timing in D16 mode A 2 VME Cycle timing in BLT CBLT mode The figure below reports the Data Select DSO or DS1 Data Acknowledge DTACK VME cycle in BLT CBLT mode and relative timing The theoretical minimum duration of the VME cycle in BLT CBLT mode is 60 15 ns 60 92 ns Fig A 2 VME cycle timing in BLT CBLT mode NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 71 CAL Rs Document type Title Revision date Revision User
24. requirements of the versions available for the V775 module are as follows Table 3 1 Model V775 power requirements Power supply st TAG PENA vare H2V 560mA 570 mA ERA NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 72 19 CAL Rs Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 3 3 Front Panel Mod V775 DTACK VME selected LED DTACK OVC PWR overcurrent power on status LED yr TERM termination status LED QU Block B INPUT connector Ch 16 31 PWR switch Block A INPUT connector Ch 0 15 I N P uU T GATE COMMON NIM input connector GATE COMM BUSY status LED CONTROL connector p GATE not used Data Ready LED Fig 3 1 Model V775 front panel Number of pages Page NPO Filename 72 20 00102 97 V775x MUTx 10 V775 REV10 DOC CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 Fig 3 2 Model V775 N front panel NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 72 21 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 3 4 External connectors The location of the connectors is shown in Fig 3 1 Their function and electro mechanical specifications are listed in the follo
25. see 4 25 in this case the event is constituted by 2 32 bit words only The MEB is mapped on a 2 Kbyte wide address space to facilitate BLT across 256 byte boundaries with some brands of CPUs but it is important to point out that any read operation at any location within the segment Base Address 0x0000 0x0FFC always returns the data word pointed by the Read Pointer Event Counter The module houses a 24 bit counter that counts the number of COMMON signals that the module has received The Event Counter can work in two different modes which can be selected via the Bit 14 ALL TRG of the Bit Set 2 Register see 4 25 Mode A ALL TRG 1 it counts all events default Mode B ALL TRG 0 _ it counts only the accepted events In the first case Mode A the Event Counter is increased each time a pulse is sent through the COMMON input In the second case Mode B the Event Counter is increased each time a pulse sent through the COMMON input is accepted i e VETO FCLR and BUSY are not active The value of the Event Counter is stored in the EOB of the Multi Event Buffer see 4 5 The Event Counter is also stored in two registers the Event Counter_Low and Event Counter_High Registers which respectively contain the 16LSBs and the 8MSBs of the Event Counter see 4 20 and 4 21 Busy Logic The board is BUSY either during the conversion sequence or during the reset of the analog section or when the MEB is not rea
26. which has received the token stores sends the data from to the master via CBLT MCST access No empty slots must thus be left between the boards or in alternative empty slots can be left only in case VME crates with automatic IACKIN IACKOUT short circuiting are used Once the addresses have been set the first and last board in a chain must have respectively only the FIRST_BOARD F_B and only the LAST_BOARD L_B bit set to 1 in the MCST Control Register see 4 17 On the contrary all intermediate boards must have both the FIRST_BOARD and the LAST_BOARD bits set to 1 active intermediate or both the FIRST BOARD and the LAST BOARD bits set to 0 inactive By default these bits are set to 0 the board is inactive Board status Board position in the chain F_B bit L_B bit inactive ee ES Please note that in a chain there must be one and only one first board i e a board with F B bit set to 1 and the L B bit set to 0 and one and only one last board i e a board with F_B bit set to 0 and the L B bit set to 1 ml EE EE e 0 The complete address in A32 mode is A 31 24 MCST CBLT Address A 23 16 00 A 15 0 offset In MCST CBLT operation it is possible to define more chains in the same crate but each chain must have an address different from the other Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 72 33 CAE Rl Document type Title Revision date Revision User s Manual MUT Mo
27. 1 and consequently the module inserted in the slot 5 will have a GEO address set to 00101 see Fig 4 1 The e address in A24 mode for geographical addressing is A 31 24 don t care A 23 19 GEO A 18 16 0 A 15 0 offset The following two figures show the binary and the hexadecimal representation of respectively the board Address and a Register Address Bit Set 1 Register in GEO addressing mode 2a ofeo 19117619 14 191211f10 s 8 7 fe 5 4 9 2 1 fofofrfofsfefefofofofofefofefofofofofofo ofofofo Binary representation e s of o o o Hexadecimal representation Fig 4 1 Binary Hexadecimal representation of the board Address in GEO mode 292220 so 17 10 r 12 04 9 fel vo 5 4 22 ol arap 1 fo1 leh lolol elolotolol els slo Srey reves 1006 offset Hexadecimal representation Fig 4 2 Binary Hexadecimal representation of Bit Set 1 Register Address in GEO mode It is suggested to perform module settings in geographical addressing mode Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 72 31 CAE Rl Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 N B In the case of versions where the SN5 SN1 lines are not available i e the versions without the PAUX connector addressing via geographical address is not possible Although in these versions it is possible to perform a write access to the GEO Address
28. 10BE V775N chO gt 0x1080 chi gt 0x1084 ch14 gt Ox10BA ch15 gt 0x10BE Each threshold register is as shown in the figure Gasca eee THRESHOLD VALUE Fig 4 37 Threshold Register KILL K allows to abort memorisation of the data from the relevant channel 0 channel data are memorised 1 channel data memorisation is aborted THRESHOLD VALUE this is a amp bit value which is compared with the 8MSB of the 12 bit value to be memorised Default settings are not defined NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 60 CAER Document type User s Manual MUT Please note that the KILL option can be used to disable some channels Title Revision date Revision Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 N B the threshold values are reset only with a hardware reset and when the board is switched off 4 40 ROM memory Base Address 0x8000 OxFFFF read only It contains some useful information according to the table below such as e OUI manufacturer identifier IEEE OUI e Version purchased version of the Mod V775 in the table Mod V775AA e Board ID Board identifier 775 e Revision hardware revision identifier e Serial MSB serial number MSB e Serial LSB serial number LSB NPO 00102 97 V775x MUTx 10 Table 4 38 ROM Address Map for the Model V775 Description 0x8026 0x00 OUI LSB Ox802E_ OxE6 Version 0x8032_
29. 2 8 The first event written in the active Event Buffer Write pointer n is that relative to the GATE n 5 during which two channels 2 and 5 were over the programmed threshold the stored event is constituted by a Header the data relative to the two channels and the End of Block word at the end of all converted data of the relevant Event During GATE n 6 and n 7 no channels were in the selected range The next event written in the following active Event Buffer Write pointer n 1 is that relative to the GATE n 8 it consists of the Header the data relative to three channels 0 17 and 3 and the End of Block word at the end of all converted data 3 sfasfagjerjesjesjeaasfenfer aotfrapr7 19 18 tapre 9 9 8 7 0 5 413 2 Lol CN O oenen of DEE TITT Write poner co olo o CHANNEL gre ADO COUNTS N eo foofof owner ef ocos mee eo of 1 EVENT COUNTER m ao oa rn 7 Pointer N 1 GATE 8 EVENT COUNTER m 3 Fig 4 9 Multi Event Buffer data structure example NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 43 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 N B in the versions which do not have the PAUX connector the GEO address must be written by the User via a write access to the relevant register see 4 6 If this operation is not performed it will be not possible to identify which module the da
30. 5x MUTx 10 V775 REV10 DOC 73 66 CAL Rs Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 5 6 Block Transfer Mode NPO The module supports the Standard BLT32 and MBLT64 modes A standard readout in Block Transfer mode for example consists of a readout of the Header for the relevant event and a Block Transfer readout of the number of data words relative to the event the number of data words referring to the event is the CNT number in the Header see 4 5 A more efficient readout in Bock Transfer mode can be performed by using the BLOCK END and BERR ENABLE bits of the Control Register 1 see 4 13 Some examples of this type of readout in Block Transfer mode are as follows Example A BLOCK END 0 BERR_ENABLE 0 A Block Transfer readout of 32x34 words 32 events max each event 34 words max allows the readout of all data stored in the buffer as the buffer is empty the module will send only not valid data Example B BLOCK END 0 BERR_ENABLE 1 A Block Transfer readout of 32x34 words 32 events max each event 34 words max allows the readout of all events stored in the buffer as the buffer is empty a BERR is generated Example C BLOCK END 1 BERR_ENABLE 0 A Block Transfer readout of 34 words each event 34 words max allows the readout of one complete event after the readout of the EOB the module will send only not valid data
31. 6 OxAA A24 D16 set MCST Address 0xAA for board 2 vme_write 0x480016 OxAA A24 D16 set MCST Address 0xAA for board 3 vme_write 0x510016 OxAA A24 D16 set MCST Address 0xAA for board 4 vme_write 0x180040 0x02 A24 D16 set board 1 First vme_write 0x300040 0x03 A24 D16 set board 2 Active vme_write 0x480040 0x00 A24 D16 set board 3 Inactive vme write 0x510040 0x01 A24 D16 set board 4 Last vme_write 0xAA001006 0x80 A32 D16 set RESET MODE for all the boards N B there must be always one and only one FIRST BOARD and one and only one LAST BOARD NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 72 35 CAL Rs Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 4 2 Interrupter capability The Mod V775 houses a RORA type VME INTERRUPTER The INTERRUPTER responds to 8 bit 16 bit and 32 bit Interrupt Acknowledge cycles providing an 8 bit STATUS ID on the VME data lines D00 D07 4 2 1 Interrupt Status ID The interrupt STATUS ID is 8bit wide and it is contained in the 8LSB of the Interrupt Vector Register see 4 11 The register is available at the VME address Base Address 0x100C 4 2 2 Interrupt Level The interrupt level corresponds to the value stored in the 3LSB of the Interrupt Level Register see 4 10 The register is available at the VM
32. AER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 GLOBAL BUSY AMNESIA PURGED TERM ON TERM OFF EVRDY Indicates that at least a module in a chain is BUSY OR of the BUSY signal of each module in the chain 0 No module is Busy 1 Atleast a one module is Busy Indicates that no GEO address was picked from the VME connectors 0 GEO is picked from the JAUX 1 GEO is not available from the JAUX it can be written in the GEO Address Register see 4 6 for MCST operation during a CBLT operation it indicates that the board is purged i e the board has finished to send data 0 the board is not purged 1 the board is purged Termination ON bit 0 not all Control Bus Terminations are ON 1 all Control Bus Terminations are ON Termination OFF bit 0 not all Control Bus Terminations are OFF 1 all Control Bus Terminations are OFF is a flag for the Event Trigger Register 0 default indicates that the number in the Event Trigger Register see 4 18 is smaller than the number of events stored in the memory 1 indicates that the number in the Event Trigger Register see 4 18 is greater than or equal to the number of events stored in the memory and an interrupt request has been generated with interrupt level different from 0 see 4 2 3 N B the condition in which both TERM ON and TERM OFF bits are equal t
33. AG is reset both via hardware reset and software reset 4 9 Bit Clear 1 Register Base Address 0x1008 read write This register allows to clear the bits in the above described Bit Set 1 Register A write access with a bit set to 1 resets that bit e g writing 0x8 to this register resets the BERR FLAG bit A write access with the bits set to 0 does NOT clear the register content in other words when 1 is written into one particular bit such bit is set to 0 cleared if 0 is written the bit remains unchanged The structure of the register is identical to the Bit Set 1 Register A read access returns the status of the register 4 10 Interrupt Level Register Base Address 0x100A read write The 3 LSB of this register contain the value of the interrupt level Bits 3 to 15 are meaningless Default setting is 0x0 In this case interrupt generation is disabled psfrafrsfrafrsfiofo e r s sfa a 2 1 o Fig 4 13 Interrupt Level Register 4 11 Interrupt Vector Register Base Address 0x100G read write This register contains the STATUS ID that the V775 INTERRUPTER places on the VME data bus during the Interrupt Acknowledge cycle Bits 8 to 15 are meaningless Default setting is 0x00 NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 46 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 a PEEL EEL
34. E CRATE 5 2 Power ON sequence To power ON the board follow this procedure 1 insert the V775 board into the crate as the board is inserted the OVC PWR green LED lights up indicating that the board is powered 2 if the board supports live insertion and the TERM LED BUSY LED and DRDY LED are off press the flush plunger PWR micro switch on the front panel by NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 62 CAER Document type User s Manual MUT Title Revision date Revision Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 inserting into it a pin as this switch is pressed the TERM LED lights up orange the BUSY LED becomes red and the DRDY LED becomes yellow this indicates that the board is turned on and is configuring if the TERM LED BUSY LED and DRDY LED are on it means that the board is already ON and is configuring the board can be on or off as it is inserted into the crate depending on how it was when it was extracted after a short time the BUSY and DRDY LEDs will light off and the TERM LED will become either red or green or off according to the status of the terminations on the PCB of the board this indicates that the board is ready to acquire data N B if the OVC PWR LED becomes orange instead of being green there is an overload and the over current protection is now running In order to acquire data it is necessary to remove the overload source then tu
35. E address Base Address Ox100A If the 3LSB of this register are set to 0 the Interrupt generation is disabled 4 2 3 Interrupt Generation An Interrupt is generated when the number of events stored in the memory equals the value written in the Event Trigger Register at the VME address Base Address 0x1020 see 4 18 If the value in Event Trigger Register is set to 0 the interrupt is disabled default setting 4 2 4 Interrupt Request Release 4 3 4 4 NPO The INTERRUPTER removes its Interrupt request when a Read Access is performed to the Output Buffer so that the number of events stored in the memory decreases and becomes less than the value written in the Event Trigger Register Data transfer capability The internal registers are accessible in D16 mode unless otherwise specified Access in D32 BLT32 MBLT64 CBLT32 and CBLT64 is available for the data buffer Register address map The Address map for the Model V775 is listed in Table 4 2 All register addresses are referred to the Base Address of the board i e the addresses reported in the Tables are the offsets to be added to the board Base Address The Table gives also information about the effects of RESET on the registers In particular column 2 through 4 refer to the following RESET operations Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 72 36 CAE Rl Document type Title Revision date Revision User s Manual MUT Mod
36. EN 58 4 38 BAD REGISTER ess 59 4 39 THRESHOLDS MEMORY seneste sokk ankelen 59 4 40 ROMMEMOR Visionado EAA E E latin is sans 60 5 1 INSTALLATION ARE E E Ad AA A A EA 61 5 2 POWER ON SEQUENGE scouts iicicd a 61 5 3 POWER ON STATUS Sa ea at beer ude 62 54 OPERATION SEQUENCE 200 ea ek 63 5 5 TEST MODES nre ieta a a e n a a a a a a a a 64 5 5 1 Random Memory Access Test Mode nrnrnrnrnonvnononononenenenenenenenenenenenenenenenenenenesenenenevenenenesenenesesenenesesenenere 64 5 3 2 Acquisition Test Mode osa 64 5 6 BLOCK TRANSFER MODE juni rare 66 5 7 ADVANCED SETTING AND READOUT MODES 5 7 1 Chained Block Transfer Mode 5 7 2 MULTCASECOMMAVES A ee eee APPENDIX As unidad aia aceras oda EEA AAIEN DEAE doin daa don dci cian 69 VME INTERFACE TIMING 69 A 1 VME CYCLE TIMING IN D16 D32 MODE rarsvsnrnvsvevrnrnrnrsnrnenrsvrsenrnssnenssrnvsnsenrnenssevsnenrsrssensnesssnsnrnenssvsnenssessensnssser 70 A 2 VME CYCLE TIMING IN BLT CBLT MODE cecesescssssssssescsesescesessseecseseseuseecseseceesesesaescaeaesensesenanecaeseeeeaeess 70 A 3 VME CYCLE TIMING IN MBLT CBLT64 MODE cccssssscssssssssesesceececsesesessescseseceesesseaeecsesecenseseseneceeseeeaeess 71 6 REFERENCES EE E E E E E E O O E E bescsassoasecse E E E E OA O 72 NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 72 5 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multiev
37. FRONT PANEL oa 21 FIG 3 3 CONTROL CONNECTOR PIN ASSIGNMENT V775 ONLY ccscsssssssesssssesesesesesencsesescneneseseneneseaenenescseneneseseneneeenes 24 FIG 3 4 V775 COMPONENT LOCATION COMPONENT SIDE rrrerererervrererererererererererererererererererererereressrerereserereressrererener 27 FIG 3 5 COMPONENTS LOCATION SOLDERING SIDE ervrvrvrersrvrerererererererererererererererererererererererererereresererererererereserererener 28 FIG 4 1 BINARY HEXADECIMAL REPRESENTATION OF THE BOARD ADDRESS IN GEO MODE cesssssesesereteeeees 31 FIG 4 2 BINARY HEXADECIMAL REPRESENTATION OF BIT SET 1 REGISTER ADDRESS IN GEO MODE 31 FIG 4 3 BASE GEO ADDRESSING EXAMPLE I rnrrrerererrerererenerererensrererensrererenerererensrererensrererererererenerererersrererenerererersrererener 32 FIG 4 4 MCST CBLT ADDRESSING EXAMPLE rrorvrersrvrvrererererererererererensrererererersrererererenerererenererereserererenererereserererererererener 34 FIG 4 5 OUTPUT BUFFER THE HEADER inntrer T EEA NE R E RE 40 FIG 4 6 OUTPUT BUFFER THE DATA WORD FORMAT ervrvrerererererererensrererenerererererererenererereserererererereressrereresererereserererener 40 FIG 4 7 OUTPUT BUFFER THE END OF BLOCK aiii 40 FIG 4 8 OUTPUT BUFFER NOT VALID DATUM rererererersrererererererenerererensrererensrererenerererenerererererererersrereneserererererereseserererener 42 FIG 4 9 MULTI EVENT BUFFER DATA STRUCTURE EXAMPLE rervrvrvrvrerererererererererersrere
38. IGITAL CONVERSION esresvesvrsvennrnnrnnrrnrsnrsnrensrnsrensensensensensensensenvesnesnennennennrsnesnesnssnssnsssnsenssnsensenne 12 2 4 ZERO SUPPRESSION urnen che ca reke eien reiste edelt 12 25 OVERFLOW SUPPRESSION n kite aia 14 2 6 NOT VALID DATA SUPPRESSION csi diia 14 2 7 MULTIPLE EVENT BUFFER MEB ccccsssssssssssssscessescessessssecsecsscssesaessecaecsecseesecsessesseseseesesessesnsseeceesesseaeeaeess 15 2 8 EVENT COUNTER instansar tetas 16 2 9 BUSY LOGICA A EEE 16 2 10 ARESET LOGI E ss cca encase se ear ester 17 DA HASTCEEBAR unne SANSENE 18 3 TECHNICAL SPECIFICATIONS sessseensersesarseveseesseraesesennenesenasssvenesnsorsesenerseneneensssvenannsorsenssernseenesnsessensnenenenssessesenee 19 3 1 PACKAGING ENG 19 3 2 POWER REQUIREMENTS uns rer eee 19 3 3 FRONT PANEL purre kresen 20 3 4 EXTERNAL CONNECTOR sjiaer kerk raden 22 3 4 1 INPUT Connector as 22 3 4 2 CONTROL CONNECIO ennhe annuo a tdi 22 3 4 3 GATE COMMON connectors mr RERE oa Pea RN ada Hadas ooh A E E 23 3 5 OTHER FRONT PANEL COMPONENTS surse a E a a i 24 3 5 1 DISPLAYS hac oc EEEE dl 24 3 5 2 SWILCROS ee 25 3 6 INTERNAL HARDWARE COMPONENTS srrsnenvennrsnrnnrsnrsnesnsensenssnnsnnsnnsensensensensennennesnennennennrsnesnesnnsnssnnsnnsensensensenne 26 3 6 1 SWILCROS ud ass AE er 26 3 6 2 JUDAS A A AA Aisa 26 3 6 3 Soldering PASA aa 28 SET TECHNICAL SPECIFICATIONS TABLE ninia E tes IEA Aussie E 29 Ao NME INTERFACE risiaccssssscacssscicc
39. PT LEVEL REGISTER sein rn Gitarer E E ERa 45 4 11 INTERRUPT VECTOR REGISTER c ccccscsscsssssscesessssessssessessssessesesscscsscssescsscsssecsscsssesassecsesassecaesecnecaesecaecaesecaeenens 45 4 12 STATUS REGISTER Lips seere 46 4 13 CONTROL REGISTER di ea teeta 47 4 14 ADDRESS DECODER HIGH REGISTER ccccccscsssssssssessesessessssessesesccscsscsseecsscsssecssescsecassecsecassecsesecsecaesecaeceesecaeseees 48 4 15 ADDRESS DECODER LOW REGISTER cccccsssssssessssessesessessssessesesscsessessescsscsesecsscscsecaseecsecassecaesessscassecaecaesecaesnens 48 4 16 SINGLE SHOT RESET REGISTER 00 adds 49 4 17 MCST CBLT CONTROL REGISTER Qu c cccssssesssssssesssessseseeescsescecscsescscscsesesescseseecscucsesessecsesescuesesesceeeeeeseneeeesenees 49 4 18 GEVENT TRIGGER REGISTER hundene eierne treer anode 50 SI ISO IA 50 4 20 EVENT COUNTER LOW REGISTER ccccccsssssssessssessssessessssessesessescssesseccssesssecssesesscaseecsecassecsesecnscaesecnecaesecaestens 51 421 EVENT COUNTER HIGH REGISTER ada 51 4 22 INCREMENT EVENT REGISTER ui aia siders 52 4 23 INCREMENT OFFSET REGISTER c csccsssscsesssseesescssessssessesesessescsacsesacsseecsscsssecsscscsecaseecsecassecaesesnscaesecascaesecaeenens 52 4 24 FAST CLEAR WINDOW REGISTER c scscssssssscsssesssesssesesenssescssscssnsnesesssensseesecesssenecessscacencneseestcneseosecavetenesessuens 52 4 25 BIT SET REGISTER A Re NENS 53 4 26 BIT C FAR 2 REGISTER mn kaka 55
40. Register see 4 6 for data identification during CBLT operation see 4 1 4 it is incorrect to use the GEO Address Register for addressing purposes when there is no PAUX 4 1 3 Base GEO addressing examples The following is an example of Base GEO Addressing for two V775 boards inserted in a VME crate BOARD 1 BOARD 2 Upper Rotary Switches Lower bytes of Address Lower Rotary Switches Slots Upper bytes in the crate of Address pe 2fafefsf 7 ape frofrfrefrsfrrsfrefrafrefrsfeder Fig 4 3 Base GEO Addressing Example 1 If the board 1 and board 2 are respectively inserted in the slots 5 and 8 with the rotary switches for VME Base Addressing set as shown in the figure the complete address of the registers of the two boards will be as follows Board 1 Base addressing A32 OxEE000000 offset Base addressing A24 0x000000 offset GEO addressing A24 0x280000 offset Output Buffer excluded Board 2 Base addressing A32 0xCC110000 offset Base addressing A24 0x110000 offset GEO addressing A24 0x400000 offset Output Buffer excluded 4 1 4 MCST CBLT addressing When the Multicast Chained Block Transfer addressing mode is adopted the module works in A32 mode only The Address Modifiers codes recognised by the module are AM 0x0F A32 supervisory block transfer CBLT NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 72 32 CAER Document type Title Revisi
41. Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 4 5 Output Buffer Base Address 0x0000 0x0FFC read only This register allows the User to access the Multiple Event Buffer to readout the converted values The output buffer contains the output data organised in 32 bit words The data in the buffer are organised in events Each event consists of e the header that contains the geographical address the crate number and the number of converted channels e one or more data words each of which contains the geographical address the number of the channel the Valid V bit the Under Threshold UN bit the Overflow OV bit and the 12 bit converted value e the End Of Block EOB which contains the geographical address and the event counter dida ooo cc ole a aroma folie omme fofo ana Fig 4 5 Output buffer the Header V775 PRA seo olele ofo o aneren pole roca V775N dd le OG dd dd ad dd sea ole ieoi PR Jeff mans Fig 4 6 Output buffer the data word format dla ed fe ed GEO 4 0 1 fofo EVENT COUNTER 23 0 Fig 4 7 Output buffer the End Of Block NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 41 CAER Document type User s Manual MUT Title Revision date Revision Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 Header content The bits 31 27 contains the GEO address The bits 26 24
42. SS MAP IN MCST OPERATIONS sad nigel ancl vice awed Eee 39 TABLE 4 38 ROM ADDRESS MAP FOR THE MODEL V775 sssssssssssssssssssssesssssssssssscssssscssssssssssscssssscsssssseessssessssesssssesesssees 60 NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 72 7 CAL NI Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 1 General description 1 1 NPO Overview The Model V775 is a 1 unit wide VME 6U module housing 32 Time to Digital Conversion channels The Full Scale Range can be selected via VME from 140 ns to 1 2 us with 8 bit resolution The board can operate both in COMMON START and in COMMON STOP mode Each time interval between the COM signal and the input signal is converted to a voltage level by the TAC sections The outputs of the TAC sections are multiplexed and subsequently converted by two fast ADC modules 5 7 us conversion time The Model V775 N houses 16 channels on LEMO 00 connectors and shares most of its features with the Mod V775 Several versions are available refer to Table 1 1 Programmable zero suppression multievent buffer memory trigger counter and test features complete the flexibility of the unit The module works in A24 A32 mode The data transfer occurs in D16 D32 BLT32 or MBLT64 mode The unit supports also the Chained Block Transfer and the Multicast commands Table 1 1 Versions available for the Mode
43. T echnical Information M anual Revision n 10 10 September 2004 MOD V775 series MOD V775N series 32 16 CHANNEL MULTIEVENT TDCs MANUAL REV 10 NPO 00102 97 V 775x M UT x 10 CAEN will repair or replace any product within the guarantee period if the Guarantor declares that the product is defective due to workmanship or materials and has not been caused by mishandling negligence on behalf of the User accident or any abnormal conditions or operations CAEN declines all responsibility for damages or injuries caused by an improper use of the Modules due to negligence on behalf of the User It is strongly recommended to read thoroughly the CAEN User s Manual before any kind of operation CAEN reserves the right to change partially or entirely the contents of this Manual at any time and without giving any notice CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 TABLE OF CONTENTS 1 GENERAL DESCRIPTION esesesvsssvesessssenenessnseneneseerenenenssnenesensenenenenseneneneensnenensssenenenenseneneseenenesensssenesesenseneneseerenesensene 8 1 1 OVERVIEW AA arna er 8 1 2 BLOCK DIAGRAM vatn aa 9 2 PRINCIPLES OF OPERA TION pissesceseicccsssssscssscaccssctsedsescoensceesadensesss coseasadsnssessccsastecessesusdsedecesossesanasesesdestoscsbsns csscese 10 2 1 OPERATING MODE DESCRIPTION A OEE 10 22 TAG SECTIONS turens era aan seeks 10 2 3 ANALOG TO D
44. TEST ADC CONVERTED VALUE 11 0 Fig 4 31 Test Event Write Register 4 32 Event Counter Reset Register 4 33 NPO Base Address 0x1040 write only A VME write access to this dummy register clears the Event Counter Full Scale Range register Base Address 0x1060 read write A write access to this register allows the User to select the Full Scale Range from 140 ns 35 ps LSB to 1200 ns 300 ps LSB with 8 bit resolution esaeen of 2 7 6 5 4 8 2 iol FSR 7 0 Fig 4 32 Full Scale Range Register Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 58 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 The OxFF value corresponds to 35 ps LSB while the 0x1E value correspond to 300 ps LSB with a non linear interpolation for intermediate values the LSB is proportional to 1 N where N is the register content 4 34 R Memory Test Address Register Base Address 0x1064 write only This register contains the address of the output buffer from which data can be read for the estaben of 2 7 6 5 4 8 2 iol memory test R TEST ADDRESS 10 0 Fig 4 33 R Memory Test Address Register N B The output buffer is a FIFO so the read address R Test Address Register must be different from the write address W Test Address Register 4 35 SW Comm Register Base Address 0x1068 write only
45. Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 number of 32 MHz clock cycles a Fig 4 24 Fast Clear Window Register Please note that the maximum allowed value for N is 3FO which leads to Trc 38 5 us 4 25 Bit Set 2 Register Base Address 0x1032 read write This register allows to set the operation mode of the module A write access with a bit to 1 sets the relevant bit to 1 in the register A write access with the bit set to 0 does not clear the register content the Bit Clear 2 Register must be used see 4 26 A read access returns the status of the register The register content is the following rspiefisfiefisfrofs 8 7 6 5 4 2 2 110 MEM TEST OFFLINE CLEAR DATA OVER RANGE PROG LOW TRESHOLD PROG VALID CONTROL TEST ACQ SLD ENABLE RESERVED RESERVED START STOP AUTO INCR EMPTY PROG SLD SUB ENABLE ALL TRG Fig 4 26 Bit Set 2 register N B DON T MODIFY RESERVED BITS SETTINGS MEM TEST Test bit allows to select the Random Memory Access Test Mode see 5 5 1 0 normal mode default NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 54 CAER Document type Title User s Manual MUT Mod V775 Revision date Revision 16 32 Channel Multievent TDC 10 09 2004 10 1 Random Memory Access Test Mode selected it is possible to write directly into the memory OFFLINE Offline
46. a ec Fig 4 14 Interrupt Vector Register 4 12 Status Register 1 Base 0x100E read only This register contains information on the status of the module TERM ON and TERM OFF refer to the terminations of the CONTROL bus lines the last module in a chain controlled via the front panel CONTROL connector must have these terminations ON while all the others must have them OFF The insertion or removal of the terminations is performed via internal DIP switches see Fig 3 4 The BUSY and DATA READY signals are available both for the individually addressed module and as a global readout of a system of many units connected together via the CONTROL bus DREADY GLOBAL DREADY BUSY rsfrafrsfrafrifiofo el7 esja afef1 0 DREADY GLOBAL DREADY BUSY GLOBAL BUSY AMNESIA PURGED TERM ON TERM OFF EVRDY Fig 4 15 Status Register 1 Indicates that there are data at least 1 event in the Output Buffer 0 No Data Ready 1 Data Ready Indicates that at least one module in the chain has data in the Output Buffer OR of the READY signal of each module in the chain 0 No module has Data Ready 1 Atleast one module has Data Ready Busy status indicates that either a conversion is in progress or the board is resetting or the Output Buffer is full or the board is in MEMORY TEST mode 0 Module not Busy 1 Module Busy NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 47 C
47. abort the memorisation of data which originated an ADC overflow The control logic provides to check if the output of the ADC is in overflow and in the case the value is not stored in the memory The overflow suppression can be disabled by means of the OVER RANGE PROG bit of the Bit Set 2 Register see 4 25 if this bit is set to 1 all the data independently from the fact that they caused ADC overflow or not are stored in the memory In this case the 16 bit word stored in the memory will have the bit 12 OVERFLOW set to 1 see 4 5 2 6 Not valid data suppression NPO When the module works in Common Stop mode it may occur that a TAC output saturates before the arrival of a Stop signal in this case the TAC section resets itself through constant current capacitor discharge and after approximately 700 ns the channel is ready to accept a new Start signal If a Stop signal arrives when the TAC is resetting the datum is not valid this condition is flagged by the bit 14 of the data word see 4 5 Start Stop Full Scale Range TAC OUTPUT AUTO RESET Fig 2 6 TAC autoreset in Common Stop mode Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 72 14 CAE Rl Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 2 7 NPO The not valid data suppression can be disabled by means of the VALID CONTROL bit of the Bit Set 2 Re
48. address see 4 7 The user must perform a number of CBLT accesses that allows for the readout of all data in all boards of the chain in all possible occupancy conditions E g if the user has a chain of 10 boards the total number of words for a given event lies between 0 i e no data and 34x10 340 32 bit words i e each board has an event each event consists of a Header 32 data End of Block In the latter case in order to be sure that a BERR is generated the user must thus perform 11 CBLT accesses of 34 word each In CBLT32 mode the first board of the chain starts sending data if there are any i e if it is not purged see 4 12 as it has sent all data and the EOB is met the board becomes purged i e the relevant bit PURGED of the Status Register 1 is set to 1 This implies that the board will not be involved in the CBLT access any more since it has already sent all the required data At this point the IACKOUT line is asserted and the next board if not purged starts sending data As the last board receives the token and is purged it asserts a BERR which acts as a data readout completion flag In CBLT64 mode the accesses work as in the CBLT32 one except br the fact that the address is acknowledged during the first cycle and consequently a DTACK is asserted at least once In CBLT mode the Read Pointer must be incremented automatically if the AUTOINC_ENABLE bit is set to 1 in the Bit Set 2 Register see 4 25 the Read P
49. bit allows to select the ADC controller s status 0 ADC controller online default 1 ADC controller offline no conversion is performed CLEAR DATA Allows to generate a reset signal which clears the data the write and read pointers the event counter and the peak sections 0 no data reset is generated default 1 a data reset signal is generated OVER RANGE Allows to disable overflow suppression see also 2 5 0 over range check enabled only the data not causing the ADC overflow are written into the output buffer overflow suppression default 1 over range check disabled all the data are written into the output buffer no overflow suppression LOW THRESHOLD Allows to disable zero suppression see also 2 4 0 low threshold check enabled only data above the threshold are written into the output buffer zero suppression default 1 low threshold check disabled all the data are written into the VALID CONTROL TEST ACQ SLIDE ENABLE START STOP AUTO INCR output buffer no zero suppression Allows to abort memorisation of not valid data when working in Common Stop mode see 2 6 0 valid data check enabled only valid data are written into the output buffer 1 valid data check disabled all the data are written into the output buffer Allows to select the Acquisition Test Mode see 5 5 2 0 normal operation mode i e the data to be stored in the buffer are the real data default 1
50. ccasdoessadescaccscsssastoedscasadcedasieasusdessaseusuastcasatbcccndcatssesestecuddadbsdsatevsscccesansse des deria titii iiaeie 30 4 1 ADDRESSING CAPABILITY arrene een Sieh dE ees aa 30 ADL Addressing via BASE Address miii sein 30 NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 72 3 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 4 1 2 Addressing via geographical address srsrnrnrnrnvnvnrnenrnrnnnenennnenenenenenenevenenenesevenevevenenenesenenesesenenesesenenere 31 4 1 3 Base GEO addressing examples nrnrnrnonvnvnononvnvnonenenenenenenenenenenenenenenenenevenenenesenenenevenenenesenenesesenenenesenenere 32 4 1 4 MESTICBLT Ad dreSSME i 32 4 1 5 MCST CBLT addressing examples nierien taivar ai E E EA aR 34 4 2 INTERRUPTER CAPABILIT Yo kristin E A acess R E A E A R 36 4 2 1 Interrupt Status 1D n EE eee E E Ae veda aaa SE REN 36 4 2 2 TA AA TA OO 36 4 2 3 Interrupt GENE Haste cased sheen aoa 36 424 Interrupt Request Release irian tddi 36 43 DATA TRANSFER CAPABILITY enrorrornronrenvennenvennrnnrnnrsnesnesnrensensssnssnssnsenssnsensensenvennesnennennennesnesnesnnsnssnnssnssnssnssnsenne 36 4 4 REGISTER ADDRESS MAP att 36 4 5 OUTPUT BUFFER rei 40 4 6 GEO ADDRESS REGISTER cuca nit diia 43 41 MCSTEBLT ADDRESSsREGIS TERS ani 43 4 8 BIT SET 1 REGISTER 0 delas 44 4 9 BIT CEEAR L REGISTER ie 45 410 INTERRU
51. d V775 16 32 Channel Multievent TDC 10 09 2004 10 N B In CBLT operation the data coming from different boards are tagged with the HEADER and with the EOB words containing the GEO address in the 5 MSB see 4 5 In the versions without the PAUX connector it is up to the User to write the GEO address in the GEO register this operation is allowed only if the PAUX is not present before executing the CBLT operation If the GEO address is not written in the relevant register before performing the CBLT operation it will not be possible to identify the module which the data are coming from 4 1 5 MCST CBLT addressing examples The following is an example of MCST and CBLT addressing for four V775 boards plugged into a VME crate To access the boards the steps to be performed are as follows 1 Set the MCST address see 4 7 for all boards via VME Base Address or geographical addressing if available 2 Set the bits F_B and L_B of the MCST Control Register see 4 17 according to the operational status active or inactive of each board and to its position in the chain first intermediate or last 3 Write or read the boards via MCST CBLT addressing An example of User procedures which can be used to perform a write access is vme_write address data addr_mode data_mode which contain the following parameters Address the complete address i e Base Address offset Data the data to be either written or read Addr mode
52. d for the memory test The higher 16 bits are set via this register while the lower 16 bits are set via the Test Word Low Register These registers are used in TEST mode as follows set the module in test mode see bit 0 of the Bit Set 2 Register 4 25 write the memory address see 4 27 write the 16 MSBs in the TESTWORD_HIGH register write the 16 LSBs in the TESTWORD_LOW register Pon With the latter operation the 32 bit pattern is transferred to the memory If operations 3 and 4 are inverted the content of the 16 MSBs may be meaningless rsfrefssjeafrsroffefr sfsfa sfeft o TESTWORD 31 16 Fig 4 28 Test Word High Register 4 29 Memory Test Word Low Register Base Address 0x103A write only This register allows to set the lower 16 bits of the Memory Test Word see above rsfrafrsfrefrifiofofe r s sfe efe r o TESTWORD 15 0 Fig 4 29 Test Word Low Register 4 30 Crate Select Register Base Address 0x103C read write This register contains the number of the crate which the board is plugged into This register must be filled at board initialisation and will be part of the Header PEP EEE PEL IA semen Fig 4 30 Crate Select Register 4 31 Test Event Write Register Base Address 0x103E write only This register is used in Acquisition Test Mode and its content constitutes the test event to be written in the output buffer NPO Filename Number of pages Page 00102
53. d is either converting or resetting or in MEMORY TEST mode or the MEB is full BUSY status is also flagged by the bit 2 of the Status Register 1 when several boards are daisy chained the global OR and NAND of BUSY signals can be read respectively on the BUSY and BUSY lines of the CONTROL bus and the status of the BUSY bidirectional line is flagged by the bit 3 of the Status Register 1 see 4 12 The Mod V775 Nfeatures BUSY RST FCLR and VETO as standard NIM logic signals high impedance on a LEMO 00 connector each function and width of the control signals are the same as for the Mod V775 3 4 3 GATE COMMON connectors Mechanical specifications two 00 type LEMO connectors Electrical specifications NIM std input signals high impedance min width 10 ns If this input is used a 50 Q termination is required in daisy chain configuration the termination must be inserted on the last board of the chain GATE COMM NPO 00102 97 V775x MUTx 10 Filename Function Start or Stop input signal common to all channels In the Mod V775 this signal is internally OR wired with the COMMON of the CONTROL connector Number of pages Page V775 REV10 DOC 72 23 CAER Document type Title Mod V775 16 32 Channel Multievent TDC User s Manual MUT FCLR FCLR RST RST DRDY DRDY COM COM GATE not used GATE not used VETO VETO BUSY BUSY not connected not connected Revision da
54. dding a known value to the analog level to be converted thus spanning different ADC conversion regions with the same analog value The known level is then digitally subtracted after the conversion and the final value is sent to the threshold comparator If the sliding scale is enabled it reduces slightly the dynamic range of the ADC the 12 bit digital output is valid from 0 to 3840 while the values from 3841 to 4095 are not correct From MUXes to the memories SLIDE SUB ENABLE Fig 2 3 Block diagram of the sliding scale section 2 4 Zero suppression NPO The output of the ADC is fed to a threshold comparator to perform the zero suppression If the converted value from a channel is greater than or equal to the relevant low threshold value set via VME in the Thresholds memory Base Address 0x1080 0x10BF see 4 39 the result is fed to the dual port memory and will be available for the readout Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 72 12 CAL NI Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 If the converted value is lower than the threshold the value is stored in the memory only if the LOW TRESHOLD PROG bit of the Bit Set 2 Register is set to 1 see 4 25 The fact that the converted value was under the threshold is also flagged in the datum stored in the memory where the bit 13 UNDERTHRESHOLD of
55. dress of the module can be fixed in two ways e by four rotary switches e by writing the Base Address in the ADER_HIGH and ADER_LOW registers The 4 rotary switches for Base Address selection are housed on two piggy back boards plugged into the main printed circuit board see Fig 3 4 NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 72 30 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 NPO To use this addressing mode the bit 4 of the Bit Set 1 Register see 4 8 must be set to 0 This is also the default setting The module Base Address can be also fixed by using the Ader_High and Ader_Low Registers These two registers set respectively the A 31 24 and the A 23 16 VME address bits see 4 14 and 4 15 To use this addressing mode bit 4 of the Bit Set 1 Register see 4 8 must be set to 1 4 1 2 Addressing via geographical address The module works in A24 mode only The Address Modifiers codes recognised by the module are AM 0x2F A24 GEO access All registers except for the Output Buffer i e the CR CSR area can be accessed via geographical addressing The geographical address is automatically read out at each RESET from the SN5 SN1 lines of the PAUX connector Each slot of the VME crate is identified by the status of the SN5 SN1 lines for example the slot 5 will have these lines respectively at 0010
56. dy to accept data MEB Full or when the board is in Random Memory Access Test mode see 5 5 1 On the occurrence of one of these conditions the front panel BUSY signal CONTROL bus is active the red BUSY LED is on and the bit 2 BUSY and bit 3 GLOBAL BUSY of the Status Register 1 are set to 1 see 4 12 The BUSY LED lights up also while the board is configuring power ON Actually each module sets to 1 its BUSY output after the leading edge of a pulse on the COMMON input module busy and releases it to 0 at the end of the conversion sequence When the module is busy it does not accept another COMMON pulse Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 72 16 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 The jumper J12 placed on the PCB see Fig 3 4 allows to select board behaviour in response to a BUSY status if this jumper is set to EXTBSY the acquisition is stopped as soon as any of the boards on the Control bus is BUSY if the jumper is set to INTBSY acquisition is stopped as the board is BUSY 2 10 Reset Logic Three different types of RESET operations can be distinguished according to the effects they have on the module and particularly on the registers These are e TypeA Data RESET e TypeB Software RESET e TypeC Hardware RESET The Data RESET clears the data in the output buffer resets the
57. e type of word 100 gt EOB The bits 23 0 contain the 24 bit event counter value see 4 20 The bits 31 27 always contains the GEO address except for the not valid datum see Fig 4 8 The bits 26 24 identify the type of word according to the following NPO 010 gt header 000 gt valid datum 100 gt end of block 110 gt not valid datum others gt reserved Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 42 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 If a read access is performed to the buffer when it is empty the readout will provide a NOT VALID DATUM arranged as shown in Fig 4 8 ee e eae reel rf ref e 4 3 2 0 C o Fig 4 8 Output buffer not valid datum The sequence followed to store the data in the buffer is as follows V775 V775N CHANNEL 0 CHANNEL 0 CHANNEL 16 CHANNEL 8 CHANNEL 1 CHANNEL 1 CHANNEL 17 CHANNEL 9 CHANNEL 2 CHANNEL 2 CHANNEL 15 CHANNEL 7 CHANNEL 31 CHANNEL 15 Please note that some of the above channel data may be missing in the sequence this is due either to overflow or under threshold conditions which caused these data not to be stored or to User s settings to kill some channels Fig 4 9 shows an example of the Multi Event Buffer structure in case of zero suppression enabled and with event counter set so as to count all events see
58. ent TDC 10 09 2004 10 LIST OF FIGURES FIG 1 1 MODEL TYPE LABEL EXAMPLE V775AC scssssccssssseccscseseccncsesecencnesecencaesecencnesecencaeseceacaeseeeacarseeencaeseeeneaeaeeeaes 8 FIG 1 2 MODEL V775 32 CHANNEL BLOCK DIAGRAM csssssscsssssseecsesesecencsesecencaesecencaesesencaesecencaeseecacaeseeencaeseeeneataeeeaes 9 FIG 2 1 SIMPLIFIED BLOCK DIAGRAM OF THE TAC SECTION rasesvenrvevrenrvevsvrrssnevrsesrenevessenevensersvenevssesnenasessenevensensvenee 10 FIG 2 2 SIGNAL CONVERSION TIMING IN COMMON STOP MODE esrvesrvnrvevvvrrssnevssesrenasessenevensersvevevssasnenasessenevensensvenee 11 FIG 2 3 BLOCK DIAGRAM OF THE SLIDING SCALE SECTION ssevevovvonrvesrenrvansvrsssnevssesrenasessenevensersvenevssesnenasesvenevenseneveneee 12 FIG 2 4 ZERO SUPPRESSION BIT 8 OF BIT SET 2 REGISTER 0 DEFAULT SETTING rerererrervrervrererererererererersrererer 13 FIG 2 5 ZERO SUPPRESSION BIT 8 OF BIT SET 2 REGISTER 1 nnrererervrvrvrvrrvrererererererererererererererererererererererererererrener 13 FIG 2 6 TAC AUTORESET IN COMMON STOP MODE rerererererererererererenerererererererenererererererererererererererereserererererereresersrerener 14 FIG 2 7 MULTI EVENT BUFFER WRITE POINTER AND READ POINTER rerorornovrvevrenevevsenrvensvrsvevevssesnenavesvensvensensvenee 15 FIG 2 82 FAST CLEAR MIND ii 18 FIG 3 1 MODEL V7 5 FRONT PANEL svcsissstsisesdessavesctocexnsdeavesveetooy AOE RE R A a en dass teases 20 FIG 3 2 MODEL V779 N
59. f the module The register content is the following psfrafrsfrafrifiofofe r s sfe efe r o Fig 4 18 ADER LOW Register 4 16 Single Shot Reset Register Base Address 0x1016 write only A write access to this dummy register performs a module reset This register must be used very carefully and for debugging purposes only In order to reset the board it is recommended to use the Bit Set 1 Register see 4 8 4 17 MCST CBLT Control Register Base Address 0x101A read write This register allows performing some general MCST CBLT settings of the module rsfrafrsfrafripiofo e rs s a a 2 1 fol LAST BOARD FIRST BOARD Fig 4 19 MCST Address Register LAST BOARD Last Board flag bit valid in CBLT and MCST modes only FIRST BOARD First Board flag bit valid in CBLT and MCST modes only The status of the boards according to the bit value is the following BOARD STATUS FIRST BOARD LAST BOARD bit bit Board disabled in CBLT or MCST chain First board in CBLT or MCST chain Active intermediate board in CBLT or MCST chain 1 HE Last board in CBLT or MCST chain ET 1 MERA Bits 2 to 15 are meaningless NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 50 CAEN Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 4 18 Event Trigger Register Base Address 0x1020 read write This register conta
60. gister see 4 25 if this bit is set to 1 all the data are however stored in the memory Multiple Event Buffer MEB After the conversion if there is at least one converted value above the programmed threshold not causing overflow and not killed the control logic stores it in the Multi Event Buffer MEB The Multi Event Buffer is a Dual Port FIFO Memory 34 Words event which can store up to 32 events It is available at the VME address Base Address 0x0000 0x0FFC see also 4 5 In order to trace the event flow two pointers Read and Write pointer are employed The Read Pointer points to the active read buffer The Write pointer is incremented automatically via hardware at the end of the channels conversion while the Read pointer can be either incremented automatically AUTO INCR bit of the Bit Set 2 Register set to 1 see 4 25 or via write access to one of two dummy registers Increment Event and Increment Offset Registers see 4 22 and 4 23 These allow to move the readout pointer to the next event in the output buffer or to the next word respectively WRITE POINTER READ POINTER l BUFFER 0 BUFFER 1 BUFFER 2 BUFFER 14 BUFFER 15 Fig 2 7 Multi Event Buffer Write pointer and Read pointer The MEB can be either in a Full a Not empty or an Empty status When the 5MSB of the Read pointer and the 5MSB of the Write pointer are different i e point to different events the MEB is in a N
61. he two modes can be selected via the Bit 14 ALL TRG of the Bit Set 2 Register see 8 4 25 EVENT CNT LOW 16 LSB of the 24 bit Event Counter Tee Fig 4 22 Event Counter Low Register This register is reset via the Event Counter Reset Register see 4 32 or via a software or hardware reset see 2 10 However if the event counter is set so as to work as relative counter i e it counts only the accepted events this register is reset also with a data reset see 2 10 4 21 Event Counter_High Register Base 0x1026 read only It contains the 8 MSB of the 24 bit event counter The event counter can work in two different ways see also 2 8 1 it counts all events 2 it counts only the accepted events NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 52 CAEN Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 The two modes can be selected via the Bit 14 ALL TRG of the Bit Set 2 Register see 4 25 EVENT CNT HIGH 8 MSB of the 24 bit Event Counter PPT PPP PEELE EL as Fig 4 23 Event Counter High Register This register is reset via the Event Counter Reset Register see 4 32 or via a software or hardware reset see 2 10 However if the event counter is set so as to work as relative counter i e it counts only the accepted events this register is reset also with a
62. ia the MCST CBLT Address Register see 4 7 This means that all boards must have the same setting on bits 31 to 24 The resulting MCST CBLT Base Address for all boards is MCST CBLT Base Address 0xNNO00000 Once the addresses have been set the first and last board in a chain must have respectively only the FIRST BOARD and only the LAST BOARD bit set to 1 in the MCST Control Register see 4 7 Conversely all intermediate boards must have both the FIRST BOARD and the LAST BOARD bits set either to 1 or to 0 5 7 1 Chained Block Transfer Mode Once set the address of the boards as described in the above section the boards can be accessed in Chained Block Transfer mode CBLT see 5 This mode allows for sequential readout of a certain number of contiguous boards in a VME crate A CBLT access is allowed with the BLT32 and MBLT64 address modifiers only CBLT32 and CBLT64 accesses respectively N B The CBLT operation can be performed only for the readout of the Multi Event Buffer its address in CBLT mode corresponds to the set of offsets listed in Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 68 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 NPO Table 4 3 to be added to the address common to all boards set by the user via the MCST CBLT Address Register which contains the most significant bits of the
63. ins a 5 bit value set by the user when the number of events stored in the memory equals this value an interrupt request is generated Default setting is 0 in this case the interrupt generation is disabled See also 4 2 psrejra 2 11 10 9 8 7 fe se of fo EV TRG 4 0 Fig 4 20 Event Trigger Register 4 19 Status Register 2 Base Address 0x1022 read only This register contains further information on the status of the module output buffer and on the type of piggy back plugged into the main board 35 ett B18 8 8 210 RESERVED BUFFER EMPTY BUFFER FULL RESERVED DSELO DSEL1 CSELO CSEL1 RESERVED RESERVED NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 51 CAE Rl Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 Fig 4 21 Status Register 2 BUFFER EMPTY Indicates if the output buffer is empty 0 buffer not empty 1 buffer empty BUFFER FULL Indicates if the output buffer is full 0 buffer not full 1 buffer full CSEL1 CSELO DSEL1 DSELO Indicate the type of piggy back plugged into the board In the case of V 775 is 0000 4 20 Event Counter_Low Register Base Address 0x1024 read only It contains the 16 LSBs of the event counter The event counter can work in two different ways see also 2 8 1 it counts all events 2 it counts only the accepted events T
64. is not available Although in these versions it is possible to perform a write access to the GEO Address Register for data identification during CBLT operation see 4 1 4 avoid to use the GEO Address Register for addressing purposes when there is no PAUX N B after a write access to the GEO Address register it is necessary to perform a reset to make the change active 4 7 MCST CBLT Address Register NPO Base Address 0x1004 read write Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 44 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 This register contains the most significant bits of the MCST CBLT address of the module set via VME i e the address used in MCST CBLT operations Refer to 4 1 4 for details about MCST CBLT addressing mode The register content is the following nshabshahole a 7 s sfetsfef1 MCST CBLT ADDR 0 MCST CBLT ADDR 1 MCST CBLT ADDR 2 MCST CBLT ADDR 3 MCST CBLT ADDR 4 MCST CBLT ADDR 5 MCST CBLT ADDR 6 MCST CBLT ADDR 7 Fig 4 11 MCST CBLT address register Default setting i e at power ON or after hardware reset is OxAA 4 8 Bit Set 1 Register Base Address 0x1006 read write This register allows to set the RESET logic of the module and to enable the change of the base address via VME A write access with the bits to 1 sets the relevant bits to 1 in the registe
65. l V775 Version Number of PAUX 5 V DC DC Live insertion channels connector converter uae WV775XACAAAA DATE MAY 9th 2002 Fig 1 1 Model type label example V775AC A label on the printed board soldering side indicates the module s version see Fig 1 1 all the versions share the same features except where indicated The version with the PAUX connector requires the V430 backplane Model available exclusively on request Filename Number of pages Page 8 00102 97 V775x MUTx 10 V775_REV10 DOC 72 CTA Document type Title Revision date User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 1 2 Block diagram Piggy back boara BLOCK A 12 bit ADC amp sliding TAC 12 I TAC 13 1 TAC 14 E THRESHOLD TAC 15 COMPARATOR 12 bit ADC 8 sliding CONTROL LOGIC DUAL PORT MEMORY ACQUISITION CONTROL VME INTERFACE Front panel Fig 1 2 Model V775 32 channel Block Diagram Revision 10 NPO Filename Number of pages Page 9 00102 97 V775x MUTx 10 V775_REV10 DOC 72 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 2 Principles of operation 2 1 2 2 NPO The board has 32 16 for the Mod V775 N channel inputs and one COM input ECL NIM common to all channels The Mod V775 N does not feature the ECL GATE input The time intervals between the input and
66. le 56 FIG 4 31 TEST EVENT WRITE REGISTER Ne 57 FIG 4 32 FULL SCALE RANGE REGISTER s ger ee eaiaieibe ta veeeeashoen asinine 57 FIG 4 33 R MEMORY TEST ADDRESS REGISTER ssssssssssesssssessssssesssssessssuecsssssecssssccsssecssssssessssesssssesessuecessssecsssesessseceessees 58 FIG 4 34 SLIDE CONSTANT REGISTER Se 58 PIG 155 AAD REGISTER A 59 FC GB DREG ER pes 59 FIG 4 37 THRESHOLD REGISTER AN A A 59 FIG At VME CYCLE TIMING IN D16 MODE Sag is 70 FIG A 2 VME CYCLE TIMING IN BLT CBLT MODE eee aid 70 FIG A 3 VME CYCLE TIMING IN MBLT CBLT64 MODE sscssssssssssssssssssessssssessssscssssscessssccssssecsssscsesssssssssecsssessssseeeessees 71 LIST OF TABLES TABLE 1 1 VERSIONS AVAILABLE FOR THE MODEL V775 ssssssssssssssssssssssssssssessssssssssucsessssesssscssssucessusesssssesssuescssseseessesess 8 TABLE 3 1 MODEL V775 POWER REQUIREMENTS id 19 TABLE 3 2 MODEL V775 TECHNICAL SPECIFICATIONS sssssssssssssssssssssessssssccsssscssssscesssscessssccsssscsesssscessssecsssessssseeesssees 29 TABLE 4 1 MODULE RECOGNISED ADDRESS MODIFIER sssssssssssssssssssssesssssssssssscssssecsssssecssssesssssesessueeessssecssesessseceessess 30 TABLE 4 2 ADDRESS MAP FOR THE MODEL V77D cssssssssssssssssssssssssssssesssssscsssssessssscssssscessussessssessssscsessuseessssessssesssssecesssess 38 TABLE 4 3 ADDRESS MAP IN CBLT OPERATION ssssssssssssssssssssssscssssesssssecsssusecsssscssssscsssssscssssesssssccessueesssecsssesssssecesssees 39 TABLE 4 4 ADDRE
67. lease note that the R Memory Test Address must be different from the W Memory Test Address at any step of the procedure If the user tries to write an address in one of these registers that is equal to the address contained in the other register write cycles step 3 above will not write the correct value 5 5 2 Acquisition Test Mode This test mode allows the User to simulate the real operation of the board without using any channel input signals but just writing the data into a FIFO via an appropriate register Test Event Write Register see 4 31 and reading them after a COM signal To operate the acquisition test follow these steps 1 Reset the board 2 Set to 1 the Bit 5 VALID CONTROL of the Bit Set 2 Register see 4 25 NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 65 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 NPO Set to 1 the Bit6 TEST ACQ of the Bit Set 2 Register see 4 25 this action selects the Acquisition Test Mode and resets the write pointer in the FIFO Set to 0 the Bit 6 TEST ACQ of the Bit Set 2 Register by using the Bit Clear 2 Register see 4 25 and 4 26 this action resets the read pointer in the FIFO and releases the write pointer Write 32 data words each word consisting of a 13 bit word corresponding to the ADC converted value the overflow bit see 4 31
68. o 0 indicates an uncommon termination status e g some terminations are on and other are off 4 13 Control Register 1 Base Address 01010 read write This register allows performing some module s general settings RANN BLKEND PROG RESET BERR ENABLE ALIGN64 NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 48 CAEN Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 BLKEND PROG RESET BERR ENABLE ALIGN 64 Fig 4 16 Control Register 1 End of Block bit Used in Block Transfer modes only 0 The module sends all requested data to the CPU when the Output Buffer is empty it will send no valid data If BERR_VME is enabled see bit 5 below BERR ENABLE a Bus Error is generated with the readout of the last word in the Output Buffer default 1 The module sends all data to the CPU until the first EOB word end of first event is reached afterwards it will send no valid data If BERR VME is enabled a Bus Error is generated at the readout of the EOB word Programmable Reset Mode setting bit 0 the front panel RESET acts only on data data reset default 1 the front panel RESET acts on the module software reset N B This bit is cleared only via hardware reset Bus Error enable bit Used in Block Transfer mode only 0 the module sends a DTACK signal until the CPU inquires the module defaul
69. ointer is automatically incremented with the readout of the End Of Block word of each board if the AUTOINC_ENABLE bit is set to 0 the Read Pointer is not automatically incremented and only the Header of the first word is read N B Please note that according to the VME standard a Chained Block Transfer readout can be performed with 256 read cycles maximum as a consequence a readout with a greater number of read cycles may require more CBLT operations This limit is not due to the board itself but only to the VME standard it is actually possible to performed a CBLT readout with more than 256 read cycles if the timeout of the BUS Timer BTO x is disabled or delayed If the latter action is not allowed and the CBLT readout stops before having read all data the new CBLT cycle will start from where the token was left in the previous cycle this goes on until the last board is reached and all data read so that a BERR is generated 5 7 2 Multicast Commands Once set the address of the boards as described in 5 7 the boards can be accessed in Multicast Commands MCST mode The MCST mode allows to write in the registers of several boards at the same time by accessing a dummy Address only once The latter is composed by the MCST Base Address plus the offset of the relevant register according to the list shown in Table 4 4 Refer to 4 1 4 for details on MCST addressing mode MCST access can be meaningless even if possible for the setting
70. on date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 NPO AM 0x0D A32 supervisory data access MCST AM 0x0B A32 User block transfer CBLT AM 0x09 A32 User data access MCST The boards can be accessed in Multicast Commands mode MCST mode see 4 that allows to write in the registers of several boards at the same time by accessing the MCST Base Address in A32 only once The boards can be accessed in Chained Block Transfer mode CBLT mode see 4 that allows to readout sequentially a certain number of contiguous boards in a VME crate This access is allowed in BLT32 and BLT64 modes only to the MCST Base Address N B The Base Address used for MCST and CBLT operations is the same i e throughout this User s Manual the MCST Base Address identifies the same Address used both for MCST commands in Write only and the CBLT Readout in Read only for the Output Buffer only The MCST Base Address must be set in a different way from the ordinary Base Address Its most significant byte i e bits 31 through 24 must be written in the MCST CBLT Address Register see 4 7 and must be set in common to all boards belonging to the MCST CBLT chain i e all boards must have the same setting of the MCST CBLT Base Address on bits 31 through 24 The default setting is OxAA In CBLT MCST operations the IACKIN IACKOUT daisy chain is used to pass a token from one board to the following one The board
71. ot empty status When the Read pointer and the Write pointer are equal the MEB can be either in a Full or an Empty status The MEB is full or empty according to the last increment pointer operation performed if the last increment is the one of the Write pointer the MEB is Full if the last increment is the one of the Read pointer the MEB is Empty The status of the MEB is monitored via two Registers the Status Register 1 and the Status Register 2 see 4 12 and 4 19 respectively After the conversion the accepted data i e the converted values above the programmed threshold not causing overflow and not killed are stored in the active event buffer i e the Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 72 15 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 2 8 2 9 NPO one pointed by the write pointer in subsequent 32 bit words These are organised in events Each event consists of a Header see Fig 4 5 a block of data words Fig 4 6 and an End Of Block EOB word Fig 4 7 Each event contains thus from a minimum of 3 32 bit words Header one data word and EOB to a maximum of 34 32 bit words Header 32 data words and EOB In case there are no accepted data the user can choose to store anyway in the MEB the Header and the EOB relative to the event see EMPTY PROG bit of the Bit Set 2 Register
72. r i e writing 0x10 to this register sets the SEL ADDR bit to 1 write access with the bits set to 0 does NOT clear the register content in other words when 1 is written into one particular bit such bit is set to 1 if 0 is written the bit remains unchanged In order to clear the register content the Bit Clear 1 Register must be used see 4 9 read access returns the status of this register The register content is the following psfrefisfrefifio se fe sf 3 2 fo BERR FLAG SEL ADDR SOFT RESET Fig 4 12 Bit Set 1 Register NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 45 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 BERR FLAG Bus Error Flag Bit meaningful in BLT CBLT modes only The User may set this flag for test purposes only Its content is cleared both via an hardware and via a software reset 0 board has not generated a Bus Error default 1 board has generated a Bus Error SELECT ADDRESS Select Address bit 0 base address is selected via Rotary Switch default 1 base address is selected via internal ADER registers SOFTW RESET Sets the module to a permanent RESET status The RESET is released only via write access with the relevant bit set to 1 in the Bit Clear Register see 4 9 This register is reset via a hardware reset see 2 10 Only the bit 3 BERR FL
73. read and write pointers the event counter and the TAC sections It does not affect the registers This type of RESET can be forwarded in two ways 1 setting the Bit 2 CLEAR DATA of the Bit Set 2 Register to 1 see 4 25 the Reset is released via the Bit Clear 2 Register see 4 26 2 sending a RESET pulse from the front panel with the Bit 4 PROG RESET of the Control Register 1 set to 0 see 4 13 The Software RESET performs the same actions as the data RESET and moreover it resets the registers marked in the column SR Software Reset in Table 4 2 This type of RESET can be forwarded in three ways 1 setting the Bit 7 SOFTWARE RESET of the Bit Set 1 Register to 1 see 4 8 this sets the module to a permanent RESET status which is released only via write access with the relevant bit set to 1 to the Bit Clear 1 Register 2 sending a RESET pulse from the front panel with the Bit 4 PROG RESET of the Control Register 1 set to 1 see 4 13 3 performing a write access to the Single Shot Reset Register see 4 16 the RESET lasts as long as the write access itself The Hardware RESET performs the same actions as the Software RESET and moreover it resets further registers All the registers reset by a Hardware RESET are marked in the column HR Hardware Reset in Table 4 2 This type of RESET is performed 1 at Power ON of the module 2 via a VME RESET SYS RES At power ON or after a reset the module
74. rerererererererereserererersreresersrsrerener 42 FIG 4 10 GEOGRAPHICAL ADDRESS REGISTER ererersrvrvrerererererrererererererererenerererererererenerererererererenerererenerererererererererererener 43 FIG 4 11 MCST CBLT ADDRESS REGISTER errori i er e E E EEO ERORE ERR ORN 44 FIG 4 12 BIT SET 1 REGISTER aniier isi E EE E AS OEA R EE RAKE E E 44 FIG 413 SINTERRUPT LEVEE REGISTER npin aeara a a e R E A E EE EES E 45 FIG 4 14 INTERRUPT VECTOR REGISTER crenn oarenien riia i TE EA ERE O REANA AT 46 FIG 4 15 STATUS REGISTER I animeen rater 46 FIG 4 16 CONTROL REGISTER Livio et obiten cages niia 48 FIG 4 177 ADER HIGH REGISTER catas aa 48 FIG 4 18 ADER EOW REGISTER iii 49 FIG 4 19 MEST ADDRESS REGISTER ii a ridders 49 NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 72 6 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 FIG 4 20 EVENT TRIGGER REGISTER eee 50 PIG 4 2 STATS REGIS Te SN NE 51 FIG 4 22 EVENT COUNTER LOW REGISTER andere 51 FIG 4 23 EVENT COUNTER HIGH REGISTER aaa 52 FIG 4 24 FAST CLEAR WINDOW REGISTER a 53 PIG 426 EM MS MLA ES SE AA A A A 53 FIG 4 27 W MEMORY TEST ADDRESS REGISTER s sssssssssssessssssssssssesssssecsssssecsssscssssscssssssessssesssssesessscessseessssessssuecessnees 55 FIG 4 28 TEST WORD HIGH REGISTER ane 56 ICAA TEST WORD LOW eee e dd 56 FIG 4 30 CRATE SELECT REGISTER seede k
75. rn the board off and switch it on again Sometimes it may happen that the OVC PWR LED is orange as soon as the board is inserted in the crate this is due to the fact that the board has been just misplaced into the crate In this case extract the board and insert it again into the crate 5 3 Power ON status At power ON the module is in the following status the Event Counter is set to 0 the Output buffer is cleared the Read and Write Pointer are cleared i e Buffer 0 is pointed the Interrupt Level is set to 0x0 in this case interrupt generation is disabled and the Interrupt Vector is set to 0x0 the values in the threshold memory are not defined see 4 39 the MCST CBLT address is set to OxAA Moreover all other registers marked in the column HR Hardware RESET in Table 4 2 are cleared or set to the default value At power on or after a hardware reset see 2 10 the module must thus be initialised NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 63 CAL Rs Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 5 4 Operation sequence After the power ON sequence the module is in the status described above Please note that the threshold values are not defined after power ON and consequently before starting the operation of the module it is necessary to set a threshold value for each channel in the Threshold
76. s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 5 5 Test Modes Two different test modes can be enabled e Random Memory Access Test Mode e Acquisition Test Mode The first test mode operation is enabled via the Bit 0 of the Bit Set 2 Register and allows to write directly into the buffer The second test mode is enabled via the Bit 6 of the Bit Set 2 Register and allows to test the whole acquisition system by writing a set of 32 data in an internal FIFO which are then transferred to the output buffer at each COM pulse for the readout The test modes will be described in detail in the following subsections 5 5 1 Random Memory Access Test Mode This test mode allows the user to write and read a word in the output buffer To perform such test follow these steps 1 Reset the board Set to 1 the Bit 0 of the Bit Set 2 Register see 4 25 Write into the W Memory Test Address Register see 4 27 the 11 bit address where to write the test word 4 Write the high and low part of the 32 bit test word respectively in the Test Word_High and Test Word_Low Registers see 4 28 and 4 29 As the Test Word_Low register is accessed the whole test word is written into the memory 5 Write in the R Test Address Register see 4 34 the 11 bit reading memory address and read out the buffer please note that this address must be different from the write address written in the W Memory Test Address Register N B p
77. s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 A 3 VME Cycle timing in MBLT CBLT64 mode The figure below reports the Data Select DS Data Acknowledge DTACK VME cycle in MBLT CBLT64 mode and relative timing The theoretical minimum duration of the VME cycle in MBLT CBLT64 mode is 120 15 ns Fig A 3 VME cycle timing in MBLT CBLT64 mode NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 72 CAL NI Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 6 References 1 C Cottini E Gatti V Svelto A new method of analog to digital conversion NIM vol 24 p 241 1963 2 C Cottini E Gatti V Svelto A sliding scale analog to digital converter for pulse height analisys in Proc Int Symp Nuclear Paris Nov 1963 3 G Bianchetti et al Specification for VMEbus CRATE Type V430 CERN EP January 1990 4 VME64 extensions draft standard Vita 1 1 199x draft 1 8 June 13 1997 5 VMEBus for Physics Application Recommendations amp Guidelines Vita23 199x draft 1 0 22 May 1997 Both documents are available from URL http www vita com NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 73
78. t 1 the module is enabled to generate a Bus error to finish a block transfer Allows to add a 32 bit dummy word marked as not valid datum see 4 5 to an event which is made up of an odd number of words during BLT32 and CBLT32 data readout In fact some 64 bit CPU s cut off the last 32 bit word of a transferred block if the number of words composing such block is odd so it is necessary to add a dummy word which will be then eventually removed via software in order to avoid data loss It is used in BLT32 and CBLT32 and is available in Firmware Rev 6 02 and later 0 no dummy word added default 1 dummy word added when the number of words is odd Bits 7 to 15 are meaningless 4 14 Address Decoder High Register Base Address 0x1012 read write This register contains the A31 A24 bits of the address of the module it can be set via VME for a relocation of the Base Address of the module The register content is the following psfrafrsfrefrifiofo e r s sfe efe rfo Fig 4 17 ADER HIGH Register 4 15 Address Decoder Low Register Base Address 0x1014 read write NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 73 49 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 This register contains the A23 A16 bits of the address of the module it can be set via VME for a relocation of the Base Address o
79. t commands D16 D32 BLT32 MBLT64 CBLT32 CBLT64 Control inputs Control outputs VME interface if sliding scale is enabled FSR is reduced from 4095 to 3840 counts gt measured from 5 to 95 of FSR 3840 counts NPO Filename Number of pages Page 00102 97 V775x MUTx 10 V775 REV10 DOC 72 29 CAER Document type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 4 VME interface 4 1 Addressing capability The modules can be addressed in three different ways specifically 1 via Base Address 2 via GEOgraphical address 3 via Multicast Chained Block Transfer addressing mode 4 1 1 Addressing via Base Address The module works in A24 A32 mode This implies that the module s address must be specified in a word of 24 or 32 bit The Address Modifier codes recognised by the module are summarised in Table 4 1 Table 4 1 Module recognised Address Modifier A24 supervisory block transfer BLT A24 supervisory data access A24 supervisory 64 bit block transfer MBLT A24 non privileged block transfer BLT A24 non privileged User data access BLT A24 non privileged 64 bit block transfer MBLT A32 non privileged 64 bit block transfer MBLT The Base Address can be selected in the range 0x000000 lt gt 0xFF0000 A24 mode 0x00000000 lt gt OxFFFFO000 A32 mode Configuration Rom Control amp Status Register CR CSR The Base Ad
80. ta are coming from when the CBLT access is used 4 6 GEO Address Register Base Address 0x1002 read write write cycles are allowed only for the versions without PAUX connector This register contains the geographical address of the module i e the slot number picked up from the JAUX connector on the VME backplane The register is filled up upon arrival of a RESET The register content is the following rsfrafrsfrafrsfiofofe r e sfe sfefi fo GEO ADDR 0 GEO ADDR 1 GEO ADDR 2 GEO ADDR 3 GEO ADDR 4 Fig 4 10 Geographical address register GEO 4 0 corresponds to A23 A19 in the address space of the CR CSR area each slot has a relevant number whose binary encoding consists of the GEO ADDR 4 to 0 In the versions without the PAUX connector this register can be also written see also AMNESIA bit in the Status Register 1 refer to 4 12 The bits of the GEO Address register are set to 1 by default In CBLT operation it is up to the User to write the correct GEO address of the module in this register before operating so that the GEO address will be contained in the HEADER and the EOB words for data identification If a write access to the GEO register is performed in the versions with the PAUX connector the module does not respond and the bus will go in timeout N B In the case of versions where the SN5 SN1 lines are not available i e the versions without the PAUX connector addressing via geographical address
81. te 10 09 2004 10 Fig 3 3 CONTROL connector pin assignment V775 only 3 5 Other front panel components 3 5 1 Displays The front panel refer to Fig 3 1 hosts the following LEDs DTACK BUSY DRDY TERM OVC PWR NPO 00102 97 V775x MUTx 10 Colour green Revision Filename Function DATA ACKNOWLEDGE command it lights up each time a VME access is performed Colour red Function it lights up each time the module is performing a conversion or resetting the analog section or in memory TEST mode or when the Multi Event Buffer is full it also lights up for a while at power ON to indicate that the board is configuring Colour yellow Function it lights up when at least one event is present in the output buffer it also lights up for a while at power ON to indicate that the board is configuring Colour orange green red Function it lights up green when all the lines of the control bus are terminated red when no line of the control bus is terminated If only some lines are terminated it is off It also lights up orange for a while at power ON to indicate that the board is configuring Colour green orange Function it lights up green when the board is inserted into the crate and the crate is powered up when it is orange it indicates that there is an over current status in this case Number of pages Page V775 REV10 DOC 72 24 CAER Document type Title Revision date Revision
82. the 16 bit data word is set to 1 see 4 5 The Thresholds memory allows to set a low threshold value for each channel Default setting corresponds to thresholds not defined By setting the bit 8 in the Bit Set 2 Register it is possible to program the Threshold values in 16 ADC counts steps over the entire full scale range or in 2 ADC counts steps over 1 8 of full scale range In more detail if Bit 8 0 default value the comparison is performed between the 8 MSB of each 12 bit converted value and the 8 bit threshold value which is stored in the relevant register as illustrated in Fig 2 5 The threshold values can be programmed over the entire full scale range 15 14 13 12 11 10 9 8 7 65 4 3 2 1 0 ADC converted ed value from the ADC CONVERTED VALUE channel n Threshold value THRESHOLD VALUE for the channel n nsjraj3121110 gt ee Fig 2 4 Zero suppression Bit 8 of Bit Set 2 Register 0 default setting if Bit 8 1 in the Bit Set 2 Register the comparison is performed between the bit 1 8 of each 12 bit converted value and the 8 bit threshold value which is stored in the relevant register as illustrated in the figure below converted value is under threshold if the value written in the 1 8 bits is smaller than the threshold value and 9 11 bits are 0 The threshold values can be programmed over 1 8 of full scale range EEN 0 ADC CONVERTED VALUE ADC converted value from the channel n
83. ument type Title Revision date Revision User s Manual MUT Mod V775 16 32 Channel Multievent TDC 10 09 2004 10 3 7 Technical specifications table Table 3 2 Model V775 technical specifications Packaging 6U high 1U wide VME unit version AA requires the V430 backplane Refer to Table 3 1 V775 32 ECL inputs 110 Q impedance V775 N 16 NIM inputs 50 Q impedance Full Scale Range VME programmable from 140 to 1200 ns Ha VME programmable from 35 to 300 ps RMS noise 0 8 counts typical 2 counts maximum LSB Integral non linearity 0 1 of FSR Interchannel isolation gt 66 dB 0 01 count mV 5V 0 02 count mV 5V Power rejection 0 005 count mV 12V 0 001 count mV 12V Common Start mode 14 ns Minimum Start Stop delay Common Stop mode 4 ns Threshold values programmable in Zero suppression 16 ADC counts steps over the entire FSR 2 ADC counts steps over 1 8 of FSR Two LEMO 00 bridged connectors NIM signal high impedance GAB eels O Common Start Stop signal V775 active high differential ECL V775 N standard NIM logic RST resets PEAK sections MEB status and control registers VETO inhibits the conversion of the peaks FCLR FAST CLEAR of TAC sections COM Common Start Stop signal V775 active high differential ECL V775 N standard NIM logic DRDY indicates the presence of data BUSY board full resetting converting or in MEMORY TEST mode A24 A32 Geographical addressing Multicas
84. wing subsections 3 4 1 INPUT connectors Mod V775 Mechanical specifications two 17 17 pin 3M 3431 5202 Header type connectors Electrical specifications ECL input signals 110 Q impedance The 17th higher pair of pins of each connector is not connected BLOCK A INPUT input signals from channel 0 through channel 15 BLOCK B INPUT input signals from channel 16 through channel 31 Mod V775 N Mechanical specifications 16 LEMO 00 connectors Electrical specifications NIM input signals 50 Q impedance BLOCK A INPUT input signals from channel 0 through channel 7 BLOCK B INPUT input signals from channel 8 through channel 15 3 4 2 CONTROL connector Mod V775 Mechanical specifications two 8 8 pin 3M 3408 5202 Header type connectors Pin assignment is shown in Fig 3 3 The 1st lower pair of pins is not connected they can be optionally connected to VEE 5 V or to DIGITAL GND by means of a soldering pad on the Printed Circuit Board Refer to 3 6 3 for further details All the control lines described below can be 110 Q terminated on board via internal DIP switches please refer to 3 5 2 for further details FCLR Electrical specifications diff ECL input signal active high high impedance min width 10 ns Function FAST CLEAR signal accepted if sent within the so called FAST CLEAR window see Fig 2 8 it clears the TAC sections of the unit and aborts completely the conversion in progress

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