PCI/PXI-9816/26/46
Contents
1. sl ojo o jo olo o o o o olo o o o o o t olololololol I I I I I I I lolololololololo E z c lolololol I I lolelelel I I I lololelo 2 d olol I lolol I lolel I lolel I lolel I lolo lol lol leol lol lol lel lol lol lel lol lo Q o o slajojslo o nojojo lalo sojonioo o s e e e e e F E EJNIA JNIN IA JNINIA aA aA O o O ma LL zu O O 6 Table 3 6 Board ID Combination Conditions Operation Theory 54 ADLINK TECHNOLOGY INC Important Safety Instructions Please read and follow all instructions marked on the product and in the documentation before operating the system Retain all safety and operating instructions for future use gt gt gt Please read these safety instructions carefully Please keep this User s Manual for future reference The equipment should be operated in an ambient tempera ture between 0 to 50 C The eguipment should be operated only from the type of power source indicated on the rating label Make sure the voltage of the power source is correct when connecting the eguipment to the power outlet If the user s equipment has a voltage selector switch make sure that the switch is set to the proper position for the area The voltage selector switch is set at the factory to the cor rect voltage For pluggable equipment ensure they are installed near a socket outlet that is easily a2. 122 50 130 63 Y HF Nike 210 03 gt CLK IN TRG Io 8 CHO E ge Q w S 2 IG gt em t 9 gt 2 2 121 High Resolution Digitizer e cha A nn rri U CTO a Le K T 4 9 3 Unit in mm Figure 2 2 PCI 98x6 Mechanical Drawing The ADLINK PXI 9816 PXI 9826 PXI 9846 is packaged in a Euro card form factor with PXI specifications measuring 160 mm in length and 100 mm in height not including connectors The PCI 9816 9826 9846 is a half length and standard height PCI form fac tor Please refer to above figure for detail dimension Getting Started 21 TECHNOLOGY INC A ADLINK A The connector types and functions are described as follows Connector Direction Type Description Function The CLK IN is a 500 AC coupled external timebase input The TRG IO is a bidirectional port CLK IN Input SMB TRG IO Input SMB for external digital trigger input or Output output CHO CH1 Input BNC These channels are for attaching CH2 the analog input signals CH3 Table 2 1 Connector Pin Assignments 22 Getting Started A 2 4 Installing the module To install the PXI 9816 PXI 9826 PXI 9846 module 1 Turn off the PXI system chassis and disconnect the power plug from the power source 2 Ali
3. Effective Number of Bit ENOB typical 12 34 Bit 11 66 Bit Test Conditions Input signal frequency is 0 998 MHz Digitizer sampling rate at 40 MHz with 50 Q input impedance Calculated with 64 K point data Note that these dynamic parameters may vary from one unit to another with input frequency and with the full scale input range selected Table 1 7 Spectral Characteristics PCI PXI 9846 PXI 9846 0 2V S Rate 40MS s Input Signal 0 998 MHz 0 9758 dBFs O GO SCG re ee ee ana ena I I I I I I I I I I I I I I I 1 I I I I I is o ii PS dci I I I I I I I I I I I I I I I I I I I I I I Ad Z GOP SR ST P aj I I I I I I I y I I I I I l I I I 2 g COR mp Sg He Eq Sp HS pa 0 fi o 3 I I I I I E I I I I I I I I I I 1 I I 1 I me ABO Loc so an aaa NN I I I I I I I I I I I I I 100 J 1 1 4 I F p 4 r I 1 I I I 120 Frequency Hz i x 107 Figure 1 8 PXI 9846 FFT with 0 2 V Input Range 12 Introduction 40MS s Input Signal 0 998 MHz 1 1732 dBFs PXI 9846 1V S Rate gp epnyuBe 0 4 0 6 0 8 1 1 2 1 4 1 6 0 2 Frequency Hz Figure 1 9 PXI 9846 FFT with 1 V Input Range 13 Introduction A A ADLINK TECHNOLOGY INC Timebase Specification Value Internal onboard oscillator
4. Magnitude dB 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 Frequency Hz x 10 Figure 1 4 PXI 9816 FFT with 0 2 V Input Range Introduction 10MS s Input Signal 0 998 MHz 1 1993 dB FS PXI 9816 1V S Rate I I I I A A Ii seri petai UE ma Ra avc pur M ij E an I I k amp I pps a eee os AA I I PTR dzese als Z r I I I I fr eae WAD R pee ed I I I I 1 1 o o o o S Y 9 gp epmiubew 2 5 Freguency Hz 2 1 5 Figure 1 5 PXI 9816 FFT with 1 V Input Range Introduction TECHNOLOGY INC A ADLINK A Spectral Characteristics PXI 9826 Specification Input Range 1 V 0 2 V Signal to Noise and Distortion SINAD typical 78 63 dBc 74 44 dBc Signal to Noise Ratio SNR typical 79 95 dBc 74 48 dBc Total Harmonic Distortion THD typical 88 29 dBc 93 52 dBc Spurious Free Dynamic Range SFDR typical 88 88dBc 95 52 dBc Effective Number of Bit ENOB typical 12 77 Bit 12 07 Bit Test Conditions Input signal freguency is 0 998 MHz Digitizer sampling rate at 20 MHz with 50 O input impedance Calculated with 64 K point data Note that these dynamic parameters may vary from one uni
5. SSI TRIG2 Tw 20 ns minimum Figure 3 23 SSI TRIG2 Input Timing Reguirement As an output the SSI START OP signal reflects the operation start signal in a pre trigger or middle trigger acguisition seguence Please refer to Figure 3 12 Figure 3 14 for the relationship between the operation start signal and the acguisition seguence As an input the PCI PXI 9816 26 46 accepts the SSI START OP signal to be the operation start signal in a pre trigger or middle trigger acguisition seguence The signal is configured in the rising edge detection mode Figure 3 24 show the SSI START OP sig nal input and output timing reguirements Operation Theory 49 TECHNOLOGY INC A ADLINK A For enabling output operations you can use the function SSI SourceConn to output the SSI_TRIG2 and SSI START OP signals For the input operations you can select TRSRC_SSI_2 to set SSI TRIG2 and SSI START OP as the source of the trigger event and operation start signal Two SSI START OP Output Two 2 TIMEBASE Clocks Twi SSI START OP Input Twi 20 ns minimum Figure 3 24 SSI START OP Output and Input Timing Characteristics 3 7 4 Comparing the Different Trigger Sources from SSI When selecting TRSRC SSI 1 as the trigger source input the signal SSI TRIG1 reflects the trigger event signal in an acquisition sequence However when synchronizing multiple PCI PXI 9816 26 46 devices each module may recognize the
6. 1 60 12 35 66 Email franceQadlinktech com ADLINK Technology Japan Corporation Address 151 0072 RRMBXARIETS 1 1 2 FB Aas SE JL 8F Asahiseimei Hatagaya Bldg 8F 1 1 2 Hatagaya Shibuya ku Tokyo 151 0072 Japan Tel 81 3 4455 3722 Fax 81 3 5333 6040 Email japan adlinktech com ADLINK Technology Inc Korean Liaison Office Address amp Get Fas 60 12 5444 43 4025 No 402 Dongsung B D 60 12 Nonhyeon Dong Gangnam gu Seoul 135 010 Korea Tel 82 2 2057 0565 Fax 82 2 2057 0563 Email korea adlinktech com ADLINK Technology Singapore Pte Ltd Address 84 Genting Lane 07 02A Cityneon Design Centre Singapore 349584 Tel 65 6844 2261 Fax 65 6844 2263 Email singaporeQadlinktech com ADLINK Technology Singapore Pte Ltd Indian Liaison Office Address No 1357 Anupama Sri Aurobindo Marg 9th Cross JP Nagar Phase I Bangalore 560078 India Tel 91 80 65605817 Fax 91 80 22443548 Email india adlinktech com ADLINK TECHNOLOGY INC Table of Contents Table of GONE usina bea cen i List of Tables os naa iii List of Figures ka kin iv 1 Infrodicti0i ss 1 AR ska i viss ads 3 1 2 Applications i aaa 3 1 3 Specifications viii nee erna nan yaaah 4 2 Getting Started aa ia 19 2 1 Installation Environment oo oom 19 2 2 Package Contents oooooooo Wo oo 20 2 3 Mechanical Drawing and I O Connectors 21 2 4 Installing the module uuue
7. 3 1 Basic Counters i oooWo oo 29 Table 3 2 Al Data Format i iiiooooo Woo 30 Table 3 3 Ideal Transfer Characteristics for Analog Triggers 36 Table 3 4 Summary of SSI timing Signals and th Corresponding Function iooooooooWoWoWoWW 44 Table 3 5 SSI Signal Locations and Pin Definition 47 Table 3 6 Board ID Combination Conditions 54 List of Tables iii TECHNOLOGY INC A ADLINK A Figure 1 1 Figure 1 2 Figure 1 3 Figure 1 4 Figure 1 5 Figure 1 6 Figure 1 7 Figure 1 8 Figure 1 9 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 3 9 Figure 3 10 Figure 3 11 Figure 3 12 Figure 3 13 Figure 3 14 Figure 3 15 Figure 3 16 Figure 3 17 Figure 3 18 Figure 3 19 Figure 3 20 Figure 3 21 Figure 3 22 Figure 3 23 List of Figures PCI PXI 9816 Bandwidth Chart 6 PCI PXI 9826 Bandwidth Chart 6 PXI 9846 Bandwidth Chart ooooooWooWo 7 PXI 9816 FFT with 0 2 V Input Range 8 PXI 9816 FFT with 1 V Input Range 9 PXI 9826 FFT with 0 2 V Input Range 10 PXI 9826 FFT with 1 V Input Range 11 PXI 9846 FFT with 0 2 V Input Range 12 PXI
8. Trigger Bus the PXI 9816 26 46 makes the synchronization between multiple modules easy and simple For PCI 9816 26 46 a dedicate connector is served as system synchronization interface With this interface PCI 9816 26 46 is capable of achieving multiple module synchronization Following figure shows the installation of multiple module synchronization The bi directional SSI I Os provide a flexible connection between modules which allows one SSI master PCI PXI 9816 26 46 to out put the SSI signals to other slaves modules to receive the signals Table 3 4 lists the summary of SSI timing signals and the function alities Figure 3 18 shows the architecture of SSI Note that it s not allowed to route different signals onto the same trigger bus line SSI Timing Signals Functionality SSI TIMEBASE Input output timebase signal through SSI SSI TRIG1 Input output trigger signal through SSI SSI TRIG2 Input output clocked trigger signal through SSI Sener ak Table 3 4 Summary of SSI timing Signals and the Corresponding Function 44 Operation Theory ADLINK TECHNOLOGY INC n SSI TIMEBASE Timing Control PXI Trigger 5 Bus 0 7 o or o SSI o S SSI TRG1 5 E SSI_TRG2 Trigger aM d x Decision o SSI_START_OP AA Figure 3 18 SSI Architecture For PCI 9816 26 46 a dedicate connector is served as
9. Trigger Counter The delay trigger counter is used to indi cate the time between a trigger event and the start of an acguisition The unit of trigDelayTicks 32 bit 1 536870911 a delay count is the period of the TIME BASE For PCI PXI 9816 the unit is 100ns and for PCI PXI 9846 the unit is 25ns Refer to section 3 5 4 for more detail Re Trigger Counter The digitizer can enable re trigger to accept multiple triggers Refer to section 3 5 5 for more detail ReTrgCnt 24 bit 1 16777215 Table 3 1 Basic Counters Refer to Figure 3 4 and use post trigger mode as an example When a trigger is accepted by digitizer the acquisition engine of the digitizer will begin to acquire data that coming from ADC and store these sampled data to onboard memory The sampled data is generated continuously at the rising edge of timebase according to the scan interval counter setting While sampled data reaches customer specified number in this example is 256 the acguisition ends Once the acquisition ends acquisition engine begins to send request to system and transfer data from onboard memory back to system by DMA Operation Theory 29 A ADLINI lt A TECHNOLOGY INC Analog N j signal 4 N j Nea S wee FILI cf fli li lf I Lf Trigger Acguisition f A i y In Progress Acquisition starts right after this clock edge DATA D1 D2 D
10. V and 5 V signaling PCI Interface 32 bit 66 MHz Electromagnetic Compatibility Emission EN 55022 Immunity EN 55024 Typical Power Requirements PCI PXI 9816 PCI PXI 9826 PCI PXI 9846 12V 0 3A 0 3A 0 3A 5 V 14A 15A 2 0A 3 3 V 0 8A 0 8A 0 8A Total Power 13 2 W 13 7 W 16 2 W Table 1 12 General Information Introduction 17 ADLINK TECHNOLOGY INC 18 Introduction ADLINK TECHNOLOGY INC 2 Getting Started This chapter describes the proper installation environment instal lation procedures its package contents and basic information user should be aware of NOTE Diagrams and images of eguipment mentioned are used for reference only Actual system configuration and specs may vary 21 Installation Environment Whenever unpacking and preparing to install any eguipment described in this manual please refer to the Important Safety Instructions chapter of this manual Only install equipment in well lit areas on flat sturdy surfaces with access to basic tools such as flat and cross head screwdrivers preferably with magnetic heads as screws and standoffs are small and easily misplaced Recommended Installation Tools Philips cross head_ screwdriver gt Flat head screwdriver gt Anti static wrist strap gt Anti static mat The PCI PXI 9816 26 46 contain several electro static sensitive components that can be easily be damaged by static electricity The eguipment
11. bus As an input the PCI PXI 9816 26 46 accepts the SSI TIMEBASE signal to be the source of timebase Operation Theory 47 TECHNOLOGY INC A ADLINK A 3 7 2 SSI_TRIG1 As an output the SSI_TRIG1 signal reflects the trigger event sig nal in an acquisition sequence You can use the function SSI SourceConn to output the SSI_TRIG1 signal As an input the PCI PXI 9816 26 46 accepts the SSI_TRIG1 sig nal to be the trigger event source The signal is configured in the rising edge detection mode When selecting the trigger sources of the PCI PXI 9816 26 46 you can select TRSRC SSI 1 to set SSI TRIG1 as the source of trigger event Two SSI_TRIG1 Output Two 3 4 TIMEBASE Clocks Twi l SSI_TRIG1 Input Twi 20 ns minimum Figure 3 21 SSI_TRIG1 Input and Output Timing Characteristics 48 Operation Theory ADLINIK 3 7 3 SSI TRIG2 and SSI START OP As an output the SSI TRIG2 signal is a clocked SSI TRIG1 sig nal by TIMEBASE as illustrated in Figure 3 22 SSI TRIG1 SEEM ae Ww y SSI_TRIG2 Tw 2 TIMEBASE Clocks Figure 3 22 SSI_TRIG2 Output Timing As an input the PCI PXI 9816 26 46 accepts the SSI TRIG2 sig nal to be the source of a one clock delayed trigger event The con troller on the PCI PXI 9816 26 46 will then compensate the one clock delay if using SSI TRIG2 as the source of trigger event The signal is configured in the rising edge detection mode Tw a
12. delay trigger mode the trigger is used to initiate acquisition In pre trigger mode the trigger is used to stop acquisi tion In middle trigger mode the trigger is used to inform the acqui sition engine to acquire the specific number of data and then stop Timebase is a clock that sent to the ADC of each channel and the acquisition engine for essential timing functionality The source of timebase can be either internal oscillator or external clock genera tor Usually the maximum sampling rate of a digitizer is determined by the speed of timebase However other sampling rate can be achieved by specifying a scan interval counter Please refer to Table 3 1 below and Section 3 3 4 on page 32 for more details 28 Operation Theory ADLINK TECHNOLOGY INC Table 3 1 shows several basic counters reguired for operating dig itizers Counter Name Length Valid value Description Scan Interval Counter This counter is a TIMEBASE divider to the achieve equivalent sampling rate of digitizer The equation is Sampling rate TIMEBASE Scanlntrv The value of TIMEBASE depends on the card type Take the PCI PXI 9846 40 MS s as an example Scanintrv 1 results in 40 MS s and Scanlntrv 2 results in 20 MS s and so on Scanlntrv 24 bit 1 16777215 Data Counter You can specify the amount of data to be acguired The digitizer eguips 512MB memory to store acguired data DataCnt 29 bit 1 536870911 Delay
13. moisture The equipment is not functioning or does not function according to the user s manual gt The equipment has been dropped and damaged b If the equipment has obvious sign of breakage Never open the equipment For safety reasons the equip ment should only be opened by qualified service personnel Important Safety Instructions
14. of ACL SSI 2 Cable 46 SSI TRIG1 Input and Output Timing Characteristics 48 SSI TRIG2 Output TIMINg ooooooooo WWW 49 SSI TRIG2 Input Timing Requirement 49 List of Figures ADLINK TECHNOLOGY INC Figure 3 24 SSI START OP Output and Input Timing Characteristics eeeeees 50 Figure 3 25 The Location of Board ID Switch 53 Figure 3 26 Enlargement of Board ID setting 53 List of Figures V ADLINK TECHNOLOGY INC vi List of Figures 1 ADLINK TECHNOLOGY INC Introduction The ADLINK PCI PXI 9816 26 46 are 10 MS s 20 MS s and 40 MS s sampling 16 bit 4 CH digitizers designed for digitizing high freguency and wide dynamic range signals with an input freguency up to 20 MHz The analog input range can be programmed via software to 1 V or 0 2 V With deep onboard acquisition memory up to 512 MB the PCI PXI 9816 26 46 are not limited by the data transfer rate of the PCI bus to enable the recording of waveforms for extended periods of time The PCI PXI 9816 26 46 are equipped with four high linearity 16 bit A D converters ideal for demanding applications with a high dynamic range such as radar ultrasound and software defined radio Analog Input The PCI PXI 9816 26 46 each feature four analog input channels The bandwidth of each channel can be up to 5 MHz 10 MHz and 20 MH
15. quency Range Sample Clock Sources External CLK IN front panel SMB connector PXI STAR PXI Trigger Bus 0 7 PXI 10MHz SSI bus PCI PXI 9816 PCI PXI 9826 PCI PXI 9846 Timebase Fre 40 MHz 1 MHz 20MHz 1 MHz 40 MHz 1 MHz Sampling Rate Range 24 bit divided coun ter 10 MS s 0 596 S s 20 MS s 1 192 S s 40 MS s 2 384 S s Internal Oscil lator Stability 25 ppm CLK IN external clock from front panel Connector Type SMB Clock Type Sine wave or square wave Input Imped 50 Q ance Input Coupling AC Input Range 1VP P to 2VP P Overvoltage Protection SPIER 14 Table 1 8 Timebase Introduction ADLINK TECHNOLOGY INC Triggering Specification Value Software TRG IO front panel SMB connector Trigger Sources analog trigger from CHO CH3 PXI STAR PXI Trigger Bus 0 7 SSI bus Trigger Modes Pre trigger Post trigger Middle trigger Delay trigger TRG IO as input port Connector type SMB Compatibility 3 3 V LVTTL 5 V tolerant High threshold Vj 2 0 V minimum Low threshold V 0 8 V maximum Maximum Input Overload 0 5 V to 5 5 V Rising edge or falling edge software program mable Minimum Pulse Width 20 ns TRG IO as output port Connector Type SMB Compatibility 3 3 V TTL High threshold VOH 2 4V minimum Low threshold VOL 0 2 maximum Input Level Trigger Polarity Ou
16. should be handled on a grounded anti static mat and the operator should wear an anti static wristband during the unpacking and installation procedure Please also inspect the components for apparent damage Improper shipping and handling may cause damage to the compo nents Be sure this is no shipping and handling damage on the components before continuing CAUTION The eguipment must be protected from static discharge and physical shock Never remove any of the socketed parts except at a static free workstation Use the anti static bag shipped with the product to handle the eguip ment and wear a grounded wrist strap when servicing Getting Started 19 TECHNOLOGY INC A ADLINK A 2 2 Package Contents Before continuing check the package contents for any damage and check if the following items are included in the packaging gt PCI PXI 9816 26 46 digitizer card gt ADLINK All in one CD gt Software installation guide gt PCI PXI 9816 26 46 User s Manual CAUTION Do not install or apply power to equipment that is dam aged or if there is missing incomplete equipment Retain the shipping carton and packing materials for inspection Please contact your ADLINK dealer vendor immediately for assistance Obtain authorization from your dealer be fore returning any product to ADLINK 20 Getting Started ADLINK TECHNOLOGY INC 2 3 Mechanical Drawing and I O Connectors lt 160 00 20 00
17. system synchronization interface Refer to Figure 3 19 for the connector position All the SSI signals are routed to the 20 pin connector from FPGA With this interface PCI 9816 26 46 is capable of achieving multiple module synchronization Users can use ACL SSI 2 ACL SSI 3 ACL SSI 4 cables to synchronize 2 3 or 4 mod ules Please refer to Figure 3 20 for the installation of an ACL SSI cable Note When powering up or reseting the synchronization sig nals are reset to use internal generated timing signals Operation Theory 45 em Figure 3 19 SSI Connector Location on the PCI 9816 26 46 Figure 3 20 Installation of ACL SSI 2 Cable 19 17 15 13 119 7 5 3 1 20 18 16 14 12 10 8 6 4 2 PCB CN11 46 Operation Theory ADLINK TECHNOLOGY INC Signal Name Direction Description Location SS _TIMEBASE Input Output ie signal through pin 1 SSI_TRIG1 Input Output signal through pin 11 Clocked trigger signal SSI TRIG2 Input Output through SSI pin 9 Acquisition start signal SSI START OP Input Output in pre trigger or middle pin 7 trigger mode pins 2 4 6 8 GND Ground 10 12 14 16 18 20 NC No Connection pins 3 13 Reserved Input Output Reserved for future use pins 5 15 17 19 Table 3 5 SSI Signal Locations and Pin Definition 3 7 1 SSI TIMEBASE As an output the SSI TIMEBASE signal outputs the onboard LVTTL timebase through PXI trigger
18. trigger signal with one clock time difference because the signal is not related to the timebase There is another phenomenon if using TRSRC SSI 2 in pre trig ger and middle trigger mode The operation start signal is gener ated by a software command so multiple PCI PXI 9816 26 46 modules don t start the data acquisition simultaneously which may result in the fact that the amount of stored samples are differ ent if the trigger event occurs before the specified amount of data has been acquired When selecting TRSRC SSI 2 as the trigger source input SSI TRIG2 and SSI START OP can achieve better synchroniza 50 Operation Theory ADLINK TECHNOLOGY INC tion between multiple PCI PXI 9816 26 46 devices A clocked SSI TRIG2 can guarantee all PCI PXI 9816 26 46 devices recog nize the trigger event at the same clock edge if they use the same timebase In pre trigger and middle trigger mode SSI START OP guarantees all the PCI PXI 9816 26 46 devices start the data acquisition at the same time Operation Theory 51 TECHNOLOGY INC A ADLINK A 3 8 Physical Location of the PXI and PCI Digitizer 3 8 1 Identify PXI Digitizer s Physical Location by Geo graphic Address CompactPCI and PXI chassis accommodate slot numbering mechanism based on the definition of Geographical Address pins on its backplane Users can identify module s physical location by reading back Geographical Address This is a useful feature espe cially when multi
19. 1 MUX Figure 3 5 PCI PXI 98x6 Timebase Source and Architecture 3 3 1 Internal Oscillator The PCI PXI 9816 26 46 equips a high stability low jitter oscillator for the ADCs The oscillators are 10 MHz 20 MHz and 40 MHz for PCI PXI 9816 PCI PXI 9826 and PCI PXI 9846 respectively 3 3 2 External Clock Through Front Panel When you need a specific timebase in some applications that the onboard oscillator is not achievable a clock from an external device can replace onboard oscillator In addition external time base also provides a method to synchronize digitizers to other measurement modules by distributing receiving a common clock to from multiple modules The PCI PXI 9816 26 46 can receive an Operation Theory 31 TECHNOLOGY INC A ADLINI lt A external timebase from the front panel connector CLK IN PXI STAR or one of the PXI Trigger Bus lines You can supply the timebase from external SMB connector CLK IN which should be a sine wave or square wave signal This sig nal is AC coupled with 50 Q input impedance and the valid input level is from 1 to 2 volts peak to peak Note that the external clock must be continuous for correct ADC operation because of the pipeline architecture of the ADC 3 3 3 External Clock from PXI Interfaces The PCI PXI 9816 26 46 can receive timebase via one of the PXI Trigger Bus lines by software selection The eight PXI Trigger Bus lines PXI TRIG 0 7 provide inter module synchronization
20. 3 D4 D253 D254 D255 D256 Trigger mode post trigger DataCnt 256 Scanintrv 1 Figure 3 4 Basic Acquisition Timing Of Digitizer 3 2 3 Al Data Format The following table illustrates the idea transfer characteristics of various input ranges of the PCI PXI 9816 26 46 The data format of the PCI PXI 9816 26 46 is straight binary Description Analog Input Range Digital Code HEX Full scale Range 1 V 0 2 V Least significant bit 30 52 uV 6 10 pV FSR 1LSB 0 999969 V 0 199993 V FFFF Midscale 1LSB 30 5 UV 6 10 uV 8001 Midscale 0 0 V 0 0 V 8000 Midscale 1LSB 30 5 UV 6 10 pV TFFF FSR 1 000 V 0 200 V 0000 Table 3 2 Al Data Format 30 Operation Theory ADLINK TECHNOLOGY INC 3 3 ADC Sampling Rate and TIMEBASE Control The PXI PCI 98X6 supports several timebase sources for analog input conversion b Internal oscillator External clock through front panel PXI STAR PCI version PXI Trigger Bus 0 7 PXI version PXI 10M PXI version SSI PCI version The following diagram shows the timebase architecture of the PXI PCI 98X6 Onboard Oscillator rp Ext CLK IN SMB Connector CLK Buffer gt el PXI STAR PXI 10M a PXI Trigger Bus 0 7 hs Z gt vvvvy 8 to 1 MUX ADCO PXI Trigger Bus or SSI to 5 Clock Buffer E ADC1 XI Interface Timebase Clock Mux ADC2 ADC3 8 to
21. 9816 26 46 supports maximum 512MB in order to meet application require ments Once all the data has been stored in the on board memory the data will be transferred to the host computers memory through bus mastering DMA In a multi user or multi tasking OS like Microsoft Windows Linux and so on it is difficult to allocate a large continuous memory block to do the DMA transfer Therefore the PCI PXI 98 16 26 46 provides the function of scatter gather DMA to link the non contin uous memory blocks into a linked list so that you can transfer very large amounts of data without being limited by the fragment of small size memory as illustrated in Figure 3 17 System Memory PXI 9816 PXI 9826 IPXI 9846 First PCI Address First Local Address Transfer Size Next Descriptor PCI Address Local Address Transfer Size Next Descriptor PCI Bus PCI Address Local Address 5 Transfer Size Next Descriptor Figure 3 17 Scatter Gather DMA for Data Transfer Operation Theory 43 TECHNOLOGY INC A ADLINK A 3 7 Synchronizing Multiple Modules The eight interconnected lines on PXI backplane named as PXI Trigger Bus 0 7 provide a flexible interface for multiple modules synchronization The PXI 9816 26 46 utilizes the PXI Trigger Bus 0 7 as the System Synchronization Interface SSI By pro viding flexible routing of timebase clock and trigger signals onto PXI
22. 9846 FFT with 1 V Input Range 13 PXI 98x6 Mechanical Drawing 21 PCI 98x6 Mechanical Drawing 21 DAQPilot Main Interface 24 DAQMaster Device Manager 1 1 1111111 25 Legacy Software Support Overview 26 PXI 98x6 Functional Block Diagram 27 PCI 98x6 Functional Block Diagram 27 Analog Input Signal Block Diagram 28 Basic Acquisition Timing Of Digitizer 30 PCI PXI 98x6 Timebase Source and Architecture 31 Configuring Different Sampling Rate of a Digitizer 33 PCI PXI 98x6 Trigger Architecture 34 External Digital Trigger Polarity and Pulse Width Requirement ooooo Woo 35 Analog Trigger Conditions 37 TRG IO Output Signal Timing 38 Post trigger AcgUisition oo 39 Pre trigger Mode Operation i oooooooo 40 Pre trigger Mode Operation 2 11 40 Middle trigger Mode Operation 41 Delay trigger Mode Operation 41 Re trigger Mode Operation oooooo 42 Scatter Gather DMA for Data Transfer 43 SSI Architecture ttt ass 45 SSI Connector Location on the PCI 9816 26 46 46 Installation
23. A ADLINK YA PCI PXI 9816 26 46 4 CH 16 Bit 10 20 40 MS s Digitizer with 512 MB SDRAM User s Manual Manual Rev 2 01 Revision Date July 21 2009 Part No 50 17031 1010 Recycled Paper Advance Technologies Automate the World A A ADLINK TECHNOLOGY INC Copyright 2009 ADLINK TECHNOLOGY INC All Rights Reserved The information in this document is subject to change without prior notice in order to improve reliability design and function and does not represent a commitment on the part of the manufacturer In no event will the manufacturer be liable for direct indirect spe cial incidental or conseguential damages arising out of the use or inability to use the product or documentation even if advised of the possibility of such damages This document contains proprietary information protected by copy right All rights are reserved No part of this manual may be repro duced by any mechanical electronic or other means in any form without prior written permission of the manufacturer Trademarks NuDAQ NulPC DAQBench are registered trademarks of ADLINK TECHNOLOGY INC Product names mentioned herein are used for identification pur poses only and may be trademarks and or registered trademarks of their respective companies ADLINK TECHNOLOGY INC Getting Service from ADLI NK Contact us should you reguire any service or assistance ADLINK Technology Inc Address 9F No 166 Jian Yi Road Chu
24. XI 9846 Bandwidth Chart ADLINK TECHNOLOGY INC System Noise measured and calculated under 50 Q input impedance Input Range PXI 9816D PXI 9826D PXI 9846D PXI 9846W PCI 9846D 0 2V 5 0 LSBpys 6 0LSBays 8 0 LSB ys 15 0 LSBys 8 0 LSB ys 1V 3 0 LSB ys 4 0 LSB ys 5 0 LSBgys 7 0LSBpys 5 0 LSB ys Input Range PCI 9816H PCI 9826H PCI 9846H PXI 9846H 1V 5 0LSBrus 6 0 LSBpys 8 0 LSBrms 8 0 LSB ys 5 V 3 0 LSB ys 4 0 LSBpys 5 0 LSBpys 5 0 LSBrms Table 1 4 System Noise Introduction 1 A A ADLINK TECHNOLOGY INC Spectral Characteristics PXI 9816 Specification Input Range 1 V 0 2 V Signal to Noise and Distortion SINAD typical 79 11 dBc 75 93 dBc Signal to Noise Ratio SNR typical 79 36 dBc 75 96 dBc Total Harmonic Distortion THD typical 89 90 dBc 95 77 dBc Spurious Free Dynamic Range SFDR typical 90 37 dBc 98 65 dBc Effective Number of Bit ENOB typical 12 85 Bit 12 32 Bit Test Conditions Input signal freguency is 0 998 MHz Digitizer sampling rate at 10 MHz with 50 Q input impedance Calculated with 64 K point data Note that these dynamic parameters may vary from one unit to another with input freguency and with the full scale input range selected Table 1 5 Spectral Characteristics PCI PXI 9816 PXI 9816 0 2V S Rate 10MS s Input Signal 0 998 MHz 0 97 dBFs
25. and communication Note that this function is only available when the PCI PXI 9816 26 46 is in a PXI system It s not supported when PCI PXI 9816 26 46 is in a CompactPCI system When the PCI PXI 9816 26 46 is plugged into a generic peripheral slot in a PXI system it can receive timebase from PXI_STAR The PXI_STAR signal comes from star trigger controller is matched in propagation delay within 1 ns and the delay from star trigger slot to peripheral slot is less than 5 ns According these hardware fea tures the PCI PXI 9816 26 46 can achieve very good synchroni zation performance when using PXI_STAR as timebase clock source Note that the function is only available when the PCI PXI 98x6 is in a PXI system It s not supported when the PCI PXI 9816 26 46 is in a CompactPCI system 3 3 4 Sampling Rate Control By specifying different scan interval counter 24 bit value differ ent sampling rate can be achieved The following formula deter mines the ADC sampling rate Sampling Rate TIMEBASE Scanlntrv Where Scanlntrv is scan interval counter value can be 1 2 3 4 24 A 32 Operation Theory ADLINK TECHNOLOGY INC Refer to Figure 3 6 for detail timing Trigger wee TIPLPLAFLU LU UU L L UU Scanintrv 1 Di D2 D3 D4 D5 D6 Dz D8 Ds Dio Scanintrv 2 Di D2 D3 D4 D5 D6 DATA Scanintrv 3 Di D2 D3 D4 Acq
26. ccessible Secure the power cord to prevent unnecessary accidents Do not place anything over the power cord If the equipment will not be in use for long periods of time disconnect the equipment from mains to avoid being dam aged by transient overvoltage All cautions and warnings on the equipment should be noted Please keep this equipment away from humidity Do not use this equipment near water or a heat source Place this equipment on a reliable surface when installing A drop or fall could cause injury Never pour any liquid into the opening this could cause fire or electrical shock Important Safety Instructions 55 A A ADLINK TECHNOLOGY INC gt Openings in the case are provided for ventilation Do not block or cover these openings Make sure there is adequate space around the system for ventilation when setting up the work area Never insert objects of any kind into the ventila tion openings To avoid electrical shock always unplug all power and modem cables from the wall outlets before removing cov ers Lithium Battery provided real time clock battery CAUTION Risk of explosion if battery is replaced by an incorrect type Dispose used batteries as instructed in the instructions The equipment should be checked by service personnel if one of the following situation arises gt The power cord or plug is damaged gt Liquid has penetrated the equipment The equipment has been exposed to
27. ed as a master module and can output SSI TRG1 SSI TRG2 or SSI START OP to PXI Trigger Bus Each signal can be routed from one of the PXI Trigger Bus 0 7 by software programming For more detail about these signals please refer to Section 3 7 on page 44 Operation Theory 37 TECHNOLOGY INC A ADLINK A 3 4 6 Trigger Signal Exporting The PCI PXI 9816 26 46 can export trigger signals to following connectors bus TRG IO on front panel and PXI Trigger Bus 0 7 The TRG IO on the front panel can also be programmed to output the trigger signal when the trigger source is from software trigger analog trigger PXI STAR or PXI Trigger Bus 0 7 The timing characteristic is in Figure 3 10 Tw TRG IO Output Tw 2 TIMEBASE Clocks Figure 3 10 TRG IO Output Signal Timing The PCI PXI 9816 26 46 utilizes PXI Trigger Bus 0 7 as System Synchronize Interface When configured as output the PCI PXI 9816 26 46 is served as a master module and can output 3 differ ent trigger signals SSI TRG1 SSI TRG2 and SSI START OP You can route these signals to any of PXI Trigger Bus 0 7 signals via software programming 38 Operation Theory ADLINK TECHNOLOGY INC 3 5 Trigger Modes There four trigger modes working with trigger sources to initiate different data acguisition timing when a trigger event occurs They are described in this section 3 5 1 Post trigger Acquisition Use post trigger acquisition when yo
28. ee eee aaa aaa Wo W W 23 2 5 Software Support ombak 24 Driver Support for Windows o oWo oo 24 WD DASK Legacy Drivers and Support 26 3 Operation Theory ian aa ha an 27 3 1 Functional Block Diagram Woow 27 3 2 Basic Al Acquisition ooooWcoWooo 28 Analog Input Path i oooooooWoWo Wo WoW Wo WWW 28 Basic Acquisition Timing sseeeeee 28 Al Data Format Mai ena 30 3 3 ADC Sampling Rate and TIMEBASE Control 31 Internal Oscillator ooooo WoooWo oom 31 External Clock Through Front Panel 31 External Clock from PXI Interfaces 32 Sampling Rate Control ooooWoooWooWo Wo 32 Timebase Exporting oooooooooo WWW Wo WoWoW WWW 33 3 4 Trigger Sources 34 Software Trigger ooooooooooWooooWoWo Wo mma 34 External Digital Trigger ooooo mena 35 Analog Trigger s usa ne eee d ue 36 PXI STAR Trigger a 37 PXI Trigger BUS sei ioo aa 37 Table of Contents i TECHNOLOGY INC A ADLINK A Trigger Signal Exporting o oooooW a 38 3 5 Trigger Modes cse eee eric bed 39 Post trigger Acquisition eseeeeeeeees 39 Pre trigger Acquisition oooooooooooowan 40 Middle trigger Acquisition ooooWooo 41 Delay trigger Acquisition ooooooooo 41 Post trigger or Delay tr
29. egin the operation 34 Operation Theory ADLINK TECHNOLOGY INC 3 4 2 External Digital Trigger An external digital trigger occurs when a TTL rising edge or a fall ing edge is detected at the SMB connector TRG IO on the front panel As illustrated in Figure 3 8 the trigger polarity can be selected by software Note that the signal level of the external dig ital trigger signal should be TTL compatible and the minimum pulse width is 20 ns Pulse Width gt 20 ns Pulse Width gt 20 ns Rising edge Falling edge trigger event trigger event Figure 3 8 External Digital Trigger Polarity and Pulse Width Requirement Operation Theory 35 A A ADLINK TECHNOLOGY INC 3 4 3 Analog Trigger You can choose either CHO CH1 CH2 or CH3 as the trigger sig nal while using external analog trigger source The trigger level can be set by software with 8 bit resolution Please refer to Table 3 3 for the ideal transfer characteristic Trigger Level Trigger Voltage Trigger Voltage Setting Hex 1V to 1V Range 0 2V to 0 2V OxFF 0 992V 0 1984V OxFE 0 984V 0 1968V 0x81 0 0078V 1 56mV 0x80 OV OV 0x7F 0 0078V 1 56mV 0x01 0 992V 0 1984V Table 3 3 Ideal Transfer Characteristics for Analog Triggers The trigger conditions for analog triggers are illustrated in Figure 3 9 and described as follows gt Positive slope trigger The trigger event occurs when the trigger si
30. ent Occurs Operation start the specified amount of data has Acquisition stop Acquisition start been acquired will be ignored Begin to transfer data to system Time Trigger Data X samples have been acguired before trigger occurs where X lt N N samples j Figure 3 13 Pre trigger Mode Operation 40 Operation Theory ADLINK TECHNOLOGY INC 3 5 3 Middle trigger Acguisition Use middle trigger acquisition when you want to collect data before and after the trigger event The amount of stored data before and after trigger event can be set individually M and N samples as illustrated in Figure 3 14 Operation start Acquisition stop Acquisition start Trigger event occurs Begin to transfer data to system Time Trigger Data M samples N samples Figure 3 14 Middle trigger Mode Operation Please note that trigger event can only accepted when the speci fied amount of data has been acguired M samples If the sam pled data is not enough the trigger event will be ignored 3 5 4 Delay trigger Acquisition Use delay trigger acquisition to delay the data collection after the trigger event as illustrated in Figure 3 15 The delay time is speci fied by a 32 bit counter value so that the maximum delay time is the period of TIMEBASE X 232 1 while the minimum delay is the period of timebase Acquisition stop Operation Trig
31. ger Event x Begin to transfer data to start Occurs Acquisition start system EN uum E A Time Trigger Data N samples Figure 3 15 Delay trigger Mode Operation Operation Theory 41 A ADLINK A TECHNOLOGY INC 3 5 5 Post trigger or Delay trigger Acquisition with Re trigger Use post trigger or delay trigger acquisition with re trigger function to collect data after several trigger events as illustrated in Figure 3 16 You can program the number of triggers then the dig itizer will acquire a specific sample data each time a trigger is accepted All of sampled data will be stored in onboard memory first until all trigger events occurred Thus the time between last sampled data and next trigger event can be only one clock period of timebase After the initial setup the process does not require software intervention PM 1st Trigger Event Occurs 2nd Trigger Event Occurs di Time Trigger Data N samples A N samples Figure 3 16 Re trigger Mode Operation 42 Operation Theory ADLINK TECHNOLOGY INC 3 6 Data Transfers Since the maximum data throughput on the PCI PXI 9846 40MS s 4 channels 2 Bytes channel 320MB s is much higher than the 32bit 33MHz PCl bus bandwidth samples are acquired into the onboard SDRAM memory before being transferred to the host computer Since the number of stored samples per acquisition is limited by the amount of on board memory the PCI PXI
32. gn the module s edge with the card guide in the PXI chassis 3 Slide the module into the chassis until resistance is felt from the PXI connector 4 Push the ejector upwards and fully insert the module into the chassis 5 Once inserted a click can be heard from the ejector latch 6 Tighten the screw on the front panel 7 Power on the PXI system chassis To remove the module reverse step 2 through 6 above To install the PCI 9816 PCI 9826 PCI 9846 module 1 Turn off your computer 2 Remove the top cover of your computer 3 Select an available PCI slot and remove the bracket retaining screw and the bracket cover 4 Line up the PCI digitizer with the PCI slot on the back panel Slowly push down on the top of the PCI digitizer until its card edge connector is resting on the slot recep tacle 5 Reinstall the bracket retaining screw to secure the PCI digitizer to the back panel rail 6 Restore the computer cover Getting Started 23 ADLINK TECHNOLOGY INC 2 5 Software Support ADLINK provides comprehensive software drivers and packages to suit various user approaches to building a system Aside from programming libraries such as DLLs for most Windows based systems ADLINK also provides drivers for other application envi ronment such as LabVIEW and MATLAB ADLINK also pro vides ActiveX component ware for measurement and SCADA HMI and breakthrough proprietary software applications All software
33. gnal analog input signal changes from a voltage that is lower than the specified trigger level to a voltage that is higher than the specified trigger level gt Negative slope trigger The trigger event occurs when the trigger signal analog input signal changes from a voltage that is higher than the specified trigger level to a voltage that is lower than the specified trigger level 36 Operation Theory ADLINK TECHNOLOGY INC Positive Slope Trigger Event Negative Slope Trigger Occurs Event Occurs A Trigger Level Analog Signal Figure 3 9 Analog Trigger Conditions 3 4 4 PXI STAR Trigger When you select PXI STAR as the trigger source the PXI 9816 PXI 9826 PXI 9846 can accept a TTL compatible digital signal as a trigger signal The trigger occurs when a rising edge or falling edge is detected at PXI STAR You can use software to configure the trigger polarity The minimum pulse width requirement of this digital trigger signal is 20 ns 3 4 5 PXI Trigger Bus The PXI 9816 PXI 9826 PXI 9846 utilizes PXI Trigger Bus 0 7 as System Synchronization Interface SSI Using the interconnected bus provided by PXI Trigger Bus you can easily synchronize mul tiple modules When configured as input the PXI 9816 PXI 9826 PXI 9846 is served as a slave module and can accept three different SSI sig nals SSI TRG1 SSI TRG2 and SSI START OP When config ured as output the PXI 9816 PXI 9826 PXI 9846 is serv
34. h lt 16 bit ADC y i Y A pc CH1 Analog Input Path 4 p 16 bit ADC N PCI 98X6 Local Bus m Y Controller sa n g CH2 Analog Input Path Id 16btADC a A gt x 5 S se 32 bit 66MHz amp RI a PCI Controller CH3 3 Ld Analog Input Path A 16i ADC Y Calibration Circuit Precision Reference Figure 3 2 PCI 98x6 Functional Block Diagram Operation Theory 27 TECHNOLOGY INC A ADLINK A 3 2 Basic Al Acquisition In this section we are going to explain the basic acquisition timing 3 2 1 Analog Input Path The following figure shows the block diagram of the single analog input path of a digitizer Each path provides a choice of 50 Q input impedance or high impedance The gain amplifier is optimized for each input range with low noise and high dynamic range An anti aliasing filter is also adopted to eliminate high frequency noise The 16 bit ADC provides not only accurate DC performance but also high signal to noise ratio high spurious free dynamic range in AC performance Calibration Source m 16 bit i ali Onboard Protection Hi Impedance Anti aliasing 40M 20M 10M p H PCI Interface EG fe Ege Gan Amper AP pipe M OME Memory 500 vw Figure 3 3 Analog Input Signal Block Diagram 3 2 2 Basic Acquisition Timing The trigger is a signal that starts or stops the acquisition In post trigger mode and
35. heory of the PCI PXI 9816 26 46 is described in this chapter including the control and setting of signal sources trigger sources trigger modes data transfers and synchronizing multiple modules 3 1 Functional Block Diagram Sa PXI Trigger Bus 7 0 CLKIN OC gt Trigger Routing _ a E ya pat i 3 TRG O OC le gt Timing Control ja PXI STAR Trigger Analog Trigger A PXI 10MHz CLK x Circuit a Y j Memory bA P CHO Lp Analog Input Path lt 16 bit ADC y Y a CH1 gt Analog Input Path 4 p 16 bit ADC i _ gt N PXI 98X6 Local Bus i y nn S Controller CH2 gt Analog Input Path e 16 bit ADC a Lx N 5 T a x N 32 bit 66MHz amp AT PCI Controller gt CH3 gt Analog Input Path e T6bitADC HI gt N T Nami Y Precision Reference Source L 4 Calibration Circuit lt q N Figure 3 1 PXI 98x6 Functional Block Diagram y CLKIN DI gt Trigger Routing p a 5 3 TRGIO OO lt pel Timing Contro x y S Analog Trigger ircuit ind Memory 4 CHO Analog Input Pat
36. igger Acquisition with Re trigger 42 3 6 Data Transfers eee e de rete 43 3 7 Synchronizing Multiple Modules 44 SSI TIMEBASE see hai tiene d anakan 47 SONIC 48 SSI TRIG2 and SSI START OP oo mm 49 Comparing the Different Trigger Sources from SSI 50 3 8 Physical Location of the PXI and PCI Digitizer 52 Identify PXI Digitizer s Physical Location by Geographic Address 1 11 1111 52 Assign a Board ID to a PCI Digitizer 52 Important Safety InstructionSs m ns 55 ii Table of Contents ADLINK TECHNOLOGY INC List of Tables Table 1 1 Analog Input Specifications iioooooc 4 Table 1 2 Offset and Gain Error ooooooooooooo WWW 4 Table 1 3 3dB Bandwidth typical oooooooWooWooWo 5 Table 1 4 System Noise eee Woman 7 Table 1 5 Spectral Characteristics PCI PXI 9816 8 Table 1 6 Spectral Characteristics PXI 9826 10 Table 1 7 Spectral Characteristics PCI PXI 9846 12 Table 1 8 Timebase i oooocoooco Woman 14 Table 1 9 Triggering zvanam augiem ete d ae 15 Table 1 10 Data Storage and Transfer 2 244111122211 16 Table 1 11 Onboard Reference ooocoocoooo 16 Table 1 12 General Information o ooooooooc 17 Table 2 1 Connector Pin Assignments 1 111121111 22 Table
37. ith out need for any manually adjustments Once the calibration pro cess has completed the calibration information will be stored in the on board EEPROM so that the values can be loaded and used as needed by the board 2 Introduction ADLINK TECHNOLOGY INC 11 Features 3U Eurocard form factor PXI version Standard height half length PCI form factor PCI version Support 5 V and 3 3 V PCI signaling Support 32 bit 66 MHz PCI interface 4 channels simultaneous single ended analog input 16 bit high resolution ADC Up to 10 MS s 20 MS s and 40 MS s per channel 512 MB onboard memory for data storage Software selectable 50 Q or 1 MQ input impedance Programmable input voltage range 0 2V 1V or 1V 5V 5 MHz 10 MHz and 20 MHz analog input bandwidth for PCI PXI 9816 PCI PXI 9826 and PCI PXI 9846 respec tively Multiple modules synchronization through PXI trigger bus Support scatter gather DMA transfer Fully auto calibration 90 dBc SFDR 79 dBc SINAD and 12 8 bit ENOB PXI 9816 vw Ww Ww Ww ww wWwWNwWNww v www 1 2 Applications Software radio wireless communication Radar Sonar Lidar Ultrasound Imaging Military Laboratory Research www v V Introduction 3 TECHNOLOGY INC A ADLINK A 1 3 Specifications Analog Input Specification Value Number of Channels 4 single ended channels Input Connector BNC Input Impedance 50 or 1 MO software selectable default 500 Input Coup
38. ling DC Input Range t0 2V 1V or 1V 5V software selectable 5V for 0 2V 1V Overvoltage Protection 15V for 1V 5V ADC Resolution 16 Bit 1 in 65536 Crosstalk lt 80 dB at 1MHz for all input ranges at 50 O input impedance Table 1 1 Analog Input Specifications Offset Error Rosa PXI 9846H PXI 9826D PCI 9816H Model Name PXI 9846D PCI 9826H A PCI 9846H PCI 9846D Offset Error t0 2 mV 0 3 mV Gain Error Input Range 0 2 V 1 V 1 V 5 V Gain Error 0 1 0 05 0 1 0 06 Note When calculating offset error and gain error sampled data are averaged with 65536 points and Al channel configured with 50 Q input impedance Table 1 2 Offset and Gain Error 4 Introduction 3dB Bandwidth typical ADLINK TECHNOLOGY INC PXI 9846D Input Range PXI 9816D PXI 9826D PCI 9846D PXI 9846W 80MHz 1 V 0 2V 1 V 5 1MHz 9 6MHz 20MHz 50MHz 0 2 V PXI 9846H Input Range PCI 9816H PCI 9826H PCI 9846H 1V 5V 5 1MHz 9 6MHz 20MHz Table 1 3 3dB Bandwidth typical Introduction ADLINK TECHNOLOGY INC A A PXI 9816 10M 1M Frequency Hz Figure 1 1 PCI PXI 9816 Bandwidth Chart PXI 9826 Freguency Hz M 1 Figure 1 2 PCI PXI 9826 Bandwidth Chart Introduction PXI 9846 Amplitude dB Frequency Hz Figure 1 3 P
39. ngho City Taipei County 235 Taiwan ATERPE i 166 ji 9 TE Tel 886 2 8226 5877 Fax 886 2 8226 5717 Email service adlinktech com Ampro ADLINK Technology Inc Address 5215 Hellyer Avenue 110 San Jose CA 95138 USA Tel 1 408 360 0200 Toll Free 1 800 966 5200 USA only Fax 1 408 360 0222 Email infoQadlinktech com ADLINK Technology Beijing Address JER TIREX EHhZRER 1 54461317 XJ amp E Jk 801 100085 Rm 801 Power Creative E No 1 B D Shang Di East Rd Beijing 100085 China Tel 86 10 5885 8666 Fax 86 10 5885 8625 Email marketQadlinktech com ADLINK Technology Shanghai Address LATA 2 ey BESTE Ack EL 333 5 39 lit 4 JZ 200233 Tel 86 21 6495 5210 Fax 86 21 5450 0414 Email market adlinktech com ADLINK Technology Shenzhen Address YIT Mil dad BPN A1 2 FE C X 518057 2F C Block Bld A1 Cyber Tech Zone Gao Xin Ave Sec 7 High Tech Industrial Park S Shenzhen 518054 China Tel 86 755 2643 4858 Fax 86 755 2664 6353 Email market adlinktech com El A A ADLINK TECHNOLOGY INC ADLINK Technology Inc German Liaison Office Address Nord Carree 3 40477 Duesseldorf Germany Tel 49 211 495 5552 Fax 49 211 495 5557 Email emea adlinktech com ADLINK French Liaison Office Address 15 rue Emile Baudot 91300 MASSY Cedex France Tel 33 0 1 60 12 35 66 Fax 33 0
40. options are included in the ADLINK All in One CD 2 5 1 Driver Support for Windows DAQPilot DAQPilot is a driver and SDK with a graphics driven interface for various application development environments DAQPilot comes as ADLINK s commitment to provide full support to its comprehen sive line of data acquisition products and is designed for the nov ice to the most experienced programmer As a task oriented DAQ driver SDK and wizard for Windows sys tems DAQPilot helps you shorten the development time while accelerating your learning curve for data acquisition programming IPAGPilot NI ANALOG INPUT ANALOG OUTPUT DIGITAL INPUT DIGITAL OUTPUT TIMER CTR Figure 2 3 DAGPilot Main Interface 24 Getting Started ADLINK TECHNOLOGY INC You can download and install DAQPilot at http www adlinktech com TM DAQPilot html DAQMaster The ADLINK DAQMaster is a smart device manager that opens up access to ADLINK data acquisition and test and measurement products DAQMaster delivers all in one configurations and pro vides you with a full support matrix to properly and conveniently configure ADLINK Test and Measurement products As a configuration based device manager for ADLINK DAQ cards DAQMaster enables you to manage ADLINK devices and inter faces install and upgrade software applications and manage ADLINK DAQPilot tasks DA Merter sa Bh Opes Yew Help CSE Qe PARE 0 PR Z L DA Device O
41. ple modules are installed in one host system The PXI 9816 26 46 can read back the Geographical Address through software driver Please refer to software function reference man ual for more detail description 3 8 2 Assign a Board ID to a PCI Digitizer When users plug two or more PCI 9816 26 46 modules in one computer board ID provides an effective mechanism for user to identity the specific module With this method users can access to specific module in accordance with board ID The dip switch of board ID is located on the top of the module Please refer to fol lowing figure and table for detail setting Please note that users have to assign a unique board ID to each module that are installed in the same computer otherwise soft ware driver will not allocate correct system resource to these mod ules Once users assign identical board ID to different module please turn off your computer first and then adjust the board ID again After correct board ID is assigned then users can power up computer again 52 Operation Theory ADLINK TECHNOLOGY INC Figure 3 25 The Location of Board ID Switch Figure 3 26 Enlargement of Board ID setting Note Only dip switches 1 5 are valid for board ID settings Dip switches 6 9 are unused When a dip switch is switched to ON it represents 1 the opposite direction represents 0 Operation Theory 53 eases A A
42. r pre trigger and middle trigger modes are also avail able to acquire data around the trigger event The PCI PXI 9816 26 46 also features repeated trigger acquisition so you can acquire data in multiple segments with successive trigger events at extremely short rearming intervals Multiple Module Synchronization The versatile trigger options provided by the PXI backplane allow the PCI PXI 9816 26 46 to achieve multi module synchronization in a simplified way Utilizing the PXI Trigger bus the PCI PXI 9816 26 46 can output trigger signals and the timebase to the PXI trigger bus when configured as a master or receive trigger signals and the timebase from the PXI trigger bus when configured as a slave Moreover when the PCI PXI 9816 26 46 is plugged into a peripheral slot of a PXI system they can also receive triggers or the timebase from the PXI star trigger controller slot The precision 10 MHz clock that comes from the PXI backplane can also be used as one of the timebase sources Combining these PXI trigger features with the interface of the PCI PXI 9816 26 46 makes it very easy to synchronize multiple modules Calibration The PCI PXI 9816 26 46 include a precision on board reference with very low temperature drift This feature not only provides a stable calibration source for auto calibration but also maintains stable acquisition accuracy over a wide temperature range The automated calibration process can be done through software w
43. t to another with input freguency and with the full scale input range selected Table 1 6 Spectral Characteristics PXI 9826 PX 9826 0 2V S Rate 20MS s Input Signal 0 998 MHz 0 8754 dBFs Magnitude dB Freguency Hz x 10 Figure 1 6 PXI 9826 FFT with 0 2 V Input Range 10 Introduction 20MS s Input Signal 0 998 MHz 1 0796 dBF PX1 9826 1V S Rate I I I o GREENA AOE id ra alas a s 2 I I A MU We EOI Xi M I DA me WED ni ol I k abia os fee oe We ee Eo LL I F I I I I 1 1 o o o o o q Y 9 gp epmiubew x 10 Frequency Hz Figure 1 7 PXI 9826 FFT with 1 V Input Range 11 Introduction TECHNOLOGY INC A ADLINK A Spectral Characteristics PXI 9846 Specification Input Range 1 V 0 2 V Signal to Noise and Distortion SINAD typical 76 06 dBc 71 97 dBc Signal to Noise Ratio SNR typical 76 17 dBc 71 98 dBc Total Harmonic Distortion THD typical 90 65 dBc 95 78 dBc Spurious Free Dynamic Range SFDR typical 91 62 dBc 96 15 dBc
44. tput Level Driving Capability 8 MA Minimum Output Pulse Width iis Analog Trigger Sources Al channel 0 3 Trigger Slope Rising or falling software selectable Trigger Level Range Full scale input range Trigger Level Resolution 8 bit 256 steps in full scale range Table 1 9 Triggering Introduction 15 TECHNOLOGY INC A ADLINK A Data Storage and Transfer Specification Value Onboard Memory Size 512 MB share for four channels Data Transfer Scatter gather DMA Table 1 10 Data Storage and Transfer Onboard Reference Specification Value Onboard Reference Voltage 5V Temperature Drift 3 ppm C Recommended Warm up Time 15 minutes Table 1 11 Onboard Reference 16 ADLINK TECHNOLOGY INC General Information Specification Value Environment Ambient temperature 0 C to 55 C for PXI version 0 C to 50 C for PCI version Relative humidity 10 to 90 non condensing Ambient temperature 20 C to 85 C Relative humidity 10 to 90 non condensing Operating Environment Storage Environment Physical PXI version Single 3U PXI module 100 mm by PCB Dimension 160 mm not including connectors PCI version Standard height half length PCI card 167 64 mm by 106 68 mm PCI Slot Width 1 slot PCI Bus Interface PCI Signaling Support 3 3
45. u want to collect data after the trigger event as illustrated in Figure 3 11 Operation Trigger Event Occurs Acquisition stop start Acquisition start Begin to transfer data to system Time Trigger Data N samples Figure 3 11 Post trigger Acguisition Operation Theory 39 TECHNOLOGY INC A ADLINK A 3 5 2 Pre trigger Acquisition Use pre trigger acquisition to collect data before the trigger event The acquisition starts once specified function calls are executed to begin the pre trigger operation and it stops when the trigger event occurs If the trigger event occurs after the specified amount of data has been acquired the system only stores the data before the trigger event with specified amount as illustrated in Figure 3 12 Trigger Event Occurs Acquisition stop Operation start Begin to transfer data to Acquisition start System SA Time Trigger Data N samples A Y de Y These data will be Only acquired N discarded samples will be transfer back to system Figure 3 12 Pre trigger Mode Operation The trigger event occurs after the specified amount of data has been acquired However if the trigger event occurs before the specified amount of data has been acquired the acquisition engine will ignore the trigger signal until the specified amount of data has been acquired Refer to Figure 3 13 for an example Trigger signals that occur before Trigger Ev
46. uisition Acquisition starts right after this clock edge In Progress Figure 3 6 Configuring Different Sampling Rate of a Digitizer 3 3 5 Timebase Exporting The PCI PXI 9816 26 46 can export timebase to one of the eight PXI trigger bus lines By software programming you can pick up a trigger line to transmit timebase clock This feature is very useful when synchronize to multiple measurement modules Operation Theory 33 TECHNOLOGY INC A ADLINK A 3 4 Trigger Sources In addition to the internal software trigger the PCI PXI 9816 26 46 also supports external analog triggers external digital triggers PXI_STAR triggers PXI Trigger Bus 0 7 and SSI bus You can configure the trigger source by software command Please refer to Figure 3 7 for trigger architecture TRG IO Software Trigger b M To Internal SMB Connector Digital Trigger Input R Circuit TRG IO P SMB Connector Digital Trigger Output EN m igital Trigger Outpu Analog CH1 Analog TRO Trigger nalog EN E AnalogCH3___ 3 1 8 8 Trigger gt 5 9 m7 PXI_STAR Decision 5 5 o S E t PXI Trigger Bus 0 7 8 E E 2 E E 5 SSI_TRIG1 x SSI TRIG2 SSI_START_OP amp SSI Bus Only available in PCI version Figure 3 7 PCI PXI 98x6 Trigger Architecture 3 4 4 Software Trigger Software trigger is generated by software command The trigger asserts right after executing specified function calls to b
47. verview Support Matrix Master reme gt PCI LECI ePCI PCIe PI Windows Limm DAOBench Cempenentee e 1 y v PCI DASA PCIE Dawan t t E TA DewceHanagednialedi de Vai Devce Ba Andog Odos Modes BER Distal UO Mode JEZ Dotze Mode p Let Mode perasa oczna v Than v rsa s ss Device Manager Installed Drag the selected device item to subfunction burton to launch T Calibrates DAO 2000 series modules ye y Figure 2 4 DAQMaster Device Manager Getting Started 25 ADLINK TECHNOLOGY INC 2 5 2 WD DASK Legacy Drivers and Support WD DASK is composed for advanced 32 bit kernel drivers for cus tomized DAQ application development WD DASK enables you to perform detailed operations and achieve superior performance and reliability from your digitizer system DASK kernel drivers now support the revolutionary Windows Vista OS User Mode Kernel Mode Delphi Structure Lo DASK Kornol Driver BCB sys pv Object s Manager 2 9 a 2 e VC 1 5 o 7 s 5 HE Z Executive 5 s an ager Support P a 2 cj gt z vB 2 H E Contiguration Power Manager P ug and Pay Manager Ir VB NET ce VO Manager File System Lowestiovel Figure 2 5 Legacy Software Support Overview 26 Getting Started ADLINK TECHNOLOGY INC 3 Operation Theory The operation t
48. z for PCI PXI 9816 PCI PXI 9826 and PCI PXI 9846 respectively The input ranges are software programmable as either 1 V or t0 2 V Software selectable 50 O input impedance makes it easy to interface with high speed high frequency sig nals Acquisition System and On board Memory The PCI PXI 9816 26 46 include four 16 bit A D converters to digi tize the input signals These four channels sample signals simulta neously at a maximum sampling rate of 10 MS s 20 MS s and 40 MS s respectively The PCI PXI 9816 26 46 supports a total of 512 MB on board memory The digitized data is stored in the on board memory before being transferred to the host memory The data transfer is performed using scatter gather DMA which pro vides a high data throughput rate and uses system memory more effectively If the data throughput from digitizer is less than the available PCI bus bandwidth the PCI PXI 9816 26 46 also fea tures an on board 2 K sample FIFO to achieve real time transfer directly to the host memory by bypassing the on board memory Introduction TECHNOLOGY INC A ADLINK A Flexible Triggering The PCI PXI 9816 26 46 feature flexible triggering options such as a software trigger external digital trigger an analog trigger from any of the analog input channels and triggers from the PXI trigger bus These versatile trigger sources allow you to configure the PCI PXI 9816 26 46 to fit your application needs Post trigger delay trigge
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