plotline user manual
Contents
1. Product brief brochure for the PLOTLINE IP core README This file README html HTML version of README README pdf PDF version of README VERSION Current version of the PLOTLINE IP core rtl vhdl RTL source code directory for the IP core plotline vhd RTL VHDL design file sim rtLsim RTL simulation files directory sim rtlsim bin RTL simulation scripts directory plotline do plotline mk do script for Mentor Modelsim simulation GNU Makefile for GHDL simulation sim rtLsim out Dumps and other useful output from RTL simulation plotline ved plotline_results txt Value Change Dump file generated from RTL simulation Diagnostic output from RTL simulation sim rtl_sim run Files for running RTL simulations plotline_data txt plotline ghdl sh plotline mti sh Reference input output data for RTL simulation Bash shell script for running the GHDL simulation Bash shell script for running the Modelsim simulation sim rtlsim vhdl VHDL sources for RTL simulation clockdiv vhd Parametric clock divider colordec vhd Color decoder to RGB444 data_bram vhd Block RAM based memory model imgmap vhd Plotline data generation and storage data_bram plotline_system vhd Top level VHDL source of the plotline demo system vga_controller vhd Parametric VGA controller sw Software utilities plotline bsl Optimized BASIL model for the plotline2. functionality plotline pbm Generated PBM binary image from C model simulation plotline ppm Generated PPM color image from C model simulation plotline_test c Reference C model for the line drawing application syn xise Synthesis files for use with Xilinx ISE sim xise bin Synthesis scripts directory xst mk Standard Makefile for command line usage of ISE sim rtl_sim out Bitfiles and other useful output from synthesis plotline 256x256 bit Reference bitstream for the plotline system sim rtLsim run Files for running synthesis plotline_sys syn sh Bash shell script for invoking the ISE tools plotline_system bit Newly generated bitstream as the result of synthesis sim rtlsim sre Additional source files for running synthesis plotline_sys_s3an ucf User constraint file for the Xilinx Spartan 3AN starter kit develop ment board 4 Simulation The PLOTLINE IP core distribution supports both GHDL and Mentor Modelsim simulation 4 1 GHDL For running the GHDL simulation change directory to the sim rtl_sim run subdirectory cd PLOTLINE_HOME sim rtl_sim run assuming PLOTLINE_HOME is the directory where the top level plotline is found Then the corresponding shell script is executed plotline ghdl sh The simulation produces two files a VCD waveform dump named plotline vcd and the diagnostic text file plotline_results txt which are automatically copied to the sim rt1l_sim out subdirectory 4 2 Models
3. text HTML and PDF form 2 Functional description PLOTLINE is implemented as a fully synchronous FSMD Finite State Machine with Datapath The interface diagram for streamed pixel generation is shown below The core uses a single external clock source connected to signal CLK It can be asynchronously reset with the active high signal RESET Signal START activates the core Data inputs XO YO and X1 Y1 are the start and end point coordinates Data outputs XOUT YOUT are the x and y axis coordinates of the currently emitted pixel DONE signifies the end of the current computation when VALID is raised a new pair of outputs XOUT YOUT has been generated READY indicates that the core can accept new input 3 File listing CLK READY RESET VALID START gt DONE XO YO x1 XOUT Y1 YOUT Figure 1 PLOTLINE FSMD I O interface The PLOTLINE distribution includes the following files plotline Top level directory bench vhdl Benchmarks VHDL directory plotline_tb vhd std_logic_1164_ta vhd std_logic_textio vhd Self checking testbench for the plotline IP Useful additions to the std_logic_1164 package Draft version of the std_logic_textio package plotline fsmd if png plotline pb pdf doc Documentation directory AUTHORS List of authors LICENSE End user license agreement for using the plotline distribution PNG image illustrating the plotline I O interface
4. al Xilinx ISE command line tools for logic synthesis as de scribed in the corresponding Makefile found in the the syn xise bin subdirectory Typically this process includes the following e Generation of the xst synthesis script file e Generation of the ngc gate level netlist file in NGC format Building the corresponding ngd file Performing mapping using map which generates the corresponding ncd file e Place and routing using par which updates the corresponding ncd file e Tracing critical paths using trce for reoptimizing the ncd file Bitstream generation bit using bitgen Finally the plotline_system bit bitstream file is produced and the impact GUI is invoked From the impact GUI the following procedure is suggested other options are also valid choices e Select No in the Automatically Project File Load popup screen e Select No in the Automatically create and save a project popup screen e Select Cancel in the New Impact project e From within the Impact Flows card near top left double click on Boundary Scan e From the File menu select Initialize Chain e Select Yes in the Auto Assign Configuration Files Query Dialog popup e Select the generated bitfile from the Assign New Configuration File popup for loading to the XC3S700AN device e Subsequently select Bypass in order not to load the XCFO4S PROM e Select OK in the Device Programming Properties popup e Right click to the XC3S700AN devic
5. e GHDL simulator http ghdl free fr or Modelsim http www model com The latest GHDL distribution 0 29 1 Windows version also installs GTKwave on Windows e Xilinx ISE free ISE webpack is available from the Xilinx website http www xilinx com e XnView optional is an image file viewer that supports PBM PGM and PPM files It is available from here http www xnview com
6. e symbol e Select Program FPGA Only Remember to connect a CRT LCD VGA monitor to the development board s DSUB 15 connector 6 Reference software application The reference C application available in the sw subdirectory provides an implementation for Bresen ham s line generation algorithm There are two basic usage schemes of plotline_test c When compiled as follows gcc DTEST DSTREAM Wall 02 o plotline_test exe plotline_test c executing plotline_test exe is used for generating the plotline_data txt reference data file plotline_test exe gt amp plotline_data txt This file should be copied to the sim rtl_sim run subdirectory Alternatively the reference application can be compiled for generating either a PBM monochrome or PPM color image file that emulates the VGA graphics display of the demo plotline system Thus when compiled as follows gcc DTEST DSTORE DDIAGNOSTICS DSPARTAN3AN DCOLOR Wall 02 o plotline_test exe plotline_test c executing plotline_test exe produces the plotline ppm file while gcc DTEST DSTORE DDIAGNOSTICS DSPARTAN3AN Wall 02 o plotline_test exe plotline_test c is used for generating the monochrome plotline pbm file 7 Prerequisities e Standard UNIX based tools tested with gcc 3 4 4 on cygwin x86 make bash shell For this reason Cygwin http sources redhat com cygwin is suggested since it provides a near complete POSIX environment
7. im Similarly for running the Modelsim simulation the corresponding shell script is executed from the sim rtl_sim run subdirectory plotline mti sh As in the GHDL case the VCD dump and the diagnostic text file are produced 5 Synthesis The PLOTLINE IP core distribution supports both logic synthesis of a demo system that utilizes the PLOTLINE IP core for basic graphics generation It should be noted that due to the specific block RAM storage size of the tested device Xilinx XC3S700AN the visible display is limited to 256x256 Different visible display dimensions are possible by configuring the X_OFFSET Y_OFFSET X_SIZE and Y_SIZE generics of the imgmap module 5 1 Demo system The demo system comprises of the following components e plotline_system The top level component e imgmap Provides data content storage Data is generated by plotline vga_controller VGA controller for graphic bitmap output clockdiv Clock divider colordec Color decoder for 16 color generation e data_bram Synchronous read RAM model using separate address ports for writing and reading Reading is solely used for graphics display plotline The actual PLOTLINE IP core component 5 2 Running the synthesis script For running the Xilinx ISE synthesis change directory to the syn xise run subdirectory cd PLOTLINE_HOME syn xise run and execute the corresponding script plotline_system syn sh The synthesis procedure invokes sever
8. plotline user manual Title plotline IP core Author Nikolaos Kavvadias Courtesy of Ajax Compilers Contact nkavvadias ajaxcompilers com Website http www ajaxcompilers com Release Date 07 January 2013 Version 1 0 0 Rev history v1 0 0 07 01 2013 First public release 1 Introduction The PLOTLINE graphics unit module is a synthesizable RTL VHDL model of Bresenham s line drawing algorithm The algorithm determines which points should be plotted in order to form a close approx imation of a straight line segment between two given points x0 y0 and x1 y1 It is typically used for drawing lines on raster displays as well as fundamental functionality in numerous software graphics libraries The algorithm uses only integer operations such as addition subtraction bit shifting comparison absolute value and conditional moves It consists of a single loop that keeps track of the propagated error over the x and y axis which is then used for calculating the subsequent pixel on the line The loop terminates when the end point is reached The following sections provide details on the contents of the distributed IP core which include all necessary materials such as source files and scripts for RTL simulation and logic synthesis Further a demonstration system with VGA output is provided for FPGA testing of the PLOTLINE IP core Reference documentation for PLOTLINE can be found in the doc subdirectory in plain
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