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Manual - Western Avionics Ltd

1. Reserved Reserved Data Message Interrupt Code Data Set of Message Number Data Reserved HS Reserved MRT Reserved HS Data descriptor Block Address Reserved HS HS DATA BUFFERS Time High HS TYPE DATA DESCRIPTOR BLOCK Time Tag Low PA Option Mask DA Reserved LS WC Data Word Count Data Data Status Report Data Toggle Freq Buffer Addr High Buffer Address Low Link Pointer to another DDB Address of Modify Word Data Value to Write Data Message Interrupt Code FCS Set of Message Number Message Indicator in Set of Message HS Frame Time out RI TI Register HS Errors High HS Errors Low Reserved Figure 4 2 Data Buffers Simulation and Monitoring UM 10997 Rev B 40 4 3 1 Look Up Table The sixth word of a message descriptor block points to a double word in the look up table that one contains the address of a LS or HS data descriptor block An identical architecture is defined in MRT mode but using LS sub addresses or HS message identifiers to point into the look up table Look up Table Address Error Injection Word MRT only 02H DDB Address Ext Subaddress look up table address 4 3 2 Data Descriptor Block A data descriptor block is associated with each data message this 16 word set defines the data buffering and associated queue control information Interrupt selection 1s defined in the option mask word Interrupt on correct or erroneous
2. 3 41 Base Register Names and Location The names and locations of the Base Registers are contained in table 3 1 Table 3 1 Base Register Names and Locations BASE Control Register Write Clock HI Word Read 02H Clock LO Word Read only 04H Command Register CR 06H Status Register SR 08H Background Running Pointer BRP Address of Program 0AH Insertion Running Pointer IRP Address of Program 0CH Reserved 0EH Low Priority Interrupt Queue Start Address Pointer 10H Reserved 12H High Priority Interrupt Queue Start Address Pointer 14H Reserved 16H Message Interrupt Queue Start Address Pointer 18H Reserved Status Report Queue Start Address Pointer 1 Reserved Simulation Table Address Register RTSTAD 20H Amplitude Register 22H Coupling Register 24H Toggle Buffer Address Offset MSB 1 Global Enable 26H SET OF MESSAGES Start Address 28H Global RT Response Time Register 15 2AH RT No Response Timeout Register us 2CH HS Subaddress Register 2EH Reserved 30H Reserved 32H Reserved 34H IRQ Selection Register 36H Minor Frame Counter Register 38H Load Clock Register 3AH Load Clock LO Register 3CH
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4. Table 4 2 Data Descriptor Block DDB ADDRESS OPTION MASK 02H Header Address 04H Data Word Count 06H Data Status Report 08H Toggle Frequency and Buffer Address HI 0AH Buffer Address LO 0CH Link Pointer to Address of another DDB 0EH Address of Modify Word 10H Value to Write 12H Message Interrupt Code 14H Set of Message Number 16H Message Indicator in the Set of Messages 18H RT TI Time Register 1AH 3910 Error Injection 1 1CH 3910 Error Injection 2 1EH 3910 Error Injection 3 10997 RewB 41 4 3 21 Option Mask 00H BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 09 BIT 08 BIT 07 BIT 06 BIT 05 BIT 04 to 00 1 Interrupt on Correct Message 1 Interrupt on Error Message 1 HI LO Priority Queue 0 LO 1 HI 1 Interrupt on Set of Messages 1 Message Interrupt If Message Correct 1 Link only on Correct Message 1 Link to New DDB Enabled 1 Modify Word Enabled 0 0 0 Header Word Count 4 3 2 2 Data Status Report 06H BIT 15 to 14 BIT 13 to 00 NOTE 00 Good Message 01 Message Running 10 Error Message Signed Wordcount Error 0 No Wordcount Error The wordcount error is calculated as follows 3838 TX Wordcount Command Wordcount DDB Count Header Count 3838 RX Wordcount Wordcount Received DDB Count Header Count 3910 TX Wordcount Action Wordcount DDB Count 3910 RX Wordcount Action Wordcount DDB Count
5. 58 6 2 6 IRQ Selection Register 34 58 6 2 7 Load Clock HI LO Registers 38 1 59 6 2 8 Current Address Register CAR 42H sese eene nennen rennen 59 6 2 9 Trigger Occurrence Register TOR 44H essen 59 0 2110 Trigger Set up Pointer ISP 469 ee tese eee gon toe res ree gae dete 59 63 DETAILED TRIGGER DESCRIPTION 60 64 STACK DATA PORMA Donoro BU RUPEE UR 70 6 4 1 Previous Address Pointer epe t etr eleg labs ea aes pa EEE Ra bees 70 6 4 2 Time Stamp FLL aaa 70 6 4 3 Mem Or E 70 6 4 4 Next Address Pointer eter OR eU FEN ED EORR REO IR 71 6 4 5 Response Time 1 2 RR 71 6 5 3910 72 6 5 1 IIIS EE 72 UM 10997 Rev B 4 List of Figures Figure 1 1 VME 4220 Board Functional Block Diagram 4 20 0 1 10 Figure 1 2 Front Panel connectors amp indicators diagram eese eee 13 Figure 1 3 Location of Address Switches and Linker
6. teu ie ere 12 111 TOOLS AND TEST EQUIPMENT ertt tritt e ee enhn e aa exito de 12 112 SAFETY PRECAUTIONS erue Po cis en EE EAE Paria 12 2 INSTALLATION AND PREPARATION FOR 6 0 1 15 24 GENERAE 15 22 INSTALLATION 4220 2040 dec et Hu ee ede dde uo EHE ae EA pre E RR Ex eeu ph 15 2 3 TURN ON m 15 2 4 SELETES ae ertet dnte eee detinet eire devi ases 15 25 SPECIFIC 3838 3910 INTERFACE 16 2 5 1 CLOCK IIT ERE 16 2 3 2 IRTG B Counter nn M 16 2 5 3 IrigserIn Features case ri E R 16 2 5 4 Trigger Out Features esses TA EE EEEE 16 20 VME INTERFACE tette 17 2 6 1 17 2 6 2 jo 17 2 6 3 Electrical Characteristics essent 17 2 6 4 umm 18 27 3838 INTERFACE c 18 2 7 1 Int
7. 34 4 1 ee eee ceed epee cee 34 42 MESSAGE DESCRIPTOR BLOCK 35 4 2 1 Message Number 00H sess eee nnne treten nennen enne nnne 35 4 2 2 LS Event 02H eet eerte be rbd oae Reate bo 35 4 2 3 Message Type Word 04H eee n nemen cebat eade ce irre DS edebat red ct 36 4 2 4 LS Message Error Phase Definition 06H sse eene eene 37 4 2 5 LS Message Error Description Word 08H sese eene 37 4 2 6 Address in Look Up Table eene nre 38 4 2 7 Command Word ua Reve a bay ERE Use eee obi kde a eee EEE 38 4 2 8 Command Word 2 38 4 2 9 ACHON Word 1 LOD m 38 4 2 10 Action Word 2 12H ete ee e oes esten cast ented 38 4 2 11 Retry Subroutine Absolute Address 14H sse enne nnne 38 42 12 HS Event Mask LOE iiec heit ode err Deo vt 39 4 2 13 Inter message Gap Time 18 39 4 2 14 HS RT RT Inter message Gap Time sees eee nennen nennen 39 4215 Status Word LUCH uui stein ROG CO UI ERR GERE cuis cas Copas e RUE OR RR 39 4226 Status Word 2
8. 54 5 6 1 Low and High Priority Interrupts two word code eene eene 54 5 6 2 Message Interrupts or set of messages interrupt essent 54 5 6 3 Status Report Queue two words per report esses eene entes 54 5 7 SPECIFIC EUNGCTIONS UE eR EE UD UE Reg 55 5 7 1 Message R ception i Lega eret E ER T Ve R 55 5 7 2 Reception of Mode Commands Data 55 5 7 3 Mode Command Synchronise with Data Word esses eene 55 5 7 4 Prequency Topple DE ret sedora d eres d onore btt 55 3 73 Programmable HS RI TI Time in 55 10997 Rev B 3 6 CHRONOLOGICAL BUS MONITOR MODE OF 56 6 1 INTRODUCTION weds 56 627 5 i RID RD OO ORO OUR 56 6 2 1 Control Register Write 00 57 6 2 2 Command Resister GR ete e bete Re et aae ee edat sles epe e Rasa pes baden 57 6 2 3 Status Register SR ass oh 58 6 2 4 Transformer Direct Coupling Select Register eee eene 58 6 2 5 HS Subaddress
9. 0 0 0 0 Cycling Message HI Queue LO Queue 0 0 C 0 M 0 0 0 0 L C Ifset a physical INTA interrupt will be generated when a Broadcast Synchronise With Data mode code occurs M If set a physical INTA interrupt will be generated when a push to the Message Queue occurs Ifset a physical INTA interrupt will be generated when a push to the High Priority Queue occurs L If set a physical INTA interrupt will be generated when a push to the Low Priority Queue occurs 3 4 2 26 Test and Set Register and SRQADP 3CH These two words are used to automatically manage FIFO s of vector words for each simulated RT For simulated RTs the Service Request bit in the status word can be set and reset by the user The vector word can be initialised by the user After a Transmit Vector Word mode command message the on board processor automatically resets the service request bit and the vector word On the other hand a service request queue is defined to automatically queue words representing successive requests for the simulated RTs This service request queue is 3 words long starting at the initial address in the service request queue address pointer SRQADP For a request two words are set in the queue as follows 1 RT number 000000000RRRRRIX RT address X Priority 1 1 2 Vector word Two different priorities are available X High priority X 1 Low priority Reading this FIFO the on board processo
10. Gap between the two 3838 messages initiating a HS RT RT message LSB lus Intermessage HS Data Message 3910 4 2 14 Status Word 1 ICH First RX Status Word in the message If the BC detects no response error this value will be updated with FFFFH 4 2 15 Status Word 2 Second RX Status Word in the message RT RT If the BC detects a no response error from the second RT this value will be updated with FFFFH UM 10997 Rev B 39 43 DATA BUFFERS SIMULATION AND MONITORING The Western Avionics 4220 board processes all the data buffers running on the LS and HS lines Data buffers to be issued by the BC or the simulated RTs are transmitted by the 4220 board all others can be monitored A multiple data buffering structure is implemented Identical paths are used to access the data buffers whether they are transmitted received LS or HS These paths use a look up table and data descriptor block Refer to figure 4 2 Data Buffers Simulation and Monitoring LOOK UP TABLE LS TYPE DATA DESCRIPTOR BLOCK LS DATA BUFFERS Option mask Time Tag High Header Address Time Tag Low NOCET Data Word Count Data Data Status Report Data Data descriptor Block Address Toggle Freq Buffer Addr High Buffer Address Low Link Pointer to another DDB
11. 20000H 1 message 8000H Selective Capture Forever 04H Start Page Register SPR This register will contain the desired PAGE address for the start of the monitor stack area 06H Finish Page Register FPR This register will contain the desired PAGE address for the end of the monitor stack area This value must be greater than the Start Page Register value 08H Window Word Count Register This register will contain the word number in the specified message on which the window trigger test is to be carried out If this value is zero the test will be carried out on any word within the specified message UM 10997 Rew B 59 0 3910 Trigger Error Register This register will define the error s in a 3910 message required for a trigger condition to occur If more than one error is defined the condition will be a logical OR of these errors This register is only relevant when the monitor trigger is in 3910 mode D15 D14 D13 D12 D11 D10 D08 D07 DOS D04 D02 DOO D 0 0 0 0 0 0 0 0 W F P E R B W Trigger on Word Count Error F Trigger on FCS Error P Preamble bit count error E Manchester encoding error R RI timeout no HS response B Bit count error 0CH Hardware Trigger Register D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 DOS
12. 4 3 2 3 Toggle Frequency and Buffer Address HI 08H The word 24H in Base Registers defines if the data buffer toggle feature is enabled and also the toggle offset MSB 1 global toggle enabled 0 no toggle offset 15 bits MSB OFFSET 15 14 0 The 5th word in a DDB enables the toggle feature for the corresponding data buffer and the toggle frequency BIT 15 BIT 14 to 11 BIT 10 to 08 BIT 07 to 00 1 Enable toggle local 0 Frequency indicator gt 000 FHz 001 F 2Hz 011 F AHz 111 F 8Hz Buffer Address When global toggle 1s enabled for a data buffer if the toggle feature is selected bit 15 1 the address of the toggle buffer is Buffer Address High Toggle Buffer Offset 15 bits Buffer Address Low 10997 Rev B 42 DDB Buffer Bank A 15 1 Buffer Address Offset Buffer Bank B The toggle 1s synchronised on the minor frame counter register which is incremented on each minor cycle restart The on board processor stores the data buffer in bank A or B depending on the number of the running minor cycle and the frequency indicator of the message Minor Cycle 0 frequency F F Hz F 2 Hz F 4 Hz F 8 Hz 952 tA gt w Q gt gt gt gt gt gt gt w gt gt w gt gt gt 99 gt gt gt
13. D11 D10 D09 D08 D07 D06 DOS 004 D02 DOL DOO 0 0 0 Py Mn Lg Sh 0 0 WC 0 0 NR TA Sy 0 Sy 1 Sync Type Error Sh 1 Short Word Error TA 1 Terminal Address Error Lg 1 Long Word Error NR 1 No Response Error Mn 1 Manchester Error WC 1 Wordcount Error Py Parity Error Trigger Data 4 Trigger Data 4 Bit Mask Register Base Address 54H This register will define the bits to be ignored in the trigger bit pattern for trigger data 4 Any bit set in this register will be masked from the trigger test condition Trigger Data 4 Bit Pattern Register Base Address 56H This register will define the bit pattern required for trigger data Trigger Data 4 Bus ID Word Type Mask Base Address 58H This register will define the Bus ID and Word Type bits to be ignored in the Bus ID Word Type Register D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 DOS 004 D02 DOL DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 Both W bits 1 Ignore Word Type in trigger condition Both B bits 1 Ignore Bus ID in trigger condition Trigger Data 4 Bus Word Type Register Base Address 5AH This register will define the Bus ID and Word Type for the trigger condition D15 D14 D13 D12 D11 D10 D08 D07 D06 DOS 004 D02 DOL DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 Wmsb WLsb BMsb BLsb 0 0 Trigger on Command 0 0 Illegal 0 1 Trigger on Status 0 1 Trigger on Primary 1 0 Trigger on Data 1
14. WESTERN AVIONICS DUAL STANAG 3838 3910 VME INTERFACE BOARD P N 1U10997G01 Rev A User Manual UM 10997 Rev B Western Avionics Ltd 13 14 Shannon Free Zone Co Clare Ireland 9 July 2002 1 GENERAL 3 6 14 INTRODUCTION 6 12 MANUAL DESCRIPTION niei reete e RESET KE SR TE a 6 1 3 SYSTEM CHARACTERISTICS AND seen 7 I 4 8 1 4 1 Generalaren E 8 1 4 2 Bus Controller BC Features With MRT Simulation and Data 8 1 4 3 Multiple Remote Terminal Features eese eene eene nennen 9 1 4 4 Chronological Bus Monitor CM Features 9 L5 VME 4220 ARCHITECTURE eet ettet nde cepe tete eb ert Ee e ERES 10 L6 BUSCOUPLING MA TRIX iiiter etre ERE ER REF AES ERE EH EE HAE RENE 11 17 PROTOCOL MANAGEMENT 11 1 8 ISOS INTERFACE t E 11 1 0 5 11 1 10 5 42 2525 lt brem eee ee
15. EH risen eerie pe debeo aen repel ERR d EGER 39 4 5 DATA BUFFERS SIMULATION AND MONITORING eee rennen enne enne 40 4 3 1 Look UP TADI e ire tell edu MEE 41 4 3 2 Data Descriptor Block et sarees adios 41 4 3 3 D ta n C 45 44 MODE COMMANDS iioi iee ereire e EER ER Ete re 46 45 JINTERRUPT REQUNESUS ii ete ie et eet reet ete i Tte e oti eee tue ste ele ir 47 4 5 1 Interrupt Codin RTT 47 4 5 2 Set Messade e dU es 47 4 5 3 Message Status Report Queue esses eene nennen eret eene 48 5 MULTIPLE REMOTE TERMINAL MODE OF OPERATION 49 5 1 INTRODUCTIO N eian ciet hie ert o Dr RUP wan pte go EO CO RERO I Dre ERR HEELS 49 52 AWOOK UP TABLES 2 03 En 50 53 MODE COMMANDS 5 2 50 54 DATA WORDS STORAGE iier e ER nat EA 50 55 LS ERROR INJECTION DEFINITION ene 50 5 5 1 Global RT Error Description Word RT Simulation Table sss 51 3 5 2 Message Error Injection Word Look up Table seen 52 5 6 INTERRUPTS CODING hen bed eene iae ert o de apre beige dd e rtc inu de de evra
16. Test and Set register TASR 3EH Service Request Queue Address Pointer SRQADSP 40H Cycling Interrupt Update Register 42H Monitor Current Address Register CAR 44H Monitor Trigger Occurrence Register TOR 46H Monitor Trigger Set up Pointer TSP 48H PRI Bus 3838 RT TX inhibit bits 4AH PRI Bus 3838 RT TX inhibit bits LO 4CH SEC Bus 3838 RT TX inhibit bits 4EH SEC Bus 3838 RT TX inhibit bits LO 50H PRI Bus 3910 RT TX inhibit bits 52H PRI Bus 3910 RT TX inhibit bits LO 54H SEC Bus 3910 RT TX inhibit bits 56H SEC Bus 3910 RT TX inhibit bits LO UM 10997 Rew B 21 3 4 2 Base Register Descriptions The Base Register functions are defined in the following paragraphs 3 4 21 Control Register Write 00H 12 CM FE D15 D14 BE BM Example UM 10997 Rev B D13 CE V2 RS FS CM BM Clear Clear Set Set Clear D10 FS D09 D08 007 D06 005 004 D03 002 DOI 0 RS 0 0 0 V2 VI 0 Request Insertion Request Release VMEI IRQ Release VME2 IRQ 3838 interface is held in RESET With the FE bit set this bit shall define the firmware selection for the interface FE FS 0 0 Nochange 0 1 Nochange 1 0 Standard firmware selected 1 1 Second enhanced custom firmware selected Note After selecting a new firmware the user mu
17. messages on a stack The size and position of this stack can be defined by the user NOTE When the Western Avionics 4220 is in this mode the BC MRT facility is not available address pointers for the Bus Monitor are 16 bit words defining a PAGE address Each page 15 32 bytes Example If a message pointer contains the value 2301H this indicates an absolute address of BASE 2301H x 20H BASE 46020H 6 2 BASE REGISTERS Table 6 1 Base Registers BASE REGISTER 00H Control Register Write Clock HI Word Read 02H Clock LO Word Read LSB of clock 0 5 uS 04H Command Register CR 06H Status Register SR 08H to 20H Reserved 22H Transformer Direct Coupling Select Register 24H to 2AH Reserved 2CH HS Subaddress Register 2EH Reserved 30H Reserved 32H Reserved 34H IRQ Selection Register 36H Reserved 38H Load Clock HI Register 3AH Load Clock LO Register 3CH Reserved 3EH Reserved 40H Reserved 42H Current Address Register CAR 44H Trigger Occurrence Register TOR 46H Trigger Set up Pointer TSP 10997 Rew B 56 6 2 1 Control Register Write 00H 05 04 D13 DI2 DIO D09 0081007 006 005 004 D02 DO 0 0 0 0 0 0 0 0 IRQ 0 0 0 CO Clear gt Command Request Clear gt Insertion Request HR Clear gt Hardware RESET If IEN is set and IRQ is set then
18. 004 D02 DOL DOO 0 0 0 0 0 0 0 0 0 0 0 The Monitor will wait LO HI transition on the TRIG IN input before storing messages and searching for the software trigger condition N 1 The Monitor will wait for a HI LO transition on the TRIG IN input before storing messages and searching for the software trigger condition T The Monitor will generate gt 1 5uS pulse the TRIG OUT when the software trigger condition has been detected 1 The Monitor will generate a gt 1 5uS pulse on the TRIG OUT when the post trigger message count has been reached 6 3 DETAILED TRIGGER DESCRIPTION The Bus Monitor has four triggers that can be set up to trigger on a wide variety of complex conditions Each trigger can be allocated one of four different data and error conditions Ifa trigger passes this condition it then moves on to the trigger defined by the Pass register If a trigger fails this condition it then moves on to the trigger defined by the Fail Register Each trigger is allocated a trigger type value from one to six and these are as follows Value 1 Value 2 Single Trigger Mode The Single Trigger Mode will search for the trigger data defined by the Trigger Data Pointer Register If this condition is TRUE for the incoming 3838 word the Single Trigger will branch to the trigger defined in the Pass Register If it fails it will branch to the trigger defined by the Fail Trigger Register Window Trigger The
19. 1 3838 TX on PRI bus 1 3838 TX on SEC bus 0 0 11 10 09 08 0 0 0 0 3838 MODE WITHOUT DATA 0 0 O0 1 3838 MODE WITH DATA 0 0 1 0 3838 RT RT 0 0 1 3838 0 1 0 0 3910 BC RT 0 1 O0 1 3910 RT BC 0 1 1 0 3910 RT RT 0 1 1 1 3910 TX MESSAGE MODE CODE 0 0 0 0 3838 MODE WITHOUT DATA BROADCAST 1 0 O0 3838 MODE WITH DATA BROADCAST 1 0 1 0 3838 RT RT BROADCAST 1 0 1 1 3838 BC RT BROADCAST 1 1 0 0 3910 BC RT BROADCAST 1 1 0 1 RECEIVE CLOCK BROADCAST 1 1 1 0 3910 RT RT BROADCAST 1 1 1 1 3910 MODE COMMAND BROADCAST 1 Extended Subaddress 1 Retry on EVENT 1 Interrupt on EVENT enabled 1 Interrupt on EVENT priority queue 0 LO priority 0 3910 Bus A 1 3910 Bus 0 0 0 If RETRY is enabled and IRQ on EVENT is disabled the RETRY will still take place Broadcast Receive Clock is a special message used for transmitting the 32 bit clock as data This message type only requires an MBD to define the command word and the inter message gap queue interrupt or buffer control is carried out The transmitted message will be the command word defined by the MDB followed by two data words Clock Value HI and Clock Value LO clock value at the end message on the bus The transmission of a Broadcast Synchronise with Data mode code using the 3838 mode with data broadcast message type will cause cycling interrupt to be generated if enabled and the associated data word defined in the da
20. 11 1 10 STORAGE DATA As the VME 4220 contains electrostatic sensitive devices ESD s special storage and handling 15 required Do not store near electrostatic electromagnetic magnetic or radiation fields 1 11 TOOLS AND TEST EQUIPMENT No special tools or test equipment is required to test the VME 4220 1 12 SAFETY PRECAUTIONS Operating personnel must observe safety regulations at all times refer to the Safety Summary at the front of this manual WARNING UM 10997 Rev 12 FRONT PANEL CONNECTORS AND INDICATORS Table 1 1 3838 Connector Pinouts Pri amp Sec A amp B PIN DESCRIPTION INNER 3838 POSATIVE OUTER 3838 NEGATIVE CASE GROUND SHEILD Table 1 2 9 Way Connector Pinouts J5 PIN DESCRIPTION 1 TRIGGER OUT Collector 2 TRIGGER OUT A Emitter 3 TRIGGER OUT B Collector 4 TRIGGER OUT B Emitter 5 TRIGGER IN A Anode 6 TRIGGER IN A Cathode 7 TRIGGER IN B Anode 8 TRIGGER IN B Cathode 9 IRIG B Input Figure 1 2 Front Panel connectors amp indicators diagram UM 10997 Rev B 13 Locations of linker blocks Z1 Z2 73 74 amp SW1 and SW2 Hexadecimal address switches SW1 and SW2 are located at top edge of the board as shown below LK1 LK2 LK3 LK4 and LKS 3 way headers used to configure the card for Electrical or Optical operation normally supplied factory configured Z 15 a 2 pin header provided to allow use on on card
21. 75 Ohm load terminator for the IRIG B supply which is applied when linker fitted Z2 and Z3 are 2 pin headers that require a linker to be fitted when performing a firmware up grade provided by means of self loading exe files 74 is a 2 pin header that when fitted with a linker connects the internal VMEFAIL signal to the SYSFAIL on the VME backplane and PP2 are 3 pin headers used for initial factory loading of on card device programming and must not be used by customers Figure 1 3 Location of Address Switches and Linkers diagram UM 10997 Rev B 14 2 INSTALLATION AND PREPARATION FOR USE 21 GENERAL On delivery inspect the unit for possible damage If it is damaged notify the shipping company and contact your distributor or Western Avionics for details of return procedure When unpacking remove all protective covering and store covering as unit may need to be reshipped at a later date CAUTION 2 0 INSTALLATION OF VME 4220 Prior to installing VME 4220 into the rack ensure that all power has been removed from the rack 23 TURN ON Set mains power on rack to ON The VME 4220 will perform system self test on the BC MRT and CM features of both Bus 1 and Bus 2 lasting approximately three seconds In the event of a failure of any part of the BIT on either Bus 1 or Bus 2 LED s will light on the front panel BIT 1 BIT 2 indicating the section that has failed 2 4 SELFTEST After applying power to th
22. PC 2 NOP3 0003H PC PC 3 BSR 0004H XXXXH XXXX 16 bit signed branch to subroutine BRA 0006H XXXXH XXXX 16 bit signed branch JMP 0007H XXXXH XXXX 16 bit absolute address for jump RTS 0008 Return from subroutine RTI 0009H Return from insertion routine ENI 000AH Enable program insertion DSI 000 Disable program insertion LOOP 000CH XXXXH Load loop counter with value XXXX DBNE 000DH XXXXH LOOP LOOP I branch signed offset XXXX INITF 000EH XXXXH Initialise frame duration to XXXX LSB 1005 SWPSE 000 Wait for new on board start of frame 0010H End of BC program SITL OOHH XXXXH Set low priority IRQ Push XXXX on LO queue SITH 0012H XXXXH Set high priority IRQ Push XXXX on queue HWPSE 0013H wait for external Trig LO HI for new frame SMB 0014 XXXXH Send message XXXXH absolute address of MDB TRGOUT 0015H XXXXH Trig out to the XXXXH level Instructions 1 2 3 By a the user can replace one two or three instruction words e BSR BRA DNBE e The offset is defined in bytes count always even offset BSR e 15 levels of subroutines available TRGOUT xxxx e Instructions to put TRIGOUT at 0 if xxxx 0000H or 1 if xxxx 0001H On power on the output is on 0 level per default e LOOP xxxx e Load loop counter with value XXXX Only one level of loop UM 10997 Rew B 26 e INITF xxxx XXXX Minor frame duration
23. Time for simulated RT in uS 101 Illegal Command XXXXXXXXXXXXX 0000000000000 TIT 110 Extended Subaddress XXXXXXXXXXXXX 0000000000000 111 gt Resync System Clock XXXXXXXXXXXXX 0000000000000 UMI 10997 Rev B 37 D03 0 D03 X Not applicable for BC Mode Not applicable for BC Mode Not applicable for BC Mode D02 DOI X D02 DOI X X X D00 X D00 X NOTES 1 Word Number For the first word of the message command or status WWWWWwW 000000 2 Synchro Pattern Error Defines a specific synchro bit each Si defines the level for 500ns duration at least 1 bit of S5 S0 must be set S5 54 53 52 51 50 right synchro bit example false synchro bit example S5 S0 011001 3 Manchester Bit Error 2 B4 BO defines the bit position in the word for the error 4 Word Length Error L4 L0 defines the number of bits in the word NOTE This count has an offset of 1 such that a value of 01111 will result on a valid word with a data bit count of 16 e Wrong bus error RT response on wrong bus Both busses error RT response on both busses e Response time error RRRRR replaces the global RT response time LSB 1 uS e Illegal command Reserved for MRT only 4 2 6 Address in Look Up Table OAH This will contain the address in the look up table for the DDB pointer See figure 4 1 4 20 7 Command Word 1 0CH First Command Word 4 2 8 Command Word
24. gt 9 gt UU gt wu gp gt gt w gt wo gt gt w Wu 4 3 24 Link Pointer to New DDB OCH If the message is good or bit 10 of the option mask is clear and bit 9 of the option mask is set the value in this location will replace the original DDB address in the look up table This feature defines a different DDB for the next occurrence of the same message 4 3 2 5 Address of Modify Word Value to Write QEH 10H After the message is complete and bit 8 of the option mask is set the Value to Write is written in the address defined by the contents of OEH Action is limited to the first 64Kbytes of the memory 4 3 2 6 3910 Frame Timeout and RI TI Time Register 18H BIT 15 to 13 Set to 0 BIT 12 If this bit is set the HS data stream will have a ve word count error BIT 11 If this bit is set the HS data stream will have a ve word count error BIT 10 If this bit is set the HS data stream will not be transmitted HS no response BIT 09 to 08 Set to 0 BIT 07 to 00 TI time for 3910 TX gt time for 3910 data to start from end of BC action word LSB luS RI time for 3910 RX gt time for RX timeout after end of BC action word LSB lus UMI 10997 Rev B 43 4 3 2 7 3910 Errors Injection 1 1AH This word defines the desired start and end delimiter patterns for transmissions as follows 05 014 D12 DII DIO D09 D07 D06 005 004 002 ED7 ED
25. interrupt line will be cleared If IEN is set and IRQ is clear then the interrupt line will be asserted for test purposes only If IEN is clear the value of IRQ is unaffected Note This register must be accessed to clear the interrupt during an interrupt service routine Examples 1 0102H generates a command request 2 0163H clears the interrupt line 6 2 2 Command Register CR Prior to clearing the Command Request bit CO in the Control Register the user must first test that the CR is clear When the CR is clear the user can insert the next command to be executed Refer to table 6 2 Table 6 2 Command Registers CODE COMMAND 0000H Illegal 0001H GO TO BCT MODE 0002H GO TO MRT MODE 0003H GO TO MON MODE 0004H Reserved 0005H Reserved 0006H Reserved 0007H Reserved 0008H Reserved 0009H Reserved 000AH Reserved 000BH Reserved 000CH LOAD CLOCK 000DH SELFTEST 000EH RUN MONITOR 000FH STOP MONITOR 0010H SYNCHRONISE CLOCK After the command is loaded bit CO in the Command register can be cleared When the CR clears the board is ready for a new command UM 10997 Rev B 57 6 2 3 Status Register SR This register contains a code reflecting the status of the board as shown in table 6 3 Table 6 3 Status Registers CODE COMMAND 0001H Reserved 0002H Reserved 0003H MONITOR IDLE 0004H Reserved 0005H Reserved 0006H Reserved 0007H MONITOR
26. message or after a set of different messages and priority of interrupt three different available one interrupt only per message The data word count contains the data word count expected by the user The Western Avionics 4220 processor compares this word count with real data word count transmitted on the bus and writes the difference if any in the data status report word This last word also contains the status flag of the transmission message received correct or with error message running The most significant byte of data buffer address can be used to enable toggled buffer control toggle on beginning of each minor frame or on multiple cycles of this minor frame This allows user software synchronised on the frame cycle to always access the correct buffer set of message interrupt features provides the possibility to send an interrupt after the last message of the set of messages It is to be used when the frame sequence 1s not purely repetitive Up to 128 different sets of messages from 2 to 16 messages each can be defined Refer to table 4 2 A HS type data descriptor block also defines HS transmission characteristics HS frame time out LSB 100 nS RI or TI values LSB 115 HS error injection no response preamble bit count error word count error FCS error encoding error Bit count error start end delimiter pattern error Error injection on LS data words is defined in the message descriptor blocks
27. messages option When setting an IRQ the Western Avionics 4220 board pushes a vector code into queues each code defines the event origin of the IRQ Each queue must start at an address multiple of 200H user must manage the reading pointer and erase with a 0000H value the codes after reading 4 5 1 Interrupt Coding 1 LO and HI priority interrupts two words Messages without error 0800H DDB Address Messages with error 0C00H DDB Address BC Event without RETRY 1000H Status Queue Address BC Event with RETRY 4000H Status Queue Address Send Interrupt SITL SITH 2000 SITL SITH Vector 2 Message Interrupts one word Message Interrupt Code from DDB Only if Message is Good 4 5 2 Set Message Interrupts When in a DDB bit 12 of the option mask word is set The 10th word gives a set of message numbers 00H to FFH e The 12th word gives a message indicator e For each set the on board processor manages a set word register It makes OR with message indicator in set word register Then if the set word register is equal to FFFFH on board processor sends a message interrupt code defined in the 9th word of the DDB and resets the set word register It is possible to define sets from 2 to 16 messages The user initialises at 0 set of messages table The 256 word set of messages table is pointed to by the set of Messages Start Address 26H in Base registers UM 10997
28. of the 1 word is set the card is not locked with the incoming IRIG B signal To Load the clock with a new value 1 Wirite the new value in the module base registers Load Clock HGH LOW 1 word LL CC DDDDDDDD HHHH 219 word HH SSSSSSS LL Leap year 0 3 CC Days x 100 0 3 DDDDDDDD Days 0 66 in BCD HHHHHH Hours 0 23 in BCD MMMMMMM Minutes 0 59 in BCD SSSSSSS Seconds 0 59 in BCD To allow decoding of IRIG B the clock always adds 1 second to the programmed value Therefore the above time must be set to the desired time minus 1 second Leap year value should be 00 Leap year 01 1 year after leap year etc 2 Write the Load Clock command code into the command register 3 Now execute generate a command request write 0x0302 in control register If the 1 word is set to LL11111111111111 the free running clock will not be loaded The LL bits will be used to define the leap year and the clock will be forced into external sync mode If the 1 word is not set to LL11111111111111 the free running clock will be loaded and the clock will be forced into free running mode 3 4 2 3 Command Register CR 04H Prior to clearing the command request bit CO in the control register the user must first test that the command register is clear When the command register is clear the user can insert the next command to be executed After the command 15 loaded bit CO 1n the control register can be cleared Whe
29. page address of the next message This value will be set to FFFFH for the last message after the post trigger count has expired and capturing has stopped 6 4 5 Response Time 1 2 These two locations will define the RT response times if any of the Status words in the message The second Response time is only applicable for 3838 RT RT transfers 10997 Rew 71 6 5 3910 DATA FORMAT If a 3838 message results in the transfer of 3910 data this message will be stored at the first new page after the 3838 message The NEXT ADDRESS value in the 3838 data will account for this and point to the first page after the expected 3910 data The first word in the 3910 data will describe the validity of the message as follows 015 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 001 0 0 0 0 0 0 0 0 5 W F 0 E R B If set this indicates that the 3910 message is ready to be interrogated W If set this indicates that the 3910 message had wordcount error If W is set then this shall indicate if the error was ve or ve 1 ve If set this indicates that the 3910 message had a FCS error If set this indicates that the 3910 message had a Manchester encoding error If set this indicates that the 3910 message had a RI timeout no HS response If set t
30. the previous DATA word TYPE BUS ID and associated errors as follows D15 D14 D13 D12 D11 D10 D09 007 D06 DOS D04 D02 DO1 DOO ED HS OV Py 15 Sh TO WC Bl BO NR TA Sy 0 ED 1 Indicates last 3838 word in message HS 1 Indicates message has associated 3910 data Only set for last word OV 3910 DATA overlap Decoder still active for previous 3910 message Py 3838 data word had a Parity error Mn 3838 data word had a Manchester error Lg 3838 data word had too many bits Long Sh 1 3838 data word had too few bits Short UM 10997 Rew B 70 T1 TO describe the 3838 word type as follows T1 TO WORD TYPE 0 0 Command Word 0 1 Status Word 1 0 Data Word 1 1 RT RT Command Word Indicates 3838 message had a word count error Only set for last word Bl Describe the bus the 3838 word was captured on as follows B1 B0 BUS ID 0 0 Illegal 0 1 Secondary 1 0 Primary 1 1 Both Buses 1 Indicates that a RT failed to respond to command No Response Only set for last word 1 Indicates that the RT status word did not match the address of the command word Terminal Address Error Sy 1 Indicates that the 3838 word did not have the correct SYNC type 6 4 4 Next Address Pointer This word will define the
31. 0 Trigger on Secondary 1 1 Trigger RT RT Transfer 1 1 Trigger on Both Buses Trigger Data 4 Error Word Mask Register Base Address 5 This register will define if the Error Word Register is to be included in the trigger condition D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 DOS 004 D02 DOL DOO 0 0 D 0 0 0 0 0 0 0 0 0 0 0 0 0 D 1 Error condition disabled UMI 10997 Rew B 66 Trigger Data 4 Error Word Register This register will define the Errors required in the trigger condition Base Address SEH If more than one error is set the trigger condition will be a logical OR of the errors D15 D14 D13 D12 D11 D10 D08 D07 D06 DOS 004 D02 D01 DOO 0 0 0 Py Lg Sh 0 0 WC 0 0 NR 5 0 Sy 1 Sync Type Error Sh 1 Short Word Error TA 1 Terminal Address Error Lg 1 Long Word Error NR No Response Error Mn 1 Manchester Error WC 1 Wordcount Error Py Parity Error Trigger Start Register Base Address 60H This register defines the first trigger to be used in the trigger sequence This will be in the range to 5 Examples The first trigger used in the sequence is defined by the contents of the Trigger Start Register For these examples assume that the Trigger Start Register points to Trigger 1 value 1 Key TTR Trigger Type Register Trigger Data Point
32. 00000RRRRR RRRR NOTE 10997 Rev B Unique Response Time for simulated RT in uS See NOTE 4 in paragraph 5 5 2 Global error injection is enabled disabled by the LSB bit of the simulation type word 51 001 5 5 2 Message Error Injection Word Look up Table The following word defines the errors that can be injected into the message D15 014 D12 009 D07 D06 005 004 D02 DO T T T X X X X X X X X X 0 X X X 000 gt Modulation Error XXXXXXXXXXXXX WWWWWWYYYYYYY WWWWWW Word Number For Modulation Error 0 status word 1 1 data word Y Y Y Y Y Y Y ERROR TYPE 0 0 0 0 0 00 Parity error 0 55 54 53 52 SI SO Synchro Pattern Error 1 0 B4 B3 B2 BO Manchester Bit Error 1 1 L4 L3 LI LO Word Length Error TTT 001 gt Wrong Bus Error XXXXXXXXXXXXX 0000000000000 010 gt Both Bus Error XXXXXXXXXXXXX 0000000000000 011 gt Word Count Error XXXXXXXXXXXXX 000000PCCCCCC P Word Count Error Polarity 0 Word Count Error VE 1 Word Count Error VE CCCCCC Word Count Error Value Allows 64 Words 100 gt Response Time Error XXXXXXXXXXXXX 00000000RRRRR RRRR Unique Response Time for simulated RT in uS See NOTE 4 in paragraph 5 5 2 101 Illegal Command XXXXXXXXXXXXX 0000000000000 TTT 110 gt Extended Subaddress XXXXXXXXXXXXX 0000000000000 11
33. 1 gt Resync System Clock XXXXXXXXXXXXX 0000000000000 UM 10997 Rev B 52 NOTES 1 UM 10997 Rev No error TTT 000 WWWWWW 111111 LS errors injection on HS action words commands The VXI 2800 module can inject errors on the LS status words in response to an action word receive command when simulating the RT The error injection is defined in the look up table in the word pointed by the HS sub address so it is common for the HS message identifiers In the HS look up table For an HS message identifier the error description word can take only two values Word 0000H for normal Word 0000 to illegalize the corresponding HS message identifier Illegalization is managed corresponding to the STANAG 3910 by the setting of the HS message frame error bit in the HS status word If a HS TX message is illegalized the RT will not transmit the HD data Error injections on the HS lines are defined in the DDB TX mode codes and all HS messages have fixed response times and will not be affected by the global or look up table response time error option other messages have a minimum response time of 8 15 The individual response time facility in the error injection word is a value that is added to the minimum response time Therefore a unique response time value of three in the error word will result in of response time of 11 45 53 5 6 INTERRUPTS CODING 5 6 Low and High Priority Interrupts two word code
34. 1 and for Bus 2 UM 10997 Rev B 16 2 6 WME INTERFACE 2 6 1 Introduction The 4220 board is used as a 16Mbyte field R W DRAM 16Mbyte Read only 32 bit counter or IRIG B format clock Write only 16 bit register one 16 bit access The Control Register and the counter are mapped into the memory field Two hex switches on the board define the starting address of the board as shown below The VME interface includes a VME slave and two VME interrupters Figure 2 1 VME Switches SWI Sw2 31 28 27 24 A32 only access for memory register counters Address only transfers without loss of data 032 016 D08 for memory access D16 for register access Block Transfers into memory 32 bit 16 bit 8 bit access Read Modify Write into memory 32 bit 16 bit 8 bit access Aligned transfer only VME interrupts High and Low Interrupts 2 6 2 Details Programmable level 1 7 Programmable daisy chains enable and disable Programmable 8 bit Status ID vector D08 0 Accept 32 bit 16 bit 8 bit interrupt handler size Programmable interrupt release ROAK Release interrupt during interrupt acknowledge cycle or during register access RORA Release interrupt during register access only Interrupters can interrupt in the same level Access rate average 5Mbyte s Address Modifiers To access the memory the counter the register A32 single access an
35. 2 0EH Second Command Word RT RT 3838 4 2 9 Action Word 1 10H First Action Word to be transmitted 3910 message 4 2 10 Action Word 2 12H Second Action Word to be transmitted RT RT 3910 4 2 11 Retry Subroutine Absolute Address 14H On completion of a message if an Event defined by the Mask has occurred and the Retry Event is enabled the Subroutine defined by this absolute address will be called NOTES 1 The retry subroutine must be terminated by the RTS instruction to return execution back to the main background or insertion program 2 This feature can be used for immediate insertion of Acyclic messages or retry of the same message on the alternate bus 10997 Rev B 38 3 HS Event Mask 16H BIT15t007 0 BIT 06 HS Data Overlap Error BIT 05 3910 Word Count Error BIT 04 FCS Error BIT 03 Invalid No End Delimiter BIT 02 Invalid NO Start Delimiter BIT 01 3910 No Response BIT 00 3910 Frame Word Timeout NOTE HS Data Overlap error bit Indicates that the HS data words of the previous message have been overlapped by the HS data words of the new image Data Message 1 Data Message 2 Overlap lt gt 3910 4 2 12 Inter message Gap Time 18H e Gap between the end of this message and the LS line and the beginning of the next one next MDB e LSB 0 1 uS For 3910 message this inter message gap time must take account of the HS message 4 2 13 HS RT RT Inter message Gap Time
36. 21 Set of Messages Start Address 26H This is the pointer of a 256 word table reserved to the on board processor to compute the registers Set of Messages For further details refer to paragraph 4 5 2 3 4 2 22 Global RT Response Time Register 28H This is the response time for all the simulated RT s Different RT response time be defined the error description words LSB lus For some modes this global RT response time register is not programmable fixed at 405 e 3838Mode without data If the value is less than 4 on board processor selects 415 3 4 2 23 RT No Response Time Out Register 2AH RT Response Time programmable RT no response time out defines the maximum response time allowed by the board to an RT before detecting NO RESPONSE LSB lus 3 4 2 24 HS Sub Address 2CH Indication for the on board processor of the sub address value used to define HS messages Set to 0x001A for EFA Set to 0x0001 for RAFALE Set to OXFFFF for 3838 operation only UM 10997 Rev B 29 3 4 2 25 IRQ Selection Register 34H D15 014 012 D11 D10 D09 008 007 D06 D05 004 D03 D02 DOI
37. D 1 Error condition disabled 10997 Rew B 64 Trigger Data 2 Error Word Register This register will define the Errors required in the trigger condition If more than one error is set the trigger condition will be a logical OR of the errors Base Address 46H D15 D14 D13 D12 D11 D10 D08 D07 D06 DOS 004 D02 DOL DOO 0 0 0 Py Sh 0 0 WC 0 0 NR 5 0 5 1 Sync Type Error Sh 1 Short Word Error TA 1 Terminal Address Error Lg 1 Long Word Error NR 1 No Response Error Mn 1 Manchester Error WC 1 Wordcount Error Py Parity Error Trigger Data 3 Trigger Data 3 Bit Mask Register Base Address 48H This register will define the bits to be ignored in the trigger bit pattern for trigger data 3 Any bit set in this register will be masked from the trigger test condition Trigger Data 3 Bit Pattern Register This register will define the bit pattern required for trigger data 3 Trigger Data 3 Bus ID Word Type Mask Base Address 4AH Base Address 4CH This register will define the Bus ID and Word Type bits to be ignored in the Bus ID Word Type Register D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 DOS 004 D02 DOL DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 Both W bits 1 Ignore Word in trigger condition Bo
38. DDDDDDD HHHHH C Days x 100 D Days Hours 254 word 0000 MMMMMM SSSSSS M Minutes S Seconds 3 word 000000 MMMMMMMMMM M Milliseconds 4 word 00000 UUUUUUUUUUU U 0 508 ticks If the MSB of the 1 word is set the card is not locked with the incoming IRIG B signal Note The remainder of this document refers to all clock and time tag information as standard 32 bit This clock mode results in 2 x 16bit words being stored in the data buffers If the firmware module is IRIG B then all time tags will be stored as 4 x 16bit words 2 5 3 Trigger In Features Trigger In enters the board logic through the 15 way front panel connector and then an opto coupler So if the diode 18 powered there is a zero logic level and if the diode 1s not powered there is a high logic level So a rising edge on this logic level can be used for hardware starts of the frame hardware starts of the minor cycle or external trigger for the bus monitor One Trigger in is provided for Bus 1 and for Bus 2 2 5 4 Trigger Out Features Trigger Out is in fact a bit in a register accessible by the on board processor to indicate to the external world that an event has been detected This event can be as follows Beginning of the minor cycle Beginning of a message e Bus Monitor trigger detected Trigger Out exits the board through an opto coupler and the 15 way front panel connector see Figure 1 2 for details One Trigger out is provided for Bus
39. E interface VME Interface Slave A32 D32 D16 D8 Block Transfers 95 Confidence Level 440 grams gt 1 Ib 5Vdc 1 45 A max 12Vdc 250mA max 12Vdc 50mA max Operating 0 C to 50 C Non operating 20 C to 70 C 0 C to 29 C 95 30 C to 40 C 75 RH Tri axial type CBBJR79 Front Panel 3910 Electrical Connectors Co axial type CBBJR29 Front Panel 3910 Optical Connectors Deutsch 454596 N e Front Panel I O Connector LED Indicators UM 10997 Rev B 9 way micro miniature to MIL C 83513 02 AN Power on indicator Green Pwr VME activity Yellow Act BIT Bus A Fail Red Fail BIT Bus B Fail Red Fail BUS A Activity Yellow Busy BUS B Activity Yellow Busy IRIG B Lock Bus A Yellow Lock IRIG B Lock Bus B Yellow Lock 14 CAPABILITIES VME 4220 is capable of the following functions 1 4 1 General Memory mapped real time VME access Simultaneous control of up to two STANAG 3838 dual redundant buses Full STANAG 3910 control one bus in or mode with simultaneous STANAG 3910 bus monitoring on second bus HS transceivers interface for either fibre optic or electrical transceivers 8MByte of RAM per 3838 3910 bus Two Vectored Interrupts per 3838 3910 bus 3838 data protocol managed by a micro controller providing flexibility and extensibility Full Error Injection capability External Triggers Internal Self tests Standard single sl
40. Look up Table giving a descriptor for each 3838 mode code NOTE The T R bit of the Command word or Action word is used as an offset to point to the RX or TX block of the look up tables Each descriptor includes Message Error Description or Illegalization word e A Data Descriptor Block Address or Extended sub address look up table address as for BC mode 53 MODE COMMANDS SPECIFICATIONS illegal mode codes defined in the 3838 standard are automatically illegalized The error descriptor word allows illegalization of complementary mode codes Associated data words which are not obtained from the RT Simulation Tables can be obtained from or stored in memory using Data Descriptor Blocks For each mode code DDB can be used to define IRQ s HS mode commands are processed in accordance with STANAG 3910 The message identifier points 00 T R O and 80H T R 1 in the HS look up table define two illegalization and DDB address word pairs for all HS mode commands This allows one of the mode types T R 0 or T R 1 to be illegalized if required The DDB allows the definition of common interrupt requests for all the HS mode commands 5 4 DATA WORDS STORAGE To avoid data buffers overwriting in memory when receiving a data message the 4220 board does not store more data words than the number defined by e Data Word Count if no header option or Data Word Count Header Word Count if header option Data Word Count for HS m
41. Message Descriptor 0 4 35 Table 4 2 Data Descriptor 41 Table 4 3 Data 46 Table 6 1 Base Register srS 56 Table 6 2 Command 002400 000 0000 57 Table 6 3 Status 1 58 Table 6 4 Stack GI PICBQOVU C 70 Trable 6 5 Stack iere eoe ettet e vp o soccsetsescvsssssacvsstenssbeseeen sesatcodeussecesoccassonssoscesscosussensvsscesesany 72 UM 10997 Rev 5 1 GENERAL INFORMATION 11 INTRODUCTION The VME 4220 Intelligent Interface Board is a VME card designed to meet the requirements of both STANAG 3838 and STANAG 3910 The VME 4220 is a standard 6U size VME card allowing up to two independent 3838 3910 modules to be used in a variety of combinations to provide up to two Bus Controller Multi Remote Terminal with Monitoring functions or one Bus Controller Multi Remote Terminal and Chronological Bus Monitors on a single VME card The VME 4220 provides a powerful and intelligent interface between VME based host equipment and the STANAG 3838 STANAG 3910 data buses providing comprehensive test and simulation functi
42. On data messages without error On data messages with error On mode commands without error On mode commands with error On HS mode commands without error On HS mode commands with error 5 6 2 Message Interrupts or set of messages interrupt 0800H DDB address 0C00H DDB address 0900H DDB address 0000 DDB address Action word OEXXH Action word XX RT number One word code equals message interrupt code in data descriptor block The code is pushed in queue only if the message is correct 5 6 3 Status Report Queue two words per report Sets of Messages Same feature as for BC mode Code pushed into queue only if error on message and Interrupt on erroneous message not set in the DDB Ist Word Pointer to the double word in look up table look up table address index 2nd Word Events BIT 15 Wrong Both Buses Error IT14 No Response Error IT13 RT Address Error IT12 TX Error Mn Lg Sh Py WC Late Response BIT 11 SYNC Type Error BIT 10 to Not Used BIT 06 HS wordcount error polarity 1 Too many words 05 HS Word Count Error BIT 04 HS FCS Error BIT 03 HS preamble bit count error BIT 02 HS manchester encoding error BIT 01 HS RI timeout BIT 00 HS bit count error The bits 15 to 11 are used for e Status Word and data if it s an LS message e Status Word if it s a transmitted HS message NOTE report is pushed in the queue 1st Word 2nd Word LS error code on bi
43. P4 0005H TFP4 0003H LTSR 0006H UM 10997 Rev 68 5 Find the message with word defined by Trigger Data followed by the Nth word within that message which does not meet the conditions of Trigger Data 2 TTRI 0001H TDP 0001H TPP 0002H 0001H PTTR2 0002H TDP2 0002H TPP2 0001H TFP2 0004H NN 0006H UM 10997 Rev 69 64 STACK DATA FORMAT When the Bus Monitor is commanded to start all messages will be stored before the trigger condition is met Therefore all pre trigger data is captured The first captured message will start at the address defined by the Start Page Register following messages will start on an even PAGE boundary The STACK data will wraparound after the Finish Page Register value has been exceeded format of the messages are shown in table 6 4 Table 6 4 Stack Data Format WORD No NAME 1 Previous Address Pointer 2 Time Stamp HI 3 Time Stamp LO 4 Data 5 Errors N 4 Data N 3 Errors N 2 RT Response Time LSB 0 5 uS N 1 RT Response Time 2 LSB 0 5 uS N Next Address Pointer 6 4 1 Previous Address Pointer The first word of each message will define the page address of the previous message The first message stored will set this pointer to 0000H 6 4 Time Stamp HI LO These two locations are a 32 bit word defining the value of the 32 bit 0 5uS clock when the message started 6 43 Data These words describe
44. RUNNING 0008H Reserved The Status Register will contain the following information after completion of selftest D15 D14 D13 D12 D11 D10 D09 D08 D07 DOS 004 DO2 DOI DOO I 0 0 LS 0 0 LC 5 4 M3 M2 MI 11 0 0 0 LS 1 3838 Interface Test Failed FR 1 Frame Counter Test Failed LC 1 Local Clock Test Failed 5 1 Memory Test 5 Failed M4 1 Memory Test 4 Failed M3 1 Memory Test 3 Failed M2 1 Memory Test 2 Failed 1 Memory Test 1 Failed If no selftest errors are detected the Status Register will be 8008H 6 2 4 Transformer Direct Coupling Select Register If the LSB of this register is set to 17 the module will be configured for 3838 transformer coupling If the LSB of this register is set to 0 the module will be configured for 3838 direct coupling 6 2 5 HS Subaddress Register The least significant five bits of this register will define the RT Subaddress used by the system for HS transfers 6 2 6 IRQ Selection Register 34H DIS Dl4 Di2 D11 DIO D07 005 D04 D03 D02 0 0 0 0 Trigger Post Trigger Full Stack Half Stack 0 0 T 0 0 P 0 0 F 0 0 H T Ifset a physical INTA interrupt will be generated when the trigger condition is met P Ifset a physical INTA interrupt will be generated when all the post trigger data is captured F Ifset a physical INTA inte
45. Rev B 47 4 5 3 Message Status Report Queue At the end of a message if an event is detected and matches with the 3838 3910 Event Masks of the MDB a Message Status Report is pushed in to the Message Status Report queue 2 words per report l 3838 Messages Message Number MSB 0 EVENTS with EVENTS BIT 15 5 Wrong Both Buses Error BIT 14 NO RESPONSE Error BIT 13 RT ADDRESS Error BIT 12 TX Error Mn LG SH Py WC Late Response BIT 11 SYNC Type Error Bit 09 3 0 Ist Status 1 2nd Status 10 BITS 08 000 RX Status Bits 2 3910 Messages Message Number MSB 1 EVENTS with EVENTS BIT 15 to 08 0 07 HS Data Overlap Error BIT 06 HS wordcount error polarity 1 Too many words BIT 05 HS Word Count Error BIT 04 HS FCS Error BIT 03 HS preamble count error BIT 02 HS Manchester encoding error BIT 01 HS RI timeout BIT 00 HS Bit count error UMI 10997 Rev B 48 5 MULTIPLE REMOTE TERMINAL MODE OF OPERATION 51 INTRODUCTION In Multiple Remote Terminal mode the Western Avionics 4220 board can simulate up to 31 RTs After initialisation by the host the board is ready to listen to the bus activity and to respond to command words for the simulated RTs The description of the mode of operation uses tables similar to those defining the bus controller mode providing the same associated features multiple data buffering signalisation etc Refer to figure 5 1 the M
46. S EDA ED3 ED2 EDI 0 507 506 505 8 4 503 8 2 SDI SDO 507 0 defines the start delimiter pattern Each bit is 5015 segment of the start delimiter starting with 507 and ending with SDO ED7 0 defines the end delimiter pattern Each bit is a 50nS segment of the end delimiter starting with ED7 and ending with EDO LJ Lo do LO 10001 110 01 11 000 SD ED As can be seen above for a good start and end delimiter this register should be set to 1000111001110001 OxSE71 Any other value will inject start end delimiter pattern errors 4 3 2 8 3910 Errors Injection 2 1CH This word defines further error injection features as follows D15 014 D12 DII DIO D09 007 D06 005 004 002 0 0 PRS PR2 PRI PRO 2 FCS ML MM PRS 0 The value of this defines the number of preamble bits to transmit 1 63 BT3 0 The value if this defines the bit count error for the HS data stream Values 0001 1111 define the number of bits to remove from the data stream Hence 1111 will result in the data stream being short by 15 bits For no bit error this value should be set to 0000 FCS Ifthis bit is set an FCS error will be injected into the data stream the FCS word will be incorrect ML If a Manchester encoding error is required in the data stream this bit will define the level for the bit ME If this bit is set a Manchester error will be injected into the data stream of le
47. TWARE PAUSE SWPSE 004 EXECUTING HARDWARE PAUSE HWPSE 0006H MRT RUNNING 8006H MRT PAUSED 0007H MON RUNNING 0008H MON RUNNING XXX8H EXECUTING SELFTEST FINISHED SELFTEST The status register will contain the following information after completion of self test D15 D14 D13 D12 DII DIO D08 D07 DOS 004 D02 1 0 0 LS HS 0 LC 5 4 M3 2 I I 0 0 0 18 1 3838 Interface Test Failed HS 1 3910 Interface Test Failed 1 Local Clock Test Failed M5 1 Memory Test 5 Failed M4 1 Memory Test 4 Failed M3 1 Memory Test 3 Failed 2 1 Memory Test 2 Failed MI 1 Memory Test 1 Failed Several bits can be set simultaneously If no self test errors are detected the code in the status register will be 8008H UMI 10997 Rev B 25 3 4 2 6 Background Running Pointer BRP 08H In the BC mode the Background Running Pointer BRP directs the firmware to the location of a background program which can be used to organise the message sequencing Before sending a BC start the user must initialise the BRP BRP is updated by the on board processor after executing a BC STOP command Table 3 4 is a list of the possible instructions with descriptions and examples Table 3 4 Instruction Set Background Program DELAY 0000H XXXXH XXXX Delay LSB of 10 5 NOPI 000 PC PCH NOP2 0002H PC
48. Window Trigger Mode will search for the trigger data defined by the Trigger Data Pointer Register within the first 3838 message it encounters If this condition is TRUE for a word within the incoming message the Window Trigger will branch to the trigger defined in the Pass Register If the value of the Window Word Count Register is non zero the Window Trigger will use this value to specify the word number within the message for the Trigger test to be carried out If this value is zero all words within the message will be tested Window Trigger would normally be preceded by a Single Trigger The Single Trigger would define the specific 3838 command word then pass to the Window Trigger to define a specific bit pattern of a particular word within this message If the Window Trigger Fail Register points back to the Single Trigger requirements then the monitor will start again with the next 3838 message 10997 Rev B 60 Value 3 Value 4 Value 5 Value 6 NOTES Trigger 3910 Message Trigger Mode The 3910 Message Trigger will act the same as the Window Trigger with the following exceptions a There is no associated word count register This trigger should only be used for 3838 messages that will initiate a 3910 data transfer b If the specified 3838 word within the message is found this trigger does not automatically pass to the next trigger The resulting 3910 message is interrogated and compared with the 3910 Trigger Err
49. age descriptor block as shown in table 4 1 Table 4 1 Message Descriptor Block MBD ADDRESS MESSAGE NUMBER 02H LS Event Mask 04H Message Type Word 06H LS Message Error Phase Definition 08H LS Message Error Description Word 0AH Address in Look up Table 0CH Command Word 1 0EH Command Word 2 10H Action Word 1 12H Action Word 2 14H Retry Subroutine Absolute Address 16H HS event Mask HS Overlap 18H Inter message Gap Time 1AH HS RT RT Inter message Gap Time 1CH Status Word received 1EH Status Word 2 for RT RT received 4 2 1 Message Number 00H The number of the message is used in Message Status Report to identify messages 4 2 2 15 Event Mask 02H A logical AND is carried out with the LS event mask and the detected bus events If the result is lt gt 0 a message status report will occur and a retry if selected BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 Bit 10 to 00 NOTE UM 10887 Rew B Wrong Both bus error No response error RT address error Transmission error Wrong sync error Status bits of RX status word not including address bits Transmission error includes Manchester error Long or Short word error Parity error Word Count error and Late Response error 35 4 2 3 Message Type Word 04H BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 to 8 BIT 07 BIT 06 BIT 05 BIT 04 BIT 03 BIT 02 BIT 01 BIT 00 NOTES 1 UM 10887 Rew B
50. b WLsb BMsb BLsb 0 0 Trigger on Command 0 0 Illegal 0 1 Trigger on Status 0 1 Trigger on Primary 1 0 Trigger Data 1 0 Trigger on Secondary 1 1 Trigger RT RT Transfer 1 1 Trigger on Both Buses Trigger Data 1 Error Word Mask Register Base Address 38H This register will define if the Error Word Register is to be included in the trigger condition D15 D14 D13 D12 D11 D10 D09 007 006 DOS D04 D02 DO1 DOO 0 0 D 0 0 0 0 0 0 0 0 0 0 0 0 0 D 1 Error condition disabled UMI 10997 Rew B 63 Trigger Data 1 Error Word Register This register will define the Errors required in the trigger condition If more than one error is set the trigger condition will be a logical OR of the errors Base Address D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 DOS D04 D02 DOL DOO 0 0 0 Sh 0 0 WC 0 0 NR TA 5 10 Sy 1 Sync Type Error Sh 1 Short Word Error TA 1 Terminal Address Error Lg 1 Long Word Error NR 1 No Response Error Mn 1 Manchester Error WC 1 Wordcount Error Py Parity Error Trigger Data 2 Trigger Data 2 Bit Mask Register Base Address 3CH This register will define the bits to be ignored in the trigger bit pattern for trigger data 2 Any bit set in this register will be masked from the trigger te
51. ck and then stops activity If the PTC is set to H8000 storage will continue until the board is commanded to halt This trigger mode always resides in the Trigger Stop Register and never other register This is trigger 5 and must always be pointed at as the last part of the trigger sequence 1 Trigger 1 type Register Base Address 0 This register will define the trigger type allocated to trigger 1 This value will be in the range 1 to 6 Trigger 1 Data Pointer Base Address 10 This register will define the trigger data allocated to trigger 1 This value will be the range 1 to 4 Trigger 1 Pass Pointer Base Address 12H This register will define the new trigger to be activated if this trigger condition passes This value will be the range 1 to 5 Trigger 1 Fail Pointer Base Address 14H This register will define the new trigger to be activated if this trigger condition fails This value will be the range 1 to 5 10997 Rev 61 Trigger 2 Trigger 2 Type Register Base Address 16H This register will define the trigger type allocated to trigger 2 This value will be the range 1 to 6 Trigger 2 Data Pointer Base Address 1 8H This register will define the trigger data allocated to trigger 2 This value will be the range 1 to 4 Trigger 2 Pass Pointer Base Address This register will define the new trigger to be activated if this trigger condition passes T
52. command mode code is correctly simulated 3 5 4 LS Bit Word For user purposes 3 5 5 HS Status Word Automatically updated for frame error RX ready busy TX ready busy bits including broadcast So the 3910 TX command is correctly simulated This word in the simulation table is used by the on board processor as a flag to record FRAME errors However the user can force a HS Status word with the FRAME bit set by writing a non zero value into this location 3 5 6 HS Last Action Automatically updated including broadcast So the 3910 TX command is correctly simulated 3 57 HS Bit Word For user purposes NOTES 1 3838 Mode Commands TX shutdown and override TX shutdown fully simulated The status of the transmitters are available to the user in the Base Registers 2 3910 Mode Commands TX shutdown and override TX shutdown are fully simulated The status of the transmitters are available to the user in the Base Registers 3 The user can modify the RTs simulation state in real time UM 10997 Rev B 33 4 BUS CONTROLLER MODE OPERATION 41 INTRODUCTION In the Bus Controller mode the Western Avionics 4220 board runs a list of instruction pointed to by the Background Running Pointer defining the bus frame Each bus message is defined by a Message Descriptor Block MDD and the associated data is accessed through a Look Up Table LUT and Data Descriptor Blocks DDB the same way as in the Multi Remote mode Remote Te
53. d read modify write A32 block transfers 2 6 3 Electrical Characteristics 5V and 12V driving and loading rules are respected 10997 Rev B 17 09h OAh 0Dh OEh OBh OFh 2 64 Capabilities Each VME 4220 3838 3910 interface is addressed as a 8Mbyte field R W DRAM 8Mbyte Read only counter clock Write only 16 bit register 16 bit access 27 3838 INTERFACE 2 7 1 Introduction The interface matches the MIL STD 3838 Standard 2 1 2 Electrical Characteristics Each 3838 interface provides one dual redundant bus e Primary bus e Secondary bus Each 3838 interface can be e Transformer coupled Direct coupled Amplitude controlled 10997 Rev B 18 3 VME 4220 OPERATION 31 INTRODUCTION The VME 4220 provides Bus Controller BC Multi Remote Terminal MRT and Chronological Bus Monitor CM functions either independently or simultaneously In order to run any of these functions information must be loaded into specific fixed register locations Base Registers Some of these registers contain pointers to other areas of memory registers The selection of these pointers is left up to the discretion of the user Therefore memory blocks can be positioned in the on board memory to suit user requirements This setup means that fixed position registers are minimal 32 CONVENTIONS The architecture of both 3838 interfaces is identical allowing two independent low speed in
54. e VME 4220 or performing a software or hardware re set system self test will be performed The VME 4220 will perform system self test on the BC MRT and CM features of both Bus 1 and Bus 2 lasting approximately three seconds In the event of a failure of any part of the BIT on either Bus 1 or Bus 2 LED s will light on the front panel BIT 1 BIT 2 indicating the section that has failed UM 10997 Rev B 15 2 5 SPECIFIC 3838 3910 INTERFACE FEATURES 2 5 1 Clock features The local clock can be one of to types depending on the module firmware type used If the module firmware type is standard 32 bit clock then the format will be a 32 bit binary clock That will have an LSB of 10uS for BC MRT and MRT operations and 0 5uS for CHRON MON operations If the module firmware type is IRIG B then the clock format will be as follows 2 5 2 IRIG B Counter Features This 4 x 16 bit word counter can be setup to decode incoming IRIG B serial time code or programmed to free run This counter reports the date and time of day accurate to 0 515 The value of this register can be read via the Clock HI and Clock LO base registers When free running this counter can be pre set updated by the user The format of this clock is as follows The first 3 values will be the current clock time as decoded from the IRIG B time code The last 16 bit word will be a value 0 1999 defining the fraction of a millisecond with a resolution of 0 5uS per tick 15 word N0 CC
55. er TPP Trigger Pass Pointer TFP Trigger Fail Pointer TSR Trigger Stop Register Example 1 Find the word defined by Trigger Data 1 then save the number of messages defined by the PTC register TTRI 0001H TDP 000 0005H 000 TSR 0006H Example 2 Find the message with word defined by the Trigger Data 2 followed by the Nth word within the message defined by the Trigger Data 4 Then save the number of messages defined by the PTC register TTRI 0001H TDPI 0002H 0002H 0001lH TTR2 0002H TDP2 0004H TPP2 0005H 0001H TSR 0006H UMI 10997 Rev B 67 3 Find the message with word defined by Trigger Data 4 followed by the Nth word within the message defined by Trigger Data by Trigger Data 3 i e Trigger on a specific 32 bit word Example 4 TTRI 0001H TDP 0004H 0002H 000 TTR2 0002 TDP2 000 TPP2 0003H TFP2 000 TTR3 000 TDP3 0003 TPP3 0005H 0001H YTTR4 0006H Find the message with word defined by Trigger Data 4 followed by the Nth word within the message defined by Trigger Data 1 Then selectively capture all messages with word defined by Trigger Data 3 followed by word within the message defined by Trigger Data 2 TTRI 0001H TDPI 0004H 0002H 000 TTR2 0002H TDP2 000 TPP2 0003H TFP2 000 TTR3 0004 TDP3 0003 TPP3 0004H TFP3 0003H YTTR4 0005H 0002H TP
56. essage Data Word Count is defined in the DDB extra word for LS messages will be the last received word of a message in excess of the DDB data word count 5 55 LS ERROR INJECTION DEFINITION Error injection on status word and 3838 data words transmitted can be defined message by message using the message error descriptor word in the look up table or globally for all messages transmitted by an RT using global RT error injection word in each RT simulation table UM 10997 Rev B 50 5 51 Global RT Error Description Word RT Simulation Table The following word defines the errors that can be injected into the message D15 014 D12 009 D07 D06 005 004 D03 102 T T T X X X X X X X X X X X 000 gt Modulation Error XXXXXXXXXXXXX WWWWWWYYYYYYY WWWWWW Word Number For Modulation Error Y 0 55 0 1 Y Y Y Y Y 0 0 0 00 Parity error 54 S3 52 51 SO Synchro Pattern Error B4 B3 B2 BO Manchester Bit Error L4 L2 LI LO Word Length Error ll ll TTT 001 gt Wrong Bus Error XXXXXXXXXXXXX 0000000000000 TTT 010 gt Both Bus Error XXXXXXXXXXXXX 0000000000000 TTT 011 gt Word Count Error XXXXXXXXXXXXX 000000PCCCCCC P 2 3 Word Count Error Polarity Word Count Error VE Word Count Error VE CCCCCC Word Count Error Value Allows 64 Words 100 gt Response Time Error XXXXXXXXXXXXX 000
57. ew trigger to be activated if this trigger condition fails This value will be the range 1 to 5 UM 10997 Rev 62 Trigger Stop Register Base Address 2 This register will always be programmed to the value 6 This register is the STOP trigger sequence register Trigger Data 1 Trigger Data 1 Bit Mask Register Base Address 30H This register will define the bits to be ignored in the trigger bit pattern for trigger data 1 Any bit set in this register will be masked from the trigger test condition Trigger Data 1 Bit Pattern Register Base Address 32H This register will define the bit pattern required for trigger data 1 Trigger Data 1 Bus ID Word Type Mask Base Address 34H This register will define the Bus ID and Word Type bits to be ignored in the Bus ID Word Type Register D15 D14 D13 D12 D11 D10 D09 D07 D06 DOS D04 D02 DO1 DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 Both W bits Ignore Word Type in trigger condition Both B bits Ignore Bus ID in trigger condition Trigger Data 1 Bus ID Word Type Register Base Address 36H This register will define the Bus ID and Word Type for the trigger condition D15 D14 D13 D12 D11 D10 D09 D07 D06 DOS D04 D02 DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 WMs
58. his indicates that the 3910 message had a bit count error The following word in the stack will be 0000 for a 3910 message with no Word Count error W bit clear If the W bit is set this word will be a signed number defining the polarity 1 ve 1 The following words in the stack will be the received 3910 message as shown in table 6 5 Table 6 5 Stack Messages WORD No NAME 1 Frame Control Physical Address 2 Destination Address 3 Word Count 4 Data 5 Data 6 Data N 2 Data N 1 Data N FCS 6 51 Flow Diagram TRIGGER SETUP Base 46H Trigger STACK Set up Register PTCR SCCR SPR FPR etc UM 10997 Rev B 532
59. his value will be the range 1 to 5 Trigger 2 Fail Pointer Base Address This register will define the new trigger to be activated if this trigger condition fails This value will be the range 1 to 5 Trigger 3 Trigger 3 Type Register Base Address This register will define the trigger type allocated to trigger 3 This value will be the range 1 to 6 Trigger 3 Data Pointer Base Address 20H This register will define the trigger data allocated to trigger 3 This value will be the range 1 to 4 Trigger 3 Pass Pointer Base Address 22H This register will define the new trigger to be activated if this trigger condition passes This value will be the range 1 to 5 Trigger 3 Fail Pointer Base Address 24H This register will define the new trigger to be activated if this trigger condition fails This value will be the range 1 to 5 Trigger 4 Trigger 4 Type Register Base Address 26H This register will define the trigger type allocated to trigger 4 This value will be the range 1 to 6 Trigger 4 Data Pointer Base Address 28H This register will define the trigger data allocated to trigger 4 This value will be the range 1 to 4 Trigger 4 Pass Pointer Base Address 2AH This register will define the new trigger to be activated if this trigger condition passes This value will be the range 1 to 5 Trigger 4 Fail Pointer Base Address 2CH This register will define the n
60. it Cl can be cleared in the control register background program can be interrupted by insertion command The insertion program cannot be interrupted by any other insertion command In this case the second insertion request will be delayed until the end of the first one Insertion program starting just before a minor cycle start will delay this one is updated by the on board processor after executing BC stop command 3 4 3 5 Reserved 0CH 3 4 2 9 LPIQAP Low priority interrupt queue start address 3 4 210 Reserved 10H 3 4 2 11 HPIQAP 12H High priority interrupt queue start address 3 4 2 12 Reserved 14H 3 4 2 13 MIQAP 16H Message interrupt queue start address 3 4 2 14 Reserved 18H 3 4 2 15 SRQAP Status report queue start address 3 4 2 16 Reserved ICH 3 4 2 17 RTSTAD RT simulation table start address Contains the address of the RT Simulation Tables which defines the RT status when they are simulated 3 4 2 18 Reserved 20H 3 4 2 19 Reserved 22H UM 10997 Rev B 28 3 4 2 20 Toggle Buffer Address Offset 24H MSB 1 globaltoggle enable 0 notoggle offset 15 bits MSB offset 15 14 0 For a data buffer if the toggle feature 15 selected bit 15 1 address of toggle buffer 15 Buffer Address High Toggle Buffer Offset Buffer Address Low 15 bits For further details refer to paragraph 4 3 3 3 3 4 2
61. minor cycle time e 10 us for LSB the value for 20ms is 7 e It must be initialised at the beginning of the background program e This instruction resets the minor frame counter register SWPSE Software Pause e To be put at the end of each minor cycle instruction list with the minor frame duration utility to have automatic minor frame restart Examples INITF xxxx HWSPE waiting an external trig SWPSE JSR Minor Cycle 1 SWPE SWPSE BRA xxxx with Minor cycle X SMB xxxx SMB xxxx RTS LOOP 8 JSR Minor cycle SWPSE DBNE xxxx SITH BRA xxxx e Insertion Commands be executed during SWPSE state e HALT Oncompletion of this instruction the board will return to the BC idle state e To re start the board BC Cold Warm Start command register e SITH xxxx SITL xxxx e The on board processor puts the value code xxxx in the cycling FIFO s gt High Priority L gt Low Priority HWPSE Hardware Pause e Restart by the external Trig In external CK All the registers are not initialised e Used to synchronise messages of minor frames on external Trig In Example See SWPSE above 10997 Rev B 27 3 4 2 7 Insertion Running Pointer OAH The Insertion Running Pointer IRP has the same set of instructions as Instruction Set Background Program To initiate an insertion the user must first load the IRP with the address of the insertion program Then b
62. mode and the configuration tables in RAM The micro controller directly drives word by word the 3838 interface and initiates the HS 3910 interface depending on the HS action word messages running on the 3838 lines The micro controller management unit allows flexibility and expandability as well as for the bus control tasks as for the user interface 18 3838 INTERFACE The 3838 interface is a dual redundant interface which includes a standard dual redundant transceiver and a Manchester encoder decoder with full error detection and error injection capabilities which include Manchester bit error Synch bit error Parity error Word length error Wrong bus error Both bus error Response time error 19 HS3910 INTERFACE The HS 3910 interface includes clock recovery encoder decoder and HS frame control functions with error detection and error injection capabilities Preamble bit count error Word count error or Start End delimiter pattern error Bit count error Frame check sequence FCS error Manchester bit error HS transmitter initialisation time TI and HS receiver initialisation timeout RIout are programmable This 3910 interface drives either an on board non redundant HS electrical transceiver or external dual redundant HS fibre optic transceivers This interface is controlled by the micro controller but is directly connected by DMA to the RAM transfer the HS data words UM 10997 Rev B
63. n the command register clears the board is ready for a new command Refer to table 3 2 10997 Rev B 23 3 4 2 4 Command Register CR 04H Prior to clearing the command request bit CO in the control register the user must first test that the command register is clear When the command register is clear the user can insert the next command to be executed After the command is loaded bit CO in the control register can be cleared When the command register clears the board is ready for a new command Refer to table 3 2 Table 3 2 Command Register CR CODE COMMAND 0000H Illegal 0001H GO TO BC MODE 0002H GO TO MRT MODE 0003H GO TO MON MODE 0004H BC COLD Start 0005H BC WARM Start 0006H BC STOP 0007H MRT COLD Start 0008H MRT WARM Start 0009H MRT STOP 000AH PAUSE 000BH UNPAUSE 000CH LOAD CLOCK 000DH SELFTEST 000EH RUN MONITOR 000FH STOP MONITOR 0010H Synchronise CLOCK NOTE PAUSE Stop the Local clock UNPAUSE Restart the Local Clock UM 10997 Rev 24 3 4 2 5 The status register will contain word reflecting the status of the board as shown in table 3 3 Status Register SR 06H Table 3 3 Status Register CODE STATUS 0001H BC IDLE 0002H MRT IDLE 0003H MON IDLE 0004H BC RUNNING 0005H BC INSERTION RUNNING 8004H BC PAUSED Background 8005H BC PAUSED Insertion 9004H EXECUTING SOF
64. ng data buffers the FC and PA bytes are automatically updated by the micro controller LS data buffers can be stored as follows e The standard way data words behind the time tag words e A particular way allowing the user to store header words of the data message in a different buffer from the following data words The header option and the number of header words are defined in the option mask Header Address Header Message K Data Message K Header Message 2 Data Message 2 Header Message 1 Header Word Data Message 1 Time Tag High Time Tag Low Data Data Data Buffer Address Data Data 10997 Rev B 45 DB ADDRESS 3838 BUFFER 3910 BUFFER 00H Time Tag HI Time Tag 3 02H Time Tag LO Time Tag 4 04H Data FC PA Automatically Updated 06H Data DA 08H Data WC 0AH Data Data 0CH Data with without Header Word Data Y Data FCS In Receive Message only Table 4 3 Data Buffers 44 MODE COMMANDS In Bus Controller mode the Western Avionics 4220 board can transmit all mode command messages LS or HS For each mode command message data descriptor blocks pointed through the look up table allow the definition of interrupt requests or associated data word address storage If such a command is directed to an on board simulated RT the co
65. ons 12 MANUAL DESCRIPTION The following paragraphs provide a general description of the manual layout and content Section 1 Section 2 Section 3 Section 4 Section 5 Section 6 UM 10997 Rev General Information contains a brief description of the manual and a general description of VME 4220 This section also contains the architecture protocol management STANAG 3838 interface information STANAG 3910 interface information instrument specifications information concerning accessories furnished items and also safety precautions Installation and Preparation for Use contains instructions on installation preparation for use self test and reset of VME 4220 Operation contains a functional description of VME 4220 and operating procedures necessary to run VME 4220 Bus Controller Mode of Operation contains information on the mode of operation for the Bus Controller of VME 4220 Multiple Remote Terminal Mode of Operation contains information on the mode of operation for the Multiple Remote Terminals of VME 4220 Chronological Bus Monitor Mode of Operation contains information on the mode of operation for the Chronological Bus Monitor of VME 4220 13 SYSTEM CHARACTERISTICS AND SPECIFICATIONS The characteristics and specifications of VME 4220 are listed as follows e VME e BITE Weight e Power e Temperature e Humidity Front Panel 3838 Connectors Memory mapped real time VM
66. or Register Only if this condition is met will it branch to the trigger defined by the Pass Register If this condition is not met the next trigger will be defined by the Fail Pointer Register Selective 1 Trigger Mode The Selective 1 Trigger searches for a particular word as with the Single Trigger type However if the last word of a message 15 encountered before this trigger condition is met the message is not saved on the stack If this trigger condition 1s met it will branch to the trigger defined by the Pass Register Selective 2 Trigger Mode This trigger type is the same as the Window Trigger with the following exceptions a If the specific word within the message is not found the message will not be stored on the stack and the next trigger is defined by the contents of the Fail Pointer Register b When the trigger condition is found the message is stored on the stack If the number of selective messages defined by the Selective Capture Count Register have not been stored the next trigger is defined by the contents of the Fail Pointer Register When the programmed number of messages have been stored the next trigger is defined by the Pass register Therefore the two selective capture triggers allow the storage of a specific message or messages Post Trigger Count Mode This mode is used as a terminator to the trigger sequence This mode simply stores the number of messages defined by the Post Trigger Count Register on the sta
67. ot VME board 6U 1 4 43 Bus Controller BC Features With MRT Simulation and Data Monitoring Bus Control Autonomous frame control using comprehensive set of instructions and message descriptor blocks Acyclic message insertion Error injection Frame frequency selection Inter message gap selection Response time out selection Bus events detection mask storage and reporting bus errors status word bits e Simultaneous MRT Simulation up to 31 e Data Words Transfers 10997 Rev B e Data buffer simulation for the BC and the simulated RT s Sub address based data buffer access with data descriptor blocks defining each bus message Multi buffering linked buffers or frequency toggled buffers Vectored interrupts section two different interrupts with vector queues e Data status report Data buffer time tagging Simultaneous monitoring of all data buffers 143 Multiple Remote Terminal MRT Features e Simulation Up to 31 RT simulations Mode and Broadcast commands handling Error Injection Data Words Transfers Data buffer simulation for simulated RTs Sub address based data buffer access offering same powerful data buffering as in bus controller mode non transmitted data messages are monitored 1 4 4 Chronological Bus Monitor CM Features Capture of all bus activity in chronological stack with time tagging of each message Comprehen
68. r manages each RT two 32 word vector words FIFO s one per priority These vector words are then used by the RT simulation If an RT FIFO is not empty the on board processor reads it then writes the value in RT vector words RT Simulation Table and sets the service request bit in the status word If a Transmit Vector Word mode command message occurs the on board processor reads the RT FIFO s Ifempty the on board processor resets the service request bit and the vector word e Otherwise the on board processor reads the FIFO s and writes this next value in RT vector word High priority vector words are processed before low priority vector words UM 10997 Rev B 30 The following 4Kbyte block after the service request queue is reserved for the individual RT requesting FIFO s managed by the on board processor gt SERVICE REQUEST QUEUE 003 0040H Meee P Tr To enter a request in the User Requesting Queue the user must manage the current writing pointer SRQADP in Base Registers and control the words pointed at are clear if these words are non zero the queue is full Reaching the end of the queue the user must restart at the beginning of the queue If several user CPUs can enter requests at the same time it is necessary to share control of SRQADP using for example the TASR flag with a test and set instruc
69. ress MRT Only 08H HS Look up Table Address MRT Only 0AH LS Mode Commands Look up table Address MRT Only 0CH Vector Word 0EH LS BIT Word 10H HS Status Word 12H HS Last Action Word 14H HS BIT Word 16H Global RT Error Descriptor Word MRT Only 18H Not Used 1AH Not Used 1CH Not Used Not Used 20H p 3E0H Only 3 words used Set all others to 0 Broadcast LS Look up Table Broadcast HS Look up Table Broadcast LS Mode Commands Look up Table Address Table 3 4 Remote Terminal Simulation Table 3 51 Simulation Type Word Bits 14 to 0 are for MRT only UMI 10997 Rev B BIT 15 BIT 14 BIT 13 BIT 12 BIT 7 BIT 6 BIT 0 other bits Bits 7 and 6 1 RT simulated 1 Reserved 1 Inhibit transmitter LS on primary bus 1 Inhibit transmitter LS on secondary bus 1 Errors enabled on primary bus status word and data Errors enabled on secondary bus Status word and data 1 Enable global error injection 0 Enable global RT errors defined in the RT simulation table as message per message errors defined in the look up tables 32 3 5 2 Status Word Broadcast and message error bits are dynamically updated Service request bit automatically set by the request files and cleared by the TX vector word mode code command Busy bit can be set by user to disable data transmission 3 5 3 LS Last Command Word Automatically updated including broadcast so the TX last
70. rminals can simultaneously be simulated All non simulated data buffers can be monitored An internal minor frame duration counter allows autonomous control of cycling frames Insertion instruction lists define sequences of messages to be messages can be inserted on the host request inserted Refer to figure 4 1 the Bus Controller Organisation Diagram Message Descriptor Block Message Number Address in LUT BASE REGISTER Control Register BRP Background Program WV way Area IRP LEN n 7 eb SMB Queues Address 4 Insertion Program RTSTAD RT Simulation Table RTO Address LS LUT RTI from MPP Resend MRT gt Reserved MR v BDD Address Low High Priority Priority Interrupt Interrupt HS LUT 4 Address from MDB Reserved MR BDD Address Message Messages Interrupt Status Report BC MRT mRERHEEHERE MRT Figure 4 1 UM 10997 Rev B 34 DDB Options mask Data buffer Address HI Data buffer Address LO DDB Options mask Data buffer Address HI Data buffer Address LO Bus Controller Organisation Diagram Acrylic ToLUT DATA BUFFERS Time Tag HI Time Tag LO Data DATA BUFFERS Time Tag HI 42 DESCRIPTOR BLOCK MDB Each bus message is defined by a mess
71. roduction T 18 2 7 2 Electrical Characteristics eese eene trennen eret 18 VME 4220 OPERA TION eere 19 3 1 INTRODUCTION eter tette eere sade eee 19 32 CONVENTIONS 2220 D ER iUas NE 19 3 3 ORGANISATION DIAGRAM 19 34 8 19 3 4 1 Base Register Names and Location esee 21 3 4 2 Base Register Descriptions essen nennen meer 22 3 5 REMOTE TERMINAL SIMULATION innen 32 3 5 1 Simulation Type Word 32 3 5 2 Status Word a a RO tess aus LO DAS eke 33 3 3 3 LS East Command Word a eas e rein ied carne reap 33 3 5 4 LS Word S 33 3 5 3 HS Status Word 33 3 5 6 HS ACUO D M 33 3 5 7 HS BU WOLU C A 33 UMI 10997 Rev B 2 4 BUS CONTROLLER MODE OF 20 124 0 2000 0
72. rresponding actions are made on the RT simulation table e Transmit RT status word last command word LS bit word e Inhibit or override inhibit LS or HS transmitters Examples Synchronise with Data Word The data is obtained from data buffer pointed by the DDB b Transmit Last Command DDB is analysed the data word transmitted is stored in data buffer If the RT is simulated the last command word from the RT simulation table is transmitted c Transmit Bit Word Similar to transmit last command d Transmit Vector Word Similar the transmit last command and then if the RT is simulated the service request bit in the RT status word is reset and the vector word is reset or updated with the next vector word in FIFO s if any UM 10997 Rev B 46 4 5 INTERRUPT REQUESTS Three types of interrupt requests IRQ can be generated by the Western Avionics 4220 board RQ L and IRQ H low priority and high priority are synchronisation interrupts defined as follows By instructions BC instruction list message descriptor block to report on bus events detection In data descriptor block to signal the transmission of a message IRQ M is a data message interrupt and occurs only when the transmission of a data buffer is correct and the requesting bit is set in the data descriptor block It can also be programmed to occur with the last message of a set of 2 to 16 messages set of
73. rrupt will be generated when the stack is full If set a physical INTA interrupt will be generated when the stack is half full UM 10997 Rev B 58 6 2 7 Load Clock HI LO Registers 38H1 3AH If a LOAD CLOCK command is executed these two registers define a 32 bit value to be loaded into the counter If a SYNCHRONIZE CLOCK command is executed the two registers define a 32 bit signed number to be added to the current clock value 6 2 8 Current Address Register CAR 42H This register contains the PAGE address of the current message being stored 6 2 0 Trigger Occurrence Register TOR 44H This register contains the PAGE address of the message that met the pre programmed trigger condition 6 2 10 Trigger Set up Pointer TSP 46H This register contains the absolute address of the trigger set up data NOTE This value is only 16 bits All trigger set up data must reside in the first 64Kbytes of the board 6 2 10 1 Trigger Set up Data TSP Address 00H Post Trigger Count Register PTCR This register will contain the number of messages to be stored after the trigger condition is met This value will be in the range 0000H to 8000H 0000H Stop immediately after trigger message 8000H Capture Forever 02H Selective Capture Count Register SCCR This register will contain the number of messages to be stored when the monitor is in the Selective Capture Mode This value will be in the range 0000H 8000H
74. s diagram eee esee eerte eene 14 Figure 2 1 Switches M 17 Figure3 1 Organisation Diagram eese suntin s sins sets sensns enne enne 20 Figure 4 1 Bus Controller Organisation 4 1 eene 34 Figure 4 2 Data Buffers Simulation and Monitoring eee ee eese essent eene setenta seta 40 Figure 5 1 Multiple Remote Terminal Organisation Diagram eee enn 49 List of Tables Table 1 1 3838 Connector Pinouts Pri amp Sec amp B eene ette tnn nest setas aseo nosset ta 13 Table 1 2 9 Way I O Connector Pinouts 13 Table 3 1 Base Register Names and Locations esee eee esee ee seen tns 21 Table 3 2 Command Register eese reet ein Serna ea e eva a e poa s SUP ERN e avg ge geh ep Sena eee reu 24 Table 3 3 Status Register 25 Table 3 4 Remote Terminal Simulation Table cscsscssssssscesscssssssscssssscsesssssscessnsesnsesssesssessssssssesssesseseoees 32 Table 4 1
75. ses the value of the data word which is for example the minor cycle number 0 to 7 to manage frequency toggling of the data buffers 5 7 44 Frequency Toggle The frequency toggle option works in the same manner as the BC mode except that the minor cycle number is given by the data word associated to the mode command synchronise with data word This mode command is due to circulate on the bus at the beginning of each minor cycle and toggles bank A or B are managed when this message occurs Minor Cycle 0 frequency F F Hz F 2 Hz F 4 Hz F 8 Hz N Erw tA gt w Q P gt S gt gt gt S 00 gt gt gt pU gt w gt gt gt w gt 00 gt w w gt gt w 0 Uu w gt gt w Uu wi gt w w wiw gt gt 5 7 5 Programmable HS RI TI Time in DDB When in MRT mode these values have an offset of 18us For example if the user requires a TI time of 30uUs a value of 12 must be stored in the DDB word UM 10997 Rew B 55 6 CHRONOLOGICAL BUS MONITOR MODE OF OPERATION 61 INTRODUCTION When acting in BC or MRT mode a comprehensive window monitor facility is provided However the Western Avionics 4220 can also act as a chronological monitor for bus event detection and message recording In this mode the Western Avionics 4220 can be set to trigger on specific events and sequentially record precise time stamped
76. sive multi trigger facilities allowing selective capture and interrupts to be performed on complex data sequence Cyclical stack up to 8Mbyte with interrupt on completion of capture 3838 and 3910 errors detected UM 10997 Rev B 9 15 VME 4220 ARCHITECTURE The VME 4220 board is a standard VME interface with high performance architecture and complex features Plugged into a VME card cage it provides enhanced test and simulation functions for all modes of operation of a STANAG 3838 and STANAG 3910 bus 3838 I FACE 1 3838 I FACE 2 COUPLING MATRIX 3910 FOFE and I FACE 1 2 INTERFACE 3910 PA I FACE2 NOTE 1 CONTROL CODE NOTE 1 Second module can only receive 3910 data Figure 1 1 VME 4220 Board Functional Block Diagram 10997 Rev B 10 16 BUS COUPLING MATRIX This matrix allows the user to define the STANAG 3838 buses as direct or stub coupled It also allows interconnections to be made between the buses This enables the two STANAG 3838 buses to be connected without the need of external coupling and interconnections Control of this matrix is achieved via the control register of the BUS 1 interface 1 7 PROTOCOL MANAGEMENT UNIT A micro controller based structure running at 40Mhz handles the management of the 3838 and 3910 protocol for each of the operating modes BC MRT BM The micro controller works each of the 3838 command status and data words functions of its operating
77. st condition Trigger Data 2 Bit Pattern Register Base Address 3EH This register will define the bit pattern required for trigger data 2 Trigger Data 2 Bus ID Word Type Mask Base Address 40H This register will define the Bus ID and Word Type bits to be ignored in the Bus ID Word Type Register D15 D14 D13 D12 D11 D10 D08 D07 DOS 004 D02 DOL DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 Both W bits 1 Ignore Word Type in trigger condition Both B bits 1 Ignore Bus ID in trigger condition Trigger Data 2 Bus ID Word Type Register Base Address 42H This register will define the Bus ID and Word Type for the trigger condition D15 D14 D13 D12 D11 D10 D08 D07 DOS 004 D02 DOL DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 WMsb WLsb BMsb BLsb 0 0 Trigger on Command 0 0 Illegal 0 1 Trigger Status 0 1 Trigger on Primary 1 0 Trigger on Data 1 0 Trigger on Secondary 1 1 Trigger RT RT Transfer 1 1 Trigger on Both Buses Trigger Data 2 Error Word Mask Register Base Address 44H This register will define if the Error Word Register is to be included in the trigger condition D15 D14 D13 D12 D11 D10 D08 D07 D06 DOS 004 D02 DOL DOO 0 0 D 0 0 0 0 0 0 0 0 0 0 0 0 0
78. st reset the interface by Taking RS LO the HI Default is standard firmware With the CE bit set this bit shall define the clock type to use CE CM 0 0 Nochange 0 1 Nochange 1 0 32bitclock 1 1 IRIG B clock Note Default is 32 bit clock With the BE bit set this bit shall define the bus coupling for the two buses E CM 0 Nochange 1 Nochange 0 1 Separate buses Buses joined Note 1 Default is separate buses 2 The BM BE bits are only applicable for the primary module The control register at address 800000 does not control the bus mode 0102H generates a command request while keeping RS set 22 3 4 2 2 Clock HI LO read register 00H 02H For the standard 32 bit clock a read HI followed by a read LO will report the current value of the 32 bit clock For IRIG B type modules the clock read 15 done as follows These two registers are for reading the current value of the on board clock A read of the Clock HI will request the current value of the clock to be latched into the output buffer The user must wait a minimum time of gt 0 5uS before beginning to read the clock value to ensure latching has completed Four consecutive reads of the Clock LO location will return the clock value as 1 word CC DDDDDDD HHHHH C Days x 100 D Days Hours 2 word 0000 MMMMMM 6555555 M Minutes S Seconds 3 word 000000 MMMMMMMMMM M Milliseconds 4 word 00000 UUUUUUUUUUU U 0 5uS ticks If the MSB
79. ta buffer will be stored in the cycling interrupt base register 40H 36 4 24 LS Message Error Phase Definition 06H The following word defines the location of errors that can be injected into the LS message D15 014 D12 Dil DIO 009 D07 D06 005 D04 0 0 0 0 0 0 0 0 0 0 0 0 XXX 000 Error Injection Disabled XXX 001 gt Inject Error in 1st BC TX Initial BC message XXX 011 gt Inject Error in 1st RT SIM Ist RT response XXX 100 gt Inject Error on 2nd RT SIM 2nd RT RT response 4 2 5 LS Message Error Description Word 08H The following word defines the errors that can be injected into the 3838 message D15 014 D12 DIO 009 D07 D06 005 D04 T T X X X X X X X X X TIT 000 gt Modulation Error XXXXXXXXXXXXX WWWWWWYYYYYYY WWWWWW Word Number For Modulation Error Y Y Y Y Y Y Y ERROR TYPE 0 0 0 0 0 00 Parity error 0 1 1 55 54 53 52 51 SO Synchro Pattern Error 0 B4 B3 B2 BO Manchester Bit Error 1 L4 L3 L2 LI LO Word Length Error ll TTT 001 gt Wrong Bus Error XXXXXXXXXXXXX 0000000000000 TIT 010 gt Both Bus Error XXXXXXXXXXXXX 0000000000000 TIT 011 gt Word Count Error XXXXXXXXXXXXX 000000PCCCCCC P Word Count Error Polarity 0 Word Count Error VE 1 Word Count Error VE CCCCCC Word Count Error Value Allows 64 Words 100 Response Time Error XXXXXXXXXXXXX 00000000RRRRR RRRR Unique Response
80. terfaces However if the card is to be used on 3910 buses the second module can only receive 3910 data This feature allows the primary module to be set up as a BC MRT or BC MRT and the secondary module to be set up as a Chronological Monitor capable of triggering and capturing all 3838 and 3910 data simultaneous with the operation of the primary module BASE Base address of module The primary module base address is the base address of the card The secondary module resides at the base address of the card 8 Mbytes The memory range BASE 10000H to End of Memory 3838 3910 interface is reserved for the 3838 3910 data blocks All other data must reside in the first 64Kbytes After a Power On On board processor doing its power on initialisation Then executing Self Test BIT Then waiting for a user command DSI per default insertion program is disabled 3 3 ORGANISATION DIAGRAM The organisation diagram figure 3 1 shows how the functional areas of the VME 4220 3838 3910 interfaces can be controlled 3 4 BASE REGISTERS The only fixed position registers are the Base Registers Base Registers are the starting points for a description of operation of any of the three modes of operation BC MRT and CM They are located starting at the module Base Address UM 10997 Rev B 19
81. th B bits 1 Ignore Bus ID in trigger condition Trigger Data 3 Bus ID Word Type Register Base Address 4EH This register will define the Bus ID and Word Type for the trigger condition D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 DOS 004 D02 DOL DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 WMsb WLsb BMsb BLsb 0 0 Trigger on Command 0 0 Illegal 0 1 Trigger on Status 0 1 Trigger on Primary 1 0 Trigger on Date 1 0 Trigger on Secondary 1 1 Trigger RT RT Transfer 1 1 Trigger on Both Buses Trigger Data 3 Error Word Mask Register Base Address 50H This register will define if the Error Word Register is to be included in the trigger condition D15 D14 D12 DII D10 D09 D08 007 D05 04 D02 DOI DOO 0 0 D 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Error condition disabled UMI 10997 Rew B 65 Trigger Data 3 Error Word Register This register will define the Errors required in the trigger condition If more than one error is set the trigger condition will be a logical OR of the errors Base Address 52H D15 D14 D13 D12
82. tion enter a request a CPU must carry out the following procedure Test and set the TASR word MSB bit and a e I ffree the SRQADP is read to define the entry address in the queue e Ifthe entry location defined by the SRQADP are clear the two words may be entered in the queue If these words are non zero the queue is full e Increments the SRQADP if the end is reached reinitialise it to the beginning e Resets the TASR b e Ifnot free waits until free 3 4 2 27 Reserved 46H 3 4 2 28 PRI SEC 3838 3910 RT TX Inhibit HI LO 48H 56H HI RT 30 e vu RT17 6 LO RT15 RT14 RTO 0 enable the transmitter disable the transmitter A bit set defines the specific RT transmitter as inhibited Initialisation by user before cold start Disable enable by corresponding mode command messages The user modify the inhibit bits in real time The receive function of the simulated RT is never disabled 10997 Rev B 31 35 TERMINAL SIMULATION TABLE For each RT 16 words are used to define and store information concerning RTs The pointer to this table RTSTAD must be a multiple of 20H Refer to table 4 4 RTSTAD 1 RT31 Broadcast 00H Simulation Type word 02H RT Status Word 04H LS Last Command Word 06H LS Look up Table Add
83. ts 15 to 11 UM 10997 Rev B 54 If an error 15 detected an action word data following a receive command with HS sub address Pointer to the LS look up table with index HS sub address 5 7 SPECIFIC FUNCTIONS 5 7 1 Data Message Reception Each data message not transmitted by the Western Avionics 4220 board may be stored The path to access the data buffer is given by the RT look up table for messages BC lt gt RT Except for gt messages even if the RTs are simulated or not the path to point to the data buffer is always given by the transmitting RT look up table but the receiving RT look up table must point to a false DDB Received status words from RTs not simulated on board are stored in the associated disabled RT SIM table Ifan external RT fails to respond a value of FFFFH will be stored in the SIM table 5 7 2 Reception of Mode Commands Data Words For each mode command with data word message if the data word is not transmitted by the board it must be stored RT simulated or not The path for storing the data word is given by the RT mode command look up table 5 73 Mode Command Synchronise with Data Word When receiving a broadcast mode command Synchronise with Data word the on board processor e Stores the data word value in the Cycling Interrupt Update Register in base registers and set the cycling IRQ e Accesses to a DDB to store the data word in a buffer and time tag the data buffer e U
84. ultiple Remote Terminal Organisation Diagram The specifics of the MRT mode of operation mainly concern the following The logical path to point into the look up tables The errors injection capabilities BASE REGISTER RT Simulation DATA Table BUFFERS RTO RTO LS LUT BRP DDB IRP Oni k Illegalization Word 4 tions mas RX Address pU v P Queues Address Data buffer Address HI RT30 TX Data buffer Address LO RTSTAD RT31 Broadcast DATA BUFFERS RTO HS LUT DDB Illegalization Word tions mask RX Address pv P Low High Data buffer Address HI Priority Priority TX Data buffer Address LO Interrupt Interrupt BUFFERS RTO LS Mode DDE Code LUT Options mask Message Message mx legalization Word Data buffer Address Interrupt Status DDB Address Report TX BC MRT Figure 5 1 Multiple Remote Terminal Organisation Diagram UM 10997 Rev 49 5 2 LOOK UP TABLES For each RT the Western Avionics 4220 board manages three different look up tables the address of these tables are obtained from the RT simulation tables These tables are as follows LS Look up Table giving a descriptor for each LS sub address HS Look up Table giving a descriptor for each HS message identifier LS Mode Command
85. vel ML The position of the Manchester error is defined by a 17 bit count This bit is the MSB of this count The remainder of the count is defined in the following register 4 3 2 9 3910 Errors Injection 3 1EH This word is the remaining 16 bits of the Manchester error injection bit position in the data stream UM 10997 Rev B 44 4 3 2 10 Extended Sub Address To enable the extended sub address feature see the MDB type word When enabled the value of the DDB address in the look up table is in fact a pointer for a further look up table called the extended look up table The on board processor uses the 3838 byte of the first data word received multiplied by four to calculate an offset in the extended look up table to find the true DDB address word Therefore the DDB and data buffer used is defined by the value of the first 3838 RX data word Offset Reserved MRT 02H DDB address 4 3 3 Data Buffers Data buffers are pointed to by the buffer address word contained in the data descriptor blocks The address of the toggled buffer is calculated by adding the global toggle offset to the data buffer address value in the DDB The first two words of a data buffer are updated with the value of the local clock at the beginning of the message HS data buffers contain e The Time Tag e The three protocol words of the HS frame FC PA DA WC e The HS data words e The frame check sequence FCS for received data buffers For transmitti

Manual - Western Avionics Ltd

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