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NUC501 User`s Manual

1. HE E Lu i i a B JL Sg LJ E IE EATING PLANE c kE L m iw pel 0 20 LB pe CE es ee E poo Hh eo 12 Nuvoton Technology Corp 280 Revision A1 3 http www nuvoton com
2. 0 Selection for GPAx as one of input Pins to IRQO IRQ1 IRQ2 or IRQ3 2x 1 2x GPAxSEL H QO IRQ1 IRQ Q interrupt source Where x 0 15 GPAXSEL 0 GPAx pin is grouped as one of interrupt sources to IRQO 1 GPAx pin is grouped as one of interrupt sources to IRQ1 2 GPAx pin is grouped as one of interrupt sources to IRQ2 3 GPAx pin is grouped as one of interrupt sources to IRQ3 Nuvoton Technology Corp 145 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee IRQ Source Grouping IRQSRCGPB IRQSRCGPB GP_BA 0x84 RW GPIO Port B IRQ Source Grouping 0x0005_5555 EEE 2 32 i3 8 7 35 4 13 2 1 0 Bits Descriptions 0000000000000 Selection for GPBx as one of input Pins to IRQO IRQ1 IRQ2 or 2x 1 2x GPBxSEL H Pre RO IRQ3 interrupt source Where x 0 15 GPAXSEL 0 GPBx pin is grouped as one of interrupt sources to IRQO 1 GPBx pin is grouped as one of interrupt sources to IRQ1 2 GPBx pin is grouped as one of interrupt sources to IRQ2 3 GPBx pin is grouped as one of interrupt sources to IRQ3 Nuvoton Technology Corp 146 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee IRQ Source Grouping IRQSRCGPC IRQSRCGPC GP_BA 0x88 R W GPIO Port C IRQ Source Grouping 0x002A_AAAA 5 14 13 12 131 10 9 8 Lov dq 8 pq s Jj e po s Z1 E 2 Bits Descriptions ooo
3. Nuvoton Technology Corp 77 Revision A1 3 http www nuvoton com nUvoTon NUCSOT ee ii 6 5 5 APU Control Register Mapping R read only W write only R W both read and write C Only value 0 can be written Tm CURAD AFU BA 0x1c R current Access RAM Address Register 0x0000_0000 Nuvoton Technology Corp 78 Revision A1 3 http www nuvoton com NUC501 nuvoTon 6 5 6 APU Control Registers APU Control Register APUCON APU_BA 0x00 APU Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 lm Reserved APURST Reserved 7 e 85 j 4 3 2 3 o Reserved Bits Descriptions ES APU Reset 16 APURST O No action 1 Reset the whole ADC except register value as APU Run 0 O Disable 1 Enable Nuvoton Technology Corp 79 Revision A1 3 http www nuvoton com NUVOTON NUGSO ee ii Parameter Control Register PARCON APU_BA 0x04 R W Parameter Control Register 0x0000_0001 ARA a 3 RARA a 39 Reserved Reserved o7 6 s j 4 j 3 2 13 o Reserved Descriptions ERES Zero cross detection enable 25 O Disable 1 Enable Reserved 24 Reserved 257 PCM data format 16 O MSB is sample data 2 LSB is sample data 1 1 MSB is sample data 1 LSB is sample data 2 zeg Nuvoton Technology Corp 80 Revision A1 3 http www nuvoton com NUC501 nuvo
4. MINIO nRESET X12M EX12M X32K EX32K 5 7 Un POWER Nuvoton Technology Corp 12 Revision A1 3 http www nuvoton com nuvoTon NUC501 pre oA AoA A AA Oa atUAAMMMWVV VPP 6 5V VBAT USBVDD33 DVDD33 DVDD33 AVDD33 DVSS DVSS DVSS AVSS VCC CORE OUTPUT Pin Function for LQFP 64 TCK TMS TDI TDO nT RST GPC 0 GPC 1 GPC 2 Ni in WN U U U k ki lt I lt S lt e E P NI NIN CIAO A GPC 3 GPC 4 GPC 5 GPC 6 GPC 7 GPC 8 GPC 9 GPC 10 Table4 1 Pin function Nuvoton Technology Corp 13 Revision A1 3 http www nuvoton com nuvoTon NUC501 Symbol Iu LQFP64 LQFP48 TYPE Description GPA 1 AI 1 MICN GPA 2 AI 2 GPA 3 AI 3 GPA 4 3 2 2 AI 4 4 8mA I O with Analog input 4 8mA I O with GPA 0 General purpose input output digital pin AI O ADC analog input 0 MICP MIC GPA 1 General purpose input output digital pin Analog input AI 1 ADC analog input 1 MICN MIC GPA 2 General purpose input output digital pin 4 8mA I O i with igi i Analog input AI 2 ADC analog input 2 GPA 3 General purpose input output digital pin 4 8mA I O i with igi i Analog input AI 3 ADC analog input 3 GPA 4 General purpose input output digital pin 4 8mA I O i with igi i Analog input AI 4 ADC analog input 4 GPA 5 4 3 3 4 8mA I O
5. 02 5 5131312 I3 I Descriptions SCH os Lange og gt oscamogy o emm __ o9 oocamo9 Jo 20 pmoo lo 10 MI0 24hr 12hr 24 Hour 12 Hour Mode Selection It indicate that TLR and TAR are in 24 hour mode or 12 hour mode 1 select 24 hour time scale 0 select 12 hour time scale with AM and PM indication 24 hour time 12 hour time 24 hour time 12 hour time scale scale scale scale oo 12 Ami gt 12 32 PM12 001 O1 AMOA 13 21 PMO1 02 02 AM02 22 PM02 S 03 AM03 23 PM03 04 AMO4 24 PM04 OS AMOS 25 PMO5 Nuvoton Technology Corp 208 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee RTC Day of the Week Register DWR R W C Description Reset Value DWR RIC_BA 0x018 R W Day of the Week Register 0x0000 0006 ee ee ERE Reserved AAA Reserved Reserved ae TT CI a I3 7 Descriptions 3 3 Day of the Week Register 5 Seny fe sstuisy Nuvoton Technology Corp 209 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee RTC Time Alarm Register TAR RUNE pesci ATT TAR RTC_BA Ox01C R W Time Alarm Register 0x0000_0000 PETRI ee ee ee New Reserved 23 22 21 20 19 18 17 16 reserved do dHR 3 151313 I2 13 I reserved dose see O Rs Descriptions OOOO oam i0Mowr Time ie OS 9 16 ame i Mourtime Die S emm mmimmepe o 8 mm i intime di o fed
6. 2x 1 2x GPCxSEL Selection for GPCx as one of input Pins to IRQO IRQ1 IRQ2 or IRQ3 interrupt l source Where x 0 15 GPExSEL 0 GPCx pin is grouped as one of interrupt sources to IRQO 1 GPCx pin is grouped as one of interrupt sources to IRQ1 2 GPCx pin is grouped as one of interrupt sources to IRQ2 3 GPCx pin is grouped as one of interrupt sources to IRQ3 Nuvoton Technology Corp 147 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee GPIO A Interrupt Enable IRQENGPA IRQENGPA GP BA 0x90 R W GPIO Port A Interrupt Enable 0x0000_0000 _PA15ENR PA14ENR PA13ENR PA12ENR PA11ENR PA1OENR PASENR PASENR_ PA7ENR PAGENR PASENR PA4ENR PASENR PA2ENR PA1ENR PAOENR_ 205 14 133 2 uo 10 9 8 PAISENF PA14ENF PA13ENF PA12ENF PA11ENF PA1OENF PASENF PASENF_ L7 58 4 3 2 1 0 PA7ENF PAGENF PASENF PA4ENF PA3ENF PAZENF PA1ENF PAOENF_ Descriptions Enable GPAx input falling edge to trigger one of interrupt sources IRQO IRQ3 IRQSRCGPA register determines which IRQn n 0wW3 is the destination Enable GPAx input rising edge to trigger one of interrupt sources IRQO IRQ3 IRQSRCGPA register determines which IRQn n 0 3 is the destination Where x 0 15 PAXENF and PAxENR can be set 1 at the same time NOTE1 In normal operation mode for each pin PAXENF and PAxENR can be set both to detect both rising and falling edge NOTE
7. 7 6 5 4 3 2 11 90 AUDIO DATA2 Bits Descriptions Converted audio data3 at bufferi Read Only SE ee 16 bit digital audio data in 2 s compliment format Converted audio data2 at bufferi Read Only SEH AUDIO ATE 16 bit digital audio data in 2 s compliment format Nuvoton Technology Corp 274 Revision A1 3 http www nuvoton com nuvoTon NUC501 Audio control register AUDIO BUF2 AUDIO BUF2 ADC_BA 0x028 R W Audio data register 0x0000 0000 31 30 29 28 27 26 25 24 AUDIO DATAS5 23 2 21 20 19 18 17 16 AUDIO DATAS5 AUDIO DATA4 7 6 5 4 3 2 1 90 AUDIO DATA4 Bits Descriptions S i Converted audio data5 at buffer2 Read Only SE AUDIO DATAS 16 bit digital audio data in 2 s compliment format Converted audio data4 at buffer2 Read Only SEH AVDIO DALAR 16 bit digital audio data in 2 s compliment format Nuvoton Technology Corp 215 Revision A1 3 http www nuvoton com nuvoTon NUC501 Audio control register AUDIO BUF3 AUDIO BUF3 ADC_BA 0x02C R W Audio data register 0x0000 0000 31 30 29 28 27 26 25 24 AUDIO DATAZ7 23 22 21 20 19 18 17 16 AUDIO DATA7 AUDIO DATAG o7 6 5 4 3 2 1 90 AUDIO DATAG6 Bits Descriptions OOOO Converted audio data7 at buffer3 Read Only SE EE 16 bit digital audio data in 2 s compliment format Converted audio data6
8. PWM Timer 1 output to GPIOC 8 12 PWM Timer 1 output to GPIOB 9 PWM Timer 0 input pin selection 000 PWM Timer 0 input from GPIOA 12 001 PWM Timer 0 input from GPIOB 1 010 PWM Timer 0 input from GPIOC 3 011 PWM Timer 0 input from GPIOC 7 100 PWM Timer 0 input from GPIOB 8 Others disable PWM Timer 0 input function 37 Revision A1 3 nuvoTon 4 0 PWM_TMRO PWM Timer 0 output pin selection 1 output enable O output disable 0 PWM Timer 0 output to GPIOA 12 1 PWM Timer O output to GPIOB 1 2 PWM Timer O output to GPIOC 3 3 PWM Timer 0 output to GPIOC 7 4 PWM Timer O output to GPIOB 8 38 NUC501 Revision A1 3 Nuvoton Technology Corp http www nuvoton com nuvoTon NUC501 Nr PAD Control Register PAD_REG1 PAD_REG1 GCR_BA 34 PAD Control Register 0x0000_0000 Reserved Ca B ER Bits Descriptions ADC pins enable 23 16 represents GPIOA 7 0 respectivel 23 16 l l rep 7 0 i y O disable 1 enable UART1 Modem pin enable 12 UART1_MEN O disable 1 GPIOC 8 7 used as the pin of UART1 CTSn and RTSn UARTO Modem pin enable 11 UARTO_MEN O disable 1 GPIOB 4 3 used as the pin of UARTO CTSn and RTSn UART1 TxD and RxD pin enable 9 UART1_EN O disable 1 GPIOC 6 5 used as the pins of UART1 TxD and RxD Nuvoton Technology Corp 39 Revision A1 3 http www nuvoton com nuvoTon NUC501 UARTO TxD and RxD pin enabl
9. nuvoTon NUCS501 Dn OxB800_7000 0xB800_7FFF PWM_BA PWM Controller Registers OxB800_8000 0xB800_8FFF RTC_BA Real Time Clock RTC Control Register 0xB800_A000 0xB800_AFFF SPIMS_BA SPI master slave function Controller Registers 0xB800_B000 0xB800_BFFF TIMER_BA Timer Control Registers 0xB800_C000 OxB800 CFFF UART BA UART Control Registers Table 6 2 1 Address Space Assignments for On Chip Modules Nuvoton Technology Corp 24 Revision A1 3 http www nuvoton com NUVOTOM NUC501 Sor 6 2 3 AHB Bus Arbitration The internal bus of NUC501 chip is an AHB compliant Bus and supports to connect with the standard AHB master or slave NUC501 s AHB arbiter provides a choice of two arbitration algorithms for simultaneous requests These two arbitration algorithms are the d priority mode and the round robin priority rotate mode The selection of modes and types is determined on the PRTMODO control register in the Arbitration Control Register AHB bus arbiter also provides a mechanism for the maximum burst length for each AHB bus transfer The maximum burst length is 16 and when the current AHB data transfer count is equal to the maximum burst length the access of current AHB bus owner will be broken 6 2 4 Fixed Priority Mode Fixed priority mode is selected if PRTMODx 0 The order of priorities on the AHB mastership among the on chip master modules listed in Table 6 2 2 If two or more master modules request to access A
10. Msn Eom AT wat clock cycle tint 1024 wdt clock cycle trst 16128 wat clock cycle Watchdog Timer Timing Diagram Nuvoton Technology Corp 229 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee 6 17 3 Timer Control Registers Map R read only W write only R W both read and write TIE Reset Value TMR_BA 0xB800_B000 TCSR1 TMR_BA 04 Timer Control and Status Register 1 0x0000_0005 TICRO TMR_BA 08 Timer Initial Control Register 0 0x0000_0000 TICR1 TMR_BA 0C Timer Initial Control Register 1 0x0000_0000 TDRO TMR_BA 10 OR Timer Data Register 0 0x0000_0000 TDR1 TMR_BA 14 OR Timer Data Register 1 0x0000_0000 TISR TMR_BA 18 Timer Interrupt Status Register 0x0000_0000 WTCR TMR_BA 1C Watchdog Timer Control Register 0x0000_0400 Nuvoton Technology Corp 230 Revision A1 3 http www nuvoton com nuvoTon NUC501 emm Timer Control Register O 1 TCSRO TCSR1 TCSR1 TMR_BA 004 Timer Control and Status Register 1 0x0000_0005 Reserved CIO ACC ACC ACC E ICI CI Reserved aa els gt p po PRESCALE 7 0 Bits Descriptions ICE debug mode acknowledge enable e 0 When DBGACK is high the TIMER counter will be held 31 nDBGACK_EN 31 e 1 No matter DBGACK is high or not the TIMER counter will not be held Counter Enable 30 e O Stops Suspends counting e 1 Starts counting Interrupt Enable e 0 Disable TIMER Interrupt 29 e 1 Enable TIMER Interrupt If time
11. Rising latch and CFLR Falling latch When Disable Capture does not update CRLR and CFLR and disable Channel 2 Interrupt Channel 2 Falling Interrupt Enable ON OFF 1 Enable 2 FL amp IE2 0 Disable When Enable if Capture detects Channel 2 has falling transition Capture issues an Interrupt Channel 2 Rising Interrupt Enable ON OFF 1 Enable 1 RL amp IE2 0 Disable When Enable if Capture detects Channel 2 has rising transition Capture issues an Interrupt Channel 2 Inverter ON OFF 0 INV20 1 Inverter ON O Inverter OFF Nuvoton Technology Corp 194 Revision A1 3 http www nuvoton com nuvoTon NUC501 Capture Rising Latch Register3 0 CRLR3 0 CRLRO PWM_BA 0x058 R W Capture Rising Latch Register channel 0 0x0000_0000 CRLR1 PWM_BA 0x060 R W Capture Rising Latch Register channel 1 0x0000_0000 CRLR2 PWM_BA 0x068 R W Capture Rising Latch Register channel 2 0x0000_0000 CRLR3 PWM_BA 0x070 R W Capture Rising Latch Register channel 3 0x0000_0000 31 30 29 28 27 26 235 2 Reserved ER EE Reserved CRLRO 15 8 7 e 5 4 3 2 1 000 CRLRO 7 0 Descriptions 31 16 Reserved Capture Rising IE ie e Register0 1 RLRO RE Latch the PWM counter when Channel 0 has rising transition Nuvoton Technology Corp 195 Revision A1 3 http www nuvoton com nuvoTon NUC501 ee Capture Falling Latch Register3 0 CFLR3 0 CFLRO PWM_BA 0x05C R W Capture Fal
12. USB_DET USB detected input PWMTO PWM output for timer 0 GPB 9 General purpose input output digital pin nTRST JTAG ICE reset pin LQFP48 only USB_DET USB detected input PWMT1 PWM output for timer 1 GPC O General purpose input output digital pin SPIM1 SO Serial data output pin for SPIM1 master USB DET USB detected input GPC 1 General purpose input output digital pin SPIM1 SI Serial data input pin for SPIM1 master USB DET USB detected input GPC 2 General purpose input output digital pin SPIM1 SCK Serial clock output pin for SPIM1 master USB DET USB detected input GPC 3 General purpose input output digital pin PWMTO PWM output for timer O USB DET USB detected input GPC 4 General purpose input output digital pin PWMT1 PWM output for timer 1 USB DET USB detected input Revision A1 3 NUVOTOM NUCS01 UART1 TXD PWMT2 PWM output for timer 2 UART1 TXD Data transmitter output pin for UART1 GPC 6 76 59 4 8mA GPC 6 General purpose input output PWMT3 I O digital pin UART1_RXD PWMT3 PWM output for timer 3 UART1_RXD Data Receiver input pin for UART1 GPC 7 4 8MA GPC 7 General purpose input output PWMTO I O digital pin UART1_CTS PWMTO PWM output for timer 0 UART1 CTS Clear to Send input pin for UART1 GPC 8 General purpose input output digital pin PWMT1 PWM output for timer 1 UART1_RTS Request to Send output pin for UART1
13. nuvoTon NUC501 V NUC501 User s Manual Publication Release Date Nov 2009 Nuvoton Technology Corp 1 Revision A1 3 http www nuvoton com NUVOTOM NUC501 EE gt yvEF 1rro r _ _1 Table of Contents 1 General Description 6 2 Feature 6 3 Pad and Pin Configuration 9 4 System Diagram 19 5 Block Diagram 20 5 1 System block diagram 20 5 2 On Chip Bus block diagram 21 6 Functional Description 22 6 1 ARM7TDMI CPU Core 22 6 2 System Manager 23 6 2 1 Overview 23 6 2 2 System Memory Mapping 23 6 2 3 AHB Bus Arbitration 25 6 2 4 Fixed Priority Mode 25 6 2 5 Power On Settings 26 6 2 6 System Manager Control Registers 27 6 3 Clock Controller 45 6 3 1 Function Description 45 6 3 2 Clock Control Registers 45 6 4 SPI Synchronous Serial Interface Controller Master Mode 58 6 4 1 Overview 58 6 4 2 Features 58 6 4 3 SPIM Timing Diagram 59 6 4 4 SPIM Programming Example without DMA 59 6 4 5 SPIM Programming Example with DMA 60 6 4 6 Direct memory mapping mode 60 6 4 7 SPIM Serial Interface Control Registers Mapping 62 6 5 Audio Processing Unit 76 6 5 1 Overview and Features 76 6 5 2 APU Functional Description 76 6 5 3 AUDIO DAC Clock 76 6 5 4 APU Run Procedures 76 6 5 5 APU Control Register Mapping 78 Nuvoton Technology Corp 2 Revision A1 3 http www nuvoton com nuvoTon NUC501 Eme http www nuvoton com 6 5 6 APU Control Registers 79 6 6 SRAM Controlle
14. nuvoTon NUC501 SS eee GPIO A Interrupt Latch IRQLHGPA IRQLHGPA GP_BA 0xA4 R GPIO Port A Interrupt Latch Value 0x0000_0000 Reserved Reserved E NOTO OFTEN ee IE ee ee ee NENNEN NN PA15LHV PA14LHV PA13LHV PA12LHV PA11LHV PA10LHV PA9LHV PASLHV NS E ESS o E NEN PA7LHV PA6LHV PASLHV PA4LHV PA3LHV PA2LHV PA1LHV PAOLHV PAXLHV Latched value of GPAx while the IRQ IRQO IRQ3 selected by IRQLHSEL is active Where x 0 15 Nuvoton Technology Corp 152 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee GPIO B Interrupt Latch IRQLHGPB IRQLHGPB GP_BA 0xA8 R GpiO Port B Interrupt Latch Value 0x0000_0000 Reserved Reserved Peis a FO CI MS Reserved A 5 4 3 2 12 _o O PBxLHV Latched value of GPBx while the IRQ IRQO IRQ3 selected by IRQLHSEL is active Where x 0 15 Nuvoton Technology Corp 153 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee GPIO C Interrupt Latch IRQLHGPC IRQLHGPC GP_BA 0xAC R GPIO Port C Interrupt Latch Value 0x0000_0000 Reserved Reserved os EE s sm e 7 s 49 3 2 dad PCxLHV Latched value of GPCx while the IRQ IRQO IRQ3 selected by IRQLHSEL is active Where x 0 15 NOTE When a latched pin value is 0 there will be 2 meanings either the pin s input is recognized as LOW or the pin is setup as output mode so the input value is masked as O Nuvoton Technology
15. 23 9 5 7 1 1 5 4 3 2 1 0 SSC PIN 7 0 Descriptions n PIN oo Port A B C Pin Values Nuvoton Technology Corp 143 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Interrupt Debounce Control DBNCECON DBNCECON GP _BA 0x70 R W External Interrupt De bounce Control 0x0000 0000 Reserved Reserved as 33 33 3 3 E o gt J e Reserved Loe TS 5 4 3 TS J 0 DEELER 3DBEN ets pesi o DE 6 Sample interrupt input once per 64 APB clocks _ 8 Sample interrupt input once per 256 APB clocks 9 Sample interrupt input once per 2 256 APB clocks DBEN x debounce sampling enable for each IRQx x20 3 3 0 1 Interrupt input IRQx is filtered with de bounce sampling O Interrupt input IRQx is input directly without de bounce sampling IRQ Source Grouping IRQSRCGPA Debounce sampling cycle selection EL 0 Sample interrupt input once per 1 APB clocks Sample interrupt input once per 2 APB clocks Sample interrupt input once per 4 APB clocks Sample interrupt input once per 8 APB clocks Sample interrupt input once per 16 APB clocks 7 4 DBCLKSEL Nuvoton Technology Corp 144 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS IRQSRCGPA GP_BA 0x80 R W GPIO Port A IRQ Source Grouping 0x0000_0000 as 14 3 239 4 T_T 7 3 4 TATI Bits Descriptions b
16. 30 29 28 27 26 25 24 AUD INT MODE OP OFFSET 233 22 21 20 19 18 17 16 Reserved AUD INT VOL EN 27 6 5 4 3 2 13 e AUDIO AUDIO RE Bits Descriptions o Audio interrupt mode selection 2 b00 If AUD INT 1 the recording for one sample is finished 2 b01 If AUD INT 1 the recording for two samples are finished Be EE MODE 2 b10 If AUD_INT 1 the recording for four samples are finished 2 b11 If AUD_INT 1 the recording for eight samples are finished l Reserved 29 26 OP OrESEL For Ee used Keep the setting value to 0 25 10 Reserved 0 00 0000 0000000 Audio interrupt flag bits If AUD INT O the recording for 1 2 4 8 samples are not finished If AUD INT 1 the recording for 1 2 4 8 samples are finished AUD INT Write O to clear it Note This flag can be set by above hardware event if AUDIO EN 1 And when it is set an interrupt signal is asserted to the interrupt controller through ADC interrupt source Volume control enable bit If VOL EN 0 the hardware open the volume control path and 8 VOL EN open the recording path If VOL EN 1 the hardware enable the volume control path and enable the recording path Volume control bits 7 3 AUDIO VOL AUDIO VOL 4 0 0 1 2 31 indicate the volume from OdB 1dB 31dB respectively Record path high pass enable bit 2 AUDIO HPEN If AUDIO HPEN 0 the digital high pass filter will be b
17. Data Register User can monitor PDR to know current value in 16 bit down counter Nuvoton Technology Corp 188 Revision A1 3 http www nuvoton com nuvoTon NUC501 PWM Interrupt Enable Register PIER PIER PWM_BA 0x040 PWM Interrupt Enable Register 0x0000_0000 31 30 29 28 27 26 235 24 Reserved 23 2 2 2 19 18 17 de Reserved Reserved Reserved Bits Descriptions DEI PWM Timer 3 Interrupt Enable 3 1 Enable 0 Disable PWM Timer 2 Interrupt Enable 2 1 Enable 0 Disable PWM Timer 1 Interrupt Enable 1 1 Enable 0 Disable PWM Timer 0 Interrupt Enable 0 1 Enable 0 Disable Nuvoton Technology Corp 189 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee PWM Interrupt Indication Register PIIR PIR PWM_BA 0x044 PWM Interrupt Indication Register 0x0000_0000 31 30 29 28 27 26 25 2 Reserved 3 22 21 20 19 18 17 16 Reserved Reserved Reserved Bits Descriptions ES PWM Timer 3 Interrupt Flag 1 Interrupt Flag ON O Interrupt Flag OFF PWM Timer 2 Interrupt Flag 1 Interrupt Flag ON O Interrupt Flag OFF PWM Timer 1 Interrupt Flag 1 Interrupt Flag ON O Interrupt Flag OFF PWM Timer O Interrupt Flag 1 Interrupt Flag ON O Interrupt Flag OFF Note User can clear each interrupt flag by writing a zero to corresponding bit in PIIR Nuvoton Technology Corp 190 Revision A1
18. Parity amp count F Istart detect State Definition IDLE The receiver has no data to receive START The receiver receives the start bit RX The receiver receives the desired data PARITY Nuvoton Technology Corp 243 Revision A1 3 http www nuvoton com nuvoTon NUC501 KK lt The receiver receives the parity bit STOP The receiver receives the parity bit Signal Description Start_detect To detect the start of the transfer SIN_syn2 The synchronized input data Count7 The counter of clock equals to 7 CountF The counter of clock equals to F RXDATA_END The data received finished PARITY Receiving the parity bit if needed Nuvoton Technology Corp 244 Revision A1 3 http www nuvoton com nuvoTon NUC501 ee 6 18 6 UART Interface Control Registers Mapping R read only W write only R W both read and write C Only value 0 can be written First set of the UART Interface register Map Channel0 UART_BaseO High Speed B800_C000 Channel1 UART Basel Normal Speed B800 C100 uaar uart ea 0000 R reene Boner Regier DU 0 Undefined UACIER UARI_BA 0x04 R W Interrupt Enable Register DLAB 0 0x0000_0000_ UA DLL UART_BA 0x00 Divisor Latch Register LS DLAB 1 0x0000_0000 UA DLM UART_BA 0x04 Divisor Latch Register MS DLAB 1 0x0000_0000 UA IIR UART BA 0x08 R Interrupt Identification Register 0x8181_8181 UART_BA 0x08 KAL FIFO Control E U
19. UA_DLM UA_DLM UA_BA 0x04 R W Divisor Latch Register MS DLAB 1 0x0000_0000 Reserved Reserved cs I5 I5 O O RCS E ICI Reserved aio ko ik LR Baud Rate Divider High Byte Ir ou Baud Rate Divisor The high byte e a the baud rate divider 7 0 High Byte This 16 bit divider UA_DLM UA_DLL is used to determine the baud rate as follows Baud Rate Crystal Clock 16 Divisor 2 Nuvoton Technology Corp 251 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Interrupt Identification Register UA_IIR UA IIR UA BA 0x08 R Interrupt Identification Register 0x8181 8181 Reserved Reserved Ts IO ILI a Reserved zZ 6 5 4 3 2 3 o Descriptions DI FIFO Mode Enable Status 7 This bit indicates whether the FIFO mode is enabled or not Since the FIFO mode is always enabled this bit always shows the logical 1 when CPU is reading this register RX FIFO Threshold Level Status 6 5 RFTLS These bits show the current setting of receiver FIFO threshold level RTHO The meaning of RTHO is defined in the following UA FCR description Interrupt Identification of RX time out 3 This bit indicates the current interrupt request from RX time out The Rx buffer have data not reach the Rx trigger level but the time out count is equal to TOR 2 0 Interrupt Identification l The IID together with NIP indicates the current interrupt request from UART Nuv
20. and therefore not visible 6 12 5 Software I C Operation The software I C function contains 3 registers for software to control the output enable of pad actually The implementation of software DC is shown bellow Nuvoton Technology Corp 162 Revision A1 3 http www nuvoton com NUVOTON NUC501 SCL_PADOEN O SDA PADOEN O SDO PADOEN O The other two registers SCW and SDW just represent the status of input port scl pin sda pin Software can read write this register at any time but the output enable scl pin and sda pin are controlled by software only when I2C EN 0 Nuvoton Technology Corp 163 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee 6 12 6 I7C Serial Interface Control Registers Mapping R read only W write only R W both read and write Register offset_ R W C Descrption_ Reset Value I2C_BA 0xB800_4000 Cep 12C_BA 0x00 Control and Status Register 0x0000_0000 DIVIDER DC BA 0x04 Clock Pre scale Register 0x0000 0000 CMDR 12C_BA 0x08 Command Register 0x0000_0000 I2C_BA 0x0C Software Mode Control Register 0x0000_003F RXR O I2C_BA 0x10 ORO Data Receive Register 0x0000_0000 12C_BA 0x14 Data Transmit Register 0x0000_0000 NOTE The reset value of SWR is 0x3F only when SCR SDR and SER are connected to pull high resistor Nuvoton Technology Corp 164 Revision A1 3 http www nuvoton com nuvoTon NUC501 A O TT M e _ a _ _ a ann IXXIS AYE
21. e 10 low active edge triggered E e 11 high active edge triggered Interrupts other than INT_EXT can be configured as level triggered during normal operation unless in the test mode 29 27 21 19 R R d 13 11 eserved eserve 5 3 Nuvoton Technology Corp 120 Revision A1 3 http www nuvoton com nuvoTon NUC501 Priority Level 0 7 e The level 0 indicates the highest priority and the level 7 indicates the lowest 26 24 priority 18 16 PRIORITY e An interrupt is treated as a FIQ mode for the priority level 0 and is treated as 11 8 an IRQ mode for other levels 2 0 e If two or more interrupts have the identical priority level the interrupts located in the upper rows of the interrupt source table have higher priorities Nuvoton Technology Corp 121 Revision A1 3 http www nuvoton com nuvoTon NUC501 AIC Interrupt Raw Status Register AIC_IRSR AIC_IRSR AIC_BA 100 MES Interrupt Raw Status Register 0x0000_0000 IRS 7 0 This a records the intrinsic state within each interrupt channel Bits Descriptions Interrupt Status Indicate the intrinsic status of the corresponding interrupt source 31 0 IRSx e O Interrupt channel is in the voltage level 0 e 1 Interrupt channel is in the voltage level 1 Nuvoton Technology Corp 122 Revision A1 3 http www nuvoton com nuvoTon NUC501 AIC Interrupt Active Status Register AIC_IASR AIC_IASR AIC_BA 104 MES Interrupt Active Sta
22. nuvoTon NUC501 SS eee Function Address Register FADDR A seven bit value uses as the address of a device on the USB BUS FADDR USB BA 0x008 R w Function Address 0x0000 0000 MN eee ee Reserved MIC IEA CO CC CS V Reserved Reserved DS O O J o CO OS A Reserved Bits Descipions au 6 0 FADDR Function Address of this USB device Nuvoton Technology Corp 102 Revision A1 3 http www nuvoton com nuvoTon NUC501 System States Register STS STS USB_BA 0x00C R System states 0x0000_00x0 ERIK O ee ee Reserved Bits Descriptions 2000000000000 System states of endpoint 5 000 In ACK 001 In NAK 25 23 STS5 010 Out 0 ACK 110 Out 1 ACK 011 Setup ACK 111 Isochronous translation end System states of endpoint 4 000 In ACK 001 In NAK 22 20 STS4 010 Out 0 ACK 110 Out 1 ACK 011 Setup ACK 111 Isochronous translation end Nuvoton Technology Corp 103 Revision A1 3 http www nuvoton com NUC501 System states of endpoint 3 000 In ACK 001 In NAK 010 Out 0 ACK 110 Out 1 ACK 011 Setup ACK 111 Isochronous translation end 19 17 STS3 System states of endpoint 2 000 In ACK 001 In NAK 010 Out 0 ACK 110 Out 1 ACK O11 Setup ACK 111 Isochronous translation end 16 14 STS2 System states of endpoint 1 000 In ACK 001 In NAK 010 Out 0 ACK 110 Out 1 ACK O11 Setup ACK 111 Isochronous translation end 13
23. spw X scw NOTE This register is used as software mode of I C Software can read write this register no matter I2C EN is O or 1 But SCL and SDA are controlled by software only when I2C EN 0 Bits Descriptions 31 6 Serial Interface SDO Status Read only 5 0 SDO is Low 1 SDO is High Serial Interface SDA Status Read only 4 0 SDA is Low 1 SDA is High Serial Interface SCK Status Read only 3 O SCL is Low 1 SCL is High Serial Interface SDO Output Control 2 O SDO pin is driven Low 1 SDO pin is tri state Serial Interface SDA Output Control 1 O SDA pin is driven Low 1 SDA pin is tri state Serial Interface SCK Output Control O SCL pin is driven Low 1 SCL pin is tri state Nuvoton Technology Corp 169 Revision A1 3 http www nuvoton com nuvoTon NUC501 Pe ria P 1 _ e _ _ __ __ ceeee e e Data Receive Register RxR Register offset R W C Description Jresetvalue RxR Oo O RO Data Receive Register 0x0000_0000 Reserved Reserved ES FE ES E FE ENE O ES Reserved Bits Descriptions 31 8 Data Receive Register 7 0 The last byte received via I C bus will put on this register The I C core only used 8 bit receive buffer Nuvoton Technology Corp 170 Revision A1 3 http www nuvoton com nuvoTon NUC501 Pe ria P 1 _ e _ _ __ __ ceeee e e Data Transmit Register TXR Register offset
24. to 400k bit s in the Fast mode Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a byte by byte basis Each data byte is 8 bits long There is one SCL clock pulse for each data bit with the MSB being transmitted first An acknowledge bit follows each transferred byte Each bit is sampled during the high period of SCL therefore the SDA line may be changed only during the low period of SCL and must be held stable during the high period of SCL A transition on the SDA line while SCL is high is interpreted as a command START or STOP 6 12 2 Feature The I C Master Core includes the following features e AMBA APB interface compatible e Compatible with Philips DC standard support master mode e Multi Master Operation e Clock stretching and wait state generation e Provide multi byte transmit operation up to 4 bytes can be transmitted in a single transfer e Software programmable acknowledge bit e Arbitration lost interrupt with automatic transfer cancellation e Start Stop Repeated Start Acknowledge generation e Start Stop Repeated Start detection e Bus busy detection e Supports 7 bit addressing mode e Fully static synchronous design with one clock domain e Software mode DC Nuvoton Technology Corp 157 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee 6 12 3 1 C Protocol Normally a standard communication consists of four parts 1 STATT or Repeated START signal generation 2 Sl
25. 0xA0 R W Interrupt Latch Trigger Selection Register 0x0000_0000 IRQLHGPA GP_BA 0xA4 R ep Port A Interrupt Latch Value 0x0000 0000 IRQLHGPB GP_BA 0xA8 R ep Port B Interrupt Latch Value 0x0000 0000 IRQLHGPC GP_BA 0xAC R GPIO Port C Interrupt Latch Value 0x0000 0000 IRQO 3 Interrupt Trigger Source Indicator from IRQTGSRCO GP_BA 0xB4 OMA Gorn SEE 0x0000 0000 IROO 3 Interrupt Trigger S Indicator f IRQTGSRCi GP_BA 0xB8 saa a rigger s0urce ERRE a 0000000 Nuvoton Technology Corp 135 Revision A1 3 http www nuvoton com nuvoTon NUC501 emm 6 11 3 GPIO Control Register Description GPIO Port A Bit Output Mode Enable GPIOA_OMD GPIOA OMD GP _BA 0x00 R W GPIO Port A Bit Output Mode Enable 0x0000 0000 Reserved Reserved GPIO Port B Bit Output Mode Enable GPIOB OMD GPIOB OMD GP _BA 0x10 R W GPIO Port B Bit Output Mode Enable 0x0000 0000 Reserved Reserved is 34 3 o 2 di 39 gt Ts Reserved OMD9 OMDS _ o7 6 5 4 j 3 2 j 1 0 OMD7 OMD6 OMD5 OMD4 OMD3 OMD2 OMDi OMDO GPIO Port C Bit Output Mode Enable GPIOC OMD Nuvoton Technology Corp 136 Revision A1 3 http www nuvoton com nuvoTon NUC501 PE ri em e _ IE A d d a _ Ere __ GPIOC OMD GP_BA 0x20 R W eng Port C Bit Output Mode Enable 0x0000 0000 Reserved Reserved Reserved OMD7 ome ORD omba OWDi OWDI omoi ees Descriptions Bit Output Mode Enable 1 GPIO port
26. 2 1 Normal Conversion Mode The normal conversion mode is for general purpose ADC user could use the control register to control the 8 to 1 MUX to select analog input channel start to conversion wait interrupt or polling flag to confirm conversion finished then to read the digital data The conversion time is 50 ADC input clocks for each sample Nuvoton Technology Corp 263 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee 6 19 2 2 Standby mode A standby mode is provided for ADC When the ADC enable bit is cleared to 0 and the ADC clock is disable the ADC enter standby mode In the standby mode the consumed current from AVDD will be less than 5uA Note that the last conversion data is not cleared 6 19 2 3 Voltage detector The architecture of the voltage detector is shown as in the following figure Result Flag Reference Voltage By control the switch sw1 sw2 sw3 sw4 sw5 sw6 sw7 and sw 8 to select the voltage V1 V2 V3 V4 V5 V6 V7 or V8 to be compared to reference voltage which will not be influenced by supply voltage or temperature 6 19 2 4 Recording path The audio recording path converts the audio analog to digital data by means of the ADC hardware When the recording path is in usage other data conversion ADC function can t operate 6 19 3 ADC Control Register Mapping R read only W write only R W both read and write C Only value 0 can be written A
27. 219 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee When transmit write data to device 2 Write the data to be transmitted into Tx0 7 0 When receive read data from device 3 Write OxFFFFFFFF into Tx0 4 Write in CNTRL set SLAVE 1 CLKP 1 Rx NEG 0 Tx NEG 1 Tx_BIT_LEN 0x08 Tx_NUM 0x0 LSB 1 and GO_BUSY 1 to start the transfer and waiting for the slave select input and serial clock input signals from the external master device Wait for interrupt if IE 1 or polling the GO_BUSY bit until it turns to 0 5 Read out the received data from RxO 6 go to 2 to continue another data transfer 6 16 4 SPIMS Serial Interface Control Register Map R read only W write only R W both read and write SPI_BA 0xB800_A000 CNTRL SPIMS_BA 0x00 Control and Status Register 0x0000_0004 DIVIDER SPIMS_BA 0x04 Clock Divider Register 0x0000_0000 SSR SPIMS_BA 0x08 Slave Select Register 0x0000_0000 Rx0 SPIMS BA 0x10 mE Data Receive Register 0 0x0000 0000 RA SPIMS BA 0x14 RI Data Receive Register 1 0x0000_0000 Rx SPIMS BA 0x18 ORO Data Receive Register 2 0x0000_0000 O R3 SPIMS_BA 0x1C R Data Receive Register 3 0x0000 0000 SPIMS BA 0x10 Data Transmit Register 0 0x0000 0000 SPIMS BA 0x14 Data Transmit Register 1 0x0000 0000 Tx2 SPIMS BA 0x18 7w Data Transmit Register 2 0x0000_0000 ODO SPIMS_BA 0x1C Mo Data Transmit Register 3 0x0000_0000 NOTE 1 When softw
28. 3 RX0 0 2 3 R W C Description Reset Value SPIM_BA 0x10 oR Data Receive Register 0 0x0000_0000 SPIM_BA 0x14 ORO Data Receive Register 1 0x0000_0000 SPIM_BA 0x18 ORO Data Receive Register 2 0x0000_0000 SPIM_BA 0x1C ORO Data Receive Register 3 0x0000_0000 Bits Descriptions Data Receive Register The Data Receive Registers hold the value of received data of the last executed transfer Valid bits depend on the transmit bit length field in the CNTRL register For example if CNTRL Tx_BIT_LEN is set to 0x08 and CNTRL Tx_NUM is set to 0x0 bit Rx0 7 0 holds the received data Nuvoton Technology Corp 71 Revision A1 3 http www nuvoton com nuvoTon NUC501 ES ee Data Transmit Register 0 1 2 3 TX0 1 2 3 R W C Description Reset Value SPIM_BA 0x20 Data Transmit Register 0 0x0000_0000 SPIM_BA 0x24 Data Transmit Register 1 0x0000_0000 SPIM_BA 0x28 Data Transmit Register 2 0x0000_0000 SPIM_BA 0x2C Data Transmit Register 3 0x0000_0000 Tx 31 24 Tx 23 16 4 3 135 2 1I s oy ys Tx 15 8 7 5 4 Jj 3 Jj 2 j i J o S Tx 7 0 M xeu AAA Data Transmit Register The Data Transmit Registers hold the data to be transmitted in the next transfer Valid bits depend on the transmit bit length field in the CNTRL 31 0 Tx register For example if CNTRL Tx BIT LEN is set to 0x08 and the CNTRL Tx NUM is set to 0x0 the bit Tx0 7 0 will be transmitted in next transfer If CNTRL Tx BIT LEN is
29. 3 http www nuvoton com nuvoTon NUC501 DZIO Dead Zone Generator pwm clk Dead Zone CNR2 CMR2 PWM2 Control Logic 8 bit Dead Zone Pre scale CP1 CNR3 CMR3 PWM3 gt Control _ y Logic Nuvoton Technology Corp 175 Revision A1 3 http www nuvoton com nuvoTon NUC501 pp 6 13 5 Basic Timer Operation Basic Timer operation SE KKK KEKE Timer output CMP 1 CNR 3 Auto reload 1 CNR 3 Timer enable Auto load Auto load Basic Timer Operation Timing 6 13 6 PWM Double Buffering and Automatic Reload PWM Timers have a double buffering function enabling the reload value changed for next timer operation without stopping current timer operation Although new timer value is set current timer operation still operate successfully The counter value can be written into CNRO 3 and current counter value can be read from PDRO 3 The auto reload operation will copy from CNRO 3 to down counter when down counter reaches zero If CNRO 3 are set as zero counter will be halt when counter count to zero If auto reload bit is set as zero counter will be stopped immediately Nuvoton Technology Corp 176 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee PWM double buffering Reg CNT 150 Reg _CNT 199 Reg CNT 99 Reg CMP 50 Reg CMPz49 Reg CMP 0 Start pwm_out write a nonzero 151 200
30. 3 http www nuvoton com nuvoTon NUC501 SS eee Capture Control Register CCRO CCRO PWM_BA 0x050 R W Capture Control Register 0x0000_0000 31 30 29 23 27 26 235 24 Reserved 33 1 21 2 19 18 17 36 CFLRD1 CRLRDI Reserved CIRI CAPCHIEN FL amp IEi RLSIEL INVI Reserved 7 6 5 4 3 2 1 0 CFLRDO CRLRDO Reserved CIIRO CAPCHOEN FL amp IEO RL amp IEO INVO Descriptions 31 24 CFLR1 dirty bit 23 CFLRD1 When input channel 1 has a rising transition CFLR1 was updated and this bit was 1 CRLR1 dirty bit 22 CRLRD1 When input channel 1 has a falling transition CRLR1 was updated and this bit was 1 E Capture Channel 1 transition Enable Disable 1 Enable 0 Disable 19 When Enable Capture latched the PMW counter and saved to CRLR Rising latch and CFLR Falling latch When Disable Capture does not update CRLR and CFLR and disable Channel 1 Interrupt Channeli Falling Interrupt Enable ON OFF 1 Enable 18 FL amp IE1 0 Disable When Enable if Capture detects Channel 1 has falling transition Capture issues an Interrupt Channel 1 Rising Interrupt Enable ON OFF 1 Enable RL amp IE1 M 2 0 Disable When Enable if Capture detects Channel 1 has rising transition Capture Nuvoton Technology Corp 191 Revision A1 3 http www nuvoton com nuvoTon NUC501 Channel 1 Inverter ON OFF 16 INV1 1 Inverter ON O Inverter OFF
31. 3 or GPB DIN 6 or GPC DIN 5 or GPC DIN 9 Kess Capture channel 3 is from GPB_DIN 0 or GPB_DIN 4 or GPB_DIN 7 or GPC_DIN 6 or GPC_DIN 10 Nuvoton Technology Corp 197 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee PWM Output Enable Register PWM POE PWM_BA 0x07C R W PWM Output Enable Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved Reserved Reserved Descriptions DEI PWM timer 3 Output Enable Setup 3 1 Enable O Disable PWM timer 2 Output Enable Setup 2 1 Enable O Disable PWM timer 1 Output Enable Setup 1 1 Enable O Disable PWM timer O Output Enable Setup 1 Enable O Disable Nuvoton Technology Corp 198 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee 6 15 Real Time Clock RTC 6 15 1 Overview Real Time Clock RTC block can be operated by independent power supply while the system power is off The RTC uses a 32 768 KHz external crystal A built in RTC is designed to generate the periodic interrupt signal The period can be 0 25 0 5 1 2 4 8 second There is RTC overflow counter and it can be adjusted by software 6 15 2 RTC Features e There is a time counter second minute hour and calendar counter day month year for user to check the time Alarm register second minute hour day month year 12 hour or 24 hour mode is selectable
32. 4 3 2 0 GPIO Port B Data Output Value GPIOB_DOUT GPIOB DOUT GP _BA 0x18 R W GPIO Port B Data Output Value 0x0000 0000 Reserved Reserved Loa o3 35 9 8 a Ts TS Ta Ta a T oo GPIO Port C Data Output Value GPIOC_DOUT GPIOC_DOUT GP_BA 0x28 R W GPIo Port C Data Output Value 0x0000 0000 Nuvoton Technology Corp 140 Revision A1 3 http www nuvoton com nuvoTon NUC501 Reserved Reserved 3 34 35 2 S 3 3 EC Reserved DOUT10 DOUT9 DOUT8 NS SS SS TE gt E DOUT7 DOUT6 DOUTS5 DOUT4 DOUT3 DOUT2 DOUT1 DOUTO Descriptions Bit Output Value 1 GPIO port A B C bit n will drive High if the corresponding output mode enabling bit is set O GPIO port A B C bit n will drive Low if the corresponding output mode enabling bit is set Nuvoton Technology Corp 141 Revision A1 3 http www nuvoton com nuvoTon NUC501 EDEM GPIO Port A Pin Value GPIOA _ PIN GPIOA PIN GP BA 0x0C R GPIO Port A Pin Value 0x0000 XXXX Reserved Reserved GPIO Port B Pin Value GPIOB PIN GPIOB PIN GP BA 0x1iC R GPIO Port B Pin Value 0x0000 OXXX Reserved 3 3 3 2 J 9 9 e Reserved a J 6e J 5 4 3 2 i o GPIO Port C Pin Value GPIOC_PIN GPIOC PIN GP BA 0x2C R GPIO Port C Pin Value 0x0000 OXXX Nuvoton Technology Corp 142 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee 35 3 2
33. A B C bit n output mode is enabled the bit value contained in the corresponding bit n of GPIO A B C DOUT is driven on the pin O GPIO port A B C bit n output mode is disabled the corresponding pin is in INPUT mode Nuvoton Technology Corp 137 Revision A1 3 http www nuvoton com nuvoTon NUC501 o GPIO Port A Bit Pull up Resistor Enable GPIOA_PUEN GPIOA PUEN GP_BA 0x04 R W GPIO Port A Bit Pull up Resistor Enable 0x0000 0000 Reserved Reserved GPIO Port B Bit Pull up Resistor Enable GPIOB PUEN GPIOB PUEN GP _BA 0x14 R W PIO Port B Bit Pull up Resistor Enable 0x0000 0000 Reserved Reserved 3 33 5 2 S8 3 3 Reserved GPIO Port C Bit Pull up Resistor Enable GPIOC PUEN GPIOC PUEN GP _BA 0x24 R W GPIo Port C Bit Pull up Resistor Enable 0x0000 0000 Nuvoton Technology Corp 138 Revision A1 3 http www nuvoton com nuvoTon NUC501 Reserved Reserved PUEN7 VENE PUENS PUENA PUENS PUENZ PUENI PUENG Descriptions PUEN n Bit Pull up Resistor Enable 1 GPIO port A B C bit n pull up resistor is enabled O GPIO port A B C bit n pull up resistor is disabled Nuvoton Technology Corp 139 Revision A1 3 http www nuvoton com nuvoTon NUC501 o GPIO Port A Data Output Value GPIOA_DOUT GPIOA_DOUT GP_BA 0x08 R W GPIo Port A Data Output Value 0x0000_0000 Reserved Reserved 35 3 3 o 2 De T_T 7 6s 5
34. Controller 6 7 1 Overview The USB device is an interface that transmits and receives data packets between host and USB device controller It also handles the routing data between the bus interface and various endpoints on the device controller On the device controller it includes the AHB bus and USB bus which comes from the USB PHY transceiver The AHB bus includes the slave interface only and the CPU programs the USB controller registers through it There are 512 bytes internal SRAM as USB buffer in the device controller For IN or OUT transfer the USB device controller needs to write data to SRAM or read data from SRAM through the AHB slave interface or SIE The BUFSEGx define the effective starting address for each endpoint buffer on the SRAM The USB device controller is complaint with USB full speed device and it contains 6 configurable endpoints These endpoints could be configured as IN OUT or ISO state on CFGx 6 4 and the endpoint number can be set on CFGx 3 0 The transmit length in each endpoint is defined in MXPLD Most handshakes between Host and Device are handled by hardware Any USB event will cause an interrupt and user can just check related event flags in EVF to acknowledge the events and store required data into buffer which is then sent to host by hardware A software disable function is also available for this USB device which simulates the disconnection of this device from the host 6 7 2 Features This Universal Se
35. DK TT BUFSEG5 USB_BA 0x070 R W Buffer Segmentation of endpoint 5 0x0000_0000 MXPLD5 USB_BA 0x074 R W Maximal payload of endpoint 5 0x0000 0000 CFG5 USB_BA 0x078 R W Configuration of endpoint 5 0x0000_0000 CFGP5 USB_BA 0x07C R W In ready clear flag of endpoint 5 0x0000 0000 USBSEO USB BA 0x090 R W Set D and D bus to idle state 0x0000 0000 Nuvoton Technology Corp 98 Revision A1 3 http www nuvoton com NUC501 nuvoTon Interrupt Enable Register IEF IEF USB_BA 0x000 R W Interrupt Enable Flag 0x0000_0000 31 30 29 28 27 26 Reserved Reserved Reserved a 1 5 4 3 2 3 Descriptions DEC O Disable IN NAK INT Write Only 15 1 Enable as 8 O Disable USB wakeup function 1 Enable ur 3 O Disable Wakeup Interrupt 1 Enable 2 FLDEN O Disable Floating detect Interrupt 1 Enable 1 O Disable USB event interrupt 1 Enable 0 O Disable BUS event interrupt 1 Enable Nuvoton Technology Corp 99 Revision A1 3 http www nuvoton com NUVOTON NUGSO ee ii Interrupt Event Flag Register EVF This register is USB Interrupt Event Flag register clear by read STS ATTR or FLODET EVF USB BA 0x004 R W Interrupt Event Flag 0x0000_0000 EE L_e ee a ee ACTA Reserved 23 22 21 20 19 18 17 16 EPTF5 EPTF4 EPTF3 EPTF2 EPTF1 EPTFO Reserved pie A Reserved Bits Descriptions 1 Setup event
36. Descriptions OOOO DI RX FIFO Interrupt INTR_RDA Trigger Level vay sem ee Se TX FIFO Reset 2 TFR Setting this bit will generate an OSC cycle reset pulse to reset TX FIFO The TX FIFO becomes empty TX pointer is reset to 0 after such reset This bit is returned to 0 automatically after the reset pulse is generated RX FIFO Reset 1 Setting this bit will generate an OSC cycle reset pulse to reset RX FIFO The RX FIFO becomes empty RX pointer is reset to 0 after such reset This bit is returned Nuvoton Technology Corp 254 Revision A1 3 http www nuvoton com nuvoTon NUC501 BEEN to 0 automatically after the reset pulse is generated FIFO Mode Enable d Because UART is always operating in the FIFO mode writing this bit has no effect while reading always gets logical one This bit must be 1 when other UA_FCR bits are written to otherwise they will not be programmed Nuvoton Technology Corp 255 Revision A1 3 http www nuvoton com nuvoTon NUC501 Line Control Register UA_LCR UA_LCR UA_BA 0x0C Line Control Register 0x0000_0000 Reserved Reserved 5 Te Ts Te ps pe Ts 7 8 Reserved Bits Descriptions Divider Latch Access Bit e O It is used to access UA RBR UA THR or UA IER e 1 It is used to access Divisor Latch Registers UA DLL UA DLMj Break Control Bit When this bit is set to logic 1 the serial data output SOUT is forced to the Spacing State logic 0 This bit acts
37. E E N o Bits Descriptions ES Loop back Mode Enable e 0O Disable e 1 When the loop back mode is enable the following signals are 4 LBME connected internally SOUT connected to SIN and SOUT pin fixed at logic 1 RTS connected to CTS and RTS pin fixed at logic 1 DD RTS Complement version of RTS Request To Send signal Note Only RTS RTS can be used in this version Nuvoton Technology Corp 258 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Line Status Control Register UA_LSR UA_LSR UA_BA 0x14 R Line Status Register 0x6060 6060 Reserved Reserved cs I I IG LS I IL IC Reserved Bits Descriptions RX FIFO Error e 0 RX FIFO works normally 7 e 1 There is at least one parity error PE framing error FE or break indication BI in the FIFO ERR_RX is cleared when CPU reads the UA_LSR and if there are no subsequent errors in the RX FIFO Transmitter Empty e O Either Transmitter Holding Register UA_THR TX FIFO or Transmitter Shift Register TSR are not empty e 1 Both UA_THR and TSR are empty Transmitter Holding Register Empty e O UA_THR is not empty e 1 UA_THR is empty THRE is set when the last data word of TX FIFO is transferred to Transmitter Shift Register TSR The CPU resets this bit when the UA_THR or TX FIFO is loaded This bit also causes the UART to issue an interrupt INTR_THRE to the CPU when UA_IER 1 1 4 BI Break Interrupt
38. GPC 9 General purpose input output digital pin PWMT2 PWM output for timer 2 I2C DATA I2C data input output pin if this pin is select for I2C function GPC 10 General purpose input output digital pin PWMT3 PWM output for timer 3 I2C CLK I2C data output pin if this pin is select for I2C function N N GPC 8 PWMT1 USRT1_RTS N LO D m NI CJ N LA ul D O del E NI kel I kel kel I a x 4 8mA I O GPC 9 PWMT2 I2C DATA NJ Ul a 4 8mA I O GPC 10 PWMT3 I2C CLK N OD 4 8mA I O O used for SPI memory 39 32 1 0 40 33 45 35 46 36 4 35 28 4 X32KO nRESET RTC 32 768KHz crystal output pin External reset input Low active set this pin low reset the NUC501 to the chip initial state 36 29 4 50 51 57 58 5 6 19 17 12 14 70 71 54 42 AO 53 Al AO VREF 71 55 43 AO Nuvoton Technology Corp 17 Revision A1 3 http www nuvoton com nuvoTon NUC501 A 38 12 31 3 3V power supply for I O ports and LDO 21 22 32 38 source for internal PLL and digital circuit AVDD33 I LIEN 3 3V power supply for internal analog circuit VBAT HE SE E MM 1 8V Power supply for internal RTC circuit VCC CORE 65 66 20 LDO 1 8V output pin LDO 1 8Voutputpin_ VPP 52 40 OTP 6 5V VPP pin For OTP write this pin supply is 6 5V for read this pin supply is 1 8V DVSS 18 41 13 34 Ground Pin for digital circuit 49 37 een Gr
39. Je Is gt 12 Reserved Descriptions ADC clock source select 00 clock source from crystal clock in 15 14 01 clock source from divided MPLL clock 1x clock source from divided MPLL clock 2 UART clock source select 00 clock source from crystal clock in 7 6 UART_S 01 clock source from divided MPLL clock 1x clock source from divided MPLL clock 2 Audio Process Unit clock source select 00 clock source from crystal clock in 5 4 01 clock source from divided MPLL clock 1x clock source from divided MPLL clock 2 USB clock source select 00 clock source from crystal clock in 3 2 01 clock source from divided MPLL clock 1x clock source from divided MPLL clock 2 Nuvoton Technology Corp 52 Revision A1 3 http www nuvoton com 1 0 HCLK_S nUvoTon HCLK clock source select 1 0 00 clock source from crystal clock in 01 clock source from divided MPLL clock 10 clock source from divided MPLL clock 2 11 clock source from crystal 32k input Nuvoton Technology Corp 53 http www nuvoton com NUC501 Revision A1 3 nuvoTon NUC501 SS eee Clock Divider RegisterO CLKDIVO CLKDIVO CLK BA 4 14 R W Clock Divider Number Register 0x0000_0000 Reserved 31 24 Reserved 0000000000000 23 20 USB in ____ _ 1 rr divide number from USB clock source The USB clock frequency USB clock source frequency USB_N 1 19 16 UART_N UART clock divide nu
40. Reg _CNT 0 Reg CMPzXX Stop 100 number to prescaler amp setup clock dividor PWM Double Buffering Illustration 6 13 7 Modulate Duty Ratio The double buffering function allows CMR written at any point in current cycle The loaded value will take effect from next cycle Nuvoton Technology Corp 177 http www nuvoton com Revision A1 3 nuvoTon NUC501 SS eee Modulate PWM controller ouput duty ratio CNR 150 101 31 1 Write Write Write CMR 100 CMR 50 CMR 0 1 PWM cycle 151 1 PWM cycle 151 1 PWM cycle 151 PWM Controller Output Duty Ratio 6 13 8 Dead Zone Generator PWM is implemented with Dead Zone generator They are built for power device protection This function enables generation of a programmable time gap at the rising of PWM output waveform User can program PPR 31 24 and PPR 23 16 to determine the two Dead Zone interval respectively Nuvoton Technology Corp 178 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Dead zone generator operation PWM out PWM out1 n PWM oul DZ H H A i PWM out n DZ H Dead zone interval Dead Zone Generation Operation 6 13 9 PWM Timer Start Procedure UM Setup clock selector CSR 2 Setup prescale amp dead zone interval PPR 3 Setup inverter on off dead zone generator on off toggle mode one shot mode and PWM ti
41. SSR register to un select spi slave no support ASS in dma mode 10 Check the BUSY status in SPI Flash O0OPONDUAWNEO 6 4 6 Direct memory mapping mode Users can see SPI flash as a ROM when in direct memory mapping mode This controller will convert the AHB cycle to SPI flash without CPU setting related SPI command The only setting CPU needs to do is Nuvoton Technology Corp 60 Revision A1 3 http www nuvoton com nuvoTon NUC501 EY to disable AHB master function CNTRL DIS_M high disable flash data read CNTRL F_DRD low set sleep interval to 1 CNTRL SLEEP 4 h1 and set SPI flash read command CNTRL SPI MODE 0x03 OxOb or Ox3b Then users can access SPI flash as a ROM module Direct memory mapping mode supports these following modes Standard Read Set CNTRL 0x0332_1344 Fast Read Set CNTRL 0x0b32_1344 Fast dual Read Set CNTRL 0x3b32_1344 Note1 In direct memory mapping mode the SPI flash IP will pre fetch 4 word flash data after a direct memory mapping access If users want to change the control registers CNTRL SSR DIVIDER Tx Rx after the direct mapping access remember to check the busy state GO_BUSY 0 Note2 Sleep interval CNTRL SLEEP can t set to zero when DIVIDER is zero Nuvoton Technology Corp 61 Revision A1 3 http www nuvoton com nuvoTon NUC501 E 6 4 7 SPIM Serial Interface Control Registers Mapping R read only W write only R W both read and write C Only value 0 can
42. The following table shows the main steps of an interrupt and the order in which they are performed according to the mode Nuvoton Technology Corp 117 Revision A1 3 http www nuvoton com nuvoTon NUC501 Calculate active interrupt Read AIC_IPER Read AIC_IPER D j h f GA return the vector o Read AIC_IPER Read AIC_IPER the active interrupt i k th PUSH internal stack the current Read AIC IPER Write AIC IPER priority level Acknowledge the interrupt Note 1 Read AIC IPER Write AIC IPER No effect Note 2 Read AIC IPER EN e NIRQ de assertion and automatic interrupt clearing if the source is programmed as level sensitive Notes e Note that software which has been written and debugged using this mode will run correctly in normal mode without modification However in normal mode writing to AIC IPER has no effect and can be removed to optimize the code 6 10 5 AIC Registers Mapping AIC BA 0xB800_ 2000 DEENEN AIC SCR2 WC pg Lu Source Control Register2 ox4747_4747 AIC SCR3 WC Bun R W Source Control Registers 0x4747_4747 AIC SCR4 AIC_BA 00C R W Source Contro Register 4 ox4747_4747 AIC SCRS AIC_BA 010 R W Source Control Registers 0x4747_4747 AIC SCRG WC pg R W Source Control Register6 0X4747 4747 ATC_IRSR AIC_BAvI00 R interrupt Raw Status Register T0x0000_0000 AIC IASR Cam R interrupt Active Status Register 0x0000_0000 AIC_ISR Cam R interrupt Status Register 0x0000_0000 AIC_IPER AIC_BA 1
43. Timer 1 Inverter ON OFF 10 CH1INV 1 Inverter ON 0 Inverter OFF Timer 1 Enable Disable 8 1 Enable 0 Disable 7a Dead Zone 1 Generator Enable Disable 5 1 Enable 0 Disable Dead Zone 0 Generator Enable Disable 4 1 Enable 0 Disable Timer 0 Toggle One Shot Mode 1 Toggle Mode 3 0 One Shot Mode NOTE If there is a rising transition at this bit it will cause CNRO and CMRO be clear Timer O Inverter ON OFF 2 CHOINV 1 Inverter ON O Inverter OFF Timer O Enable Disable 0 1 Enable 0 Disable Nuvoton Technology Corp 185 Revision A1 3 http www nuvoton com nuvoTon NUC501 PWM Counter Register 3 0 CNR3 0 CNRO PWM_BA 0x00C R W PWM Counter Register 0 0x0000_0000 CNR1 PWM_BA 0x018 R W PWM Counter Register 1 0Ox0000 0000 CNR2 PWM_BA 0x024 R W PWM Counter Register 2 0Ox0000 0000 CNR3 PWM_BA 0x030 R W PWM Counter Register 3 0Ox0000 0000 31 30 29 28 27 26 235 24 Reserved Ti CH AS AAA AS ee EN Reserved NAS SI A E SA CNR 7 0 Descriptions 3116 PWM Counter Timer Loaded Value Inserted data range 655350 Unit 1 PWM clock cycle 15 0 Note One PWM cycle width CNR 1 1 If CNR equal zero PWM counter timer will be stopped Note Programmer can feel free to write a data to CNR at any time and it 2 will take effect in next cycle Nuvoton Technology Corp 186 Revision A1 3 http www nuvoton com nuvoT
44. Watchdog Timer reset function is enabled and the Watchdog Timer is not being reset before timing out then the Watchdog Timer reset is activated after 1024 WDT clock cycles Interrupt timeout Setting WTE in the register WTCR enables the Watchdog Timer The WTR should be set before making use of Watchdog Timer This ensures that the Watchdog Timer restarts from a know state Watchdog Timer will start counting and timeout after a specified period of time The timeout interval is selected by two bits WTIS 1 0 The WTR is self clearing i e after setting it the hardware will automatically reset it When timeout occurs Watchdog Timer interrupt flag is set Watchdog Timer waits for an additional 1024 WDT clock cycles before issuing a reset signal if the WTRE is set The WTRF will be set and the reset signal will last for 16128 WDT clock cycles long When used as a simple timer the interrupt and reset functions are disabled Watchdog Timer will set the WTIF each time a timeout occurs The WTIF can be polled to check the status and software can restart the timer by setting the WTR The Watchdog Timer can be put in the test mode by setting WTTME in the register WTCR Nuvoton Technology Corp 228 Revision A1 3 http www nuvoton com NUVOTOM NUC501 pp WTCLK Prescale Counter wdt_int_o wdt_rst_n 16128 Clocks WTIS 1 0 gt Delay WTRE Watchdog Timer Block Diagram Counter Ol 1 2 Ind n oldes Wdt init tinit gt
45. access a device with following specifications e Data is transferred with the MSB first e Only one byte transmits receives in a transfer e Chip select signal is active low You should do following actions basically you should refer to the specification of device for the detailed steps 1 Write a divisor into DIVIDER to determine the frequency of serial clock 2 Write in SSR set ASS 0 SS_LVL 0 and SSR 0 to 1 to activate the device you want to access When transmit write data to device 3 Write the data you want to transmit into Tx0 7 0 When receive read data from device 4 Write in CNTRL Tx_BIT_LEN 0x08 Tx NUM 0x0 LSB 0 SLEEP 0x1 and GO BUSY 1 to start the transfer Wait for interrupt or polling the GO BUSY bit until it turns to O 5 Read out the received data from RxO in received mode 6 Go to 3 to continue data transfer or set SSR 0 to 0 to inactivate the device Nuvoton Technology Corp 59 Revision A1 3 http www nuvoton com nuvoTon NUC501 ee 6 4 5 SPIM Programming Example with DMA If users want to access a device with DMA function 3 additional registers need to be configured They are CODE_LEN AHB_ADDR and SPI_ADDR DMA function can be used to support loading boot code reading data from system memory into peripherals or copy data from peripherals reading data from peripherals into system memory Users must define the length and destination and hardware will automatically move the d
46. at buffer3 Read Only SEH EE 16 bit digital audio data in 2 s compliment format Nuvoton Technology Corp 276 Revision A1 3 http www nuvoton com NUVOTON NS TT 7 Electrical Characteristics 7 1 Absolute Maximum Ratings Ambient temperature O C 105 C Storage temperature 40 C 125 C Voltage on any pin 0 3V 5 5V Power supply voltage Core logic 0 5V 2 5V Power supply voltage IO Buffer 0 5V A DN Injection current latch up testing 100mA Crystal Frequency AMHz 20MHz 7 2 DC Specifications _ Parameter Condition Min Typ Max unit Voss IO Post Driver Voltage ji 3 00 3 30 3 60 v 18 Ven 1 5 1 8 VCC CORE Core Logic Pre Driver Voltage 162 180 198 V Vu 03 08 V Vw InputHigh Voltage 55 v V threshold Point 130 136 142 v V Schmitt trig Low to High threshold point 1 51 1 56 1 60 V ve Schmitt trig High to Low threshold point 1 15 121 125 v lc Supply Current FCPU 81MHz 27 mA 1 uU uA mA mA mA mA mA mA KO lt lt lt ela e Output High Voltage Io 4 8 12 mA 2 4 Low Level Output Current sma Na oav 8 a SES 1 1 ua Output Low Voltage I 4 812mA 2 4 o v 4 Low Level Output Current 4mA Vor 0 4V Tot 7 3 AC Specifications 7 3 1 Audio DAC Characteristic Nuvoton Technology Corp 277 Revision A1 3 http www nuvoton com NUVOT
47. by writing 1 to the interrupt flag The active level of device slave select signal can be chosen to low active or high active which depends on the peripheral it s connected Writing a divisor into DIVIDER register can program the frequency of serial clock output to peripherals This controller contains four 32 bit transmit receive buffers and can provide 1 to 4 burst mode operation The maximum bits can be transmitted received is 32 bits in each transaction and can transmit receive data up to four successive transactions in one transfer 6 4 2 Features AMBA AHB interface compatible Support SPI master mode Variable length of transaction bits up to 32 bits Provide burst mode operation transmit receive transaction can be executed up to four times in one transfer MSB or LSB first transaction 2 slave device select lines SPIMO_SS is a dedicated I O However SPIM1 needs a GPIO pin to be SPIM1_SS and it can t be configured as auto select to perform DMM or DMA mode Fully static synchronous design with one clock domain Nuvoton Technology Corp 58 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee 6 4 3 SPIM Timing Diagram The timing diagram of SPI transaction is shown as following Spi Ss O ue MSB LSB misi hen eo MILL CNTRL LSB 0 CNTRL Tx_NUM 0x0 CNTRL Tx_BIT_LEN 0x08 CNTRL Tx_NEG 1 CNTRL Rx_NEG 0 SSR SS LVL 0 SPI Timing 6 4 4 SPIM Programming Example without DMA If you want to
48. each memory block is 2KB Each memory block could be randomly mapped to any 2KB space of 0x0000_0000 Ox1FFF_FFFF of system memory by modifying the control register Each 2KB memory block could also be disabled individually by modifying control register By default these 16 2KB memory blocks are all enabled and mapped to 0x0000 0000 0x0000 7FFF sequentially 6 6 2 Features e Support 1 AHB slave interface e Support 16 separated 2KB memory block and SRAM size is up to 32KB e Support random memory address mapping in 2KB space of 0x0000 0000 Ox1FFF_FFFF of system memory Nuvoton Technology Corp 87 Revision A1 3 http www nuvoton com NUVOTON NUCSO1 O ___ 0 A ALaA AO ii 6 6 3 SRAM Block Diagram The block diagram of SRAM Controller is depicted as following AHB Bus AHB Slave Wrapper I O Decoder TAG Control Register Nuvoton Technology Corp 88 Revision A1 3 http www nuvoton com NUVOTON NUGSO TT 6 6 4 SRAM System Diagram The following diagram briefs the related circuit with SRAM Controller AHB Bus E clock SRAM Controller MESE Controller Controller Nuvoton Technology Corp 89 Revision A1 3 http www nuvoton com NUVOTON NUCSO1 ee ii 6 6 5 SRAM Function Description It s an AHB slave and SRAM size is up to 32KB The 32KB memory is separated into 16 memory block and the size of each memory block is 2KB Each memory block could be randomly mapped to any 2KB spa
49. effect e 1 Reset the contents of the Watchdog timer NOTE This bit will auto clear after few clock cycle 238 Revision A1 3 nuvoTon NUC501 SS eee 6 18 UART Interface Controller 6 18 1 Overview The UART interface controller module includes two channels UARTO UARTR1 One of them is equipped with flow control function High Speed UART and the other is a Normal Speed UART The Universal Asynchronous Receiver Transmitter UART performs a serial to parallel conversion on data characters received from the peripheral and a parallel to serial conversion on data characters received from the CPU There are six types of interrupts they are transmitter FIFO empty interrupt Int_THRE receiver threshold level reaching interrupt Int_RDA line status interrupt overrun error or parity error or framing error or break interrupt Int_RLS time out interrupt Int_Tout MODEM status interrupt Int Modem and Wake up status interrupt Int_WakeUp The two UART Interface Controller that one have a 64 byte transmitter FIFO TX FIFO and a 64 byte plus 3 bit of error data per byte receiver FIFO RX FIFO has been built in to reduce the number of interrupts presented to the CPU and the other have a 16 byte transmitter FIFO TX FIFO and a 16 byte plus 3 bit of error data per byte receiver FIFO RX FIFO has been built in to reduce the number of interrupts presented to the CPU The CPU can completely read the status of the UART at any time dur
50. for the duration of the transmit receive and will be driven to inactive state for the rest of the time The active level of spi_ss_o is specified in SSR SS_LVL NOTE This interface can only drive one device slave at a given time Therefore the slave select of the selected device must be set to its active level before starting any read or write transfer NOTE spi_ss_o is also defined as device slave select input spi_ss_i Nuvoton indie _ _xl ld zq eee a Corp 224 Revision A1 3 http www nuvoton com nuvoTon NUC501 signal in slave mode And that the slave select input spi_ss_i must be driven by edge active trigger which level depend on the SS_LVL setting otherwise the SPI slave core will go into dead path until the Nuvoton Technology Corp http www nuvoton com edge active trigger again or reset the SPI core by software 223 Revision A1 3 nuvoTon NUC501 Data Receive Register RX SPIMS_BA 0x10 RO Data Receive Register 0 0x0000_0000 SPIMS_BA 0x14 ORO Data Receive Register 1 0x0000_0000 SPIMS_BA 0x18 ORO Data Receive Register 2 0x0000_0000 SPIMS_BA Ox1C ORO Data Receive Register 3 0x0000_0000 Bits Descriptions Data Receive Register The Data Receive Registers hold the value of received data of the last executed transfer Valid bits depend on the transmit bit length field in the CNTRL register For example if CNTRL Tx_BIT_LEN is set to 0x08 and CNTRL Tx_NUM is set to 0x0 bit Rx0 7 0 hold
51. from LOW to HIGH Nuvoton Technology Corp 47 Revision A1 3 http www nuvoton com nuvoTon NUC501 Crystal Pre Divide Control for Wake Up from Power Down Mode The chip will XIN CTL delay 256 Pre scale cycles after the reset signal to wait the Crystal to stable 1 Enable the pre scale counter O Disable the pre scale assume the crystal is stable Crystal Oscillator Power Down Control XTAL_EN 1 Crystal oscillation enable Normal operation 0 Crystal oscillation disable Power down Nuvoton Technology Corp 48 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee AHB Devices Clock Enable Control Register AHBCLK These register bits are used to enable disable clock for AMBA clock AHB engine and peripheral AHBCLK CLK_BA 04 R W AHB Devices Clock Enable Control Register 0x0000 0083 e AT ATRAPAR A O LE BE ee ee LEE ee eee ZE Bits Descriptions APU Clock Enable Control 8 O Disable SPI FLASH ROM Controller Clock Enable Control SPIMO amp SPIM1 7 O Disable USB Device Clock Enable Control 6 O Disable APB Clock Enable Control 1 APB_CK_EN 0 Disable 1 Enable Nuvoton Technology Corp 49 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS EEE APB Devices Clock Enable Control Register APBCLK These register bits are used to enable disable clock for APB engine and peripheral APBCLK CLK_BA 08 R W APB Devices Clock Enable Control Register 0x
52. hour time scale selection depends on TSSR bit 0 Day of the week counter Count from Sunday to Saturday Time tick interrupt RTC block use a counter to calibrate the time tick count value When the value in counter reaches zero RTC will issue an interrupt RTC register property When system power is off but RTC power is on data stored in RTC registers will not lost except RIER and RIIR Because of clock difference between RTC clock and system clock when user write new data to any one of the registers the register will not be updated until 2 RTC clocks later 60us Hence programmer should consider about access sequence between TSSR TAR and TLR In addition user must be aware that RTC block does not check whether loaded data is out of bounds or not RTC does not check rationality between DWR and CLR either Note 1 TAR CAR TLR and CLR registers are all BCD counter Nuvoton Technology Corp 200 Revision A1 3 http www nuvoton com nuvoTon NUC501 E 2 Programmer has to make sure that the loaded values are reasonable For example Load CLR as 201a year 13 month 00 day or CLR does not match with DWR etc 3 Reset state AER OCRTC read write dial car oyoyo TSSR 1 24 hr mode DWR Je Saturday 4 FCR Calibration Example 1 Frequency counter measurement 32773 65Hz gt 32768 Hz Integer part 32773 gt 0x8005 FCR int 0x05 0x01 0x08 OxOc Fraction part 0
53. http www nuvoton com nuvoTon NUC501 SLEEP Oxf 17 SCLK clock cycle Clock Polarity O The serial clock output spi_sclk_o idle low 1 The serial clock output spi_sclk_o idle high 11 10 9 8 7 3 2 1 0 Tx_BIT_LEN Tx NEG GO BUSY Send LSB First O The MSB is transmitted received first which bit in TXX RxX register that is depends on the Tx BIT LEN field in the CNTRL register 1 The LSB is sent first on the line bit TxX 0 and the first bit received from the line will be put in the LSB position in the Rx register bit RxX 0 Transmit Receive Numbers This field specifies how many transmit receive numbers should be executed in one transfer 00 Only one transmit receive will be executed in one transfer 01 Two successive transmit receive will be executed in one transfer 10 Three successive transmit receive will be executed in one transfer 11 Four successive transmit receive will be executed in one transfer Transmit Bit Length This field specifies how many bits are transmitted in one transmit receive Up to 32 bits can be transmitted Tx BIT LEN 0x01 1 bit Tx BIT LEN 0x02 2 bits Tx BIT LEN Ox1f 31 bits Tx BIT LEN 0x00 32 bits Data Transmit On Negative Edge O The spi so o signal is changed on the rising edge of spi sclk o in master mode or spi sclk i in slave mode 1 The spi so o signal is changed on
54. i iii IP Reset Control Register IPRST This register provides specific read only information for software to identify this chip IPRST GCR_BA 14 IP Reset Control Resister 0x0000 0000 Reserved TET TS a 3 ae IC NI EC E CI Descriptions SPIMS Reset 30 SPIMS RST 0 Normal operation 1 IP reset ADC Reset 28 ADC RST 0 Normal operation 1 IP reset GPIO Reset 27 GPIO RST 0 Normal operation 1 IP reset SRAM Controller Reset 25 SRAM RST 0 Normal operation 1 IP reset Nuvoton Technology Corp 33 Revision A1 3 http www nuvoton com nuvoTon 16 APU_RST NUC501 APU controller Reset 0 Normal operation 1 IP reset USB Device controller Reset 0 Normal operation 1 IP reset SPIMO and SPI1 controller Reset 0 Normal operation 1 IP reset I2C controller Reset 0 Normal operation 1 IP reset PWM controller Reset 0 Normal operation 1 IP reset Timer and Watch Dog controller Reset 0 Normal operation 1 IP reset 4 21 UARTI1 controller Reset 0 Normal operation 1 IP reset UARTO controller Reset 0 Normal operation 1 IP reset Nuvoton Technology Corp http www nuvoton com 34 Revision A1 3 nuvoTon NUC501 EE i iii AHB Control Register AHB_CTRL AHB CTRL GCR_BA 0x20 R W AHB Control Register 0x0000 0000 Reserved Reserved cs o4 35 1 3 s 3 1 3 3 Reserved
55. no write access to the TxX register is executed between the transfers 221 Revision A1 3 nuvoTon NUC501 gl eee 6 17 TIMER Controller 6 17 1 General Timer Controller The timer module includes two channels TIMERO TIMER1 which allow you to easily implement a counting scheme for use The clock source of timer is always the external crystal input clock i e the TCLK speed is dependent on the external crystal clock speed The timer can perform functions like frequency measurement event counting interval measurement clock generation delay timing and so on The timer possesses features such as adjustable resolution programmable counting period and detailed information The timer can generate an interrupt signal upon timeout or provide the current value of count during operation The general TIMER Controller includes the following features e AMBA APB interface compatible e Each channel with a 8 bit pre scale counter 32 bit counter and an interrupt request signal e Independent clock source for each channel TCLKO TCLK1 e Maximum uninterrupted time 1 25 MHz 2 8 2432 if TCLK 25 MHz 6 17 2 Watchdog Timer The purpose of Watchdog Timer is to perform a system restart after the software running into a problem This prevents system from hanging for an indefinite period of time It is a free running timer with programmable timeout intervals When the specified time interval expires a system reset can be generated If the
56. occurred cleared by read register STS or write 1 to 131 EVF 31 1 USB event occurred check RISALE to know SEH kind of USB event was occurred cleared by read register STS or write 1 to EVF 21 1 USB event occurred check E to know RICA kind of USB event was occurred cleared by read register STS or write 1 to EVF 20 1 USB event occurred check SE to know Nen kind of USB event was occurred cleared by read register STS or write 1 to EVF 19 1 USB event occurred check BIST to know iL kind of USB event was occurred cleared by read register STS or write 1 to EVF 18 1 USB event occurred check ia ed to know vaca kind of USB event was occurred cleared by read register STS or write 1 to EVF 17 16 EPTFO 1 USB event occurred check STSX 2 0 to know which kind of USB event was occurred cleared by read register STS or write 1 to EVF 16 asa 1 waue Wake up event occurred cleared by write 1 to EVF 3 Nuvoton Technology Corp 100 Revision A1 3 http www nuvoton com nuvoTon Nuvoton Technology Corp http www nuvoton com NUC501 Floating detect event occurred cleared by write 1 to EVF 2 USB event occurred check STS 6 4 or STSO 5 2 0 to know which kind of USB event was occurred cleared by write 1 to EVF 1 or EPTFO 5 and Setup 0 Bus event occurred check ATTR 3 0 to know which kind of bus event was occurred cleared by write 1 to EVF O 101 Revision A1 3
57. only but can be cleared by writing 1 to this bit Suspend Interval These four bits provide the configuration of suspend interval between two successive transmit receive in a transfer The default value is 0x0 When CNTRL Tx_NUM 00 setting this field has no effect on transfer The desired interval is obtained according to the following equation from the last falling edge of current sclk to the first rising edge of next sclk 15 12 SLEEP Nuvoton Technology Corp 64 Revision A1 3 http www nuvoton com NUC501 CNTRL SLEEP 2 period of SCLK SLEEP 0x0 2 SCLK clock cycle SLEEP 0x1 3 SCLK clock cycle SLEEP Oxe 16 SCLK clock cycle SLEEP Oxf 17 SCLK clock cycle Note SLEEP can t set to zero when DIVIDER is zero 11 incon Dumm This bit is used to insert a dummy phase in SPI flash fast dual 7 y read fast read mode when in DMA mode Send LSB First e 0 The MSB is transmitted received first which bit in TxX RxX register 10 LSB that is depends on the Tx_BIT_LEN field in the CNTRL register e 1 The LSB is sent first on the line bit TxX 0 and the first bit received from the line will be put in the LSB position in the Rx register bit RxX 0 Transmit Receive Numbers This field specifies how many transmit receive numbers should be executed in one transfer 9 8 Tx NUM 00 Only one transmit receive will be executed in one transfer 01 Two successive transmit receive will be execute
58. set to 0x00 and CNTRL Tx NUM is set to 0x3 the core will perform four 32 bit transmit receive successive using the same setting the order is Tx0 31 0 Tx1 31 0 Tx2 31 0 Tx3 31 0 Nuvoton Technology Corp 72 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee AHB Address Register AHB_ADDR eg Description Reset Value AHB ADDR SPIM_BA 0x30 R W _ AHB address Register 0x0000 0000 Bits Descriptions SO l AHB address E Ane ER This ts the system memory address when in DMA mode Nuvoton Technology Corp 73 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Code Length Register CODE_LEN R W C pescipon Reset Valus CODE LEN SPIM BA 0x34 R W Code length Register 0x0000 0000 Reserved Bits Descriptions ooo 31 24 23 0 CODE LEN Code length data length when users want to use DMA function Nuvoton Technology Corp 74 Revision A1 3 http www nuvoton com NUC501 nuvoTon SPI Flash Start Address Register SPIM_ADDR R W C Description Reset Valu SPIM ADDR SPIM BA 0x40 R W _ SPI Flash Start Address Register 0x0000_0000 Reserved SPIM_ADDR 15 lao la 2 ft SPIM_ADDR y le bp kB Pp J PpDplo SPIM_ADDR Bits Descriptions 31 24 i SPI Flash start access address ee PECADOR Note SPI Flash starting address must be word alignment 1 0 Reserved Nuvoton Technology Corp 75 Revision A1 3 http www nuvoton com nUvoTon NU
59. the falling edge of spi sclk o in master mode or spi sclk i in slave mode Data Receive On Negative Edge O The spi si i signal is latched on the rising edge of spi sclk o in master mode or spi sclk i in slave mode 1 The spi si i signal is latched on the falling edge of spi sclk o in master mode or spi sclk i in slave mode Go and Busy Status O Writing O to this bit has no effect 1 Writing 1 to this bit to start the transfer This bit remains set during the transfer and is automatically cleared after transfer finished NOTE All registers should be set before writing 1 to the GO BUSY bit in the CNTRL register When a transfer is in progress writing to any register of the SPI master slave core has no effect Nuvoton Technology Corp http www nuvoton com 227 Revision A1 3 nuvoTon NUC501 Divider Register DIVIDER DIVIDER SPIMS_BA 0x04 R W Clock Divider Register 0x0000_0000 31 30 29 28 27 26 235 24 Reserved 23 2 2 2 19 18 17 de Q Reserved DIVIDER 15 8 ESSE ee Se SE eee Ee eee DIVIDER 7 0 Bits Descriptions 31 16 Clock Divider Register master only The value in this field is the frequency divider of the system clock PCLK to generate the serial clock on the output spi_sclk_o The desired frequency is 15 0 DIVIDER obtained according to the following equation fa Ton DIVIDER 1 2 NOTE Suggest DIVIDER should be at least 1 Nuvoton
60. the trigger source to generate x PCxTG interrupt to the IRQ IRQO IRQ3 selected by IRQLHSEL 4 Write 1 to the bit x will clear the correspond interrupt source Where x 0 15 NOTE The trigger source will be latched when the corresponding rising or falling trigger enable is setup and the pin state toggle is recognized through de bounce or without de bounce no matter whether the source is an input or output pin Other NOTE for related setup NOTE1 For the AIC s normal functionality to be triggered by external IO interrupt the external IRQ source settings for IRQ0 1 2 3 can only be set as positive edge see AIC_SCRxx bit7 6 SRCTYPE NOTE2 For power down wake up setting in order to keep normal wake up functionality the wake up source polarity should be set as positive level see IRQWAKECON bit7 4 IRQWAKEUPPOL Nuvoton Technology Corp 156 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee 6 12 I2C Synchronous Serial Interface 6 12 1 Overview DC is a two wire bi directional serial bus that provides a simple and efficient method of data exchange between devices The I C standard is a multi master bus with integrated addressing and data transfer protocols It includes collision and arbitration loses detection that prevents data corruption if two or more masters attempt to control the bus simultaneously Serial 8 bit oriented bi directional data transfers can be made up to 100k bit s in Standard mode up
61. this change is not desired for example a noise on floating detect pin no interrupt but wakeup interrupt will occur After USB wakeup this interrupt will occur when no other USB interrupt events are present for more than 20mS USB interrupt is to notify users of any USB event on the bus and a user can read SFR STSX and EPTF to acknowledge what kind of request is to which endpoint and take necessary responses Same as USB interrupt BUS interrupt notifies users of some bus events like USB reset suspend timeout and resume A user can read SFR ATTR to acknowledge bus events 6 7 3 6 Power Saving USB turns off PHY automatically to save power while NUC501 enter power down mode Furthermore a user can write 0 into SFT ATTR 4 to turn off PHY under special circumstances like suspend to save power 6 7 4 Memory Mapping Adres ss te pescripion USB_BA 256 Bytes Register Special function register 000h OFFh USB_BA 256 Bytes SRAM USB buffer 100h 1FFh Nuvoton Technology Corp 96 Revision A1 3 http www nuvoton com NUVOTON dll TT 6 7 5 USB Control Registers Mapping EVE USB_BA 0x004 _R_ interupt Event feg_____ 0x0000_0000 FLODET USB_BA 0x014 _R_ Moating det 0x0000_0000 AAA Il control register and in out ready clear fl CFGPO USB_BA 0x02C R w Stal control register and In out ready clear flag o 20099 0000 of endpoint 0 BUFSEG1 USB_BA 0x030 R W Buffer Segmentation of endp
62. 0 SCCx e O No effect e Deactivates the corresponding interrupt channels Nuvoton Technology Corp 132 Revision A1 3 http www nuvoton com nuvoTon NUC501 AIC End of Service Command Register AIC_EOSCR AIC_EOSCR AIC_BA 130 End of Service Command Register Undefined This register is used by the interrupt service routine to indicate that it is completely served Thus the interrupt handler can write any value to this register to indicate the end of its interrupt service Descriptions E ma ao OOO ooo Nuvoton Technology Corp 133 Revision A1 3 http www nuvoton com nuvoTon NUC501 Zu AAA 1A IN A A A Aiiiiliiziiii 5 P21 I a e 6 11 General Purpose I O 6 11 1 Overview and Features 26 pins for 48 pins package and 37 pins for 64 pins package and COB of General Purpose I O are Shared with special feature functions Supported Features of these I O are input or output facilities pull up resistors All these general purpose I O functions are achieved by software programming setting And the following figures illustrate the control mechanism to achieve the GPIO functions Clock l Controller l Wakeup INT cPIO o 3 i l External Interrupt Controller GPIO 1 Controller Debounce Counter Nuvoton Technology Corp 134 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee 6 11 2 GPIO Control Register Mapping
63. 0000 0007 Reserved 5 5 I9 I I 5 Tope 8 reserved acc seins e en 7 ys DST 3 TT po0 gt Reserved ac cic en pwm cx en uanra_cx_en uarro_cx en arco en wo cx en rimer cen Bits Descriptions Analog Digital Converter Clock Enable Control 9 O Disable 1 Enable SPI master amp slave Clock Enable Control 8 O Disable I2C Clock Enable Control O Disable 1 Enable PWM_0 channel 3 0 Clock Enable Control O Disable 1 Enable UART1 Clock Enable Control 4 UART1_CK_ENO Disable 1 Enable UARTO Clock Enable Control 3 UARTO_CK_ENO Disable 1 Enable Nuvoton Technology Corp 50 Revision A1 3 http www nuvoton com nuvoTon NUC501 Real Time Clock APB interface Clock Control This bit is used to control the APB 2 RTC CK EN clock only The RTC engine clock source is from the 32 768 KHz crystal input dd i O Disable 1 Enable Watch Dog Clock Enable The Watch Dog engine clock source is from the crystal H O Disable 1 Enable Timer Clock Enable The Timer clock engine source is from the crystal input 0 TIMER_CK_ENO Disable Enable Nuvoton Technology Corp 51 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Clock Source Select Control Register CLKSEL Before clock switch the related clock sources pre select and new select must be turn on CLKSEL CLK_BA 10 R W Clock Source Select Control Register 0x0000 0000 Reserved Reserved
64. 0C R interrupt Priority Encoding Register 0x0000_0000 AIC ISNR AIC BA 110 R interrupt Source Number Register 0x0000_0000 AICIMR Can R interrupt Mask Register 0x0000_0000 ATC_OISR_JAIC BA 118 R output Interrupt Status Register 0x0000_0000 Nuvoton Technology Corp 118 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Reserved Reserve Resemed Undefined AIC MECR NC 8A 120 W Mask Enable Command Register Undefined AIC MDCR AIC_BA 124 W Mask Disable Command Register Undefined AIC SSCR AIC_BA 128 W Source Set Command Register Undefined AIC SCCR AIC_BA 12C W Source Clear Command Register Undefined AIC EOSCR AIC_BA 130 W End of Service Command Register Undefined AIC TEST AIC_BA 134 W R ICE Debug mode Register Ox0000 0000 Nuvoton Technology Corp 119 Revision A1 3 http www nuvoton com nuvoTon NUC501 i 6 10 6 AIC Control Registers AIC Source Control Registers AIC SCR1 AIC_SCR8 Register Address R W C Description Reset Value AIC SCR1 AIC_BA 000 Source Control Register 1 Hu z R W 0x4747_4747 AIC_SCR8 AIC_BA 01C LN Control Register 8 Reserved Reserved as qs Ss I 2 Ta 1 I 5 5 Reserved 7 5 5 4 3 2 1 7 0 Reserved Bits Descriptions Interrupt Type 7 Indicates the level 0 edge 1 triggered 6 Indicates the low 0 high 1 level 31 30 e 00 low active level triggered 23 22 e 01 high active level triggered 15 14
65. 11 STS1 System states of endpoint 0 000 In ACK 001 In NAK 010 Out 0 ACK 110 Out 1 ACK 011 Setup ACK 111 Isochronous translation end Out Data more than Max Payload or Setup Data more than 8 Bytes In ACK In NAK Out O ACK 10 8 STSO 7 6 4 STS Out 1 ACK Setup ACK Isochronous translation end EPT Endpoint number 3 0 Nuvoton Technology Corp 104 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Bus States amp Attribution Register ATTR ATTR USB_BA 0x010 Rw Bus states amp attribution 0x0000 0040 MA AE A AE Reserved MEC a O o o e a Reserved Reserved a s 5 3 2 3 9 Descriptions O Disable USB 7 _ 1 Enable O Nothing 5 RWakeU 1 force USB bus to K state used for remote wake up O Disable PHY No response more than 18 bits time Read Only 2 Reume Resume from suspension Read Only d Bus idle more than 3mS either cable is plugged off or host is sleeping Read Only usbRST Bus reset when SEO single ended 0 more than 2 5uS Read Only Nuvoton Technology Corp 105 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Floating detection Register FLODET FLODET USB_BA 0x014 R Floating detection 0x0000 0000 Lose po qx cp RS EE EN Reserved Reserved pup qiu Reserved 03 s 5 1 7 31 2 3 9 we eme O floating FLODET Nuvoton Technology Co
66. 2 ADC_MUX 011 select AIN3 ADC_MUX 100 select AIN4 ADC_MUX 101 select AIN5 ADC_MUX 110 select AIN6 ADC_MUX 111 select AIN7 The ADC_MUX bits are read write AINO and AINi channel are differential inputs for audio recorder only When in Audio Recording operation AUDIO_CON 1 AUDIO EN 1 only AINO and AINi are dedicated inputs and ADC_MUX value is not effective in this operation ADC_FINISH Read Only O Converting 1 ADC conversion finish Nuvoton Technology Corp http www nuvoton com 267 Revision A1 3 nuvoTon NUC501 SS eee ADC X data buffer ADC_XDATA ADC XDATA ADC_BA 0x00C R ADC X data buffer 0x0000_0000 31 30 29 28 27 26 25 24 Reserved S O Reserved 23 22 a 20 19 18 17 16 CAI Reserved Reserved ADC_XDATA 2 6 5 4 3 2 1 0 ADC_XDATA Bits Descriptions ADC Data Buffer 9 0 ADC_XDATA When normal conversion mode the conversion data is always put at this register Nuvoton Technology Corp 268 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Low Voltage Detector Control Register LV_CON LV_CON ADC_BA 0x014 Low voltage detector control register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved Reserved Reserved Bits Descriptions Low voltage detector enable control pin 3 LV EN If LV EN 0
67. 2 When use a pin as powerdown wake up source the setting of edges must be explained as level trigger For example if set one pin for rising user must keep this pin low while start to enter power down a high level will make power down entrance be ignored After entering power down a high level at this pin will make chip leave power down NOTE3 When use a pin as power down wake up source if both edges are set the high level will be set as wake up level Nuvoton Technology Corp 148 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee GPIO B Interrupt Enable IRQENGPB IRQENGPB GP BA 0x94 R W GPIO Port B Interrupt Enable 0x0000_0000 O 15 14 1 13 2 i1 10 9 8 Reserved A 6 1 5 4 3 2 0 0 PB7ENF PBGENF PBSENF PB4ENF PB3ENF PB2ENF PBIENF PBOENF_ Bits Descriptions Enable GPBx input falling edge to trigger one of interrupt sources IRQO IRQ3 IRQSRCGPB register determines which IRQn n 0wW3 is the destination x 16 PBxENR Enable GPBx input rising edge to trigger one of interrupt sources IRQO IRQ3 IRQSRCGPB register determines which IRQn n 0 3 is the destination Where x 0 15 PBxENF and PBxENR can be set 1 at the same time NOTE1 In normal operation mode for each pin PBXENF and PBxENR can be set both to detect both rising and falling edge NOTE2 When use a pin as powerdown wake up source the setting of edges must be explained as level trigger For exam
68. 357 CRLRO dirty bit 6 CRLRDO When input channel 0 has a falling transition CRLRO was updated and this bit was 1 Capture Channel 0 transition Enable Disable 1 Enable 0 Disable 3 When Enable Capture latched the PWM counter value and saved to CRLR Rising latch and CFLR Falling latch When Disable Capture does not update CRLR and CFLR and disable Channel 0 Interrupt Channel O Falling Interrupt Enable ON OFF 1 Enable 2 FL amp IEO 0 Disable When Enable if Capture detects Channel 0 has falling transition Capture issues an Interrupt Channel O Rising Interrupt Enable ON OFF 1 Enable 1 RL amp IEO 0 Disable When Enable if Capture detects Channel 0 has rising transition Capture issues an Interrupt Channel 0 Inverter ON OFF 0 INVO 1 Inverter ON O Inverter OFF Nuvoton Technology Corp 192 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Capture Control Register CCR1 CCR1 PWM BA 0Ox054 R W Capture Control Register Ox0000 0000 Reserved Reserved CRLRD3 Reserved CIIR3 CAPCH3EN FL amp IE3 RL amp IE3 INV3 os 34 3 3 3 3 3 e a Ts 5 4 3 2 o CFLRD2 CRLRD2 Reserved CIIR2 CAPCH2EN FL amp IE2 RL amp IE2 INV2 Descriptions 31 23 CRLR3 dirty bit 22 CRLRD3 When input channel 1 has a falling transition CRLR3 was updated and this bit was 1 DI Capture Interrupt Indication 3 Enable Disable 1 Interrupt Fl
69. 6 14 2 RTC Features 199 6 14 3 RTC Function Description 200 6 14 4 RTC Register Mapping 202 6 14 5 RTC Register Descriptions 203 6 15 Serial Peripheral Interface Controller SPI Master Slave 216 6 15 1 SPI Function Description and Features 216 6 15 2 SPIMS Timing Diagram 217 6 15 3 SPIMS Programming Example 219 6 15 4 SPIMS Serial Interface Control Register Map 220 6 15 5 SPIMS Control Register Description 221 6 16 TIMER Controller 228 6 16 1 General Timer Controller 228 6 16 2 Watchdog Timer 228 6 16 3 Timer Control Registers Map 230 6 17 UART Interface Controller 239 6 17 1 Overview 239 6 17 2 Features 239 6 17 3 Block Diagram 239 6 17 4 Functional Blocks Descriptions 240 6 17 5 Finite State Machine 242 6 17 6 UART Interface Control Registers Mapping 245 6 18 Analog to Digital Converter 263 6 18 1 Features 263 6 18 2 ADC Functional Description 263 6 18 3 ADC Control Register Mapping 264 6 18 4 ADC Control Register Description 266 7 Electrical Characteristics 277 7 1 Absolute Maximum Ratings 277 7 2 DC Specifications 277 Nuvoton Technology Corp 4 Revision A1 3 http www nuvoton com nuvoTon NUC501 Eme 7 3 AC Specifications 277 7 3 1 Audio DAC Characteristic 277 7 3 2 ADC Characteristic 278 7 3 9 Voice Recorder Characteristic 278 8 Package Specifications 279 Nuvoton Technology Corp 5 Revision A1 3 http www nuvoton com NUVOTOM NUC501 Sor 1 General Description The NUC501 is an ARM7TDMI based MCU
70. 65 x 60 39 gt 0x27 FCR_fra 0x27 Example 2 Frequency counter measurement 32765 27Hz lt 32768 Hz Integer part 32765 gt Ox7ffd FCR int OxOd 0x01 0x08 0x04 Fraction part 0 27 x 60 16 2 gt 0x10 FCR fra 0x10 5 In TLR and TAR only 2 BCD digits are used to express year We assume 2 BCD digits of xY denote 20xY but not 19xY or 21xY Nuvoton Technology Corp 201 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee 6 15 4 RTC Register Mapping mim RTC_BA 0x000 ww RTC Initiation Register 0x0000_0000_ AER RTC_Bavox004 Rw RTC Access Enable Register 0x0000_0000_ rer Je bg yw RTC Frequency Compensation Register 00000 0700 DWR_ RTC_BA 0x018 ww Day of tne Week Register 0x0000_0006_ cam RTC_BA 0x020 ww calendar Alarm Regter 0x0009_0000_ TUIR RTC_BA 0x024 R Leap year Indicator Register 0x0900_0000_ TRIER RTC_BA 0x028 RAW RTG Interrupt Enable Register 0x0000_0000_ um RTC_BA 0x02c w c RTC Interrupt Indicator Register 0x0000_0000_ Nuvoton Technology Corp 202 Revision A1 3 http www nuvoton com nuvoTon NUC501 6 15 5 RTC Register Descriptions RTC Initiation Register INIR R W C Description Reset Value INIR RTC_BA 0x000 R W RTC Initiation Register 0x0000_0000 INIR Active RTC Active Status Read only O RTC is at reset state 1 RTC is at normal active state RTC Initiation When RTC block is power on RTC is at reset state program
71. Alternate Phase SCLK Clock Timing Master SS LVL 0 spi ss SS_LVL 1 gt rent ott UI wan SS Vroom ram ann ETT Slave Mode CNTRL SLAVE 1 CNTRL LSB 0 CNTRL Tx_NUM 0x01 CNTRL Tx_BIT_LEN 0x08 1 CNTRL CLKP 0 CNTRL Tx_NEG 1 CNTRL Rx_NEG 0 or 2 CNTRL CLKP 1 CNTRL Tx_NEG 0 CNTRL Rx_NEG 1 i P SPI Timing Slave So L L 0 spi ss SS_LVL 1 akp 0 IA PA HHH S code ees ous REE sn abn en Gem Slave Mode CNTRL SLAVE 1 CNTRL LSE 1 CNTRL Tx_NUM 0x01 CNTRL Tx BIT LEN 0x08 1 CNTRL CLKP 0 CNTRL Tx_NEG 0 CNTRL Rx_NEG 1 or 2 CNTRL CLKP 1 CNTRL Tx_NEG 1 CNTRL Rx_NEG 0 spi sclk i cu met EE APRES A UNS eae A T eee Se al 2d Ge op Zescz C mem rap Tal T C mem Nuvoton Technology Corp 218 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Alternate Phase SCLK Clock Timing Slave 6 16 3 SPIMS Programming Example When using this SPI controller as a master to access a slave device as slave device with following specifications Data bit latches on positive edge of serial clock Data bit drives on negative edge of serial clock Data is transferred with the MSB first SCLK idle low Only one byte transmits receives in a transfer Chip select signal is active low Basically the following actions should be done also the specification of the connected slave device sh
72. Boot from SRAM Boot from USB OTP program mode Boot from SpiMemory Nuvoton Technology Corp 30 Revision A1 3 http www nuvoton com nuvoTon NUC501 EE i iii CPU Control Register CPUCR CPUCR GCR_BA 08 CPU control register 0x0000_0000 Reserved Reserved o5 4 35 1 3 H 39 3 5 Reserved lea CI E A EES EC Reserved CPURST Descriptions CPU one shut reset Write this bit 1 will reset the CPU This bit will auto clear after the CPU reset 0 CPURST O Normal 1 Reset CPU Nuvoton Technology Corp 31 Revision A1 3 http www nuvoton com nuvoTon NUCS501 MISC Control Register MISCR MISCR GCR_BA 0C Miscellaneous Control Register 0x0000_0000 Reserved Reserved o5 4 1 35 8 39 3 1 8 Reserved Lo 9 q s os Jo s gt e a Reserved LVR WARM LVD EN Descriptions Low Voltage Reset Warm Up 1 LVR WARM 0 Disable 1 Low Voltage Reset function is warmed up to operate Low Voltage Detect Enable 0 LVD EN O Disable 1 Low Voltage Reset is selected and enabled Note 1 Enable LVR_WARM first waiting 5us and then enable LVD_EN 2 Disable LVD_EN first and then disable LVR_WARM 3 System will be reset when low voltage reset LVR function was enabled and AVDD drops below 2 4V 4 When LVR WARM is 1 the LVR function block will consumes about several tens uA Nuvoton Technology Corp 32 Revision A1 3 http www nuvoton com nuvoTon NUC501 EE
73. CPU read access from SpiMemory e 128 bit OTP key for code protection against illegal pirating e 2 bit SPI mode supported for doubling data transfer rate e Shared when not in use with other SPI device for high speed transfer via DMA e Audio Process Unit e Mono 16 bit Sigma Delta DAC output e Equalization function supported e USB 2 0 Full speed device e 6 programmable endpoints for Control Bulk In Out Interrupt and Isochronous transfers e 512 byte buffer Auto suspend function e Remote wakeup capability e Compatible with Philips DC standard e Master mode e Programmable master slave mode Speed up to 40MHz e 4 Channel PWM Four 16 bit timers e Programmable duty control of output waveform PWM Auto reload mode or one shot pulse mode e Capture and compare function e Analog to Digital Converter e 10 bit x 8 ch ADC for sensor MIC LVD LVR Maximum conversion rate 400K samples per second Power supply voltage 3 3V Analog input voltage range 0 3 3 volts Support wait for trigger mode amp standby mode e Dedicated LVD LVR Nuvoton Technology Corp 7 Revision A1 3 http www nuvoton com nuvoTon NUC501 VS e 8 level voltage detection e Miscellaneous e Two programmable 32 bit timers with 8 bit pre scale One 32 bit watch dog timer 32 768KHz RTC function support Up to 26 37 GPIO pins for LQFP 48 LQFP 64 Two UART ports with flow control TX RX CTS and RTS and UARTO is for high speed Power ma
74. CSOT ee ii 6 5 Audio Processing Unit The main purpose of Audio Processing Unit APU is used to playback the audio data PCM format which CPU decoded and stored in global RAM The APU built in a monophonic DAC with 16 bit resolution per channel which supports speakerphone output and monophonic output for headphone The APU is composed of an AHB Master and built in FIFO and timer 6 5 1 Overview and Features Built in a monophonic DAC with 16 bit resolution per channel e AHB Master with DMA Built in FIFO with length 16Bytes x 2 6 5 2 APU Functional Description 6 5 2 1 Audio DAC e Monophonic Digital to Analog Converter with 16 bit resolution per channel Supports speakerphone output and stereophonic output for headphone 6 5 2 2 Register Bank e AHB Slave interface on AHB A bridge that CPU control and observe the state of APU 6 5 2 3 Buffer Interface and Timer AHB Master interface on AHB Read Audio PCM data from global RAM Built in FIFO with length 16Bytes x 2 Built in timer to generate conversion trigger signal automatically 6 5 3 AUDIO DAC Clock This is the clock input for DAC from clock control module You can set CLKSEL 5 4 and CLKDIVO 15 8 to generate a clock with needed frequency The frequency of this clock must be equal to input audio data sampling rate x 128 For example if the sampling rate is 48KHz then the clock Should be 128 x 48KHz 6 144Mhz The APU module internally handles a 7 bit c
75. Control and Status Register CSR Register offset R W C Description Reset Value Control and Status Register 0x0000 0000 Reserved Reserved S Reserved Reserved Hg A PEPA AS EE 9 9 Reserved I2C RxACK I2C BUSY I2C AL I2C TIP Ve Cae E EE Reserved ss SCT TX NUM jReserved IF IE I2C EN Bits Descriptions 31 12 Received Acknowledge From Slave Read only 11 This flag represents acknowledge from the addressed slave O Acknowledge received ACK 1 Not acknowledge received NACK I7C Bus Busy Read only 10 I2C BUSY O After STOP signal detected 1 After START signal detected Arbitration Lost Read only 9 I2C AL This bit is set when the IC core lost arbitration Arbitration is lost when A STOP signal is detected but no requested The master drives SDA high but SDA is low Transfer In Progress Read only O Transfer complete 8 I2C_TIP 1 Transferring data NOTE When a transfer is in progress you will not allow writing to any register of the I C master core except SWR 7 6 Transmit Byte Counts These two bits represent how many bytes are remained to transmit When a byte has been transmitted the Tx NUM will decrease 1 until all bytes are transmitted Tx NUM 0x0 or NACK received from slave Then the interrupt signal will assert if IE was set ES RENO 0x0 Only one byte is left for transmission Ox1 Two bytes are left to for transmission 0x2 Three bytes are left for
76. Corp 154 Revision A1 3 http www nuvoton com nuvoTon NUC501 IRQ Interrupt Trigger Source 0 IRQTGSRCO IRQ0 3 Interrupt Trigger Source IRQTGSRCO GP_BA 0xB4 R C Indicator from GPIO Port A and GPIO Port 0x0000_0000 B Reserved NAT SS 0 Lo 1 89 8 5 47 1 3 E PP RA PA7TG PA6TG PA5TG PA4TG PA3TG PA2TG PA1TG PAOTG Bits Descriptions When this bit is read as 1 it indicates GPAx is the trigger source to PAxTG generate interrupt to the IRQ IRQO IRQ3 selected by IRQLHSEL 4 Write 1 to the bit x will clear the correspond interrupt source When this bit is read as 1 it indicates GPBx is the trigger source to x 16 PBxTG generate interrupt to the IRQ IRQO IRQ3 selected by IRQLHSEL 4 Write 1 to the bit x will clear the correspond interrupt source Where x 0 15 NOTE The trigger source will be latched when the corresponding rising or falling trigger enable is setup and the pin state toggle is recognized through de bounce or without de bounce no matter whether the source is an input or output pin Nuvoton Technology Corp 155 Revision A1 3 http www nuvoton com nuvoTon NUC501 IRQ Interrupt Trigger Source 1 IRQTGSRC1 IRQO 3 Interrupt Trigger Source Indicator Reserved Reserved Po EE Reserved PC10TG PC9TG PC8TG O 7 6 5 4 3 2 1 0 PC7TG PC6TG PC5TG PC4TG PC3TG PC2TG PC1TG PCOTG Bits Descriptions When this bit is read as 1 it indicates GPCx is
77. DC_BA 0xB800_1000 ADC CON ADC_BA 0x000 ADC control register 0x0000_0000 Nuvoton Technology Corp 264 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee ADC_BA 0x004 o o ADC_BA 0x008 Ti R ADC XDATA register BEN 0x0000 0000 5 ADC XDATA register o O LV_CON 0x0000_0000 x R W 0x0000 0000 E R W 0x0000_0000 0x0000_0000 iv cov gt C g E i UJ C T pl 5 ADC_BA 0x024 Audio data buffer register 0x0000_0000 a ADC_BA 0x028 R W Audio data buffer register 0x0000_0000 g ADC_BA 0x02C Audio data buffer register 0x0000_0000 D gt gt c c VO mi O O DH WwW c c min WIN Nuvoton Technology Corp 265 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee 6 19 4 ADC Control Register Description ADC Control Register ADC_CON ADC CON ADC _BA 0x000 R W ADC control register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved ADC_CON eet 72 6 5 4 3 2 1 0O ADC_DIV Bits Descriptions Low voltage detector interrupt enable bit 22 LVD INT EN If LVD_INT_EN 0 The LVD interrupt is disable If LVD INT EN 1 The LVD interrupt is enable ADC interrupt enable bit 21 ADC INT EN If ADC INT EN O The ADC interrupt is disable If ADC INT EN 1 The ADC interrupt is enable Reserved Reserved Low voltage detector LVD interrupt status bit 19 LVD INT If LV_INT 0 The LVD interrupt status is cleared If LV INT 1
78. GPA 5 General purpose input output en a eee Analog input AI 5 ADC analog input 5 GPA 6 General purpose input output AI 6 ADC analog input 6 GPA 7 General purpose input output GPA 6 AI 6 EE r SPIMS SO AI 7 Nuvoton Technology Corp LVD GPA 8 http www nuvoton com SPIMO_SCK 33 GPA 9 32 SPIMO_SO GPA 10 SPIMO_SI 3 GPA 11 SPIMS_SI 30 4 8mA I O with Analog input 4 8mA I O with 4 8mA I O 4 8mA I O 4 8mA I O 4 8mA I O 14 Analog input AI 7 ADC analog input 7 digital pin LVD Low voltage detection GPA 8 General purpose input output digital pin SPIMO SCK Serial clock output pin for SPIMO GPA 9 General purpose input output digital pin SPIMO SO Serial data input output pin for SPIMO Normal SPI mode this pin is used as data out Fast SPI read mode this pin is the 2 bit for data in GPA 10 General purpose input output digital pin SPIMO SI Serial data input pin for SPIMO GPA 11 General purpose input output digital pin SPIMS SI Serial data input pin for SPIMS 4 8mA GPA 12 General purpose input output I O digital pin Revision A1 3 NUVOTOM NUCS01 PWMTO SPIMS SO Serial data output pin for SPIMS PWMTO PWM output for timer O GPA 13 37 EN GPA 13 General purpose input output SPIMS SCK I O digital pin SPIMS SCK Serial clock pin for SPIMS master slave PW
79. HB bus at the same time the higher priority request will get the permission to access AHB bus Table 6 2 2 AHB Bus Priority Order in Fixed Priority Mode Priority AHB Bus Priority Sequence PRTMOD 0 0 1 Lowest ARM7TDMI SPIMO The SPI flash controller normally has the lowest priority under the fixed priority mode NUC501 provides a mechanism to raise the priority of CPU request to the highest If the IPEN bit bit 4 of AHB Control Register is set to 1 the IPACT bit bit 5 of AHB Control Register will be automatically set to 1 while an unmasked external NFIQ or NIRQ occurs Under this circumstance the ARM core will become the highest priority to access AHB bus The programmer can recover the original priority order by directly writing 1 to clear the IPACT bit For example this can be done that at the end of an interrupt service routine Note that IPACT only can be automatically set to 1 by an external interrupt when IPEN 1 It will not take effect for a programmer to directly write 1 to IPACT to raise ARM core s AHB priority 6 2 4 1 Round Robin Priority Mode Round robin priority mode is selected if PRTMODx 1 The AHB bus arbiter uses a round robin arbitration scheme for every master module to gain the bus ownership in turn That is the requestor Nuvoton Technology Corp 23 Revision A1 3 http www nuvoton com NUVOTOM NUCS01 having the highest priority becomes the lowest priority requestor after it ha
80. IPER application software or ICE when no interrupt pending The current priority level is not updated in this situation Hence the AIC EOSCR shouldn t be written ICE Debug Mode This mode allows reading of the AIC IPER without performing the associated automatic operations This is necessary when working with a debug system When an ICE or debug monitor reads the AIC user interface the AIC IPER can be read This has the following consequences in normal mode e If there is no enabled pending interrupt the fake vector will be returned e If an enabled interrupt with a higher priority than the current one is pending it will be stacked In the second case an End of Service command would be necessary to restore the state of the AIC This operation is generally not performed by the debug system Therefore the debug system would become strongly intrusive and could cause the application to enter an undesired state This can be avoided by using ICE Debug Mode When this mode is enabled the AIC performs interrupt stacking only when a write access is performed on the AIC IPER Hence the interrupt service routine must write to the AIC IPER any value just after reading it When AIC IPER is written the new status of AIC including the value of interrupt source number register AIC ISNR is updated with the value that is kept at previous reading of AIC IPER the debug system must not write to the AIC IPER as this would cause undesirable effects
81. Indicator Nuvoton Technology Corp 259 Revision A1 3 http www nuvoton com nuvoTon NUC501 This bit is set to a logic 1 whenever the received data input is held in the spacing state logic 0 for longer than a full word transmission time that is the total time of start bit data bits parity stop bits and is reset whenever the CPU reads the contents of the UA_LSR Framing Error Indicator This bit is set to logic 1 whenever the received character does not have a valid stop bit that is the stop bit following the last data bit or parity bit is detected as a logic 0 and is reset whenever the CPU reads the contents of the UA_LSR Parity Error Indicator This bit is set to logic 1 whenever the received character does not have a valid parity bit and is reset whenever the CPU reads the contents of the UA_LSR Overrun Error Indicator An overrun error will occur only after the RX FIFO is full and the next character has been completely received in the shift register The character in the shift register is overwritten but it is not transferred to the RX FIFO OE is indicated to the CPU as soon as it happens and is reset whenever the CPU reads the contents of the UA_LSR RX FIFO Data Ready e O RX FIFO is empty e 1 RX FIFO contains at least 1 received data word UA_LSR 4 2 BII FEI PEI are revealed to the CPU when its associated character is at the top of the RX FIFO These three error indicators are reset wheneve
82. La CASAS S E a e o __ Reserved IPACT IPEN Reserved PRTMODO Bits Descriptions Interrupt active status in IPEN enabled mode This bit is set when the IPEN is enabled and the external FIQ or IRQ is active 5 IPACT Write 1 to clear the status 0 Inactive 1 Active Enable raising the Priority of CPU in IRQ or FIQ period It can be used to reduce the interrupt latency in a real time system set this 4 bit the CPU will has the highest AHB priority 0 Disable 1 Enable AHB Bus Arbitration mode control 0 fixed priority mode 0 PRTMODO 1 round robin priority mode rotate The priority mode for fixed priority mode is APU SPIMO ARM7Tdmi Nuvoton Technology Corp 33 Revision A1 3 http www nuvoton com nuvoTon NUC501 PAD Control Register PAD REGO There are four PWM timers within the NUC501 and each PWM can free output to several GPIO pin by user setting for different application PAD REGO GCR_BA 30 PAD Control Register 0x0000_0000 o5 s 33 x 3s 3 7 6 J 5 4a j 3 j 2 j 13 j 0 Bits Descriptions 31 29 PWM_TMR3_I 28 24 PWM_TMR3_O Nuvoton Technology Corp http www nuvoton com PWM Timer 3 input pin selection 000 PWM Timer 3 input from GPIOB 0 001 PWM Timer 3 input from GPIOB 4 010 PWM Timer 3 input from GPIOC 6 011 PWM Timer 3 input from GPIOC 10 100 PWM Timer 3 input from GPIOB 7 Others disable PWM Timer 3 input function PWM Ti
83. MT1 PWM output for timer 1 4 8mA GPA 14 General purpose input output I O digital pin SPIMS SS Serial chip select pin for SPIMS slave mode USB DET USB detected pin 4 8mA GPA 15 General purpose input output I O digital pin PWMT2 PWM output for timer 2 USB DET USB detected pin I2C DATA I2C data input output pin if this pin is select for I2C function 4 8mA GPB 0 General purpose input output I O digital pin PWMT3 PWM output for timer 3 USB DET USB detected input I2C CLK I2C data output pin if this pin is select for I2C function 12 16mA GPB 1 General purpose input output I O digital pin PWMTO PWM output for timer O USB DET USB detected input UARTO TXD Data transmitter output pin for UARTO High speed PWMT1 GPA 14 SPIMS_SS USB_DET LA GPA 15 PWMT2 USB_DET IC2 DATA LA LP N oO A O pa N N HA A N GPB 0 PWMT3 USB_DET I2C CLK CJ I NJ U1 GPB 1 PWMTO USB DET UARTO TXD GPB 2 PWMT1 USB DET UARTO RXD LA O N LA 12 16mA GPB 2 General purpose input output I O digital pin PWMT1 PWM output for timer 1 USB_DET USB detected input UARTO_RXD Data receiver input pin for UARTO High speed 12 16mA GPB 3 General purpose input output I O digital pin PWMT2 PWM output for timer 2 c USB_DET USB detected input UARTO CTS Clear to Send input pin for UARTO High speed 12 16mA GPB 4 General purpose input output I O digi
84. Mask Register 0x0000_0000 IM 7 0 bie ESA Interrupt Mask This bit determines whether the corresponding interrupt channel is enabled or disabled Every interrupt channel can be active no matter whether it is enabled or disabled If an interrupt channel is enabled it does not definitely mean it is active Every interrupt 31 0 IMX channel can be authorized by the AIC only when it is both active and enabled e 0 Corresponding interrupt channel is disabled e 1 Corresponding interrupt channel is enabled Nuvoton Technology Corp 127 Revision A1 3 http www nuvoton com nuvoTon NUC501 ee AIC Output Interrupt Status Register AIC_OISR AIC_OISR AIC_BA 118 OR Output Interrupt Status Register 0x0000_0000 Reserved Reserved 035 35 IG 2 I 5S5 1G I 3 I 5 Reserved Reserved The AIC classifies the interrupt into FIQ mode and IRQ mode This register indicates whether the asserted interrupt is NFIQ or NIRQ If both NIRQ and NFIQ are equal to O it means there is no interrupt occurred Bits Descriptions Interrupt Request 1 e 0 NIRQ line is inactive e 1 NIRQ line is active Fast Interrupt Request 107 e O NFIQ line is inactive e 1 NFIQ line is active Nuvoton Technology Corp 128 Revision A1 3 http www nuvoton com nuvoTon NUC501 AIC Mask Enable Command Register AIC_MECR AIC_MECR AIC_BA 120 Mask Enable Command Register Undefined MEC 7 0 Bits Descriptions Mask Enable C
85. ON NUCSO1 ee ii Parameter To Wm Tw Wa Unt _ 7 3 2 ADC Characteristic Parameter Symbol Conditions Wim Typ Max Unit operating voltage Vo __ 30 33 36 operating Curent to 3 meemmmegn 9 Le smpmome s o lenso 30 De Wl mf pep Input Resistance 7 3 3 Voice Recorder Characteristic Parameter Symbel conditions mm Typ Mex Unit Gomme tese vo __ 30 39 ae CT Operating Current Reference Voltage VREF 3 3V Reference Current Lm 1 1 E l9 pow Conversiontime __ a 30 vw Some 40 e A A E Differential non linearity Dw ise Nuvoton Technology Corp 278 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee 8 Package Specifications LQFP 48 7x7x1 4mm footprint 2 0mm COTRGL DIMENSIONS ARE IN MILLIMETERS di wu O MEC Pa pe ar oes foro a8 fo o rs e ae o or se 700 ree Et eae 7 00 250 e jose oso oss o ps sm aro fo e es eco so o ons EE u re e Jews To e fo o os oz a un oOo IO ha lol J inh O BI wa ho ejua m Jalg J ID ICH CH N DI 0 350 0 350 an 007 p 0087 0 011 CH 3 Lu Nuvoton Technology Corp 219 Revision A1 3 http www nuvoton com nuvoTon NUC501 KL LQFP 64 10x10x1 4mm
86. R read only W write only R W both read and write GP_BA 0xB800_ 3000 GPIOA OMD GP_BA 0x00 R W GPIO Port A Bit Output Mode Enable 0x0000 0000 GPIOA PUEN GP_BA 0x04 R W GPIO Port A Bit Pull up Resistor Enable 0x0000 0000 GPIOA DOUT GP_BA 0x08 R W GPIO Port A Data Output Value 0x0000 0000 GPIOA PIN GP_BA 0x0C R ep Port A Pin Value OxXXXX XXXX GPIOB OMD GP_BA 0x10 R W GPIO Port B Bit Output Mode Enable 0x0000 0000 GPIOB PUEN GP_BA 0x14 R W GPIO Port B Bit Pull up Resistor Enable 0x0000 0000 GPIOB DOUT GP_BA 0x18 R W GPIO Port B Data Output Value 0x0000 0000 GPIOB PIN GP_BA 0x1iC R ep Port B Pin Value OxXXXX XXXX GPIOC OMD GP_BA 0x20 R W GPIO Port C Bit Output Mode Enable 0x0000 0000 GPIOC PUEN GP_BA 0x24 R W GPIO Port C Bit Pull up Resistor Enable 0x0000 0000 GPIOC DOUT GP_BA 0x28 R W GPIO Port C Data Output Value 0x0000 0000 GPIOC PIN GP_BA 0x2C R GPIO Port C Pin Value OxXXXX XXXX DBNCECON GP BA 0x70 R W External Interrupt De bounce Control 0x0000 0000 IRQSRCGPA GP BA 0x80 R W GPIO Port A IRQ Source Grouping 0x0000 0000 IRQSRCGPB GP_BA 0x84 R W GPIO Port B IRQ Source Grouping 0x5555 5555 IRQSRCGPC GP_BA 0x88 R W GPIO Port C IRQ Source Grouping OxAAAA AAAA IRQENGPA GP_BA 0x90 R W GPIO Port A Interrupt Enable 0x0000 0000 IRQENGPB GP BA 0x94 R W GPIO Port B Interrupt Enable 0x0000 0000 IRQENGPC GP BA 0x98 R W GPIO Port C Interrupt Enable 0x0000 0000 IRQLHSEL GP_BA
87. R W CDesciption reset Value inu Test eae 0x0000 0000 Tx 31 24 Tx 23 16 n n Tx 23 16 TN Jide 0 EN TS EE CO ES REA LEFT Tx 15 8 Bits Descriptions SO Data Transmit Register The I C core used 32 bit transmit buffer and provide multi byte transmit function Set CSR Tx_NUM to a value that you want to transmit I C core will always issue a transfer from the highest byte first For example if CSR Tx_NUM 0x3 Tx 31 24 will be transmitted first then Tx 23 16 and 31 0 Tx SO on In case of a data transfer all bits will be treated as data In case of a slave address transfer the first 7 bits will be treated as 7 bit address and the LSB represent the R W bit In this case LSB 1 reading from slave LSB 0 writing to slave Nuvoton Technology Corp 171 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee 6 13 PWM Timer 6 13 1 Introduction There are 4 PWM Timers enclosed The 4 PWM Timers has 2 Pre scale 2 clock divider 4 clock selectors 4 16 bit counters 4 16 bit comparators 2 Dead Zone generators They are all driven by APB clock Each can be used as a timer and issues interrupt independently Each two PWM Timers share the same pre scale 0 1 share prescaleO and 2 3 share prescale1 Clock divider provides each timer with 5 clock sources 1 1 2 1 4 1 8 1 16 Each timer receives its own clock signal from clock divider which receives clock from 8 bit pre scale Th
88. R register 3 e 1 If this bit is set spi ss o signals are generated automatically It means that device slave select signal which is set in SSR register is asserted by the SPI controller when transmit receive is started by setting CNTRL GO BUSY and is de asserted after every transmit receive is finished Slave Select Active Level It defines the active level of device slave select signal spi ss o 2 SS LVL e O the spi ss o slave select signal is active Low e 1 the spi_ss_o slave select signal is active High Slave Select Register If SSR ASS bit is cleared writing 1 to any bit location of this field sets the 0 proper spi_ss_o line to an active state and writing 0 sets the line back to inactive state Nuvoton Technology Corp 69 Revision A1 3 http www nuvoton com nuvoTon NUC501 If SSR ASS bit is set writing 1 to any bit location of this field will select appropriate spi_ss_o line to be automatically driven to active state for the duration of the transmit receive and will be driven to inactive state for the rest of the time The active level of spi_ss_o is specified in SSR SS_LVL NOTE This interface can only drive one device slave at a given time Therefore the slave select of the selected device must be set to its active level before starting any read or write transfer Nuvoton Technology Corp http www nuvoton com 70 Revision A1 3 nuvoTon NUC501 Data Receive Register 0 1 2
89. Recognize leap year automatically The day of week counter Frequency compensate register FCR Beside FCR all clock and alarm data expressed in BCD code Support time tick interrupt Support wake up function Nuvoton Technology Corp 199 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee 6 15 3 RTC Function Description RTC Initiation When RTC block is power on programmer has to write a number Oxa5eb1357 to INIR to reset all logic INIR act as hardware reset circuit Once INIR has been set as 0xa5eb1357 there is no action for RTC if any value be programmed into INIR register RTC Read Write Enable Register AER bit 15 0 is served as RTC read write password It is used to avoid signal interference from system during system power off AER bit 15 0 has to be set as 0xa965 after system power on Once it is set it will take effect 512 RTC clocks later about 15ms Programmer can read AER bit 16 to find out whether RTC register can be accessed Frequency Compensation The RTC FCR allows software control digital compensation of a 32 768 KHz crystal oscillator User can utilize a frequency counter to measure RTC clock in one of GPIO pin during manufacture and store the value in Flash memory for retrieval when the product is first power on Time and Calendar counter TLR and CLR are used to load the time and calendar TAR and CAR are used for alarm They are all represented by BCD 12 24 hour Time Scale Selection The 12 24
90. SS eee CLK_BA 0xB100_0200 AHBCLK CLK_BA 04 R W AHB Device Clock Enable Control Register 0x0000 0083 APBCLK CLK BA 08 R W APB Device Clock Enable Control Register 0x0000 0007 Nuvoton Technology Corp 46 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Power Down Control Register PWRCON The chip clock source is from an external crystal The crystal oscillator can be control on off by the register XTAL_EN When turn off the crystal the chip into power down state Crystal wake up pre scale counter value After the clock counter count pre scale x 256 crystal cycle the clock controller output the clock to system PWRCON CLK_BA 00 R W System Power Down Control Register OxOOFF_FFO3 Reserved e a ia e a a RL Pre Scale 15 8 cs I 5 pe pa po Ts Ts Pre Scale 7 0 7 e 5 4 3 2 3 o Bits Descriptions 31 24 24 Reserved Reserved 0000000000000 23 8 Pre Scale EA A counter Assume the UU RH is stable after the Pre Scale 256 crystal cycle ci e uu mm Down interrupt status Read O normal 1 Indicate crystal enable change from low to high the chip is resume form 3 INTSTS power down state The interrupt is active if the GPIO USB or Host controller wakeup Write O no action 1 Clear interrupt Power On Interrupt Enable O Disable 2 INT_EN l 1 Enable The interrupt will occur when the Crystal enable signal XTAL EN change
91. T1_RXD GPC 7 PWMT0 UART1_CTS 60 GPC 8 PWMT1 UART1_RTS GPA 0 AI 0 MICP GPA 1 AI 1 MICN GPA 2 Al 2 O Nuvoton Technology Corp http www nuvoton com E A O A O WS E a a GPA 3 AI 3 GPC 3 PWMTO EAS GPA 4 Al 4 X12MO GPA 5 AIS X12MI 4 n RES GPA 6 AI 6 GPA 7 Al 7 LVD VBAT NUCS01BDN E Lu WA LLI c c ce EC TDO 7 7 GPB 8 PWMTO 10 TDI EA nTRST GPB 9 PWMT1 LQFP 64 Pin Out 10 APA mem GPB 7 SPI2 SCK PWMT3 X32KO X32KI 14 TCK 15 GPB 6 SPIM1_SO SPIMO SS GPA 8 SPIMO SCK i Sei cme GPB 5 SPIM1_SI NUC501 GPA 9 SPIMO SO GPA 10 SPIMO SI GPA 11 SPIMS SI GPA 12 SPIMS SO PWMTO GPA 13 SPIMS_SCK PWMT1 GPA 14 SPIMS SS GPA 15 PWMT2 I2C DATA GPB 0 PWMT3 I2C CLK GPB 1 PNMTO UARTO_TXD GPB 2 PWMT1 UARTO RXD GPB 3 PNMT2 UARTO CTS GPB 4 PWMT3 UARTO RTS GPC 10 PWMT3 I2C CLK GPC 9 PWMT2 I2C DATA Revision A1 3 nuvoTon NUCS01 eem Pin Descriptions In order to maximize the NUC501 application for different field each pin of NUC501 is very flexible and can play up to four different functions The user can program each pin to the wanted function for the different product The pin functions are controlled by the registers PAD REGO PAG REG1 and PAD REG2 For each multiple function pin the default function is
92. Technology Corp 223 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Slave Select Register SSR SSR SPIMS_BA 0x08 R W Slave Select Register 0x0000 0000 31 30 29 28 27 26 25 24 amp Reserved 23 22 21 20 19 18 17 16 _ Reserved Reserved 7 5 4 3 2 3 9 Reserved ASS ss ivi Reserved SSR Bits Descriptions ES Automatic Slave Select master only O If this bit is cleared slave select signals are asserted and de asserted by setting and clearing related bits in SSR register 3 1 If this bit is set spi_ss_o signals are generated automatically It means that device slave select signal which is set in SSR register is asserted by the SPI controller when transmit receive is started by setting CNTRL GO_BUSY and is de asserted after every transmit receive is finished Slave Select Active Level It defines the active level of device slave select signal spi ss o 2 SS LVL i i O The spi_ss_o slave select signal is active Low 1 The spi ss o slave select signal is active High Slave Select Register master only If SSR ASS bit is cleared writing 1 to any bit location of this field sets the proper spi_ss_o line to an active state and writing 0 sets the line back to inactive state If SSR ASS bit is set writing 1 to any bit location of this field will select appropriate spi_ss_o line to be automatically driven to active state
93. The LVD is in interrupt state and write O to clear it ADC interrupt status bit 18 ADC INT If ADC_INT 0 The ADC interrupt status is cleared If ADC_INT 1 The ADC is in interrupt state and write O to clear it ADC block enable bit 17 If ADC_EN 0 The ADC block is disable If ADC_EN 1 The ADC block is enable ADC reset control bit 16 ADC_RST If ADC_RST 1 the ADC block is at reset mode If ADC_RST 0 the ADC block is at normal mode The conversion mode control bits 15 14 ADC_MODE If ADC_MODE 00 normal conversion mode is selected If ADC_MODE others reserved Nuvoton Technology Corp 266 Revision A1 3 http www nuvoton com nuvoTon 13 ADC_CONV 12 ADC_READ_CONV di 8 1 Reserved Il 1 mem NUC501 ADC conversion control bit If ADC_CONV 1 inform ADC to converse when conversion finished this bit will be auto clear If ADC_CONV 0 the ADC no action and this only could be cleared by hardware This bit can be wrote 1 ONLY This bit control if next conversion start after ADC_XDATA register is read in normal conversion mode If ADC_READ_CONV 1 start next conversion after the ADC_XDATA is read and ignore the ADC_CONV bit If ADC_READ_CONV 0 after the ADC_XDATA is read the ADC no action These bits select ADC input from the 8 analog inputs in normal conversion mode ADC_MUX 000 not available in normal data conversion ADC_MUX 001 not available in normal data conversion ADC_MUX 010 select AIN
94. Time Tick Register The RTC time tick is used for interrupt request TTRIZ 0 oo Z E E EA em m IG ue a ue so um 6 MM Nuvoton Technology Corp 215 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS EEE 6 16 Serial Peripheral Interface Controller SPI Master Slave 6 16 1 SPI Function Description and Features The SPI controller performs a serial to parallel conversion on data characters received from the peripheral and a parallel to serial conversion on data characters received from CPU This controller can drive up to 2 external peripherals but is time shared and can not operate simultaneously It also can be driven as the slave device when the CNTRL 18 SLAVE bit be set It can generate an interrupt signal when data transfer is finished and can be cleared by writing 1 to the interrupt flag The active level of slave select signal can be chosen to low active or high active on SSR SS_LVL bit which depends on the peripheral it s connected Writing a divisor into DIVIDER register can program the frequency of serial clock output This controller contains four 32 bit transmit receive buffers and can provide burst mode operation It supports variable length transfer and the maximum transmitted received length can be up to 128 bits The SPI Master Slave Core includes the following features AMBA APB interface compatible Support SPI master slave mode Full duplex synchronous serial data transfer Variable length of tr
95. Timer Initial Control Register 0 0x0000_0000 TICR1 TMR_BA 00C Timer Initial Control Register 1 0x0000_0000 TIC 31 24 TIC 23 16 as Io Is I Ta Ts TT TIC 15 8 TIC 7 0 o7 dq s s po a a 2 J 2 J EE Timer Initial Count This is a 32 bit value representing the initial count Timer will reload this value whenever the counter is decremented to zero 31 0 TIC NOTE1 Never write 0x0 in TIC or the core will run into unknown state NOTE2 No matter CEN is 0 or 1 whenever software write a new value into this register TIMER will restart counting using this new value and abort previous count Nuvoton Technology Corp 233 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Timer Data Register 0 1 TDRO TDR1 TDRO TMR_BA 10 CH Timer Data Register 0 0x0000_0000 TDR1 TMR_BA 14 OR Timer Data Register 1 0x0000_0000 TDR 31 24 TDR 23 16 cs TT Te Tae TDR 15 8 gt jos jos Jos Jj s a s jo TDR 7 0 Bits Descriptions Timer Data Register The current count is registered in this 32 bit value NOTE Software can read a correct current value on this register only when CEN O or the value represents here could not be a correct one Nuvoton Technology Corp 234 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Timer Interrupt Status Register TISR TISR TMR_BA 18 Timer Interrupt Status Register 0x0000_0000 Reserved Reserved SI I I I E CI O Reserved Res
96. Ton APU Power Down Control Register PDCON APU_BA 0x08 Power Down Control Register 0x0001 0000 IL SEEK INE NIRE IURE Reserved Oa E ee ee ee ee Reserved Reserved a ee eee Reserved Descriptions m Audio DAC Power Down 16 ANA PD Normal operation Power down as Nuvoton Technology Corp 81 Revision A1 3 http www nuvoton com NUVOTON dll TT APU Interrupt Register APUINT APU BA OxOC R W APU Interrupt Register 0x0000 0000 O eee ee ae ee eee Reserved AO AAA Lm e 8 qo CA ow j j Reserved pex Reserved T2INTS T1INTS Descriptions 3 38 Threshold 2 Interrupt Enable 17 T2INTEN 0 Disable 1 Enable Threshold 1 Interrupt Enable 16 TLIINTEN 0 Disable 1 Enable 15 2 Reserved Reserved Threshold 2 Interrupt Status 1 T2INTS A APU fetch data from Threshold 2 complete Write O to clear it Threshold 1 Interrupt Status 0 T1INTS r APU fetch data from Threshold 1 complete Write O to clear it Nuvoton Technology Corp 82 Revision A1 3 http www nuvoton com NUC501 nuvoTon RAM Base Address Register RAMBSAD APU_BA 0x10 RAM Base Address Register 0x0000 0000 Eee ee ee EENEG BSAD 31 24 33 22 2 20 19 18 1 16 BSAD 23 16 BSAD 15 8 7 e 5 4 3 2 3 BSAD 7 0 Bits Descriptions 31 0 BSAD Global RAM Base Address Nuvoton Technology Corp 83 Revision A1 3 http www nuvoton
97. ag ON 20 0 Interrupt Flag OFF Note If this bit is 1 PWM counter 3 will not reload when next capture interrupt occur Capture Channel 3 transition Enable Disable 1 Enable 0 Disable 19 When Enable Capture latched the PMW counter and saved to CRLR Rising latch and CFLR Falling latch When Disable Capture does not update CRLR and CFLR and disable Channel 3 Interrupt Channel 3 Falling Interrupt Enable ON OFF 1 Enable 18 FL amp IE3 0 Disable When Enable if Capture detects Channel 3 has falling transition Capture issues an Interrupt 17 RL amp IE3 Channel 3 Rising Interrupt Enable ON OFF Nuvoton Technology Corp 193 Revision A1 3 http www nuvoton com nuvoTon NUC501 1 Enable 0 Disable When Enable if Capture detects Channel 3 has rising transition Capture issues an Interrupt Channel 3 Inverter ON OFF 16 INV3 1 Inverter ON 0 Inverter OFF eg CFLR2 dirty bit 7 CFLRD2 When input channel 2 has a rising transition CFLR2 was updated and this bit was 1 CRLR2 dirty bit 6 CRLRD2 When input channel 2 has a falling transition CRLR2 was updated and this bit was 1 Capture Interrupt Indication 2 Enable Disable 1 Interrupt Flag ON 0 Interrupt Flag OFF 4 If this bit is 1 PWM counter 2 will not reload when next capture interrupt Capture Channel 2 transition Enable Disable 1 Enable 0 Disable 3 When Enable Capture latched the PMW counter value and saved to CRLR
98. ager section System memory map Bus arbitration algorithm Power on setting Product identify register System control registers for reset share pin GPIO Clock control registers 6 2 2 System Memory Mapping NUC501 provides a 4G byte address space for programmers The memory locations assigned to each on chip modules are shown in table 6 2 1 The detailed register and memory addressing and programming will be described in the following sections for individual on chip modules NUC501 only supports little endian data format Address Space Toen modules ooo Memory Space 0x0000 0000 0x0000 7FFF IBR BA Internal Boot ROM IBR Memory Space IBR_remap 0 0x0000_0000 Ox1FFF_FFFF SRAM_BA SRAM Memory Space IBR_remap 1 0x2000_0000 Ox3FFF FFFF SRAM BA SRAM Memory Space IBR remap 0 0x4000_0000 Ox4FFF_FFFF SPI Flash ROM Memory Space SPIMO 0x6000_0000 0x6000 7FFF IBR BA Internal Boot ROM IBR Memory Space IBR_remap 1 OxB100 0000 0xB100_01FF GCR_BA OxB100 0200 0xB100_02FF CLK BA OxB100 4000 OxB100 4FFF SRAMCTL BA OxB100 7000 OxB100 7FFF SPIM BA OxB100 8000 OxB100 8FFF APU BA OxB100 9000 OxB100 9FFF USB BA OxB800 1000 0xB800_1FFF ADC BA Analog Digital Converter ADC Controller Registers OxB800 2000 OxB800 2FFF AIC BA Interrupt Controller Registers OxB800 3000 OxB800 3FFF GPIO BA GPIO Controller Registers Nuvoton Technology Corp 23 Revision A1 3 http www nuvoton com
99. ailable interrupt sources into eight priority levels Interrupt sources within the priority level 0 have the highest priority and the priority level 7 has the lowest To work this scheme properly you must specify a certain priority level to each interrupt source during power on initialization otherwise the system shall behave unexpectedly Within each priority level interrupt source that is positioned in a lower channel has a higher priority Interrupt source that is active enabled and positioned in the lowest channel within the priority level 0 is promoted to the FIQ mode Interrupt sources within the priority levels other than 0 can petition for the IRQ mode The IRQ mode can be preempted by the occurrence of the FIQ mode Interrupt nesting is performed automatically by the AIC A higher priority interrupt source will cause the NIRQ to CPU be asserted again when CPU is servicing a lower priority interrupt if the I bit in CPSR is enabled Though interrupt sources originated from the NUC501 itself are intrinsically high level sensitive the AIC can be configured as either low level sensitive high level sensitive negative edge triggered or positive edge triggered to each interrupt source 6 10 2 Features e AMBA APB bus interface and Individual mask for each interrupt source e External interrupts can be programmed as either edge triggered or level sensitive e External interrupts can be programmed as either low active or high active Has flags to r
100. ansfer word up to 32 bits Provide burst mode operation transmit receive can be executed up to four times in one transfer MSB or LSB first data transfer Rx and Tx on both rising or falling edge of serial clock independently 2 slave device select lines when it is as the master mode and 1 slave device select line when it is as the slave mode Fully static synchronous design with one clock domain Only Support the external master device that the frequency of its serial clock output is less 1 4 than the SPI Core clock input PCLK and its slave select output is edge active trigger Nuvoton Technology Corp 216 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee 6 16 2 SPIMS Timing Diagram The timing diagrams of SPI Master Slave are shown as following SS LVL 0 spi ss o st ee CLKP 0 f spi ech o DOLO 3x E03 EE 331 3 3 spi so o D D D 0 H H spi si i Master Mode CNTRL SLAVE 0 CNTRL LSB 0 CNTRL Tx_NUM 0x0 CNTRL Tx_BIT_LEN 0x08 1 CNTRL CLKP 0 CNTRL Tx_NEG 1 CNTRL Rx NEG 0 or 2 CNTRL CLKP 1 CNTRL Tx_NEG 0 CNTRL Rx_NEG 1 SPI Timing Master So LVL 0 spi ss o SS LVL 1 F Master Mode CNTRLISLAVE 0 CNTRL LSB 1 CNTRL Tx_NUM 0x0 CNTRL Tx_BIT_LEN 0x08 1 CNTRL CLKP 0 CNTRL Tx_NEG 0 CNTRL Rx_NEG 1 or 2 CNTRL CLKP 1 CNTRL Tx_NEG 1 CNTRL Rx_NEG 0 Nuvoton Technology Corp 217 Revision A1 3 http www nuvoton com NUVOTON NUC501 SS eee
101. ansferred byte is followed by an acknowledge bit on the 9th SCL clock cycle If the slave signals a Not Acknowledge NACK the master can generate a STOP signal to abort the data transfer or generate a Repeated START signal and start a new transfer cycle If the master as the receiving device does Not Acknowledge NACK the slave the slave releases the SDA line for the master to generate a STOP or Repeated START signal Nuvoton Technology Corp 159 Revision A1 3 http www nuvoton com NUVOTON NUC501 SS eee To write data to a slave store the data to be transmitted in the Transmit Register TxR and set the WRITE bit To read data from a slave set the READ bit During a transfer the core set the I2C_TIP flag indicating that a Transfer is in Progress When the transfer is done the I2C_TIP flag is cleared the IF the flag set if enabled then an interrupt generated The Receive Register RxR contains valid data after the IF flag has been set The software may issue a new write or read command when the I2C_TIP flag is cleared Fhange of data allowedl Gata line stable data valid Bit transfer on the 1 C bus clock pulse for acknowledgement SCL FROM MASTER DATA OUTPUT B TRANSMITTER DATA OUTPUT BY RECEIVER P acknowledge conditio n Acknowledge on the I7C bus 6 12 4 I C Programming Examples Example 1 Write 1 byte of data to a slave using multi byte transmit mode Slave address 0
102. are programs CNTRL the GO_BUSY bit should be written last Nuvoton Technology Corp 220 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee 6 16 5 SPIMS Control Register Description Control and Status Register CNTRL CNTRL SPIMS BA 0x00 Control and Status Register 0x0000 0004 31 30 29 28 27 26 25 24 Reserved CLKP Tx NUM 7 6 5 4 3 2 3 9 Tx BIT LEN Tx NEG Rx NEG GO BUSY Descriptions DEU SPI Operation Mode 18 SLAVE O Master mode 1 Slave mode Interrupt Enable 17 O Disable SPI Interrupt 1 Enable SPI Interrupt Interrupt Flag O It indicates that the transfer dose not finish yet 16 1 It indicates that the transfer is done The interrupt flag is set if it was enable NOTE This bit is read only but can be cleared by writing 1 to this bit Suspend Interval master only These four bits provide the configuration of suspend interval between two successive transmit receive in a transfer The default value is 0x0 When CNTRL Tx_NUM 00 setting this field has no effect on transfer The desired interval is obtained according to the following equation from the last falling 15 12 SLEEP edge of current sclk to the first rising edge of next sclk CNTRL SLEEP 2 period of SCLK SLEEP 0x0 2 SCLK clock cycle SLEEP 0x1 3 SCLK clock cycle SLEEP Oxe 16 SCLK clock cycle Nuvoton indice A e eee RA Corp 221 Revision A1 3
103. ast read mode 8 h3b fast read dual output mode The direction control of spi so o see block diagram In most case spi so o is output But in flash fast dual read mode spi so o 23 is bi direction pin 0 spi so o is output 1 spi so o is input For cipher IP 22 0 current transfer is data phase 1 current transfer is command phase 21 men Disable AHB master in boot mode Nuvoton Technology Corp 63 Revision A1 3 http www nuvoton com nuvoTon NUC501 NOTE When want to access SPI flash through direct memory mapping please set this bit high SPI ROM Boot Page Write enable e 0 Disable ROM boot or page write operation 20 BOOT_SPIM e 1 Enable ROM boot or page write operation NOTE When want to access SPI flash through direct memory mapping please set this bit high Flash Data Read Enable write data to Flash operation when BOOT_SPI high 19 Enable read data from Flash operation when BOOT_SPI high NOTE When want to access SPI flash through direct memory mapping please set this bit LOW Flash Type 18 F_TYPE e O SST 16Mbit SPI Serial Flash ST25VFO16B e 1 PMC 512Kbit Serial Flash Memory with SPI Bus Interface Interrupt Enable 17 Disable SPI Interrupt Enable SPI Interrupt Interrupt Flag e 0 It indicates that the transfer dose not finish yet e 1 It indicates that the transfer is done The interrupt flag is set if it was enable 16 NOTE This bit is read
104. ave address transfer 3 Data transfer 4 STOP signal generation 3 7 ACK Y oz of oo foo MSY U MSB LSB ponet or Sr uw J EI SLAVE ADDRESS data transfer n bytes acknowledge from master to slave E A acknowledge SDA low A not acknowledge SDA high from slave to master S START condition P STOP condition A master transmitter addressing a slave receiver with a 7 bit address The transfer direction is not changed HSE SLAVE ADDRESS B 2 a DATA DATA data transfer n bytes acknowledge A master reads a slave immediately after the first byte address START or Repeated START signal When the bus is free idle meaning no master device is engaging the bus both SCL and SDA lines are high a master can initiate a transfer by sending a START signal A START signal usually referred to as the S bit is defined as a HIGH to LOW transition on the SDA line while SCL is HIGH The START signal denotes the beginning of a new data transfer A Repeated START Sr is a START signal without first generating a STOP signal The master uses this method to communicate with another slave or the same slave in a different transfer direction e g from writing to a device to reading from a device without releasing the bus Nuvoton Technology Corp 158 Revision A1 3 http www nuvoton com NUVOTON NUC501 ES _e e e lt lt lt lt lt T
105. be written R W C Description Reset Value Base Address 0xB100_7000 CNTRL SPI_BA 0x00 Control and Status Register 0x0000 0004 DIVIDER SPI BA 0x04 Clock Divider Register 0x0000 0000 SSR SPI BA 0x08 Slave Select Register 0x0000 0000 Rx0 SPI BA 0x10 OR Data Receive Register 0 0x0000_0000 Rui o o SPI BA 0x14 ORO Data Receive Register 1 0x0000_0000 Bai o o SPI_BA 0x18 CH Data Receive Register 2 0x0000_0000 RXB Oooo SPI BA OxiC ORO Data Receive Register 3 0x0000_0000 TxO SPI BA 0x20 Data Transmit Register 0 0x0000_0000 TE o SPI_BA 0x24 O RW Data Transmit Register 1 0x0000_0000 T SPI_BA 0x28 Data Transmit Register 2 0x0000_0000 SPI_BA 0x2C Data Transmit Register 3 0x0000_0000 AHB_ADDR SPI_BA 0x30 AHB memory address 0x0000_0000 CODE_LEN SPI_BA 0x34 Boot code length 0x0000_0000 SPIRA Dec OxFFFF_FFFF SPIM_ADDR SPI BA 0x40 SPI Flash Start Address 0x0000 0000 NOTE1 When software programs CNTRL the GO_BUSY bit should be written last Nuvoton Technology Corp 62 Revision A1 3 http www nuvoton com nuvoTon NUC501 p Control and Status Register CNTRL R W C Description TO Reset Value CNTRL SPI_BA 0x00 Control and Status Register 0x0000_0004 OEN COMMAND DIS_M_ BOOT_SPI F_DRD F_TYPE IE E o Q _ I dummy Tx_BIT_LEN Tx_NEG Ee r GO BUSY Bits Descriptions SPI read mode selection 8 h03 standard read mode 31 24 8 hOb f
106. ce of 0x0000_0000 Ox1FFF_FFFF of system memory For this purpose 16 tag registers are implemented to keep the base address of each 2KB memory block Besides each 2KB memory block could also be disabled individually by modifying control register 16 memory block enable bits are implemented for this purpose Nuvoton Technology Corp 90 Revision A1 3 http www nuvoton com NUC501 nuvoTon 6 6 6 SRAM Register Mapping SRAMCTRL_BA 0xB100_4000 Nuvoton Technology Corp 91 Revision A1 3 http www nuvoton com NUVOTON NUGSO _ __y__y_ __ r 6 6 6 1 Register Descriptions SRAM Control Register 0 SCTRLO SCTRL15 Reserved Reserved Bits Descriptions 31 29 TAG Address This field keeps the base address of each 2KB memory block Once the 28 11 TAG address bits 28 11 from system bus are the same with the content of this filed and the VALID flag is enabled the related memory block will be opened for access Nuvoton Technology Corp 92 Revision A1 3 http www nuvoton com NUVOTON menn 10 1 TAG Valid Flag This bit indicates if the TAG value is valid 0 VALID This bit 1 bO indicates the corresponding 2KB memory block was disabled and inaccessible O corresponding 2KB memory block is disabled 1 corresponding 2KB memory block is enabled Nuvoton Technology Corp 93 Revision A1 3 http www nuvoton com NUVOTON dll TT 6 7 USB Device
107. cial care to minimize the power consumption while allowing for the flexibility to reach for high performance It includes the clock gating variable frequency control for individual IP s and bus control to reduce signal toggle Besides the NUC501 can be further operated under different power saving modes idle power down with RTC active and power down mode With so many practical peripherals integrated around the high performance ARM7 CPU the NUC501 is Suitable for such applications as Interactive toys edutainment robots and home appliances Whenever MIPS hungry task meets cost effective demand you ll find the NUC501 truly useful to satisfy the requirement 2 Feature e 32 bit RISC CPU e ARM TDMI O 108 MHz e 16 bit Thumb mode supported to save code size e Embedded 32 KB Local Memory divided into 16 segments for easier S W programming e Boot from SpiMemory or USB e Program download into SRAM through JTAG before OTP key programmed e Integrate JTAG port to support real time non stop ICE function for system development and debugging Nuvoton Technology Corp 6 Revision A1 3 http www nuvoton com NUVOTOM NUC501 ee AU AAMAMAA ALL LULA e 6KB internal ROM e Bootloader e ICP for SpiFlash amp security OTP key via USB e 32KB internal SRAM e Embedded 32KB SRAM for code and data 16 segments with address tags e SpiMemory interface with code protection e DMA mode for code booting from SpiMemory to internal SRAM e Direct
108. com NUVOTON dll TT Threshold 1 Address Register THAD1 APU BA 0x14 Threshold 1 Address Register 0x0000 0000 AEREI RARO NR TH1 31 24 33 22 a 20 19 18 1 16 TH1 23 16 TH1 15 8 7 e 5 4 3 2 3 TH1 7 0 Bits Descriptions 31 0 Threshold 1 Address Nuvoton Technology Corp 84 Revision A1 3 http www nuvoton com NUVOTON dll TT Threshold 2 Address Register THAD2 APU BA 0x18 Threshold 2 Address Register 0x0000 0000 TH2 31 24 ME NE MUERE EIER TH2 23 16 TH2 15 8 DOI 0000 ee IC E E O TH2 7 0 MI Bits Descriptions LP oo 31 0 Threshold 2 Address 0x00000000 Internal SRAM RAM Base Address Threshold 1 Address Threshold 2 Address Nuvoton Technology Corp 85 Revision A1 3 http www nuvoton com NUC501 nuvoTon Current Address Register CURAD APU_BA 0x1C R Current Access RAM Address Register 0x0000_0000 ARIE INR ARIZONA CURAD 31 24 CURAD 23 16 CURAD 15 8 7 e 5 4 3 2 3 CURAD 7 0 CRA A AA eee Bits Descriptions 31 0 CURAD Current APU Access RAM Address Nuvoton Technology Corp 86 Revision A1 3 http www nuvoton com NUVOTON NUCSO1 ee ii 6 6 SRAM Controller 6 6 1 Overview The SRAM controller is design for program code and data storage It s an AHB slave and SRAM size is up to 32KB This 32KB memory is separated into 16 memory block and the size of
109. d Reserved Descriptions DEI Time Tick Interrupt Enable 1 TIER 1 gt RTC Time Tick Interrupt and counter enable O gt RTC Time Tick Interrupt and counter disable Alarm Interrupt Enable 0 1 gt RTC Alarm Interrupt enable O gt RTC Alarm Interrupt disable Nuvoton Technology Corp 213 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee RTC Interrupt Indication Register RIIR Register Address R W C Description _Reset Value CS ee ee ee Reserved MNAC CA Reserved Reserved Reserved Descriptions DEI RTC Time Tick Interrupt Indication d TI 1 It indicates that time tick interrupt has been activated O It indicates that time tick interrupt never occurred Software can also clear this bit after RTC interrupt has occur RTC Alarm Interrupt Indication 1 It indicates that time counter and calendar counter have counted to a d specified time recorded in TAR and CAR RTC alarm interrupt has been activated O It indicates that alarm interrupt never occurred Software can also clear this bit after RTC interrupt has occurred Nuvoton Technology Corp 214 Revision A1 3 http www nuvoton com nuvoTon NUC501 RTC Time Tick Register TTR R W C Description Resetvane TTR RTC_BA 0x030 R C RTC Time Tick Register 0x0000_0000 TW E NEUE INIM eee UN Reserved C eee ee ee ae ee Reserved Reserved EA e I Rim Hi Reserved TTR 2 0 Bits Descriptions OOOO 3 3
110. d in one transfer 10 Three successive transmit receive will be executed in one transfer 11 Four successive transmit receive will be executed in one transfer Transmit Bit Length This field specifies how many bits are transmitted in one transmit receive 7 3 Tx BIT LEN Up to 32 bits can be transmitted Tx BIT LEN 0x01 1 bit Nuvoton Technology Corp 65 Revision A1 3 http www nuvoton com nuvoTon NUC501 Tx_BIT_LEN 0x02 2 bits Tx_BIT_LEN Ox1f 31 bits Tx_BIT_LEN 0x00 32 bits Transmit On Negative Edge Read Only 1 b1 e This module only supports transmitting on negative edge Receive On Negative Edge Read Only 1 bO e This module only supports receiving on positive edge Go and Busy Status e O Writing O to this bit has no effect e 1 Writing 1 to this bit starts the transfer This bit remains set during GO_BUSY the transfer and is automatically cleared after transfer finished NOTE All registers should be set before writing 1 to the GO_BUSY bit in the CNTRL register When a transfer is in progress writing to any register of the SPI master core has no effect Nuvoton Technology Corp 66 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Divider Register DIVIDER E Reset Value DIVIDER SPIM BA 0x04 Clock Divider Register 0x0000_0000 Reserved I Es ee IEA RCA VECES CT TS 3 2 TT 0 DIVIDER 7 0 Descriptions SES Seria
111. dshake Nuvoton Technology Corp 110 Revision A1 3 http www nuvoton com nuvoTon NUC501 Extra Configuration Register CFGPx x 0 5 Register Address R W Description Reset Value tall trol ist d I t d CEGPO USB_BA 0x02C R W stall control regis ei and In out ready 0x0000 0000 clear flag of endpoint 0 tall trol ist d I t d CFGP1 USB_BA 0x03C R W EE ola 0000 clear flag of endpoint 1 tall trol ist d I t d CFGP2 USB_BA 0x04C R W SCONO SA SE ONE SETS p00 00 gege clear flag of endpoint 2 CFGP 3 USB _BA 0x05C R W stall control register and In out ready 0x0000 0000 clear flag of endpoint 3 Il i I CFGP4 USB_BA 0x06C R W pean OHO Sg SSA MA CULI eer geb clear flag of endpoint 4 tall control register and In out read CFGP5 USB_BA 0x07C R W etal 00 HO Ted EEN 0x0000_0000 clear flag of endpoint 5 ES E E ee ee AMEN EN EE NN Reserved Reserved EE NENNEN ae NN MEM O EMEN NN Reserved 3 s 5 3 1 2 3 Reserve a rr Descriptions Di stat Force device to response STALL R W 0 IN Write 1 to clear in ready that was set by MXPLD OUT Write 1 to clear out ready that was set by MXPLD 6 8 Nuvoton Technology Corp 111 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee USBSEO USBSEO USB _BA 0x090 RW o Set D and D to idle state 0x0000 0000 ee ee ee eee Reserved Reserved Reserved o7 e 5 4 3 2 Reserved Descriptions 0 Normal
112. e 8 UARTO_EN O disable 1 GPIOB 2 1 used as the pins of UARTO TxD and RxD SPIMO pin enable GPIOA 10 8 used as pins of the SPIMO SPI_ROM O disable 1 enable SPIMS pin enable SPIMS pins at GPIOA 14 11 GPA 14 used as the CS_ pin of SPIMS and was controlled by SPIMS CNTRL 16 O disable 1 enable SPIM1 pin enable 2 b00 disable 2 b01 SPIM1 pins at GPIOB 7 5 SPIM1 pins at GPIOC 2 0 Unacceptable I2C pin enable disable I2C pins at GPIOA 15 and GPIOB 0 I2C pins at GPIOC 10 9 Unacceptable Nuvoton Technology Corp 40 Revision A1 3 http www nuvoton com nNnUvVoTon NUC501 PAD Control Register PAD REG2 PAD REG2 GCR_BA 38 PAD Control Register 0x0000_0000 Reserved Reserved cs o8 1 35 3 uH 1 9 8 Reserved C7 Ts 13 1 4 3 2 0 Descriptions USB detection selection 3 0 USBDET_SEL Nuvoton Technology Corp http www nuvoton com 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 disable USB connection detect pin from GPA 14 USB connection detect pin from GPA 15 USB connection detect pin from GPB 0 USB connection detect pin from GPB 1 USB connection detect pin from GPB 2 USB connection detect pin from GPB 3 USB connection detect pin from GPB 4 USB connection detect pin from GPB 8 USB connection detect pin from GPB 9 USB connection detect pin fr
113. e mechanism are much simpler than those of micro programmed Complex Instruction Set Computers Pipelining is employed so that all parts of the processing and memory systems can operate continuously The high instruction throughput and impressive real time interrupt response are the major benefits The ARM7TDMI CPU core has two instruction sets 1 The standard 32 bit ARM code 2 16 bit THUMB code The THUMB code is 16 bit instruction set that allows it to increase the code density compare to standard ARM core while retaining most of the ARM performance advantage over a traditional 16 bit processor using 16 bit registers THUMB instructions operate with the standard ARM register configuration allowing excellent interoperability between ARM and THUMB states Each 16 bit THUMB instruction has a corresponding 32 bit ARM instruction with the same effect on the processor model ARM7TDMI CPU core has 31 x 32 bit registers At any one time 16 registers are visible the other registers are used to speed up exception processing All the register specifies in ARM instructions can address any of the 16 registers The CPU also supports 5 types of exception such as two levels of interrupt memory aborts attempted execution of an undefined instruction and software interrupts Nuvoton Technology Corp 22 Revision A1 3 http www nuvoton com NUVOTOM NUC501 EE 6 2 System Manager 6 2 1 Overview The following functions are included in system man
114. e 16 bit counter in each timer receive clock signal from clock selector and can be used to handle one PWM period The 16 bit comparator compares number in counter with threshold number in register loaded previously to generate PWM duty cycle The clock signal from clock divider is called PWM clock Dead Zone generator utilize PWM clock as clock source Once Dead Zone generator is enabled output of two PWM Timers are blocked Two output pin are all used as Dead Zone generator output signal to control off chip power device Dead Zone generator 0 is used to control outputs of timer 081 and Dead Zone generator 1 is used to control outputs of timer 283 To prevent PWM driving output pin with unsteady waveform 16 bit counter and 16 bit comparator are implemented with double buffering feature User can feel free to write data to counter buffer register and comparator buffer register without generating glitch When 16 bit down counter reaches zero the interrupt request is generated to inform CPU that time is up When counter reaches zero if counter is set as toggle mode it is reloaded automatically and start to generate next cycle User can set counter as one shot mode instead of toggle mode If counter is set as one shot mode counter will stop and generate one interrupt request when it reaches zero The value of comparator is used for pulse width modulation The counter control logic changes the output level when down counter value matches the value o
115. eflect the status of each interrupt source Proprietary 8 level interrupt scheme to ease the burden from the interrupt e Daisy chain priority mechanism is applied to interrupts set as the same priority level e Automatically masking out the lower priority interrupt during interrupt nesting e Automatically clearing the interrupt flag when the external interrupt source is programmed to be edge triggered Nuvoton Technology Corp 113 Revision A1 3 http www nuvoton com nuvoTon NUC501 Ep 6 10 3 Interrupt Sources The following table lists all interrupts from various peripheral interface modules or external devices 1 WDT_INT Watch Dog Timer Interrupt 2 Reserved Reserved 3 INT GPIOO GPIO Interrupto 4 INT GPIO1 GPIO Interrupt1 5 INT GPIO2 GPIO Interrupt2 6 INT GPIO3 GPIO Interrupt3 7 INT APU Audio Processing Unit Interrupt 8 Reserved Reserved 9 Reserved Reserved 10 INT ADC AD Converter Interrupt INT RTC RTC Interrupt 12 INT UARTO UART 0 Interrupt Reset default Channel level 13 INT UART1 UART 1 Interrupt 14 INT TMR1 Timer 1 Interrupt 15 INT TMRO Timer 0 Interrupt 16 Reserved Reserved 17 Reserved Reserved 18 Reserved Reserved 19 INT_USB USB Device Interrupt Notes 20 Reserved Reserved 21 Reserved Reserved INT PWMO PWM InterruptO 23 INT _PWM1 PWM Interruptl Nuvoton Technology Corp 114 Revision A1 3 http www nuvoton com N N pa pa nuvoTon NUC501 m 24 INT PWM2 SCR7 7 0 PWM I
116. egister TLR WE Description Reset Value TLR RTC BA 0x00C R W Time Loading Register 0x0000 0000 TWR a a 7z ERE NN Reserved 23 22 21 20 19 18 17 16 Reserved doHR E 0 j s l1514 3123131 9 Seed ose see Bits Descriptions Eidem ee Domm i0MnTmeDgk O O Do um EN 6 3 0 1 Sec Time Digit Notes TLR is a BCD digit counter and RTC will not check loaded data Nuvoton Technology Corp 206 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee RTC Calendar Loading Register CLR TI Reset value CLR s RTC_BA 0x010 R w Calendar Loading Register 0x0005 0101 EE NENNEN NINE IMEEM Reserved ELEME IRE o MIN IDEEN WE A ee 10YEAR Reserved OMON AMON 3 s 51 3 5 312131 31 24 Reserved Reserved 23 20 LOYEAR 10 Year Calendar Digit 19 16 1YEAR 1 Year Calendar Digit 15 13 Reserved 12 10MON 10 Month Calendar Digit 10DAY 10 Day Calendar Digit 3 0 1DAY 1 Day Calendar Digit Notes CLR is a BCD digit counter and RTC will not check loaded data reserved o Nuvoton Technology Corp 207 Revision A1 3 http www nuvoton com nuvoTon NUC501 o NNNSN 4_ RTC Time Scale Selection Register TSSR TI Reset value TSSR RTC_BA 0x014 R W Time Scale Selection Register 0x0000_0001 CLARA IR E ee a Reserved pump em Reserved Reserved
117. er is serviced first The current priority level is defined as the priority level of the interrupt with the highest priority at the time the register AIC_IPER is read In the case when a higher priority unmasked interrupt occurs while an interrupt already exits there are two possible outcomes depending on whether the AIC_IPER has been read e If the processor has already read the AIC_IPER and caused the NIRQ line to be de asserted then the NIRQ line is reasserted When the processor has enabled nested interrupts and reads the AIC_IPER again it reads the new higher priority interrupt vector At the same time the current priority level is updated to the higher priority e If the AIC_ IPER has not been read after the NIRQ line has been asserted then the processor will read the new higher priority interrupt vector in the AIC_IPER register and the current priority level is updated When the End of Service Command Register AIC_EOSCR is written the current interrupt level is updated with the last stored interrupt level from the stack if any Therefore at the end of a higher priority interrupt the AIC returns to the previous state corresponding to the preceding lower priority interrupt which had been interrupted Interrupt Handling When the NIRQ line is asserted the interrupt handler must read the AIC_IPER as soon as possible This can de assert the NIRQ request to the processor and clears the interrupt if it is programmed to be edge trigge
118. erved Descriptions DEI Timer Interrupt Flag 1 This bit indicates the interrupt status of Timer channel 1 e O It indicates that the Timer 1 dose not countdown to zero yet 1 TIF1 e 1 It indicates that the counter of Timer 1 has decremented to zero The interrupt flag is set if it was enable NOTE This bit is read only but can be cleared by writing 1 to this bit Timer Interrupt Flag 0 This bit indicates the interrupt status of Timer channel 0 e O It indicates that the Timer O dose not countdown to zero yet 0 TIFO e 1 It indicates that the counter of Timer O has decremented to zero The interrupt flag is set if it was enable NOTE This bit is read only but can be cleared by writing 1 to this bit Nuvoton Technology Corp 235 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Watchdog Timer Control Register WTCR WTCR TMR_BA 01C Watchdog Timer Control Register 0x0000_0400 gt Reserved s Reserved o e Je e o f c a E IL Descriptions Emm Watchdog Timer Clock This bit is used for deciding whether the Watchdog timer clock input is divided by 256 or not Clock source of Watchdog timer is Crystal input e 0 Using original clock input 10 WTCLK L10 e 1 The clock input will be divided by 256 NOTE When WTTME 1 set this bit has no effect on WDT clock using original clock input ICE debug mode acknowledge enable e 0 When DBGACK is high the Watchdog timer counter will be
119. esired length of code to specific target address 6 4 5 1 Code Boot Process Step 1 Read the Check ID and code length in device Step 2 Set the target memory address in AHB_ADDR system memory address Set the boot code length which read from step 1 into CODE_LEN register Set the SPI start address in SPI_ADDR peripheral address Set SSR register to select spi slave no support ASS in dma mode Set the READ command 03 and 3 Byte SPI Start Address into Tx0 Tx1 Tx2 Tx3 Set SPI CNTRL Ox1a1345 for control information Wait code read finish Wait interrupt Set SSR register to un select spi slave no support ASS in dma mode IJ A E If used SPI flash supports other read mode users can also use the following mode 1 Fast read Ob set read command Ob into Tx0 amp SPI CNTRL 0x0b1a1b45 2 Fast dual read 3b set read command 3b into Tx0 amp SPI CNTRL Ox3b1a1b45 6 4 5 2 Move data from system memory to peripheral Program SPI Flash Step 1 Erase the spi flash before program it Step 2 Send Write Enable command to SPI flash Set the source memory address in AHB_ADDR Set the code length into CODE_LEN register Set the spi start address in SPI_ADDR Set SSR register to select spi slave no support ASS in dma mode Set the Page Program command 02 and 3 Byte SPI Start Address into Tx0 Tx1 Tx2 Tx3 Set SPI_CNTRL 0x161345 for control information Wait code write finish Wait interrupt Set
120. f compare register Each PWM Timer includes a capture channel The Capture 0 and PWM O share a timer that included in PWM 0 and the Capture 1 and PWM 1 share another timer and etc Therefore user must setup the PWM Timer before turn on Capture feature Please reference the section of PWM Timer for more detail description of setup PWM Timer After enabling capture feature the capture always latched PWM counter to CRLR when input channel has a rising transition and latched PWM counter to CFLR when input channel has a falling transition Capture channel O interrupt is programmable by setting CCRO 1 Rising latch Interrupt enable and CCRO 2 Falling latch Interrupt enable to decide the condition of interrupt occur Capture channel 1 has the same feature by setting CCRO 17 and CCRO 18 And capture channel 2 amp 3 has the same feature by setting CCR1 1 CCR1 2 and CCR1 17 CCR1 18 respectively Whenever Capture issues Interrupt 0 1 2 3 the PWM counter 0 1 2 3 will be reload at this moment There are only four interrupts from PWM to advanced interrupt controller AIC PWM 0 and Capture 0 Nuvoton Technology Corp 172 Revision A1 3 http www nuvoton com nuvoTon NUC501 ES MEOEEUUUUET Share the same interrupt PWM1 and Capture 1 share the same interrupt and so on Therefore PWM function and Capture function in the same channel cannot be used at the same time 6 13 2 Features Two 8 bit pre scales and Tw
121. he DC core generates a START signal when the START bit in the Command Register CMDR is set and the READ or WRITE bits are also set Depending on the current status of the SCL line a START or Repeated START is generated STOP signal The master can terminate the communication by generating a STOP signal A STOP signal usually referred to as the P bit is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH lele START condition STOP condition START and STOP conditions Slave Address Transfer The first byte of data transferred by the master immediately after the START signal is the slave address This is a 7 bits calling address followed by a RW bit The RW bit signals the slave the data transfer direction No two slaves in the system can have the same address Only the slave with an address that matches the one transmitted by the master will respond by returning an acknowledge bit by pulling the SDA low at the 9th SCL clock cycle The core treats a Slave Address Transfer as any other write action Store the slave device s address in the Transmit Register TxR and set the WRITE bit The core will then transfer the slave address on the bus AO RW L slave address The first byte after the START procedure Data Transfer Once successful slave addressing has been achieved the data transfer can proceed on a byte by byte basis in the direction specified by the RW bit sent by the master Each tr
122. held 9 nDBGACK EN e 1 No matter DBGACK is high or not the Watchdog timer counter will not be held Watchdog Timer Test Mode Enable For reasons of efficiency the 20 bit counter within the Watchdog timer is 8 WTTME considered as two independent 10 bit counters in the test mode They are operated concurrently and separately during the test This approach can save a lot of time spent in the test When the 10 bit counter overflows a Watchdog timer interrupt is generated Nuvoton Technology Corp 236 Revision A1 3 http www nuvoton com NUC501 Put the Watchdog timer in normal operating mode Put the Watchdog timer in test mode Watchdog Timer Enable e O Disable the Watchdog timer This action will reset the internal counter e 1 Enable the Watchdog timer Watchdog Timer Interrupt Enable e O Disable the Watchdog timer interrupt e 1 Enable the Watchdog timer interrupt Watchdog Timer Interval Select These two bits select the interval for the Watchdog timer No matter which interval is chosen the reset timeout is always occurred 16128 WDT clock cycles later than the interrupt timeout Real Time Interval WTIS Timeout Inte t Timeout WTIS Timeout Interrupt Timeout CLK 15MHz 256 00 2 clocks 217 1024 docks 2 14 1024 clocks 2 1024 clocks 5 4 Watchdog Timer Interrupt Flag If the Watchdog timer interrupt is enabled then the hardware will set this bit to indicate that the Watchdog timer interrup
123. i rosee m schen O 30 asee iSeTmebgt Notes TAR is a BCD digit counter and RTC will not check loaded data Nuvoton Technology Corp 210 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee RTC Calendar Alarm Register CAR R W C Description Reset Value CAR IRTC_BA 0x020 R w Calendar Alarm Register 0x0000 0000 Oa EN NUN INNEN IE RN Reserved pup miim 10YEAR reserved MON dMN 02 s 513513 I2 I3 I CO 23 20 10YEAR 1916 15 13 121 10MON to onth Calendar Di SSS 118 IMON t onth Calendar DIE 78 sai DO Notes CAR is a BCD digit counter and RTC will not check loaded data Nuvoton Technology Corp 211 Revision A1 3 http www nuvoton com nuvoTon NUC501 RTC Leap year Indication Register LIR R W C Description _ Reset Value LIR RTC_BA 0x024 R RTC Leap year Indication Register 0x0000_0000 WC E CCA ee ee Reserved MEC CA O Reserved Reserved 03 ICI E aag e Descriptions SCH Leap Year Indication REGISTER Real only 0 LIR 10 1 It indicate that this year is leap year O It indicate that this year is not a leap year Nuvoton Technology Corp 212 Revision A1 3 http www nuvoton com nuvoTon NUC501 RTC Interrupt Enable Register RIER R W C Description Reset Value RIER RTC_BA 0x028 R w RTC Interrupt Enable Register 0x0000_0000 TW IEC ee eee ee M Reserved E E ee ee ee ae ee e Reserved Reserve
124. ined as level trigger For example if set one pin for rising user must keep this pin low while start to enter power down a high level will make power down entrance be ignored After entering power down a high level at this pin will make chip leave power down NOTE3 When use a pin as power down wake up source if both edges are set the high level will be set as wake up level Nuvoton Technology Corp 150 Revision A1 3 http www nuvoton com nuvoTon NUC501 Interrupt Latch Trigger Selection IRQLHSEL IRQLHSEL GP_BA 0xA0 Rw Interrupt Latch Trigger Selection Register 0x0000_0000 Reserved Reserved 5 a Bg nR un 10 9 8 Reserved 7 6 5 4 3 2 1 0 a nan Uem IRQ3LHE IRQ2LHE IRQ1LHE IRQOLHE Descriptions 31 9 Interrupt Request Source Control O While the gpio interrupt occur the gpio interrupt controller generate one clock pulse to the AIC 8 1 While the gpio interrupt occur the interrupt from gpio to AIC will keep till the CPU clear the interrupt trigger source IRQTGSRCO IRQTGSRC1 GPIO interrupt wake up system enable IRQxWake While IRQxWake is 1 enable the GPIO IRQx wake up the chip from power down mode While IRQXLTH is 1 it enables active IRQx interrupt to latch the input values IRQxLHE of GPAx GPBx GPCx to IRQLHGPA IRQLHGPB IRQLHGPC register 3 simultaneously Where x 0 3 Nuvoton Technology Corp 151 Revision A1 3 http www nuvoton com
125. ing the operation The reported status information includes the type and condition of the transfer operations being performed by the UART as well as any error conditions parity error overrun error framing error or break interrupt found The UART includes a programmable baud rate generator that is capable of dividing crystal clock input by divisors to produce the clock that transmitter and receiver needed The baud rate equation is Baud Out crystal clock 16 Divisor 2 6 18 2 Features e 64 byte 16 byte entry FIFOs for received and transmitted data payloads e Flow control functions CTS RTS are supported e Programmable baud rate generator that allows the internal clock to be divided by 2 to 2 16 1 to generate an internal 16X clock e Fully programmable serial interface characteristics 5 6 7 or 8 bit character Even odd or no parity bit generation and detection 1 181 2 or 2 stop bit generation Baud rate generation False start bit detection Loop back mode for internal diagnostic testing 6 18 3 Block Diagram Nuvoton Technology Corp 230 Revision A1 3 http www nuvoton com NUVOTON NUC501 SSS Eee APB BUS TX FIFO viti RX FIFO 64 16 ontroller 64 16 Rx shift register Tx shift register Baud Rate Generator SOUT External clock SIN 6 18 4 Functional Blocks Descriptions TX_FIFO The transmitter is buffered with a 64 16 byte FIFO to reduce the number of interrupts p
126. interrupt comparator TOIC a 16 0 TOIC receiver time out interrupt INTR TOUT is generated if UA TOR 7 UA IER 0 1 A new incoming data word or RX FIFO empty clears INTR TOUT Note The time out cycles must be larger than the number of cycles to receive one byte For example if it needs 10 cycles to receive one byte the TOIC should be 11 127 Nuvoton Technology Corp 262 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee 6 19 Analog to Digital Converter The 10 bit analog to digital converter ADC in this chip is a successive approximation type ADC with 8 channel inputs 2 inputs of them are dedicated for audio recorder It needs 50 cycles to convert one sample the maximum input clock to ADC is 25MHz so the maximum conversion rate is 400K sec and the operating voltage range is 3 3V 10 The power down mode is supported in the ADC Beside the 10 bit ADC an 8 levels voltage detector is included in this chip The detector result is independent with power supply and it could give the system a warning signal when battery voltage is lower than an absolute reference voltage 6 19 1 Features e Maximum conversion rate 400K sample per second Power supply voltage 3 3V Analog input voltage range 0 3 3 volts Standby mode supports 8 level voltage detector Control Register Low voltage detector Battery Voltage ADC Block Diagram 6 19 2 ADC Functional Description 6 19
127. ions 27 24 CVI Chip Version Identifier Chip version identifier is 4 hO for 1 version 23 0 Chip Identifier l Chip identifier is 24 h55_ 0501 for NUC501 Nuvoton Technology Corp 28 Revision A1 3 http www nuvoton com nuvoTon NUCS501 System Power On Configuration Register SPOCR This register provides specific information for software to identify this chip s power on setting SPOCR 6 0 are the status of the power on setting pins They can be modified by software programming SPOCR GCR_BA 04 System Power On Configuration Register 0x0000_00XX e IG 3 S Lo 7 qp 9 qp s p 49 1 l s 2 J 3 J 9 Bits Descriptions 31 21 IBR_remap 0 Boot ROM address mapping at 0x0000_0000 0x0000 7FFF and the SRAM address mapping at 0x2000_0000 Ox3FFF_FFFF 20 IBR_remap j RPM a 1 Boot ROM address mapping at 0x6000 0000 0x6000 7FFF and the SRAM address mapping at 0x0000_0000 Ox1FFF_FFFF SPI flash speed selection SCLK 00 72 MHz 6 5 SYS_CFG 01 36 MHz 10 18 MHz 11 50 KHz ICE Mode configuration setting Read Only 4 SYS CFG O ICE mode enable and the disable the cipher function 1 Normal mode Nuvoton Technology Corp 29 Revision A1 3 http www nuvoton com NUVOTOM NUC501 LQFP48 ICE mode configuration setting 0 48 pins package and GPB 9 5 for ICE connection 1 48 pins package and GPB 9 5 use the normal function test mode test mode test mode test mode
128. l CLK Input Delay register Set this register to adjust the spi_sclki clock input delay There are total 8 buffers in this delay path The actual delay value depends on process 22 20 SCLK_IN_DLY STA 000 one buffer delay 111 8 buffer delay The idle interval of slave select 19 16 IDLE_CNT In direct memory mapping mode IDLE_CNT is used to ensure the slave select idle interval in peripheral specification between two successive flash access Clock Divider Register The value in this field is the frequency divider of the system clock pclk to generate the serial clock on the output spi_sclk_o The desired frequency is obtained according to the following equation 15 0 DIVIDER De lai DIVIDER 2 Nuvoton Technology Corp 67 Revision A1 3 http www nuvoton com nuvoTon NUC501 NOTE When set DIVIDER to zero SPI clock will be equal to engine clock NOTE when set DIVIER to zero sleep CNTRL SLEEP can t set to zero Nuvoton Technology Corp 68 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Slave Select Register SSR EEN Sep SPIM_BA 0x08 Slave Select Register 0x0000_0000 Reserved Reserved a 3 135 I1 2 1 4 I3 I 35 18 Reserved 7 e 5 4 3 2 1 9 Reserved ASS SS LVL Reserved SSR Descriptions DEI Automatic Slave Select e O If this bit is cleared slave select signals are asserted and de asserted by setting and clearing related bits in SS
129. ling Latch Register channel 0 0x0000_0000 CFLR1 PWM_BA 0x064 R W Capture Falling Latch Register channel 1 Ox0000 0000 CFLR2 PWM_BA 0x06C R W Capture Falling Latch Register channel 2 0x0000_0000 CFLR3 PWM_BA 0x074 R W Capture Falling Latch Register channel 3 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved CFLRO 15 8 7 6 5 4 3 2 1 0 CFLRO 7 0 31 16 Reserve Capture re _ eo 0 ng Latch Register0 15 0 CFLRO peer dix ipid Latch the PWM counter when Channel 0 has Falling transition Nuvoton Technology Corp 196 Revision A1 3 http www nuvoton com nuvoTon NUC501 Capture Input Enable Register CAPENR CAPENR PWM_BA 0x078 R W Capture Input Enable Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved Reserved 07 s 15 1 4 3 2 I 3 9 CAPENR 3 0 DEI Capture Input Enable Register There are eight capture inputs from pad BitO Bit3 are used to control each inputs ON or OFF At most 4 inputs can be used at the same time O0 OFF 1 ON CAPENR 3 0 3210 Xxx1 Capture channel 0 is from GPA DIN 12 or GPB DIN 1 or 3 0 GPB DIN 8 or GPC DIN 3 or GPC DIN 7 xx1x Capture channel 1 is from GPA_DIN 13 or GPB_DIN 2 or GPB_DIN 9 or GPC_DIN 4 or GPC_DIN 8 X1xx Capture channel 2 is from GPA DIN 15 or GPB DIN
130. ll 2 o l o 7 Reserved Reserved Bits Descriptions Read IN Length of Data transmitting to host Out Max Length of Data receiving from host Write 7 0 MXPLD IN Length of Data to transmit to host assert INrdy IN buffer ready OUT Max Length of Data receiving from host assert OUTrdy OUT buffer ready Note once MXPLD is filled out the data packets will be transmitted received immediately after IN OUT token arrived Nuvoton Technology Corp 109 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Configuration Register CFGx x 0 5 CFGO USB_BA 0x028 R W Configuration of Endpoint 0 0x0000_0000 CFG1 USB_BA 0x038 R W Configuration of Endpoint 1 0x0000_0000 CFG2 USB_BA 0x048 R w Configuration of Endpoint 2 0x0000_0000 CFG3 USB_BA 0x058 R w Configuration of Endpoint 3 0x0000_0000 CFG4 USB_BA 0x068 R w Configuration of Endpoint 4 0x0000_0000 CFG5 USB_BA 0x078 R W Configuration of Endpoint 5 0x0000_0000 31 30 29 28 27 26 25 Reserved EN O NNNM NNNM a MEM UM Reserved 15 14 13 12 1 10 9 8 Reserved stall ctl Reserved 7 6 S5 4 3 2 1 O DSQ state ISOCH EPT Descriptions Bits Descriptions OOO ERC 1 enable auto clear stall in setup stage mi PSA Spes Data 0 or 1 after IN token toggle automaticly after host ACK 00 endpoint is disabled 6 5 01 Out ENER 10 IN endpoint 11 undefined CN Isochronous no han
131. low voltage detector is disable If LV EN 1 low voltage detector is enable The low voltage detector voltage level switch control bits If SW CON 000 SW1 is close others are open If SW CON 001 SW2 is close others are open If SW CON 010 SW3 is close others are open If SW CON 011 SW4 is close others are open If SW CON 100 SW5 is close others are open If SW CON 101 SW6 is close others are open If SW CON 110 SW7 is close others are open If SW CON 111 SW8 is close others are open The relationship of SW CON setting vs detected voltage level See Nuvoton Technology Corp 269 Revision A1 3 http www nuvoton com nuvoTon NUC501 Low Voltage Detector Status Register LV_STS LV_STS ADC_BA 0x018 R W The status register of low voltage detector 0x0000 0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved Reserved 727 6 5 4 3 2 13 0 Reserved LV status Bits Descriptions Low voltage detector status pin Read Only e If LV status O the compared voltage is higher than reference voltage 0 LV status e If LV status 1 the compared voltage is lower than reference voltage Nuvoton Technology Corp 270 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Audio control register AUDIO_CON AUDIO_CON ADC_BA 0x01C R W_ Audio control status and data register 0x0000_0000 31
132. mber from UART clock source The UART clock frequency UART clock source frequency UART_N 1 15 8 APU clock divide number from APU clock source The APU clock frequency APU clock source frequency APU N 1 7 6 APB N APB clock divide number from CPU The APB clock frequency CPU clock frequency APB N 1 5 4 RMS 3 0 HCLK_N HCLK ee divide number from HCLK clock source The HCLK clock frequency HCLK clock source frequency 2 HCLK_N 1 Nuvoton Technology Corp 54 Revision A1 3 http www nuvoton com nuvoTon NUC501 Clock Divider Register CLKDIV 1 CLKDIV1 CLK BA 18 R W Clock Divider Number Register 0x0000 0000 Reserved cs 4I 9 I1 I c5IG I Reserved Reserved E AIAR RN ECH Descriptions ADC engine clock divide number from ADC clock source 23 16 The ADC engine clock frequency ADC engine clock source frequency ADC_N 1 Nuvoton Technology Corp 55 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee MPLL Control Register MPLLCON The MPLL reference clock input is directly from the external clock input and the other PLL control inputs are connected to bits of the registers MPLLCON CLK BA 20 R W mpLL Control Register 0x0001_4035 Reserved Bits Descriptions 31 19 PLL OE FOUT enable pin Control 18 0 PLL FOUT enable 1 PLL FOUT is fixed low PLL Bypass Control 17 0 PLL is in normal mode default 1 PLL clock out
133. mer off PCR Setup the comparator register CMR Setup the counter register CNR Setup the interrupt enable register PIER Setup PWM output enables POE Enable PWM timer PCR O A 6 13 10 PWM Timer Stop Procedure Method 1 Set 16 bit down counter CNR as 0 and monitor PDR When PDR reaches to 0 disable PWM timer PCR Recommended Method 2 Set 16 bit down counter CNR as 0 When interrupt request happen disable PWM timer PCR Recommended Method 3 Disable PWM timer directly PCR Not recommended Nuvoton Technology Corp 179 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee 6 13 10 1 Capture Start Procedure 1 Setup clock selector CSR 2 Setup pre scale amp dead zone interval PPR 3 Setup inverter on off dead zone generator on off toggle mode one shot mode and PWM timer off PCR Setup the comparator register CMR Setup the counter register CNR Setup the capture register CCR Setup PWM output enables POE Enable PWM timer PCR sa dg ex 6 13 10 2 Capture Basic Timer Operation Reload Reload Capture Channel CFLR 1 x 3 CRLR D CAP INT At this case the CNR is 8 1 When set falling interrupt enable the PWM counter will be reload at time of interrupt occur 2 The channel low pulse width is CNT CRLR 3 The channel high pulse width is CRLR CFLR 4 The channel cycle time is CNR CFLR Nuvoton Technology Corp 180 Re
134. mer 3 output pin selection 1 output enable O output disable 24 PWM Timer 3 output to GPIOB 0 25 PWM Timer 3 output to GPIOB 4 26 PWM Timer 3 output to GPIOC 6 27 PWM Timer 3 output to GPIOC 10 28 PWM Timer 3 output to GPIOB 7 36 Revision A1 3 23 21 PWM_TMR2_I 20 16 PWM_TMR2_O 15 13 PWM_TMRI_I 12 8 PWM_TMR1_O 7 5 PWM_TMRO_I Nuvoton Technology Corp http www nuvoton com NUC501 PWM Timer 2 input pin selection 000 PWM Timer 2 input from GPIOA 15 001 PWM Timer 2 input from GPIOB 3 010 PWM Timer 2 input from GPIOC 5 011 PWM Timer 2 input from GPIOC 9 100 PWM Timer 2 input from GPIOB 6 Others disable PWM Timer 2 input function PWM Timer 2 output pin selection 1 output enable O output disable 16 PWM Timer 2 output to GPIOA 15 17 PWM Timer 2 output to GPIOB 3 18 PWM Timer 2 output to GPIOC 5 19 PWM Timer 2 output to GPIOC 9 20 PWM Timer 2 output to GPIOB 6 PWM Timer 1 input pin selection 000 PWM Timer 1 input from GPIOA 13 001 PWM Timer 1 input from GPIOB 2 010 PWM Timer 1 input from GPIOC 4 011 PWM Timer 1 input from GPIOC 8 100 PWM Timer 1 input from GPIOB 9 Others disable PWM Timer 1 input function PWM Timer 1 output pin selection 1 output enable O output disable 8 PWM Timer 1 output to GPIOA 13 9 PWM Timer 1 output to GPIOB 2 10 PWM Timer 1 output to GPIOC 4 11
135. mer has to write a number 0x a5eb1357 to INIR to release all of logic and counters INIR act as hardware reset circuit Nuvoton Technology Corp 203 Revision A1 3 http www nuvoton com nuvoTon NUC501 RTC Access Enable Register AER R W C Description _ Reset Value AER RTC_BA 0x004 R w RTC Access Enable Register 0x0000_0000 Ca l a l NEUE INIM INN INE UN Reserved Ca a Tjj NA e Reserved Descriptions DEU RTC Register Access Enable Flag Read only 1 RTC register read write enable 16 0 RTC register read write disable This bit will be set after AER 15 0 register is load a 0xA965 and be clear automatically in a long time or AER 15 0 is not OxA965 RTC Register Access Enable Password Write only 15 0 OxA965 access enable Others access disable Nuvoton Technology Corp 204 Revision A1 3 http www nuvoton com nuvoTon NUC501 ES ee RTC Frequency Compensation Register FCR Register Address R W C Description Reset Value CS ee eee UN Reserved MN II ee Reserved Reserved INTEGER 03 5 CO IE II 12 13 1 FRACTION Bits Beier 31 12 Integer Part value E value 327760 di 132768 o i8 INTEGER 7a Fraction Part 5 0 FRACTION Formula fraction part of detected value x 60 Note Digit in FCR must be expressed as hexadecimal number Nuvoton Technology Corp 205 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee RTC Time Loading R
136. nagement modes normal idle power down with RTC and power down e 3 3V to 1 8V 200mA LDO regulator e Software Support e GNU based open source IDE compiler linker and debugger e Technology amp Package e 0 18um CMOS e 3 3 volt single supply e LQFP 48 NUCBO1ADN LQFP 64 NUC501BDN Nuvoton Technology Corp 8 Revision A1 3 http www nuvoton com nuvoTon NUC501 OO _ F Fryv 3 Pad and Pin Configuration SPIMO_SS GPA 8 SPIMO_SCK GPA 9 SPIMO_SO SZ i 26 _ 25 DVSS PA 10 SPIMO_SI DVDD33 PA 11 SPIMS_SI VCC_CORE PA 12 SPIMS_SO PWMTO VPP PA 13 SPIMS_SCK PWMT1 AO_VREF18 PA 14 SPIMS_SS AO_OUT PA 15 PWMT2 I2C DATA AO_VREF N UC501 ADN PB O PWMT3 I2C CLK AVSS PB 1 PWMTO UARTO TXD AVDD33 PB 2 PWMT 1 UARTO_RXD GPA 0 AI 0 MICP PB 3 PWMT2 UARTO CTS GPA 1 AI 1 MICN PB 4 PWMT3 UARTO RTS GPALZ AIR O vss a TA a E e 0 Q e se Ur wm Ee eo A 1 2 1 2 M6 2 Y E a es X qe Ss Ss o 5 5 E ce 6 6 2 bb A amp X cor 95 O 00 0 gt Xx E Bo T E O gt x F gt e m m on LO D amp D mq c 9 m B O A o O 0 E ea A O LQFP 48 Pin Out Nuvoton Technology Corp 9 Revision A1 3 http www nuvoton com nuvoTon e lt lt lt amp DVSS DVDD33 VCC_CORE VPP AO_VREF18 AO_OUT AO_VREF AVSS AVDD33 GPC 5 PNMT2 UART1_TXD GPC 6 PWMT3 UAR
137. ndefined UA FCR LA MCR UART_BA 0x10 RAV Modem Contro Register 00000 0000 wm umt sa Dda R Une status Registe neen UA_MSR ART_BA 0x18 R W Modem Status Register 00000 0000 Nuvoton Technology Corp 245 Revision A1 3 http www nuvoton com nuvoTon NUC501 Receive Buffer Register UA_RBR UA_RBR UA_BA 0x00 DURO Receive Buffer Register DLAB 0 Undefined Reserved Reserved cs I5 I5 RSC Reserved paia LA 8 bit Received Data Bits Descriptions CCOO 8 bit Received Data By reading this register the UART will return an 8 bit data received from SIN pin LSB first Nuvoton Technology Corp 246 Revision A1 3 http www nuvoton com nuvoTon NUC501 Transmit Holding Register UA_THR UA_THR UA_BA 0x00 Transmit Holding Register DLAB 0 Undefined Reserved Reserved cs I5 I5 RSC Reserved gia LA 8 bit Transmitted Data Bits Descriptions CCOO 8 bit Transmitted Data By writing to this register the UART will send out an 8 bit data through the SOUT pin LSB first Nuvoton Technology Corp 247 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Interrupt Enable Register UA_IER UA IER UA BA 0x04 Interrupt Enable Register DLAB 0 0x0000 0000 Reserved 5 1 5 I e offs Ts Reserved o7 e J 5 4 3 2 o Wake o 18 WakelE nDBGACK_EN rro MSIE reste THREIE ROAIE_ Bits Descriptions 31 8 Wake
138. nterrupt2 25 INT_PWM3 SCR7 15 8 PWM Interrupt3 26 INT I2C SCR7 23 16 I2C Interface Interrupt 27 INT SPIMS SCR7 31 24 SPI Master Slave Serial Interface LOW Interrupt TMRO MRI var varto RIE Abc 07 ys 5s 4 3 2 7 0 A cros erroz erro Gero0 wor _ Nuvoton Technology Corp 115 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee 6 10 4 AIC Functional Descriptions Hardware Interrupt Vectoring The hardware interrupt vectoring can be used to shorten the interrupt latency If not used priority determination must be carried out by software When the Interrupt Priority Encoding Register AIC_IPER is read it will return an integer representing the channel that is active and having the highest priority This integer is equivalent to multiplied by 4 shifted left two bits to word align it such that it may be used directly to index into a branch table to select the appropriate interrupt service routine vector Priority Controller An 8 level priority encoder controls the NIRQ and NFIQ line Each interrupt source belongs to priority group between of 0 to 7 Group 0 has the highest priority and group 7 the lowest Group 0 means FIQ mode group When more than one unmasked interrupt channels are active at a time the interrupt with the highest priority is serviced first If all active interrupts have equal priority the interrupt with the lowest interrupt source numb
139. o clock dividers Four clock selectors Four 16 bit counters and four 16 bit comparators Two Dead Zone generator Capture function 6 13 3 PWM Timer Start Procedure 1 Setup clock selector CSR 2 Setup prescale amp dead zone interval PPR di Setup inverter on off dead zone generator on off toggle mode one shot mode and PWM timer off PCR 4 Setup comparator register CMR Di Setup counter register CNR 6 Setup interrupt enable register PIER 7 Setup pwm output enable POE 8 Enable PWM timer PCR Nuvoton Technology Corp 173 Revision A1 3 http www nuvoton com nuvoTon NUC501 ee 6 13 4 PWM Architecture PWM_OE 0 enable gt timer PWMO output gt GPA 12 or GPB 1 or GPB 8 or GPC 3 or GPC 7 PWM_OE 1 enable gt timer PWM1 output gt GPA 13 or GPB 2 or GPB 9 or GPC 4 or GPC 8 PWM_OE 2 enable gt timer PWM2 output gt GPA 15 or GPB 3 or GPB 6 or GPC 5 or GPC 9 PWM_OE 3 enable gt timer PWM3 output gt GPB 0 or GPB 4 or GPB 7 or GPC 6 or GPC 10 timer output GPIO pin select by PAD Control register PAD_REGO The following figure describes the architecture of PWM in one group Timer 081 are in one group and timer 283 are in another group DZIO Dead Zone Generator pwm_clk Dead Zone CNRO CMRO PWMO gt Control Logic 8 bit Dead Zone Pre scale CPO CNR1 CMRI PWM1 gt Control p Logic Nuvoton Technology Corp 174 Revision A1
140. ock input for timer O Table is the same as CSR3 Nuvoton Technology Corp 183 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee PWM Control Register PCR Register Offset R W Description ResetValue 31 3e 39 238 z 6 ATA Reserved CH3MOD CHSINV Reserved CH3EN 33 zz zi 29 19 18 1 36 Reserved CH2MOD CHZINV Reserved CH2EN _ as 34 1 mm u 1 9 8 Reserved CHIMOD CHIINV Reserved CHIEN _ 037 s 5 7 4 3s 2 3 9 Reserved DZENi DZENO CHOMOD CHOINV Reserved CHOEN Bits Descriptions 31 26 Timer 3 Toggle One Shot Mode 1 Toggle Mode 27 0 One Shot Mode NOTE If there is a rising transition at this bit it will cause CNR3 and CMR3 be clear Timer 3 Inverter ON OFF 26 CH3INV 1 Inverter ON 0 Inverter OFF as Timer 3 Enable Disable 24 1 Enable 0 Disable 23 20 Timer 2 Toggle One Shot Mode 1 Toggle Mode 19 0 One Shot Mode NOTE If there is a rising transition at this bit it will cause CNR2 and CMR2 be clear Timer 2 Inverter ON OFF 18 CH2INV 1 Inverter ON 0 Inverter OFF Tu 16 CH2EN Timer2 Enable Disable Nuvoton Technology Corp 184 Revision A1 3 http www nuvoton com nuvoTon NUC501 1 Enable 0 Disable eg Timer 1 Toggle One Shot Mode 1 Toggle Mode 11 0 One Shot Mode NOTE If there is a rising transition at this bit it will cause CNR1 and CMR1 be clear
141. oint 1 0x0000_0000 MXPLD1 USB_BA 0x034 R W Maximal payload of endpoint 1 0x0000_0000 CFG1 USB_BA 0x038 R W Configuration of endpoint 1 of endpoint 1 0x0000_0000 0000 O trol ter and In out ready clear fl CFGP1 USB_BA 0x03C R w Stall contro register and In out ready clear flag 20009 0000 of endpoint 1 BUFSEG2 USB_BA 0x040 R W Buffer Segmentation of endpoint 2 0x0000_0000 MXPLD2 USB_BA 0x044 R W Maximal payload of endpoint 2 0x0000_0000 CFG2 USB_BA 0x048 R W Configuration of endpoint 2 0x0000_0000 tall control register and In out ready clear fl CFGP2 Use BAXOxDAC RAW control register and In out ready clear flag 5 0000 0000 of endpoint 2 BUFSEG3 USB_BA 0x050 R W Buffer Segmentation of endpoint 3 0x0000_0000 MXPLD3 USB_BA 0x054 R W Maximal payload of endpoint 3 0x0000_0000 CFG3 USB_BA 0x058 R W Configuration of endpoint 3 0x0000_0000 Il control register and in out ready clear fl CFGP3 USB_BA 0x05C R w Stall control register and In out ready clear flag o 2009 0000 of endpoint 3 BUFSEG4 USB_BA 0x060 R W Buffer Segmentation of endpoint 4 0x0000_0000 MXPLD4 USB_BA 0x064 R W Maximal payload of endpoint 4 0x0000_0000 CFG4 USB_BA 0x068 R W Configuration of endpoint 4 0x0000_0000 Il control register and in out ready clear fl CFGP4 USB BA 0x06C R w Stall control register and In out ready clear flag 20099 0000 of endpoint 4 Nuvoton Technology Corp 97 Revision A1 3 http www nuvoton com NUVOTON
142. om GPC 0 USB connection detect pin from GPC 1 USB connection detect pin from GPC 2 USB connection detect pin from GPC 3 USB connection detect pin from GPC 4 disable 4 Revision A1 3 nuvoTon NUC501 EE i iii GPIOA driving strength GPA_DS GPA_DS GCR_BA 74 GPIOA driving strength 0x0000_0000 Reserved Reserved o5 o4 1 35 1 2 H 39 3 GPA DS 15 8 Lo 0 9 9 jJ ce j 9 qo 27 J d i GPA DS 7 0 Bits Descriptions GPIOA driving strength 15 0 0 4mA driving strength IO 1 8mA driving strength IO Nuvoton Technology Corp 42 Revision A1 3 http www nuvoton com nuvoTon NUCS501 GPIOB driving strength GPB_DS GPB_DS GCR_BA 78 GPIOB driving strength 0x0000_0000 Reserved i5 TS 3 3 9 8 Ts IG 3 2 NAAA GPB_DS 7 0 Bits Descriptions GPIOB driving strength 0 and 9 0 4mA driving strength IO 9 0 GPB_DS 1 8mA driving strength IO others O 12mA driving strength IO 1 16mA driving strength IO Nuvoton Technology Corp 43 Revision A1 3 http www nuvoton com nuvoTon NUC501 EE i iii GPIOC driving strength GPC_DS GPC_DS GCR_BA 7C GPIOC driving strength 0x0000 0000 Reserved Reserved o5 o4 35 1 2x H 3 3 Reserved GPC DS 10 8 o Le qs lai d 9 2 pcc e _ GPC DS Z7 0 Bits Descriptions GPIOC driving strength 10 0 0 4mA driving strength IO 1 8mA driving strength IO Nuvo
143. ommand e O No effect e 1 Enables the corresponding interrupt channel 31 0 MECx Nuvoton Technology Corp 129 Revision A1 3 http www nuvoton com nuvoTon NUC501 AIC Mask Disable Command Register AIC_MDCR AIC_MDCR AIC_BA 124 Mask Disable Command Register Undefined MDC 7 0 Bits Descriptions Mask Disable Command e O No effect e 1 Disables the corresponding interrupt channel 31 0 MDCx Nuvoton Technology Corp 130 Revision A1 3 http www nuvoton com nuvoTon NUC501 AIC Source Set Command Register AIC_SSCR AIC_SSCR AIC_BA 128 Source Set Command Register Undefined SSC 7 0 When the NUC501 is under debugging or verification software can activate any interrupt channel by setting the corresponding bit in this register This feature is useful in hardware verification or software debugging Bits Descriptions Source Set Command 31 0 SSCx e O No effect e Activates the corresponding interrupt channel Nuvoton Technology Corp 131 Revision A1 3 http www nuvoton com nuvoTon NUC501 AIC Source Clear Command Register AIC_SCCR AIC_SCCR AIC_BA 12C Source Clear Command Register Undefined SCC 7 0 When the NUC501 is under debugging or verification software can deactivate any interrupt channel by setting the corresponding bit in this register This feature is useful in hardware verification or software NM Bits Descriptions Source Clear Command 31
144. on NUC501 SS eee PWM Comparator Register 3 0 CMR3 0 CMRO PWM_BA 0x010 R W PWM Comparator Register 0 0x0000_0000 CMRi PWM_BA Ox01C R W PWM Comparator Register 1 Ox0000 0000 CMR2 PWM_BA 0x028 R W PWM Comparator Register 2 0Ox0000 0000 CMR3 PWM_BA 0x034 R W PWM Comparator Register 3 0x0000_0000 31 30 29 28 27 26 25 24 AS A LI ASA ASA A S 15 14 13 12 n 10 9 8 A EAS NAS Lo A E SA Descriptions ais PWM Comparator Register Inserted data range 65535 0 Unit 1 PWM clock cycle CMR are used to determine PWM output duty ratio Assumption PWM output initial high CMR gt CNR PWM output is always high 15 0 CMR lt CNR PWM output high gt CMR 1 unit CMR 0 PWM output high gt 1 unit Note PWM duty CMR 1 1 If CMR equal zero PWM duty 1 Note Programmer can feel free to write a data to CMR at any time and it 2 will take effect in next cycle Nuvoton Technology Corp 187 Revision A1 3 http www nuvoton com nuvoTon NUC501 PWM Data Register 3 0 PDR 3 0 PDRO PWM BA Ox014 R PWM Data Register 0 0x0000_0000 PWM BA 0x020 R PWM Data Register 1 0x0000_0000 PWM BA O0x02C R PWM Data Register 1 0x0000_0000 PDR3 PWM BA 0x038 R PWM Data Register 1 0x0000_0000 31 30 29 23 27 26 235 24 Reserved Ti CH AS AAA AS ee EN Reserved PDR 15 8 NAS ee eee A E ii PDR 7 0 Descriptions 15 0 e rr
145. only on SOUT and has no effect on the transmitter logic Stick Parity Enable e O Disable stick parity e 1 Parity bit is transmitted and checked as a logic 1 if bit 4 is O odd parity or as a logic 0 if bit 4 is 1 even parity This bit has effect only when bit 3 parity bit enable is set Even Parity Enable e 0 Odd number of logic 1 s are transmitted or checked in the data word and parity bits e 1 Even number of logic 1 s are transmitted or checked in the data word and parity bits This bit has effect only when bit 3 parity bit enable is set Nuvoton Technology Corp 256 Revision A1 3 http www nuvoton com nuvoTon NUC501 Parity Bit Enable e 0 Parity bit is not generated transmit data or checked receive data during transfer e 1 Parity bit is generated or checked between the last data word bit and stop bit of the serial data Number of STOP bit e 0 One STOP bit is generated in the transmitted data e 1 One anda half STOP bit is generated in the transmitted data when 5 bit word length is selected Two STOP bit is generated when 6 7 and 8 bit word length is selected Word Length Select 09 sw Nuvoton Technology Corp 257 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee MODEM Control Register UA_MCR UA_MCR UA BA 0x10 MODEM Control Register 0x0000 0000 Reserved Reserved 5s Ts Ts Te I 3 I 9 Ts I Reserved 7 I SL ES
146. oton Technology Corp 232 Revision A1 3 http www nuvoton com nuvoTon NUC501 Interrupt Control Functions Priority Interrupt Type Interrupt Source Interrupt Reset Lo None oe Overrun error parity error Receiver Line Status Lapi d 0110 Highest INTR RLS Henning error or break Reading the UA LSR interrupt Receiver FIFO drops 0100 Second Received Data Available Receiver FIFO threshold be laut si INTR_RDA level is reached level Receiver FIFO is non empty and no activities are Recei FIFO Time out 1100 Second NM vie E occurred in the receiver Reading the UA RBR Hu FIFO during the UA TOR defined time duration Reading the UA IIR if Transmitter Holing A aeu l E Transmitter holding register source of interrupt is 0010 Third Register Empty o INTR_THRE empty INTR_THRE or writing into the UA_THR The CTS DSR or DCD bits MODEM Status are changing state or the 0000 Fourth Reading the MSR INTR_MOS RI bit is changing from high 9 to low Notel The definition of bit 7 bit 6 bit 5 and bit 4 is different from the 16550 Note2 Only CTS CTS can be used in this version Nuvoton Technology Corp 253 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee FIFO Control Register UA_FCR UA FCR UA BA 0x08 w FIFO Control Register Undefined Reserved Reserved 5 Tse Ts Te I 3 I 5 gt I s Reserved 7 es fs fo DE 7 9 RITE serves Tm mm DE Bits
147. ould be referred to when consider the following steps in detail 1 Write a divisor into DIVIDER to determine the frequency of serial clock 2 Write in SSR set ASS 0 SS_LVL 0 and SSR 0 or SSR 1 to 1 to activate the device to be accessed When transmit write data to device 3 Write the data to be transmitted into TxO 7 0 When receive read data from device 4 Write OxFFFFFFFF into Tx0 5 Write in CNTRL set SLAVE 0 CLKP 0 Rx NEG 0 Tx NEG 1 Tx BIT LEN 0x08 Tx NUM 0x0 LSB 0 SLEEP 0x0 and GO BUSY 1 to start the transfer Wait for interrupt if IE 1 or polling the GO BUSY bit until it turns to O 6 Read out the received data from RxO 7 Go to 3 to continue another data transfer or set SSR O or SSR 1 to O to inactivate the device When using this SPI controller as a slave device and connected to a master device suppose the external master device accesses the on chip SPI interface with the following specifications e Data bit latches on positive edge of serial clock Data bit drives on negative edge of serial clock Data is transferred with the LSB first SCLK idle high Only one byte transmits receives in a transfer Chip select signal is active high trigger Basically the following actions should be done also the specification of the connected master device should be referred to when consider the following steps in detail 1 Write in SSR set SS_LVL 1 Nuvoton Technology Corp
148. ound Pin for analog circuit Nuvoton Technology Corp 18 Revision A1 3 http www nuvoton com nuvoTon NUC501 4 System Diagram 32 768kHz 12MHz ywueso4 11 Po Battery LDV LVR 32KB SRAM OTP Security 37 GPIO s Mar EN 4 5 6 gp x oi Sensor V Keypad LED MIC System Block Diagram Nuvoton Technology Corp 19 Revision A1 3 http www nuvoton com nuvoTon 5 Block Diagram 5 1 System block diagram JJ C TIMER UARTx2 PWM O GPIO SPIMS I2C Nuvoton Technology Corp http www nuvoton com NUC501 Internal SRAM ADC 8ch 10b Audio SARADC DAC Mono LVD LDR 16 bits DAC 20 Revision A1 3 nuvoTon NUC501 5 2 On Chip Bus block diagram NUC501 Bus Block Diagram ARM 7TDMI USBPHY CLKCTL PLL e LDO RAPP mm we NN uw MISC Mono WRAPPER I 16 bits DAC APB Bridge 6K Byte ROM 32K Byte SRAM ADC ADC 8ch 10b SARADC LVD LDR UARTO TT UAI wm n Nuvoton Technology Corp 21 Revision A1 3 http www nuvoton com NUVOTOM NUC501 Sor 6 Functional Description 6 1 ARMZTDMI CPU Core The ARM7TDMI CPU core a member of the Advanced RISC Machines ARM family of general purpose 32 bit microprocessors offers high performance with very low power consumption The architecture is based on Reduced Instruction Set Computer RISC principles and the instruction set and related decod
149. ounter that it will generate a STORBE signal to DAC whenever the counter reaches 128 This makes DAC to output the audio data with correct sampling rate 6 5 4 APU Run Procedures 1 Setup clock source e If the PLL output frequency set by MPLLCON is 160Mhz and you the sample rate of input data is 48KHz the AUDIO DAC clock should be set to 6 144Mhz Therefore CLKSEL 5 4 and CLKDIVO 15 8 should be set a proper value to divide the clock source by about 26 166 6 144 We my set CLKSEL 5 4 2 b01 and set CLKDIVO 15 8 0x19 Nuvoton Technology Corp 76 Revision A1 3 http www nuvoton com NUVOTON NUCSO1 ee ii 2 Set base address and threshold addresses e The APU implement the ping pong buffer mechanism and the buffers are consecutive You can set the start address of first buffer in BSAD register set the end address of fist buffer in THAD1 register and set the end address of second buffer in THAD2 register Remember to set APUINT register to enable threshold 1 2 interrupts If the registers are set properly every time the APU reach the end of each one buffer it will issue an interrupt and then you can update the buffer 3 Reset APU before start e Set bit 16 of APUCON register to 1 and then set it to O again This action will reset internal buffers and registers Remember to do this step before you start to run APU 4 Start APU e Set bit O of APUCON register to 1 This makes APU start to transfer audio data from buffer to DAC
150. ple if set one pin for rising user must keep this pin low while start to enter power down a high level will make power down entrance be ignored After entering power down a high level at this pin will make chip leave power down NOTES When use a pin as power down wake up source if both edges are set the high level will be set as wake up level Nuvoton Technology Corp 149 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee GPIO C Interrupt Enable IRQENGPC IRQENGPC GP BA 0x98 R W GPIO Port C Interrupt Enable 0x0000 0000 po Reserved PCiOENR PCOENR PCSENR PC7ENR PCGENR PCSENR PC4ENR PC3ENR PC2ENR PCIENR PCOENR_ 15 14 13 12 11 10 9 8 Reserved PCiOENF PCOENF PCSENF 72 6 5 4 3 2 1 0 D PC7ENF PCGENF PCSENF PC4ENF PC3ENF PC2ENF PCIENF PCOENF_ Bits Descri ptions Enable GPCx input falling edge to trigger one of interrupt sources IRQO IRQ3 IRQSRCGPC register determines which IRQn n 20 3 is the destination x 16 Enable GPCx input rising edge to trigger one of interrupt sources IRQO IRQ3 IRQSRCGPC register determines which IRQn n 0 3 is the destination Where x 0 15 PCXENF and PCxENR can be set 1 at the same time NOTE1 In normal operation mode for each pin PCXENF and PCxENR can be set both to detect both rising and falling edge NOTE2 When use a pin as powerdown wake up source the setting of edges must be expla
151. presents the interrupt channel number that is active enabled and has the highest priority If the representing interrupt channel possesses a priority level O then the interrupt asserted is FIQ mode otherwise it is IRQ mode The value of VECTOR is copied to the register AIC ISNR thereafter by the AIC This register is restored a value O after it was read by the interrupt handler This register can help indexing into a branch table to quickly jump to the corresponding interrupt service routine The reserved bits are set to zero Bits Descriptions Interrupt Vector e 0 no interrupt occurs 6 2 VECTOR e 1 31 representing the interrupt channel that is active enabled and having the highest priority Nuvoton Technology Corp 125 Revision A1 3 http www nuvoton com nuvoTon NUC501 ES ee AIC Interrupt Source Number Register AIC_ISNR AIC_ISNR AIC_BA 110 OR Interrupt Source Number Register 0x0000_0000 Reserved Reserved 5 4 3 I I 3 1 591 5 I Reserved 7 eo 5 3 2 3 o Reserved a The purpose of this register is to record the interrupt channel number that is active enabled and has the highest priority The reserved bits are set to zero Descriptions 4 0 IRQ Identification Stands for the interrupt channel number Nuvoton Technology Corp 126 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee AIC Interrupt Mask Register AIC_IMR AIC_IMR AIC_BA 114 MES Interrupt
152. put is same as clock input XTALin Power Down Mode 16 0 PLL is in normal mode default LEN 1 PLL is in DONI down mode IN DV PLL Input Divider Control Pins PLL R A 0 e FB DV PLL Feedback Divider Control Pins PLL F 6 0 Output Clock Frequency Setting Nuvoton Technology Corp 56 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee FOUT FIN x E X 1 NR NO Constrain 1 3 2MHz lt FIN lt 150MHz 2 800KHz lt PM lt 8MHZ NR 200MHz lt FCO FIN x Vs 500M Hz 250M Hz FCO 1s preferred FOUT Output Clock Frequency F Input Reference Clock Frequency NR Input Divider 2 x IN DV 2 NF Feedback Divider 2 x FB_DV 2 IN NR NF NO OUT DV 00 OUT DV 01 OUT DV 10 OUT DV 2 11 Default Setting The default value 0x4035 FIN 12 MHz NR 2 x 0 2 4 NF 2 x 53 2 110 NO 2 FOUT 12 4 x 110 x 1 2 165 MHz Nuvoton Technology Corp 57 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee 6 4 SPI Synchronous Serial Interface Controller Master Mode 6 4 1 Overview The SPI Synchronous Serial Interface controller performs a serial to parallel conversion on data received from the peripheral and a parallel to serial conversion on data received from CPU This controller can drive up to 2 external peripherals and is seen as the master It can generate an interrupt signal when data transfer is finished and can be cleared
153. r 87 6 6 1 Overview 87 6 6 2 Features 87 6 6 3 SRAM Block Diagram 88 6 6 4 SRAM System Diagram 89 6 6 5 SRAM Function Description 90 6 6 6 SRAM Register Mapping 91 6 7 USB Device Controller 94 6 7 1 Overview 94 6 7 2 Features 94 6 7 3 Functional Descriptions 95 6 7 4 Memory Mapping 96 6 7 5 USB Control Registers Mapping 97 6 9 Advanced Interrupt Controller 113 6 9 1 Overview 113 6 9 2 Features 113 6 9 3 Interrupt Sources 114 6 9 4 AIC Functional Descriptions 116 6 9 5 AIC Registers Mapping 118 6 9 6 AIC Control Registers 120 6 10 General Purpose I O 134 6 10 1 Overview and Features 134 6 10 2 GPIO Control Register Mapping 135 6 10 3 GPIO Control Register Description 136 6 11 12C Synchronous Serial Interface 157 6 11 1 Overview 157 6 11 2 Feature 157 6 11 3 CC Protocol 158 6 11 4 IC Programming Examples 160 6 11 5 Software IC Operation 162 6 11 6 IFC Serial Interface Control Registers Mapping 164 6 12 PWM Timer 172 6 12 1 Introduction 172 6 12 2 Features 173 6 12 3 PWM Timer Start Procedure 173 6 12 4 PWM Architecture 174 6 12 5 Basic Timer Operation 176 Nuvoton Technology Corp 3 Revision A1 3 nuvoTon NUC501 TT 6 12 6 PWM Double Buffering and Automatic Reload 176 6 12 7 Modulate Duty Ratio 177 6 12 8 Dead Zone Generator 178 6 12 9 PWM Timer Start Procedure 179 6 12 10 PWM Timer Stop Procedure 179 6 12 11 PWM Timer Register Mapping 181 6 13 Register Description 182 6 14 Real Time Clock RTC 199 6 14 1 Overview 199
154. r interrupt is enabled the timer asserts its interrupt signal when the associated counter is equal to TICR Timer Operating Mode MODE Timer Operating Mode The timer is operating in the one shot mode The associated ient signals generated once IE enabled and CEN Nuvoton Technology Corp 231 Revision A1 3 http www nuvoton com nuvoTon NUC501 is automatically cleared then The timer is operating in the periodic mode The associated interrupt signal is generated periodically if IE is enabled The timer is operating in the toggle mode The interrupt signal is generated periodically if IE is enabled And the associated signal tout is changing back and forth with 50 duty cycle The timer is operating in the uninterrupted mode The associated interrupt signal is generated when TDR TICR if IE is enabled Counter Reset Set this bit will reset the TIMER counter and also force CEN to 0 No effect Reset Timer s pre scale counter internal 32 bit counter and CEN Timer is in Active This bit indicates the counter status of timer e O Timer is not active e 1 Timer is in active Pre scale 7 PRESCALE SE Se Clock input is divided by Prescale 1 before it is fed to the counter If Pre scale 0 then there is no scaling Nuvoton Technology Corp 292 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Timer Initial Count Register O 1 TICRO TICR1 TICRO TMR_BA 008
155. r the CPU reads the contents of the UA_LSR UA LSR 4 1 BII FEI PEI OEI are the error conditions that produce a receiver line status interrupt INTR_RLS when UA_IER 2 1 Reading UA_LSR clears INTR_RLS Writing UA_LSR is a null operation not suggested Nuvoton Technology Corp 260 Revision A1 3 http www nuvoton com nuvoTon NUC501 Modem Status Register UA_MSR UA_MSR UA_BA 0x18 R W Modem Status Register 0x0000_0000 Reserved Reserved cs I5 I 5 I2 Is EI E IEC Reserved 07 I Ts TJ Bits Descriptions CTS Complement version of Clear to Send CTS input CTS State Change 0 DCTS This bit is set whenever CTS input has change state it will be reset if the CPU reads the MSR Note Only CTS RTS can be used in this version Whenever any of MSR 3 0 is set to logic 1 a Modem Status Interrupt is generated if IE 3 1 Writing MSR is a null operation not suggested Nuvoton Technology Corp 261 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Time out Register UA_TOR UA TOR UA BA 0x1C Time Out Register 0x0000_0000 Reserved Reserved cs STO Ts IG LS I GI IIG ICI CI Ic IG IG IG I c pene se Descriptions DEI Time Out Interrupt Comparator The time out counter resets and starts counting the counting clock baud rate whenever the RX FIFO receives a new data word Once the content of time out counter TOUT_CNT is equal to that of time out
156. receive acknowledge from slave 4 generate repeated start signal 5 write slave address read bit then receive acknowledge from slave 6 read byte from slave 7 write not acknowledge NACK to slave indicating end of transfer 8 generate stop signal Nuvoton Technology Corp 161 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Commands 1 Write a value into DIVIDER to determine the frequency of serial clock 2 Set Tx NUM 0x0 and set I2C EN 1 to enable I C core 3 Write Ox9C address write bit to TxR 7 0 set START bit and WRITE bit Wait for interrupt or I2C TIP flag to negate 4 Read I2C RxACK bit from CSR Register it should be 0 5 Write 0x20 to TxR 7 0 set WRITE bit Wait for interrupt or I2C TIP flag to negate 6 Read I2C RxACK bit from CSR Register it should be O 7 Write Ox9D address read bit to TxR 7 0 set START bit set WRITE bit Wait for interrupt or I2C TIP flag to negate 8 Read I2C RxACK bit from CSR Register it should be O 9 Set READ bit set ACK to 1 NACK set STOP bit 10 Read out received data from RxR it will put on RxR 7 0 be First command sequence Q Second command sequence P Third command sequence Fourth command sequence NOTE Please note that the time for the Interrupt Service Routine is not shown here It is assumed that the ISR is much faster then the DC cycle time
157. red This allows the AIC to assert the NIRQ line again when a higher priority unmasked interrupt occurs The AIC_EOSCR End of Service Command Register must be written at the end of the interrupt service routine This permits pending interrupts to be serviced Interrupt Masking Nuvoton Technology Corp 116 Revision A1 3 http www nuvoton com nuvoTon NUC501 ES _e e lt lt lt lt lt lt Each interrupt source can be enabled or disabled individually by using the command registers AIC_MECR and AIC_MDCR The status of interrupt mask can be read in the read only register AIC_IMR A disabled interrupt doesn t affect the servicing of other interrupts Interrupt Clearing and Setting All interrupt sources can be individually set or clear by respectively writing to the registers AIC_SSCR and AIC_SCCR when they are programmed to be edge triggered This feature of the AIC is useful in auto testing or software debugging Fake Interrupt When the AIC asserts the NIRQ line the processor enters interrupt mode and the interrupt handler reads the AIC_IPER it may happen that interrupt sources de assert NIRQ lines after the processor has taken into account the NIRQ assertion and before the read of the AIC_IPER This behavior is called a fake interrupt The AIC is able to detect these fake interrupts and returns all zero when AIC_IPER is read The same mechanism of fake interrupt occurs if the processor reads the AIC_
158. resented to the CPU RX_FIFO The receiver is buffered with a 64 16 byte FIFO plus three error bits per byte to reduce the number of interrupts presented to the CPU TX shift Register Shifting the transmitting data out serially RX shift Register Shifting the receiving data in serially Modem Control Register This register controls the interface to the MODEM or data set or a peripheral device emulating a MODEM Modem Status Register This register provides the current status of the control lines from the MODEM and cause the MODEM status interrupt CTS or DSR or RI or DCD Note Only CTS RTS can be used in this version Baud Rate Generator Dividing the external clock by the divisor to get the desired internal clock Nuvoton Technology Corp 240 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Control and Status Register This is a register set including the FIFO control registers FCR FIFO status registers FSR and line control register LCR for transmitter and receiver The line status register LSR provides information to the CPU concerning the data transfer The time out control register TOR identifies the condition of time out interrupt This register set also includes the interrupt enable register IER and interrupt identification register IIR to enable or disable the responding interrupt and to identify the occurrence of the responding interrupt There are four types of interrupts line status inter
159. rial Bus USB performs a serial interface with a single connector type for attaching all USB peripherals to the host system Following is the feature list of this USB e Conforming to USB2 0 full speed device e Full Speed 12Mbps e Provide 1 interrupt source with 4 interrupt events e Support Control Bulk In Out Interrupt and Isochronous transfers e Suspend when no bus signaling for 3 ms e Provide 6 endpoints e Include 512 Bytes internal SRAM as USB buffer e Provide remote wakeup capability Nuvoton Technology Corp 94 Revision A1 3 http www nuvoton com nUvoTon NUCSO1 TT 6 7 3 Functional Descriptions 6 7 3 1 SIE Serial Interface Engine The SIE is the front end of the device controller and handles most of the USB packet protocol The SIE typically comprehends signaling up to the transaction level The functions that it handles could include Packet recognition transaction sequencing SOP EOP RESET RESUME signal detection generation Clock Data separation NRZI Data encoding decoding and bit stuffing CRC generation and checking Token and Data Packet ID PID generation and checking decoding Serial Parallel Parallel Serial conversion 6 7 3 2 UIE The UIE is the endpoints management All the operations include Control Bulk Interrupt and Isochronous transfer are implemented in it 6 7 3 3 Digital Phase Lock Loop The bit rate of USB data is 12MHz The DPLL use the 48MHz which come
160. rp 106 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Buffer Segmentation Register BUFSEG For Setup token only BUFSEG USB_BA 0x018 R W Buffer segmentation 0x0000_0000 de A SA ee Reserved Reserved Reserved 03 s 7s 4 1 3 3 9 Ae e Descriptions 8 3 For Setup token only l Effective starting address USB buffer BUFSEG 8 3 3 b000 Nuvoton Technology Corp 107 Revision A1 3 http www nuvoton com nuvoTon NUC501 Buffer Segmentation Register BUFSEGx x 0 5 BUFSEG4 USB BA 0x060 R W X Buffer segmentation of endpoint 4 0x0000 0000 BUFSEG5 USB BA 0x070 R W Buffer segmentation of endpoint 5 0x0000 0000 Oa MEM a eee ee Reserved Reserved 37 6 184 18 a Tia o SCC me peseriptions 31 9 8 3 BUFSEGX Effective starting address USB buffer BUFSEGx 8 3 3 b000 Nuvoton Technology Corp 108 Revision A1 3 http www nuvoton com nuvoTon NUC501 Maximal Payload Register MXPLDx x 0 5 MXPLDO USB_BA 0x024 R W Maxima Payload of endpoint 0 0x0000_0000 MXPLD1 USB_BA 0x034 R W Maximal Payload of endpoint 1 0x0000_0000 MXPLD2 USB_BA 0x044 R W Maximal Payload of endpoint 2 0x0000_0000 MXPLD3 USB_BA 0x054 R W Maximal Payload of endpoint 3 0x0000_0000 MXPLD4 USB_BA 0x064 R W Maximal Payload of endpoint 4 0x0000_0000 MXPLD5 USB_BA 0x074 R W Maximal Payload of endpoint 5 0x0000_0000 EEE ee E ee ee Reserved EA 2 L_a
161. rupt overrun error or parity error or framing error or break interrupt transmitter holding register empty interrupt receiver threshold level reaching and time out interrupt Nuvoton Technology Corp 241 Revision A1 3 http www nuvoton com nuvoTon 6 18 5 Finite State Machine 6 18 5 1 Transmitter count F ITXDATIA END x eu amp count F PARITY amp TXDATA END IPARITY amp TXDATA_END State Definition IDLE The transmitter has no data to transmit WAIT The transmitter s FIFO is not empty START The transmitter transmits the start bit TX The transmitter transmits the data PARITY The transmitter transmits the parity bit STOP The transmitter transmits the stop bit Signal Description THRE Te transmitter holding register is empty Count7 The counter of clock equals to 7 Nuvoton Technology Corp 242 http www nuvoton com NUC501 Revision A1 3 nuvoTon NUC501 EE CountF The counter of clock equals to 15 TXDATA_END The data part transfer is finished PARITY The transfer includes the parity bit NOTE The format of the transfer is as following One transfer START DATA Parity bit if dedicated Stop bit 6 18 5 2 Receiver Istart detect start detect SIN syn2 amp ISIN syn2 count 7 RXDATA END amp Parity amp count F count F start_detect stor IRXDATA EN D amp count F RXDATA_END amp
162. s been granted access 6 2 4 2 Rotate rule Example In the default sequence of AHB Master Bus the priority is APU gt SPIMO gt ARM 6 2 5 Power On Settings The power on setting is used to configure the chip to enter the specified state when the chip is power up or reset Application board needs to add the proper pull down or pull up resistor for the relative configuration pins SE Register Bit Descriptions Mapping SPI flash speed selection SCLK 00 72 MHz d 01 36 MHz SPOCR 6 5 10 18 MHz 11 50 KHz ICE Mode configuration setting SPOCR Al 0 ICE mode enable and the disable the cipher function 1 Normal mode LOFP48 ICE mode configuration setting 0 48 pins package and GPB 9 5 for ICE connection 1 48 pins package and GPB 9 5 use the normal function test mode SPOCR 2 0 test mode test mode GPA 12 test mode GPA 9 GPA 8 Boot from SRAM Boot from USB OTP program mode Boot from SpiMemory Nuvoton Technology Corp 26 Revision A1 3 http www nuvoton com nuvoTon NUC501 nn mn 6 2 6 System Manager Control Registers Ford eg rodi eration Reit ee Nuvoton Technology Corp 24 Revision A1 3 http www nuvoton com nuvoTon NUCS501 Product Identifier Register PDID This register provides specific read only information for software to identify this chip PDID GCR_BA 00 RO Product Identifier Register 0x0x55 0501 Reserved CVI 3 0 CID 17 0 Descript
163. s from the clock control to lock the input data RXDP and RXDM The 12MHz bit rate clock is also converted from DPLL 6 7 3 4 Floating De bounce A USB device may be plug in or unplug from the USB In order to monitor the state of a USB device when it is detached from the USB the device controller provides hardware de bounce for USB floating detect interrupt to avoid bounce problems on USB plug in and unplug Floating detect interrupt appears about 10 ms later than USB plug in and unplug A user can acknowledge USB plug in unplug by reading SFR FLODET and should understand that the flag in FLODET represents the current state on the bus without de bounce If the user poling this flag to check USB state he she must add software de bounce if necessary 6 7 3 5 Interrupt This USB provides 1 interrupt source with 4 interrupt events WAKEUP FLO USB BUS WAKEUP interrupt is for stop wakeup only FLO interrupt is for USB plug in or unplug USB event notifies users of Nuvoton Technology Corp 95 Revision A1 3 http www nuvoton com NUVOTON dll TT some USB requests like IN ACK OUT ACK etc and BUS event notifies users of some bus events like Suspend resume etc User must enable both AIC and IEF of USB to enable USB interrupts Wakeup interrupt is only present after stop wakeup After the IC enters power down mode any change on D D and floating detect pin can wake up NUC501 provided that USB wakeup function is enabled If
164. s the received data NOTE The Data Receive Registers are read only registers A Write to these registers will actually modify the Data Transmit Registers because those registers share the same FFs Nuvoton Technology Corp 226 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Data Transmit Register TX SPIMS_BA 0x10 Data Transmit Register 0 0x0000_0000 SPIMS_BA 0x14 Data Transmit Register 1 0x0000_0000 SPIMS_BA 0x18 Data Transmit Register 2 0x0000_0000 SPIMS BA OxiC Data Transmit Register 3 0x0000 0000 31 30 29 28 27 26 25 24 Tx 31 24 23 22 21 20 19 18 17 16 Tx 23 16 Tx 15 8 Be igo AAA Nuvoton Technology Corp http www nuvoton com Data Transmit Register The Data Transmit Registers hold the data to be transmitted in the next transfer Valid bits depend on the transmit bit length field in the CNTRL register For example if CNTRL Tx_BIT_LEN is set to 0x08 and the CNTRL Tx_NUM is set to 0x0 the bit Tx0 7 0 will be transmitted in next transfer If CNTRL Tx_BIT_LEN is set to 0x00 and CNTRL Tx_NUM is set to 0x3 the core will perform four 32 bit transmit receive successive using the same setting the order is Tx0 31 0 Tx1 31 0 Tx2 31 0 Tx3 31 0 NOTE The RxX and TxX registers share the same flip flops which mean that what is received from the input data line in one transfer will be transmitted on the output data line in the next transfer if
165. scale Register 0x0000_0000 Bits Descriptions Dead zone interval register 1 31 24 These 8 bit determine dead zone length The 1 unit time of dead zone length is received from clock selector 1 Dead zone interval register 0 23 16 These 8 bit determine dead zone length The 1 unit time of dead zone length is received from clock selector 0 Clock pre scale 1 for PWM Timer 2 3 15 8 Clock input is divided by CP1 1 before it is fed to the counter 2 3 If CP1 0 then the pre scale 1 output clock will be stopped Clock pre scale 0 for PWM Timer 0 1 7 0 Clock input is divided by CPO 1 before it is fed to the counter O 1 If CPO 0 then the pre scale O output clock will be stopped Nuvoton Technology Corp 182 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee PWM Clock Selector Register CSR 31 30 29 23 27 25 235 24 Reserved 23 2 21 2 19 18 17 de 9 Reserved Reserved css Reserved SSCS a 5 4 3 2 3 1 9 Reserved csn Reserved cso Bits Descriptions Gras Timer 3 Clock Source Selection Select clock input for timer 3 CSR3 14 12 Input clock divided by 14 12 a Timer 2 Clock Source Selection 10 8 Select clock input for timer O Table is the same as CSR3 Timer 1 Clock Source Selection 6 4 Select clock input for timer O Table is the same as CSR3 Timer O Clock Source Selection 2 0 Select cl
166. specifically designed to offer low cost and high performance for various applications like interactive toys edutainment robots and home appliances It integrates the 32 bit RISC CPU with 32KB high speed SRAM crypto engine with OTP key boot ROM LDO regulator ADC DAC I2C SPI USB2 0 FS Device amp GPIO into a cost affordable while feature rich micro controller Owing to the simplicity of the NUC501 architecture that boots SpiMemory into the high speed SRAM for program execution the total system BOM is reduced to its minimum Unlike usual ARM based MCU products the NUC501 operates without the use of SDRAM which is usually the source of complexity higher power consumption and cost The ARM7TDMI runs up to 108MHz on the high speed SRAM to offer enough horsepower for many MIPS hungry tasks while the remaining MIPS is still able to serve the need of application program For those applications like cartridge games that require large code storage and variation of game play scenarios the patented Extensible XIP Addressing on SpiMemory gives the flexibility whenever program execution speed is not a critical concern To protect the code against illegal pirating the NUC501 provides a crypto engine that works with internal OTP2 key to encrypt the data stored at external SpiMemory when the design in is finished Without the knowledge of the OTP key others can t decrypt the data even by means of ICE debugging The NUC501 is designed with spe
167. state 1 SEO state 0 In SEO state the USB D and D will be drive low and cause host doesn t see the device even the USB cable is still connected Therefore SEO could be used to force host to re connect the USB device Nuvoton Technology Corp 112 Revision A1 3 http www nuvoton com nuvoTon NUC501 peer EEE 6 10 Advanced Interrupt Controller 6 10 1 Overview An interrupt temporarily changes the execution sequence of a program to react to a particular event such as power failure watchdog timer timeout and engine complete system events external event trigger and so on The ARM processor provides two modes of interrupts the Fast Interrupt FIQ mode for critical session and the Interrupt IRQ mode for general purpose The IRQ exception mode is occurred when the NIRQ input is asserted Similarly the FIQ exception mode is occurred when the NFIQ input is asserted The FIQ mode has privilege over the IRQ mode and can preempt an ongoing IRQ mode It is possible to ignore the NFIQ and the NIRQ by setting the F bit and I bit in the current program status register CPSR The NUC501 incorporates the advanced interrupt controller AIC that is capable of dealing with the interrupt requests from different sources Each interrupt source is uniquely assigned to an interrupt channel For example the watchdog timer interrupt is assigned to channel 2 The AIC implements a proprietary eight level priority scheme that differentiates the av
168. t has occurred If the Watchdog timer interrupt is not enabled then this bit indicates that a 3 timeout period has elapsed e O Watchdog timer interrupt does not occur e 1 Watchdog timer interrupt occurs NOTE This bit is read only but can be cleared by writing 1 to this bit Watchdog Timer Reset Flag When the Watchdog timer initiates a reset the hardware will set this bit This flag can be read by software to determine the source of reset Software is responsible to clear it up manually If WTRE is disabled then the 2 WTRF Watchdog timer has no effect on this bit e 0 Watchdog timer reset does not occur e 1 Watchdog timer reset occurs NOTE This bit is read only but can be cleared by writing 1 to this bit 1 WTRE Watchdog Timer Reset Enable Setting this bit will enable the Watchdog timer reset function Nuvoton Technology Corp 237 Revision A1 3 http www nuvoton com nuvoTon Nuvoton Technology Corp http www nuvoton com NUC501 Disable Watchdog timer reset function Enable Watchdog timer reset function Watchdog Timer Reset This bit brings the Watchdog timer into a known state It helps reset the Watchdog timer before a timeout situation occurring Failing to set WTR before timeout will initiates an interrupt if WTIE is set If the WTRE Dit is set Watchdog timer reset will be occurred 16128 WDT clock cycles after timeout This bit is self clearing e O Writing O to this bit has no
169. tal pin PWMT3 PWM output for timer 3 USB DET USB detected input UARTO RTS Request to Send output pin for UARTO High speed 12 16mA GPB 5 General purpose input output I O digital pin GPB 3 PWMT2 USB_DET UARTO_CTS N O N N N 00 N GPB 4 PWMT3 USB_DET UARTO_RTS GPB 5 TCK SPIM1_SI N O OY TCK JTAG ICE Test Clock pin LQFP48 only Nuvoton Technology Corp Revision A1 3 http www nuvoton com nuvoTon NUC501 SPIM1 esten GPB 6 18 12 16mA TMS I O SPIM1_SO PWMT2 GPB 7 TDI SPIM1_SCK m Ul PWMT3 GPB 8 TDO USB_DET PWMTO LA pa GPB 9 NTRST USB_DET PWMT1 O GPC 0 SPIM1_SO USB_DET GPC 1 SPIM1 SI USB DET Ul Ul GPC 2 SPIM1 SCK USB DET Ul D UI pa pa D U1 I P I I I CO CO NI LE UJ N O GPC 3 PWMTO USB_DET Ul O GPC 4 PWMT1 USB_DET i PWMT2 Nuvoton Technology Corp 16 http www nuvoton com GPB 6 General purpose input output digital pin TMS JTAG ICE Test Mode Select pin LQFP48 only SPI2_SO Serial data output pin for SPIM1 master PWMT2 PWM output for timer 2c GPB 7 General purpose input output digital pin TDI JTAG ICE TDO pin LQFP48 only SPIM1_SCK Serial clock output pin for SPIM1 master PWMT3 PWM output for timer 3 GPB 8 General purpose input output digital pin TDO JTAG ICE TDO interface LQFP48 only
170. the GPIO When the user programs the PAD REG the pins play the alternative function If the different alternative functions are enabled simultaneous the priority is Alternative Function 1 Alternative Function 2 Alternative Function 3 Default Function For example If the GPA 12 is configured to be SPIMS SO by PAD REG1 and it is also configured to be PWMTO by PAD REGO the actual function of GPA 12 would be SPIMS SO because the SPIMS SO function priority is higher than PWMTO Except the multiple functions each NUC501 output driving current strength is also controllable The driving strength control register is the GPA DS GPB DS and GPC DS For different pin the driving can be 4mA or 8mA and 12mA or 16mA For example user can control the GPB 1 strength to 16mA and directed drive the high current LED to save PCB extra component to reduce the BOM cost Default Function Alternative Alternative Alternative Power on Name Function 1 Function 2 Function 3 setting GPIO Nuvoton Technology Corp 1 Revision A1 3 http www nuvoton com Power on set IBR NUVOTOM NUC501 nn see SPIMS_SI SPIMS_SO Power on set IBR SPIMS_SCK Power on set 48 64 SPIMS_SS Slave Power on set ICE Power on set SPI SO CK SPIM1_SI GPB 7 TDI SPIM1_SCK GPB 8 TDO Power on set SPI_S1 GPB 9 Audio DAC AO OUTO AO REF18 AO VREF USB2 0 Device USB_DP USB_DM
171. ton Technology Corp 44 Revision A1 3 http www nuvoton com nuvoTon NUC501 a FFFFFEEEErz 6 3 Clock Controller 6 3 1 Function Description The clock controller generates the clocks for the whole chip it include all AMBA interface modules and all peripheral clocks the USB UART APU and so on There is one PLL modules in this chip and the PLL clock source is from the external crystal input AD ADC_CK_EN APU 1 2 APU_CK_EN gt h km Crystal E n _S O Clock Select AHB_Modules_CK_EN Oo __ gt 1 HCLK_N x 2 O CPU_CK_EN 1 APB_N APB CK EN O APB_Modules_CK_EN The clock controller implements the power control function include the individually clock on or off control register clock source select and the divided number from clock source These functions minimize the extra power consumption and the chip run on the just condition On the power down mode the controller turn off the crystal oscillator to minimize the chip power consumption The clock HCLK is the source for all the AMBA modules The HCLK is the operating clock for the SRAM and it is divided by two from one of the sources Crystal PLL PLL 2 and the crystal 32 KHz the HCLK is used for the AMBA AHB BUS clock The ARM7 CPU uses the same frequency as the HCLK The APB clock is divided from the HCLK too 6 3 2 Clock Control Registers Nuvoton Technology Corp 45 Revision A1 3 http www nuvoton com nuvoTon NUC501
172. transmission 0x3 Four bytes are left for transmission NOTE When NACK received Tx_NUM will not decrease 2 iF Interrupt Flag Nuvoton Technology Corp 165 Revision A1 3 http www nuvoton com nuvoTon NUC501 The Interrupt Flag is set when Transfer has been completed Transfer has not been completed but slave responded NACK in multi byte transmit mode Arbitration is lost NOTE This bit is read only but can be cleared by writing 1 to this bit Interrupt Enable O Disable I C Interrupt 1 Enable C Interrupt I C Core Enable O Disable I C core serial bus outputs are controlled by SDW SCW 1 Enable I C core serial bus outputs are controlled by I C core Nuvoton Technology Corp 166 Revision A1 3 http www nuvoton com nuvoTon NUC501 Pe ria P 1 _ e _ _ __ __ ceeee e e Pre scale Register DIVIDER Register Offset R W C Description reset value DIVIDER Clock Pre scale Register 0x0000_0000 Reserved Reserved da A a de JA a TE mm DIVIDER 15 8 AA e E ERE DIVIDER 7 0 Bits Descriptions 31 16 Clock Pre scale Register It is used to pre scale the SCL clock line Due to the structure of the I C interface the core uses a 5 SCL clock internally The pre scale register must be programmed to this 5 SCL frequency minus 1 Change the value of the 15 0 DIVIDER pre scale register only when the I2C EN bit is cleared E
173. tus Register 0x0000_0000 IAS 7 0 This register indicates the status of each interrupt channel in consideration of the interrupt source type as CM in the corresponding Source Control Register but regardless of its mask setting Bits Descriptions Interrupt Active Status Indicate the status of the corresponding interrupt source 31 0 IASx e O Corresponding interrupt channel is inactive e 1 Corresponding interrupt channel is active Nuvoton Technology Corp 123 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee AIC Interrupt Status Register AIC_ISR AIC_ISR AIC_BA 108 MES Interrupt Status Register 0x0000_0000 ISR 7 0 This register identifies those interrupt channels whose are both active and enabled PA i Interrupt Status Register Indicates the status of corresponding interrupt channel e 0 Two possibilities a The corresponding interrupt channel is inactive no matter whether it is 31 0 enabled or disabled b It is active but not enabled e 1 Corresponding interrupt channel is both active and enabled can assert an interrupt Nuvoton Technology Corp 124 Revision A1 3 http www nuvoton com nuvoTon NUC501 ee AIC IRQ Priority Encoding Register AIC_IPER AIC_IPER AIC_BA 10C OR Interrupt Priority Encoding Register 0x0000_0000 Reserved Reserved i5 34 5 1 2I 3 I 39 I 5 5 Reserved 7 6 5 j 4 3 2 1 o When the AIC generates the interrupt VECTOR re
174. up interrupt enable for Irpt_WakeUp e 0 Mask off Irpt_Wakeup e 1 Enable Irpt Wakeup Wake up interrupt enable for INTR wakeup 6 e 0 Mask off INTR Wakeup e 1 Enable INTR Wakeup ICE debug mode acknowledge enable e 0 When DBGACK is high the UART receiver time out clock will be held 5 nDBGACK EN 1 No matter what DBGACK is high or not the UART receiver timer out clock will not be held RX Time out Interrupt Enable 4 e 0 Mask off INTR tout e 1 Enable INTR tout MODEM Status Interrupt INTR MOS Enable e O Mask off INTR MOS e 1 Enable INTR MOS RLSIE Receive Line Status Interrupt INTR RLS Enable Nuvoton Technology Corp 248 Revision A1 3 http www nuvoton com nuvoTon NUC501 e Mask off INTR RLS 6 Enable INTR_RLS Transmit Holding Register Empty Interrupt INTR_THRE Enable e 1 Enable INTR THRE Receive Data Available Interrupt INTR_RDA Enable e 1 Enable INTR RDA Nuvoton Technology Corp 249 Revision A1 3 http www nuvoton com nuvoTon NUC501 Divider Latch Low Byte Register UA_DLL UA DLL UA BA 0x00 Divisor Latch Register LS DLAB 1 0x0000 0000 Reserved Reserved cs I5 I5 I2 Is I5 a Reserved aio BECHER WE AA Baud Rate Divider Low Byte L8 NNNM B R Di 7 0 BEER The low byte of the baud rate divider Low Byte Nuvoton Technology Corp 250 Revision A1 3 http www nuvoton com nuvoTon NUC501 Divisor Latch High Byte Register
175. vision A1 3 http www nuvoton com nuvoTon NUC501 6 13 11 PWM Timer Register Mapping R read only W write only R W both read and write C Only value 0 can be written PPR PWM_BA Ox000 R W PWM Presscale Register 0x0000_0000_ CSR__ _PWM_BA 0x004_ _R W_ PWN Clock Select Register 0x0000_0000_ CNRO PWM_BAFOXOOC R W PWM Counter Register O 0x0000 0000 CMRO PWM_BA 0x010 R W PWM Comparator Register 0x0000 0000 PDRO PWW_BA Ox014 R PWM Data Registero 0x0000_0000_ CMRI PWM_BAFOXOIC R W PWM Comparator Registeri 0x0000 0000 PDRI PWM_BA 0x020 R PWM Data Registert 0x0000_0000_ CNR2 PWM_BAFOxO24 R W PWM CounterRegister 0x0000 0000 PDR2 PWM BAvOXD2C R PWMDataRegister2 0x0000_0000_ CNR3 PWM_BA 0x030 R W PWM Counter Register3 0x0000_0000_ CMR3 PWM_BA 0x034 R W PWM Comparator Register3 0x0000 0000 PDR3 PWM_BA 0x038 R PWM Data Register3 0x0000_0000_ PIIR PWM_BA 0x044 R C PWM Interrupt Indication Register 0x0000 0000 CCRO PWM BA 0x050 R W Capture Control Register0 0x0000_0000_ CCRi PWM_BA 0x054 R W Capture Control Registeri 0x0000_0000_ CAPENR PWW_BA 0x078_ R W Capture Input Enable Register 0x0000_0000_ POE PWM BAvOX07C R W PWM Output Enable 0x0000_0000_ Nuvoton Technology Corp 181 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee 6 14 Register Description PWM Pre Scale Register PPR PPR PWM_BA 0x000 R W PWM Pre
176. x51 7b 1010001 Data to write OxAC I C Sequence Nuvoton Technology Corp 160 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee 1 generate start command 2 write slave address write bit 3 receive acknowledge from slave 4 write data 5 receive acknowledge from slave 6 generate stop command Commands 1 Write a value into DIVIDER to determine the frequency of serial clock 2 Set Tx NUM Ox1 and set I2C_EN 1 to enable I C core 3 Write OxA2 address write bit to Transmit Register TxR 15 8 and OxAC to TxR 7 0 4 Set START bit and WRITE bit Wait for interrupt or I2C TIP flag to negate 5 Read I2C RxACK bit from CSR Register it should be O 6 Set Tx NUM 0x0 7 Set STOP bit Wait for interrupt or I2C TIP flag to negate First command sequence 994 Second command sequence cb SCL SDA s W ack Y ACK d NOTE Please note that the time for the Interrupt Service Routine is not shown here It is assumed that the ISR is much faster then the DC cycle time and therefore not visible Example 2 Read a byte of data from an I2C memory device using single byte transfer mode Slave address Ox4E 7 b1001110 Memory location to read from 0x20 I2C sequence 1 generate start signal 2 write slave address write bit then receive acknowledge from slave 3 write memory location then
177. xample PCLK 32MHz desired SCL 100KHz prescale E UU 1 63 dec 3F hex 5 100KAHz Nuvoton Technology Corp 167 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Command Register CMDR Register Offset R W cpescripton________________ reset Value CMDR Command Register 0x0000_000x Reserved hs p Ts Tz Tu Te p p 7o p p RR Reserved START Stop rean ware Ac NOTE Software can write this register only when I2C_EN 1 Bits Descriptions 31 5 Generate Start Condition DUBIE Generate repeated start condition on I C bus when this bit set 1 Generate Stop Condition PESE Generate stop condition on I C bus when this bit set 1 2 Read Data From Slave Retrieve data from slave when this bit set 1 Write Data To Slave supe Transmit data to slave when this bit set 1 Send Acknowledge To Slave 0 When I C behaves as a receiver sent ACK ACK 0 or NACK ACK 1 to Slave NOTE The START STOP READ and WRITE bits are cleared automatically while transfer finished READ and WRITE cannot be set concurrently Nuvoton Technology Corp 168 Revision A1 3 http www nuvoton com nuvoTon NUC501 SS eee Software Mode Register SWR Register Get R W c escription______________ Reset value Software Mode Control Register 0x0000_003F Reserved Reserved Gs a 5 p Ta Ta TT 7 le ls 4 Z3 Q2 h lo Reserved SER SDR Ten sew
178. ypassed If AUDIO HPEN OQ the digital high pass filter will be enable 1 AUDIO EN JjRecord operation enable bit Nuvoton Technology Corp 271 Revision A1 3 http www nuvoton com If AUDIO EN O the hardware digital decimation filter will be disabled If AUDIO_EN 1 the hardware digital decimation filter will be enabled Digital filter reset bit 0 AUDIO_RESET If AUDIO_RESET 0 the digital filter is not reset If AUDIO_RESET 1 the digital filter is on the reset state Nuvoton Technology Corp 272 Revision A1 3 http www nuvoton com nuvoTon NUC501 nuvoTon NUC501 Audio control register AUDIO BUFO AUDIO BUFO ADC_BA 0x020 R W Audio data register 0x0000 0000 31 30 29 28 27 26 25 24 AUDIO DATA1 23 22 21 20 19 18 17 16 AUDIO DATA1 AUDIO DATAO 7 6 j 5 4 3 2 1 0 AUDIO DATAO Bits Descriptions SO Converted audio datai at butter Read Only E rear liye 16 bit digital audio data in 2 s compliment format Converted audio data0 at bufferO Read Only aoe pene tA 16 bit digital audio data in 2 s compliment format Nuvoton Technology Corp 213 Revision A1 3 http www nuvoton com nuvoTon NUC501 Audio control register AUDIO BUF1 AUDIO_BUF1 ADC_BA 0x024 R W Audio data register 0x0000_0000 31 30 29 28 27 26 25 24 AUDIO DATA3 23 2 21 20 19 18 17 16 AUDIO DATA3 AUDIO DATA2

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