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Z8F4823 Datasheet From xinpian.net

1. ZiLoG UN Caution The 24 bit WDT Reload Value must not be set to a value less than 000004H Table 48 Watch Dog Timer Reload Upper Byte Register WDTU BITS 7 6 5 4 3 2 1 0 FIELD WDTU RESET 1 R W R W ADDR FF1H R W Read returns the current WDT count value Write sets the desired Reload Value WDTU WDT Reload Upper Byte Most significant byte MSB Bits 23 16 of the 24 bit WDT reload value Table 49 Watch Dog Timer Reload High Byte Register WDTH BITS 7 6 5 4 3 2 1 0 FIELD WDTH RESET 1 R W R W ADDR FF2H R W Read returns the current WDT count value Write sets the desired Reload Value WDTH WDT Reload High Byte Middle byte Bits 15 8 of the 24 bit WDT reload value PS019915 1005 htt p ww xi npi an net Watch Dog Timer D U Uu LH 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z ziLog Table 50 Watch Dog Timer Reload Low Byte Register WDTL BITS 7 6 5 4 3 2 1 0 FIELD WDTL RESET 1 R W R W ADDR FF3H R W Read returns the current WDT count value Write sets the desired Reload Value WDTL WDT Reload Low Least significant byte LSB Bits 7 0 of the 24 bit WDT reload value PS019915 1005 htt p ww xi npi an net uU D Uu UU W
2. Assembly Binary Hex Mnemonic Definition Flag Test Operation 0000 0 F Always False 0001 1 LT Less Than S XOR V 1 0010 2 LE Less Than or Equal Z OR S XOR V 1 0011 3 ULE Unsigned Less Than or Equal COR Z 1 0100 4 OV Overflow V 1 0101 5 MI Minus S 1 0110 6 Z Zero Z 1 0110 6 EQ Equal Z 1 0111 7 C Carry C 1 0111 7 ULT Unsigned Less Than C 1 1000 8 T or blank Always True 1001 9 GE Greater Than or Equal S XOR V 0 1010 A GT Greater Than Z OR S XOR V 20 1011 B UGT Unsigned Greater Than C 0 AND Z 0 1 1100 C NOV No Overflow V 0 1101 D PL Plus S 0 1110 E NZ Non Zero Z 0 1110 E NE Not Equal Z 0 1111 F NC No Carry C 0 1111 F UGE Unsigned Greater Than or Equal C 0 PS019915 1005 eZ8 CPU Instruction Set htt p ww xi npi an net OO HOOOdIqMooog Oo 010 62245566 13810019655 237 Z8 Encore 64K Series Product Specification Z z ZiLOG eZ8 CPU Instruction Classes eZ8 CPU instructions can be divided functionally into the following groups Arithmetic Bit Manipulation Block Transfer CPU Control Load Logical Program Control Rotate and Shift Tables 124 through 131 contain the instructions belonging to each group and the number of operands required for each instruction Some instructions appear in more than one table as these instruction can be considered as a subset of more than one category Within these tables the source operand is identified as src t
3. 249 Z8 Encore 64K Series Product Specification ZiILoOdG Table 132 eZ8 CPU Instruction Summary Continued Address Mode Flags Assembly Opcode s Fetch Instr Mnemonic Symbolic Operation dst src Hex C Z S V D H Cycles Cycles TCM dst src NOT dst AND src r r 62 Q 2 3 r Ir 63 2 4 R R 64 3 3 R IR 65 3 4 R IM 66 3 3 IR IM 67 3 4 TCMX dst src NOT dst AND src ER ER 68 Q 4 3 ER IM 69 4 3 TM dst src dst AND src r r 72 Q0 2 3 r Ir 73 2 4 R R 74 3 3 R IR 75 3 4 R IM 76 3 3 IR IM TI 3 4 TMX dst src dst AND src ER ER 78 Q0 4 3 ER IM 79 4 3 TRAP Vector SP SP 2 Vector F2 DEL S LLL ZZ 2 6 SP lt PC SP SP 1 GSP lt FLAGS PC lt Vector WDT SF 2 1 2 Flags Notation Value is a function of the result of the operation 0 Reset to 0 Unaffected 1 Set to 1 X Undefined PS019915 1005 eZ8 CPU Instruction Set htt p ww xi npi an net o ee ee a og 010 62245566 13810019655 250 Z8 Encore 64K Series Product Specification 251 ZiLOG Table 132 eZ8 CPU Instruction Summary Continued Address Mode Flags Assembly ____ Opcode s Fetch Instr Mnemonic Symbolic Operation dst src Hex C Z S V D H Cycles Cycles XOR dst src dst
4. Z8 Encore 64K Series Product Specification L a ZiLOG Information Area Table 90 describes the 64K Series Information Area This 512 byte Information Area is accessed by setting bit 7 of the Page Select Register to 1 When access is enabled the Information Area is mapped into Flash Memory and overlays the 512 bytes at addresses FEOOH to FFFFH When the Information Area access is enabled LDC instructions return data from the Information Area CPU instruction fetches always comes from Flash Mem ory regardless of the Information Area access bit Access to the Information Area is read only Table 90 64K Series Information Area Map Flash Memory Address Hex Function FEO0H FE3FH Reserved FE40H FE53H Part Number 20 character ASCII alphanumeric code Left justified and filled with zeros FES4H FFFFH Reserved Operation The Flash Controller provides the proper signals and timing for Byte Programming Page Erase and Mass Erase of the Flash memory The Flash Controller contains a protection mechanism via the Flash Control register FCTL to prevent accidental programming or erasure The following subsections provide details on the various operations Lock Unlock Sector Protect Byte Programming Page Erase and Mass Erase PS019915 1005 Flash Memory htt p ww xi npi an net DOT 010 62245566 13810019655 Z8 Encore 64K Series Product Sp
5. BITS 7 6 5 4 3 2 1 0 FIELD ADCD L Reserved RESET X R W R ADDR F73H ADCD_L ADC Data Low Bits These are the least significant two bits of the 10 bit ADC output These bits are undefined after a Reset Reserved These bits are reserved and are always undefined PS019915 1005 Analog to Digital Converter htt p ww xi npi an net o CO FSEPET EU og 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 178 ZiLOG Flash Memory Overview The products in the Z8 Encore 64K Series feature up to 64KB 65 536 bytes of non volatile Flash memory with read write erase capability The Flash memory can be pro grammed and erased in circuit by either user code or through the On Chip Debugger The Flash memory array is arranged in 512 byte per page The 512 byte page is the mini mum Flash block size that can be erased The Flash memory is also divided into 8 sectors which can be protected from programming and erase operations on a per sector basis Table 88 describes the Flash memory configuration for each device in the 64K Series Table 89 lists the sector address ranges Figure 35 illustrates the Flash memory arrange ment Table 88 Flash Memory Configurations Numberof Flash Memory Number of Pages per Part Number Flash Size Pages Addresses Sector Size Sectors Sector Z8F162x 16K 16 384 32 0000H
6. ADC Analog Input Number 0000 Analog input 0 updated 0001 Analog input 0 1 updated 0010 Analog input 0 2 updated 0011 Analog input 0 3 updated 0100 Analog input 0 4 updated 0101 Analog input 0 5 updated 0100 Analog input 0 6 updated 0101 Analog input 0 7 updated 1000 Analog input 0 8 updated 1001 Analog input 0 9 updated 1010 Analog input 0 10 updated 1011 Analog inputs 0 11 updated 11xx Reserved ______________ Reserved Interrupt request enable 0 DMA ADC does not generate interrupt requests 1 2DMA ADC generates interrupt requests after last analog input DMA ADC Enable 0 2 DMA ADC is disabled 1 DMA ADC is enabled DMA Status DMAA STAT FBFH Read Only D7 D6 DSIDAID3ID2IDI DO L DMAO Interrupt Request Indicator 0 DMAO is not the source of the IRQ 1 DMAO is the source of the IRQ DMAI Interrupt Request Indicator 0 DMAL is not the source of the IRQ 1 DMAI is the source of the IRQ L DMA_ADC Interrupt Request Indicator 0 DMA_ADC is not the source of the IRQ 1 DMA ADC is the source of the IRQ L Reserved L Curent ADC analog input Identifies the analog input the ADC is currently converting Control Register Summary ugggmniu IMOO000000 010 62245566 13810019655 36 htt p ww x
7. Program Memory Address Hex Function Z8F482x Products 0000 0001 Option Bits 0002 0003 Reset Vector 0004 0005 WDT Interrupt Vector 0006 0007 Illegal Instruction Trap 0008 0037 Interrupt Vectors 0038 BFFF Program Memory Z8F642x Products 0000 0001 Option Bits 0002 0003 Reset Vector 0004 0005 WDT Interrupt Vector 0006 0007 Illegal Instruction Trap 0008 0037 Interrupt Vectors 0038 FFFF Program Memory See Table 23 on page 63 for a list of the interrupt vectors Data Memory The Z8 Encore 64K Series does not use the eZ8 CPU s 64KB Data Memory address space Information Area Table 6 describes the Z8 Encore 64K Series Information Area This 512 byte Informa tion Area is accessed by setting bit 7 of the Page Select Register to 1 When access is enabled the Information Area is mapped into the Program Memory and overlays the 512 bytes at addresses FEOOH to FFFFH When the Information Area access is enabled execu tion of LDC and LDCI instruction from these Program Memory addresses return the Infor mation Area data rather than the Program Memory data Reads of these addresses through the On Chip Debugger also returns the Information Area data Execution of code from these addresses continues to correctly use the Program Memory Access to the Information Area is read only PS019915 1005 Address Space htt p ww xi npi an net Hl uu IG1U D UU UU 010 62245566 13810
8. Z8 Encore 64K Series Product Specification L a ZiLOG Timer 0 3 Control 0 Registers The Timer 0 3 Control 0 TxCTLO registers Tables 44 and 45 allow cascading of the Timers Table 44 Timer 0 3 Control 0 Register TxCTLO0 BITS 7 6 5 4 1 FIELD Reserved CSC Reserved RESET 0 R W R W ADDR F06H FOEH F16H FIEH CSC Cascade Timers 0 Timer Input signal comes from the pin 2 For Timer 0 Input signal is connected to Timer 3 output For Timer 1 Input signal is connected to Timer 0 output For Timer 2 Input signal is connected to Timer 1 output For Timer 3 Input signal is connected to Timer 2 output Timer 0 3 Control 1 Registers The Timer 0 3 Control 1 TxCTL 1 registers enable disable the timers set the prescaler value and determine the timer operating mode Table 45 Timer 0 3 Control 1 Register TxCTL 1 htt p ww xi npi an net o BITS 7 6 5 4 1 FIELD TEN TPOL PRES TMODE RESET 0 R W R W ADDR F07H FOFH F17H FIFH TEN Timer Enable 0 Timer is disabled 1 Timer enabled to count TPOL Timer Input Output Polarity Operation of this bit is a function of the current operating mode of the timer PS019915 1005 Timers 010 62245566 13810019655 HHHHJISGIHEH UU Z8 Encore 64K Series Product Specification L a
9. Z8 Encore 64K Series Product Specification ZI Table 7 64K Series Register File Address Map Continued ZiLOG Address Hex Register Description Mnemonic Reset Hex Page FC7 IRQ2 Enable High Bit IRQ2ENH 00 71 FC8 IRQ2 Enable Low Bit IRQ2ENL 00 71 FC9 FCC Reserved XX FCD Interrupt Edge Select IRQES 00 72 FCE Interrupt Port Select IRQPS 00 73 FCF Interrupt Control IRQCTL 00 74 GPIO Port A FDO Port A Address PAADDR 00 55 FD1 Port A Control PACTL 00 56 FD2 Port A Input Data PAIN XX 60 FD3 Port A Output Data PAOUT 00 61 GPIO Port B FD4 Port B Address PBADDR 00 55 FD5 Port B Control PBCTL 00 56 FD6 Port B Input Data PBIN XX 60 FD7 Port B Output Data PBOUT 00 61 GPIO Port C FD8 Port C Address PCADDR 00 55 FD9 Port C Control PCCTL 00 56 FDA Port C Input Data PCIN XX 60 FDB Port C Output Data PCOUT 00 61 GPIO Port D FDC Port D Address PDADDR 00 55 FDD Port D Control PDCTL 00 56 FDE Port D Input Data PDIN XX 60 FDF Port D Output Data PDOUT 00 61 GPIO Port E FEO Port E Address PEADDR 00 55 FEI Port E Control PECTL 00 56 FE2 Port E Input Data PEIN XX 60 FE3 Port E Output Data PEOUT 00 61 GPIO Port F FE4 Port F Address PFADDR 00 55 FES Port F Control PFCTL 00 56 FE6 Port F Input Data PFIN XX 60 FE7 Port F Output Data PFOUT 00 61 GPIO Port G FE8 Port G Address PGADDR 00 55 FE9 P
10. BITS 7 6 5 4 3 D 1 0 FIELD Reserved DIAG NUMBITS 2 0 SSIO SSV RESET 0 R W R R W ADDR F63H AN Caution Reserved Must be 0 DIAG Diagnostic Mode Control bit This bit is for SPI diagnostics Setting this bit allows the Baud Rate Generator value to be read using the SPIBRH and SPIBRL register locations 0 Reading SPIBRH SPIBRL returns the value in the SPIBRH and SPIBRL registers 1 Reading SPIBRH returns bits 15 8 of the SPI Baud Rate Generator and reading SPI BRL returns bits 7 0 of the SPI Baud Rate Counter The Baud Rate Counter High and Low byte values are not buffered Exercise caution if reading the values while the BRG is counting NUMBITS 2 0 Number of Data Bits Per Character to Transfer This field contains the number of bits to shift for each character transfer Refer to the SPI Data Register description for information on valid bit positions when the character length is less than 8 bits 000 8 bits 001 1 bit 010 2 bits 011 3 bits 100 4 bits 101 5 bits PS019915 1005 Serial Peripheral Interface htt p ww xi npi an net LEE EB DRE EL EE EGET ET VE Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z 137 ZiLOG 110 6 bits 111 7 bits SSIO Slave Select I O 0 SS pin configured as an input 1 SS pin configured as an output Master mode only SSV Slave Select Value If SSI
11. External VREF select 0 Internal voltage reference selected 1 External voltage reference selected Reserved Conversion Enable 0 Conversion is complete 1 Begin conversion Control Register Summary FER DL Ta a EH 010 62245566 13810019655 ADC Data High Byte ADCDH F72H Read Only D7 D6 D5 D4ID3 D2ID1 DO ADC Data Low Bits ADCD L F73H Read Only D7ID6 ID5D4D3D2DDI DO Reserved DMAO Control DMAOCTL FBOH Read Write D7 ID6 ID5DAID3ID2DI DO Word Select DMAO Enable ADC Data 9 2 ADC Data 1 0 L Request Trigger Source Select 000 Timer 0 001 Timer 1 010 Timer 2 011 Timer 3 100 UARTO Received Data register contains valid data 101 UARTI Received Data register contains valid data 110 I2C receiver contains valid data 111 Reserved 0 DMA transfers 1 byte per request 1 DMA transfers 2 bytes per request DMAO Interrupt Enable 0 DMAO does not generate interrupts 1 DMAO generates an interrupt when End Address data is transferred L DMAO Data Transfer Direction 0 Register File to peripheral registers 1 Peripheral registers to Register File DMAO Loop Enable 0 DMA disables after End Address 1 DMA reloads Start Address after End Address and contin
12. Index Symbols 236 236 Q 236 Numerics 10 bit ADC 4 40 lead plastic dual inline package 257 44 lead low profile quad flat package 258 44 ead plastic lead chip carrier package 259 64 lead low profile quad flat package 259 68 lead plastic lead chip carrier package 260 80 lead quad flat package 261 A absolute maximum ratings 209 AC characteristics 224 ADC 238 architecture 171 automatic power down 172 block diagram 172 continuous conversion 173 control register 175 control register definitions 175 data high byte register 176 data low bits register 176 DMA control 174 electrical characteristics and timing 222 operation 172 single shot conversion 173 ADCCTL register 175 ADCDH register 176 ADCDL register 176 ADCX 238 ADD 238 add extended addressing 238 add with carry 238 add with carry extended addressing 238 PS019915 1005 Z8 Encore 64K Series Product Specification Zi ZiLOG additional symbols 236 address space 17 ADDX 238 analog signals 14 analog to digital converter ADC 171 AND 241 ANDX 241 arithmetic instructions 238 assembly language programming 233 assembly language syntax 234 B B 236 b 235 baud rate generator UART 108 BCLR 239 binary number suffix 236 BIT 239 bit 235 clear 239 manipulation instructions 239 set 239 set or clear 239 swap 239 test and jump 241 test and jump if non zero 241 test and jump if zero 241 bit jump and test if non zero
13. Z8 Encore 64K Series Product Specification ziLoG Table 23 Interrupt Vectors in Order of Priority Program Memory Priority Vector Address Interrupt Source Highest 0002H Reset not an interrupt 0004H Watch Dog Timer see Watch Dog Timer chapter 0006H Illegal Instruction Trap not an interrupt 0008H Timer 2 000AH Timer 1 000CH Timer 0 000EH UART 0 receiver 0010H UART 0 transmitter 0012H PC 0014H SPI 0016H ADC 0018H Port A7 or Port D7 rising or falling input edge 001AH Port A6 or Port D6 rising or falling input edge 001CH Port A5 or Port D5 rising or falling input edge 001EH Port A4 or Port D4 rising or falling input edge 0020H Port A3 or Port D3 rising or falling input edge 0022H Port A2 or Port D2 rising or falling input edge 0024H Port A1 or Port D1 rising or falling input edge 0026H Port AO or Port DO rising or falling input edge 0028H Timer 3 not available in 44 pin packages 002AH UART 1 receiver 002CH UART 1 transmitter 002EH DMA 0030H Port C3 both input edges 0032H Port C2 both input edges 0034H Port C1 both input edges Lowest 0036H Port CO both input edges PS019915 1005 Interrupt Controller htt p ww xi npi an net LEE EB DRE EL EE EGET ET VE Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z ZiLOG Architecture Figure 11 illustr
14. 48 Low Power Mod s 43 2 ROCA UR eens eg Roe On OR CA OR ew Sade eae ewe 49 OVOrVIeW uuo pee det wd dat e RD o E Dacha hae Pe eek al t Je e to de eal ed 49 STOP MOGE ceo e cece ead eA bee NOS Cade UI ooo Ree ht ha Rod aee 49 HALT Mod essers eens atl a sede e EEE UR EUR UA ee eae ERE dad e 50 General Purpose I O 2 ccc ccc ccc ccc cece e eee eee ce ene e ners ee seeeseenes 51 OVetVI W cach tha nee eda hd Be ea whee E EE CE MeL ON ees ed eee band ee dada weed 51 GPIO Port Availability By Device 0 0 cee eee 51 Architecture ic cca dee e e bea ee bbe RR ceed dae Ede Veal EL ERE E ER rd 52 GPIO Alternate Functions 00 0 c cc ene e eens 52 GPIO Interrupts occo cs eset hoa eee ak ee ee ERE ERR ERE Y ERR bead 54 GPIO Control Register Definitions 0 0 0 0 eee 54 Port A H Address Registers 2 0 0 eee eee e 55 Port A H Control Registers 0 eee cece een ene 56 Port A H Input Data Registers leseseeeeeee e 60 Port A H Output Data Register lseeeeeee ee 61 Interrupt Controller 0 ccc ccc cc cece cece ener eens ee ee senses eeseecnes 62 OVErVIe Ws cited ueeauete at ere anes Ferias ae Guana et qaa ey yia ou od OR ea tenn ye 62 Interrupt Vector Listing prenec eite seniii oenen E I Ih 62 Architecture oou oed Deu e eee i renta i eant gt ect e es 64 OPerallOn gc ads dieses eiacenpPaee dues Rae bee s otedu Ee evi d cpu S beans 64 Master Interrupt Enable sssosess ea etae am el b ac esi
15. Lu Z8 Encore 64K Series Product Specification Zi ZiLOG Table 122 Additional Symbols Symbol Definition dst Destination Operand sre Source Operand Indirect Address Prefix SP Stack Pointer PC Program Counter FLAGS Flags Register RP Register Pointer Immediate Operand Prefix B Binary Number Suffix Hexadecimal Number Prefix H Hexadecimal Number Suffix Assignment of a value is indicated by an arrow For example dst lt dst src indicates the source data is added to the destination data and the result is stored in the des tination location PS019915 1005 eZ8 CPU Instruction Set htt p ww xi npi an net uggamBpmmuagdrqiudtut Ooo 010 62245566 13810019655 Condition Codes Z8 Encore 64K Series Product Specification ZiLOG The C Z S and V flags control the operation of the conditional jump JP cc and JR cc instructions Sixteen frequently useful functions of the flag settings are encoded in a 4 bit field called the condition code cc which forms Bits 7 4 of the conditional jump instruc tions The condition codes are summarized in Table 123 Some binary condition codes can be created using more than one assembly code mnemonic The result of the flag test oper ation decides if the conditional jump is executed Table 123 Condition Codes
16. lesse 175 ADC Control Register 0 0 ters eutre ea ia KA E EE OER EE 175 ADC Data High Byte Register 0 0 eee eA 176 ADC Data Low Bits Register 0 0 0 eee cece eee 176 Flash Memory sepe EhRRRE oe ead decal ea En E ead eur eae NEREKAN NERNEY 178 OVETV EW c r 178 Information ATea iocus ewe wt RE toe RU e Ea be deu ee 180 Operation ced eed d Maniac dais d cepted aped ied ted be ede bid s 180 Timing Using the Flash Frequency Registers 0 0 00 20 eee eee 181 Flash Read Protection eec eot dine aide UR Dee UST Gade wie a als 181 Flash Write Erase Protection 0 0 cece eee I 181 Byte Programming i i o deer a ee ee a 182 Pase Erase egere Debe di eto dodi er wie brenda P tei ue rd eke 183 MasS Br se 22s ber beer Rer gr Redde eee irre KERE dX ne n 184 Flash Controller Bypass lsleeeeeee III 184 Flash Controller Behavior in Debug Mode 0 0 0 0 eee eee eee 184 Flash Control Register Definitions 0 0 cee eee eee 185 Flash Control Register 5 new edi bee nee ba eA D GR 185 Flash Status Register seco ita ves ado Whee Ree a ee 186 Page Select Register 2 0 0 0 eee ccc cette eens 187 Flash Sector Protect Register 0 2 cece cece teens 188 Flash Frequency High and Low Byte Registers 0 0 00 00005 189 Option Bits 6 9 6 sie ssa ss o REX RE ERGO Hae E Rau eO Gu qa E S a 190 OVEIVIEW eh cerebro e oer e tu Eo ree dre eia iot SD Fotos bete pio 190 UC MEER
17. Flash Control FCTL FF8H Write Only D7 D6 D5 D4 D3 D2 D1 D0 L Flash Command L WDT reload value 23 16 WDT reload value 15 8 L WDT reload value 7 0 73H First unlock command 8CH Second unlock command 95H Page erase command 63H Mass erase command 5EH Flash Sector Protect reg select Control Register Summary TENENT IMOQOO000000 010 62245566 13810019655 Flash Status FSTAT FF8H Read Only D7 D6 D5 D4 D3D2DI DO Flash Controller Status 00 0000 Flash controller locked 00 0001 First unlock received 00 0010 Second unlock received 00 0011 Flash controller unlocked 00 0100 Flash Sector Protect register selected 00 Ixxx Programming in progress 01 Oxxx Page erase in progress 10 Oxxx Mass erase in progress Reserved Page Select FPS FF9H Read Write D7 D6 D5 DA D3ID2IDI DO Page Select 6 0 Identifies the Flash memory page for Page Erase operation Information Area Enable 0 Information Area access is disabled 2 Information Area access is enabled Flash Sector Protect FPROT FF9H Read Write to 1 s D7 D6 D5 DA D3DD2IDI DO Flash Sector Protect 7 0 0 Sector can be programmed or erased from user code 1 Sector is
18. Z8 Encore 64K Series Product Specification 44 ZiLOG System Reset During a System Reset the 64K Series devices are held in Reset for 66 cycles of the Watch Dog Timer oscillator followed by 16 cycles of the system clock At the beginning of Reset all GPIO pins are configured as inputs During Reset the eZ8 CPU and on chip peripherals are idle however the on chip crystal oscillator and Watch Dog Timer oscillator continue to run The system clock begins oper ating following the Watch Dog Timer oscillator cycle count The eZ8 CPU and on chip peripherals remain idle through the 16 cycles of the system clock Upon Reset control registers within the Register File that have a defined Reset value are loaded with their reset values Other control registers including the Stack Pointer Regis ter Pointer and Flags and general purpose RAM are undefined following Reset The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H and loads that value into the Program Counter Program execution begins at the Reset vector address Reset Sources Table 9 lists the reset sources as a function of the operating mode The text following pro vides more detailed information on the individual Reset sources A Power On Reset Volt age Brown Out event always takes priority over all other possible reset sources to ensure a full system reset occurs Table 9 Reset Sources and Resulting Reset Type Operating Mode Reset S
19. 12 GPIO port pin interrupt sources 12 on chip peripheral interrupt sources e Flexible GPIO interrupts 8 selectable rising and falling edge GPIO interrupts 4 dual edge interrupts e 3 levels of individually programmable interrupt priority e Watch Dog Timer can be configured to generate an interrupt Interrupt requests IRQs allow peripheral devices to suspend CPU operation in an orderly manner and force the CPU to start an interrupt service routine ISR Usually this interrupt service routine is involved with the exchange of data status information or control infor mation between the CPU and the interrupting peripheral When the service routine is com pleted the CPU returns to the operation from which it was interrupted The eZ8 CPU supports both vectored and polled interrupt handling For polled interrupts the interrupt control has no effect on operation Refer to the eZ8 CPU User Manual for more information regarding interrupt servicing by the eZ8 CPU The eZ8 CPU User Man ual is available for download at www zilog com Interrupt Vector Listing Table 23 lists all of the interrupts available in order of priority The interrupt vector is stored with the most significant byte MSB at the even Program Memory address and the least significant byte LSB at the following odd Program Memory address PS019915 1005 Interrupt Controller htt p ww xi npi an net DOT 010 62245566 13810019655
20. System Bus v Transmit Data Register v Control Registers v Status Register Baud Rate Generator Transmit Shift TXD Register L Parity Generator Transmitter Control CTS DE Figure 13 UART Block Diagram Operation Data Format The UART always transmits and receives data in an 8 bit data format least significant bit first An even or odd parity bit can be optionally added to the data stream Each character begins with an active Low Start bit and ends with either 1 or 2 active High Stop bits Figures 14 and 15 illustrates the asynchronous data format employed by the UART with out parity and with parity respectively PS019915 1005 htt p ww xi npi an net 0 DET Iq10U U UU UART 010 62245566 13810019655 lt q Data Field Z8 Encore 64K Series Product Specification L w ZiLOG Idle State of Line Isb Stop Bit s sb 1 V Start Bito Y Bit Y Bit2 y Bit3 i Bit4 Bit5 y Bit6 0 CE 1 1 r 2 Figure 14 UART Asynchronous Data Format without Parity E Data Field Stop Bit s Idle State of Line Isb msb 1 T l A Sen Bito y Bit Bit2 y Bit3 Bit4 Bit5 Y Bit6 I Bit7 Y Pari 0 Eg r 2 Figure 15 UART Asynchronous
21. 0 0 0 0 0 ee eee eee 85 Timer 0 3 PWM High and Low Byte Registers 0 0 0 0 c eee eee 87 Timer 0 3 Control O Registers 2 0 0 ccc ee 88 Timer 0 3 Control 1 Registers 2 0 0 2 cece eee eee 88 Watch Dog Timer 0 e re Rr re Rh Re RI he ee cea ae 91 OVEIVICW T TIT 91 Op eratioB peeo rsen per tb ee IDE aad ru ren PR Rue Ge ee bs eee 91 Watch Dog Timer Refresh leseeeeeeeeeeee ees 92 Watch Dog Timer Time Out Response 0 0 0 0c eee eee eee 92 Watch Dog Timer Reload Unlock Sequence 0 000 eee eee 93 Watch Dog Timer Control Register Definitions 0 0 0 e eee eee eee 94 Watch Dog Timer Control Register 0 0 0 cece eee eee 94 Watch Dog Timer Reload Upper High and Low Byte Registers 95 UART ex dk 3X ERESEEARAREEREREERAGWEGERREFUEEERSERGERERPSERG EP X Rp E PUE 98 OVEIVICW iu osuere vane do edge i ote dee duet Rohde wot ode eed aot atas 98 ATChitectute lt 2 54 Aland d Biedaedaseuendd DbeUESO OU ged ante da diego bib edes 98 Operation cesso nce So Re Ee ee RE T ee 99 Data our RETI PCR 99 Transmitting Data using the Polled Method 0 000000 02 eee 100 Transmitting Data using the Interrupt Driven Method 101 Receiving Data using the Polled Method 0 00020 e eee 102 Receiving Data using the Interrupt Driven Method 4 103 PS019915 1005 Table of Contents htt p w
22. 010 62245566 13810019655
23. TCLK E gt XIN E z T1 j T2 p d gt Output I T3 T4 lt gt gt Input Figure 52 On Chip Debugger Timing Table 115 On Chip Debugger Timing Delay ns Parameter Abbreviation Min Max DBG T XIN Rise to DBG Valid Delay 30 T5 XIN Rise to DBG Output Hold Time 2 T5 DBG to XIN Rise Input Setup Time 10 T4 DBG to XIN Rise Input Hold Time 5 DBG frequency System Clock 4 PS019915 1005 Electrical Characteristics htt p ww xi npi an net OR ee DE EET HS o a 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Zi ZiLOG SPI Master Mode Timing Figure 53 and Table 116 provide timing information for SPI Master mode pins Timing is shown with SCK rising edge used to source MOSI output data SCK falling edge used to sample MISO input data Timing on the SS output pin s is controlled by software sox T1 i gt Output l T2 T3 e a N Input e l l Figure 53 SPI Master Mode Timing Table 116 SPI Master Mode Timing Delay ns Parameter Abbreviation Min Max SPI Master T SCK Rise to MOSI output Valid Delay 5 5 T5 MISO input to SCK receive edge Setup Time 20 T5 MISO input to SCK receive edge Hold Time 0 PS019915 1005 Electrical Characteristics htt p ww xi npi an net OR ee DE EET HS o a 010 62245566 13810019655 Z8 Encore 64K Series Pro
24. When congured as a general purpose timer the SPI BRG interrupt interval is calculated using the following equation SPI BRG Interrupt Interval s System Clock Period s xBRG 15 0 Table 67 SPI Baud Rate High Byte Register SPIBRH BITS 7 6 5 4 3 2 1 0 FIELD BRH RESET 1 R W R W ADDR F66H BRH SPI Baud Rate High Byte Most significant byte BRG 15 8 of the SPI Baud Rate Generator s reload value Table 68 SPI Baud Rate Low Byte Register SPIBRL BITS 7 6 5 4 3 2 1 0 FIELD BRL RESET 1 R W R W ADDR F67H PS019915 1005 htt p ww xi npi an net o HAMANI ELE T HE BRL SPI Baud Rate Low Byte Least significant byte BRG 7 0 of the SPI Baud Rate Generator s reload value Serial Peripheral Interface 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 139 ZiLOG PC Controller Overview The I C Controller makes the 64K Series products bus compatible with the PCm proto col The C Controller consists of two bidirectional bus lines a serial data signal SDA and a serial clock signal SCL Features of the IC Controller include Transmit and Receive Operation in MASTER mode e Maximum data rate of 400kbit sec e 7 and 10 bit addressing modes for Slaves Unrestricted number of data bytes transmitted per transfer The C C
25. Z8 Encore 64K Series Product Specification ZiLOG The Page Select FPS register Table 93 selects one of the 128 available Flash memory pages to be erased or programmed Each Flash Page contains 512 bytes of Flash memory During a Page Erase operation all Flash memory locations with the 7 most significant bits of the address given by the PAGE field are erased to FFH The Page Select register shares its Register File address with the Flash Sector Protect Reg ister The Page Select register cannot be accessed when the Flash Sector Protect register is enabled BITS 7 6 4 3 1 0 FIELD INFO_EN PAGE RESET 0 R W R W ADDR FF9H INFO_EN Information Area Enable 0 Information Area is not selected 1 Information Area is selected The Information area is mapped into the Flash Memory address space at addresses FEO OH through FFFFH PAGE Page Select This 7 bit field selects the Flash memory page for Programming and Page Erase opera tions Flash Memory Address 15 9 PAGE 6 0 PS019915 1005 htt p ww xi npi an net uu IG i uu UU Flash Memory 010 62245566 13810019655 187 Z8 Encore 64K Series Product Specification L as ZiLOG Flash Sector Protect Register The Flash Sector Protect register Table 94 protects Flash memory sectors from being programmed or erased from user code The Flash Sector Pr
26. Z8X6422 64 and 68 pin 7 0 7 0 7 0 7 0 7 0 7 3 3 0 Z8X6423 80 pin 7 0 7 0 7 0 7 0 7 0 7 0 7 0 3 0 Architecture Figure 10 illustrates a simplified block diagram of a GPIO port pin In this figure the abil ity to accommodate alternate functions and variable port current drive strength are not illustrated Port Input Schmitt Trigger Data Register Q D lt System Clock VDD Port Output Control Port Output Data Register CJ DATA Bs D Q gt o Port Pin System Clock gt y Port Data Direction oie GND Figure 10 GPIO Port Pin Block Diagram GPIO Alternate Functions Many of the GPIO port pins can be used as both general purpose I O and to provide access to on chip peripheral functions such as the timers and serial communication devices The Port A H Alternate Function sub registers configure these pins for either general purpose PS019915 1005 General Purpose I O htt p ww xi npi an net LEE EB DRE EL EE EGET ET VE Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 53 ZiLOG T O or alternate function operation When a pin is configured for alternate function control of the port pin direction input output is passed from the Port A H Data Direction regis ters to the alternate function a
27. 0 0 0 0 ee eee 6 Signal Descriptions eri cedar y ede eda eig e rade p Ra Oe ud 13 Pin Characteristics of the 64K Series llle 16 Z8 Encore 64K Series Program Memory Maps sess 18 Z8 Encore 64K Series Information Area Map 20 64K Series Register File Address Map eleeleesees 21 Reset and STOP Mode Recovery Characteristics and Latency 43 Reset Sources and Resulting Reset Type 0 000000 008 44 STOP Mode Recovery Sources and Resulting Action 47 Port Availability by Device and Package Type 51 Port Alternate Function Mapping 0 0 cece ee 53 Port A H GPIO Address Registers PXADDR 20 0005 55 GPIO Port Registers and Sub Registers 0 0 0 0 ee aes 55 Port A H Control Registers PXCTL 0 0 c eee eee 56 Port A H Data Direction Sub Registers 0 0 0 0 00 00 eae 57 Port A H Alternate Function Sub Registers 00 57 Port A H Output Control Sub Registers sleeeeeeeesn 58 Port A H High Drive Enable Sub Registers 00 59 Port A H Input Data Registers PXIN sees 60 Port A H STOP Mode Recovery Source Enable Sub Registers 60 Port A H Output Data Register PXOUT esses eese 61 Interrupt Vectors in Order of Priority 0 0 0 0 cece eee eee 63 Interrupt Request 0 Register IRQO 0 0
28. PA1 TOOUT wo A 39 44 X PDA RXD1 no SE PA6 SCL 17 AVDD PBO ANAO PB1 ANA1 PB4 ANA4 PB5 ANA5 PB6 ANA6 9 PB7 ANA7 PB3 ANA3 PB2 ANA2 VREF AVSS Z8 Encore 64K Series PA7 PD6 PC3 VSS Product Specification ZiLOG SDA CTS1 SCK VDD PC7 PC6 T2OUT T2IN DBG PC1 PCO VSS TIOUT TAIN Figure 4 64K Series in 44 Pin Low Profile Quad Flat Package LQFP PS019915 1005 htt p ww xi npi an net uu IG i uu UU Signal and Pin Descriptions 010 62245566 13810019655 PAO TOIN PD2 PC2 SS RESET VDD PE4 PE3 VSS PE2 PE1 PEO VSS PD1 T3OUT PDO T3IN XOUT XIN PA2 DEO PA3 CTSO VSS VDD PF7 PC5 MISO r PD3 DE1 PD5 TXD1 PC4 MOSI VDD VSS PA4 RXDO PA5 TXDO Z8 Encore 64K Series Product Specification Z ZiLOG Az BL PA1 TOOUT amp PD4 RXD1 amp PA6 SCL Co n 25 L PA7 SDA PD6 CTS1 L PC3 SCK i PD7 RCOUT VSS PE5 PE6 PE7 VDD PG3 VDD PC7 T20UT PC6 T2IN DBG PC1 T1OUT 17L PCO T1IN VSS AVDD PHO ANA8 PH1 ANA9 PBO ANAO PB1 ANA1 PB4 ANA4 PB5 ANA5
29. PS019915 1005 htt p ww xi npi an net EE I2C Controller HHHEHEHIGBUHBBHBHH 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 153 ZiLOG register during a read from a slave The IC Shift Register is not accessible in the Register File address space but is used only to buffer incoming and outgoing data Table 69 C Data Register I2ZCDATA BITS 7 6 5 4 3 2 1 0 FIELD DATA RESET 0 R W R W ADDR F50H I2C Status Register The Read only PC Status register Table 70 indicates the status of the PC Controller Table 70 I C Status Register I2CSTAT BITS 7 6 5 4 3 D 1 0 FIELD TDRE RDRF ACK 10B RD TAS DSS NCKI RESET 1 0 R W R ADDR F51H PS019915 1005 htt p ww xi npi an net OTe PSEP ELE T H E TDRE Transmit Data Register Empty When the C Controller is enabled this bit is 1 when the C Data register is empty When this bit is set an interrupt is generated if the TXI bit is set except when the rc Controller is shifting in data during the reception of a byte or when shifting an address and the RD bit is set This bit is cleared by writing to the I2CDATA register RDRF Receive Data Register Full This bit is set 1 when the IC Controller is enabled and the C Controller has received a byte of data When asserted this bit causes the PC Controller to g
30. Port Alternate Function enabled 0 The port pin is in normal mode and the DDx bit in the Port A H Data Direction sub register determines the direction of the pin 1 The alternate function is selected Port pin operation is controlled by the alternate function Port A H Output Control Sub Registers The Port A H Output Control sub register Table 18 is accessed through the Port A H Control register by writing 03H to the Port A H Address register Setting the bits in the Port A H Output Control sub registers to 1 configures the specified port pins for open drain operation These sub registers affect the pins directly and as a result alternate func tions are also affected Table 18 Port A H Output Control Sub Registers BITS 7 6 5 4 3 2 1 0 FIELD POC7 POC6 POCS POC4 POC3 POC2 POCI POCO RESET 0 R W R W ADDR If 03H in Port A H Address Register accessible through Port A H Control Register PS019915 1005 htt p ww xi npi an net Hg g dg p B m POC 7 0 Port Output Control These bits function independently of the alternate function bit and disables the drains if set to 1 0 The drains are enabled for any output mode 1 The drain of the associated pin is disabled open drain mode General Purpose I O IG1 D U DLE 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 59 ZiLOG Port A H High Drive
31. Table 47 Watch Dog Timer Control Register WDTCTL BITS 7 6 5 4 2 0 FIELD POR STOP WDT EXT Reserved SM RESET See descriptions below 0 R W R ADDR FFOH PS019915 1005 Watch Dog Timer htt p ww xi npi an net IHROMGA EE H E 010 62245566 13810019655 Z8 Encore 64K Series Product Specification VAR ZiLOG Reset or STOP Mode Recovery Event POR STOP WDT EXT Power On Reset 1 0 0 0 Reset using RESET pin assertion 0 0 0 1 Reset using Watch Dog Timer time out 0 0 1 0 Reset using the On Chip Debugger OCDCTL 1 set to 1 1 0 0 0 Reset from STOP Mode using DBG Pin driven Low 1 0 0 0 STOP Mode Recovery using GPIO pin transition 0 1 0 0 STOP Mode Recovery using Watch Dog Timer time out 0 1 1 0 POR Power On Reset Indicator If this bit is set to 1 a Power On Reset event occurred This bit is reset to 0 if a WDT time out or STOP Mode Recovery occurs This bit is also reset to O when the register is read STOP STOP Mode Recovery Indicator If this bit is set to 1 a STOP Mode Recovery occurred If the STOP and WDT bits are both set to 1 the STOP Mode Recovery occurred due to a WDT time out If the STOP bit is 1 and the WDT bit is 0 the STOP Mode Recovery was not caused by a WDT time out This bit is reset by a Power On Reset or a WDT time out that occurred while not in STOP mode Reading this register also resets this b
32. Vpp 3 0 3 6V TA 40 C to 125 C Symbol Parameter Minimum Maximum Units Conditions Fyyscik System Clock Frequency 20 0 MHz Read only from Flash memory 0 032768 20 0 MHz Program or erasure of the Flash memory FxpyAL Crystal Oscillator Frequency 0 032768 20 0 MHz System clock frequencies below the crystal oscillator minimum require an external clock driver TXIN Crystal Oscillator Clock Period 50 x ns Tory WF yscik Txiu System Clock High Time 20 ns TxINL System Clock Low Time 20 ns TxmR System Clock Rise Time 3 ns Top_K 50ns Slower rise times can be tolerated with longer clock periods TxiNF System Clock Fall Time 3 ns TopK 50ns Slower fall times can be tolerated with longer clock periods PS019915 1005 Electrical Characteristics htt p ww xi npi an net LEE EB DRE EL EE EGET ET VE Ooo 010 62245566 13810019655 224 General Purpose I O Port Input Data Sample Timing Z8 Encore 64K Series Product Specification 225 ZiLOG Figure 50 illustrates timing of the GPIO Port input sampling Table 113 lists the GPIO port input timing TCLK System Clock Port Value Changes to 0 GPIO Pin Input Value GPIO Input Latch Data Latch opened Into Port Input Data Register GPIO Data Register GPIO Data Value 0 Read Read on
33. ZiLOG ONE SHOT mode When the timer is disabled the Timer Output signal is set to the value of this bit When the timer is enabled the Timer Output signal is complemented upon timer Reload CONTINUOUS mode When the timer is disabled the Timer Output signal is set to the value of this bit When the timer is enabled the Timer Output signal is complemented upon timer Reload COUNTER mode When the timer is disabled the Timer Output signal is set to the value of this bit When the timer is enabled the Timer Output signal is complemented upon timer Reload PWM mode 0 Timer Output is forced Low 0 when the timer is disabled When enabled the Timer Output is forced High 1 upon PWM count match and forced Low 0 upon Reload 1 Timer Output is forced High 1 when the timer is disabled When enabled the Timer Output is forced Low 0 upon PWM count match and forced High 1 upon Reload CAPTURE mode 0 Count is captured on the rising edge of the Timer Input signal 1 Count is captured on the falling edge of the Timer Input signal COMPARE mode When the timer is disabled the Timer Output signal is set to the value of this bit When the timer is enabled the Timer Output signal is complemented upon timer Reload GATED mode 0 Timer counts when the Timer Input signal is High 1 and interrupts are generated on the falling edge of the Timer Input 1 Timer counts when the Timer Input signal is Low 0 and interrupt
34. dst XOR src r r B2 Q0 2 3 r Ir B3 2 4 R R B4 3 3 R IR B5 3 4 R IM B6 3 3 IR IM B7 3 4 XORX dst src dst dst XOR src ER ER B8 Q0 4 3 ER IM B9 4 3 Flags Notation Value is a function of the result of the operation 0 Reset to 0 Unaffected 1 Set to 1 X Undefined PS019915 1005 eZ8 CPU Instruction Set htt p ww xi npi an net ut CO FSEPET EU og 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 252 ZiLOG Flags Register The Flags Register contains the status information regarding the most recent arithmetic logical bit manipulation or rotate and shift operation The Flags Register contains six bits of status information that are set or cleared by CPU operations Four of the bits C V Z and S can be tested for use with conditional jump instructions Two flags H and D can not be tested and are used for Binary Coded Decimal BCD arithmetic The two remaining bits User Flags F1 and F2 are available as general purpose status bits User Flags are unaffected by arithmetic operations and must be set or cleared by instructions The User Flags cannot be used with conditional Jumps They are undefined at initial power up and are unaffected by Reset Figure 58 illustrates the flags and their bit positions in the Flags Register Bit Bit 7 0 Ic zis v p H F2 F1 Flags Register MS User Flags Half Carry Flag Decimal
35. 3 6V TA 40 C to 125 C Symbol Parameter Minimum Typical Maximum Units Conditions Fwpr WDT Oscillator Frequency 5 10 20 kHz Iwpt WDT Oscillator Current including I 5 pA internal RC oscillator PS019915 1005 Electrical Characteristics htt p ww xi npi an net LEE EB DRE EL EE EGET ET VE Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Zi ZiLOG Table 111 provides electrical characteristics and timing information for the Analog to Digital Converter Figure 49 illustrates the input frequency response of the ADC Table 111 Analog to Digital Converter Electrical Characteristics and Timing VDD 3 0 3 6V TA 40 C to 125 C Symbol Parameter Minimum Typical Maximum Units Conditions Resolution 10 bits External Vggp 3 0V Differential Nonlinearity 25 25 Iso Guaranteed by design DNL Integral Nonlinearity INL 3 0 1 0 3 0 lso External Vggg 3 0V DC Offset Error 35 25 mV DC Offset Error 50 25 mV 44 pin LQFP 44 pin PLCC and 68 pin PLCC packages VREF Internal Reference Voltage 1 9 2 0 2 4 V Vpp 3 0 3 6V T 40 C to 105 C VCggr Voltage Coefficient of 78 mV V Vggyp variation as a Internal Reference Voltage function of AVDD TCggp Temperature Coefficient of 1 mV C Internal Reference Voltage Single Shot Conversion 5129 cycles System
36. 5 Configure the associated GPIO port pin for the Timer Input alternate function 6 Write to the Timer Control 1 register to enable the timer 7 Counting begins on the first appropriate transition of the Timer Input signal No interrupt is generated by this first edge In m COMPARE mode the elapsed time from timer start to Capture event can be calcu lated using the following equation Capture Value Z Start Value x Prescale El Ti Capture Elapsed Time s System Clock Frequency Hz Reading the Timer Count Values The current count value in the timers can be read while counting enabled This capability has no effect on timer operation When the timer is enabled and the Timer High Byte reg ister is read the contents of the Timer Low Byte register are placed in a holding register A subsequent read from the Timer Low Byte register returns the value in the holding register This operation allows accurate reads of the full 16 bit timer count value while enabled When the timers are not enabled a read from the Timer Low Byte register returns the actual value in the counter Timer Output Signal Operation Timer Output is a GPIO Port pin alternate function Generally the Timer Output is toggled every time the counter is reloaded Timer Control Register Definitions Timers 0 2 are available in all packages Timer 3 is only available in the 64 68 and 80 pin packages Timer 0 3 High and Low Byte Registers The Timer 0 3 High
37. 9 Software responds by reading the PC Data register which clears the RDRF bit If there is only one more byte to receive set the NAK bit of the PC Control register 10 If there are more bytes to transfer return to step 7 11 After the last byte is shifted in a Not Acknowledge interrupt is generated by the PC Controller 12 Software responds by setting the STOP bit of the PC Control register 13 A STOP condition is sent to the PC slave the STOP and NCKI bits are cleared Read Transaction with a 10 Bit Address Figure 33 illustrates the read transaction format for a 10 bit addressed slave The shaded regions indicate data transferred from the PC Controller to slaves and unshaded regions indicate data transferred from the slaves to the I C Controller Slave Address Slave Address Slave Address 1st 7 bits 2nd Byte 1st 7 bits Figure 33 Receive Data Format for a 10 Bit Addressed Slave The first seven bits transmitted in the first byte are 11110xx The two bits XX are the two most significant bits of the 10 bit address The lowest bit of the first byte transferred is the write control bit The data transfer procedure for a read operation to a 10 bit addressed slave is as follows PS019915 1005 12C Controller htt p ww xi npi an net ugagamBmgmuagdisqiudtut Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification A ZiLOG 1 Software writes 11110B followed by th
38. D7 D6DD5 D4ID3D2D1 DO I2C Baud Rate divisor 7 0 PS019915 1005 Control Register Summary htt p ww xi npi an net COA ee ee DELI 010 62245566 13810019655 SPI Status SPISTAT F62H Read Only D7 D6 D5 D4 D3 D2 D1 DO L Slave Select 0 If Slave SS pin is asserted 1 If Slave SS pin is not asserted L Transmit Status 0 No data transmission in progress 1 Data transmission now in progress Reserved Slave Mode Transaction Abort 0 No slave mode transaction abort detected 1 Slave mode transaction abort was detected Collision 0 2 No multi master collision detected 1 Multi master collision was detected Overrun 0 2 No overrun error detected 1 Overrun error was detected Interrupt Request SPI Mode 0 No SPI interrupt request pending 1 SPI interrupt request is pending SPIMODE F63H Read Write D7 D6 lD5 D4 D3 D2 D1 DO L Slave Select Value If Master and SPIMODE 1 1 0 SS pin driven Low 1 SS pin driven High L Slave Select I O 0 SS pin configured as an input 1 2 SS pin configured as an output Master mode only L Number of Data Bits Per Character 000 8 bits 001 1 bit 010 2 bits 011 3 bits 100 4 bits 101 2 5 bit 110 6 bit
39. High Performance 8 Bit Microcontrollers Z8 Encoref 64K Series Product Specification PS019915 1005 ZiLOG Worldwide Headquarters 532 Race Street San Jose CA 95126 3432 Telephone 408 558 8500 Fax 408 558 8300 www ZiLOG com htt p ww xi npi an net o Oe ee a og 010 62245566 13810019655 Z ZiLOG This publication is subject to replacement by a later edition To determine whether a later edition exists or to request copies of publications contact ZiLOG Worldwide Headquarters 532 Race Street San Jose CA 95126 Telephone 408 558 8500 Fax 408 558 8300 www ZiLOG com Document Disclaimer ZiLOG is a registered trademark of ZiLOG Inc in the United States and in other countries All other products and or service names mentioned herein may be trademarks of the companies with which they are associated 2005 by ZiLOG Inc All rights reserved Information in this publication concerning the devices applications or technology described is intended to suggest possible uses and may be superseded ZiLOG INC DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION DEVICES OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION DEVICES OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE Devices sold by ZiLOG Inc are covered
40. co PB6 ANA6 PB7 ANA7 PB3 ANA3 PB2 ANA2 PH2 ANA10 PHS3 ANA11 VREF AVSS Figure 5 64K Series in 64 Pin Low Profile Quad Flat Package LQFP PS019915 1005 htt p ww xi npi an net uu IG i uu UU Signal and Pin Descriptions 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z ZILO G 5 o O Oo oo Oo o o ya AA a E Sacks amp iio qaoonon0Ormruoosox00c sxiudo aconodauoa aaaoancgg xc c xs x aaa gt naauannaad o 5nunmwxmu l TES ae ee TE o eoo o ESS E 1 61 PAO TOIN 10 60 PA7 SDA PD2 t PD6 CTS1 PC2 SS PC3 SCK RESET 4 i PD7 RCOUT VDD r VSS PE4 PES PE3 PE6 vss L PE7 PE2 18 52 VDD PE1 PG3 PEO j VDD vss PC7 T20UT VDD PC6 T2lN PD1 T3OUT p DBG PDO TSIN PC1 T1OUT XOUT PCO T1IN XIN 26 44 VSS OP ee v Oe 43 rt LH LT tT yt tT T S tt tT PP I 283323222322z 5989 aco SO eS Nx orortrtTuoorR ON gt T I d m cec e em ce cdm ce e c a anncannnantir C n Figure 6 64K Series in 68 Pin Plastic Leaded Chip Carrier PLCC PS019915 1005 Signal and Pin Descriptions htt p ww xi npi an net LEE EB DRE EL EE EGET ET VE Oo 010 62245566 13810019655 PA1 TOOUT PA2 DEO PA3 CTSO VSS
41. ee eee eee 66 Interrupt Request 1 Register IRQ1 0 eee eee eee 68 Interrupt Request 2 Register IRQ2 0 2c eee eee eee 68 IRQO Enable and Priority Encoding 0 0 2c ee eee eee 69 IRQO Enable High Bit Register IRQOENH lessen 69 IRQO Enable Low Bit Register IRQOENL sese 70 IRQI Enable and Priority Encoding lsseleleeeeee eee ee 70 IRQI Enable Low Bit Register IRQIENL 020 000 eee 71 IRQ2 Enable and Priority Encoding 0 0 0 ee eee eae 71 List of Tables LEER ETONE ESEP oe 010 62245566 13810019655 xiv Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 PS019915 1005 htt p ww xi npi an net Z8 Encore 64K Series Product Specification ZiLOG IRQI Enable High Bit Register IRQIENH 2 0 0 71 IRQ2 Enable Low Bit Register IRQ2ENL 00000 72 IRQ2 Enable High Bit Register IRQ2ENH 000 72 Interrupt Edge Select Register IRQES 0 0 02 eee eee eee 73 Interrupt Port Select Register IRQPS 20 0
42. 001 CONTINUOUS mode 010 COUNTER mode 011 PWM mode 100 CAPTURE mode 101 COMPARE mode 110 GATED mode 111 Capture COMPARE mode L Prescale Value 000 Divide by 1 001 Divide by 2 010 Divide by 4 011 Divide by 8 100 Divide by 16 101 Divide by 32 110 Divide by 64 111 Divide by 128 Timer Input Output Polarity Operation of this bit is a function of the current operating mode of the timer Timer Enable 0 Timer is disabled 1 Timer is enabled Timer 1 High Byte TIH FO8H Read Write D7 D6 D5 D4 D3 D2 D1 D0 Timer 1 current count value 15 8 Timer 1 Low Byte TIL FO9H Read Write D7 D6 DSID4 D3 D2 DI DO _____________ Timer 1 current count value 7 0 Timer 1 Reload High Byte TIRH FOAH Read Write D7 D6 D5 D4 D3 D2 DI DO ____________ Timer 1 reload value 15 8 Timer 1 Reload Low Byte TIRL FOBH Read Write D7 D6 D5 D4 D3D2DI1 DO Timer 1 reload value 7 0 Control Register Summary htt p ww xi npi an net Hg g dg p B m IG1U D UU UU 010 62245566 13810019655 Timer 1 PWM High Byte TIPWMH FOCH Read Write D7 D6 D5 D4ID3 D2DD1 DO Timer 1 PWM value 15 8 Timer 1 PWM Low Byte TIPWML FODH Read Write
43. 04H High drive enable 05H STOP mode recovery enable 06H FFH No function Port H Control PHCTL FEDH Read Write D7 D6 D5 D4 D3 D2DD1 DO jo Reserved Port H Input Data PHIN FEEH Read Only D7 D6D5 D4ID3D2D1 DO jo Reserved Port H Output Data PHOUT FEFH Read Write D7 D6DD5 D4ID3D2DD1 DO LL Reserved PS019915 1005 htt p ww xi npi an net Port H Control 3 0 Provides Access to Port Sub Registers Port H Input Data 3 0 Port H Output Data 3 0 Z8 Encore 64K Series Watch Dog Timer Control WDTCTL FFOH Read Only D7 D6 D5 DA4ID3 D2 D1 DO Reserved EXT WDT STOP POR Z8 Encore Z ZiLOG SM Configuration Indicator 0 Reset not generated by RESET pin 1 Reset generated by RESET pin 0 WDT timeout has not occurred 1 WDT timeout occurred 0 SMR has not occurred 1 SMR has occurred 0 POR has not occurred 1 POR has occurred Watch Dog Timer Reload Upper Byte WDTU FF1H Read Write D7 D6ID5 DAID3ID2 DI DO Watch Dog Timer Reload Middle Byte WDTH FF2 H Read Write D7 D6 D5 D4ID3 D2ID1 DO Watch Dog Timer Reload Low Byte WDTL FF3H Read Write D7 D6 DS D4 D3 D2 D1 DO
44. 1250 0 1 1041 69 16 67 1250 0 N A N A N A 625 0 2 520 8 16 67 625 0 1 691 2 10 59 250 0 4 260 4 4 17 250 0 3 230 4 7 84 115 2 9 115 7 0 47 115 2 6 115 2 0 00 57 6 18 57 87 0 47 57 6 12 57 6 0 00 38 4 27 38 6 0 47 38 4 18 38 4 0 00 19 2 54 19 3 0 47 19 2 36 19 2 0 00 9 60 109 9 56 0 45 9 60 72 9 60 0 00 4 80 217 4 80 0 83 4 80 144 4 80 0 00 2 40 434 2 40 0 01 2 40 288 2 40 0 00 1 20 868 1 20 0 01 1 20 576 1 20 0 00 0 60 1736 0 60 0 01 0 60 1152 0 60 0 00 PS019915 1005 UART htt p ww xi npi an net EE OTe PSEP ELE T Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z ZiLOG Table 60 UART Baud Rates Continued 0 30 3472 0 30 0 01 0 30 2304 0 30 0 00 10 0 MHz System Clock 5 5296 MHz System Clock Desired Rate BRG Divisor Actual Rate Error Desired Rate BRG Divisor Actual Rate Error kHz Decimal kHz kHz Decimal kHz 1250 0 N A N A N A 1250 0 N A N A N A 625 0 1 625 0 0 00 625 0 N A N A N A 250 0 3 208 33 16 67 250 0 1 345 6 38 24 115 2 5 125 0 8 51 115 2 3 115 2 0 00 57 6 11 56 8 1 36 57 6 6 57 6 0 00 38 4 16 39 1 1 73 38 4 9 38 4 0 00 19 2 33 18 9 0 16 19 2 18 19 2 0 00 9 60 65 9 62 0 16 9 60 36 9 60 0 00 4 80 130 4 81 0 16 4 80 72 4 80 0 00 2 40 260 2 40 0 03 2 40 144 2 40 0 00 1 20 521 1 20 0 03 1 20 288 1 20 0 00 0 60 1042 0 60 0 03
45. D7 D6 ID5 DAID3 ID2 DI DO Timer 1 PWM value 7 0 Timer 1 Control 0 TICTLO FOEH Read Write D7ID6ID5 D4D3DD2DDI DO Reserved Cascade Timer 0 Timer Input signal is GPIO pin 1 Timer 1 Input signal is Timer 0 out Reserved Timer 1 Control 1 TICTLI FOFH Read Write D7 D6 D5 D4 D3 D2 D 1 D0 L Timer Mode 000 One Shot mode 001 CONTINUOUS mode 010 COUNTER mode 011 PWM mode 100 CAPTURE mode 101 COMPARE mode 110 GATED mode 111 Capture COMPARE mode Prescale Value 000 Divide by 1 001 Divide by 2 010 Divide by 4 011 Divide by 8 100 Divide by 16 101 Divide by 32 110 Divide by 64 111 Divide by 128 Timer Input Output Polarity Operation of this bit is a function of the current operating mode of the timer Timer Enable 0 Timer is disabled 1 Timer is enabled PS019915 1005 Z8 Encore 64K Series Z8 Encore Z ZiLOG Timer 2 High Byte T2H F10H Read Write D7 D6 D5 DA4ID3 D2 D1 DO Timer 2 current count value 15 8 Timer 2 Low Byte T2L FIIH Read Write D7 D6 D5 D4 D3 D2 D1 D0 Timer 2 current count value 7 0 Timer 2 Reload High Byte T2RH F12H Read Write D7 D6 D5 D4 D3 D2 D1 DO Timer 2 reload value 15
46. Error detection e Dedicated Baud Rate Generator Architecture The SPI may be configured as either a Master in single or multi master systems or a Slave as illustrated in Figures 22 through 24 SPI Master To Slave s SS Pin 5S l MISO 8 bit Shift Register From Slave Bit 0 A Bit 7 l To Slave a MOSI l l l SCK Baud Rate l To Slave i i Lea a ue 4 Figure 22 SPI Configured as a Master in a Single Master Single Slave System PS019915 1005 Serial Peripheral Interface htt p ww xi npi an net utu ee ee EU og 010 62245566 13810019655 Z8 Encore 64K Series Product Specification L ZiLOG vcc SPI Master I To Slave 2 s SS Pin lt GPIO To Slave 1 s SS Pin _4 GPIO 8 bit Shift Register Bit 0 A Bit 7 From Slave To Slave MOSI To SI SCK Baud Rate o slave Generator oe E 8 bit Shift Register Bit 7 A Bit 0 To Master From Master From Master Figure 24 SPI Configured as a Slave Operation The SPI is a full duplex synchronous character oriented channel that supports a four wire interface serial clock transmit receive and Slave select The SPI block consists of a transmit receive shift register a Baud Rate clock Generator and a control unit PS019915 1005 Serial P
47. Only receiver errors generate an interrupt request PS019915 1005 UART htt p ww xi npi an net DOT 010 62245566 13810019655 IREN Infrared Encoder Decoder Enable 0 Infrared Encoder Decoder is disabled UART operates normally operation 1 Infrared Encoder Decoder is enabled The UART transmits and receives data through the Infrared Encoder Decoder UART Address Compare Register Z8 Encore 64K Series Product Specification 115 ZiLOG The UART Address Compare register Table 57 stores the multi node network address of the UART When the MPMD 1 bit of UART Control Register 0 is set all incoming address bytes are compared to the value stored in the Address Compare register Receive interrupts and RDA assertions only occur in the event of a match Table 57 UART Address Compare Register Ux ADDR BITS 7 6 5 4 3 FIELD COMP ADDR RESET 0 R W R W ADDR F45H and FADH UART Baud Rate High and Low Byte Registers COMP ADDR Compare Address This 8 bit value is compared to the incoming address bytes The UART Baud Rate High and Low Byte registers Tables 58 and 59 combine to create a 16 bit baud rate divisor value BRG 15 0 that sets the data transmission rate baud rate of the UART To configure the Baud Rate Generator as a timer with interrupt on time out complete the following procedure 1 Dis
48. RESET 0 R W R W R WI R WI R W R W R WI WI R W ADDR F52H PS019915 1005 htt p ww xi npi an net Hg g dg p B m IEN I C Enable 1 The C transmitter and receiver are enabled 0 The C transmitter and receiver are disabled START Send Start Condition This bit sends the Start condition Once asserted it is cleared by the PC Controller after it sends the START condition or if the TEN bit is deasserted If this bit is 1 it cannot be cleared to 0 by writing to the register After this bit is set the Start condition is sent if there is data in the C Data or C Shift register If there is no data in one of these registers the PC Controller waits until the Data register is written If this bit is set while the PC Con troller is shifting out data it generates a START condition after the byte shifts and the acknowledge phase completes If the STOP bit is also set it also waits until the STOP con dition is sent before the sending the START condition STOP Send Stop Condition This bit causes the IC Controller to issue a Stop condition after the byte in the PC Shift register has completed transmission or after a byte has been received in a receive opera tion Once set this bit is reset by the PC Controller after a Stop condition has been sent or by deasserting the IEN bit If this bit is 1 it cannot be cleared to 0 by writing to the regis ter BIRQ Baud Rate Generator Interrupt Request This bit allows the C Contro
49. Reading the Baud Rate High and Low Byte registers returns the baud rate counter value PS019915 1005 12C Controller htt p ww xi npi an net o CO FSEPET EU og 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 161 ZiLOG Direct Memory Access Controller Overview The 64K Series Direct Memory Access DMA Controller provides three independent Direct Memory Access channels Two of the channels DMAO and DMA1 transfer data between the on chip peripherals and the Register File The third channel DMA_ADC controls the Analog to Digital Converter ADC operation and transfers SINGLE SHOT mode ADC output data to the Register File Operation DMAO and DMA1 Operation DMAO and DMA1 referred to collectively as DMAx transfer data either from the on chip peripheral control registers to the Register File or from the Register File to the on chip peripheral control registers The sequence of operations in a DMAx data transfer is 1 DMAx trigger source requests a DMA data transfer 2 DMAx requests control of the system bus address and data from the eZ8 CPU 3 Afterthe eZ8 CPU acknowledges the bus request DMAx transfers either a single byte or a two byte word depending upon configuration and then returns system bus control back to the eZ8 CPU 4 f Current Address equals End Address DMA x reloads the original Start Address If confi
50. Tggspr RESET pin assertion to 4 Tcrk Notin STOP Mode initiate a System Reset Tcrk System Clock period Tsmr STOP Mode Recovery pin 10 20 40 ns RESET DBG and GPIO pins Pulse Rejection Period configured as SMR sources PS019915 1005 Electrical Characteristics htt p ww xi npi an net LEE EB DRE EL EE EGET ET VE Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification L z ZiLOG Table 109 list the Flash Memory electrical characteristics and timing Table 109 Flash Memory Electrical Characteristics and Timing Vpp 3 0 3 6V T4 40 C to 125 C Parameter Minimum Typical Maximum Units Notes Flash Byte Read Time 50 ns Flash Byte Program Time 20 40 us Flash Page Erase Time 10 ms Flash Mass Erase Time 200 ms Writes to Single Address Before 2 Next Erase Flash Row Program Time 8 ms Cumulative program time for single row cannot exceed limit before next erase This parameter is only an issue when bypassing the Flash Controller Data Retention 100 years 25 C Endurance 40 to 105 C 10 000 cycles Program erase cycles Endurance 106 to 125 C 1 000 cycles Program erase cycles Table 110 lists the Watch Dog Timer electrical characteristics and timing Table 110 Watch Dog Timer Electrical Characteristics and Timing Vpp 3 0
51. These 2 bytes TMRH 7 0 TMRL 7 0 contain the current 16 bit timer count value Timer Reload High and Low Byte Registers The Timer 0 3 Reload High and Low Byte TxRH and TxRL registers Tables 40 and 41 store a 16 bit reload value TRH 7 0 TRL 7 0 Values written to the Timer Reload High Byte register are stored in a temporary holding register When a write to the Timer Reload Low Byte register occurs the temporary holding register value is written to the Timer High Byte register This operation allows simultaneous updates of the 16 bit Timer Reload value In COMPARE mode the Timer Reload High and Low Byte registers store the 16 bit Compare value PS019915 1005 Timers htt p ww xi npi an net o ee ee a og 010 62245566 13810019655 Z8 Encore 64K Series Product Specification ZiLOG Table 40 Timer 0 3 Reload High Byte Register TxRH BITS 7 6 5 4 0 FIELD TRH RESET 1 R W R W ADDR F02H FOAH F12H FIAH Table 41 Timer 0 3 Reload Low Byte Register TxRL BITS 7 6 5 4 0 FIELD TRL RESET 1 R W R W ADDR F03H FOBH F13H FIBH TRH and TRL Timer Reload Register High and Low These two bytes form the 16 bit Reload value TRH 7 0 TRL 7 0 This value sets the maximum count value which initiates a timer reload to 0001H In COMPARE mode these two byte form the 16 b
52. Uu UU Ordering Information 010 62245566 13810019655 266 Part Number Suffix Designations Z8 F 64 21 Z8 Encore 64K Series Product Specification ZiLOG A N 020 S C Environmental Flow C Plastic Standard G Lead Free Package Temperature Range C S Standard 0 to 70 E Extended 40 to 105 A Automotive Industrial 40 to 125 Speed 020 20MHz Pin Count M 40 pins N 44 pins R 64 pins S 68 pins T 80 pins Package A LQFP F QFP P PDIP V PLCC Device Type Memory Size 64 KB Flash 4 KB RAM 48 KB Flash 4 KB RAM 32 KB Flash 2 KB RAM 24 KB Flash 2 KB RAM 16 KB Flash 2 KB RAM Memory Type F Flash Device Family Example Part number Z8F6421 ANO20SC is an 8 bit microcontroller product in an LQFP package using 44 pins operating with a maximum 20MHz external clock frequency over a 0 C to 70 C temperature range and built using the Plastic Standard environmental flow PS019915 1005 htt p ww xi npi an net Ordering Information uu IG1 D U DLE 010 62245566 13810019655 267 Z8 Encore 64K Series Product Specification Z x ZiLOG Document Information Document Number Description The Document Control Number that appears in the footer on each page of this document contains unique identifying attributes as indicated in the
53. Z 191 ZiLOG Flash Memory Address 0000H Table 97 Flash Option Bits At Flash Memory Address 0000H BITS 7 6 5 4 3 2 1 0 FIELD WDT RES WDT AO OSC SEL 1 0 VBO AO RP Reserved FWP RESET U R W R W ADDR Program Memory 0000H Note U Unchanged by Reset R W Read Write WDT_RES Watch Dog Timer Reset 0 Watch Dog Timer time out generates an interrupt request Interrupts must be globally enabled for the eZ8 CPU to acknowledge the interrupt request 1 Watch Dog Timer time out causes a Short Reset This setting is the default for unpro grammed erased Flash WDT AO Watch Dog Timer Always On 0 Watch Dog Timer is automatically enabled upon application of system power Watch Dog Timer can not be disabled except during STOP Mode if configured to power down during STOP Mode 1 Watch Dog Timer is enabled upon execution of the WDT instruction Once enabled the Watch Dog Timer can only be disabled by a Reset or STOP Mode Recovery This set ting is the default for unprogrammed erased Flash OSC_SEL 1 0 Oscillator Mode Selection 00 On chip oscillator configured for use with external RC networks lt 4MHz 01 Minimum power for use with very low frequency crystals 32KHz to 1 0MHz 10 Medium power for use with medium frequency crystals or ceramic resonators 0 5MHz to 10 0MHz 11 Maximum power for use with high frequency crystals 8 0MHz to 20 0MHz This setti
54. ZiLOG TXD Transmit Data UART transmitter data byte to be shifted out through the TXDx pin UART Receive Data Register Data bytes received through the RXDx pin are stored in the UART Receive Data register Table 52 The Read only UART Receive Data register shares a Register File address with the Write only UART Transmit Data register Table 52 UART Receive Data Register UxRXD BITS 7 6 5 4 3 2 1 0 FIELD RXD RESET X R W R ADDR F40H and F48H RXD Receive Data UART receiver data byte from the RXDx pin UART Status 0 Register The UART Status 0 and Status 1 registers Table 53 and 54 identify the current UART operating configuration and status Table 53 UART Status 0 Register UxSTATO BITS 7 6 5 4 3 2 1 0 FIELD RDA PE OE FE BRKD TDRE TXE CTS RESET 0 1 X R W R ADDR F41H and F49H RDA Receive Data Available This bit indicates that the UART Receive Data register has received data Reading the UART Receive Data register clears this bit 0 The UART Receive Data register is empty 1 There is a byte in the UART Receive Data register PS019915 1005 htt p ww xi npi an net D U Uu UU UART 010 62245566 13810019655 Z8 Encore 64K Series Product Specification ZiLOG PE Parity Error This bit indicates that a parity error has occurred Rea
55. addresses FOOH to FFFH DMAx Address High Nibble Register The DMAx Address High register Table 78 specifies the upper four bits of address for the Start Current and End Addresses of DMAx Table 78 DMAx Address High Nibble Register DMAxH BITS 7 6 5 4 3 2 1 0 FIELD DMA END H DMA START H RESET X R W R W ADDR FB2H FBAH PS019915 1005 Direct Memory Access Controller i DEL EE EE TERT ELLE 0O 010 62245566 13810019655 htt p ww xi npi an net Z8 Encore 64K Series Product Specification L ZiLOG DMA_END_H DMAx End Address High Nibble These bits used with the DMAx End Address Low register form a 12 bit End Address The full 12 bit address is given by DMA_END_H 3 0 DMA END 7 0 DMA START H DMAx Start Current Address High Nibble These bits used with the DMAx Start Current Address Low register form a 12 bit Start Current Address The full 12 bit address is given by DMA START H 3 0 DMA_START 7 0 DMAx Start Current Address Low Byte Register The DMAx Start Current Address Low register in conjunction with the DMAx Address High Nibble register forms a 12 bit Start Current Address Writes to this register set the Start Address for DMA operations Each time the DMA completes a data transfer the 12 bit Start Current Address increments by either 1 single byte transfer or 2 two byte word transfer R
56. by warranty and limitation of liability provisions appearing in the ZiLOG Inc Terms and Conditions of Sale ZiLOG Inc makes no warranty of merchantability or fitness for any purpose Except with the express written approval of ZiLOG use of information devices or technology as critical components of life support systems is not authorized No licenses are conveyed implicitly or otherwise by this document under any intellectual property rights PS019915 1005 htt p ww xi npi an net ugagamBpmmuagdisqiaudtt Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification ZiLOG Revision History Each instance in Table 1 reflects a change to this document from its previous revi sion To see more detail click the appropriate link in the table Table 1 Revision History of this Document Revision Date Level Description Page January 12 Added Die Form Sales information to Table 1 2 2005 March 13 Provided timing equation when the Baud Rate Generator for a 109 115 2005 peripheral is used as a simple timer Closes CR 5618 131 137 155 August 14 Updated Manual Objectives on page xviii Introduction on page 1 Available 2005 Packages on page 6 Program Memory on page 18 Flash Memory on page 178 Option Bits on page 190 On Chip Debugger Commands on page 198 Absolute Maximum Ratings on page 209 DC Characteristics on page 211 Figure 48 on page
57. control interrupting only on frames that match the UART s address When an incoming address byte does not match the UART s address it is ignored All successive data bytes in this frame are also ignored When a matching address byte occurs an interrupt is issued and further interrupts now occur on each succesive data byte The first data byte in the frame contains the NEWFRM 1 in the UART Status 1 Register When the next address byte occurs the hardware compares it to the UART s address If there is a match the interrupts continue sand the NEWFRM bit is set for the first byte of the new frame If there is no match then the UART ignores all incoming bytes until the next address match The third scheme is enabled by setting MPMD 1 0 to 11b and by writing the UART s address into the UART Address Compare Register This mode is identical to the second scheme except that there are no interrupts on address bytes The first data byte of each frame is still accompanied by a NEWFRM assertion External Driver Enable The UART provides a Driver Enable DE signal for off chip bus transceivers This feature reduces the software overhead associated with using a GPIO pin to control the transceiver when communicating on a multi transceiver bus such as RS 485 Driver Enable is an active High signal that envelopes the entire transmitted data frame including parity and Stop bits as illustrated in Figure 17 The Driver Enable signal asserts when a byte is wri
58. mode fault error con dition Slave Operation The SPI block is configured for slave mode operation by setting the SPIEN bit to 1 and the MMEN bit to 0 in the SPICTL register and setting the SSIO bit to 0 in the SPIMODE reg PS019915 1005 Serial Peripheral Interface htt p ww xi npi an net COA ee ee DELI 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 131 ZiLOG ister The IRQE PHASE CLKPOL WOR bits in the SPICTL register and the NUMBITS field in the SPIMODE register must be set to be consistent with the other SPI devices The STR bit in the SPICTL register may be used if desired to force a startup interrupt The BIRQ bit in the SPICTL register and the SSV bit in the SPIMODE register are not used in slave mode The SPI baud rate generator is not used in slave mode so the SPIBRH and SPIBRL registers need not be initialized If the slave has data to send to the master the data must be written to the SPIDAT register before the transaction starts first edge of SCK when SS is asserted If the SPIDAT regis ter is not written prior to the slave transaction the MISO pin outputs whatever value is currently in the SPIDAT register Due to the delay resulting from synchronization of the SPI input signals to the internal sys tem clock the maximum SPICLK baud rate that can be supported in slave mode is the sys tem clock frequency XIN divided by 8 This rate is controlled by the SPI master Error
59. must be initialized to select the PC transmit and receive requests Transmit DMA requests require that the TXI bit in the PC Control regis ter be set AN Caution A transmit write DMA operation hangs if the slave responds with a Not Acknowledge before the last byte has been sent After receiving the Not Acknowledge the PC Controller sets the NCKI bit in the Status register and pauses until either the STOP or START bits in the Control register are set PS019915 1005 12C Controller htt p ww xi npi an net DOTA 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Zi ZiLOoG In order for a receive read DMA transaction to send a Not Acknowledge on the last byte the receive DMA must be set up to receive n 1 bytes then software must set the NAK bit and receive the last nth byte directly Start and Stop Conditions The master PO drives all Start and Stop signals and initiates all transactions To start a transaction the IC Controller generates a START condition by pulling the SDA signal Low while SCL is High To complete a transaction the PC Controller generates a Stop condition by creating a low to high transition of the SDA signal while the SCL signal is high The START and STOP bits in the PC Control register control the sending of the Start and Stop conditions A master is also allowed to end one transaction and begin a new one by issuing a Restart This is accomplished
60. src Test Complement Under Mask using Extended Addressing TM dst src Test Under Mask TMX dst src Test Under Mask using Extended Addressing Table 126 Block Transfer Instructions Mnemonic Operands Instruction LDCI dst src Load Constant to from Program Memory and Auto Increment Addresses LDEI dst src Load External Data to from Data Memory and Auto Increment PS019915 1005 Addresses eZ8 CPU Instruction Set htt p ww xi npi an net utu ee ee EU og 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Zi ZiLOG Table 127 CPU Control Instructions Mnemonic Operands Instruction ATM Atomic Execution CCF Complement Carry Flag DI Disable Interrupts EI Enable Interrupts HALT HALT Mode NOP No Operation RCF Reset Carry Flag SCF Set Carry Flag SRP src Set Register Pointer STOP STOP Mode WDT Watch Dog Timer Refresh Table 128 Load Instructions Mnemonic Operands Instruction CLR dst Clear LD dst src Load LDC dst src Load Constant to from Program Memory LDCI dst src Load Constant to from Program Memory and Auto Increment Addresses LDE dst src Load External Data to from Data Memory LDEI dst src Load External Data to from Data Memory and Auto Increment Addresses LDWX dst src Load Word using Extended Ad
61. the receiver Stop Bit Select 0 Transmitter sends 1 Stop bit 1 Transmitter sends 2 Stop bits Send Break 0 No break is sent 1 Output of the transmitter is zero Parity Select 0 Even parity 1 Odd parity Parity Enable 0 Parity is disabled 1 Parity is enabled CTS Enable 0 CTS signal has no effect on the transmitter 1 UART recognizes CTS signal as a transmit enable control signal Receive Enable 0 Receiver disabled 1 Receiver enabled Transmit Enable 0 Transmitter disabled 1 Transmitter enabled Control Register Summary 010 62245566 13810019655 UARTI Control 1 UOCTLI F4BH Read Write D7 D6 D5 D4 D3 D2D1 DO L Infrared Encoder Decoder Enable 0 Infrared endec is disabled 1 Infrared endec is enabled L Received Data Interrupt Enable 0 Received data and errors generate interrupt requests 1 Only errors generate interrupt requests Received data does not Baud Rate Registers Control Refer to UART chapter for operation Driver Enable Polarity 0 DE signal is active High 1 DE signal is active Low Multiprocessor Bit Transmit 0 Send a 0 as the multiprocessor bit 1 Senda 1 as the multiprocessor bit Multiprocessor Mode 0 See Multiprocessor Mode 1 below Multiprocessor 9 bit Enable 0 Multiprocessor mode is disabled 1 Multiprocessor mode is enabled Multiprocessor Mode 1 with Mul
62. 0 cece eee eee 73 Interrupt Control Register IRQCTL 0 0 cece eee 74 Timer 0 3 High Byte Register TXH eeeeeeeeeeee 85 Timer 0 3 Low Byte Register TXL 0 0 0 cece eee eee eee 85 Timer 0 3 Reload High Byte Register TXRH 0 86 Timer 0 3 Reload Low Byte Register TXRL 0 86 Timer 0 3 PWM High Byte Register TXPWMH 87 Timer 0 3 PWM Low Byte Register TXPWML eeseessss 87 Timer 0 3 Control 0 Register TXCTLO lsleeseseeeeesn 88 Timer 0 3 Control 1 Register TXCTL1 sese 88 Watch Dog Timer Approximate Time Out Delays 92 Watch Dog Timer Control Register WDTCTL esses 94 Watch Dog Timer Reload Upper Byte Register WDTU 96 Watch Dog Timer Reload High Byte Register WDTH 96 Watch Dog Timer Reload Low Byte Register WDTL 97 UART Transmit Data Register UXTXD 0 0 0 0 000 109 UART Receive Data Register UXRXD 0 000 cee eee ee 110 UART Status 0 Register UXSTATO 20 0 cece eee 110 UART Status 1 Register UxSTAT1 20 0 0 ananena 112 UART Control 0 Register UXCTLO 0 0 0 0 eee ee eee 112 UART Control 1 Register UxCTL1 00 00 00 cee eee ee 113 UART Address Compare Register UXADDR 0 115 UART Baud Rate High Byte Register UXBRH
63. 010 COUNTER mode 011 PWM mode 100 CAPTURE mode 101 COMPARE mode 110 GATED mode 111 CAPTURE COMPARe mode EH OOO Moo OU Timers 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 91 ZiLOG Watch Dog Timer Overview The Watch Dog Timer WDT helps protect against corrupt or unreliable software power faults and other system level problems which may place the Z8 Encore into unsuitable operating states The Watch Dog Timer includes the following features e On chip RC oscillator e A selectable time out response e WDT Time out response Reset or interrupt e 24 bit programmable time out value Operation The Watch Dog Timer WDT is a retriggerable one shot timer that resets or interrupts the 64K Series devices when the WDT reaches its terminal count The Watch Dog Timer uses its own dedicated on chip RC oscillator as its clock source The Watch Dog Timer has only two modes of operation ON and OFF Once enabled it always counts and must be refreshed to prevent a time out An enable can be performed by executing the WDT instruction or by setting the WDT AO Option Bit The WDT AO bit enables the Watch Dog Timer to operate all the time even if a WDT instruction has not been executed The Watch Dog Timer is a 24 bit reloadable downcounter that uses three 8 bit registers in the eZ8 CPU register space to set the reload value The nominal WDT time ou
64. 116 UART Baud Rate Low Byte Register UXBRL 116 UART Baud Rates 0 0 0 cen eens 117 SPI Clock Phase PHASE and Clock Polarity CLKPOL Operation 128 SPI Data Register SPIDATA seen 133 SPI Control Register SPICTL sseeseeeeeeeeeeeee 134 SPI Status Register SPISTAT 0 0 0 cece eee eee 135 SPI Mode Register SPIMODE sees 136 SPI Diagnostic State Register SPIDST 0 0008 137 SPI Baud Rate High Byte Register SPIBRH lesse 138 List of Tables u uggaggaagatrqirnrtut OU 010 62245566 13810019655 XV Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 Table 79 Table 80 Table 81 Table 82 Table 83 Table 84 Table 85 Table 86 Table 87 Table 88 Table 89 Table 90 Table 91 Table 92 Table 93 Table 94 Table 95 Table 96 Table 97 Table 98 Table 99 Table 100 Table 101 Table 102 Table 103 Table 104 Table 105 PS019915 1005 htt p ww xi npi an net Z8 Encore 64K Series Product Specification ZiLOG SPI Baud Rate Low Byte Register SPIBRL sees 138 I2C Data Register IZCDATA sssesee eee 153 DC Status Register I2CSTAT 0 0 0 cee eee 153 I2C Control Register I2CCTL 0 0 0 0 eee 155 I2C Baud Rate High Byte Register IDCBRH 1
65. 218 On Chip Peripheral AC and DC Electrical Characteristics on page 219 AC Characteristics on page 224 Ordering Information on page 262 and Part Number Suffix Designations on page 267 Removed Preliminary from all pages Deleted first sentence of Electrical Characteristics chapter Deleted Precharacterization Product section in the Packaging chapter Added automotive industrial parts removed all ROM references October 15 The paragraph tag for Ordering Information has been changed from 262 2005 H1 Heading to Chapter Title PS019915 1005 htt p ww xi npi an net utu ee ee EU og 010 62245566 13810019655 Z8 Encore 64K Series Product Specification ZiLOG Table of Contents Revision History 3 054 aed4 dni eo Raed oe baka an qe es aud OS ae Hh de eee dates ii Table of Contents ssp eerie 0c cece cece ce reece cence hh hh hh nnn iv List of Figures PPP UT xi List of Tables 2 25 kR ES Re rS EEO E Sr RS os xiv Manual Objectives ie scsi epe rherR e mra Em E nee SER Cole PES EE E RE xviii About This Manual 20 0 0c cece m rn xviii Intended Audience sssssseseeeeeeee DE DEEE eee nee xviii Manual Conventions 0 0 0 cece eh hn xviii Sale SU ards sos ais dal E get vs so dace doe Ra e Xd e se ver d XX Trademarks edere Uem t ie BANS Un EE Ae RR pid es edad d XX Introduction 2 0 ccc ccc ccc cere reece eee e nee e eee teen teen ee hh
66. 24 2 46 4 12 2 1 1 X Z8F3221 32 2 31 3 8 2 1 1 X Z8F3222 32 2 46 4 12 2 1 1 X Z8F4821 48 4 31 3 8 2 1 1 X Z8F4822 48 4 46 4 12 2 1 1 X Z8F4823 48 4 60 4 12 2 1 1 X Z8F6421 64 4 31 3 8 2 1 1 X Z8F6422 64 4 46 4 12 2 1 1 X Z8F6423 64 4 60 4 12 2 1 1 X Die Form Please Sales contact ZiLOG PS019915 1005 Introduction htt p ww xi npi an net ugugmgmgmuadrqiudt Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z ZiLOG Block Diagram Figure 1 illustrates the block diagram of the architecture of the Z8 Encore 64K Series XTAL RC On Chip Oscillator i gt Debugger e78 POR VBO CPU Interrupt ts Ray WDT with System Controller ontroller RC Oscillator Clock lt y Memory Busses Register Bus Y ALLII Ll Timers UARTs Ko SPI ADC l DMA Flash RAM Controller Controller PUT P NE Memory y Y y y y GPIO RAM Figure 1 Z8 Encore 64K Series Block Diagram CPU and Peripheral Overview eZ8 CPU Features The eZ8 ZiLOG s latest 8 bit Central Processing Unit CPU meets the continuing demand for faster and more code efficient microcontrollers The eZ8 CPU executes a superset of the original Z8 instruction set The
67. 3 1 An interrupt request from Timer 3 is awaiting service Interrupt Controller 010 62245566 13810019655 Z8 Encore 64K Series Product Specification L a ZiLOG UIRXI UART 1 Receive Interrupt Request 0 No interrupt request is pending for the UARTI receiver 1 An interrupt request from UARTI receiver is awaiting service UITXI UART 1 Transmit Interrupt Request 0 No interrupt request is pending for the UART 1 transmitter 1 An interrupt request from the UART 1 transmitter is awaiting service DMAI DMA Interrupt Request 0 No interrupt request is pending for the DMA 1 An interrupt request from the DMA is awaiting service PCxI Port C Pin x Interrupt Request 0 No interrupt request is pending for GPIO Port C pin x 1 An interrupt request from GPIO Port C pin x is awaiting service where x indicates the specific GPIO Port C pin number 0 through 3 IRQO Enable High and Low Bit Registers The IRQO Enable High and Low Bit registers Tables 28 and 29 form a priority encoded enabling for interrupts in the Interrupt Request 0 register Priority is generated by setting bits in each register Table 27 describes the priority control for IRQO Table 27 IRQ0 Enable and Priority Encoding IRQOENH x IRQOENL x Priority Description 0 0 Disabled Disabled 0 1 Level 1 Low 1 0 Level 2 Nominal 1 1 Level 3 High where x indicates the regis
68. 3 8 1 1 2 PLCC 44 pin package Z8F4822AR020EC 48KB 4KB 46 24 4 12 1 1 2 LQFP 64 pin package Z8F4822VS020EC 48KB 4KB 46 24 4 12 1 1 2 PLCC 68 pin package Z8F4823FTO20EC 48KB 4KB 46 24 4 12 1 1 2 QFP 80 pin package Automotive Industrial Temperature 40 to 125 C Z8F4821PMO020AC 48KB 4KB 29 23 3 8 1 1 2 PDIP 40 pin package Z8F4821 ANO20AC 48KB 4KB 31 23 3 8 1 1 2 LQFP 44 pin package Z8F4821VNO020AC 48KB 4KB 31 23 3 8 1 1 2 PLCC 44 pin package Z8F4822AR020AC 48KB 4KB 46 24 4 12 1 1 2 LQFP 64 pin package Z8F4822VS020AC 48KB 4KB 46 24 4 12 1 1 2 PLCC 68 pin package Z8F4823FTO20AC 48KB 4KB 46 24 4 12 1 1 2 QFP 80 pin package Note Replace C with G for lead free packaging PS019915 1005 Ordering Information htt p ww xi npi an net LH uam ai ood DLE 010 62245566 13810019655 263 Z8 Encore 64K Series Product Specification ZiLOG Part Number Flash lt x oc O Lines nterrupts 16 Bit Timers w PWM 10 Bit A D Channels o N SPI UARTS with IrDA Description Standard Temperature 0 to 70 C Digital Z8F322x with 32KB Flash 10 Bit Analog to Converter Z8F3221PM020SC 32KB 2KB 29 23 3 8 1 1 2 PDIP 40 pin package Z8F3221ANO020SC 32KB 2KB 31 23 3 8 1 1 2 LQFP 44 pin package Z8F3221VN020SC 32KB 2KB 31 23 3 8 1 1 2 PLCC 44 pin package Z8F3222AR020SC 32KB 2KB 46 24 4 12 1 1 2 LQ
69. 3FFFH 2K 2048 8 4 Z8F242x 24K 24 576 48 0000H SFFFH 4K 4096 6 8 Z8F322x 32K 32 768 64 0000H 7FFFH 4K 4096 8 8 Z8F482x 48K 49 152 96 0000H BFFFH 8K 8192 6 16 Z8F642x 64K 65 536 128 0000H FFFFH 8K 8192 8 16 PS019915 1005 Flash Memory htt p ww xi npi an net ugagamBpmmuagdisqiaudtt Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Zi ZiLOG Table 89 Flash Memory Sector Addresses Flash Sector Address Ranges Sector Number Z8F162x Z8F242x Z8F322x Z8F482x Z8F642x 0 0000H 07FFH 0000H 0FFFH 0000H 0FFFH 0000H 1FFFH 0000H 1FFFH 1 0800H 0FFFH 1000H 1FFFH 1000H 1FFFH 2000H 3FFFH 2000H 3FFFH 2 1000H 17FFH 2000H 2FFFH 2000H 2FFFH 4000H 5FFFH 4000H 5FFFH 3 1800H 1FFFH 3000H 3FFFH 3000H 3FFFH 6000H 7FFFH 6000H 7FFFH 4 2000H 27FFH 4000H 4FFFH 4000H 4FFFH 8000H 9FFFH 8000H 9FFFH 5 2800H 2FFFH 5000H 5FFFH 5000H 5FFFH AO000H BFFFH A000H BFFFH 6 3000H 37FFH N A 6000H 6FFFH N A C000H DFFFH 7 3800H 3FFFH N A 7000H 7FFFH N A E000H FFFFH 64KB Flash Program Memory Addresses FFFFH FEOOH FDFFH FCOOH FBFFH 7 FAOOH l 1 128 Pages 512 Bytes per Page Y O5FFH 0400H 03FFH 0200H 01FFH 0000H Figure 35 Flash Memory Arrangement PS019915 1005 Flash Memory htt p ww xi npi an net HE EB ELLE GTI E 7 D u t 010 62245566 13810019655
70. 4 obere tede exe rk be e e tre ee eae SUPRA E aed 205 Operatmg Modes oca nian dance pg ond dee pesar ance ui ec esa n 205 Crystal Oscillator Operation leeeeeeeeeee e 205 Oscillator Operation with an External RC Network 0 0 00 000005 207 Electrical Characteristics o66 25628 662s E Y GRRRERERREREE RE REREREGRRE ERRARE RS 209 Absolute Maximum Ratings lee 209 DC Characteristics a sntd med ont ROI OG ce eb Seiden dubi wie doped Ble 211 On Chip Peripheral AC and DC Electrical Characteristics llle 219 AG Characteristics se cce breui bete aw ea eth as E E O Er bie 224 General Purpose I O Port Input Data Sample Timing Ls 225 General Purpose I O Port Output Timing 0 0 0 eee eee eee eee 226 On Chip Debugger Timing 0 0 0 cece cece eee eee 227 SPI Master Mode Timing 0 0 0 eee cee cette 228 SPI Slave Mode Timing 0 cece ect eens 229 I2C Ding og secs cides ies x Era Sates a vata e aco en eda eee 230 UART Min ehe Por Lda a an a Oh ea Oe ca 231 eZ8 CPU Instruction Set ius ees tas pier ERR A X REX HEE OS ROSE GER Ro Ra des 233 Assembly Language Programming Introduction 0 0 02 eee eee 233 Assembly Language Syntax selle 234 eZ8 CPU Instruction Notation sseeeeeeeee ee 234 Condition Codes si a ci ee ete tbe be E Roe Ra oed eue Ob a a due 237 eZ8 CPU Instruction Classes 238 eZ8 CPU Instructio
71. 8 Timer 2 Reload Low Byte T2RL F13H Read Write D7 D6 D5 D4 D3 D2 D1 DO Timer 2 reload value 7 0 Timer 2 PWM High Byte T2PWMH F14H Read Write D7 D6 D5 D4 D3 D2 DI DO Timer 2 PWM value 15 8 Timer 2 PWM Low Byte T2PWML FI5H Read Write D7 D6 DSID4 D3 D2 DI DO Timer 2 PWM value 7 0 Timer 2 Control 0 T2CTLO F16H Read Write D7 D6 DSID4ID3ID2 DI DO Reserved Cascade Timer 0 Timer 2 Input signal is GPIO pin 1 Timer 2 Input signal is Timer 1 out Reserved Control Register Summary htt p ww xi npi an net EE TENENT IMOQOO000000 010 62245566 13810019655 Z8 Encore 64K Series Z8 Encore 28 ZiLOG Timer 2 Control 1 Timer 3 PWM High Byte T2CTL1 F17H Read Write T3PWMH F1CH Read Write D7 D6 D5 D4 D3D2DI DO D7 D6 D5 DA D3 D2IDI DO ____ Timer Mode LL Timer 3 PWM value 15 8 000 2 One Shot mode 001 2 CONTINUOUS mode 010 2 COUNTER mode SLE d Timer 3 PWM Low Byte gt mode n a ride T3PWML FIDH Read Write 110 GATED mode D7 D6 D5 D4 D3 D2 DI DO 111 CAPTURE COMPARE mode Timer 3 PWM value 7 0 L Prescale Value 00
72. Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag U Undefined Figure 58 Flags Register Interrupts the Software Trap TRAP instruction and Illegal Instruction Traps all write the value of the Flags Register to the stack Executing an Interrupt Return IRET instruc tion restores the value saved on the stack into the Flags Register PS019915 1005 eZ8 CPU Instruction Set htt p ww xi npi an net ugagamBpmmuagdisqiaudtt Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 253 ZiLOG Opcode Maps A description of the opcode map data and the abbreviations are provided in Figure 59 and Table 132 Figures 60 and 61 provide information on each of the eZ8 CPU instructions Opcode Lower Nibble Fetch Cycles Instruction Cycles Opcode Upper Nibble A First Operand Second Operand After Assembly After Assembly Figure 59 Opcode Map Cell Description PS019915 1005 Opcode Maps htt p ww xi npi an net LEE EB DRE EL EE EGET ET VE Ooo 010 62245566 13810019655 Table 132 Opcode Map Abbreviations Z8 Encore 64K Series Product Specification ZI ZiLOG Abbreviation Description Abbreviation Description b Bit position IRR Indirect Register Pair cc Condition code p Polarity 0 or 1 X 8 bit signed index or displacemen
73. Detection The SPI contains error detection logic to support SPI communication protocols and recog nize when communication errors have occurred The SPI Status register indicates when a data transmission error has been detected Overrun Write Collision An overrun error write collision indicates a write to the SPI Data register was attempted while a data transfer is in progress in either master or slave modes An overrun sets the OVR bit in the SPI Status register to 1 Writing a 1 to OVR clears this error flag The data register is not altered when a write occurs while data transfer is in progress Mode Fault Multi Master Collision A mode fault indicates when more than one Master is trying to communicate at the same time a multi master collision The mode fault is detected when the enabled Master s SS pin is asserted A mode fault sets the COL bit in the SPI Status register to 1 Writing a 1 to COL clears this error flag Slave Mode Abort In slave mode of operation if the SS pin deasserts before all bits in a character have been transferred the transaction is aborted When this condition occurs the ABT bit is set in the SPISTAT register as well as the IRQ bit indicating the transaction is complete The next time SS asserts the MISO pin outputs SPIDAT 7 regardless of where the previous trans action left off Writing a 1 to ABT clears this error flag SPI Interrupts When SPI interrupts are enabled the SPI generates an
74. During a single shot conversion this value is invalid Access to the ADC Data High Byte register is read only The full 10 bit ADC result is given by ADCD H 7 0 ADCD_L 7 6 Reading the ADC Data High Byte register latches data in the ADC Low Bits register Table 86 ADC Data High Byte Register ADCD H BITS 7 6 5 4 3 2 1 0 FIELD ADCD H RESET X R W R ADDR F72H ADCD_H ADC Data High Byte This byte contains the upper eight bits of the 10 bit ADC output These bits are not valid during a single shot conversion During a continuous conversion the last conversion out put is held in this register These bits are undefined after a Reset ADC Data Low Bits Register The ADC Data Low Bits register Table 87 contains the lower two bits of the conversion value The data in the ADC Data Low Bits register is latched each time the ADC Data High Byte register is read Reading this register always returns the lower two bits of the conversion last read into the ADC High Byte register Access to the ADC Data Low Bits PS019915 1005 Analog to Digital Converter htt p ww xi npi an net LEE EB DRE EL EE EGET ET VE Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification L ZiLOG register is read only The full 10 bit ADC result is given by ADCD H 7 0 ADCD L 7 6 Table 87 ADC Data Low Bits Register ADCD L
75. Flash programming and erasure is not supported for system clock frequen cies below 20KHz above 20MHz or outside of the valid operating fre quency range for the device The Flash Frequency High and Low Byte registers must be loaded with the correct value to insure proper program and erase times AN Caution Table 95 Flash Frequency High Byte Register FFREQH BITS 7 6 5 4 3 2 1 0 FIELD FFREQH RESET 0 R W R W ADDR FFAH Table 96 Flash Frequency Low Byte Register FFREQL BITS 7 6 5 4 3 2 1 0 FIELD FFREQL RESET 0 R W R W ADDR FFBH FFREQH and FFREQL Flash Frequency High and Low Bytes These 2 bytes FFREQH 7 0 FFREQL 7 0 contain the 16 bit Flash Frequency value PS019915 1005 Flash Memory htt p ww xi npi an net OTe PSER ELE T H E 189 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 190 ZiLOG Option Bits Overview Option Bits allow user configuration of certain aspects of the 64K Series operation The feature configuration data is stored in the Flash Memory and read during Reset The fea tures available for control via the Option Bits are Operation Watch Dog Timer time out response selection interrupt or Reset Watch Dog Timer enabled at Reset The ability to prevent unwanted read access to user code in Fla
76. PS019915 1005 Serial Peripheral Interface htt p ww xi npi an net LEE EB DRE EL EE EGET ET VE Ooo 010 62245566 13810019655 133 Z8 Encore 64K Series Product Specification L i ZiLOG Table 63 SPI Control Register SPICTL BITS 7 6 5 4 3 2 1 0 FIELD IRQE STR BIRQ PHASE CLKPOL WOR MMEN SPIEN RESET 0 R W R W ADDR F61H PS019915 1005 htt p ww xi npi an net Hg g dg p B m IRQE Interrupt Request Enable 0 SPI interrupts are disabled No interrupt requests are sent to the Interrupt Controller 1 SPI interrupts are enabled Interrupt requests are sent to the Interrupt Controller STR Start an SPI Interrupt Request 0 No effect 1 Setting this bit to 1 also sets the IRQ bit in the SPI Status register to 1 Setting this bit forces the SPI to send an interrupt request to the Interrupt Control This bit can be used by software for a function similar to transmit buffer empty in a UART Writing a 1 to the IRQ bit in the SPI Status register clears this bit to 0 BIRQ BRG Timer Interrupt Request If the SPI is enabled this bit has no effect If the SPI is disabled 0 The Baud Rate Generator timer function is disabled 1 The Baud Rate Generator timer function and time out interrupt are enabled PHASE Phase Select Sets the phase relationship of the data to the clock Refer to the SPI Clock Phase and Polarity Co
77. Port A Input Data PAIN FD2H Read Only D7 D6 D5 D4 D3 D2 D1 DO Port A Input Data 7 0 Port A Output Data PAOUT FD3H Read Write D7 D6 D5 DA4 D3 D2 D1 DO ____________ Port A Output Data 7 0 Control Register Summary htt p ww xi npi an net EE TENENT IMOQOO000000 010 62245566 13810019655 Port B Address PBADDR FD4H Read Write D7 D6 D5 D4 D3 D2DD1 DO ___________ Port B Address 7 0 Selects Port Sub Registers 00H No function 01H Data direction 02H Alternate function 03H z Output control open drain 04H High drive enable 05H STOP mode recovery enable 06H FFH No function Port B Control PBCTL FD5H Read Write D7 D6 D5 D4 D3 D2DD1 DO Port B Control 7 0 Provides Access to Port Sub Registers Port B Input Data PBIN FD6H Read Only D7 D6 D5 ID4ID3D2DD1 DO Port B Input Data 7 0 Port B Output Data PBOUT FD7H Read Write D7 D6 ID5 D4ID3D2ID1 DO ____________ Port B Output Data 7 0 Port C Address PCADDR FD8H Read Write D7 D6 D5 D4 D3 D2 D1 D0 L Port Address 7 0 Selects Port Sub Registers 00H No function 01H Data direction 02H Alternate
78. Port A or D Pin Interrupt Request 0 IRQ from corresponding pin 7 0 is not pending 1 IRQ from corresponding pin 7 0 is awaiting service IRQI Enable High Bit IRQIENH FC4H Read Write D7 D6 D5 DA4ID3 D2 D1 DO Port A or D Pin IRQ Enable High Bit IRQI Enable Low Bit IRQIENL FC5H Read Write D7 D6ID5ID4DD3D2 D1 D0 Port A or D Pin IRQ Enable Low Bit Control Register Summary TENENT IMOQOO000000 010 62245566 13810019655 Interrupt Request 2 IRQ2 FC6H Read Write D7 D6 D5 D4 D3 D2 D1 Do Port C Pin Interrupt Request 0 IRQ from corresponding pin 3 0 is not pending 1 IRQ from corresponding pin 3 0 is awaiting service L DMA Interrupt Request L UART 1 Transmitter Interrupt Request UART 1 Receiver Interrupt Request Timer 3 Interrupt Request For all of the above peripherals 0 Peripheral IRQ is not pending 1 Peripheral IRQ is awaiting service IRQ2 Enable High Bit IRQ2ENH FC7H Read Write D7 D6D5 D4ID3D2D1 D0 Port C Pin IRQ Enable High Bit L DMA IRQ Enable High Bit UART 1 Transmitter IRQ Enable High UART 1 Receiver IRQ Enable High Bit Timer 3 IRQ Enable High Bit IRQ2 Enable Low Bit IRQ2ENL FC8H Read Write D7 D6 D5 D4ID3 D2 D
79. Product Specification ziLog Table 132 eZ8 CPU Instruction Summary Continued Assembly ATEN MONE Opcode s ai Fetch Instr Mnemonic Symbolic Operation dst src Hex C Z S V D H Cycles Cycles ADD dst src dst lt dst src r r 02 NW we WO s Uy och 2 3 r Ir 03 2 4 R R 04 3 3 R IR 05 3 4 R IM 06 3 3 IR IM 07 3 4 ADDX dst src dst dst src ER ER 08 WU co sow pn Pw 4 3 ER IM 09 4 3 AND dst src dst dst AND src r r 52 Q0 2 3 r Ir 53 2 4 R R 54 3 3 R IR 55 3 4 R IM 56 3 3 IR IM 57 3 4 ANDX dst src dst dst AND src ER ER 58 Q0 4 3 ER IM 59 4 3 ATM Block all interrupt and 2F JE ZZ S ML 1 2 DMA requests during execution of the next 3 instructions BCLR bit dst dst bit lt 0 r E2 0 2 2 BIT p bit dst dst bit lt p r E2 0 2 2 BRK Debugger Break 00 JE eee 1 1 BSET bit dst dst bit 1 r E2 0 2 2 BSWAP dst dst 7 0 dst 0 7 R D5 X Q0 2 2 BTJ p bit src dst if src bit p r F6 LLLI At 3 3 PC lt PC X Ir F7 3 4 Flags Notation Value is a function of the result of the operation 0 Reset to 0 Unaffected 1 Set to 1 X Undefined PS019915 1005 eZ8 CPU Instruction Set htt p ww xi npi an net o ee ee a og 010 62245566 13810019655 243 Table 132 eZ8 CPU Instruction Summary Continued Z8 E
80. Purpose I O D U Uu LH 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Lle Port A H Output Data Register The Port A H Output Data register Table 22 writes output data to the pins Table 22 Port A H Output Data Register PxOUT BITS 7 6 5 4 3 2 1 0 FIELD POUT7 POUT6 POUTS POUT4 POUT3 POUT2 POUTI POUTO RESET 0 R W R W ADDR FD3H FD7H FDBH FDFH FE3H FE7H FEBH FEFH POUTT 7 0 Port Output Data These bits contain the data to be driven out from the port pins The values are only driven if the corresponding pin is configured as an output and the pin is not configured for alter nate function operation 0 Drive a logical 0 Low 1 Drive a logical 1 High High value is not driven if the drain has been disabled by set ting the corresponding Port Output Control register bit to 1 PS019915 1005 General Purpose I O htt p ww xi npi an net ut CO FSEPET EU og 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 62 ZiLOG Interrupt Controller Overview The interrupt controller on the 64K Series products prioritizes the interrupt requests from the on chip peripherals and the GPIO port pins The features of the interrupt controller include the following e 24 unique interrupt vectors
81. R W R W R W R W R W R W R W ADDR FCSH PADxENL Port A or Port D Bit x Interrupt Request Enable Low Bit Refer to the Interrupt Port Select register for selection of either Port A or Port D as the interrupt source IRQ2 Enable High and Low Bit Registers The IRQ2 Enable High and Low Bit registers Tables 34 and 35 form a priority encoded enabling for interrupts in the Interrupt Request 2 register Priority is generated by setting bits in each register Table 33 describes the priority control for IRQ2 Table 33 IRQ2 Enable and Priority Encoding IRQ2ENH x IRQ2ENL x Priority Description 0 0 Disabled Disabled 0 1 Level 1 Low 1 0 Level 2 Nominal 1 1 Level 3 High where x indicates the register bits from 0 through 7 PS019915 1005 htt p ww xi npi an net D U Uu UU Interrupt Controller 010 62245566 13810019655 71 Table 34 IRQ2 Enable High Bit Register IRQ2ENH Z8 Encore 64K Series Product Specification Z ZiLOG BITS 7 6 5 4 3 2 1 0 FIELD T3ENH UIRENH UITENH DMAENH C3ENH C2ENH CIENH COENH RESET 0 R W R W ADDR FC7H T3ENH Timer 3 Interrupt Request Enable High Bit UIRENH UART 1 Receive Interrupt Request Enable High Bit UITENH UART 1 Transmit Interrupt Request Enable High Bit DMAENH DMA Interrupt Request Enable High Bit C3ENH Port C3 Interrupt Request Enab
82. Select 0 The transmitter sends one stop bit 1 The transmitter sends two stop bits LBEN Loop Back Enable 0 Normal operation 1 All transmitted data is looped back to the receiver Table 56 UART Control 1 Register UxCTL1 BITS 7 6 5 4 3 2 1 0 FIELD MPMD 1 MPEN MPMD 0 MPBT DEPOL BRGCTL RDAIRQ IREN RESET 0 R W R W ADDR F43H and F4BH PS019915 1005 UART htt p ww Xi npi an net KATE TOTEH ri m u 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z 114 ZiLOG MPMD 1 0 MULTIPROCESSOR Mode If MULTIPROCESSOR 9 bit mode is enabled 00 The UART generates an interrupt request on all received bytes data and address 01 The UART generates an interrupt request only on received address bytes 10 The UART generates an interrupt request when a received address byte matches the value stored in the Address Compare Register and on all successive data bytes until an address mismatch occurs 11 The UART generates an interrupt request on all received data bytes for which the most recent address byte matched the value in the Address Compare Register MPEN MULTIPROCESSOR 9 bit Enable This bit is used to enable MULTIPROCESSOR 9 bit mode 0 Disable MULTIPROCESSOR 9 bit mode 1 Enable MULTIPROCESSOR 9 bit mode MPBT MULTIPROCESSOR Bit Transmit This bit is applicable on
83. Timer High and Low Byte registers to set the starting count value Write to the Timer Reload High and Low Byte registers to set the Reload value 4 If desired enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers 5 If using the Timer Output function configure the associated GPIO port pin for the Timer Output alternate function 6 Write to the Timer Control 1 register to enable the timer and initiate counting In ONE SHOT mode the system clock always provides the timer input The timer period is given by the following equation Reload Value Z Start Value x Prescale One Shot Mode Time Out Period s System Clock Frequency Hz CONTINUOUS Mode In CONTINUOUS mode the timer counts up to the 16 bit Reload value stored in the Timer Reload High and Low Byte registers The timer input is the system clock Upon reaching the Reload value the timer generates an interrupt the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes Also if the Timer Output alternate function is enabled the Timer Output pin changes state from Low to High or from High to Low upon timer Reload The steps for configuring a timer for CONTINUOUS mode and initiating the count are as follows 1 Write to the Timer Control 1 register to Disable the timer Configure the timer for CONTINUOUS mode Set the prescale value PS019915 1005 Timers htt
84. Transmission is complete CTS CTS signal When this bit is read it returns the level of the CTS signal PS019915 1005 UART htt p ww xi npi an net DOT 010 62245566 13810019655 UART Status 1 Register This register contains multiprocessor control and status bits Table 54 UART Status 1 Register UxSTAT1 Z8 Encore 64K Series Product Specification Z 112 ZiLOG BITS 7 6 5 2 1 0 FIELD Reserved NEWFRM MPRX RESET R W R W R ADDR F44H and F4CH Reserved Must be 0 NEWFRM Status bit denoting the start of a new frame Reading the UART Receive Data register resets this bit to 0 0 The current byte is not the first data byte of a new frame 1 The current byte is the first data byte of a new frame MPRX Multiprocessor Receive Returns the value of the last multiprocessor bit received Reading from the UART Receive Data register resets this bit to 0 UART Control 0 and Control 1 Registers The UART Control 0 and Control 1 registers Tables 55 and 56 configure the properties of the UART s transmit and receive operations The UART Control registers must not been written while the UART is enabled Table 55 UART Control 0 Register UxCTLO BITS 7 6 5 4 3 2 1 0 FIELD TEN REN CTSE PEN PSEL SBRK STOP LBEN RESET 0 R W R W ADDR F42H and F4AH TEN Tr
85. VDD PC5 MISO PD3 DE1 PD4 RXD1 PD5 TXD1 VDD VSS PA4 RXDO PA5 TXDO Z8 Encore 64K Series Product Specification PA6 SCL PAO TOIN PD2 PC2 SS PF6 RESET VDD PF5 PF4 PF3 PE4 PE3 vss PE2 PE1 4 PEO vss PF2 PF1 PFO VDD 4 PD1 T3OUT PDO T3IN XOUT XIN f eo 20 24 ait PF7 St PC4 MOSI oL ox A 60 55 50 45 Opn vss 4 AVDD PHO ANA8 PH1 ANA9 PBO ANAO PB1 ANA1 48 PB4 ANA4 PB5 ANA5 PB6 ANA6 PB7 ANA7 PB3 ANA3 amp PB2 ANA2 PH2 ANA10 PH3 ANA11 VREF Figure 7 64K Series in 80 Pin Quad Flat Package QFP PS019915 1005 htt p ww xi npi an net uu IG i uu UU AVSS A VAR ZiLOG PA7 SDA PD6 CTS1 PC3 SCK PD7 RCOUT PGO VSS PG1 PG2 PE5 PE6 PE7 L VDD PG3 PG4 PG5 I PG6 VDD PG7 PC7 T20UT PC6 T2IN DBG PC1 T1OUT PCO T1IN VSS Signal and Pin Descriptions 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z 13 ZiLOG Signal Descriptions Table 3 describes the Z8 Encore signals Refer to the section Pin Configurations on page 7 to determine the signals available for th
86. a Not Acknowledge condition is received during a write either during the address or data phases the PC Controller generates the Not Acknowledge interrupt NCKI 1 and pause until either the STOP or START bit is set Unless the Not Acknowledge was received on the last byte the Data register will already have been written with the next address or data byte to send In this case the FLUSH bit of the Control register should be set at the same time the STOP or START bit is set to remove the stale transmit data and enable subsequent Transmit interrupts When reading data from the slave the PC pauses after the data Acknowledge cycle until the receive interrupt is serviced and the RDRF bit of the status register is cleared by read PS019915 1005 I2C Controller htt p ww xi npi an net DOT 010 62245566 13810019655 Z8 Encore 64K Series Product Specification ZI ZiLOoG ing the PC Data register Once the PC data register has been read the C reads the next data byte Address Only Transaction with a 7 bit Address In the situation where software determines if a slave with a 7 bit address is responding without sending or receiving data a transaction can be done which only consists of an address phase Figure 28 illustrates this address only transaction to determine if a slave with a 7 bit address will acknowledge As an example this transaction can be used after a write has been done to a EEP
87. and Low Byte TxH and TxL registers Tables 38 and 39 contain the current 16 bit timer count value When the timer is enabled a read from TxH causes the value in TxL to be stored in a temporary holding register A read from TMRL always returns this temporary register when the timers are enabled When the timer is disabled reads from the TMRL reads the register directly Writing to the Timer High and Low Byte registers while the timer is enabled is not recom mended There are no temporary holding registers available for write operations so simul PS019915 1005 Timers htt p ww xi npi an net ugagamBpmmuagdisqiaudtt Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification L ZiLOG taneous 16 bit writes are not possible If either the Timer High or Low Byte registers are written during counting the 8 bit written value is placed in the counter High or Low Byte at the next clock edge The counter continues counting from the new value Timer 3 is unavailable in the 40 and 44 pin packages Table 38 Timer 0 3 High Byte Register TxH BITS 7 6 5 4 3 2 1 0 FIELD TH RESET 0 R W R W ADDR FOOH FO8H F10H F18H Table 39 gt Timer 0 3 Low Byte Register TxL BITS 7 6 5 4 3 2 1 0 FIELD TL RESET 0 1 R W R W ADDR F01H FO9H F11H F19H TH and TL Timer High and Low Bytes
88. appear in the Courier typeface Example R1 is set to F8H Brackets The square brackets indicate a register or bus PS019915 1005 Manual Objectives htt p ww xi npi an net DOT 010 62245566 13810019655 Z8 Encore 64K Series Product Specification xix ZiLOG Example for the register R1 7 0 R1 is an 8 bit register R1 7 is the most significant bit and R1 0 is the least significant bit Braces The curly braces indicate a single register or bus created by concatenating some com bination of smaller registers buses or individual bits Example the 12 bit register address 0H RP 7 4 R1 3 0 is composed of a 4 bit hexadecimal value 0H and two 4 bit register values taken from the Register Pointer RP and Working Register R1 0H is the most significant nibble 4 bit value of the 12 bit register and R1 3 0 is the least significant nibble of the 12 bit register Parentheses The parentheses indicate an indirect register address lookup e Example R1 is the memory location referenced by the address contained in the Working Register R1 Parentheses Bracket Combinations The parentheses indicate an indirect register address lookup and the square brackets indicate a register or bus e Example assume PC 15 0 contains the value 1234h PC 15 0 then refers to the contents of the memory location at address 1234h Use of the Words Set R
89. asserts the START bit of the I C Control register 3 If this is a single byte transfer Software asserts the NAK bit of the IC Control register so that after the first byte of data has been read by the PC Controller a Not Acknowledge is sent to the PC slave PS019915 1005 12C Controller htt p ww xi npi an net EE HHHEHEHIGBUHBBHBHH 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Zi ZiLOoG 4 The PC Controller sends the START condition The C Controller shifts the address and read bit out the SDA signal 6 Ifthe I C slave acknowledges the address by pulling the SDA signal Low during the next high period of SCL the PC Controller sets the ACK bit in the I7C Status register Continue with step 7 If the slave does not acknowledge the Not Acknowledge interrupt occurs NCKI bit is set in the Status register ACK bit is cleared Software responds to the Not Acknowledge interrupt by setting the STOP bit and clearing the TXI bit The I2C Controller sends the STOP condition on the bus and clears the STOP and NCKI bits The transaction is complete ignore the following steps 7 The I C Controller shifts in the byte of data from the PC slave on the SDA signal The IC Controller sends a Not Acknowledge to the PC slave if the NAK bit is set last byte else it sends an Acknowledge 8 The I7C Controller asserts the Receive interrupt RDRF bit set in the Status register
90. be set to 1 it cannot be cleared to 0 and the only method of putting the device back into normal operating mode is to reset the device On Chip Debugger htt p ww xi npi an net LEE EB DRE EL EE EGET ET VE Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification L m ZiLOG DBG lt 04H DBG lt OCDCTL 7 0 Read OCD Control Register 05H The Read OCD Control Register command reads the value of the OCDCTL register DBG lt 05H DBG OCDCTL 7 0 Write Program Counter 06H The Write Program Counter command writes the data that follows to the eZ8 CPU s Program Counter PC If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled the Program Counter PC values are discarded DBG lt 06H DBG lt ProgramCounter 15 8 DBG ProgramCounter 7 0 Read Program Counter 07H The Read Program Counter command reads the value in the eZ8 CPU s Program Counter PC If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled this command returns FFFFH DBG lt 07H DBG ProgramCounter 15 8 DBG ProgramCounter 7 0 Write Register 08H The Write Register command writes data to the Register File Data can be written 1 256 bytes at a time 256 bytes can be written by setting size to zero If the device is not in DEBUG mode the address and data values are discarded If the Read Protect Opt
91. bits of the 12 bit Register File addresses used for storing the ADC output data The ADC Analog Input Number defines the five least significant bits of the Register File address Full 12 bit address is Reserved This bit is reserved and must be 0 DMA ADC Control Register The DMA ADC Control register Table 83 enables and sets options DMA enable and interrupt enable for ADC operation PS019915 1005 htt p ww xi npi an net DMAA_ADDR 7 1 4 bit ADC Analog Input Number 0 Direct Memory Access Controller OOoO0 d Uu LH 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z zZ1iLodG Table 83 DMA_ADC Control Register DMAACTL BITS 7 6 5 4 3 2 1 0 FIELD DAEN IRQEN Reserved ADC IN RESET 0 R W R W ADDR FBEH DAEN DMA ADC Enable 0 DMA ADC is disabled and the ADC Analog Input Number ADC IN is reset to 0 12 DMA ADC is enabled IRQEN Interrupt Enable 0 DMA ADC does not generate any interrupts 1 DMA ADC generates an interrupt after transferring data from the last ADC Analog Input specified by the ADC IN field Reserved These bits are reserved and must be 0 ADC IN ADC Analog Input Number These bits set the number of ADC Analog Inputs to be used in the continuous update data conversion followed by DMA data transfer The conversion always begins with ADC Analog Inpu
92. by setting the START bit at the end of a transaction rather than the STOP bit Note that the Start condition not sent until the START bit is set and data has been written to the C Data register Master Write and Read Transactions The following sections provide a recommended procedure for performing PC write and read transactions from the PC Controller master to slave PC devices In general soft ware should rely on the TDRE RDRF and NCKI bits of the status register these bits gen erate interrupts to initiate software actions When using interrupts or DMA the TXI bit is set to start each transaction and cleared at the end of each transaction to eliminate a trail ing Transmit interrupt Caution should be used in using the ACK status bit within a transaction because it is diffi cult for software to tell when it is updated by hardware When writing data to a slave the PC pauses at the beginning of the Acknowledge cycle if the data register has not been written with the next value to be sent TDRE bit in the PC Status register 1 In this scenario where software is not keeping up with the PC bus TDRE asserted longer than one byte time the Acknowledge clock cycle for byte n is delayed until the Data register is written with byte n 1 and appears to be grouped with the data clock cycles for byte n 1 If either the START or STOP bit is set the PC does not pause prior to the Acknowledge cycle because no additional data is sent When
93. consumption across the full oper ating temperature range of the device and versus the system clock frequency All GPIO pins are configured as outputs and driven High T E kej rI 0 5 10 15 20 System Clock Frequency MHz 3 0V 3 3V 3 6V Figure 46 Maximum HALT Mode Icc Versus System Clock Frequency PS019915 1005 Electrical Characteristics htt p ww xi npi an net COA ee ee DELI 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 217 ZiLOG Figure 47 illustrates the maximum current consumption in STOP mode with the VBO and Watch Dog Timer enabled versus the power supply voltage All GPIO pins are configured as outputs and driven High 700 650 600 550 500 450 STOP Idd microamperes 400 Vdd V 40 105C 0 70C 25C Typical Figure 47 Maximum STOP Mode Idd with VBO enabled versus Power Supply Voltage PS019915 1005 htt p ww xi npi an net ugggmniu IG1U D UU Uu Electrical Characteristics 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 218 ZiLOG Figure 48 illustrates the maximum current consumption in STOP mode with the VBO dis abled and Watch Dog Timer enabled versus the power supply voltage All GPIO pins are configured as outputs and driven High Disab
94. disable the interrupt request sent to the Interrupt Controller the interrupt request must be enabled within the Request Trigger Source block 000 Timer 0 001 Timer 1 010 Timer 2 011 Timer 3 100 DMAO Control register UARTO Received Data register contains valid data DMA1 Control register UARTO Transmit Data register empty Direct Memory Access Controller IG1 D U Od 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Zi ZiLOG 101 DMAO Control register UART1 Received Data register contains valid data DMA 1 Control register UART1 Transmit Data register empty 110 DMAO Control register PC Receiver Interrupt DMA1 Control register PC Trans mitter Interrupt register empty 111 Reserved DMAx I O Address Register The DMAx I O Address register Table 77 contains the low byte of the on chip peripheral address for data transfer The full 12 bit Register File address is given by FH DMAx IO 7 0 When the DMA is configured for two byte word transfers the DMAx I O Address register must contain an even numbered address Table 77 DMAx I O Address Register DMAxIO BITS 7 6 5 4 3 2 1 0 FIELD DMA IO RESET X R W R W ADDR FB1H FB9H DMA IO DMA on chip peripheral control register address This byte sets the low byte of the on chip peripheral control register address on Register File Page FH
95. e The first bit of a 10 bit address shifts out e The first bit of write data shifts out gt Note Writing to the PC Data register always clears the TRDE bit to 0 When TDRE is asserted the I2C Controller pauses at the beginning of the Acknowledge cycle of the byte currently shifting out until the Data register is written with the next value to send or the STOP or START bits are set indicating the current byte is the last one to send The fourth interrupt source is the baud rate generator If the I2C Controller is disabled IEN bit in the I2CCTL register 0 and the BIRQ bit in the I2CCTL register 1 an inter rupt is generated when the baud rate generator counts down to 1 This allows the PC baud rate generator to be used by software as a general purpose timer when IEN 0 Software Control of IC Transactions Software can control IC transactions by using the PC Controller interrupt by polling the PC Status register or by DMA Note that not all products include a DMA Controller To use interrupts the PC interrupt must be enabled in the Interrupt Controller The TXI bit in the C Control register must be set to enable transmit interrupts To control transactions by polling the interrupt bits TDRE RDRF and NCKT in the PC Status register should be polled The TDRE bit asserts regardless of the state of the TXI bit Either or both transmit and receive data movement can be controlled by the DMA Control ler The DMA Controller channel s
96. eZ8 CPU features include e Direct register to register architecture allows each register to function as an accumulator improving execution time and decreasing the required program memory PS019915 1005 Introduction htt p ww xi npi an net o ee ee a og 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z ZiLOG e Software stack allows much greater depth in subroutine calls and interrupts than hardware stacks e Compatible with existing Z8 code e Expanded internal Register File allows access of up to 4KB New instructions improve execution efficiency for code developed using higher level programming languages including C Pipelined instruction fetch and execution e New instructions for improved performance including BIT BSWAP BTJ CPC LDC LDCI LEA MULT and SRL e New instructions support 12 bit linear addressing of the Register File Up to 10 MIPS operation e C Compiler friendly e 2 9 clock cycles per instruction For more information regarding the eZ8 CPU refer to the eZ8 CPU User Manual avail able for download at www zilog com General Purpose I O The 64K Series features seven 8 bit ports Ports A G and one 4 bit port Port H for gen eral purpose I O GPIO Each pin is individually programmable All ports except B and H support 5V tolerant inputs Flash Controller The Flash Controller programs and eras
97. following Select loop or single pass mode operation Select the data transfer direction either from the Register File RAM to the on chip peripheral control register or from the on chip peripheral control register to the Register File RAM Enable the DMAx interrupt request if desired Select Word or Byte mode Select the DMAx request trigger Enable the DMAx channel DMA ADC Operation DMA ADC transfers data from the ADC to the Register File The sequence of operations in a DMA_ ADC data transfer is 1 PS019915 1005 htt p ww xi npi an net EE ADC completes conversion on the current ADC input channel and signals the DMA controller that two bytes of ADC data are ready for transfer DMA_ADC requests control of the system bus address and data from the eZ8 CPU After the eZ8 CPU acknowledges the bus request DMA_ADC transfers the two byte ADC output value to the Register File and then returns system bus control back to the eZ8 CPU If the current ADC Analog Input is the highest numbered input to be converted DMA ADC resets the ADC Analog Input number to 0 and initiates data conversion on ADC Analog Input 0 If configured to generate an interrupt DMA_ADC sends an interrupt request to the Interrupt Controller Direct Memory Access Controller HHHHEHIGHHBBHBHH 010 62245566 13810019655 162 Z8 Encore 64K Series Product Specification 163 Z
98. function Provides some protection against accidental Port reconfiguration 01H Data Direction 02H Alternate Function 03H Output Control Open Drain 04H High Drive Enable 05H STOP Mode Recovery Source Enable 06H FFH No function Port A H Control Registers The Port A H Control registers set the GPIO port operation The value in the correspond ing Port A H Address register determines the control sub registers accessible using the Port A H Control register Table 15 Table 15 Port A H Control Registers PxCTL BITS 7 6 5 4 2 1 0 FIELD PCTL RESET 00H R W R W ADDR FD1H FD5H FD9H FDDH FE1H FESH FE9H FEDH PCTL 7 0 Port Control The Port Control register provides access to all sub registers that configure the GPIO Port operation PS019915 1005 General Purpose I O htt p ww xi npi an net OTe PSEP ELE T Ooo 010 62245566 13810019655 Port A H Data Direction Sub Registers Z8 Encore 64K Series Product Specification 57 ZiLOG The Port A H Data Direction sub register is accessed through the Port A H Control regis ter by writing 01H to the Port A H Address register Table 16 Table 16 Port A H Data Direction Sub Registers BITS 7 6 5 4 3 2 1 0 FIELD DD7 DD6 DD5 DD4 DD3 DD2 DDI DDO RESET l R W R W ADDR If 01H in Port A H Address Register accessible through Port A H Control Register DD 7 0 Data Direction These
99. inputs GPIO Port Availability By Device Table 11 lists the port pins available with each device and package type Table 11 Port Availability by Device and Package Type Device Packages PortA PortB PortC PortD PortE PortF PortG PortH Z8X1621 40 pin 7 0 7 0 6 0 6 3 1 0 Z8X1621 44 pin 7 0 7 0 7 0 6 0 z Z8X1622 64 and 68 pin 7 0 7 0 7 0 7 0 7 0 7 3 3 0 Z8X2421 40 pin 7 0 7 0 6 0 6 3 1 0 Z8X2421 44 pin 7 0 7 0 7 0 6 0 2 2 Z8X2422 64 and 68 pin 7 0 7 0 7 0 7 0 7 0 7 3 3 0 Z8X3221 40 pin 7 0 7 0 6 0 6 3 1 0 Z8X322 44 pin 7 0 7 0 7 0 6 0 R Z8X3222 64 and 68 pin 7 0 7 0 7 0 7 0 7 0 7 3 3 0 Z8X4821 40 pin 7 0 7 0 6 0 6 3 1 0 Z8X4821 44 pin 7 0 7 0 7 0 6 0 r 2 P Z8X4822 64 and 68 pin 7 0 7 0 7 0 7 0 7 0 7 3 3 0 Z8X4823 80 pin 7 0 7 0 7 0 7 0 7 0 7 0 7 0 3 0 PS019915 1005 General Purpose I O htt p ww xi npi an net KATE TOTEH eo oo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification VAF ZiLOG Table 11 Port Availability by Device and Package Type Continued Device Packages PortA PortB PortC PortD PortE PortF PortG PortH Z8X6421 40 pin 7 0 7 0 6 0 6 3 1 0 Z8X6421 44 pin 7 0 7 0 7 0 6 0
100. interface 194 serial errors 197 status register 204 timing 227 OCD commands execute instruction 12H 202 read data memory 0DH 201 read OCD control register 05H 200 read OCD revision 00H 199 read OCD status register 02H 199 read program counter 07H 200 read program memory 0BH 201 read program memory CRC OEH 201 read register 09H 200 step instruction 10H 202 stuff instruction 11H 202 write data memory 0CH 201 write OCD control register 04H 199 write program counter 06H 200 write program memory 0AH 200 write register 08H 200 on chip debugger 5 on chip debugger OCD 193 on chip debugger signals 15 on chip oscillator 205 one shot mode 89 opcode map Index htt p ww xi npi an net DEL EY EC BRE UE FER DL ED ERE E EL EH 010 62245566 13810019655 abbreviations 254 cell description 253 first 255 second after FH 256 Operational Description 98 OR 241 ordering information 262 ORX 241 oscillator signals 14 P p 235 packaging LQFP 44 lead 258 64 lead 259 PDIP 257 PLCC 44 lead 259 68 lead 260 QFP 261 part number description 267 part selection guide 2 PC 236 PDIP 257 peripheral AC and DC electrical characteristics 219 PHASE 0 timing SPI 129 PHASE 1 timing SPD 130 pin characteristics 16 PLCC 44 lead 259 68 lead 260 polarity 235 POP 240 pop using extended addressing 240 POPX 240 port availability device 51 port input timing GPIO 225 port output tim
101. interrupt after character transmis sion reception completes in both master and slave modes A character can be defined to be PS019915 1005 Serial Peripheral Interface htt p ww xi npi an net DOT 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 132 ZiLOG 1 through 8 bits by the NUMBITS field in the SPI Mode register In slave mode it is not necessary for SS to deassert between characters to generate the interrupt The SPI in Slave mode can also generate an interrupt if the SS signal deasserts prior to transfer of all the bits in a character see description of slave abort error above Writing a 1 to the IRQ bit in the SPI Status Register clears the pending SPI interrupt request The IRQ bit must be cleared to 0 by the Interrupt Service Routine to generate future interrupts To start the transfer pro cess an SPI interrupt may be forced by software writing a 1 to the STR bit in the SPICTL register If the SPI is disabled an SPI interrupt can be generated by a Baud Rate Generator time out This timer function must be enabled by setting the BIRQ bit in the SPICTL register This Baud Rate Generator time out does not set the IRQ bit in the SPISTAT register just the SPI interrupt bit in the interrupt controller SPI Baud Rate Generator In SPI Master mode the Baud Rate Generator creates a lower frequency serial clock SCK for data transmission synchronization between the Mast
102. is completely received to avoid an overrun error Note that in multiprocessor mode MPEN 1 the receive data interrupts are dependent on the multiprocessor configuration and the most recent address byte e A break is received e Anoverrun is detected e A data framing error is detected UART Overrun Errors When an overrun error condition occurs the UART prevents overwriting of the valid data currently in the Receive Data register The Break Detect and Overrun status bits are not displayed until after the valid data has been read After the valid data has been read the UART Status 0 register is updated to indicate the overrun condition and Break Detect if applicable The RDA bit is set to 1 to indicate that the Receive Data register contains a data byte However because the overrun error occurred this byte may not contain valid data and should be ignored The BRKD bit indi cates if the overrun was caused by a break condition on the line After reading the status byte indicating an overrun error the Receive Data register must be read again to clear the error bits is the UART Status 0 register Updates to the Receive Data register occur only when the next data word is received UART Data and Error Handling Procedure Figure 18 illustrates the recommended procedure for use in UART receiver interrupt ser vice routines PS019915 1005 UART HHHEHEHIGBUHBBHBHH 010 62245566 13810019655 htt p ww xi npi an net
103. nn 1 Features esee he eta PAG o Bobo CUR Rab too hdow dhe pr PRA eR qos 1 Part Selection Guide se Sahin Ver SG Shieh ea ae Maes 2 Block Di gram oo oec sensns beca REL RE Ree bey Ra cede be ee e 3 CPU and Peripheral Overview 0 cece cece eh 3 EZS CPU Features x uer due cre tae eae Op ege oboe e eos bee unen uad 3 General Purpose VO i i sciret ree ee leew ae AER RU ERR e og ER 4 Flash Controller i e mee tane ahate RR dds Gobind UR ep d ege ds 4 10 Bit Analog to Digital Converter leeeeeeeee eee 4 WARTS 2 epe d ener ERES REDE VR EAR da eR e RE 4 PO P 5 Serial Peripheral Interface 0 0 cee eens 3 l ng RE TT TMTT 5 Interrupt Controller rede ves arce d a e na ae 5 Reset Controllet 21 eee yer es uen ob ROS xU RR gc d NU ede de 5 On Chip Debugger oi cave ee Re o de oe E T n Rcs RE dna 5 DMA Controller ssri cs lee even esed edalasd ae Qa ua Ra eee ea 5 Signal and Pin Descriptions cece cece cece cece cece teen cece rnt 6 OVEIVIEW a4 6 dak nek ie iad nde Gh a we le edu ee a peed a alee Ce des 6 Available Packages 0 2 0 cence ene en ee bee nh eh bebe betes 6 Pin Contig ratlons sesser clus phe ee bue ee geb uc ee ee ee 7 Signal Descriptions 2 2 set dee veto dede eq a oa Waa 13 Pin CharacteriSucs uus et e geo E on ge RM d n e Ra d 16 Address Space serae nn tree Sn teaser P e Rien Rack alum Ronchi SPON e sae 17 OVetVIeW oss a URN seas IRA SUE ERRARE Na FCR
104. out and the 64K Series devices are configured to respond to interrupts the eZ8 CPU ser vices the Watch Dog Timer interrupt request following the normal STOP Mode Recovery sequence STOP Mode Recovery Using a GPIO Port Pin Transition HALT Each of the GPIO Port pins may be configured as a STOP Mode Recovery input source On any GPIO pin enabled as a STOP Mode Recovery source a change in the input pin value from High to Low or from Low to High initiates STOP Mode Recovery The GPIO STOP Mode Recovery signals are filtered to reject pulses less than 10ns typical in dura tion In the Watch Dog Timer Control register the STOP bit is set to 1 AN Caution In STOP mode the GPIO Port Input Data registers PxIN are disabled The Port Input Data registers record the Port transition only if the signal stays on the Port pin through the end of the STOP Mode Recovery delay Thus short pulses on the Port pin can initiate STOP Mode Recovery with out being written to the Port Input Data register or without initiating an in terrupt if enabled for that pin PS019915 1005 Reset and STOP Mode Recovery htt p ww xi npi an net uggamBpmmuagdrqiudtut Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 49 ZiLOG Low Power Modes Overview The 64K Series products contain power saving features The highest level of power reduc tion is provided by STOP mode The next level o
105. pass in COUNTER mode After the first timer Reload in COUNTER mode counting always begins at the reset value of 0001H Generally in COUNTER mode the Timer High and Low Byte registers must be written with the value 0001H 3 Write to the Timer Reload High and Low Byte registers to set the Reload value 4 If desired enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers 5 Configure the associated GPIO port pin for the Timer Input alternate function 6 Ifusing the Timer Output function configure the associated GPIO port pin for the Timer Output alternate function 7 Write to the Timer Control 1 register to enable the timer In COUNTER mode the number of Timer Input transitions since the timer start is given by the following equation Counter Mode Timer Input Transitions Current Count Value Z Start Value PWM Mode In PWM mode the timer outputs a Pulse Width Modulator PWM output signal through a GPIO Port pin The timer input is the system clock The timer first counts up to the 16 bit PWM match value stored in the Timer PWM High and Low Byte registers When the timer count value matches the PWM value the Timer Output toggles The timer continues counting until it reaches the Reload value stored in the Timer Reload High and Low Byte registers Upon reaching the Reload value the timer generates an interrupt the count value in the Timer High and Low Byte registers is re
106. point within the program where the START label occurs LD R4 R7 A Load LD instruction with two operands The first operand Working Register R4 is the destination The second operand Working Register R7 is the source The contents of R7 is written into R4 LD 234H 01 Another Load LD instruction with two operands The first operand Extended Mode Register Address 2344 identifies the destination The second operand Immediate Data PS019915 1005 eZ8 CPU Instruction Set htt p ww xi npi an net DOT 010 62245566 13810019655 Z8 Encore 64K Series Product Specification L z ZiLOG value 01H is the source The value 01H is written into the Register at address 234H Assembly Language Syntax For proper instruction execution eZ8 CPU assembly language syntax requires that the operands be written as destination source After assembly the object code usually has the operands in the order source destination but ordering is opcode dependent The fol lowing instruction examples illustrate the format of some basic assembly instructions and the resulting object code produced by the assembler This binary format must be followed by users that prefer manual program coding or intend to implement their own assembler Example 1 If the contents of Registers 43H and 08H are added and the result is stored in 43H the assembly syntax and resulting object code is As
107. protected and cannot be programmed or erased from user code Flash Frequency High Byte FFREQH FFAH Read Write D7 D6 D5 D4ID3 D2IDI DO Flash Frequency value 15 8 Flash Frequency Low Byte FFREQL FFBH Read Write D7 D6 D5 D4ID3 D2 D1 DO Flash Frequency value 7 0 PS019915 1005 Flags Z8 Encore 64K Series Z8 Encore 42 ZiLOG FLAGS FFC Read Write D7 D6 D5 D4 D3 D2 D1 D0 L F1 User Flag 1 L F2 User Flag 2 L H Half Carry D Decimal Adjust V Overflow Flag S Sign Flag Z Zero Flag C Carry Flag Register Pointer RP FFDH Read Write D7 D6 D5 D4 D3 D2 D1 D0 ____ Working Register Page Address 11 8 Working Register Group Address 7 4 Stack Pointer High Byte SPH FFEH Read Write D7 D6 D5 D4 D3 D2 DI DO Stack Pointer 15 8 Stack Pointer Low Byte SPL FFFH Read Write D7 D6 D5 D4 D3 D2 D1 D0 Stack Pointer 7 0 Control Register Summary htt p ww xi npi an net DEL EY EC BRE UE IG1U D UU 010 62245566 13810019655 Uu Z8 Encore 64K Series Product Specification 43 ZiLOG Reset and STOP Mode Recovery Overview The Reset Controller wit
108. pulse kee IR TXD yp Clock delay Figure 20 Infrared Data Transmission Receiving IrDA Data Data received from the infrared transceiver via the IR_RXD signal through the RXD pin is decoded by the Infrared Endec and passed to the UART The UART s baud rate clock is used by the Infrared Endec to generate the demodulated signal RXD that drives the UART Each UART Infrared data bit is 16 clocks wide Figure 21 illustrates data recep tion When the Infrared Endec is enabled the UART s RXD signal is internal to the 64K Series products while the IR RXD signal is received through the RXD pin PS019915 1005 Infrared Encoder Decoder htt p ww xi npi an net o ee ee a og 010 62245566 13810019655 Z8 Encore 64K Series Product Specification L ZiLOG 16 clock period gt Banas ll Start Bit 0 Data Bit 0 1 Data Bit 1 0 Data Bit 2 1 Data Bit 3 1 IR RXD min 1 6us 7 pulse UART s RXD Start Bit 0 Data Bit 0 1 Data Bit 1 0 Data Bit 2 1 Data Bit 3 1 8 clock CL delay 16 clock 16 clock 16 clock 16 clock lt period gt r period gt r period gt r period gt Figure 21 Infrared Data Reception A N Caution The system clock frequency must be at least 1 0MHz to ensure proper re ception
109. purpose I O ports Interrupt upon conversion complete Internal voltage reference generator Direct Memory Access DMA controller can automatically initiate data conversion and transfer of the data from to 12 of the analog inputs Figure 34 illustrates the three major functional blocks converter analog multiplexer and voltage reference generator of the ADC The ADC converts an analog input signal to its digital representation The 12 input analog multiplexer selects one of the 12 analog input sources The ADC requires an input reference voltage for the conversion The voltage ref erence for the conversion may be input through the external VREF pin or generated inter nally by the voltage reference generator PS019915 1005 Analog to Digital Converter htt p ww xi npi an net ugagamBpmmuagdisqiaudtt Ooo 010 62245566 13810019655 Internal Voltage Reference Generator Analog to Digital Converter Z8 Encore 64K Series Product Specification L ZiLOG VREF Reference Input Analog Input Multiplexer ANAO ANA1 ANA2 ANA3 ANA4 ANA5 ANA6 ANA7 ANA8 Analog Input ANA9 ANA10 ANA11 ANAIN 3 0 Figure 34 Analog to Digital Converter Block Diagram The sigma delta ADC architecture provides alias and image attenuation below the ampli tude resolution of the ADC in the frequency range of DC to one half th
110. r2 2 4 TCM rira 3 3 TCM R2 R 3 4 TCM IR2 R 3 3 TCM R1 IM 3 4 TCM R1 IM 4 3 TCMX ER2 ER 43 TCMX M ER 2 3 TM ri 2 2 4 r1 lr2 3 3 TM R2 R 3 4 TM IR2 R 3 3 TM R1 IM 3 4 TM R1 IM 4 3 TMX ER2 ER 4 3 TMX M ER 2 5 LDE r1 lrr2 2 9 LDEI Ir1 Irr2 3 2 LDX r1 ER2 3 8 LDX Irt ER2 3 4 LDX IRR2 R1 3 5 LDX IRR2 IR1 3 4 LDX r1 rr2 X 3 4 LDX rr1 r2 X Upper Nibble Hex 25 LDE r2 lrr1 2 9 LDEI Ir2 lrri 3 2 LDX r2 ER1 3 3 LDX Ir2 ER1 3 4 LDX R2 IRR1 3 5 LDX IR2 IRR1 3 3 LEA r1 r2 X 3 5 LEA rr1 rr2 X 2 8 CP ri 2 2 4 CP r1 lr2 3 3 CP R2 R1 3 4 CP IR2 R1 3 3 CP R1 M 3 4 CP IR1 IM 4 8 CPX ER2 ER1 4 3 CPX IM ER1 2 3 XOR ri 2 2 4 XOR r1 lr2 3 3 XOR R2 R1 34 XOR IR2 R1 3 3 XOR R1 IM 3 4 XOR IR1 IM 4 3 XORX ER2 ER1 43 XORX IM ER1 2 5 LDC r1 lrr2 2 9 LDCI Ir1 lrr2 2 3 JP IRR1 2 9 LDC Ir1 Irr2 3 4 LD r1 r2 X 3 2 PUSHX ER2 2 5 LDC r2 lrr1 2 9 LDCI Ir2 lrri 2 6 CALL IRR1 2 2 BSWAP R1 3 3 CALL DA 3 4 LD r2 r1 X 3 2 POPX ER1 2 2 BIT p b r1 2 3 LD r1 lr2 3 2 LD R2 R1 3 3 LD IR2 R1 3 2 LD 3 3 LD IR1 IM 4 2 LDX ER2 ER1 2 6 TRAP Vector 2 3 LD Ir1 r2 Figure 60 First Opcode Ma
111. rates from 9600 baud to 115 2 Kbaud Higher baud rates are possible but do not meet IrDA specifications The UART must be enabled to use the Infrared Endec The Infrared Endec data rate is calculated using the following equation R _ System Clock Frequency Hz Infrared Data Rate bils s 7 TART Baud Rate Divisor Value Transmitting IrDA Data The data to be transmitted using the infrared transceiver is first sent to the UART The UART s transmit signal TXD and baud rate clock are used by the IrDA to generate the modulation signal IR_TXD that drives the infrared transceiver Each UART Infrared data bit is 16 clocks wide If the data to be transmitted is 1 the IR_TXD signal remains low for the full 16 clock period If the data to be transmitted is 0 a 3 clock high pulse is output following a 7 clock low period After the 3 clock high pulse a 6 clock low pulse is output to complete the full 16 clock data period Figure 20 illustrates IrDA data transmis sion When the Infrared Endec is enabled the UART s TXD signal is internal to the 64K Series products while the IR_TXD signal is output through the TXD pin PS019915 1005 Infrared Encoder Decoder htt p ww xi npi an net DOT 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 122 ZiLOG 16 clock F period gt ll gei Start Bit 0 Data Bit 0 1 Data Bit 1 0 Data Bit 2 1 Data Bit 3 1 3 clock
112. right 242 rotate right through carry 242 RP 236 RR 235 242 rr 235 RRC 242 S SBC 239 SCF 239 240 SCK 127 SDA and SCL IrDA signals 141 second opcode map after 1FH 256 serial clock 127 serial peripheral interface SPI 125 set carry flag 239 240 set register pointer 240 shift right arithmetic 242 shift right logical 242 signal descriptions 13 single shot conversion ADC 173 SIO 5 slave data transfer formats 12C 147 slave select 128 software trap 241 source operand 236 SP 236 SPI Index htt p ww xi npi an net DEL EY EC BRE UE IMOO000000 010 62245566 13810019655 architecture 125 baud rate generator 132 baud rate high and low byte register 138 clock phase 128 configured as slave 126 control register 133 control register definitions 133 data register 133 error detection 131 interrupts 131 mode fault error 131 mode register 136 multi master operation 130 operation 126 overrun error 131 signals 127 single master multiple slave system 126 single master single slave system 125 status register 135 timing PHASE 0 129 timing PHASE 1 130 SPI controller signals 13 SPI mode SPIMODE 136 SPIBRH register 138 SPIBRL register 138 SPICTL register 134 SPIDATA register 133 SPIMODE register 136 SPISTAT register 135 SRA 242 src 236 SRL 242 SRP 240 SS SPI signal 127 stack pointer 236 status register I2C 153 STOP 240 STOP mode 49 240 STOP mode recovery sources 47 usi
113. the START or STOP bit is set The Not Acknowledge event sets the NCKI bit of the PC Status register and can only be cleared by setting the START or STOP bit in the PC Control register When this interrupt occurs the PC Controller waits until either the STOP or START bit is set before performing any action In an interrupt service routine the NCKI bit should always be checked prior to ser vicing transmit or receive interrupt conditions because it indicates the transaction is being terminated Receive interrupts occur when a byte of data has been received by the PC Controller master reading data from slave This procedure sets the RDRF bit of the PC Status regis ter The RDRF bit is cleared by reading the PC Data register The RDRF bit is set during the acknowledge phase The PC Controller pauses after the acknowledge phase until the receive interrupt is cleared before performing any other action PS019915 1005 I2C Controller htt p ww xi npi an net COA ee ee DELI 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Zi ZiLOoG Transmit interrupts occur when the TDRE bit of the PC Status register sets and the TXI bit in the C Control register is set Transmit interrupts occur under the following condi tions when the transmit data register is empty The I C Controller is enabled The first bit of the byte of an address is shifting out and the RD bit of the PC Status register is deasserted
114. the Watch Dog Timer Control register WDTCTL Write the Watch Dog Timer Reload Upper Byte register WDTU Write the Watch Dog Timer Reload High Byte register WDTH Uh deo te d oF Write the Watch Dog Timer Reload Low Byte register WDTL All steps of the Watch Dog Timer Reload Unlock sequence must be written in the order just listed There must be no other register writes between each of these operations If a register write occurs the lock state machine resets and no further writes can occur unless the sequence is restarted The value in the Watch Dog Timer Reload registers is loaded into the counter when the Watch Dog Timer is first enabled and every time a WDT instruction is executed Watch Dog Timer Control Register Definitions Watch Dog Timer Control Register The Watch Dog Timer Control WDTCTL register detailed in Table 47 is a Read Only register that indicates the source of the most recent Reset event indicates a STOP Mode Recovery event and indicates a Watch Dog Timer time out Reading this register resets the upper four bits to 0 Writing the 55H AAH unlock sequence to the Watch Dog Timer Control WDTCTL reg ister address unlocks the three Watch Dog Timer Reload Byte registers WDTU WDTH and WDTL to allow changes to the time out period These write operations to the WDTCTL register address produce no effect on the bits in the WDTCTL register The locking mechanism prevents spurious writes to the Reload registers
115. timers described in this chapter the Baud Rate Generators for any unused UART SPI or IPC peripherals may also be used to provide basic timing function ality Refer to the respective serial communication peripheral chapters for information on using the Baud Rate Generators as timers Timer 3 is unavailable in the 44 pin package devices Architecture Figure 12 illustrates the architecture of the timers PS019915 1005 htt p ww xi npi an net EE Timers HHHEHEHIGBUHBBHBHH 010 62245566 13810019655 Z8 Encore 64K Series Product Specification L r ZiLOG Po ee a nuce Pec E ee Timer Block Data l Timer Bus i a Control l l Block Control 16 Bit Interrupt Timer Reload Register PWM Interrupt and Timer Output System p Timer Control Outout Clock 16 Bit Counter p Timer with Prescaler m Input Gate 16 Bit l Input l M PWM Compare apture l Input rrr A Figure 12 Timer Block Diagram Operation The timers are 16 bit up counters Minimum time out delay is set by loading the value 0001H into the Timer Reload High and Low Byte registers and setting the prescale value to 1 Maximum time out delay is set by loading the value 0000H into the Timer Reload High and Low Byte registers and setting the prescale value to 128 If the Timer reaches FFFFH the timer rolls over to 0000H and continues counting Timer
116. transmitter and the receiver In addition when the UART primary functionality is disabled the Baud Rate Generator can also func tion as a basic timer with interrupt capability Transmitter Interrupts The transmitter generates a single interrupt when the Transmit Data Register Empty bit TDRE is set to 1 This indicates that the transmitter is ready to accept new data for trans mission The TDRE interrupt occurs after the Transmit shift register has shifted the first bit of data out At this point the Transmit Data register may be written with the next character to send This provides 7 bit periods of latency to load the Transmit Data register before the Transmit shift register completes shifting the current character Writing to the UART Transmit Data register clears the TDRE bit to 0 PS019915 1005 UART HHHEHEHIGBUHBBHBHH 010 62245566 13810019655 htt p ww xi npi an net EE Z8 Encore 64K Series Product Specification 107 ZiLOG Receiver Interrupts The receiver generates an interrupt when any of the following occurs e A data byte has been received and is available in the UART Receive Data register This interrupt can be disabled independent of the other receiver interrupt sources The received data interrupt occurs once the receive character has been received and placed in the Receive Data register Software must respond to this received data available condition before the next character
117. twice before an erase occurs The proper steps to program the Flash from user code are Write 00H to the Flash Control register to reset the Flash Controller Write the page of memory to be programmed to the Page Select register Write the first unlock command 73H to the Flash Control register Write the second unlock command 8CH to the Flash Control register Re write the page written in step 2 to the Page Select register Write Flash Memory using LDC or LDCI instructions to program the Flash Repeat step 6 to program additional memory locations on the same page 9o c xo 5A deo oN ES Write 00H to the Flash Control register to lock the Flash Controller Page Erase The Flash memory can be erased one page 512 bytes at a time Page Erasing the Flash memory sets all bytes in that page to the value FFH The Page Select register identifies the page to be erased While the Flash Controller executes the Page Erase operation the eZ8 CPU idles but the system clock and on chip peripherals continue to operate The eZ8 CPU resumes operation after the Page Erase operation completes Interrupts that occur when the Page Erase operation is in progress are serviced once the Page Erase operation is com plete When the Page Erase operation is complete the Flash Controller returns to its locked state Only pages located in unprotected sectors can be erased The proper steps to perform a Page Erase operation are 1 Write 00H to the Flash Control regi
118. 0 Divide by 1 001 Divide by 2 010 Divide by 4 Timer 3 Control 0 011 Divide by 8 T3CTLO FIEH Read Write 100 Divide by 16 101 Divide by 32 D7 D6 D5 D4D3D2D1 DO 110 Divide by 64 111 Divide by 128 Timer Input Output Polarity Operation of this bit is a function of Reserved Cascade Timer 0 Timer 3 Input signal is GPIO pin 1 Timer 3 Input signal is Timer 2 out the current operating mode of the timer Reserved Timer Enable 0 Timer is disabled 1 Timer is enabled Timer 3 Control 1 T3CTLI1 FIFH Read Write x D7 D6 D5 DA D3D2 DI DO Timer 3 High Byte T3H FI8H Read Write PET R D7 D6 D5 D4 D3 D2 D1 DO 000 One Shot mode 001 CONTINUOUS mode Timer 3 current count value 15 8 010 COUNTER mode 011 PWM mode 100 CAPTURE mode 101 COMPARE mode Timer 3 Low Byte 110 GATED mode T3L FI9H Read Write 111 Capture COMPARE mode D7 D6 D5 DAD3 D2DI DO L Prescale Value 000 Divide by 1 ___________ Timer 3 current count value 7 0 001 Divide by 2 010 Divide by 4 011 Divide by 8 100 Divide by 16 Timer 3 Reload High Byte 101 Divide by 32 T3RH F1AH Read Write ur by s D7 D6 D5 D4 D3 D2 D1 DO i x Timer Input Output Polarity Timer
119. 0 60 576 0 60 0 00 0 30 2083 0 30 0 2 0 30 1152 0 30 0 00 3 579545 MHz System Clock 1 8432 MHz System Clock Desired Rate BRG Divisor Actual Rate Error Desired Rate BRG Divisor Actual Rate Error kHz Decimal kHz 9c kHz Decimal kHz 1250 0 N A N A N A 1250 0 N A N A N A 625 0 N A N A N A 625 0 N A N A N A 250 0 1 223 72 10 51 250 0 N A N A N A 115 2 2 111 9 2 90 115 2 1 115 2 0 00 57 6 4 55 9 2 90 57 6 2 57 6 0 00 38 4 6 37 3 2 90 38 4 3 38 4 0 00 19 2 12 18 6 2 90 19 2 6 19 2 0 00 9 60 23 9 73 1 32 9 60 12 9 60 0 00 4 80 47 4 76 0 83 4 80 24 4 80 0 00 2 40 93 241 0 23 2 40 48 2 40 0 00 1 20 186 1 20 0 23 1 20 96 1 20 0 00 PS019915 1005 UART htt p ww xi npi an net o HANANI ELE T Ooo 010 62245566 13810019655 Table 60 UART Baud Rates Continued Z8 Encore 64K Series Product Specification Zi ZiLOG 0 60 373 0 60 0 04 0 60 192 0 60 0 00 0 30 746 0 30 0 04 0 30 384 0 30 0 00 PS019915 1005 UART htt p ww xi npi an net ut CO FSEPET EU og 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 120 ZiLOG Infrared Encoder Decoder Overview The 64K Series products contain two fully functional high performance UART to Infra red Encoder Decoders Endecs Each Infrared Endec is integrated with an on chip UART to allow easy communication between the 64K Series
120. 0 MHz P 9 Vpp 3 3 V Ippg Halt Mode Supply Current 4 7 mA Vpp 3 6 V Fsysclk 20 MHz See Figures 45 and 46 5 Vpp233 V RUM ai eonneureias E 3 5 mA Vpp 3 6 V Fsysclk 10 MHz p 4 Vpp 3 3 V Ipps Stop Mode Supply Current 520 700 uA Vpp 3 6 V VBO and WDT See Figures 47 and 48 Enabled GPIO pins configured as 650 Vpp 3 3 V i ia 10 25 uA Vpp 3 6 V TA 0 to 70 VBO Disabled WDT Enabled 20 Vpp 3 3 V 80 HA Vpp 3 6 V TA 40 to 105 VBO Disabled WDT Enabled 70 Vpp 3 3 V 250 BA Vpp 3 6 V TA 2 40 to 4125 VBO Disabled WDT Enabled 150 Vpp 3 3 V This condition excludes all pins that have on chip pull ups when driven Low These values are provided for design guidance only and are not tested in production PS019915 1005 htt p ww xi npi an net o LH BHEEH H IG1U D UU UU Electrical Characteristics 010 62245566 13810019655 212 Z8 Encore 64K Series Product Specification Zi ZiLOG Figure 43 illustrates the typical active mode current consumption while operating at 25 C versus the system clock frequency All GPIO pins are configured as outputs and driven High Idd mA 0 5 10 15 20 System Clock Frequency MHz 3 0V 3 3V 3 6V Figure 43 Typical Active Mode Idd Versus System Clock Frequency PS019915 1005 Electrical Characteristics FER DL Ta a EH
121. 00 Idle State 0_0001 START State 0_0010 Send Receive data bit 7 0_0011 Send Receive data bit 6 0_0100 Send Receive data bit 5 0_0101 Send Receive data bit 4 0_0110 Send Receive data bit 3 0_0111 Send Receive data bit 2 0_1000 Send Receive data bit 1 0_1001 Send Receive data bit 0 0_1010 Data Acknowledge State 0_1011 Second half of data Acknowledge State used only for not acknowledge 0_1100 First part of STOP state 0_1101 Second part of STOP state 0_1110 10 bit addressing Acknowledge State for 2nd address byte 7 bit addressing Address Acknowledge State PS019915 1005 12C Controller htt p ww xi npi an net ugugmgmgmuadrqiudt Ooo 010 62245566 13810019655 TXRXSTATE 0 1111 1 0000 1 0001 1 0010 1 0011 1 0100 1 0101 1 0110 1 0111 1 1000 1 1001 1 1010 1011 1 1100 1 1101 1 1110 1_1111 PS019915 1005 htt p ww xi npi an net Z8 Encore 64K Series Product Specification Z 159 ZiLOoG State Description 10 bit address Bit 0 Least significant bit of 2nd address byte 7 bit address Bit O Least significant bit R W of address byte 10 bit addressing Bit 7 Most significant bit of 1st address byte 10 bit addressing Bit 6 of 1st address byte 10 bit addressing Bit 5 of 1st address byte 10 bit addressing Bit 4 of 1st address byte 10 bit addressing Bit 3 of 1st address byte 10 bit addressing Bit 2 of 1st address byte 10 bit address
122. 010 62245566 13810019655 htt p ww xi npi an net DEL EY EC BRE UE Z8 Encore 64K Series Product Specification Z4 ZiLOG Figure 44 illustrates the maximum active mode current consumption across the full oper ating temperature range of the device and versus the system clock frequency All GPIO pins are configured as outputs and driven High Idd mA 10 15 20 0 5 System Clock Frequency MHz gy 33V 3 6V Figure 44 Maximum Active Mode Idd Versus System Clock Frequency PS019915 1005 Electrical Characteristics FER DL ED ERE E O EH 010 62245566 13810019655 htt p ww xi npi an net DEL EY EC BRE UE Z8 Encore 64K Series Product Specification L zs ZiLOG Figure 45 illustrates the typical current consumption in HALT mode while operating at 25 C versus the system clock frequency All GPIO pins are configured as outputs and driven High HALT Idd mA 0 5 10 15 20 System Clock Frequency MHz OV 3 3V 3 6V Figure 45 Typical HALT Mode Idd Versus System Clock Frequency PS019915 1005 Electrical Characteristics FER DL ED ERE E O EH 010 62245566 13810019655 htt p ww xi npi an net IUE ET ELE EET Z8 Encore 64K Series Product Specification 216 ZiLOG Figure 45 illustrates the maximum HALT mode current
123. 019655 Z8 Encore 64K Series Product Specification VAF ZiLOG Table 6 Z8 Encore 64K Series Information Area Map Program Memory Address Hex Function FEOOH FE3FH Reserved FE40H FE53H Part Number 20 character ASCII alphanumeric code Left justified and filled with zeros ASCII Null character FE54H FFFFH Reserved PS019915 1005 Address Space htt p ww xi npi an net ugmumgmngumnuigdiBui Ooo 010 62245566 13810019655 Register File Address Map Table 7 64K Series Register File Address Map Z8 Encore 64K Series Product Specification ZiLOG Table 7 provides the address map for the Register File of the 64K Series products Not all devices and package styles in the 64K Series support Timer 3 and all of the GPIO Ports Consider registers for unimplemented peripherals as Reserved Address Hex Register Description Mnemonic Reset Hex Page General Purpose RAM 000 EFF General Purpose Register File RAM XX Timer 0 F00 Timer 0 High Byte TOH 00 84 F01 Timer 0 Low Byte TOL 01 84 F02 Timer 0 Reload High Byte TORH FF 85 F03 Timer 0 Reload Low Byte TORL FF 85 F04 Timer 0 PWM High Byte TOPWMH 00 87 F05 Timer 0 PWM Low Byte TOPWML 00 87 F06 Timer 0 Control 0 TOCTLO 00 88 F07 Timer 0 Control 1 TOCTLI 00 88 Timer 1 F08 Timer 1 High Byte T1H 00 84 F09 Tim
124. 0MHz Typo Voltage Brown Out Pulse E 10 HS Vpp lt Vypo to generate a Rejection Period Reset Tramp Time for VDD to transition 0 10 100 ms from Vgs to Vpop to ensure valid Reset 1 Data in the typical column is from characterization at 3 3V and 0 C These values are provided for design guidance only and are not tested in production PS019915 1005 Electrical Characteristics htt p ww xi npi an net utu ee ee EU og 010 62245566 13810019655 Table 107 External RC Oscillator Electrical Characteristics and Timing Z8 Encore 64K Series Product Specification L z ZiLOG T4 40 C to 125 C Symbol Parameter Minimum Typical Maximum Units Conditions VDD Operating Voltage Range 2 70 V Rexy External Resistance from 40 45 200 kO Vpp Vypo XIN to VDD Cpxpy External Capacitance from 0 20 1000 pF XIN to VSS Fosc External RC Oscillation 4 MHz Frequency 1 When using the external RC oscillator mode the oscillator may stop oscillating if the power supply drops below 2 7V but before the power supply drops to the voltage brown out threshold The oscillator will resume oscillation as soon as the supply voltage exceeds 2 7V Table 108 Reset and STOP Mode Recovery Pin Timing T4 40 C to 125 C Symbol Parameter Minimum Typical Maximum Units Conditions
125. 1 DO Port C Pin IRQ Enable Low Bit L DMA IRQ Enable Low Bit UART 1 Transmitter IRQ Enable Low UART I Receiver IRQ Enable Low Bit Timer 3 IRQ Enable Low Bit Interrupt Edge Select IRQES FCDH Read Write D7 D6 D5 D4 D3 D2 D1 DO L Port A or D Interrupt Edge Select 7 0 0 Falling edge 1 Rising edge PS019915 1005 Z8 Encore 64K Series Z8 Encore 38 ZiLOG Interrupt Port Select IRQPS FCEH Read Write D7 D6 D5S D4 D3 D2 D1 DO ____________ Port A or D Port Pin Select 7 0 0 Port A pin is the interrupt source 1 Port D pin is the interrupt source Interrupt Control IRQCTL FCFH Read Write D7 D6 D5S D4 D3 D2 D1 DO Reserved Interrupt Request Enable 0 Interrupts are disabled 1 Interrupts are enabled Port A Address PAADDR FDOH Read Write D7 D6 DSIDAID3ID2IDI DO ___________ Port A Address 7 0 Selects Port Sub Registers 00H No function 01H Data direction 02H Alternate function 03H z Output control open drain 04H High drive enable 05H STOP mode recovery enable 06H FFH No function Port A Control PACTL FDIH Read Write D7 D6 D5IDA4D3 D2ID1 DO Port A Control 7 0 Provides Access to Port Sub Registers
126. 20SC 24KB 2KB 31 23 3 8 1 1 2 LQFP 44 pin package Z8F2421VNO020SC 24KB 2KB 31 23 3 8 1 1 2 PLCC 44 pin package Z8F2422AR020SC 24KB 2KB 46 24 4 12 1 1 2 LQFP 64 pin package Z8F2422VS020SC 24KB 2KB 46 24 4 12 1 1 2 PLCC 68 pin package Extended Temperature 40 to 105 C Z8F2421PMO20EC 24KB 2KB 29 23 3 8 1 1 2 PDIP 40 pin package Z8F2421ANO020EC 24KB 2KB 31 23 3 8 1 1 2 LQFP 44 pin package Z8F2421VNO20EC 24KB 2KB 31 23 3 8 1 1 2 PLCC 44 pin package Z8F2422ARO020EC 24KB 2KB 46 24 4 12 1 1 2 LQFP 64 pin package Z8F2422VS020EC 24KB 2KB 46 24 4 12 1 1 2 PLCC 68 pin package Automotive Industrial Temperature 40 to 125 C Z8F2421PM020AC 24KB 2KB 29 23 3 8 1 1 2 PDIP 40 pin package Z8F2421ANO020AC 24KB 2KB 31 23 3 8 1 1 2 LQFP 44 pin package Z8F2421VNO020AC 24KB 2KB 31 23 3 8 1 1 2 PLCC 44 pin package Z8F2422AR020AC 24KB 2KB 46 24 4 12 1 1 2 LQFP 64 pin package Z8F2422VS020AC 24KB 2KB 46 24 4 12 1 1 2 PLCC 68 pin package Note Replace C with G for lead free packaging PS019915 1005 Ordering Information htt p ww xi npi an net o ee ee a og 010 62245566 13810019655 265 Z8 Encore 64K Series Product Specification ZiLOG Part Number Flash z lt x oc O Lines nterrupts 16 Bit Timers w PWM 10 Bit A D Channels o N SPI UARTS with IrDA Description Standard Temperature 0 to 70 C Digital Z8F162x with 16KB Flas
127. 241 bit swap 242 block diagram 3 block transfer instructions 239 BRK 241 BSET 239 BSWAP 239 242 BTJ 241 BTJNZ 241 BTJZ 241 C CALL procedure 241 capture mode 89 capture compare mode 89 Index htt p ww xi npi an net DEL EY EC BRE UE IMOO000000 010 62245566 13810019655 cc 235 CCF 240 characteristics electrical 209 clear 240 clock phase SPI 128 CLR 240 COM 241 compare 89 compare extended addressing 238 compare mode 89 compare with carry 238 compare with carry extended addressing 238 complement 241 complement carry flag 239 240 condition code 235 continuous conversion ADC 173 continuous mode 89 control register definition UART 109 control register I2C 155 counter modes 89 CP 238 CPC 238 CPCX 238 CPU and peripheral overview 3 CPU control instructions 240 CPX 238 customer feedback form 269 customer information 269 D DA 235 238 data register I2C 152 DC characteristics 211 debugger on chip 193 DEC 238 decimal adjust 238 decrement 238 decrement and jump non zero 241 decrement word 238 DECW 238 destination operand 236 device port availability 51 DI 240 PS019915 1005 Z8 Encore 64K Series Product Specification L a ZiLOG direct address 235 direct memory access controller 161 disable interrupts 240 DJNZ 241 DMA address high nibble register 165 configuring for DMA_ADC data transfer 163 confiigurting DMAO 1 data transfer 162 cont
128. 3 reload value 15 8 Operation of this bit is a function of the current operating mode of the timer Timer Enable Timer 3 Reload Low Byte 0 Timer is disabled T3RL FIBH Read Write 1 Timer is enabled D7D6 D5 DA4D3 D2DI DO Timer 3 reload value 7 0 PS019915 1005 Control Register Summary htt p ww xi npi an net COA ee ee DELI 010 62245566 13810019655 Z8 Encore 64K Series Z8 Encore 29 ZiLOG UARTO Transmit Data UARTO Control 0 UOTXD F40H Write Only UOCTLO F42H Read Write D7 D6 D5 D4 D3D2 D1 DO D7 D6 D5 D4D3D2DI1 DO UARTO transmitter data byte 7 0 L Loop Back Enable 0 Normal operation 1 Transmit data is looped back to the receiver UARTO Receive Data SCIES UORXD F40H Read Only otop Bit select 0 Transmitter sends 1 Stop bit D7 D6 D5 D4D3 D2 D1 D0 1 Transmitter sends 2 Stop bits UARTO receiver data byte 7 0 Send Break 0 No break is sent 1 Output of the transmitter is zero UARTO Status 0 L Parity Select UOSTATO F41H Read Only 0 Even parity D7 D6IDSID4D3 D2ID1 DO 1 Odd parity ENTIS Parity Enable L CTS signal M PER Returns the level of the CTS signal i i E is sey ___ Transmitter Empty CTS Enable 0 Data is currently
129. 4KB 4KB 31 23 3 8 1 1 2 LQFP 44 pin package Z8F6421VN020AC 64KB 4KB 31 23 3 8 1 1 2 PLCC 44 pin package Z8F6422AR020AC 64KB 4KB 46 24 4 12 1 1 2 LQFP 64 pin package Z8F6422VS020AC 64KB 4KB 46 24 4 12 1 1 2 PLCC 68 pin package Z8F6423FT020AC 64KB 4KB 60 24 4 12 1 1 2 QFP 80 pin package Note Replace C with G for lead free packaging PS019915 1005 Ordering Information htt p ww xi npi an net o ee ee a og 010 62245566 13810019655 Z8 Encore 64K Series Product Specification ZiLOG i o N o z c e E i o A iL oc nterrupts 16 Bit Timers w PWM 10 Bit A D Channels o N SPI UARTS with IrDA Description Standard Temperature 0 to 70 C Digital Z8F482x with 48KB Flash 10 Bit Analog to Converter Z8F4821PMO20SC 48KB 4KB 29 23 3 8 1 1 2 PDIP 40 pin package Z8F4821 ANO20SC 48KB 4KB 31 23 3 8 1 1 2 LQFP 44 pin package Z8F4821VNO020SC 48KB 4KB 31 23 3 8 1 1 2 PLCC 44 pin package Z8F4822AR020SC 48KB 4KB 46 24 4 12 1 1 2 LQFP 64 pin package Z8F4822VS020SC 48KB 4KB 46 24 4 12 1 1 2 PLCC 68 pin package Z8F4823FTO20SC 48KB 4KB 60 24 4 12 1 1 2 QFP 80 pin package Extended Temperature 40 to 4 105 C Z8F4821PMO020EC 48KB 4KB 29 23 3 8 1 1 2 PDIP 40 pin package Z8F4821ANO020EC 48KB 4KB 31 23 3 8 1 1 2 LQFP 44 pin package Z8F4821VNO20EC 48KB 4KB 31 23
130. 55 Z8 Encore 64K Series Product Specification ZiLOG cycles the devices progress through the System Reset sequence While the RESET input pin is asserted Low the 64K Series devices continue to be held in the Reset state If the RESET pin is held Low beyond the System Reset time out the devices exit the Reset state immediately following RESET pin deassertion Following a System Reset initiated by the external RESET pin the EXT status bit in the Watch Dog Timer Control WDTCTL reg ister is set to 1 On Chip Debugger Initiated Reset A Power On Reset can be initiated using the On Chip Debugger by setting the RST bit in the OCD Control register The On Chip Debugger block is not reset but the rest of the chip goes through a normal system reset The RST bit automatically clears during the system reset Following the system reset the POR bit in the WDT Control register is set STOP Mode Recovery STOP mode is entered by the eZ8 executing a STOP instruction Refer to the Section Low Power Modes on page 49 for detailed STOP mode information During STOP Mode Recovery the devices are held in reset for 66 cycles of the Watch Dog Timer oscillator followed by 16 cycles of the system clock STOP Mode Recovery only affects the contents of the Watch Dog Timer Control register STOP Mode Recovery does not affect any other values in the Register File including the Stack Pointer Register Pointer Flag
131. 57 I2C Baud Rate Low Byte Register I2CBRL 157 I2C Diagnostic State Register I2ZCDST 0 00 0 0004 158 I2C Diagnostic Control Register DCDIAG 160 DMAx Control Register DMAxCTL 0 0 0 c ee eee ee 164 DMAx I O Address Register DMAXIO esee 165 DMAx Address High Nibble Register DMAxH 165 DMAx Start Current Address Low Byte Register DMAxSTART 166 DMAx End Address Low Byte Register DMAxEND 167 DMA ADC Register File Address Example 167 DMA ADC Address Register DMAA ADDR sss 168 DMA ADC Control Register DMAACTL uueeeess 169 DMA ADC Status Register DMAA_STAT 0004 170 ADC Control Register ADCCTL 0 0 0 cece eee eee 175 ADC Data High Byte Register ADCD_H 176 ADC Data Low Bits Register ADCD L 020000 177 Flash Memory Configurations 0 0 cece eee eee ee 178 Flash Memory Sector Addresses 0 0 00 c eee eee eee eee 179 64K Series Information Area Map 0 0 0 e eee eee eee 180 Flash Control Register FCTL 20 0 0 cece eee 185 Flash Status Register FSTAT 0 0 e cece eee ee 186 Page Select Register FPS 0 2 c cece eee ee nee 187 Flash Sector Protect Register FPROT 00002 e eens 188 Flash Frequency High Byte Re
132. 60 SPI Data SPIDATA XX 133 F61 SPI Control SPICTL 00 133 F62 SPI Status SPISTAT 01 135 F63 SPI Mode SPIMODE 00 136 F64 SPI Diagnostic State SPIDST 00 137 F65 Reserved XX F66 SPI Baud Rate High Byte SPIBRH FF 138 F67 SPI Baud Rate Low Byte SPIBRL FF 138 F68 F6F Reserved XX Analog to Digital Converter ADC F70 ADC Control ADCCTL 20 175 F71 Reserved XX F72 ADC Data High Byte ADCD H XX 176 F73 ADC Data Low Bits ADCD L XX 176 F74 FAF Reserved XX DMA 0 FBO DMAO Control DMAOCTL 00 164 FB1 DMAO I O Address DMAOIO XX 165 FB2 DMAO End Start Address High Nibble DMAOH XX 165 FB3 DMAO Start Address Low Byte DMAOSTART XX 166 FB4 DMAO End Address Low Byte DMAOEND XX 167 DMA 1 FB8 DMAI Control DMAICTL 00 164 FB9 DMAI I O Address DMAIIO XX 165 FBA DMAI End Start Address High Nibble DMAIH XX 165 FBB DMA Start Address Low Byte DMAISTART XX 166 FBC DMAI End Address Low Byte DMAIEND XX 167 DMA ADC FBD DMA ADC Address DMAA_ADDR XX 168 FBE DMA_ADC Control DMAACTL 00 169 FBF DMA_ADC Status DMAASTAT 00 170 Interrupt Controller FCO Interrupt Request 0 IRQO 00 66 FC1 IRQO Enable High Bit IRQOENH 00 69 FC2 IRQO Enable Low Bit IRQOENL 00 69 FC3 Interrupt Request 1 IRQI 00 67 FC4 IRQI Enable High Bit IRQIENH 00 70 FC5 IRQI Enable Low Bit IRQIENL 00 70 FC6 Interrupt Request 2 IRQ2 00 68 XX Undefined PS019915 1005 Register File Address Map htt p ww xi npi an net LH Bugmaltqi tt EN 010 62245566 13810019655
133. 7 The slave may either Acknowledge or Not Acknowledge the last byte Because either the STOP or START bit is already set the NCKI interrupt does not occur 18 The C Controller sends the STOP or RESTART condition to the PC bus The STOP or START bit is cleared Address Only Transaction with a 10 bit Address In the situation where software wants to determine if a slave with a 10 bit address is responding without sending or receiving data a transaction can be done which only con sists of an address phase Figure 30 illustrates this address only transaction to determine if a slave with 10 bit address will acknowledge As an example this transaction can be used after a write has been done to a EEPROM to determine when the EEPROM com pletes its internal write operation and is once again responding to I2C transactions If the slave does not Acknowledge the transaction can be repeated until the slave is able to Acknowledge EX Slave Address T 1st 7 bits ee 2nd Byte AAT Slave Address Figure 30 10 Bit Address Only Transaction Format The procedure for an address only transaction to a 10 bit addressed slave is as follows 1 Software asserts the IEN bit in the I C Control register 2 Software asserts the TXI bit of the IC Control register to enable Transmit interrupts 3 The C interrupt asserts because the PC Data register is empty TDRE 1 4 Software responds to the TDRE interrupt by writing the first slave addr
134. 8 CPU s HALT instruction places the device into HALT mode In HALT mode the operating characteristics are Primary crystal oscillator is enabled and continues to operate System clock is enabled and continues to operate eZ8 CPU is stopped Program counter PC stops incrementing Watch Dog Timer s internal RC oscillator continues to operate The Watch Dog Timer continues to operate if enabled All other on chip peripherals continue to operate The eZ8 CPU can be brought out of HALT mode by any of the following operations Interrupt Watch Dog Timer time out interrupt or reset Power on reset Voltage brown out reset External RESET pin assertion To minimize current in HALT mode all GPIO pins which are configured as inputs must be driven to one of the supply rails V cc or GND PS019915 1005 htt p ww xi npi an net EE Low Power Modes HHHEHIHB HBIBBHBHH 010 62245566 13810019655 General Purpose I O Overview Z8 Encore 64K Series Product Specification 51 ZiLOG The 64K Series products support a maximum of seven 8 bit ports Ports A G and one 4 bit port Port H for general purpose input output I O operations Each port contains control and data registers The GPIO control registers are used to determine data direction open drain output drive current and alternate pin functions Each port pin is individually programmable All ports except B and H support 5V tolerant
135. 9915 1005 Packaging htt p ww xi npi an net COA PSEPENED UBL ELET DIT 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 262 ZiLOG Ordering Information Z v aj lt 2865 a x o0 E o 9 lt o 2E 28 EBE 3 o grLr o 8 z c E Z x EE s zz2i58 l k i amp le fai eo ic Q Zeg ef Gls oc Z8F642x with 64KB Flash 10 Bit Analog to Digital Converter Standard Temperature 0 to 70 C 1 Z8F6421PM020SC 64KB 4KB 29 23 3 8 1 1 2 PDIP 40 pin package Z8F6421ANO020SC 64KB 4KB 31 23 3 8 1 1 2 LQFP 44 pin package Z8F6421VNO020SC 64KB 4KB 31 23 3 8 1 1 2 PLCC 44 pin package Z8F6422AR020SC 64KB 4KB 46 24 4 12 1 1 2 LQFP 64 pin package Z8F6422VS020SC 64KB 4KB 46 24 4 12 1 1 2 PLCC 68 pin package Z8F6423FTO20SC 64KB 4KB 60 24 4 12 1 1 2 QFP 80 pin package Extended Temperature 40 to 105 C Z8F6421PMO20EC 64KB 4KB 29 23 3 8 1 1 2 PDIP 40 pin package Z8F6421AN020EC 64KB 4KB 31 23 3 8 1 1 2 LQFP 44 pin package Z8F6421VNO20EC 64KB 4KB 31 23 3 8 1 1 2 PLCC 44 pin package Z8F6422AR020EC 64KB 4KB 46 24 4 12 1 1 2 LQFP 64 pin package Z8F6422VS020EC 64KB 4KB 46 24 4 12 1 1 2 PLCC 68 pin package Z8F6423FTO20EC 64KB 4KB 60 24 4 12 1 1 2 QFP 80 pin package Automotive Industrial Temperature 40 to 125 C Z8F6421PMO020AC 64KB 4KB 29 23 3 8 1 1 2 PDIP 40 pin package Z8F6421 ANO20AC 6
136. ARTI Receive Data UIRXD F48H Read Only D7 D6 D5 D4 D3 D2 D1 DO htt p ww xi npi an net DEL EY EC BRE UE IG1U D UU Uu UARTI transmitter data byte 7 0 UART receiver data byte 7 0 Control Register Summary 010 62245566 13810019655 30 UARTI Status 0 UISTATO F49H Read Only D7ID6 ID5 D4D3DD2DDI DO L CTS signal Returns the level of the CTS signal L Transmitter Empty 0 Data is currently transmitting 1 Transmission is complete Transmitter Data Register Empty 0 Transmit Data Register is full 1 Transmit Data register is empty Break Detect 0 No break occurred 1 A break occurred Framing Error 0 No framing error occurred 1 A framing occurred Overrun Error 0 No overrun error occurred 1 An overrun error occurred Parity Error 0 No parity error occurred 1 A parity error occurred Receive Data Available PS019915 1005 htt p ww xi npi an net 0 Receive Data Register is empty 1 A byte is available in the Receive Data Register UARTI Control 0 D7 D6 D5 D4 D3 D2 D1 DO OOUOQUOO IMOO000000 Z8 Encore 64K Series Z8 Encore 31 ZiLOG UICTLO F4AH Read Write L Loop Back Enable 0 Normal operation 1 Transmit data is looped back to
137. B AME o 2 2 JR cc dst if cc is true DA OB FB JE 2 2 PC lt PC X LD dst rc dst lt src r IM 0C FC PL LLL 2 2 r X r C7 3 3 Xr r D7 3 4 r Ir E3 2 3 R R E4 3 2 R IR E5 3 4 R IM E6 3 2 IR IM E7 3 3 Ir r F3 2 3 IR R F5 3 3 LDC dst src dst lt src r Irr C2 2 5 Ir Irr C5 2 9 Irr r D2 2 5 LDCI dst src dst src Ir Irr C3 LLLI A 2 9 te ir dr D3 2 3 LDE dst src dst lt src r Irr 82 2 2 5 Irr r 92 2 5 LDEI dst src dst lt src Ir Irr 83 o2 2 9 AA 1 irr lr a a i LDW X dst src dst lt src ER ER 1F E8 LI LL 5 4 Flags Notation Value is a function of the result of the operation 0 Reset to 0 Unaffected 1 Setto 1 X Undefined PS019915 1005 eZ8 CPU Instruction Set htt p ww xi npi an net o ee ee a og 010 62245566 13810019655 Z8 Encore 64K Series Product Specification ziLoG Table 132 eZ8 CPU Instruction Summary Continued Assembly abel Opcode s rae Fetch Instr Mnemonic Symbolic Operation dst src Hex C Z S V D H Cycles Cycles LDX dst src dst src r ER 84 DEM S LL ZZ 3 2 Ir ER 85 3 3 R IRR 86 3 4 IR IRR 87 3 5 r X rr 88 3 4 Xa r 89 3 4 ER r 94 3 2 ER Ir 95 3 3 IRR R 96 3 4 IRR IR 97 3 5 ER ER E8 4 2 ER IM E9 4 2 LEA dst X src dst lt src X r X r 98 JM S LZ 3 3 IT X rr 99 3 5 MU
138. CD takes when a BRK instruction is decoded if breakpoints are enabled BRKEN is 1 If this bit is 0 then the DBGMODE bit is automat ically set to 1 and the OCD entered DEBUG mode If BRKLOOP is set to 1 then the eZ8 CPU loops on the BRK instruction 0 BRK instruction sets DBGMODE to 1 1 eZ8 CPU loops on BRK instruction Reserved These bits are reserved and must be 0 On Chip Debugger IMoOo00 UU 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 204 ZiLOG RST Reset Setting this bit to 1 resets the 64K Series devices The devices go through a normal Power On Reset sequence with the exception that the On Chip Debugger is not reset This bit is automatically cleared to O when the reset finishes 0 No effect 1 Reset the 64K Series device OCD Status Register The OCD Status register Table 102 reports status information about the current state of the debugger and the system Table 102 OCD Status Register OCDSTAT BITS 7 6 5 4 3 2 1 0 FIELD IDLE HALT RPEN Reserved RESET 0 R W R PS019915 1005 htt p ww xi npi an net Hg g dg p B m IDLE CPU idling This bit is set if the part is in DEBUG mode DBGMODE is 1 or if a BRK instruction occurred since the last time OCDCTL was written This can be used to determine if the CPU is running or if it is idling 0 The eZ8 CPU is running 1
139. CK VSS VDD PC6 T2IN DBG PC1 T1OUT PCO T1IN AVSS L VREF PB2 ANA2 PB3 ANA3 I PB7 ANA7 PB6 ANA6 Figure 2 64K Series in 40 Pin Dual Inline Package PDIP PS019915 1005 htt p ww xi npi an net uu IG i uu UU T2OUT is not supported Signal and Pin Descriptions 010 62245566 13810019655 2 oO O o08e9 OooDg Ondo ocnd GaP eneasess aAgQHaTHTTHS acxogdaoaaoaxza x C n nn nn na na n a a i d PAO TOIN 7 39 PD2 Pc2 SS RESET VDD VSS 12 34 PD1 PDO XOUT XIN VDD 17 29 18 23 28 Pe dee ae Pa a azgzxzx22z2209 SZ22222242a5 aataaqatatttrt I gt X o soorBmdg emccxcdcccclmunntumn oO n a a n a n Z8 Encore 64K Series Product Specification ZiLOG PA7 SDA PD6 CTS1 PC3 SCK VSS VDD PC7 T2OUT PC6 T2IN DBG PC1 T1OUT PCO T1IN VSS Figure 3 64K Series in 44 Pin Plastic Leaded Chip Carrier PLCC PS019915 1005 htt p ww xi npi an net OOU IG D U D UU Signal and Pin Descriptions 010 62245566 13810019655 PA2 DEO I PA3 CTSO PC5 MISO PD3 DE1 PD5 TXD1 PC4 MOSI PA4 RXDO PA5 TXDO PAO TOIN PD2 PC2 SS RESET VDD vss PD1 PDO XOUT XIN VDD amp i
140. Command Byte in DEBUG mode Read Protect Option Bit Write Register 08H Only writes of the Flash Memory Control registers are allowed Additionally only the Mass Erase command is allowed to be written to the Flash Control register Read Register 09H Disabled Write Program Memory OAH Disabled Read Program Memory OBH Disabled Write Data Memory OCH Disabled Read Data Memory O0DH Disabled Read Program Memory CRC OEH Reserved OFH Step Instruction 10H Disabled Stuff Instruction 11H Disabled Execute Instruction 12H Disabled Reserved 13H FFH In the following bulleted list of OCD Commands data and commands sent from the host to the On Chip Debugger are identified by DBG lt Command Data Data sent from the On Chip Debugger back to the host is identified by DBG Data PS019915 1005 Read OCD Revision 00H The Read OCD Revision command determines the version of the On Chip Debugger If OCD commands are added removed or changed this revision number changes DBG lt 00H DBG OCDREV 15 8 Major revision number DBG OCDREV 7 0 Minor revision number Read OCD Status Register 02H The Read OCD Status Register command reads the OCDSTAT register DBG lt 02H DBG OCDSTAT 7 0 Write OCD Control Register 04H The Write OCD Control Register command writes the data that follows to the OCDCTL register When the Read Protect Option Bit is enabled the DBGMODE bit OCDCTL 7 can only
141. D commands are avail able In DEBUG mode all OCD commands become available unless the user code and control registers are protected by programming the Read Protect Option Bit RP The Read Protect Option Bit prevents the code in memory from being read out of the 64K Series products When this option is enabled several of the OCD commands are disabled Table 100 contains a summary of the On Chip Debugger commands Each OCD com mand is described in further detail in the bulleted list following Table 100 Table 100 indi cates those commands that operate when the device is not in DEBUG mode normal operation and those commands that are disabled by programming the Read Protect Option Bit Table 100 On Chip Debugger Commands Enabled when NOT Disabled by Debug Command Command Byte in DEBUG mode Read Protect Option Bit Read OCD Revision 00H Yes Read OCD Status Register 02H Yes Read Runtime Counter 03H Write OCD Control Register 04H Yes Cannot clear DBGMODE bit Read OCD Control Register 05H Yes Write Program Counter 06H Disabled Read Program Counter 07H Disabled PS019915 1005 On Chip Debugger htt p ww xi npi an net LEE EB DRE EL EE EGET ET VE Ooo 010 62245566 13810019655 Table 100 On Chip Debugger Commands Continued Z8 Encore 64K Series Product Specification L ZiLOG Enabled when NOT Disabled by Debug Command
142. Data Bus r byez8CPU Figure 50 Port Input Sample Timing Table 113 GPIO Port Input Timing Delay ns Parameter Abbreviation Min Max Ts PORT Port Input Transition to XIN Fall Setup Time 5 Not pictured Tu poRT XIN Fall to Port Input Transition Hold Time 6 z Not pictured TSMR GPIO Port Pin Pulse Width to Insure STOP Mode lus PS019915 1005 htt p ww xi npi an net Recovery for GPIO Port Pins enabled as SMR sources D U Uu UU Electrical Characteristics 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Zi ZiLOG General Purpose I O Port Output Timing Figure 51 and Table 114 provide timing information for GPIO Port pins TCLK j XIN T2 Port Output Figure 51 GPIO Port Output Timing Table 114 GPIO Port Output Timing Delay ns Parameter Abbreviation Min Max GPIO Port pins Ty XIN Rise to Port Output Valid Delay 20 T2 XIN Rise to Port Output Hold Time 2 PS019915 1005 Electrical Characteristics htt p ww xi npi an net COA PSEPENED UBL ELET DIT 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z ZiLOG On Chip Debugger Timing Figure 52 and Table 115 provide timing information for the DBG pin The DBG pin tim ing specifications assume a 4us maximum rise and fall time
143. Data Format with Parity Transmitting Data using the Polled Method Follow these steps to transmit data using the polled method of operation 1 Write to the UART Baud Rate High and Low Byte registers to set the desired baud rate 2 Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation 3 If multiprocessor mode is desired write to the UART Control 1 register to enable Multiprocessor 9 bit mode functions Set the MULTIPROCESSOR Mode Select MPEN to Enable MULTIPROCESSOR mode 4 Write to the UART Control 0 register to Set the transmit enable bit TEN to enable the UART for data transmission If parity is desired and MULTIPROCESSOR mode is not enabled set the parity enable bit PEN and select either Even or Odd parity PSEL PS019915 1005 htt p ww xi npi an net HBBHHEHEBEEHJISIHHEBHB O0 UART 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 101 ZiLOG Setor clear the CTSE bit to enable or disable control from the remote receiver using the CTS pin 5 Check the TDRE bit in the UART Status 0 register to determine if the Transmit Data register is empty indicated by a 1 If empty continue to Step 6 If the Transmit Data register is full indicated by a 0 continue to monitor the TDRE bit until the Transmit Data register becomes available to receive new data 6 Writ
144. Data Rate 7 Desired Data Rate Desired Data Rate For reliable communication the UART baud rate error must never exceed 5 percent Table 60 provides information on data rate errors for popular baud rates and commonly used crystal oscillator frequencies PS019915 1005 UART htt p ww xi npi an net o ee ee a og 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z 117 ZiLOG Table 60 UART Baud Rates 20 0 MHz System Clock 18 432 MHz System Clock Desired Rate BRG Divisor Actual Rate Error Desired Rate BRG Divisor Actual Rate Error KHz Decimal kHz kHz Decimal kHz 1250 0 1 1250 0 0 00 1250 0 1 1152 0 7 84 625 0 2 625 0 0 00 625 0 2 576 0 7 84 250 0 5 250 0 0 00 250 0 5 230 4 7 84 115 2 11 113 6 1 36 115 2 10 115 2 0 00 57 6 22 56 8 1 36 57 6 20 57 6 0 00 38 4 33 37 9 1 36 38 4 30 38 4 0 00 19 2 65 19 2 0 16 19 2 60 19 2 0 00 9 60 130 9 62 0 16 9 60 120 9 60 0 00 4 80 260 4 81 0 16 4 80 240 4 80 0 00 2 40 521 2 40 0 03 2 40 480 2 40 0 00 1 20 1042 1 20 0 03 1 20 960 1 20 0 00 0 60 2083 0 60 0 02 0 60 1920 0 60 0 00 0 30 4167 0 30 0 01 0 30 3840 0 30 0 00 16 667 MHz System Clock 11 0592 MHz System Clock Desired Rate BRG Divisor Actual Rate Error Desired Rate BRG Divisor Actual Rate Error kHz Decimal kHz kHz Decimal kHz
145. E Equals One Figure 26 illustrates the timing diagram for an SPI transfer in which PHASE is one Two waveforms are depicted for SCK one for CLKPOL reset to 0 and another for CLKPOL set to 1 PS019915 1005 Serial Peripheral Interface HHHEHEHIGBUHBBHBHH 010 62245566 13810019655 htt p ww xi npi an net EE Z8 Encore 64K Series Product Specification L ZiLOG SCK CLKPOL 0 SCK CLKPOL 1 MOSI MISO Input Sample Time SS Figure 26 SPI Timing When PHASE is 1 Multi Master Operation In a multi master SPI system all SCK pins are tied together all MOSI pins are tied together and all MISO pins are tied together All SPI pins must then be configured in open drain mode to prevent bus contention At any one time only one SPI device is con figured as the Master and all other SPI devices on the bus are configured as Slaves The Master enables a single Slave by asserting the SS pin on that Slave only Then the single Master drives data out its SCK and MOSI pins to the SCK and MOSI pins on the Slaves including those which are not enabled The enabled Slave drives data out its MISO pin to the MISO Master pin For a Master device operating in a multi master system if the SS pin is configured as an input and is driven Low by another Master the COL bit is set to 1 in the SPI Status Regis ter The COL bit indicates the occurrence of a multi master collision
146. EE Z8 Encore 64K Series Product Specification Z 108 Zz L a Receiver Ready Receiver Interrupt Read Status No Errors Yes Read Data which clears RDA bit and resets error bits Read Data Discard Data Figure 18 UART Receiver Interrupt Service Routine Flow Baud Rate Generator Interrupts If the Baud Rate Generator BRG interrupt enable is set the UART Receiver interrupt asserts when the UART Baud Rate Generator reloads This action allows the Baud Rate Generator to function as an additional counter if the UART functionality is not employed UART Baud Rate Generator The UART Baud Rate Generator creates a lower frequency baud rate clock for data trans mission The input to the Baud Rate Generator is the system clock The UART Baud Rate High and Low Byte registers combine to create a 16 bit baud rate divisor value PS019915 1005 UART htt p ww xi npi an net LEE EB DRE EL EE EGET ET VE Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 109 ZiLOG BRG 15 0 that sets the data transmission rate baud rate of the UART The UART data rate is calculated using the following equation A _ System Clock Frequency Hz DARE Data Rate ubera 16 x UART Baud Rate Divisor Value When the UART is disabled the Baud Rate Generator can function as a basic 16 bit timer with interrupt on tim
147. ES5 IES4 IES3 IES2 IES1 IESO RESET 0 R W R W ADDR FCDH IESx Interrupt Edge Select x The minimum pulse width should be greater than 1 system clock to guarantee capture of the edge triggered interrupt Shorter pulses may be captured but not guaranteed 0 An interrupt request is generated on the falling edge of the PAx PDx input 1 An interrupt request is generated on the rising edge of the PAx PDx input where x indicates the specific GPIO Port pin number 0 through 7 Interrupt Port Select Register The Port Select IRQPS register Table 37 determines the port pin that generates the PAx PDx interrupts This register allows either Port A or Port D pins to be used as inter rupts The Interrupt Edge Select register controls the active interrupt edge Table 37 Interrupt Port Select Register IRQPS BITS 7 6 5 4 3 2 1 0 FIELD PAD7S PAD6S PAD5S PAD4S PAD3S PAD2S PADIS PADOS RESET 0 R W R W ADDR FCEH PADxS PAx PDx Selection 0 PAx is used for the interrupt for PAx PDx interrupt request 1 PDx is used for the interrupt for PAx PDx interrupt request where x indicates the specific GPIO Port pin number 0 through 7 PS019915 1005 htt p ww xi npi an net Interrupt Controller D U Uu LH 010 62245566 13810019655 Z8 Encore 64K Series Product Specification VAE ZiLOG Interrupt Control Registe
148. Enable Sub Registers The Port A H High Drive Enable sub register Table 19 is accessed through the Port A H Control register by writing 04H to the Port A H Address register Setting the bits in the Port A H High Drive Enable sub registers to 1 configures the specified port pins for high current output drive operation The Port A H High Drive Enable sub register affects the pins directly and as a result alternate functions are also affected Table 19 Port A H High Drive Enable Sub Registers BITS 7 6 5 4 3 2 1 0 FIELD PHDE7 PHDE6 PHDE5 PHDE4 PHDE3 PHDE2 PHDE1 PHDEO RESET 0 R W R W ADDR If 04H in Port A H Address Register accessible through Port A H Control Register PS019915 1005 htt p ww xi npi an net Hg g dg p B m PHDE 7 0 Port High Drive Enabled 0 The Port pin is configured for standard output current drive 1 The Port pin is configured for high output current drive Port A H STOP Mode Recovery Source Enable Sub Registers The Port A H STOP Mode Recovery Source Enable sub register Table 20 is accessed through the Port A H Control register by writing 05H to the Port A H Address register Setting the bits in the Port A CH STOP Mode Recovery Source Enable sub registers to 1 configures the specified Port pins as a STOP Mode Recovery source During STOP Mode any logic transition on a Port pin enabled as a STOP Mode Recovery source initiates STOP Mode Recovery Genera
149. Encore 64K Series Product Specification L z ZiLOG Table 131 Rotate and Shift Instructions Mnemonic Operands Instruction BSWAP dst Bit Swap RL dst Rotate Left RLC dst Rotate Left through Carry RR dst Rotate Right RRC dst Rotate Right through Carry SRA dst Shift Right Arithmetic SRL dst Shift Right Logical SWAP dst Swap Nibbles eZ8 CPU Instruction Summary Table 132 summarizes the eZ8 CPU instructions The table identifies the addressing modes employed by the instruction the effect upon the Flags register the number of CPU clock cycles required for the instruction fetch and the number of CPU clock cycles required for the instruction execution Table 132 eZ8 CPU Instruction Summary Address Mode Flags Assembly Opcode s Fetch Instr Mnemonic Symbolic Operation dst src Hex C Z S V D H Cycles Cycles ADC dst src dst lt dst src C r r 12 wo OS we we yo o 2 3 r Ir 13 2 4 R R 14 3 3 R IR 15 3 4 R IM 16 3 3 IR IM 17 3 4 ADCKX dst src dst lt dst src C ER ER 18 WU oes sue vw pn Ow 4 3 ER IM 19 4 3 Flags Notation Value is a function of the result of the operation 0 Reset to 0 Unaffected 1 Set to 1 X Undefined PS019915 1005 eZ8 CPU Instruction Set htt p ww xi npi an net utu ee ee EU og 010 62245566 13810019655 Z8 Encore 64K Series
150. FP 64 pin package Z8F3222VS020SC 32KB 2KB 46 24 4 12 1 1 2 PLCC 68 pin package Extended Temperature 40 to 105 C Z8F3221PMO020EC 32KB 2KB 29 23 3 8 1 1 2 PDIP 40 pin package Z8F3221 ANO20EC 32KB 2KB 31 23 3 8 1 1 2 LQFP 44 pin package Z8F3221VN020EC 32KB 2KB 31 23 3 8 1 1 2 PLCC 44 pin package Z8F3222AR020EC 32KB 2KB 46 24 4 12 1 1 2 LQFP 64 pin package Z8F3222VS020EC 32KB 2KB 46 24 4 12 1 1 2 PLCC 68 pin package Automotive Industrial Temperature 40 to 125 C Z8F3221PM020AC 32KB 2KB 29 23 3 8 1 1 2 PDIP 40 pin package Z8F3221 ANO20AC 32KB 2KB 31 23 3 8 1 1 2 LQFP 44 pin package Z8F3221VN020AC 32KB 2KB 31 23 3 8 1 1 2 PLCC 44 pin package Z8F3222AR020AC 32KB 2KB 46 24 4 12 1 1 2 LQFP 64 pin package Z8F3222VS020AC 32KB 2KB 46 24 4 12 1 1 2 PLCC 68 pin package Note Replace C with G for lead free packaging PS019915 1005 Ordering Information htt p ww xi npi an net LH uam ai ood DLE 010 62245566 13810019655 264 Z8 Encore 64K Series Product Specification ZiLOG Part Number Flash z lt x oc O Lines nterrupts 16 Bit Timers w PWM 10 Bit A D Channels o N SPI UARTS with IrDA Description Standard Temperature 0 to 70 C Digital Z8F242x with 24KB Flash 10 Bit Analog to Converter Z8F2421PMO20SC 24KB 2KB 29 23 3 8 1 1 2 PDIP 40 pin package Z8F 2421 ANO
151. H 3 0 I O I N A Yes No Yes Yes Programmable RESET I I Low N A Pull up Yes N A VDD N A N A N A N A No No N A XIN I I N A N A No No N A XOUT O O N A Yes in No No No STOP mode x represents integer 0 1 to indicate multiple pins with symbol mnemonics that differ only by the integer PS019915 1005 Signal and Pin Descriptions htt p ww xi npi an net o ee ee a og 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 17 ZiLOG Address Space Overview The eZ8 CPU can access three distinct address spaces The Register File contains addresses for the general purpose registers and the eZ8 CPU peripheral and general purpose I O port control registers The Program Memory contains addresses for all memory locations having executable code and or data The Data Memory contains addresses for all memory locations that hold data only These three address spaces are covered briefly in the following subsections For more detailed information regarding the eZ8 CPU and its address space refer to the eZ8 CPU User Manual available for download at www zilog com Register File The Register File address space in the 64K Series is 4KB 4096 bytes The Register File is composed of two sections control registers and general purpose registers When instructions are executed registers are read from when defined as sources and written to when de
152. IP Maximum Ratings at 70 C to 125 C Total power dissipation 540 mW Maximum current into Vpp or out of Vss 150 mA Notes 1 This voltage applies to all pins except the following VDD AVDD pins supporting analog input Ports B and H RESET and where noted otherwise PS019915 1005 Electrical Characteristics htt p ww xi npi an net utu ee ee EU og 010 62245566 13810019655 DC Characteristics Z8 Encore 64K Series Product Specification Z 211 ZiLOG Table 105 lists the DC characteristics of the 64K Series products All voltages are refer enced to Vgg the primary system ground Table 105 DC Characteristics T 40 C to 125 C Symbol Parameter Minimum Typical Maximum Units Conditions VDD Supply Voltage 3 0 3 6 V Viri Low Level Input Voltage 0 3 0 3 Vpp V For all input pins except RESET DBG XIN ViL2 Low Level Input Voltage 0 3 0 2 Vpp V For RESET DBG and XIN Vini High Level Input Voltage 0 7 Vpp B 5 5 V Port A C D E F and G pins Vino High Level Input Voltage 0 7 Vpp Vppt0 3 V Port B and H pins Via High Level Input Voltage 0 8 Vpp Vppt0 3 V RESET DBG and XIN pins VoL Low Level Output Voltage 0 4 V Ho 2mA VDD 3 0V Standard Drive High Output Drive disabled Von High Level Output Voltage 2 4 V oq 2mA VDD 3 0V
153. IRQ1 BITS T 6 5 4 3 2 1 0 FIELD PAD7I PAD6I PADSI PAD4I PAD3I PAD2I PADII PADOI RESET 0 R W R W ADDR FC3H PADxI Port A or Port D Pin x Interrupt Request 0 No interrupt request is pending for GPIO Port A or Port D pin x 1 An interrupt request from GPIO Port A or Port D pin x is awaiting service where x indicates the specific GPIO Port pin number 0 through 7 For each pin only 1 of either Port A or Port D can be enabled for interrupts at any one time Port selection A or D is determined by the values in the Interrupt Port Select Register Interrupt Request 2 Register The Interrupt Request 2 IRQ2 register Table 26 stores interrupt requests for both vec tored and polled interrupts When a request is presented to the interrupt controller the cor responding bit in the IRQ2 register becomes 1 If interrupts are globally enabled vectored interrupts the interrupt controller passes an interrupt request to the eZ8 CPU If interrupts are globally disabled polled interrupts the eZ8 CPU can read the Interrupt Request 1 register to determine if any interrupt requests are pending Table 26 Interrupt Request 2 Register IRQ2 BITS 7 6 5 4 3 2 1 0 FIELD T3I UIRXI UITXI DMAI PC3I PC2I PCII PCOI RESET 0 R W R W ADDR FC6H PS019915 1005 htt p ww xi npi an net OTe PSER ELE T H E T3I Timer 3 Interrupt Request 0 No interrupt request is pending for Timer
154. Interrupt Request Enable Low Bit IRQ1 Enable High and Low Bit Registers The IRQ1 Enable High and Low Bit registers Tables 31 and 32 form a priority encoded enabling for interrupts in the Interrupt Request 1 register Priority is generated by setting bits in each register Table 30 describes the priority control for IRQ Table 30 IRQ1 Enable and Priority Encoding IRQIENH x IRQIENL x Priority Description 0 0 Disabled Disabled 0 1 Level 1 Low 1 0 Level 2 Nominal 1 1 Level 3 High where x indicates the register bits from O through 7 PS019915 1005 Interrupt Controller htt p ww xi npi an net utu ee ee EU og 010 62245566 13810019655 Z8 Encore 64K Series Product Specification ZiLOG Table 31 IRQ1 Enable High Bit Register IRQIENH BITS 7 6 5 4 3 2 1 0 FIELD PAD7ENH PAD6ENH PADSENH PAD4ENH PAD3ENH PAD2ENH PADIENH PADOENH RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FC4H PADxENH Port A or Port D Bit x Interrupt Request Enable High Bit Refer to the Interrupt Port Select register for selection of either Port A or Port D as the interrupt source Table 32 IRQ1 Enable Low Bit Register IRQIENL BITS 7 6 5 4 3 2 1 0 FIELD PAD7ENL PAD6ENL PADSENL PADAENL PAD3ENL PAD2ENL PADIENL PADOENL RESET 0 0 0 0 0 0 0 0 R w R W
155. K Series Product Specification xviii ZiLOG Manual Objectives This Product Specification provides detailed operating information for the Flash devices within the Z8 Encore 64K Series Microcontroller MCU products Within this docu ment the Z8F642x Z8F482x Z8F322x Z8F242x and Z8F162x devices are referred to collectively as the Z8 Encore 64K Series unless specifically stated otherwise About This Manual ZiLOG recommends that the user read and understand everything in this manual before setting up and using the product However we recognize that there are different styles of learning Therefore we have designed this Product Specification to be used either as a how to procedural manual or a reference guide to important data Intended Audience This document is written for ZiLOG customers who are experienced at working with microcontrollers integrated circuits or printed circuit assemblies Manual Conventions The following assumptions and conventions are adopted to provide clarity and ease of use Courier Typeface Commands code lines and fragments bits equations hexadecimal addresses and various executable items are distinguished from general text by the use of the Courier typeface Where the use of the font is not indicated as in the Index the name of the entity is pre sented in upper case e Example FLAGS 1 is smrf Hexadecimal Values Hexadecimal values are designated by uppercase H suffix and
156. KR Rr Gh ETT 190 Option Bit Configuration By Reset 2 0 0 eee eee eee 190 Option Bit Address Space 0 eee cece eee 190 Flash Memory Address 0000H 0 0 0 cece eee eA 191 Flash Memory Address 0001H 2 0 0 cee eee eens 192 On Chip Debugger 55 yere seca ehm my ea et n n inte ERIS Ws sae sls Wiese Ie eke Le inn 193 OVEIVIEW oi yeu uer dee eve ique y pU Ep dede Ene ear EEG Sere ee 193 At1chitect te 222r me oe towed toned dae bud deed dT d 193 Operation sesei dieu iaces p xe DURPP nied br debe dad wie Shed Ads 194 OCD Interface lolo eue ser RERO n re E PERI RETE de 194 Debug Mode cre c eerte e a cbe hr tb o ob es EE eae 195 OCD Data Format 52i d teme Rada bes sida dda piddies ceed 196 OCD Auto Baud Detector Generator 0 0 0 eee ee 196 OCD Serial Errors i oru eee ells la ade a a el ed eel ee aad 197 Breakpoimts i21 ctawedddawerS stew sadn pere Ranked antea Ear Seat 197 PS019915 1005 Table of Contents htt p ww xi npi an net DOT 010 62245566 13810019655 Z8 Encore 64K Series Product Specification ZiLOG On Chip Debugger Commands 0 0c eee eee ree 198 On Chip Debugger Control Register Definitions 0 0 0 0 e ee ee eee 202 OCD Control Register 2 d ugs ek ae Mae dW as o 202 OCD Stattis Resister edes cce elus eas lRes puoR esa RR d e LER 204 On Chip Oscillator 3er ah RR EE RR GueE Ur EE NE TA RE SR E RAE 205 OVEIVIEW
157. LLIMETER SYMBOL MIN MAX A 14 1 60 Al 0 0 A2 0 5 0 15 1 45 0 012 0 018 0 004 0 008 0 463 0 482 HE 0 390 0 398 0 463 0 482 DETAIL A 0 390 0 398 0 031 BSC 0 018 0 030 F 0 039 REF 1 CONTROLLING DIMENSIONS mm 2 MAX COPLANARITY 10mm 0 004 a L E a 0 7 DETAIL A Figure 63 44 Lead Low Profile Quad Flat Package LQFP PS019915 1005 Packaging htt p ww xi npi an net ugmumgmngumnuigdiBui Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification L z ZiLOG Figure 64 illustrates the 44 pin PLCC plastic lead chip carrier package available for the Z8X1621 Z8X2421 Z8X3221 Z8X4821 and Z8X6421 devices be A D At m D1 0 71 0 51 45 028 020 a 8 1 40 i lt yoo Tt i pod i 6 5 MILLIMETER O LR Ie FL oj m MAX H ss 5b 5 ce Et P ag FRO osyos 9 al ABB EEA ue D jam s E L I 1 0 032 0 026 O zi i L D 1E 1 27 BSC 0 050 BSC 7g DEP Pee ees R 1 14 0 64 z NOTES 0 045 0 025 1 CONTROLLING DIMENSION INCH 2 LEADS ARE COPLANAR WITHIN 0 004 3 DIMENSION MM N Figure 64 44 Lead Plastic Lead Chip Carrier Package PLCC Figure 64 illustrates the 64 pin LQFP low profile quad flat package avai
158. LT dst dst 15 0 lt RR F4 AM o 2 8 dst 15 8 dst 7 0 NOP No operation OF JE ZZ 1 2 OR dst sre dst lt dst OR src r r 42 Q0 2 3 r Ir 43 2 4 R R 44 3 3 R IR 45 3 4 R IM 46 3 3 IR IM 47 3 4 ORX dst src dst dst OR src ER ER 48 Q0 4 3 ER IM 49 4 3 Flags Notation Value is a function of the result of the operation 0 Reset to 0 Unaffected 1 Set to 1 X Undefined PS019915 1005 eZ8 CPU Instruction Set htt p ww xi npi an net o ee ee a og 010 62245566 13810019655 247 Table 132 eZ8 CPU Instruction Summary Continued Z8 Encore 64K Series Product Specification ZiLOG 248 Assembly A Opcode s PRO Fetch Instr Mnemonic Symbolic Operation dst src Hex C Z S V D H Cycles Cycles POP dst dst lt GSP R 50 JE I I SL C 2 2 SP lt SP 1 IR 51 2 3 POPX dst dst lt GSP ER D8 ZZ L 3 2 SP lt SP 1 PUSH src SP lt SP 1 R 70 JE I SL C 2 2 SP lt src IR 7l 2 3 IM IF 70 3 2 PUSHX src SP lt SP 1 ER C8 JE ZZ S 3 2 SP lt src RCF Cc 0 CF 0 os 1 2 RET PC SP AF JM ZI SL 1 4 SP SP 2 RL dst R 90 de ge ceo oko o 2 2 R a RLC dst R 10 X X ck Ub nc 2 2 IR T Eum RR dst R EO de ck WS 39 mtu 2 2 7 E xm RRC dst R C0 do e o 5e m 4 2 2 pip pee IR Cl f 3 Flags Notation Value is a function of the result of the operat
159. Mode through the On Chip Debug ger the Watch Dog Timer is continuously refreshed to prevent spurious Watch Dog Timer time outs Watch Dog Timer Time Out Response The Watch Dog Timer times out when the counter reaches 000000H A time out of the Watch Dog Timer generates either an interrupt or a Reset The WDT RES Option Bit determines the time out response of the Watch Dog Timer Refer to the Option Bits chap ter for information regarding programming of the WDT RES Option Bit WDT Interrupt in Normal Operation If configured to generate an interrupt when a time out occurs the Watch Dog Timer issues an interrupt request to the interrupt controller and sets the WDT status bit in the Watch Dog Timer Control register If interrupts are enabled the eZ8 CPU responds to the interrupt request by fetching the Watch Dog Timer interrupt vector and executing code from the vector address After time out and interrupt generation the Watch Dog Timer counter rolls over to its maximum value of FFFFFH and continues counting The Watch Dog Timer counter is not automatically returned to its Reload Value WDT Interrupt in STOP Mode If configured to generate an interrupt when a time out occurs and the 64K Series devices are in STOP mode the Watch Dog Timer automatically initiates a STOP Mode Recovery and generates an interrupt request Both the WDT status bit and the STOP bit in the Watch Dog Timer Control register are set to 1 following WDT time out in STO
160. Nd eed Re eR 17 Register Fil 2 120 risisco wina Bena x EEG Ee ERIT EON Di s 17 Program Memoty isse t re RA PER he eter eae en Wee glee em E Leer E aces 18 PS019915 1005 Table of Contents htt p ww xi npi an net ugagamBpmmuagdisqiaudtt Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification ZiLOG Data Memory so oie eve uere ete hig aie aiden ak bae ees hea fein boe p toe ette o e 19 Information Area sose Loses ee e eoo m SOR E URL e UR CIC BERT RR 19 Register File Address Map eeeeeeeeeeeehrh hh hh trn 21 Control Register Summary 0 cece cece cece cece eee cece hh hrs 26 Reset and STOP Mode Recovery ccc cccc ccc ccc cc ccccececcescscsseees 43 OVEIVIEW au uk EUR HR tian cae elas EE baad eg EGRE RA teal ERR ahaa aed 43 Reset Types us ebesecbewces me SU pe EP E qu E Pa e eg c erc qus 43 Reset SOUrCES c ves P Ree ee ees Law is RP Ee Waa ewe Ge eRe SE S 44 Power On Reset cscs ice ivaa RR e mE RERer ER IA E RR RES ER TO 44 Voltage Brown Out Reset llle 45 Watch Dog Timer Reset 0 0 0 cece eee eens 46 External Pin Reset 6 0 ore atin Va tata i qe e E eg Rn d 46 On Chip Debugger Initiated Reset 0 0 eee eee 47 STOP Mode Recovery 2 er peas wade lose suse knead lal buena bead 47 STOP Mode Recovery Using Watch Dog Timer Time Out 48 STOP Mode Recovery Using a GPIO Port Pin Transition HALT
161. O 1 and SPI configured as a Master 0 SS pin driven Low 0 1 SS pin driven High 1 This bit has no effect if SSIO 0 or SPI configured as a Slave SPI Diagnostic State Register The SPI Diagnostic State register Table 66 provides observability of internal state This is a read only register used for SPI diagnostics Table 66 SPI Diagnostic State Register SPIDST BITS 7 6 5 4 3 2 1 0 FIELD SCKEN TCKEN SPISTATE RESET 0 R W R ADDR F64H SCKEN Shift Clock Enable 0 The internal Shift Clock Enable signal is deasserted 1 The internal Shift Clock Enable signal is asserted shift register is updates on next sys tem clock TCKEN Transmit Clock Enable 0 The internal Transmit Clock Enable signal is deasserted 1 The internal Transmit Clock Enable signal is asserted When this is asserted the serial data out is updated on the next system clock MOSI or MISO SPISTATE SPI State Machine Defines the current state of the internal SPI State Machine PS019915 1005 Serial Peripheral Interface htt p ww xi npi an net LEE EB DRE EL EE EGET ET VE ut 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 138 ZiLOG SPI Baud Rate High and Low Byte Registers The SPI Baud Rate High and Low Byte registers Tables 67 and 68 combine to form a 16 bit reload value BRG 15 0 for the SPI Baud Rate Generator
162. Operating Modes PS019915 1005 The timers can be configured to operate in the following modes ONE SHOT Mode In ONE SHOT mode the timer counts up to the 16 bit Reload value stored in the Timer Reload High and Low Byte registers The timer input is the system clock Upon reaching the Reload value the timer generates an interrupt and the count value in the Timer High and Low Byte registers is reset to 0001H Then the timer is automatically disabled and stops counting Also if the Timer Output alternate function is enabled the Timer Output pin changes state for one system clock cycle from Low to High or from High to Low upon timer Reload If it is desired to have the Timer Output make a permanent state change upon One Shot time Timers htt p ww xi npi an net utu ee ee EU og 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 7T ZiLOG out first set the TPOL bit in the Timer Control 1 Register to the start value before begin ning ONE SHOT mode Then after starting the timer set TPOL to the opposite bit value The steps for configuring a timer for ONE SHOT mode and initiating the count are as fol lows 1 Write to the Timer Control 1 register to Disable the timer Configure the timer for ONE SHOT mode Set the prescale value If using the Timer Output alternate function set the initial output level High or Low 2 Write to the
163. P mode Refer to PS019915 1005 Watch Dog Timer htt p ww xi npi an net ugagamBpmmuagdisqiaudtt Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 93 ZiLOG the Reset and STOP Mode Recovery chapter for more information on STOP Mode Recovery If interrupts are enabled following completion of the STOP Mode Recovery the eZ8 CPU responds to the interrupt request by fetching the Watch Dog Timer interrupt vector and executing code from the vector address WDT Reset in Normal Operation If configured to generate a Reset when a time out occurs the Watch Dog Timer forces the device into the Reset state The WDT status bit in the Watch Dog Timer Control register is set to 1 Refer to the Reset and STOP Mode Recovery chapter for more information on Reset WDT Reset in STOP Mode If enabled in STOP mode and configured to generate a Reset when a time out occurs and the device is in STOP mode the Watch Dog Timer initiates a STOP Mode Recovery Both the WDT status bit and the STOP bit in the Watch Dog Timer Control register are set to 1 following WDT time out in STOP mode Refer to the Reset and STOP Mode Recovery chapter for more information Default operation is for the WDT and its RC oscillator to be enabled during STOP mode WDT RC Disable in STOP Mode To minimize power consumption in STOP Mode the WDT and its RC oscillator can be disabled in STOP mode The following s
164. PWM value 4 Write to the Timer Reload High and Low Byte registers to set the Reload value PWM period The Reload value must be greater than the PWM value 5 If desired enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers 6 Configure the associated GPIO port pin for the Timer Output alternate function 7 Write to the Timer Control 1 register to enable the timer and initiate counting The PWM period is given by the following equation PWM Period s Reload Value x Prescale System Clock Frequency Hz If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers the One Shot mode equation must be used to determine the first PWM time out period If TPOL is set to 0 the ratio of the PWM output High time to the total period is given by PWM Output High Time Ratio Reload Value S x 100 If TPOL is set to 1 the ratio of the PWM output High time to the total period is given by PWM Value PWM High Time Ratio 5 ne x1 WM Output High Time Ratio Reload Value i Capture Mode In CAPTURE mode the current timer count value is recorded when the desired external Timer Input transition occurs The Capture count value is written to the Timer PWM High and Low Byte Registers The timer input is the system clock The TPOL bit in the Timer Control 1 register determines if the Capture occurs on a rising edge or a falling edge of
165. Product Specification Vii Z8 Encore 64K Series Product Specification ZiLOG Operation sece rinie remet aiie pee ee tA ote rh E o RC E tace ee Ohaus 140 SDA and SCL Signals irais neien nos cira nia nion ete ce een 141 PC Interr pts 51e es re emet m E E E Grece d RR Se ae elg s 141 Software Control of I2C Transactions 0 0 eee eee 142 Start and Stop Conditions 0 eee cnet ees 143 Master Write and Read Transactions 0 0 0 ce eee eee eee 143 Address Only Transaction with a 7 bit Address 0 0 0 0 cece eee eee 144 Write Transaction with a 7 Bit Address 00 cece eee eee 145 Address Only Transaction with a 10 bit Address 000 000005 146 Write Transaction with a 10 Bit Address lseelslelleeeleeees 147 Read Transaction with a 7 Bit Address 0 0 0 0 cece ee ee eee 149 Read Transaction with a 10 Bit Address 0 0 cece eee ee 150 I2C Control Register Definitions 0 0 0 eee eee eee 152 I2C Data Register io rio ddan deal sian beg ae dda iac bed ea 152 PDE Status Register 2 a e Red a a ERR ae dr ve cl Ea o 153 DC Control Register osse e Uer DA ER pa PCR RE 155 I2C Baud Rate High and Low Byte Registers 0 00 00 000 156 I2C Diagnostic State Register llle 158 I2C Diagnostic Control Register 0 0 2 eee eee eA 160 Direct Memory Access Controller 0 cece cece cee eee cece cece eee eees 161 u
166. Product Specification Z ZiLOG on the multi node network The following three MULTIPROCESSOR modes are avail able in hardware Interrupt on all address bytes Interrupt on matched address bytes and correctly framed data bytes Interrupt only on correctly framed data bytes These modes are selected with MPMD 1 0 in the UART Control 1 Register For all MULTIPROCESSOR modes bit MPEN of the UART Control 1 Register must be set to 1 The first scheme is enabled by writing 01b to MPMD 1 0 In this mode all incoming address bytes cause an interrupt while data bytes never cause an interrupt The interrupt service routine must manually check the address byte that caused triggered the interrupt If it matches the UART address the software clears MPMD 0 At this point each new incoming byte interrupts the CPU The software is then responsible for determining the end of the frame It checks for end of frame by reading the MPRX bit of the UART Status 1 Register for each incoming byte If MPRX 1 a new frame has begun If the address of this new frame is different from the UART s address then set MPMD 0 to 1 causing the UART interrupts to go inactive until the next address byte If the new frame s address matches the UART s the data in the new frame is processed as well The second scheme is enabled by setting MPMD 1 0 to 10b and writing the UART s address into the UART Address Compare Register This mode introduces more hardware
167. ROM to determine when the EEPROM completes its inter nal write operation and is once again responding to C transactions If the slave does not Acknowledge the transaction can be repeated until the slave does Acknowledge S Slave Address W 0 A A P Figure 28 7 Bit Address Only Transaction Format The procedure for an address only transaction to a 7 bit addressed slave is as follows 1 2 3 4 PS019915 1005 htt p ww xi npi an net EE Software asserts the IEN bit in the I C Control register Software asserts the TXI bit of the C Control register to enable Transmit interrupts The I C interrupt asserts because the PC Data register is empty TDRE 1 Software responds to the TDRE bit by writing a 7 bit slave address plus write bit 20 to the C Data register As an alternative this could be a read operation instead of a write operation Software sets the START and STOP bits of the I C Control register and clears the TXI bit The I C Controller sends the START condition to the C slave The I C Controller loads the IC Shift register with the contents of the PC Data register Software polls the STOP bit of the I2C Control register Hardware deasserts the STOP bit when the address only transaction is completed Software checks the ACK bit of the I2C Status register If the slave acknowledged the ACK bit is 1 If the slave does not acknowledge the ACK bit is 0 The NCKI interrupt does
168. Rate High and Low Byte registers to set the desired baud rate 2 Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation 3 Write to the UART Control 1 register to enable Multiprocessor mode functions if desired 4 Write to the UART Control 0 register to Set the receive enable bit REN to enable the UART for data reception Enable parity if desired and if multiprocessor mode is not enabled and select either even or odd parity 5 Check the RDA bit in the UART Status 0 register to determine if the Receive Data register contains a valid data byte indicated by a 1 If RDA is set to 1 to indicate available data continue to Step 6 If the Receive Data register is empty indicated by a 0 continue to monitor the RDA bit awaiting reception of the valid data 6 Read data from the UART Receive Data register If operating in Multiprocessor 9 bit mode further actions may be required depending on the Multiprocessor Mode bits MPMD 1 0 7 Return to Step 5 to receive additional data UART HHHEHEHIGBUHBBHBHH 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 103 ZiLOG Receiving Data using the Interrupt Driven Method The UART Receiver interrupt indicates the availability of new data as well as error con ditions Follow these steps to configure the UART receiver for interrupt driven operation 1 Write to the UART B
169. Register DMAxCTL BITS 7 6 5 4 3 2 1 0 FIELD DEN DLE DDIR IRQEN WSEL RSS RESET 0 R W R W ADDR FBOH FB8H PS019915 1005 htt p ww xi npi an net Hg g dg p B m DEN DMAx Enable 0 DMAx is disabled and data transfer requests are disregarded 1 DMAx is enabled and initiates a data transfer upon receipt of a request from the trigger source DLE DMAx Loop Enable 0 DMAx reloads the original Start Address and is then disabled after the End Address data is transferred 1 DMAx after the End Address data is transferred reloads the original Start Address and continues operating DDIR DMAx Data Transfer Direction 0 Register File on chip peripheral control register 1 on chip peripheral control register Register File IRQEN DMAx Interrupt Enable 0 DMAx does not generate any interrupts 1 DMAx generates an interrupt when the End Address data is transferred WSEL Word Select 0 DMAx transfers a single byte per request 1 DMAx transfers a two byte word per request The address for the on chip peripheral control register must be an even address RSS Request Trigger Source Select The Request Trigger Source Select field determines the peripheral that can initiate a DMA transfer The corresponding interrupts do not need to be enabled within the Interrupt Con troller to initiate a DMA transfer However if the Request Trigger Source can enable or
170. S019915 1005 Register File Address Map htt p ww xi npi an net o uam ai ood L 010 62245566 13810019655 Control Register Summary Timer 0 High Byte TOH FOOH Read Write D7 D6ID5 ID4ID3 D2DD1 DO Timer 0 current count value 15 8 Timer 0 Low Byte TOL FO1H Read Write D7 D6 D5 D4ID3 D2DD1 DO L Timer 0 current count value 7 0 Timer 0 Reload High Byte TORH F02H Read Write D7 D6 D5 D4ID3 D2IDI DO _______ Timer 0 reload value 15 8 Timer 0 Reload Low Byte TORL HFO03 Read Write D7 D6 D5 D4ID3 D2DD1 DO Timer 0 reload value 7 0 Timer 0 PWM High Byte TOPWMH F04H Read Write D7 D6ID5 ID4ID3 D2DD1 DO L Timer 0 PWM value 15 8 Timer 0 Control 0 TOCTLO FO6H Read Write D7ID6 ID5D4D3D2IDI DO Reserved L Cascade Timer 0 Timer 0 Input signal is GPIO pin 1 Timer 0 Input signal is Timer 3 out Reserved PS019915 1005 Z8 Encore 64K Series Z8 Encore zZ 26 ZILO G Timer 0 Control 1 TOCTL1 F07H Read Write D7 D6 D5 D4 D3 D2 D1 D0 L Timer Mode 000 One Shot mode
171. SRP 240 Index htt p ww xi npi an net DEL EY EC BRE UE IMOO000000 010 62245566 13810019655 STOP 240 SUB 239 SUBX 239 SWAP 242 TCM 239 TCMX 239 TM 239 TMX 239 TRAP 241 watch dog timer refresh 240 XOR 241 XORX 241 instructions eZ8 classes of 238 interrupt control register 74 interrupt controller 5 62 architecture 62 interrupt assertion types 65 interrupt vectors and priority 65 operation 64 register definitions 66 software interrupt assertion 65 interrupt edge select register 72 interrupt port select register 73 interrupt request 0 register 66 interrupt request 1 register 67 interrupt request 2 register 68 interrupt return 241 interrupt vector listing 62 interrupts not acknowledge 141 receive 141 SPI 131 transmit 141 UART 106 introduction 1 IR 235 Ir 235 IrDA architecture 120 block diagram 120 control register definitions 124 operation 121 receiving data 122 transmitting data 121 PS019915 1005 Z8 Encore 64K Series Product Specification Z4 ZiLOG IRET 241 IRQO enable high and low bit registers 69 IRQI enable high and low bit registers 70 IRQ2 enable high and low bit registers 71 IRR 235 Irr 235 J JP 241 jump conditional relative and relative conditional 241 L LD 240 LDC 240 LDCI 239 240 LDE 240 LDEI 239 240 LDX 240 LEA 240 load 240 load constant 239 load constant to from program memory 240 load constant with auto incr
172. Second Opcode Map after IFH 0 0 0 e eee eee eet 256 40 Lead Plastic Dual Inline Package PDIP lusus 257 44 Lead Low Profile Quad Flat Package LQFP 258 44 Lead Plastic Lead Chip Carrier Package PLCC 259 List of Figures OR ee DE EET HS o a 010 62245566 13810019655 xii Z8 Encore 64K Series Product Specification ZiLOG Figure 65 64 Lead Low Profile Quad Flat Package LQFP 259 Figure 66 68 Lead Plastic Lead Chip Carrier Package PLCC 260 Figure 67 80 Lead Quad Flat Package QFP 0 0 0 cece cence eee ee 261 PS019915 1005 htt p ww xi npi an net UOUU IMoOo00 HOU List of Figures 010 62245566 13810019655 Z8 Encore 64K Series Product Specification List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 PS019915 1005 htt p ww xi npi an net ZiLOG Revision History of this Document 00 00 cece eee eee iii Z8 Encore 64K Series Part Selection Guide 004 2 Z8 Encore 64K Series Package Options
173. Sohn E eee ee Led eee ee 125 Architecte 2 douse eere Serre tut ee tube e wa ANG a ha eG deems hanes 125 Operatiot tac cena chi sieved seved ehedetetde i view sated red eeebesddpa d 126 SPI Signals 2222 22 99 909 4d rel esse Le pie E Pe as ERR PED E 127 SPI Clock Phase and Polarity Control 0 0 0 eee cece 128 Multi Master Operation 0 0 cee eee teens 130 Slave Operation 2 haa eed ae ad ee oe eeu ae dete sc e d 130 Error Detection eed eccetue Rr oe bie rem ha ee BA esee d RR e ae 131 SPI Interrupts ooie scai cenai hc cea bbe eed hee seeded eee heure Se 131 SPI Baud Rate Generator 2 knees 132 SPI Control Register Definitions 0 0 0 ccc eee eee nee 133 SPI Data Register csocsi icis she bbe e her ER Eu de bee ee 133 SPI Control Register 222i dee ee Ree e Rr ace de t rs oe 133 SPI Status Resister 1222229 adeciadsdaaadp eda eve ac eie eda stagunle 135 SPI Mode Register 2c ssnl sca hc n ee ERE EET A T nar 136 SPI Diagnostic State Register lleeeeeee es 137 SPI Baud Rate High and Low Byte Registers 0 0 0 0 eee eee eee 138 LC Controller 2uows owsoosas ea EPPREEPRERSQEARSEREREEYRRERGGRRREPPREFGSR CEU 139 OVERVIEW ARCET C T 139 Architecture zoe ele ek CREE UE ERSO DEA ERG ONU Quo ERU ARR end 140 PS019915 1005 Table of Contents htt p ww xi npi an net ugmmupBBuBum qintu ut oo 010 62245566 13810019655 Z8 Encore 64K Series
174. Standard Drive High Output Drive disabled Voi Low Level Output Voltage 0 6 V Lop 2 20mA VDD 3 3V High Drive High Output Drive enabled Ta 40 C to 70 C Vou2 High Level Output Voltage 2 4 V oq 20mA VDD 3 3V High Drive High Output Drive enabled Ta 40 C to 70 C Vor3 Low Level Output Voltage 0 6 V Lop 15mA VDD 3 3V High Drive High Output Drive enabled T4 70 C to 105 C Vou3 High Level Output Voltage 2 4 B x V oq 15mA VDD 3 3V High Drive High Output Drive enabled T4 70 C to 105 C VnAM RAM Data Retention 0 7 e V Ig Input Leakage Current 5 5 HA Vpp 3 6V Vin VDD or VSS ITL Tri State Leakage Current 5 5 LA Vpp 3 6V Cpap GPIO Port Pad Capacitance 8 0 pF Cxyn XIN Pad Capacitance 8 0 pF PS019915 1005 Electrical Characteristics htt p ww xi npi an net ugagamBpmmuagdisqiaudtt Ooo 010 62245566 13810019655 Table 105 DC Characteristics Continued Z8 Encore 64K Series Product Specification ZiLOG T4 40 C to 125 C Symbol Parameter Minimum Typical Maximum Units Conditions Cxour XOUT Pad Capacitance 9 5 pF Ipy Weak Pull up Current 30 100 350 uA Vpp 3 0 3 6 V Ippa Active Mode Supply Current 11 16 mA Vpp 3 6 V Fsysclk 20 MHz See Figures 43 and 44 12 Vpp 3 3 V oo pone unsere 5 9 11 mA Vpp 3 6 V Fsysclk 1
175. TAT 186 GPIO port A H address PXADDR 55 GPIO port A H alternate function sub registers 57 GPIO port A H control address PxCTL 56 GPIO port A H data direction sub registers 57 I2C baud rate high IZCBRH 157 158 160 I2C control I2ZCCTL 155 I2C data I2CDATA 153 I2C status 153 I2C status IZCSTAT 153 I2Cbaud rate low I2CBRL 157 mode SPI 136 OCD control 202 OCD status 204 SPI baud rate high byte SPIBRH 138 SPI baud rate low byte SPIBRL 138 SPI control SPICTL 134 SPI data SPIDATA 133 SPI status SPISTAT 135 status I2C 153 status SPI 135 JARTx baud rate high byte UxBRH 116 ARTx baud rate low byte UxBRL 116 JARTx Control 0 UxCTLO 112 115 JARTx control 1 UxCTL1 113 ARTXx receive data UxRXD 110 JARTx status 0 UxSTATO 110 JARTx status 1 UxSTAT1 112 JARTx transmit data UxTXD 109 watch dog timer control WDTCTL 94 watch dog timer reload high byte WDTH 96 watch dog timer reload low byte WDTL 97 watch dog timer reload upper byte WDTU 96 register file 17 register file address map 21 register pair 235 coccaccac PS019915 1005 Z8 Encore 64K Series Product Specification L ZiLOG register pointer 236 reset and STOP mode characteristics 43 and STOP mode recovery 43 carry flag 239 controller 5 sources 44 RET 241 return 241 return information 269 RL 242 RLC 242 rotate and shift instructions 242 rotate left 242 rotate left through carry 242 rotate
176. The eZ8 CPU is either stopped or looping on a BRK instruction HALT HALT Mode 0 The device is not in HALT mode 1 The device is in HALT mode RPEN Read Protect Option Bit Enabled 0 The Read Protect Option Bit is disabled 1 1 The Read Protect Option Bit is enabled 0 disabling many OCD commands Reserved These bits are always 0 On Chip Debugger IG1 D U DLE 010 62245566 13810019655 Z8 Encore 64K Series Product Specification ZiLOG On Chip Oscillator Overview The products in the 64K Series feature an on chip oscillator for use with external crystals with frequencies from 32KHz to 20MHz In addition the oscillator can support external RC networks with oscillation frequencies up to 4MHz or ceramic resonators with oscilla tion frequencies up to 20MHz This oscillator generates the primary system clock for the internal eZ8 CPU and the majority of the on chip peripherals Alternatively the Xqy input pin can also accept a CMOS level clock input signal 32KHz 20MHz If an external clock generator is used the Xgyr pin must be left unconnected When configured for use with crystal oscillators or external clock drivers the frequency of the signal on the Xqy input pin determines the frequency of the system clock that is no internal clock divider In RC operation the system clock is driven by a clock divider divide by 2 to ensure 5046 duty cycle Operating Mod
177. Unchanged by Reset R Read Only R W Read Write Reserved These Option Bits are reserved for future use and must always be 1 This setting is the default for unprogrammed erased Flash PS019915 1005 Option Bits htt p ww xi npi an net utu ee ee EU og 010 62245566 13810019655 On Chip Debugger Overview Z8 Encore 64K Series Product Specification The 64K Series products contain an integrated On Chip Debugger OCD that provides advanced debugging features including Reading and writing of the Register File Reading and writing of Program and Data Memory e Setting of Breakpoints e Execution of eZ8 CPU instructions Architecture The On Chip Debugger consists of four primary functional blocks transmitter receiver auto baud generator and debug controller Figure 36 illustrates the architecture of the On Transmitter Chip Debugger System Auto Baud Clock Detector Generator gt SET Xe DBG Pin 7 al Receiver Figure 36 On Chip Debugger Block Diagram PS019915 1005 htt p ww xi npi an net uu IG i uu 193 ZiLOG eZ8 CPU Control I Debug Controller o On Chip Debugger H 010 62245566 13810019655 Z8 Encore 64K Series Product Specification L ZiLOG Operation OCD Interface The On Chip Debugger u
178. WDTCTL register is set to 1 Figure 8 illustrates Power On Reset operation Refer to the Electrical Characteristics chapter for the POR threshold voltage Vpop VCC 8 3V Program amp Execution gt venous A A Primary Ec a Oscillator ATTI ULT l VCC 0 0V l Oscillator I l Start up l Internal RESET signal l I l X gt lt z POR XTAL Not to Scale counter delay counter delay Figure 8 Power On Reset Operation Voltage Brown Out Reset The devices in the 64K Series provide low Voltage Brown Out VBO protection The VBO circuit senses when the supply voltage drops to an unsafe level below the VBO threshold voltage and forces the device into the Reset state While the supply voltage remains below the Power On Reset voltage threshold Vpop the VBO block holds the device in the Reset state After the supply voltage again exceeds the Power On Reset voltage threshold the devices progress through a full System Reset sequence as described in the Power On Reset sec PS019915 1005 Reset and STOP Mode Recovery htt p ww xi npi an net LEE ERE DRE EL EE EGET ET VE Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 46 ZiLOG tion Following Power On Reset the POR status bit in the Watch Dog Timer Control WDTCTL register is set to 1 Figure 9 illustrates Voltage Brown Out operation Refer to the Electric
179. Z ZiLOG Port F Input Data PFIN FE6H Read Only D7 D6 D5 DA4ID3 D2ID1 DO Port F Input Data 7 0 Port F Output Data PFOUT FE7H Read Write D7ID6 D5 DA4ID3ID2 DI DO Port F Output Data 7 0 Port G Address PGADDR FESH Read Write D7 D6 DSIDAID3ID2IDI DO Port G Address 7 0 Selects Port Sub Registers 00H No function 01H Data direction 02H Alternate function 03H z Output control open drain 04H High drive enable 05H STOP mode recovery enable 06H FFH No function Port G Control PGCTL FE9H Read Write D7 D6 DSIDAID3ID2IDI DO Port G Control 7 0 Provides Access to Port Sub Registers Port G Input Data PGIN FEAH Read Only D7ID6 D5 DAID3ID2 IDI DO Port G Input Data 7 0 Port G Output Data PGOUT FEBH Read Write D7 D6 D5 D4 D3 D2 D1 D0 Port G Output Data 7 0 Control Register Summary htt p ww xi npi an net EE TENENT IMOQOO000000 010 62245566 13810019655 Port H Address PHADDR FECH Read Write D7 D6 D5 D4 D3 D2DD1 DO ___________ Port H Address 7 0 Selects Port Sub Registers 00H No function 01H Data direction 02H Alternate function 03H Output control open drain
180. able 120 provide timing information for UART pins for the case where the Clear To Send input signal CTS is not used for flow control In this example it is assumed that the Driver Enable polarity has been configured to be Active Low and is rep resented here by DE DE asserts after the UART Transmit Data Register has been written DE remains asserted for multiple characters as long as the Transmit Data register is writ ten with the next character before the current character has completed BE O NAO O oer Output T i To gt TXD de Ti eben p Output Start n oX Bi F Kar 7 Pay l End of Stop Bit s Figure 57 UART Timing without CTS Table 120 UART Timing without CTS Delay ns Parameter Abbreviation Minimum Maximum Ty DE Assertion to TXD Falling Edge Start Delay 1 Bit period 1 Bit period 1 XIN period T5 End of Stop Bit s to DE Deassertion Delay 1 XIN period 2 XIN period PS019915 1005 Electrical Characteristics htt p ww xi npi an net LEE EB DRE EL EE EGET ET VE Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 233 ZiLOG eZ CPU Instruction Set Assembly Language Programming Introduction The eZ8 CPU assembly language provides a means for writing an application program without having to be concerned with actual memory addresses or machine instruction for mats A pro
181. able the UART by clearing the REN and TEN bits in the UART Control 0 register to 0 Load the desired 16 bit count value into the UART Baud Rate High and Low Byte registers Enable the Baud Rate Generator timer function and associated interrupt by setting the BRGCTL bit in the UART Control 1 register to 1 When congured as a general purpose timer the UART BRG interrupt interval is calculated using the following equation UART BRG Interrupt Interval s System Clock Period s xBRG 15 0 PS019915 1005 htt p ww xi npi an net UART uu Uu LH 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z 116 ZiLOG Table 58 UART Baud Rate High Byte Register UxBRH BITS 7 6 5 4 2 1 0 FIELD BRH RESET 1 R W R W ADDR F46H and F4EH Table 59 UART Baud Rate Low Byte Register UxBRL BITS 7 6 5 4 3 2 1 0 FIELD BRL RESET 1 R W R W ADDR F47H and F4FH For a given UART data rate the integer baud rate divisor value is calculated using the fol lowing equation ma System Clock Frequenc an ART Baud Rate D lue BRG R System Clock Frequency Hz U aud Rate Divisor Value BRG ound 16 x UART Data Rate bits s The baud rate error relative to the desired baud rate is calculated using the following equa tion UART Baud Rate Error 100 x Actus
182. al Characteristics chapter for the VBO and POR threshold voltages Vygo and Vpop The Voltage Brown Out circuit can be either enabled or disabled during STOP mode Operation during STOP mode is set by the VBO AO Option Bit Refer to the Option Bits chapter for information on configuring VBO AO VCC 3 3V VCC 3 3V VPoR VvBo Program Voltage Program Execution Brownout Execution lt gt WDT Clock Primary KE RD HE MENS Oscillator Internal RESET Signal lt gt lt POR XTAL Counter Delay Counter Delay Figure 9 Voltage Brown Out Reset Operation Watch Dog Timer Reset If the device is in normal or HALT mode the Watch Dog Timer can initiate a System Reset at time out if the WDT RES Option Bit is set to 1 This capability is the default unprogrammed setting of the WDT RES Option Bit The WDT status bit in the WDT Con trol register is set to signify that the reset was initiated by the Watch Dog Timer External Pin Reset The RESET pin has a Schmitt triggered input an internal pull up an analog filter and a digital filter to reject noise Once the RESET pin is asserted for at least 4 system clock PS019915 1005 Reset and STOP Mode Recovery htt p ww xi npi an net LEE EB DRE EL EE EGET ET VE Ooo 010 62245566 138100196
183. and IrDA Physical Layer Specifica tion Version 1 3 compliant infrared transceivers Infrared communication provides secure reliable low cost point to point communication between PCs PDAs cell phones printers and other infrared enabled devices Architecture Figure 19 illustrates the architecture of the Infrared Endec System Clock ZiLOG ZHX1810 RxD RXD 4 at RXD TxD Infrared TXD UART E a Encoder Decoder TXD Baud Rate Endec Infrared Clock j pU Med Transceiver EN Interrupt y o Data Signal Address Figure 19 Infrared Data Communication System Block Diagram PS019915 1005 Infrared Encoder Decoder 010 62245566 13810019655 htt p ww xi npi an net u Donnan Og Z8 Encore 64K Series Product Specification 121 ZiLOG Operation When the Infrared Endec is enabled the transmit data from the associated on chip UART is encoded as digital signals in accordance with the IrDA standard and output to the infra red transceiver via the TXD pin Likewise data received from the infrared transceiver is passed to the Infrared Endec via the RXD pin decoded by the Infrared Endec and then passed to the UART Communication is half duplex which means simultaneous data transmission and reception is not allowed The baud rate is set by the UART s Baud Rate Generator and supports IrDA standard baud
184. and clears the STOP and NCKI bits The transaction is complete ignore the following steps 17 The C Controller shifts the data out by the SDA signal After the first bit is sent the Transmit interrupt is asserted 18 If more bytes remain to be sent return to step 14 19 If the last byte is currently being sent software sets the STOP bit of the PC Control register or START bit to initiate a new transaction In the STOP case software also clears the TXI bit of the C Control register at the same time 20 The IC Controller completes transmission of the last data byte on the SDA signal 21 The slave may either Acknowledge or Not Acknowledge the last byte Because either the STOP or START bit is already set the NCKI interrupt does not occur 22 The C Controller sends the STOP or RESTART condition to the IC bus and clears the STOP or START bit Read Transaction with a 7 Bit Address Figure 32 illustrates the data transfer format for a read operation to a 7 bit addressed slave The shaded regions indicate data transferred from the FC Controller to slaves and unshaded regions indicate data transferred from the slaves to the IC Controller S Slave Address R 1 A Data A Data A P S Figure 32 Receive Data Transfer Format for a 7 Bit Addressed Slave The procedure for a read operation to a 7 bit addressed slave is as follows 1 Software writes the I C Data register with a 7 bit slave address plus the read bit 21 2 Software
185. annot be unprotected by user code The Flash Sector Protect register is cleared after reset and any previously written protection values is lost User code must write this register in their initialization routine if they want to enable sector protection The Flash Sector Protect register shares its Register File address with the Page Select reg ister The Flash Sector Protect register is accessed by writing the Flash Control register with 5EH Once the Flash Sector Protect register is selected it can be accessed at the Page Select Register address When user code writes the Flash Sector Protect register bits can only be set to 1 Thus sectors can be protected but not unprotected via register write operations Writing a value other than 5EH to the Flash Control register de selects the Flash Sector Protect register and re enables access to the Page Select register The steps to setup the Flash Sector Protect register from user code are 1 Write 00H to the Flash Control register to reset the Flash Controller 2 Write 5EH to the Flash Control register to select the Flash Sector Protect register 3 Read and or write the Flash Sector Protect register which is now at Register File address FF 9H 4 Write 00H to the Flash Control register to return the Flash Controller to its reset state Flash Write Protection Option Bit The Flash Write Protect option bit can be enabled to block all program and erase opera tions from user code Refer to the O
186. ansmit Enable This bit enables or disables the transmitter The enable is also controlled by the CTS signal and the CTSE bit If the CTS signal is low and the CTSE bit is 1 the transmitter is PS019915 1005 htt p ww xi npi an net UART D U Uu 010 62245566 13810019655 UU Z8 Encore 64K Series Product Specification Zi ZiLOG enabled 0 Transmitter disabled 1 Transmitter enabled REN Receive Enable This bit enables or disables the receiver 0 Receiver disabled 1 Receiver enabled CTSE CTS Enable 0 The CTS signal has no effect on the transmitter 1 The UART recognizes the CTS signal as an enable control from the transmitter PEN Parity Enable This bit enables or disables parity Even or odd is determined by the PSEL bit It is over ridden by the MPEN bit 0 Parity is disabled 1 The transmitter sends data with an additional parity bit and the receiver receives an additional parity bit PSEL Parity Select 0 Even parity is transmitted and expected on all received data 1 Odd parity is transmitted and expected on all received data SBRK Send Break This bit pauses or breaks data transmission Sending a break interrupts any transmission in progress so ensure that the transmitter has finished sending data before setting this bit 0 No break is sent 1 The output of the transmitter is zero STOP Stop Bit
187. are and PWM modes Only 3 timers Timers 0 2 are available in the 44 pin packages Interrupt Controller The 64K Series products support up to 24 interrupts These interrupts consist of 12 inter nal and 12 general purpose I O pins The interrupts have 3 levels of programmable inter rupt priority Reset Controller The Z8 Encore can be reset using the RESET pin power on reset Watch Dog Timer WDT STOP mode exit or Voltage Brown Out VBO warning signal On Chip Debugger The Z8 Encore features an integrated On Chip Debugger OCD The OCD provides a rich set of debugging capabilities such as reading and writing registers programming the Flash setting breakpoints and executing code A single pin interface provides communi cation to the OCD DMA Controller The 64K Series features three channels of DMA Two of the channels are for register RAM to and from I O operations The third channel automatically controls the transfer of data from the ADC to the memory PS019915 1005 Introduction HHHEHEHIGBUHBBHBHH 010 62245566 13810019655 htt p ww xi npi an net EE Z8 Encore 64K Series Product Specification ZiLOG Signal and Pin Descriptions Overview The Z8 Encore 64K Series products are available in a variety of packages styles and pin configurations This chapter describes the signals and available pin configurations for each of the package styles For informatio
188. are wants to stop the CPU on the BRK instruction it is looping on software should not set the DBGMODE bit of the OCDCTL register The CPU may have vectored to and be in the middle of an interrupt service routine when this bit gets set Instead software must clear the BRKLP bit This action allows the CPU to PS019915 1005 On Chip Debugger htt p ww xi npi an net DOT 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 198 ZiLOG finish the interrupt service routine it may be in and return the BRK instruction When the CPU returns to the BRK instruction it was previously looping on it automatically sets the DBGMODE bit and enter DEBUG mode Software detects that the majority of the OCD commands are still disabled when the eZ8 CPU is looping on a BRK instruction The eZ8 CPU must be stopped and the part must be in DEBUG mode before these commands can be issued Breakpoints in Flash Memory The BRK instruction is opcode 00H which corresponds to the fully programmed state of a byte in Flash memory To implement a Breakpoint write 00H to the desired address over writing the current instruction To remove a Breakpoint the corresponding page of Flash memory must be erased and reprogrammed with the original data On Chip Debugger Commands The host communicates to the On Chip Debugger by sending OCD commands using the DBG interface During normal operation only a subset of the OC
189. at Table 61 lists the SPI Clock Phase and Polarity Operation parameters The clock phase bit PHASE selects one of two fundamen tally different transfer formats For proper data transmission the clock phase and polarity must be identical for the SPI Master and the SPI Slave The Master always places data on the MOSI line a half cycle before the receive clock edge SCK signal in order for the Slave to latch the data Table 61 SPI Clock Phase PHASE and Clock Polarity CLKPOL Operation SCK Transmit SCK Receive SCK Idle PHASE CLKPOL Edge Edge State 0 0 Falling Rising Low 0 1 Rising Falling High 1 0 Rising Falling Low 1 1 Falling Rising High PS019915 1005 Serial Peripheral Interface htt p ww xi npi an net ugagamBpmmuagdisqiaudtt Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 129 ZiLOG Transfer Format PHASE Equals Zero Figure 25 illustrates the timing diagram for an SPI transfer in which PHASE is cleared to 0 The two SCK waveforms show polarity with CLKPOL reset to 0 and with CLKPOL set to one The diagram may be interpreted as either a Master or Slave timing diagram because the SCK Master In Slave Out MISO and Master Out Slave In MOSI pins are directly connected between the Master and the Slave SCK CLKPOL 0 SCK CLKPOL 1 MOSI MISO Figure 25 SPI Timing When PHASE is 0 Transfer Format PHAS
190. atch Dog Timer 010 62245566 13810019655 UART Overview Z8 Encore 64K Series Product Specification Z ZiLOG The Universal Asynchronous Receiver Transmitter UART is a full duplex communica tion channel capable of handling asynchronous data transfers The UART uses a single 8 bit data mode with selectable parity Features of the UART include Architecture 8 bit asynchronous data transfer Selectable even and odd parity generation and checking Option of one or two Stop bits Separate transmit and receive interrupts Framing parity overrun and break detection Separate transmit and receive enables 16 bit Baud Rate Generator BRG Selectable Multiprocessor 9 bit mode with three configurable interrupt schemes Baud Rate Generator timer mode Driver Enable output for external bus transceivers The UART consists of three primary functional blocks transmitter receiver and baud rate generator The UART s transmitter and receiver function independently but employ the same baud rate and data format Figure 13 illustrates the UART architecture PS019915 1005 htt p ww xi npi an net EE UART HHHEHEHIGBUHBBHBHH 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z ZiLOG RXD Parity Checker gt Receive Shifter gt Receiver Control with address compare v Receive Data Register
191. ates a block diagram of the interrupt controller High Port Interrupts Priority Vector Priority Mux IRQ Request Medium Priority Internal Interrupts Low Priority Interrupt Request Latches and Control Figure 11 Interrupt Controller Block Diagram Operation Master Interrupt Enable The master interrupt enable bit IRQE in the Interrupt Control register globally enables and disables interrupts Interrupts are globally enabled by any of the following actions e Executing an EI Enable Interrupt instruction Executing an IRET Return from Interrupt instruction e Writing a 1 to the IRQE bit in the Interrupt Control register Interrupts are globally disabled by any of the following actions e Execution of a DI Disable Interrupt instruction e eZ8 CPU acknowledgement of an interrupt service request from the interrupt controller e Writing a 0 to the IRQE bit in the Interrupt Control register e Reset PS019915 1005 Interrupt Controller htt p ww xi npi an net LEE EB DRE EL EE EGET ET VE Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z ZiLOG Executing a Trap instruction e Illegal Instruction trap Interrupt Vectors and Priority The interrupt controller supports three levels of interrupt priority Level 3 is the highest priority Level 2 is the second highest priority and Level 1 is the
192. aud Rate High and Low Byte registers to set the desired baud rate 2 Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation Execute a DI instruction to disable interrupts 4 Write to the Interrupt control registers to enable the UART Receiver interrupt and set the desired priority 5 Clear the UART Receiver interrupt in the applicable Interrupt Request register 6 Write to the UART Control 1 Register to enable Multiprocessor 9 bit mode functions if desired Set the MULTIPROCESSOR Mode Select MPEN to Enable Multiprocessor mode Set the MULTIPROCESSOR Mode Bits MPMD 1 0 to select the desired address matching scheme Configure the UART to interrupt on received data and errors or errors only interrupt on errors only is unlikely to be useful for Z8 Encore devices without a DMA block 7 Write the device address to the Address Compare Register automatic multiprocessor modes only 8 Write to the UART Control 0 register to Set the receive enable bit REN to enable the UART for data reception Enable parity if desired and if multiprocessor mode is not enabled and select either even or odd parity 9 Execute an EI instruction to enable interrupts The UART is now configured for interrupt driven data reception When the UART Receiver interrupt is detected the associated interrupt service routine ISR performs the following 1 Check the UART Status 0 register to dete
193. bits control the direction of the associated port pin Port Alternate Function opera tion overrides the Data Direction register setting 0 Output Data in the Port A H Output Data register is driven onto the port pin 2 Input The port pin is sampled and the value written into the Port A H Input Data Reg ister The output driver is tri stated Port A H Alternate Function Sub Registers The Port A H Alternate Function sub register Table 17 is accessed through the Port A H Control register by writing 02H to the Port A H Address register The Port A H Alter nate Function sub registers select the alternate functions for the selected pins Refer to the GPIO Alternate Functions section to determine the alternate function associated with each port pin AN Caution Do not enable alternate function for GPIO port pins which do not have an associated alternate function Failure to follow this guideline may result in unpredictable operation Table 17 Port A H Alternate Function Sub Registers BITS 7 6 5 4 3 2 1 0 FIELD AF7 AF6 AF5 AF4 AF3 AF2 AFI AFO RESET o R W R W ADDR If 02H in Port A H Address Register accessible through Port A H Control Register PS019915 1005 htt p ww xi npi an net General Purpose I O D U Uu LH 010 62245566 13810019655 Z8 Encore 64K Series Product Specification L s ZiLOG AF 7 0
194. ble 0 DMAI does not generate interrupts 1 DMAI generates an interrupt when End Address data is transferred LL DMA Data Transfer Direction 0 Register File to peripheral registers 1 Peripheral registers to Register File 0 2 DMA disables after End Address 1 2 DMA reloads Start Address after End Address and continues to run Control Register Summary ugggmniu IMOO000000 010 62245566 13810019655 htt p ww xi npi an net DMA1 I O Address DMAIIO FB9H Read Write D7ID6 ID5 D4D3DD2DDI DO DMAI Peripheral Register Address Low byte of on chip peripheral control registers on Register File page FH DMA Address High Nibble DMAIH FBAH Read Write D7 D6 D5 D4ID3D2ID1 DO DMAI Start Address 11 8 DMAI End Address 11 8 DMAI Start Current Address Low Byte DMAISTART FBBH Read Write D7 D6 D5 D4ID3D2ID1 DO DMAI Start Address 7 0 DMAI End Address Low Byte DMAIEND FBCH Read Write D7 D6 D5 D4ID3 D2 D1 DO DMAI End Address 7 0 DMA ADC Address DMAA ADDR FBDH Read Write D7ID6 ID5D4D3D2DDI DO L Reserved DMA ADC Address PS019915 1005 Z8 Encore 64K Series Z8 Encore ZiLOG DMA_ADC Control DMAACTL FBEH Read Write D7 D6 DSIDA4D3 D2ID1 DO
195. ble 82 points to a block of the Register File to store ADC conversion values as illustrated in Table 81 This register contains the seven most significant bits of the 12 bit Register File addresses The five least significant bits are cal culated from the ADC Analog Input number 5 bit base address is equal to twice the ADC Analog Input number The 10 bit ADC conversion data is stored as two bytes with the most significant byte of the ADC data stored at the even numbered Register File address Table 81 provides an example of the Register File addresses if the DMA ADC Address register contains the value 72H Table 81 DMA ADC Register File Address Example ADC Analog Input Register File Address Hex 0 720H 721H 1 722H 723H 724H 725H 726H 727H 728H 729H 72AH 72BH 72CH 72DH 72EH 72FH 730H 731H o NIAI A UIN Direct Memory Access Controller 010 62245566 13810019655 Table 82 DMA ADC Address Register DMAA ADDR Table 81 DMA ADC Register File Address Example ADC Analog Input Register File Address Hex 9 732H 733H 10 734H 735H 11 736H 737H DMAA_ADDR set to 72H Z8 Encore 64K Series Product Specification L ZiLOG BITS 7 6 5 4 2 1 0 FIELD DMAA_ADDR Reserved RESET X R W R W ADDR FBDH DMAA_ADDR DMA_ADC Address These bits specify the seven most significant
196. ble parity if desired and if multiprocessor mode is not enabled and select either even or odd parity Set or clear the CTSE bit to enable or disable control from the remote receiver via the CTS pin PS019915 1005 UART htt p ww xi npi an net DOT 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z 102 ZiLOG 8 Execute an EI instruction to enable interrupts The UART is now configured for interrupt driven data transmission Because the UART Transmit Data register is empty an interrupt is generated immediately When the UART Transmit interrupt is detected the associated interrupt service routine ISR performs the following 1 Write the UART Control 1 register to select the outgoing address bit Set the MULTIPROCESSOR Bit Transmitter MPBT if sending an address byte clear it if sending a data byte 2 Write the data byte to the UART Transmit Data register The transmitter automatically transfers the data to the Transmit Shift register and transmits the data Clear the UART Transmit interrupt bit in the applicable Interrupt Request register 4 Execute the IRET instruction to return from the interrupt service routine and wait for the Transmit Data register to again become empty Receiving Data using the Polled Method PS019915 1005 htt p ww xi npi an net EE Follow these steps to configure the UART for polled data reception 1 Write to the UART Baud
197. cation Encore 64K Series 209 ZiLOG Stresses greater than those listed in Table 104 may cause permanent damage to the device These ratings are stress ratings only Operation of the device at any condition outside those indicated in the operational sections of these specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability For improved reliability unused inputs must be tied to one of the supply voltages Vpp or Vss Table 104 Absolute Maximum Ratings Parameter Minimum Maximum Units Notes Ambient temperature under bias 40 125 C Storage temperature 65 150 C Voltage on any pin with respect to Ves 0 3 5 5 V 1 Voltage on Vpp pin with respect to V ss 0 3 43 6 V Maximum current on input and or inactive output pin 5 5 uA Maximum output current from active output pin 25 25 mA 80 Pin QFP Maximum Ratings at 40 C to 70 C Total power dissipation 550 mW Maximum current into Vpp or out of Vss 150 mA 80 Pin QFP Maximum Ratings at 70 C to 125 C Total power dissipation 200 mW Maximum current into Vpp or out of Vss 56 mA 68 Pin PLCC Maximum Ratings at 40 C to 70 C Total power dissipation 1000 mW Maximum current into Vpp or out of Vss 275 mA 68 Pin PLCC Maximum Ratings at 70 C to 125 C Notes 1 This voltage applies to all pins except the following VDD AVDD pins supporting analog in
198. cause of the open drain nature of the DBG pin the host can send a Serial Break to the OCD even if the OCD is transmitting a character Breakpoints Execution Breakpoints are generated using the BRK instruction opcode 00H When the eZ8 CPU decodes a BRK instruction it signals the On Chip Debugger If Breakpoints are enabled the OCD idles the eZ8 CPU and enters DEBUG mode If Breakpoints are not enabled the OCD ignores the BRK signal and the BRK instruction operates as an NOP If breakpoints are enabled the OCD can be configured to automatically enter DEBUG mode or to loop on the break instruction If the OCD is configured to loop on the BRK instruction then the CPU is still enabled to service DMA and interrupt requests The loop on BRK instruction can be used to service interrupts in the background For interrupts to be serviced in the background there cannot be any breakpoints in the inter rupt service routine Otherwise the CPU stops on the breakpoint in the interrupt routine For interrupts to be serviced in the background interrupts must also be enabled Debug ging software should not automatically enable interrupts when using this feature since interrupts are typically disabled during critical sections of code where interrupts should not occur such as adjusting the stack pointer or modifying shared data Software can poll the IDLE bit of the OCDSTAT register to determine if the OCD is loop ing on a BRK instruction When softw
199. ce state if the Slave is not selected When the SPI is not enabled this signal is in a high impedance state Master Out Slave In The Master Out Slave In MOSI pin is configured as an output in a Master device and as an input in a Slave device It is one of the two lines that transfer serial data with the most significant bit sent first When the SPI is not enabled this signal is in a high impedance state Serial Clock The Serial Clock SCK synchronizes data movement both in and out of the device through its MOSI and MISO pins In MASTER mode the SPI s Baud Rate Generator cre ates the serial clock The Master drives the serial clock out its own SCK pin to the Slave s SCK pin When the SPI is configured as a Slave the SCK pin is an input and the clock sig nal from the Master synchronizes the data transfer between the Master and Slave devices Slave devices ignore the SCK signal unless the SS pin is asserted When configured as a slave the SPI block requires a minimum SCK period of greater than or equal to 8 times the system XIN clock period PS019915 1005 Serial Peripheral Interface htt p ww xi npi an net DOT 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Zi ZiLOG The Master and Slave are each capable of exchanging a character of data during a sequence of NUMBITS clock cycles refer to NUMBITS field in the SPIMODE register In both Master and Slave SPI de
200. ci m 161 Sisccut MEME 161 DMAO and DMAI Operation 0 0 0 eee III 161 Configuring DMAO and DMAI for Data Transfer 0 00 162 DMA_ADC Operation oi coepere pA a RR en Re 162 Configuring DMA ADC for Data Transfer 0 0 0 0 ee eee eee eee 163 DMA Control Register Definitions llle 163 DMAX Control Register sc vices eae b ke ee oe Ee Ropa wp oh ere epe 163 DMAx I O Address Register llle 165 DMAx Address High Nibble Register 00 0 cee eee ee eee 165 DMAx Start Current Address Low Byte Register 00 166 DMAx End Address Low Byte Register 0 0 0 166 DMA ADC Address Register eleleeeeeee eens 167 DMA ADC Control Register l sleeeeeeeee eens 168 DMA Status Register 2 0 0 ee 169 Analog to Digital Converter ceeeeeeeeeeeeeee e hh hh tha 171 cl Aq M 171 Architecture i ellc c ke lA e eR AR Eee ES ERR ERE ER eee cea bbe cea 171 Operation uus ceder bee Desa ues once eq d Dolce danke ate 172 Automatic Power Down sseseeeeee ehh ran 172 Single Shot Conversion 0 cece eee rennene 173 PS019915 1005 Table of Contents htt p ww xi npi an net DOT 010 62245566 13810019655 Z8 Encore 64K Series Product Specification ZiLOG Continuous Conversion lisse s 173 DMA Control of the ADC leeeeeeleeeeeee eens 174 ADC Control Register Definitions
201. clock cycles Period Continuous Conversion 256 cycles System clock cycles Period Rs Analog Source Impedance 150 Q Recommended Zin Input Impedance 150 kQ VREF External Reference Voltage AVDD V AVDD lt VDD When using an external reference voltage decoupling capacitance should be placed from VREF to AVSS IREF Current draw into VREF pin 25 0 40 0 pA when driving with external source PS019915 1005 Electrical Characteristics htt p ww xi npi an net LEE EB DRE EL EE EGET ET VE Ooo 010 62245566 13810019655 0 9 0 8 3 dB 0 6 0 5 O08 0 4 Frequency Response 0 3 0 2 0 1 Z8 Encore 64K Series Product Specification Zi ZiLOG ADC Magnitude Transfer Function Linear Scale 10 15 Frequency kHz Figure 49 Analog to Digital Converter Frequency Response PS019915 1005 htt p ww xi npi an net D U Uu UU 25 30 Electrical Characteristics 010 62245566 13810019655 Z8 Encore 64K Series Product Specification ZiLOG AC Characteristics The section provides information on the AC characteristics and timing All AC timing information assumes a standard load of 50pF on all outputs Table 112 lists the 64K Series AC characteristics and timing Table 112 AC Characteristics
202. data bits least significant bit first and 1 Stop bit Figure 39 DO D1 D2 D3 D4 D5 D6 D7 STOP Figure 39 OCD Data Format OCD Auto Baud Detector Generator To run over a range of baud rates bits per second with various system clock frequencies the On Chip Debugger has an Auto Baud Detector Generator After a reset the OCD is idle until it receives data The OCD requires that the first character sent from the host is the character 80H The character 80H has eight continuous bits Low one Start bit plus 7 data bits The Auto Baud Detector measures this period and sets the OCD Baud Rate Generator accordingly The Auto Baud Detector Generator is clocked by the system clock The minimum baud rate is the system clock frequency divided by 512 For optimal operation the maximum recommended baud rate is the system clock frequency divided by 8 The theoretical maxi mum baud rate is the system clock frequency divided by 4 This theoretical maximum is possible for low noise designs with clean signals Table 99 lists minimum and recom mended maximum baud rates for sample crystal frequencies Table 99 OCD Baud Rate Limits System Clock Frequency Recommended Maximum Baud Rate Minimum Baud Rate MHz kbits s kbits s 20 0 2500 39 1 1 0 125 0 1 96 0 032768 32KHz 4 096 0 064 If the OCD receives a Serial Break nine or more continuous bits Low the Auto Baud Detector Generator resets The Auto Baud D
203. ding the UART Receive Data regis ter clears this bit 0 No parity error occurred 1 A parity error occurred OE Overrun Error This bit indicates that an overrun error has occurred An overrun occurs when new data is received and the UART Receive Data register has not been read If the RDA bit is reset to 0 then reading the UART Receive Data register clears this bit 0 No overrun error occurred 1 An overrun error occurred FE Framing Error This bit indicates that a framing error no Stop bit following data reception was detected Reading the UART Receive Data register clears this bit 0 No framing error occurred 1 A framing error occurred BRKD Break Detect This bit indicates that a break occurred If the data bits parity multiprocessor bit and Stop bit s are all zeros then this bit is set to 1 Reading the UART Receive Data register clears this bit 0 No break occurred 1 A break occurred TDRE Transmitter Data Register Empty This bit indicates that the UART Transmit Data register is empty and ready for additional data Writing to the UART Transmit Data register resets this bit 0 Do not write to the UART Transmit Data register 1 The UART Transmit Data register is ready to receive an additional byte to be transmit ted TXE Transmitter Empty This bit indicates that the transmit shift register is empty and character transmission is fin ished 0 Data is currently transmitting 1
204. dressing LDX dst src Load using Extended Addressing LEA dst X src Load Effective Address POP dst Pop POPX dst Pop using Extended Addressing PUSH src Push PUSHX src Push using Extended Addressing PS019915 1005 eZ8 CPU Instruction Set htt p ww xi npi an net LEE EB DRE EL EE EGET ET VE Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification L a ZiLOG Table 129 Logical Instructions Mnemonic Operands Instruction AND dst src Logical AND ANDX dst src Logical AND using Extended Addressing COM dst Complement OR dst src Logical OR ORX dst src Logical OR using Extended Addressing XOR dst src Logical Exclusive OR XORX dst src Logical Exclusive OR using Extended Addressing Table 130 Program Control Instructions eZ8 CPU Instruction Set Mnemonic Operands Instruction BRK On Chip Debugger Break BTJ p bit src DA Bit Test and Jump BTJNZ bit src DA Bit Test and Jump if Non Zero BTJZ bit src DA Bit Test and Jump if Zero CALL dst Call Procedure DJNZ dst src RA Decrement and Jump Non Zero IRET Interrupt Return JP dst Jump JP cc dst Jump Conditional JR DA Jump Relative JR cc DA Jump Relative Conditional RET Return TRAP vector Software Trap PS019915 1005 htt p ww xi npi an net Oo HARRENA UU 010 62245566 13810019655 Z8
205. ds lost interrupt requests ANDX IRQO MASK Software Interrupt Assertion Program code can generate interrupts directly Writing a 1 to the desired bit in the Interrupt Request register triggers an interrupt assuming that interrupt is enabled When the inter rupt request is acknowledged by the eZ8 CPU the bit in the Interrupt Request register is automatically cleared to 0 PS019915 1005 Interrupt Controller HHHEHEHIGBUHBBHBHH 010 62245566 13810019655 htt p ww xi npi an net EE Z8 Encore 64K Series Product Specification Z ZiLOG The following style of coding to generate software interrupts by setting bits in the Interrupt Request registers is NOT recommended All incoming interrupts that are received between execution of the first LDX command and the last LDX command are lost Poor coding style that can result in lost interrupt requests LDX r0 IRQO OR r0 MASK LDX IRQO rO To avoid missing interrupts the following style of coding to set bits in the Interrupt Request registers is recommended Good coding style that avoids lost interrupt requests ORX IRQO MASK Interrupt Control Register Definitions For all interrupts other than the Watch Dog Timer interrupt the interrupt control registers enable individual interrupts set interrupt priorities and indicate interrupt requests Interrupt Request 0 Register The Interrupt Request 0 IRQO register Table 24 stores t
206. duct Specification 229 ZiLOG SPI Slave Mode Timing Figure 54 and Table 117 provide timing information for the SPI slave mode pins Timing is shown with SCK rising edge used to source MISO output data SCK falling edge used to sample MOSI input data SCK T1 gt Output i T2 T3 pose Input T4 i FH ss Input l Figure 54 SPI Slave Mode Timing Table 117 SPI Slave Mode Timing Delay ns Parameter Abbreviation Min Max SPI Slave Ty SCK transmit edge to MISO output Valid Delay 2 Xin 3 Xin period period 20 nsec T5 MOSI input to SCK receive edge Setup Time 0 T3 MOSI input to SCK receive edge Hold Time 3 Xin period T4 SS input assertion to SCK setup 1 Xin period PS019915 1005 Electrical Characteristics htt p ww xi npi an net OR ee DE EET HS o a 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Zi ZiLOG PC Timing Figure 55 and Table 118 provide timing information for PC pins SCL 7 Output T1 l SDA P4 Output Data Output l T2 qar PES Input j j Figure 55 PC Timing Table 118 C Timing Delay ns Parameter Abbreviation Minimum Maximum PC T SCL Fall to SDA output delay SCL period 4 T5 SDA Input to SCL rising edge Setup Time 0 T5 SDA Input to SCL falling edge Hold T
207. e The operating characteristics of the 64K Series devices in DEBUG mode are The eZ8 CPU fetch unit stops idling the eZ8 CPU unless directed by the OCD to execute specific instructions The system clock operates unless in STOP mode e All enabled on chip peripherals operate unless in STOP mode e Automatically exits HALT mode Constantly refreshes the Watch Dog Timer if enabled Entering Debug Mode The device enters DEBUG mode following any of the following operations e Writing the DBGMODE bit in the OCD Control Register to 1 using the OCD interface e eZ8 CPU execution of a BRK Breakpoint instruction when enabled e Ifthe DBG pin is Low when the device exits Reset the On Chip Debugger automatically puts the device into DEBUG mode Exiting Debug Mode The device exits DEBUG mode following any of the following operations Clearing the DBGMODE bit in the OCD Control Register to 0 Power on reset e Voltage Brown Out reset PS019915 1005 On Chip Debugger htt p ww xi npi an net EE HHHEHEHIGBUHBBHBHH 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 196 ZiLOG e Asserting the RESET pin Low to initiate a Reset Driving the DBG pin Low while the device is in STOP mode initiates a System Reset OCD Data Format START The OCD interface uses the asynchronous data format defined for RS 232 Each character is transmitted as 1 Start bit 8
208. e ADC clock rate one fourth the system clock rate The ADC provides alias free conversion for frequen cies up to one half the ADC clock rate Thus the sigma delta ADC exhibits high noise immunity making it ideal for embedded applications In addition monotonicity no miss ing codes is guaranteed by design Operation Automatic Power Down If the ADC is idle no conversions in progress for 160 consecutive system clock cycles portions of the ADC are automatically powered down From this power down state the ADC requires 40 system clock cycles to power up The ADC powers up when a conver sion is requested using the ADC Control register PS019915 1005 htt p ww xi npi an net LI E Hu Uu UU Analog to Digital Converter 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 173 ZiLOG Single Shot Conversion When configured for single shot conversion the ADC performs a single analog to digital conversion on the selected analog input channel After completion of the conversion the ADC shuts down The steps for setting up the ADC and initiating a single shot conversion are as follows 1 Enable the desired analog inputs by configuring the general purpose I O pins for alternate function This configuration disables the digital input and output drivers 2 Write to the ADC Control register to configure the ADC and begin the conversion The bit fields i
209. e Z8 Encore 64K Series contains 16 KB to 64 KB of on chip Flash in the Program Memory address space depending upon the device Reading from Program Memory addresses outside the avail able Flash memory addresses returns FFH Writing to these unimplemented Program Memory addresses produces no effect Table 5 describes the Program Memory Maps for the 64K Series products Table 5 Z8 Encore 64K Series Program Memory Maps Program Memory Address Hex Function Z8F162x Products 0000 0001 Option Bits 0002 0003 Reset Vector 0004 0005 WDT Interrupt Vector 0006 0007 Illegal Instruction Trap 0008 0037 Interrupt Vectors 0038 3FFF Program Memory Z8F242x Products 0000 0001 Option Bits 0002 0003 Reset Vector 0004 0005 WDT Interrupt Vector 0006 0007 Illegal Instruction Trap 0008 0037 Interrupt Vectors 0038 5FFF Program Memory Z8F322x Products 0000 0001 Option Bits 0002 0003 Reset Vector 0004 0005 WDT Interrupt Vector 0006 0007 Illegal Instruction Trap 0008 0037 Interrupt Vectors 0038 7FFF Program Memory See Table 23 on page 63 for a list of the interrupt vectors PS019915 1005 Address Space htt p ww xi npi an net EE uu Iq10U U UU 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z ZiLOG Table 5 Z8 Encore 64K Series Program Memory Maps Continued
210. e conversion restarts This bit remains 1 until the conversion is complete Reserved Must be 0 VREF 0 Internal voltage reference generator enabled The VREF pin should be left uncon nected or capacitively coupled to analog ground if the internal voltage reference is selected as the ADC reference voltage 1 Internal voltage reference generator disabled An external voltage reference must be provided through the VREF pin CONT 0 Single shot conversion ADC data is output once at completion of the 5129 system clock cycles 1 Continuous conversion ADC data updated every 256 system clock cycles ANAIN Analog Input Select These bits select the analog input for conversion Not all Port pins in this list are available in all packages for the Z8F642x familyZ8R642x family of products Refer to the Signal and Pin Descriptions chapter for information regarding the Port pins available with each package style Do not enable unavailable analog inputs 0000 ANAO 0001 ANA1 0010 ANA2 0011 ANA3 Analog to Digital Converter 010 62245566 13810019655 IG i uu UU Z8 Encore 64K Series Product Specification Zi ZiLOG 0100 ANA4 0101 ANA5 0110 ANA6 0111 ANA7 1000 ANA8 1001 ANA9 1010 ANA10 1011 ANAII 11XX Reserved ADC Data High Byte Register The ADC Data High Byte register Table 86 contains the upper eight bits of the 10 bit ADC output
211. e eee 130 I2C Controller Block Diagram 0 cece eee eee 140 7 Bit Address Only Transaction Format 00 020 e eee ee 144 7 Bit Addressed Slave Data Transfer Format 145 10 Bit Address Only Transaction Format 00005 146 10 Bit Addressed Slave Data Transfer Format 147 Receive Data Transfer Format for a 7 Bit Addressed Slave 149 List of Figures LEER ETONE ESEP oe 010 62245566 13810019655 xi Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63 Figure 64 PS019915 1005 htt p ww xi npi an net Z8 Encore 64K Series Product Specification ZiLOG Receive Data Format for a 10 Bit Addressed Slave 150 Analog to Digital Converter Block Diagram 0 4 172 Flash Memory Arrangement 0 0 0 c cece eee eee 179 On Chip Debugger Block Diagram 0 0 0 0 eee ee eee 193 Interfacing the On Chip Debugger s DBG Pin with an RS 232 Interface 1 20 teens 194 Interfacing the On Chip Debugger s DBG Pin with an RS 232 Interface 2 1 0 0 eee ee
212. e out To configure the Baud Rate Generator as a timer with interrupt on time out complete the following procedure 1 Disable the UART by clearing the REN and TEN bits in the UART Control 0 register to 0 2 Load the desired 16 bit count value into the UART Baud Rate High and Low Byte registers 3 Enable the Baud Rate Generator timer function and associated interrupt by setting the BRGCTL bit in the UART Control 1 register to 1 When configured as a general purpose timer the interrupt interval is calculated using the following equation Interrupt Interval s System Clock Period s xBRG 15 0 UART Control Register Definitions The UART control registers support the UART and the associated Infrared Encoder Decoders For more information on the infrared operation refer to the Infrared Encoder Decoder chapter on page 120 UART Transmit Data Register Data bytes written to the UART Transmit Data register Table 51 are shifted out on the TXDx pin The Write only UART Transmit Data register shares a Register File address with the Read only UART Receive Data register Table 51 UART Transmit Data Register Ux TXD BITS 7 6 5 4 3 2 1 0 FIELD TXD RESET X R W W ADDR F40H and F48H PS019915 1005 UART htt p ww xi npi an net utu ee ee EU og 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z 110
213. e signals are the transmit outputs from the UARTs The TXD signals are multiplexed with general purpose I O pins RXDO RXDI I Receive Data These signals are the receiver inputs for the UARTS and IrDAs The RXD signals are multiplexed with general purpose I O pins CTSO CTS1 I Clear To Send These signals are control inputs for the UARTs The CTS signals are multiplexed with general purpose I O pins DEO DE1 O Driver Enable This signal allows automatic control of external RS 485 drivers This signal is approximately the inverse of the TXE Transmit Empty bit in the UART Status 0 register The DE signal may be used to ensure an external RS 485 driver is enabled when data is transmitted by the UART Timers TOOUT TIOUT O Timer Output 0 3 These signals are output pins from the timers The Timer Output T2OUT T30UT signals are multiplexed with general purpose I O pins T3OUT is not available in 44 pin package devices TOIN T1IN I Timer Input 0 3 These signals are used as the capture gating and counter inputs T2IN T3IN The Timer Input signals are multiplexed with general purpose I O pins T3IN is not available in 44 pin package devices Analog ANA 11 0 I Analog Input These signals are inputs to the analog to digital converter ADC The ADC analog inputs are multiplexed with general purpose I O pins VREF I Analog to digital converter reference voltage input The VREF pin must be left unconnected or ca
214. e specific package styles Table 3 Signal Descriptions Signal Mnemonic rO Description General Purpose I O Ports A H PA 7 0 IO Port A 7 0 These pins are used for general purpose I O and support 5V tolerant inputs PB 7 0 IO Port B 7 0 These pins are used for general purpose I O PC 7 0 IO Port C 7 0 These pins are used for general purpose I O These pins are used for general purpose I O and support 5V tolerant inputs PD 7 0 IO Port D 7 0 These pins are used for general purpose I O These pins are used for general purpose I O and support 5V tolerant inputs PE 7 0 IO Port E 7 0 These pins are used for general purpose I O These pins are used for general purpose I O and support 5V tolerant inputs PF 7 0 IO Port F 7 0 These pins are used for general purpose I O These pins are used for general purpose I O and support 5V tolerant inputs PG 7 0 IO Port G 7 0 These pins are used for general purpose I O These pins are used for general purpose I O and support 5V tolerant inputs PH 3 0 IO Port H 3 0 These pins are used for general purpose I O PC Controller SCL O Serial Clock This is the output clock for the I C This pin is multiplexed with a general purpose I O pin When the general purpose I O pin is configured for alternate function to enable the SCL function this pin is open drain SDA IO Serial Data This open drain pin transfers data between the PC and a slave This pin is mu
215. e the UART Control 1 register to select the outgoing address bit 7 Set the MULTIPROCESSOR Bit Transmitter MPBT if sending an address byte clear it if sending a data byte 8 Write the data byte to the UART Transmit Data register The transmitter automatically transfers the data to the Transmit Shift register and transmits the data 9 If desired and MULTIPROCESSOR mode is enabled make any changes to the MULTIPROCESSOR Bit Transmitter MPBT value 10 To transmit additional bytes return to Step 5 Transmitting Data using the Interrupt Driven Method The UART transmitter interrupt indicates the availability of the Transmit Data register to accept new data for transmission Follow these steps to configure the UART for interrupt driven data transmission 1 Write to the UART Baud Rate High and Low Byte registers to set the desired baud rate 2 Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation Execute a DI instruction to disable interrupts 4 Write to the Interrupt control registers to enable the UART Transmitter interrupt and set the desired priority 5 If MULTIPROCESSOR mode is desired write to the UART Control 1 register to enable MULTIPROCESSOR 9 bit mode functions 6 Set the MULTIPROCESSOR Mode Select MPEN to Enable MULTIPROCESSOR mode 7 Write to the UART Control 0 register to Set the transmit enable bit TEN to enable the UART for data transmission Ena
216. e two address bits and a 0 write to the I2C Data register 2 Software asserts the START and TXI bits of the C Control register The I C Controller sends the Start condition 4 The C Controller loads the C Shift register with the contents of the PC Data register 5 After the first bit has been shifted out a Transmit interrupt is asserted 6 Software responds by writing the lower eight bits of address to the PC Data register 7 The PC Controller completes shifting of the two address bits and a 0 write 8 Ifthe C slave acknowledges the first address byte by pulling the SDA signal low during the next high period of SCL the IC Controller sets the ACK bit in the IC Status register Continue with step 9 If the slave does not acknowledge the first address byte the PC Controller sets the NCKI bit and clears the ACK bit in the I7C Status register Software responds to the Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI bit The I2C Controller sends the STOP condition on the bus and clears the STOP and NCKI bits The transaction is complete ignore following steps 9 The I C Controller loads the I7C Shift register with the contents of the PC Data register second address byte 10 The C Controller shifts out the second address byte After the first bit is shifted the IC Controller generates a Transmit interrupt 11 Software responds by setting the START bit of the PC Control register to gen
217. ea er eds 64 Interrupt Vectors and Priority lleseeeeee eee 65 Interrupt Assertion sseeeeee m 65 Software Interrupt Assertion lessen 65 PS019915 1005 Table of Contents htt p ww xi npi an net ugagamBpmmuagdisqiaudtt Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification ZiLOG Interrupt Control Register Definitions 66 Interrupt Request 0 Register lese 66 Interrupt Request 1 Register lclelee II 67 Interrupt Request 2 Register leeeeeeeee eee 68 IRQO Enable High and Low Bit Registers 0 0 0 cee eee ee eee 69 IRQI Enable High and Low Bit Registers 0 0 0 0 0 cece eee eee 70 IRQ2 Enable High and Low Bit Registers 0 0 0 cece eee eee 71 Interrupt Edge Select Register 2 0 2 eect eee 72 Interrupt Port Select Register 0 2 eee eA 73 Interrupt Control Register 0 2 teen eens 74 l AT 75 OVETVIEW AE CL 75 ATClitectute ix Aiadiend diated aep gba tbe ce Penbuw Dida sida a Roda debe uis 75 Operation c Lus aei iode t a ore e os qe sU qe ae a o at 76 Timer Operating Modes lsseleeee eh 76 Reading the Timer Count Values seeeeeeeeee eee 84 Timer Output Signal Operation 0 0 0 eh 84 Timer Control Register Definitions llleeeelee ee 84 Timer 0 3 High and Low Byte Registers lees 84 Timer Reload High and Low Byte Registers
218. eads from this register return the low byte of the Current Address to be used for the next DMA data transfer Table 79 DMAx Start Current Address Low Byte Register DMAxSTART BITS 7 6 5 4 3 2 1 0 FIELD DMA_START RESET a R W R W ADDR FB3H FBBH DMA START DMAx Start Current Address Low These bits with the four lower bits of the DMAx H register form the 12 bit Start Current address The full 12 bit address is given by DMA START H 3 0 DMA START 7 0 DMAx End Address Low Byte Register The DMAx End Address Low Byte register Table 79 in conjunction with the DMAx H register Table 80 forms a 12 bit End Address PS019915 1005 Direct Memory Access Controller htt p ww xi npi an net utu ee ee EU og 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z 167 ZiLOG Table 80 DMAx End Address Low Byte Register DMAxEND BITS 7 6 5 4 3 2 1 0 FIELD DMA END RESET X R W R W ADDR FB4H FBCH DMA END DMAx End Address Low These bits with the four upper bits of the DMAx H register form a 12 bit address This address is the ending location of the DMAx transfer The full 12 bit address is given by DMA END H 3 0 DMA_END 7 0 DMA ADC Address Register PS019915 1005 htt p ww xi npi an net u Donnan Uu The DMA ADC Address register Ta
219. ecification Z 181 ZiLOG Timing Using the Flash Frequency Registers Before performing a program or erase operation on the Flash memory the user must first configure the Flash Frequency High and Low Byte registers The Flash Frequency regis ters allow programming and erasure of the Flash with system clock frequencies ranging from 20kHz through 20MHz the valid range is limited to the device operating frequen cies The Flash Frequency High and Low Byte registers combine to form a 16 bit value FFREQ to control timing for Flash program and erase operations The 16 bit Flash Fre quency value must contain the system clock frequency in KHz This value is calculated using the following equation FFREQ 15 0 System Clock Ere uency Hz AN Caution Flash programming and erasure are not supported for system clock fre quencies below 20KHz above 20MHZ or outside of the device operating frequency range The Flash Frequency High and Low Byte registers must be loaded with the correct value to insure proper Flash programming and erase operations Flash Read Protection The user code contained within the Flash memory can be protected from external access Programming the Flash Read Protect Option Bit prevents reading of user code by the On Chip Debugger or by using the Flash Controller Bypass mode Refer to the Option Bits chapter and the On Chip Debugger chapter for more information Flash Write Erase Protection The 64K Series provid
220. ective GPIO ports the pins are automatically configured for open drain operation The master C is responsible for driving the SCL clock signal although the clock signal can become skewed by a slow slave device During the low period of the clock the slave pulls the SCL signal Low to suspend the transaction The master releases the clock at the end of the low period and notices that the clock remains low instead of returning to a high level When the slave releases the clock the PC Controller continues the transaction All data is transferred in bytes and there is no limit to the amount of data transferred in one operation When transmitting data or acknowledging read data from the slave the SDA signal changes in the middle of the low period of SCL and is sampled in the middle of the high period of SCL PC Interrupts The I C Controller contains four sources of interrupts Transmit Receive Not Acknowl edge and baud rate generator These four interrupt sources are combined into a single interrupt request signal to the Interrupt Controller The Transmit interrupt is enabled by the IEN and TXI bits of the Control register The Receive and Not Acknowledge interrupts are enabled by the IEN bit of the Control register The baud rate generator interrupt is enabled by the BIRQ and IEN bits of the Control register Not Acknowledge interrupts occur when a Not Acknowledge condition is received from the slave or sent by the PC Controller and neither
221. ed The Flash Sector Protect register is ignored for programming and erase operations Programming operations are not limited to the page selected in the Page Select register Bits in the Flash Sector Protect register can be written to one or zero The second write of the Page Select register to unlock the Flash Controller is not necessary The Page Select register can be written when the Flash Controller is unlocked The Mass Erase command is enabled through the Flash Control register AN Caution For security reasons flash controller allows only a single page to be opened for write erase When writing multiple flash pages the flash con troller must go through the unlock sequence again to select another page PS019915 1005 Flash Memory http ww xi npi an net DOTA 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Zi ZiLOG Flash Control Register Definitions Flash Control Register The Flash Control register Table 91 unlocks the Flash Controller for programming and erase operations or to select the Flash Sector Protect register The Write only Flash Control Register shares its Register File address with the Read only Flash Status Register Table 91 Flash Control Register FCTL BITS 7 6 5 4 3 2 1 0 FIELD FCMD RESET 0 R W W ADDR FF8H PS019915 1005 FCMD Flash Command 73H First unl
222. egisters to set the starting count value 3 Write to the Timer Reload High and Low Byte registers to set the Compare value 4 If desired enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers 5 Ifusing the Timer Output function configure the associated GPIO port pin for the Timer Output alternate function 6 Write to the Timer Control 1 register to enable the timer and initiate counting In COMPARE mode the system clock always provides the timer input The Compare time is given by the following equation Compare Mode Time s Compare Value Z Start Value x Prescale System Clock Frequency Hz GATED Mode In GATED mode the timer counts only when the Timer Input signal is in its active state asserted as determined by the TPOL bit in the Timer Control 1 register When the Timer Input signal is asserted counting begins A timer interrupt is generated when the Timer Input signal is deasserted or a timer reload occurs To determine if a Timer Input signal deassertion generated the interrupt read the associated GPIO input value and compare to the value stored in the TPOL bit The timer counts up to the 16 bit Reload value stored in the Timer Reload High and Low Byte registers The timer input is the system clock When reaching the Reload value the timer generates an interrupt the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes ass
223. eload value gt Note If the DIAG bit in the PC Diagnostic Control Register is set to 1 a read of the I2CBRH register returns the current value of the IC Baud Rate Counter 15 8 Table 73 I C Baud Rate Low Byte Register IZCBRL BITS 7 6 5 4 2 1 0 FIELD BRL RESET FFH R W R W ADDR F54H BRL C Baud Rate Low Byte Least significant byte BRG 7 0 of the IC Baud Rate Generator s reload value y Note If the DIAG bit in the C Diagnostic Control Register is set to 1 a read of the IZCBRL register returns the current value of the IC Baud Rate Counter 7 0 PS019915 1005 htt p ww xi npi an net 12C Controller D U Uu LH 010 62245566 13810019655 I C Diagnostic State Register Z8 Encore 64K Series Product Specification Zi ZiLOoG The C Diagnostic State register Table 74 provides observability of internal state This is a read only register used for PC diagnostics and manufacturing test Table 74 C Diagnostic State Register IZCDST BITS 7 6 5 4 2 0 FIELD SCLIN SDAIN STPCNT TXRXSTATE RESET 0 R W R ADDR F55H SCLIN Value of Serial Clock input signal SDAIN Value of the Serial Data input signal STPCNT Value of the internal Stop Count control signal TXRXSTATE Value of the internal I7C state machine TXRXSTATE State Description 0_00
224. em clock cycle latency on the inputs 1 low pass filters are enabled 0 low pass filters are disabled I C Baud Rate High and Low Byte Registers The I C Baud Rate High and Low Byte registers Tables 72 and 73 combine to form a 16 bit reload value BRG 15 0 for the C Baud Rate Generator When the C is disabled the Baud Rate Generator can function as a basic 16 bit timer with interrupt on time out To configure the Baud Rate Generator as a timer with interrupt on time out complete the following procedure 1 Disable the C by clearing the IEN bit in the PC Control register to 0 2 Load the desired 16 bit count value into the IC Baud Rate High and Low Byte registers 3 Enable the Baud Rate Generator timer function and associated interrupt by setting the BIRQ bit in the C Control register to 1 When configured as a general purpose timer the interrupt interval is calculated using the following equation Interrupt Interval s System Clock Period s xBRG 15 0 PS019915 1005 I2C Controller HHHEHEHIGBUHBBHBHH 010 62245566 13810019655 htt p ww xi npi an net EE Z8 Encore 64K Series Product Specification Zi ZiLoG Table 72 I C Baud Rate High Byte Register I2CBRH BITS 7 6 5 4 2 1 0 FIELD BRH RESET FFH R W R W ADDR F53H BRH IC Baud Rate High Byte Most significant byte BRG 15 8 of the C Baud Rate Generator s r
225. ement addresses 240 load effective address 240 load external data 240 load external data to from data memory and auto increment addresses 239 load external to from data memory and auto incre ment addresses 240 load instructions 240 load using extended addressing 240 logical AND 241 logical AND extended addressing 241 logical exclusive OR 241 logical exclusive OR extended addressing 241 logical instructions 241 logical OR 241 logical OR extended addressing 241 low power modes 49 LQFP 44 lead 258 Index htt p ww xi npi an net DEL EY EC BRE UE IMOO000000 010 62245566 13810019655 64 lead 259 M master interrupt enable 64 master in slave out and in 127 memory program 18 MISO 127 mode capture 89 capture compare 89 continuous 89 counter 89 gated 89 one shot 89 PWM 89 modes 89 MOSI 127 MULT 238 multiply 238 multiprocessor mode UART 104 N NOP no operation 240 not acknowledge interrupt 141 notation b 235 cc 235 DA 235 ER 235 IM 235 IR 235 Ir 235 IRR 235 Irr 235 p 235 R 235 r 235 RA 235 RR 235 rr 235 vector 235 PS019915 1005 Z8 Encore 64K Series Product Specification L zs ZiLOG X 235 notational shorthand 235 O OCD architecture 193 auto baud detector generator 196 baud rate limits 196 block diagram 193 breakpoints 197 commands 198 control register 202 data format 196 DBG pin to RS 232 Interface 194 debug mode 195 debugger break 241
226. enerate an interrupt This bit is cleared by reading the PC Data register unless the read is performed using exe cution of the On Chip Debugger s Read Register command ACK Acknowledge This bit indicates the status of the Acknowledge for the last byte transmitted or received When set this bit indicates that an Acknowledge occurred for the last byte transmitted or received This bit is cleared when IEN 0 or when a Not Acknowledge occurred for the 12C Controller 010 62245566 13810019655 Z8 Encore 64K Series Product Specification L i ZiLOG last byte transmitted or received It is not reset at the beginning of each transaction and is not reset when this register is read UN Caution Software must be cautious in making decisions based on this bit within a transaction because software cannot tell when the bit is updated by hard ware In the case of write transactions the I2C pauses at the beginning of the Acknowledge cycle if the next transmit data or address byte has not been written TDRE 1 and STOP and START 0 In this case the ACK bit is not updated until the transmit interrupt is serviced and the Acknowl edge cycle for the previous byte completes Refer to Address Only Trans action with a 7 bit Address on page 144 and Address Only Transaction with a 10 bit Address on page 146 for examples of how the ACK bit can be used 10B 10 Bit Address This bit ind
227. equence configures the WDT to be disabled when the 64K Series devices enter STOP Mode following execution of a STOP instruction 1 Write 55H to the Watch Dog Timer Control register WDTCTL 2 Write AAH to the Watch Dog Timer Control register WDTCTL 3 Write 81H to the Watch Dog Timer Control register WDTCTL to configure the WDT and its oscillator to be disabled during STOP Mode Alternatively write 00H to the Watch Dog Timer Control register WDTCTL as the third step in this sequence to reconfigure the WDT and its oscillator to be enabled during STOP Mode This sequence only affects WDT operation in STOP mode Watch Dog Timer Reload Unlock Sequence Writing the unlock sequence to the Watch Dog Timer WDTCTL Control register address unlocks the three Watch Dog Timer Reload Byte registers WDTU WDTH and WDTL to allow changes to the time out period These write operations to the WDTCTL register address produce no effect on the bits in the WDTCTL register The locking mechanism prevents spurious writes to the Reload registers The follow sequence is required to unlock the Watch Dog Timer Reload Byte registers WDTU WDTH and WDTL for write access PS019915 1005 Watch Dog Timer htt p ww xi npi an net ugagamBpmmuagdisqiaudtt Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z 94 ZiLOG Write 55H to the Watch Dog Timer Control register WDTCTL Write AAH to
228. er Table 101 OCD Control Register OCDCTL BITS 7 6 5 4 3 2 1 0 FIELD DBGMODE BRKEN DBGACK BRKLOOP Reserved RST RESET g R W R W R R W PS019915 1005 htt p ww xi npi an net Hg g dg p B m DBGMODE Debug Mode Setting this bit to 1 causes the device to enter DEBUG mode When in DEBUG mode the eZ8 CPU stops fetching new instructions Clearing this bit causes the eZ8 CPU to start running again This bit is automatically set when a BRK instruction is decoded and Break points are enabled If the Read Protect Option Bit is enabled this bit can only be cleared by resetting the device it cannot be written to 0 0 The 64K Series device is operating in Normal mode 1 The 64K Series device is in DEBUG mode BRKEN Breakpoint Enable This bit controls the behavior of the BRK instruction opcode 00H By default Break points are disabled and the BRK instruction behaves like a NOP If this bit is set to 1 anda BRK instruction is decoded the OCD takes action dependent upon the BRKLOOP bit 0 BRK instruction is disabled 1 BRK instruction is enabled DBGACK Debug Acknowledge This bit enables the debug acknowledge feature If this bit is set to 1 then the OCD sends an Debug Acknowledge character FFH to the host when a Breakpoint occurs 0 Debug Acknowledge is disabled 1 Debug Acknowledge is enabled BRKLOOP Breakpoint Loop This bit determines what action the O
229. er 1 Low Byte TIL 01 84 F0A Timer 1 Reload High Byte TIRH FF 85 FOB Timer 1 Reload Low Byte TIRL FF 85 FOC Timer 1 PWM High Byte TIPWMH 00 87 FOD Timer 1 PWM Low Byte TIPWML 00 87 FOE Timer 1 Control 0 TICTLO 00 88 FOF Timer 1 Control 1 TICTLI 00 88 Timer 2 F10 Timer 2 High Byte T2H 00 84 F11 Timer 2 Low Byte T2L 01 84 F12 Timer 2 Reload High Byte T2RH FF 85 F13 Timer 2 Reload Low Byte T2RL FF 85 F14 Timer 2 PWM High Byte T2PWMH 00 87 F15 Timer 2 PWM Low Byte T2PWML 00 87 F16 Timer 2 Control 0 T2CTLO 00 88 F17 Timer 2 Control 1 T2CTLI 00 88 XX Undefined PS019915 1005 htt p ww xi npi an net 0 DET Uu UU Register File Address Map 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Zi zZiILoOdG Table 7 64K Series Register File Address Map Continued Address Hex Register Description Mnemonic Reset Hex Page Timer 3 unavailable in the 44 pin packages F18 Timer 3 High Byte T3H 00 84 F19 Timer 3 Low Byte T3L 01 84 FIA Timer 3 Reload High Byte T3RH FF 85 FIB Timer 3 Reload Low Byte T3RL FF 85 FIC Timer 3 PWM High Byte T3PWMH 00 87 FID Timer 3 PWM Low Byte T3PWML 00 87 FIE Timer 3 Control 0 T3CTLO 00 88 FIF Timer 3 Control 1 T3CTLI 00 88 20 3F Reserved XX UART 0 F40 UARTO Transmit Data UOTXD XX 109 UARTO Rece
230. er and the external Slave The input to the Baud Rate Generator is the system clock The SPI Baud Rate High and Low Byte registers combine to form a 16 bit reload value BRG 15 0 for the SPI Baud Rate Generator The SPI baud rate is calculated using the following equation SPI Baud Rate bits s 5Xstem Clock Frequency Hz ROSE Hz Minimum baud rate is obtained by setting BRG 15 0 to 0000H for a clock divisor value of 2 X 65536 131072 When the SPI is disabled the Baud Rate Generator can function as a basic 16 bit timer with interrupt on time out To configure the Baud Rate Generator as a timer with interrupt on time out complete the following procedure 1 Disable the SPI by clearing the SPIEN bit in the SPI Control register to 0 2 Load the desired 16 bit count value into the SPI Baud Rate High and Low Byte registers 3 Enable the Baud Rate Generator timer function and associated interrupt by setting the BIRQ bit in the SPI Control register to 1 When configured as a general purpose timer the interrupt interval is calculated using the following equation Interrupt Interval s System Clock Period s xBRG 15 0 PS019915 1005 Serial Peripheral Interface HHHEHEHIGBUHBBHBHH 010 62245566 13810019655 htt p ww xi npi an net EE Z8 Encore 64K Series Product Specification ZiLOG SPI Control Register Definitions SPI Data Register The SPI Data register Table 62 store
231. erate a repeated START and by clearing the TXI bit 12 Software responds by writing 11110B followed by the 2 bit slave address and a 1 read to the I2C Data register 13 If only one byte is to be read software sets the NAK bit of the PC Control register 14 After the C Controller shifts out the 2nd address byte the IC slave sends an acknowledge by pulling the SDA signal low during the next high period of SCL the PC Controller sets the ACK bit in the 7C Status register Continue with step 15 If the slave does not acknowledge the second address byte the PC Controller sets the NCKI bit and clears the ACK bit in the C Status register Software responds to the Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI bit The I2C Controller sends the STOP condition on the bus and clears the STOP and NCKI bits The transaction is complete ignore the following steps 15 The IC Controller sends the repeated START condition PS019915 1005 I2C Controller htt p ww xi npi an net COA ee ee DELI 010 62245566 13810019655 16 17 18 19 20 21 22 23 24 25 Z8 Encore 64K Series Product Specification Z 152 ZiLOoG The C Controller loads the C Shift register with the contents of the PC Data register third address transfer The C Controller sends 111108 followed by the two most significant bits of the slave read address and a 1 read The I7C slave send
232. eripheral Interface htt p ww xi npi an net o ee ee a og 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 127 ZiLOG During an SPI transfer data is sent and received simultaneously by both the Master and the Slave SPI devices Separate signals are required for data and the serial clock When an SPI transfer occurs a multi bit typically 8 bit character is shifted out one data pin and an multi bit character is simultaneously shifted in on a second data pin An 8 bit shift register in the Master and another 8 bit shift register in the Slave are connected as a circular buffer The SPI shift register is single buffered in the transmit and receive directions New data to be transmitted cannot be written into the shift register until the previous transmission is complete and receive data if valid has been read SPI Signals The four basic SPI signals are e MISO Master In Slave Out e MOSI Master Out Slave In e SCK SPI Serial Clock e SS Slave Select The following paragraphs discuss these SPI signals Each signal is described in both Mas ter and Slave modes Master In Slave Out The Master In Slave Out MISO pin is configured as an input in a Master device and as an output in a Slave device It is one of the two lines that transfer serial data with the most significant bit sent first The MISO pin of a Slave device is placed in a high impedan
233. es The 64K Series products support 4 different oscillator modes e On chip oscillator configured for use with external RC networks lt 4MHz e Minimum power for use with very low frequency crystals 32KHz to 1 0MHz Medium power for use with medium frequency crystals or ceramic resonators 0 5MHz to 10 0MHz e Maximum power for use with high frequency crystals or ceramic resonators 8 0MHz to 20 0MHz The oscillator mode is selected through user programmable Option Bits Refer to the Option Bits chapter for information Crystal Oscillator Operation Figure 40 illustrates a recommended configuration for connection with an external funda mental mode parallel resonant crystal operating at 20MHz Recommended 20MHz crys tal specifications are provided in Table 103 Resistor R1 is optional and limits total power dissipation by the crystal The printed circuit board layout must add no more than 4pF of PS019915 1005 On Chip Oscillator htt p ww xi npi an net EE 205 HHHEHEHIGBUHBBHBHH 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Zi ZiLOG stray capacitance to either the Xp or Xop pins If oscillation does not occur reduce the values of capacitors C1 and C2 to decrease loading On Chip Oscillator XIN XOUT R1 2200 Crystal C1 22pF C2 22pF Figure 40 Recommended 20MHz Cr
234. es several levels of protection against accidental program and era sure of the Flash memory contents This protection is provided by the Flash Controller unlock mechanism the Flash Sector Protect register and the Flash Write Protect option bit Flash Controller Unlock Mechanism At Reset the Flash Controller locks to prevent accidental program or erasure of the Flash memory To program or erase the Flash memory the Flash controller must be unlocked After unlocking the Flash Controller the Flash can be programmed or erased Any value written by user code to the Flash Control register or Page Select Register out of sequence will lock the Flash Controller The proper steps to unlock the Flash Controller from user code are 1 Write 00H to the Flash Control register to reset the Flash Controller PS019915 1005 Flash Memory htt p ww xi npi an net EE HHHEHEHIGBUHBBHBHH 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z 182 ZiLOG Write the page to be programmed or erased to the Page Select register Write the first unlock command 73H to the Flash Control register Write the second unlock command 8CH to the Flash Control register wk Y m Re write the page written in step 2 to the Page Select register Flash Sector Protection The Flash Sector Protect register can be configured to prevent sectors from being pro grammed or erased Once a sector is protected it c
235. es the Flash memory 10 Bit Analog to Digital Converter The Analog to Digital Converter ADC converts an analog input signal to a 10 bit binary number The ADC accepts inputs from up to 12 different analog input sources UARTs Each UART is full duplex and capable of handling asynchronous data transfers The UARTS support 8 and 9 bit data modes selectable parity and an efficient bus transceiver Driver Enable signal for controlling a multi transceiver bus such as RS 485 PS019915 1005 htt p ww xi npi an net EE TENENT IG1U D UU Lu Introduction 010 62245566 13810019655 Z8 Encore 64K Series Product Specification ZiLOG PC The inter integrated circuit C9 controller makes the Z8 Encore compatible with the PC protocol The IC controller consists of two bidirectional bus lines a serial data SDA line and a serial clock SCL line Serial Peripheral Interface The serial peripheral interface SPI allows the Z8 Encore to exchange data between other peripheral devices such as EEPROMs A D converters and ISDN devices The SPI is a full duplex synchronous character oriented channel that supports a four wire interface Timers Up to four 16 bit reloadable timers can be used for timing counting events or for motor control operations These timers provide a 16 bit programmable reload counter and oper ate in One Shot Continuous Gated Capture Compare Capture and Comp
236. eset and Clear The word set implies that a register bit or a condition contains a logical 1 The words reset or clear imply that a register bit or a condition contains a logical 0 When either of these terms is followed by a number the word logical may not be included however it is implied Notation for Bits and Similar Registers A field of bits within a register is designated as Register n r1 e Example ADDR 15 0 refers to bits 15 through bit 0 of the Address Use of the Terms LSB MSB Isb and msb In this document the terms LSB and MSB when appearing in upper case mean least sig nificant byte and most significant byte respectively The lowercase forms sb and msb mean least significant bit and most significant bit respectively Use of Initial Uppercase Letters Initial uppercase letters designate settings and conditions in general text e Example 1 The receiver forces the SCL line to Low PS019915 1005 Manual Objectives htt p ww xi npi an net ugagamBpmmuagdisqiaudtt Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z ZiLOG Example 2 The Master can generate a Stop condition to abort the transfer Use of All Uppercase Letters The use of all uppercase letters designates the names of states modes and commands e Example 1 The bus is considered BUSY after the Start condition Example 2 A START command triggers the processing o
237. ess byte The least significant bit must be 0 for the write operation Software asserts the START bit of the C Control register The I C Controller sends the START condition to the IC slave ea PS019915 1005 12C Controller htt p ww xi npi an net ugagamBpmmuagdisqiaudtt Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Zi ZiloaoG 7 The I C Controller loads the I7C Shift register with the contents of the PC Data register 8 After one bit of address is shifted out by the SDA signal the Transmit interrupt is asserted 9 Software responds by writing the second byte of address into the contents of the re Data register 10 The C Controller shifts the rest of the first byte of address and write bit out the SDA signal 11 If the PC slave sends an acknowledge by pulling the SDA signal low during the next high period of SCL the IC Controller sets the ACK bit in the I C Status register Continue with step 12 If the slave does not acknowledge the first address byte the PC Controller sets the NCKI bit and clears the ACK bit in the C Status register Software respons to the Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI bit The I2C Controller sends the STOP condition on the bus and clears the STOP and NCKI bits The transaction is complete ignore following steps 12 The IC Controller loads the I7C Shift register with
238. etector Generator can then be reconfigured by sending 80H PS019915 1005 On Chip Debugger htt p ww xi npi an net ugagamBpmmuagdisqiaudtt Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z 197 ZiLOG OCD Serial Errors The On Chip Debugger can detect any of the following error conditions on the DBG pin e Serial Break a minimum of nine continuous bits Low e Framing Error received Stop bit is Low e Transmit Collision OCD and host simultaneous transmission detected by the OCD When the OCD detects one of these errors it aborts any command currently in progress transmits a Serial Break 4096 system clock cycles long back to the host and resets the Auto Baud Detector Generator A Framing Error or Transmit Collision may be caused by the host sending a Serial Break to the OCD Because of the open drain nature of the inter face returning a Serial Break break back to the host only extends the length of the Serial Break if the host releases the Serial Break early The host transmits a Serial Break on the DBG pin when first connecting to the 64K Series devices or when recovering from an error A Serial Break from the host resets the Auto Baud Generator Detector but does not reset the OCD Control register A Serial Break leaves the device in DEBUG mode if that is the current mode The OCD is held in Reset until the end of the Serial Break when the DBG pin returns High Be
239. f power reduction is provided by the HALT mode STOP Mode Execution of the eZ8 CPU s STOP instruction places the device into STOP mode In STOP mode the operating characteristics are e Primary crystal oscillator is stopped the XIN pin is driven High and the XOUT pin is driven Low e System clock is stopped e eZ8 CPU is stopped Program counter PC stops incrementing The Watch Dog Timer and its internal RC oscillator continue to operate if enabled for operation during STOP mode The Voltage Brown Out protection circuit continues to operate if enabled for operation in STOP mode using the associated Option Bit e All other on chip peripherals are idle To minimize current in STOP mode all GPIO pins that are configured as digital inputs must be driven to one of the supply rails V cc or GND the Voltage Brown Out protection must be disabled and the Watch Dog Timer must be disabled The devices can be brought out of STOP mode using STOP Mode Recovery For more information on STOP Mode Recovery refer to the Reset and STOP Mode Recovery chapter beginning on page 43 AN Caution STOP Mode must not be used when driving the 64K Series devices with an external clock driver source PS019915 1005 Low Power Modes htt p ww xi npi an net ugagamBpmmuagdisqiaudtt Ooo 010 62245566 13810019655 HALT Mode Z8 Encore 64K Series Product Specification VAF ZiLOG Execution of the eZ
240. f the initialization sequence Example 3 STOP mode Bit Numbering Bits are numbered from 0 to n where n indicates the total number of bits For example the 8 bits of a register are numbered from 0 to 7 Safeguards It is important that all users understand the following safety terms which are defined here AN Caution Indicates a procedure or file may become corrupted if the user does not fol low directions Trademarks ZiLOGS eZ8 Z8 Encore and Z89 are trademarks of ZiLOG Inc in the U S A and other countries All other trademarks are the property of their respective corporations PS019915 1005 Manual Objectives htt p ww xi npi an net DOTA nono 010 62245566 13810019655 Z8 Encore 64K Series Product Specification ZiLOG Introduction The Z8 Encore MCU family of products are a line of ZiLOG microcontroller products based upon the 8 bit eZ8 CPU The Z8 Encore 64K Series hereafter referred to collec tively as the Z8 Encore or the 64K Series adds Flash memory to ZiLOG s extensive line of 8 bit microcontrollers The Flash in circuit programming capability allows for faster development time and program changes in the field The new eZ8 CPU is upward compat ible with existing Z8 instructions The rich peripheral set of the Z8 Encore makes it suitable for a variety of applications including motor control security systems home appliances personal electr
241. fined as destinations The architecture of the eZ8 CPU allows all general purpose registers to function as accumulators address pointers index registers stack areas or scratch pad memory The upper 256 bytes of the 4KB Register File address space are reserved for control of the eZ8 CPU the on chip peripherals and the I O ports These registers are located at addresses from FOO0H to FFFH Some of the addresses within the 256 byte control register section are reserved unavailable Reading from an reserved Register File addresses returns an undefined value Writing to reserved Register File addresses is not recom mended and can produce unpredictable results The on chip RAM always begins at address 000H in the Register File address space The 64K Series provide 2KB to 4KB of on chip RAM depending upon the device Reading from Register File addresses outside the available RAM addresses and not within the con trol register address space returns an undefined value Writing to these Register File addresses produces no effect Refer to the Part Selection Guide on page 2 to determine the amount of RAM available for the specific 64K Series device PS019915 1005 Address Space htt p ww xi npi an net ELEE PEELEDEE EL EL EGER BY ERE EL EJ ET EH 010 62245566 13810019655 Program Memory Z8 Encore 64K Series Product Specification 18 ZiLOG The eZ8 CPU supports 64 KB of Program Memory address space Th
242. following table PS Product Specification 0199 Unique Document Number 07 Revision Number 0204 Month and Year Published PS019915 1005 Ordering Information htt p ww xi npi an net OU CUOMO oo Oo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Zi ZiLOG Customer Feedback Form The Z8 Encore 64K Series Product Specification If you experience any problems while operating this product or if you note any inaccuracies while reading this Product Specification please copy and complete this form then mail or fax it to ZiLOG see Return Information below We also welcome your suggestions Customer Information Name Country Company Phone Address Fax City State Zip E Mail Product Information Part Serial 4 Board Fab or Rev Software Version Document Number Host Computer Description Type Return Information ZiLOG Inc 532 Race Street San Jose CA 95126 Fax 408 558 8536 Problem Description or Suggestion Provide a complete description of the problem or your suggestion If you are reporting a specific problem include all steps leading up to the occurrence of the problem Attach additional pages as necessary PS019915 1005 Ordering Information htt p ww xi npi an net o ee ee a og 010 62245566 13810019655
243. fter the ADC writes a new 10 bit data result to ADCD_H 7 0 ADCD_L 7 6 every 256 system clock cycles An interrupt request is sent to the Interrupt Controller when each conversion is complete 5 To disable continuous conversion clear the CONT bit in the ADC Control register to 0 DMA Control of the ADC The Direct Memory Access DMA Controller can control operation of the ADC includ ing analog input selection and conversion enable For more information on the DMA and configuring for ADC operations refer to the chapter Direct Memory Access Controller on page 161 PS019915 1005 Analog to Digital Converter htt p ww xi npi an net COA ee ee DELI 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 175 ZiLOG ADC Control Register Definitions ADC Control Register The ADC Control register selects the analog input channel and initiates the analog to dig ital conversion Table 85 ADC Control Register ADCCTL BITS 7 6 5 4 3 2 1 0 FIELD CEN Reserved VREF CONT ANAIN 3 0 RESET 0 1 0 R W R W ADDR F70H PS019915 1005 htt p ww xi npi an net Hg g dg p B m CEN Conversion Enable 0 Conversion is complete Writing a 0 produces no effect The ADC automatically clears this bit to O when a conversion has been completed 1 Begin conversion Writing a 1 to this bit starts a conversion If a conversion is already in progress th
244. function 03H z Output control open drain 04H High drive enable 05H STOP mode recovery enable 06H FFH No function Port C Control PCCTL FD9H Read Write D7ID6 ID5 D4D3D2IDI DO L Port C Control 7 0 Provides Access to Port Sub Registers PS019915 1005 Z8 Encore 64K Series Z8 Encore VAR ZiLOG Port C Input Data PCIN FDAH Read Only D7 D6 D5 D4 D3 D2 D1 D0 L Port Input Data 7 0 Port C Output Data PCOUT FDBH Read Write D7ID6 D5 DA4ID3ID2 DI DO L Port C Output Data 7 0 Port D Address PDADDR FDCH Read Write D7 D6 DSIDAID3ID2 DI DO Port D Address 7 0 Selects Port Sub Registers 00H No function 01H Data direction 02H Alternate function 03H Output control open drain 04H High drive enable 05H STOP mode recovery enable 06H FFH No function Port D Control PDCTL FDDH Read Write D7 D6 D5 D4 D3 D2 D1 D0 L Port D Control 7 0 Provides Access to Port Sub Registers Port D Input Data PDIN FDE H Read Only D7 D6 D5 D4 D3 D2IDI DO L Port D Input Data 7 0 Port D Output Data PDOUT FDFH Read Write D7 D6 D5 D4 D3 D2 D1 D0 Port D Output Data 7 0 Control Regi
245. g p B m CADC 3 0 Current ADC Analog Input This field identifies the Analog Input that the ADC is currently converting Reserved This bit is reserved and must be 0 IRQA DMA ADC Interrupt Request Indicator This bit is automatically reset to 0 each time a read from this register occurs 02 DMA ADC is not the source of the interrupt from the DMA Controller 12 DMA ADC completed transfer of data from the last ADC Analog Input and generated an interrupt IRQ1 DMAI Interrupt Request Indicator This bit is automatically reset to 0 each time a read from this register occurs 0 DMAI is not the source of the interrupt from the DMA Controller 1 DMAI completed transfer of data to from the End Address and generated an interrupt IRQ0 DMAO Interrupt Request Indicator This bit is automatically reset to 0 each time a read from this register occurs 0 DMAO is not the source of the interrupt from the DMA Controller 1 DMAO completed transfer of data to from the End Address and generated an interrupt Direct Memory Access Controller IG1 D U Od 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 171 ZiLOG Analog to Digital Converter Overview The Analog to Digital Converter ADC converts an analog input signal to a 10 bit binary number The features of the sigma delta ADC include Architecture 12 analog input sources are multiplexed with general
246. ges at the input are not seen at the next output from the ADC The response of the ADC in all modes is limited by the input signal bandwidth and the latency The steps for setting up the ADC and initiating continuous conversion are as follows PS019915 1005 Analog to Digital Converter http ww xi npi an net DOTA 010 62245566 13810019655 Z8 Encore 64K Series Product Specification L m ZiLOG 1 Enable the desired analog input by configuring the general purpose I O pins for alternate function This disables the digital input and output driver 2 Write to the ADC Control register to configure the ADC for continuous conversion The bit fields in the ADC Control register may be written simultaneously Write to the ANAIN 3 0 field to select one of the 12 analog input sources Set CONT to 1 to select continuous conversion Write to the VREF bit to enable or disable the internal voltage reference generator Set CEN to 1 to start the conversions 3 When the first conversion in continuous operation is complete after 5129 system clock cycles plus the 40 cycles for power up if necessary the ADC control logic performs the following operations CEN resets to 0 to indicate the first conversion is complete CEN remains 0 for all subsequent conversions in continuous operation An interrupt request is sent to the Interrupt Controller to indicate the conversion is complete 4 Therea
247. gister FFREQH 189 Flash Frequency Low Byte Register FFREQL 0 189 Flash Option Bits At Flash Memory Address 0000H 191 Options Bits at Flash Memory Address 0001H 192 OCD Baud Rate Limits lleeeeeeeeee eh 196 On Chip Debugger Commands 0 0 0 0 cece eee eee 198 OCD Control Register OCDCTL seseseeeeeeeeee 203 OCD Status Register OCDSTAT 0 0 0 0 cee eee eee eee 204 Recommended Crystal Oscillator Specifications 20MHz Operation 206 List of Tables Ig1 H ELO U f L3 TENENT Lu 010 62245566 13810019655 xvi Z8 Encore 64K Series Product Specification Table 106 Absolute Maximum Ratings 0 0 0c ee e 209 Table 107 DC Characteristics 0 0 eee IRI 211 Table 108 Power On Reset and Voltage Brown Out Electrical Characteristics and Timing eleeeee eh 219 Table 109 Reset and STOP Mode Recovery Pin Timing 220 Table 110 External RC Oscillator Electrical Characteristics and Timing 220 Table 111 Flash Memory Electrical Characteristics and Timing 221 Table 112 Watch Dog Timer Electrical Characteristics and Timing 221 Table 113 Analog to Digital Converter Electrical Characteristics and Timing 222 Table 114 AC Characteristics 0 0 eee eee eens 224 Table 115 GPIO Port Inpu
248. gram written in assembly language is called a source program Assembly lan guage allows the use of symbolic addresses to identify memory locations It also allows mnemonic codes opcodes and operands to represent the instructions themselves The opcodes identify the instruction while the operands represent memory locations registers or immediate data values Each assembly language program consists of a series of symbolic commands called state ments Each statement can contain labels operations operands and comments Labels can be assigned to a particular instruction step in a source program The label iden tifies that step in the program as an entry point for use by other instructions The assembly language also includes assembler directives that supplement the machine instruction The assembler directives or pseudo ops are not translated into a machine instruction Rather the pseudo ops are interpreted as directives that control or assist the assembly process The source program is processed assembled by the assembler to obtain a machine lan guage program called the object code The object code is executed by the eZ8 CPU An example segment of an assembly language program is detailed in the following example Assembly Language Source Program Example JP START Everything after the semicolon is a comment START A label called START The first instruction JP START in this example causes program execution to jump to the
249. gure the associated GPIO port pin for the Timer Input alternate function 7 Write to the Timer Control 1 register to enable the timer and initiate counting In CAPTURE mode the elapsed time from timer start to Capture event can be calculated using the following equation Capture Value Z Start Value x Prescale Capture Elapsed Time s p p 6 System Clock Frequency Hz Compare Mode In COMPARE mode the timer counts up to the 16 bit maximum Compare value stored in the Timer Reload High and Low Byte registers The timer input is the system clock Upon reaching the Compare value the timer generates an interrupt and counting continues the timer value is not reset to 0001H Also if the Timer Output alternate function is enabled the Timer Output pin changes state from Low to High or from High to Low upon Com pare PS019915 1005 Timers HHHEHEHIGBUHBBHBHH 010 62245566 13810019655 81 Z8 Encore 64K Series Product Specification 82 ZiLOG If the Timer reaches FFFFH the timer rolls over to 0000H and continue counting The steps for configuring a timer for COMPARE mode and initiating the count are as fol lows 1 Write to the Timer Control 1 register to Disable the timer Configure the timer for COMPARE mode Set the prescale value Set the initial logic level High or Low for the Timer Output alternate function if desired 2 Write to the Timer High and Low Byte r
250. gured to generate an interrupt DMAx sends an interrupt request to the Interrupt Controller If configured for single pass operation DMAx resets the DEN bit in the DMAx Control register to 0 and the DMA is disabled If Current Address does not equal End Address the Current Address increments by 1 single byte transfer or 2 two byte word transfer PS019915 1005 Direct Memory Access Controller htt p ww xi npi an net ugagamBpmmuagdisqiaudtt Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification ZiLOG Configuring DMAO and DMA1 for Data Transfer Follow these steps to configure and enable DMAO or DMAT 1 Write to the DMAx I O Address register to set the Register File address identifying the on chip peripheral control register The upper nibble of the 12 bit address for on chip peripheral control registers is always FH The full address is FH DMAx_IO 7 0 Determine the 12 bit Start and End Register File addresses The 12 bit Start Address is given by DMAx_H 3 0 DMA_STARTT 7 0 The 12 bit End Address is given by DMAx_H 7 4 DMA_END 7 0 Write the Start and End Register File address high nibbles to the DMAx End Start Address High Nibble register Write the lower byte of the Start Address to the DMAx Start Current Address register Write the lower byte of the End Address to the DMAx End Address register Write to the DMAx Control register to complete the
251. h 10 Bit Analog to Converter Z8F1621PM020SC 16KB 2KB 29 23 3 8 1 1 2 PDIP 40 pin package Z8F1621ANO020SC Q1eKB 2KB 31 23 3 8 1 1 2 LQFP 44 pin package Z8F1621VNO020SC 16KB 2KB 31 23 3 8 1 1 2 PLCC 44 pin package Z8F1622AR020SC 16KB 2KB 46 24 4 12 1 1 2 LQFP 64 pin package Z8F1622VS020SC 16KB 2KB 46 24 4 12 1 1 2 PLCC 68 pin package Extended Temperature 40 to 105 C Z8F1621PMO20EC 16KB 2KB 29 23 3 8 1 1 2 PDIP 40 pin package Z8F1621ANO020EC 16KB 2KB 31 23 3 8 1 1 2 LQFP 44 pin package Z8F1621VNO20EC 16KB 2KB 31 23 3 8 1 1 2 PLCC 44 pin package Z8F1622AR020EC 16KB 2KB 46 24 4 12 1 1 2 LQFP 64 pin package Z8F1622VS020EC 16KB 2KB 46 24 4 12 1 1 2 PLCC 68 pin package Automotive Industrial Temperature 40 to 125 C Z8F1621PM020AC 16KB 2KB 29 23 3 8 1 1 2 PDIP 40 pin package Z8F1621AN020AC 16KB 2KB 31 23 3 8 1 1 2 LQFP 44 pin package Z8F 1621 VNO20AC 16KB 2KB 31 23 3 8 1 1 2 PLCC 44 pin package Z8F1622AR020AC 16KB 2KB 46 24 4 12 1 1 2 LQFP 64 pin package Z8F1622VS020AC 16KB 2KB 46 24 4 12 1 1 2 PLCC 68 pin package Z8F64200100KIT Development Kit Note Replace C with G for lead free packaging For technical and customer support hardware and software development tools visit the ZiLOG web site at www zilog com The latest released version of ZDS can be down loaded from this site PS019915 1005 htt p ww xi npi an net uU D
252. he destination operand is dst and a con dition code is cc Table 124 Arithmetic Instructions Mnemonic Operands Instruction ADC dst src Add with Carry ADCX dst src Add with Carry using Extended Addressing ADD dst src Add ADDX dst src Add using Extended Addressing CP dst src Compare CPC dst src Compare with Carry CPCX dst src Compare with Carry using Extended Addressing CPX dst src Compare using Extended Addressing DA dst Decimal Adjust DEC dst Decrement DECW dst Decrement Word INC dst Increment INCW dst Increment Word MULT dst Multiply PS019915 1005 eZ8 CPU Instruction Set htt p ww xi npi an net ugagamBpmmuagdisqiaudtt Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Zi ZiLOG Table 124 Arithmetic Instructions Continued Mnemonic Operands Instruction SBC dst src Subtract with Carry SBCX dst src Subtract with Carry using Extended Addressing SUB dst src Subtract SUBX dst src Subtract using Extended Addressing Table 125 Bit Manipulation Instructions Mnemonic Operands Instruction BCLR bit dst Bit Clear BIT p bit dst Bit Set or Clear BSET bit dst Bit Set BSWAP dst Bit Swap CCF Complement Carry Flag RCF Reset Carry Flag SCF Set Carry Flag TCM dst src Test Complement Under Mask TCMX dst
253. he interrupt requests for both vectored and polled interrupts When a request is presented to the interrupt controller the corresponding bit in the IRQO register becomes 1 If interrupts are globally enabled vec tored interrupts the interrupt controller passes an interrupt request to the eZ8 CPU If interrupts are globally disabled polled interrupts the eZ8 CPU can read the Interrupt Request 0 register to determine if any interrupt requests are pending Table 24 Interrupt Request 0 Register IRQO BITS 7 6 5 4 3 2 1 0 FIELD T2I THE TOI UORXI UOTXI I2CI SPII ADCI RESET 0 R W R W ADDR FCOH PS019915 1005 Interrupt Controller htt p ww xi npi an net ee ee EU og 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z ZiLOG T21 Timer 2 Interrupt Request 0 No interrupt request is pending for Timer 2 1 An interrupt request from Timer 2 is awaiting service T1I Timer 1 Interrupt Request 0 No interrupt request is pending for Timer 1 1 An interrupt request from Timer 1 is awaiting service TOI Timer 0 Interrupt Request 0 No interrupt request is pending for Timer 0 1 An interrupt request from Timer 0 is awaiting service UORXI UART 0 Receiver Interrupt Request 0 No interrupt request is pending for the UART 0 receiver 1 An interrupt request from the UART 0 receiver is awaiting ser
254. hin the Z8 Encore 64K Series controls Reset and STOP Mode Recovery operation In typical operation the following events cause a Reset to occur Power On Reset POR e Voltage Brown Out VBO e Watch Dog Timer time out when configured via the WDT RES Option Bit to initiate a Reset e External RESET pin assertion e On Chip Debugger initiated Reset OCDCTL 0 set to 1 When the 64K Series devices are in STOP mode a STOP Mode Recovery is initiated by either of the following e Watch Dog Timer time out e GPIO Port input pin transition on an enabled STOP Mode Recovery source e DBG pin driven Low Reset Types The 64K Series provides two different types of reset operation System Reset and STOP Mode Recovery The type of Reset is a function of both the current operating mode of the 64K Series devices and the source of the Reset Table 8 lists the types of Reset and their operating characteristics Table 8 Reset and STOP Mode Recovery Characteristics and Latency Reset Characteristics and Latency Reset Type Control Registers eZ8 CPU Reset Latency Delay System Reset Reset as applicable Reset 66 WDT Oscillator cycles 16 System Clock cycles STOP Mode Unaffected except Reset 66 WDT Oscillator cycles 16 System Clock cycles Recovery WDT_CTL register PS019915 1005 Reset and STOP Mode Recovery htt p ww xi npi an net ugagamBpmmuagdisqiaudtt Ooo 010 62245566 13810019655
255. i npi an net EE Interrupt Request 0 IRQO FCOH Read Write D7 D6 D5 D4 D3 D2 D1 DO L ADC Interrupt Request ___ SPI Interrupt Request I2C Interrupt Request UART 0 Transmitter Interrupt Request UART 0 Receiver Interrupt Request Timer 0 Interrupt Request Timer 1 Interrupt Request Timer 2 Interrupt Request For all of the above peripherals 0 Peripheral IRQ is not pending 1 Peripheral IRQ is awaiting service IRQO Enable High Bit IRQOENH FC1H Read Write D7 D6D5 D4ID3D2D1 DO ADC IRQ Enable Hit Bit L SPI IRQ Enable High Bit ______ DC IRQ Enable High Bit UART 0 Transmitter IRQ Enable High UART 0 Receiver IRQ Enable High Bit Timer 0 IRQ Enable High Bit Timer 1 IRQ Enable High Bit Timer 2 IRQ Enable High Bit PS019915 1005 Z8 Encore 64K Series Z8 Encore ZiLOG IRQO Enable Low Bit IRQOENL FC2H Read Write D7 D6 DSIDA4 D3 D2 DI DO L ADC IRQ Enable Hit Bit C SPI IRQ Enable Low Bit L DC IRQ Enable Low Bit UART 0 Transmitter IRQ Enable Low UART 0 Receiver IRQ Enable Low Bit Timer 0 IRQ Enable Low Bit Timer 1 IRQ Enable Low Bit Timer 2 IRQ Enable Low Bit Interrupt Request 1 IRQI FC3H Read Write D7 D6 D5 DA4ID3 D2 D1 DO
256. iLOG If the current ADC Analog Input is not the highest numbered input to be converted DMA_ADC initiates data conversion in the next higher numbered ADC Analog Input Configuring DMA_ADC for Data Transfer Follow these steps to configure and enable DMA_ADC 1 Write the DMA_ADC Address register with the 7 most significant bits of the Register File address for data transfers 2 Write to the DMA_ADC Control register to complete the following Enable the DMA ADC interrupt request if desired Select the number of ADC Analog Inputs to convert Enable the DMA_ADC channel AN Caution When using the DMA_ADC to perform conversions on multiple ADC in puts the Analog to Digital Converter must be configured for SINGLE SHOT mode If the ADC IN field in the DMA_ADC Control Register is greater than 000b the ADC must be in SINGLE SHOT mode CONTINUOUS mode operation of the ADC can only be used in conjunc tion with DMA ADC if the ADC IN field in the DMA ADC Control Register is reset to 000b to enable conversion on ADC Analog Input 0 only DMA Control Register Definitions DMAx Control Register The DMAx Control register Table 76 enables and selects the mode of operation for DMAx PS019915 1005 Direct Memory Access Controller htt p ww xi npi an net ugagamBpmmuagdisqiaudtt Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification L ZiLOG Table 76 DMAx Control
257. icates whether a 10 or 7 bit address is being transmitted After the START bit is set if the five most significant bits of the address are 11110B this bit is set When set it is reset once the first byte of the address has been sent RD Read This bit indicates the direction of transfer of the data It is active high during a read The status of this bit is determined by the least significant bit of the PC Shift register after the START bit is set TAS Transmit Address State This bit is active high while the address is being shifted out of the PC Shift register DSS Data Shift State This bit is active high while data is being shifted to or from the PC Shift register NCKI NACK Interrupt This bit is set high when a Not Acknowledge condition is received or sent and neither the START nor the STOP bit is active When set this bit generates an interrupt that can only be cleared by setting the START or STOP bit allowing the user to specify whether he wants to perform a STOP or a repeated START PS019915 1005 I2C Controller htt p ww xi npi an net DOT 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Zi ZiLOG I2C Control Register The PC Control register Table 71 enables the PC operation Table 71 I C Control Register IZCCTL BITS 7 6 5 4 3 2 1 0 FIELD IEN START STOP BIRQ TXI NAK FLUSH FILTEN
258. ilable in 44 pin packages PD2 N A No alternate function PD3 DEI UART 1 Driver Enable PD4 RXD1 IRRX1 UART 1 IrDA 1 Receive Data PD5 TXDI IRTXI UART 1 IrDA 1 Transmit Data PD6 CTSI UART 1 Clear to Send PD7 RCOUT Watch Dog Timer RC Oscillator Output Port E PE 7 0 N A No alternate functions Port F PF 7 0 N A No alternate functions Port G PG 7 0 N A No alternate functions PortH PHO ANA8 ADC Analog Input 8 PHI ANA9 ADC Analog Input 9 PH2 ANAIO ADC Analog Input 10 PH3 ANAII ADC Analog Input 11 GPIO Interrupts Many of the GPIO port pins can be used as interrupt sources Some port pins may be con figured to generate an interrupt request on either the rising edge or falling edge of the pin input signal Other port pin interrupts generate an interrupt when any edge occurs both rising and falling Refer to the Interrupt Controller chapter for more information on interrupts using the GPIO pins GPIO Control Register Definitions Four registers for each Port provide access to GPIO control input data and output data Table 13 lists these Port registers Use the Port A H Address and Control registers together to provide access to sub registers for Port configuration and control PS019915 1005 htt p ww xi npi an net General Purpose I O uu IG1 D U DLE 010 62245566 13810019655 Z8 Encore 64K Series Product Specification L ZiLOG Table 13 GPIO Port Registers and Sub Regis
259. ime 0 PS019915 1005 Electrical Characteristics htt p ww xi npi an net OR ee DE EET HS o a 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 231 ZiLOG UART Timing Figure 56 and Table 119 provide timing information for UART pins for the case where the Clear To Send input pin CTS is used for flow control In this example it is assumed that the Driver Enable polarity has been configured to be Active Low and is represented here by DE The CTS to DE assertion delay T1 assumes the UART Transmit Data register has been loaded with data prior to CTS assertion CT X 0 0 0 0 0Q0 L Input mo M Output T2 i T3 lt _ gt e TXD l V s mi p Output Stan Bt oX Bi Xe 7 Party k End of Stop Bit s Figure 56 UART Timing with CTS Table 119 UART Timing with CTS Delay ns Parameter Abbreviation Minimum Maximum Ty CTS Fall to DE Assertion Delay 2 XIN period 2 XIN period 1 Bit period T5 DE Assertion to TXD Falling Edge Start Delay 1 Bit period 1 Bit period XIN period T3 End of Stop Bit s to DE Deassertion Delay XIN period 2 XIN period PS019915 1005 Electrical Characteristics htt p ww xi npi an net LEE EB DRE EL EE EGET ET VE Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 232 ZiLOG Figure 57 and T
260. ing 0 4 bytes of the instruction are read from Program Memory This command is useful for stepping over instructions where the first byte of the instruction has been overwritten by a Breakpoint If the device is not in DEBUG mode or the Read Protect Option Bit is enabled the OCD ignores this command DBG 11H DBG lt opcode 7 0 Execute Instruction 12H The Execute Instruction command allows sending an entire instruction to be executed to the eZ8 CPU This command can also step over Breakpoints The number of bytes to send for the instruction depends on the opcode If the device is not in DEBUG mode or the Read Protect Option Bit is enabled the OCD ignores this command DBG lt 12H DBG 1 5 byte opcode On Chip Debugger Control Register Definitions OCD Control Register The OCD Control register Table 101 controls the state of the On Chip Debugger This register enters or exits DEBUG mode and enables the BRK instruction It can also reset the Z8F642x familyZ8R642x family device PS019915 1005 On Chip Debugger htt p ww xi npi an net DOT 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Zi ZiLOG A reset and stop function can be achieved by writing 81H to this register A reset and go function can be achieved by writing 41H to this register If the device is in DEBUG mode a run function can be implemented by writing 40H to this regist
261. ing Bit 1 of 1st address byte 10 bit addressing Bit 0 R W of 1st address byte 10 bit addressing Acknowledge state for 1st address byte 10 bit addressing Bit 7 of 2nd address byte 7 bit addressing Bit 7 of address byte 10 bit addressing Bit 6 of 2nd address byte 7 bit addressing Bit 6 of address byte 10 bit addressing Bit 5 of 2nd address byte 7 bit addressing Bit 5 of address byte 10 bit addressing Bit 4 of 2nd address byte 7 bit addressing Bit 4 of address byte 10 bit addressing Bit 3 of 2nd address byte 7 bit addressing Bit 3 of address byte 10 bit addressing Bit 2 of 2nd address byte 7 bit addressing Bit 2 of address byte 10 bit addressing Bit 1 of 2nd address byte 7 bit addressing Bit 1 of address byte 12C Controller OR ee DE EET HS o a 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 160 ZiLOoG IC Diagnostic Control Register The C Diagnostic register Table 75 provides control over diagnostic modes This regis ter is a read write register used for PC diagnostics Table 75 I2C Diagnostic Control Register I2ZCDIAG BITS 7 6 5 4 3 2 1 0 FIELD Reserved DIAG RESET 0 R W R R W ADDR F56H DIAG Diagnostic Control Bit Selects read back value of the Baud Rate Reload regis ters 0 Normal mode Reading the Baud Rate High and Low Byte registers returns the baud rate reload value 1 Diagnostic mode
262. ing GPIO 226 power supply signals 15 power down automatic ADC 172 power on and voltage brown out 219 power on reset POR 44 PS019915 1005 Z8 Encore 64K Series Product Specification Zi ZiLOG problem description or suggestion 269 product information 269 program control instructions 241 program counter 236 program memory 18 PUSH 240 push using extended addressing 240 PUSHX 240 PWM mode 89 PxADDR register 55 PxCTL register 56 Q QFP 261 R R 235 r 235 RA register address 235 RCF 239 240 receive 10 bit data format I2C 150 7 bit data transfer format I2C 149 IrDA data 122 receive interrupt 141 receiving UART data interrupt driven method 103 receiving UART data polled method 102 register 136 165 235 ADC control ADCCTL 175 ADC data high byte ADCDH 176 ADC data low bits ADCDL 176 baud low and high byte I2C 156 158 160 baud rate high and low byte SPI 138 control SPI 133 control I2C 155 data SPI 133 DMA status DMAA STAT 169 DMA ADC address 167 DMA ADC control DMAACTL 168 DMAx address high nibble DMAxH 165 DMAx control DMAxCTL 164 Index htt p ww xi npi an net DEL EY EC BRE UE IMOO000000 010 62245566 13810019655 DMAx end address low byte DMAxEND 167 DMAx start current address low byte register DMAxSTART 166 flash control FCTL 185 flash high and low byte FFREQH and FRE EQL 189 flash page select FPS 187 flash status FS
263. ion 0 Reset to 0 Unaffected 1 Set to 1 X Undefined PS019915 1005 eZ8 CPU Instruction Set htt p ww xi npi an net o EL ELE E FQ 010 62245566 13810019655 Uu UU Z8 Encore 64K Series Product Specification ziLog Table 132 eZ8 CPU Instruction Summary Continued Assembly IRURE EN Opcode s rae Fetch Instr Mnemonic Symbolic Operation dst src Hex C Z S V D H Cycles Cycles SBC dst src dst lt dst src C r r 32 EE E SEL MN 2 3 r Ir 33 2 4 R R 34 3 3 R IR 35 3 4 R IM 36 3 3 IR IM 37 3 4 SBCX dst src dst lt dst src C ER ER 38 WU ok o ow po Y 4 3 ER IM 39 4 3 SCF Cel DF l o e 1 2 SRA dst r1 R DO c o 00 9 03 2 2 a B ws SRL dst 7 R 1F CO 0 3 2 IR IFCI 3 8 SRP src RP lt src IM 01 JE eee 2 2 STOP STOP Mode 6F AM o 1 2 SUB dst src dst lt dst src r r 22 o c om ow qo ox 2 3 r Ir 23 2 4 R R 24 3 3 R IR 25 3 4 R IM 26 3 3 IR IM 21 3 4 SUBX dst src dst lt dst src ER ER 28 woo ow cw o ow 4 3 ER IM 29 4 3 SWAP dst dst 7 4 dst 3 0 R F0 X X 2 2 IR Fl 2 3 Flags Notation Value is a function of the result of the operation 0 Reset to 0 Unaffected 1 Set to 1 X Undefined PS019915 1005 eZ8 CPU Instruction Set htt p ww xi npi an net o ee ee a og 010 62245566 13810019655
264. ion Bit is enabled then only writes to the Flash Control Registers are allowed and all other register write data values are discarded DBG lt 08H DBG lt 4 hO Register Address 11 8 DBG lt Register Address 7 0 DBG Size 7 0 DBG 1 256 data bytes Read Register 09H The Read Register command reads data from the Register File Data can be read 1 256 bytes at a time 256 bytes can be read by setting size to zero If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled this command returns FFH for all the data values DBG lt 09H DBG 4 hO Register Address 11 8 DBG Register Address 7 0 DBG Size 7 0 DBG 1 256 data bytes Write Program Memory 0AH The Write Program Memory command writes data to Program Memory This command is equivalent to the LDC and LDCI instructions Data can be written 1 65536 bytes at a time 65536 bytes can be written by setting size to zero The on chip Flash Controller must be written to and unlocked for the PS019915 1005 On Chip Debugger htt p ww xi npi an net EE HHHEHEHIGBUHBBHBHH 010 62245566 13810019655 Z8 Encore 64K Series Product Specification L a ZiLOG programming operation to occur If the Flash Controller is not unlocked the data is discarded If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled the data is discarded DBG lt OAH DBG P
265. irect Address Addrs Addrs represents a number in the range of 0000H to FFFFH ER Extended Addressing Register Reg Reg represents a number in the range of 000H to FFFH IM Immediate Data Data Data is a number between 00H to FFH Ir Indirect Working Register Rn n 0 15 IR Indirect Register Reg Reg represents a number in the range of 00H to FFH Irr Indirect Working Register Pair RRp p 0 2 4 6 8 10 12 or 14 IRR Indirect Register Pair Reg Reg represents an even number in the range 00H to FEH p Polarity p Polarity is a single bit binary value of either OB or 1B T Working Register Rn n 0 15 R Register Reg Reg represents a number in the range of 00H to FFH RA Relative Address X X represents an index in the range of 127 to 128 which is an offset relative to the address of the next instruction Tr Working Register Pair RRp p 0 2 4 6 8 10 12 or 14 RR Register Pair Reg Reg represents an even number in the range of 00H to FEH Vector Vector Address Vector Vector represents a number in the range of 00H to FFH X Indexed Index The register or register pair to be indexed is offset by the signed Index value Index in a 127 to 128 range Table 122 contains additional symbols that are used throughout the Instruction Summary and Instruction Set Description sections PS019915 1005 htt p ww xi npi an net EE eZ8 CPU Instruction Set TENENT Ig1 H ELO U f 010 62245566 13810019655
266. it WDT Watch Dog Timer Time Out Indicator If this bit is set to 1 a WDT time out occurred A Power On Reset resets this pin A STOP Mode Recovery from a change in an input pin also resets this bit Reading this register resets this bit EXT External Reset Indicator If this bit is set to 1 a Reset initiated by the external RESET pin occurred A Power On Reset or a STOP Mode Recovery from a change in an input pin resets this bit Reading this register resets this bit Reserved These bits are reserved and must be 0 SM STOP Mode Configuration Indicator 0 Watch Dog Timer and its internal RC oscillator will continue to operate in STOP Mode 1 Watch Dog Timer and its internal RC oscillator will be disabled in STOP Mode Watch Dog Timer Reload Upper High and Low Byte Registers The Watch Dog Timer Reload Upper High and Low Byte WDTU WDTH WDTL reg isters Tables 48 through 50 form the 24 bit reload value that is loaded into the Watch Dog Timer when a WDT instruction executes The 24 bit reload value is WDTU 7 0 WDTH 7 0 WDTL 7 0 Writing to these registers sets the desired Reload Value Read ing from these registers returns the current Watch Dog Timer count value PS019915 1005 Watch Dog Timer htt p ww xi npi an net ugagamBpmmuagdisqiaudtt Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z
267. it Compare value PS019915 1005 htt p ww xi npi an net D U Uu Ul Timers 010 62245566 13810019655 86 Z8 Encore 64K Series Product Specification ZiLOG Timer 0 3 PWM High and Low Byte Registers The Timer 0 3 PWM High and Low Byte TXPWMH and TxPWML registers Tables 42 and 43 are used for Pulse Width Modulator PWM operations These registers also store the Capture values for the Capture and Capture COMPARE modes Table 42 Timer 0 3 PWM High Byte Register TxPWMH BITS 7 6 5 4 3 2 1 0 FIELD PWMH RESET 0 R W R W ADDR F04H FOCH F14H FICH Table 43 Timer 0 3 PWM Low Byte Register TxPWML BITS 7 6 5 4 3 2 1 0 FIELD PWML RESET 0 R W R W ADDR F05H FODH F15H FIDH PWMH and PWML Pulse Width Modulator High and Low Bytes These two bytes PWMH 7 0 PWML 7 0 form a 16 bit value that is compared to the current 16 bit timer count When a match occurs the PWM output changes state The PWM output value is set by the TPOL bit in the Timer Control 1 Register TXCTL 1 regis ter The TxPWMH and TxPWML registers also store the 16 bit captured timer value when operating in Capture or Capture COMPARE modes PS019915 1005 Timers 87 htt p ww xi npi an net o ee ee a og 010 62245566 13810019655
268. ive Data UORXD XX 110 F41 UARTO Status 0 UOSTATO 0000011Xb 110 F42 UARTO Control 0 UOCTLO 00 112 F43 UARTO Control 1 UOCTLI 00 112 F44 UARTO Status 1 UOSTATI 00 110 F45 UARTO Address Compare Register UOADDR 00 115 F46 UARTO Baud Rate High Byte UOBRH FF 115 F47 UARTO Baud Rate Low Byte UOBRL FF 115 UART 1 F48 UARTI Transmit Data UITXD XX 109 UARTI Receive Data UIRXD XX 110 F49 UARTI Status 0 UISTATO 0000011Xb 110 F4A UARTI Control 0 UICTLO 00 112 FAB UART I Control 1 UICTLI 00 112 FAC UARTI Status 1 UISTATI 00 110 F4D UARTI Address Compare Register ULADDR 00 115 F4E UARTI Baud Rate High Byte UIBRH FF 115 FAF UARTI Baud Rate Low Byte UIBRL FF 115 rc F50 IC Data I2CDATA 00 152 F51 IC Status I2CSTAT 80 153 F52 C Control DCCTL 00 155 F53 IC Baud Rate High Byte I2CBRH FF 156 F54 1 C Baud Rate Low Byte I2CBRL FF 156 F55 rc Diagnostic State I2CDST CO 158 F56 PC Diagnostic Control I2CDIAG 00 160 F57 F5F Reserved XX XX Undefined PS019915 1005 Register File Address Map htt p ww xi npi an net o uam ai ood L 010 62245566 13810019655 Table 7 64K Series Register File Address Map Continued Z8 Encore 64K Series Product Specification Zi ZiLOG Address Hex Register Description Mnemonic Reset Hex Page Serial Peripheral Interface SPI F
269. ken from the GPIO Port pin Timer Input alternate function The TPOL bit in the Timer Control 1 Register selects whether the count occurs on the rising edge or the falling edge of the Timer Input signal In COUNTER mode the prescaler is disabled AN Caution The input frequency of the Timer Input signal must not exceed one fourth the system clock frequency Upon reaching the Reload value stored in the Timer Reload High and Low Byte registers the timer generates an interrupt the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes Also if the Timer Output alternate function is enabled the Timer Output pin changes state from Low to High or from High to Low at timer Reload The steps for configuring a timer for COUNTER mode and initiating the count are as fol lows 1 Write to the Timer Control 1 register to Disable the timer Configure the timer for COUNTER mode PS019915 1005 Timers htt p ww xi npi an net DOTA 010 62245566 13810019655 Z8 Encore 64K Series Product Specification VAF ZiLOG Select either the rising edge or falling edge of the Timer Input signal for the count This also sets the initial logic level High or Low for the Timer Output alternate function However the Timer Output function does not have to be enabled 2 Write to the Timer High and Low Byte registers to set the starting count value This only affects the first
270. l Purpose I O 010 62245566 13810019655 IG i uu UU Z8 Encore 64K Series Product Specification Z ZiLOG Table 20 Port A H STOP Mode Recovery Source Enable Sub Registers BITS 7 6 5 4 3 2 1 0 FIELD PSMRE7 PSMRE6 PSMRES PSMRE4 PSMRE3 PSMRE2 PSMREI PSMREO RESET o R W ROK ADDR If 05H in Port A H Address Register accessible through Port A H Control Register PSMRE 7 0 Port STOP Mode Recovery Source Enabled 0 The Port pin is not configured as a STOP Mode Recovery source Transitions on this pin during STOP mode do not initiate STOP Mode Recovery 1 The Port pin is configured as a STOP Mode Recovery source Any logic transition on this pin during STOP mode initiates STOP Mode Recovery Port A H Input Data Registers Reading from the Port A H Input Data registers Table 21 returns the sampled values from the corresponding port pins The Port A H Input Data registers are Read only Table 21 Port A H Input Data Registers PxIN BITS 7 6 5 4 3 2 1 0 FIELD PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PINI PINO RESET X R W R ADDR FD2H FD6H FDAH FDEH FE2H FE6H FEAH FEEH PIN 7 0 Port Input Data Sampled data from the corresponding port pin input 0 Input data is logical 0 Low 1 Input data is logical 1 High PS019915 1005 htt p ww xi npi an net General
271. l resistor For very small values of C the parasitic capacitance of the oscillator XIN pin and the printed circuit board should be included in the estimation of the oscillator frequency It is possible to operate the RC oscillator using only the parasitic capacitance of the pack age and printed circuit board To minimize sensitivity to external parasitics external capacitance values in excess of 20pF are recommended PS019915 1005 On Chip Oscillator htt p ww xi npi an net EE HHHEHEHIGBUHBBHBHH 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z a ZiLOG 1750 Frequency kHz DS e e eo 1500 1250 1000 750 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 420 440 460 480 500 C pF Figure 42 Typical RC Oscillator Frequency as a Function of the External Capacitance with a 45kQ Resistor AN Caution PS019915 1005 htt p ww xi npi an net When using the external RC oscillator mode the oscillator may stop oscil lating if the power supply drops below 2 7V but before the power supply drops to the voltage brown out threshold The oscillator will resume oscil lation as soon as the supply voltage exceeds 2 7V On Chip Oscillator LEER ETONE eo 010 62245566 13810019655 Electrical Characteristics Absolute Maximum Ratings Z8 Product Specifi
272. lable for the Z8X1622 Z8X2422 Z8X3222 Z8X4822 and Z8X6422 devices MILLIMETER SYMBOL MIN MAX 1 40 1 60 0 05 0 15 1 35 145 0 17 0 27 DETAIL A J LE i z LE 1 00 REF 0 039 REF 1 CONTROLLING DIMENSIONS mm 2 MAX COPLANARITY 0 10mm 0 004 i E 1 T7 DETAIL A Figure 65 64 Lead Low Profile Quad Flat Package LQFP PS019915 1005 Packaging htt p ww xi npi an net ugagamBpmmuagdisqiaudtt Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification L a ZiLOG Figure 66 illustrates the 68 pin PLCC plastic lead chip carrier package available for the Z8X1622 Z8X2422 Z8X3222 Z8X4822 and Z8X6422 devices Figure 66 68 Lead Plastic Lead Chip Carrier Package PLCC PS019915 1005 Packaging htt p ww xi npi an net COA PSEPENED UBL ELET DIT 010 62245566 13810019655 Z8 Encore 64K Series Product Specification L a ZiLOG Figure 67 illustrates the 80 pin QFP quad flat package available for the Z8X4823 and Z8X6423 devices HD r D i SYMBOL MILLIMETER INCH MIN MAX i A1 004 015 A2 102 110 b 012 018 005 008 E HE HD 933 951 D 783 791 HE 697 715 E 547 555 1 e 0315 BSC t 028 043 DETAIL A NOTES 1 CONTROLLING DIMENSIONS MILLIMETER 2 LEAD COPLANARITY MAX 10 004 y E i 9710 DETAIL A Figure 67 80 Lead Quad Flat Package QFP PS01
273. lat Package LQFP 9 64K Series in 64 Pin Low Profile Quad Flat Package LQFP 10 64K Series in 68 Pin Plastic Leaded Chip Carrier PLCC 11 64K Series in 80 Pin Quad Flat Package QFP 000008 12 Power On Reset Operation 0 0 cece cece eee tenes 45 Voltage Brown Out Reset Operation 0 0 0 c eee eee eee 46 GPIO Port Pin Block Diagram 2 0 0 0 eee eee eee ee eee 52 Interrupt Controller Block Diagram 0 0 0 0 c eee eee eee 64 Timer Block Diagram 0 0 0 ccc eee 76 UART Block Diagram eseeeeee III 99 UART Asynchronous Data Format without Parity 100 UART Asynchronous Data Format with Parity 100 UART Asynchronous MULTIPROCESSOR Mode Data Format 104 UART Driver Enable Signal Timing shown with 1 Stop Bit and Parity 0 0 0 0 ee ee 106 UART Receiver Interrupt Service Routine Flow 108 Infrared Data Communication System Block Diagram 120 Infrared Data Transmission seeeeeeeee e 122 Infrared Data Reception slsleseeeeeeeee e 123 SPI Configured as a Master in a Single Master Single Slave System 125 SPI Configured as a Master in a Single Master Multiple Slave System 126 SPI Configured as a Slave 0 2 eee eee eee 126 SPI Timing When PHASE is Q 2 2 0 eee eee eee 129 SPI Timing When PHASE is 1 1 2 0 2 eee ee
274. le High Bit C2ENH Port C2 Interrupt Request Enable High Bit C1ENH Port C1 Interrupt Request Enable High Bit COENH Port CO Interrupt Request Enable High Bit Table 35 IRQ2 Enable Low Bit Register IRQ2ENL BITS 7 6 5 4 3 2 1 0 FIELD T3ENL UIRENL UITENL DMAENL C3ENL C2ENL CIENL COENL RESET 0 R W R W ADDR FC8H T3ENL Timer 3 Interrupt Request Enable Low Bit UIRENL UART 1 Receive Interrupt Request Enable Low Bit UITENL UART 1 Transmit Interrupt Request Enable Low Bit DMAENL DMA Interrupt Request Enable Low Bit C3ENL Port C3 Interrupt Request Enable Low Bit C2ENL Port C2 Interrupt Request Enable Low Bit C1ENL Port C1 Interrupt Request Enable Low Bit COENL Port CO Interrupt Request Enable Low Bit Interrupt Edge Select Register PS019915 1005 htt p ww xi npi an net The Interrupt Edge Select IRQES register Table 36 determines whether an interrupt is generated for the rising edge or falling edge on the selected GPIO Port input pin The Interrupt Controller AOUN Uu UU 010 62245566 13810019655 Z8 Encore 64K Series Product Specification VA ZiLOG Interrupt Port Select register selects between Port A and Port D for the individual inter rupts Table 36 Interrupt Edge Select Register IRQES BITS 7 6 5 4 3 2 1 0 FIELD IES7 IES6 I
275. ling the Watch Dog Timer and its internal RC oscillator in STOP mode will provide some additional reduction in STOP mode cur rent consumption This small current reduction would be indistinquishable on the scale of Figure 48 o o E oO g i o 40 00 n e LL ELI em 20 00 M 0 00 ees Ses 3 0 3 2 3 4 3 6 Vdd V 25C Typical 0 70C 40 105C 40 4125C Figure 48 Maximum STOP Mode Idd with VBO Disabled versus Power Supply Voltage PS019915 1005 Electrical Characteristics htt p ww xi npi an net ugagamBmgmuagdisqiudtut Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Zi ZiLOG On Chip Peripheral AC and DC Electrical Characteristics Table 106 Power On Reset and Voltage Brown Out Electrical Characteristics and Timing T4 40 C to 125 C Symbol Parameter Minimum Typical Maximum Units Conditions Vpor Power On Reset Voltage 2 40 2 70 2 90 V Vpp VpoR Threshold Vygo _ Voltage Brown Out Reset 2 30 2 60 2 85 V Vpp Vypo Voltage Threshold Vpor to Vygo hysteresis 50 100 mV Starting Vpp voltage to Vss V ensure valid Power On Reset Tana Power On Reset Analog 50 a us Vpp gt Vpor Tpog Digital Delay Reset delay follows Tana Tpog Power On Reset Digital 6 6 e ms 66 WDT Oscillator cycles Delay 10KHz 16 System Clock cycles 2
276. ller to be used as an additional timer when the I2C Control ler is disabled This bit is ignored when the PC Controller is enabled 1 An interrupt occurs every time the baud rate generator counts down to one 0 No baud rate generator interrupt occurs TXI Enable TDRE interrupts This bit enables the transmit interrupt when the PC Data register is empty TDRE 1 1 Transmit interrupt and DMA transmit request is enabled 0 Transmit interrupt and DMA transmit request is disabled I2C Controller IG i uu UU 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 156 ZiLOoG NAK Send NAK This bit sends a Not Acknowledge condition after the next byte of data has been read from the C slave Once asserted it is deasserted after a Not Acknowledge is sent or the TEN bit is deasserted If this bit is 1 it cannot be cleared to 0 by writing to the register FLUSH Flush Data Setting this bit to 1 clears the PC Data register and sets the TDRE bit to 1 This bit allows flushing of the PC Data register when a Not Acknowledge interrupt is received after the data has been sent to the IC Data register Reading this bit always returns 0 FILTEN TC Signal Filter Enable This bit enables low pass digital filters on the SDA and SCL input signals These filters reject any input pulse with periods less than a full system clock cycle The filters introduce a 3 syst
277. lowest priority If all of the interrupts were enabled with identical interrupt priority all as Level 2 interrupts for example then interrupt priority would be assigned from highest to lowest as specified in Table 23 Level 3 interrupts always have higher priority than Level 2 interrupts which in turn always have higher priority than Level 1 interrupts Within each interrupt priority level Level 1 Level 2 or Level 3 priority is assigned as specified in Table 23 Reset Watch Dog Timer interrupt 1f enabled and Illegal Instruction Trap always have highest priority Interrupt Assertion Interrupt sources assert their interrupt requests for only a single system clock period sin gle pulse When the interrupt request is acknowledged by the eZ8 CPU the correspond ing bit in the Interrupt Request register is cleared until the next interrupt occurs Writing a 0 to the corresponding bit in the Interrupt Request register likewise clears the interrupt request AN Caution The following style of coding to clear bits in the Interrupt Request registers is NOT recommended All incoming interrupts that are received between execution of the first LDX command and the last LDX command are lost Poor coding style that can result in lost interrupt requests LDX r0 IRQO AND r0 MASK LDX IRQO r0 To avoid missing interrupts the following style of coding to clear bits in the Interrupt Request 0 register is recommended Good coding style that avoi
278. ltiplexed with a general purpose I O pin When the general purpose I O pin is configured for alternate function to enable the SDA function this pin is open drain SPI Controller SS IO Slave Select This signal can be an output or an input If the Z8 Encore 64K Series is the SPI master this pin may be configured as the Slave Select output If the Z8 Encore 64K Series is the SPI slave this pin is the input slave select It is multiplexed with a general purpose I O pin SCK IO SPI Serial Clock The SPI master supplies this pin If the Z8 Encore 64K Series is the SPI master this pin is an output If the Z8 Encore 64K Series is the SPI slave this pin is an input It is multiplexed with a general purpose I O pin PS019915 1005 Signal and Pin Descriptions htt p ww xi npi an net utu ee ee EU og 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z ZiLOG Table 3 Signal Descriptions Continued Signal Mnemonic VO Description MOSI IO Master Out Slave In This signal is the data output from the SPI master device and the data input to the SPI slave device It is multiplexed with a general purpose I O pin MISO IO Master In Slave Out This pin is the data input to the SPI master device and the data output from the SPI slave device It is multiplexed with a general purpose I O pin UART Controllers TXDO0 TXD1 O Transmit Data Thes
279. ly when MULTIPROCESSOR 9 bit mode is enabled 0 Send a 0 in the multiprocessor bit location of the data stream 9th bit 1 Send a 1 in the multiprocessor bit location of the data stream 9th bit DEPOL Driver Enable Polarity 0 DE signal is Active High 1 DE signal is Active Low BRGCTL Baud Rate Control This bit causes different UART behavior depending on whether the UART receiver is enabled REN 1 in the UART Control 0 Register When the UART receiver is not enabled this bit determines whether the Baud Rate Gener ator issues interrupts 0 Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value 1 The Baud Rate Generator generates a receive interrupt when it counts down to 0 Reads from the Baud Rate High and Low Byte registers return the current BRG count value When the UART receiver is enabled this bit allows reads from the Baud Rate Registers to return the BRG count value instead of the Reload Value 0 Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value 1 Reads from the Baud Rate High and Low Byte registers return the current BRG count value Unlike the Timers there is no mechanism to latch the High Byte when the Low Byte is read RDAIRQ Receive Data Interrupt Enable 0 Received data and receiver errors generates an interrupt request to the Interrupt Con troller 1 Received data does not generate an interrupt request to the Interrupt Controller
280. mately receives the data The UART is only synchronized to the incoming data stream when a Start bit is received PS019915 1005 Infrared Encoder Decoder htt p ww xi npi an net LEE EB DRE EL EE EGET ET VE Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 124 ZiLOG Infrared Encoder Decoder Control Register Definitions All Infrared Endec configuration and status information is set by the UART control regis ters as defined beginning on page 109 AN Caution To prevent spurious signals during IrDA data transmission set the IREN bit in the UARTx Control 1 register to 1 to enable the Infrared Encoder Decoder before enabling the GPIO Port alternate function for the corre sponding pin PS019915 1005 Infrared Encoder Decoder htt p ww xi npi an net ugmumgmngumnuigdiBui Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 125 ZiLOG Serial Peripheral Interface Overview The Serial Peripheral Interface SPI is a synchronous interface allowing several SPI type devices to be interconnected SPI compatible devices include EEPROMs Analog to Digital Converters and ISDN devices Features of the SPI include e Full duplex synchronous character oriented communication e Four wire interface e Data transfers rates up to a maximum of one half the system clock frequency
281. n Summary ssseeeeeeee teen eee 242 Blass Register 12s Etui ace Saee soe drei pace d uic at deu ies dake Geo 252 Opcode Maps hr rer mhi hh rema y ee s Ra xa Ra ERE E ES 253 Packaging 2 2 9 22 9 9 9 sae one cha eee sa eee mea ace e mes aed RENE PAM ses 257 Ordering Information e rh e e hr rhe EP PR E T TREE TES 262 Part Number Suffix Designations 0 0 0 eect eee 267 Document Information 0 0c eee nett eens 268 Customer Feedback Form 0 0 cece eee eee E 269 Index 22 99999 yo x SOE EE RSW SEES E E ETE TE ECR FEE ERN ES 270 PS019915 1005 Table of Contents htt p ww xi npi an net DOT 010 62245566 13810019655 Z8 Encore 64K Series Product Specification List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 PS019915 1005 htt p ww xi npi an net ZiLOG Z8 Encore 64K Series Block Diagram 00 00 00 e eee ee 3 64K Series in 40 Pin Dual Inline Package PDIP 7 64K Series in 44 Pin Plastic Leaded Chip Carrier PLCC 8 64K Series in 44 Pin Low Profile Quad F
282. n regarding the physical package specifications please refer to Packaging on page 257 Available Packages Table 2 identifies the package styles that are available for each device within the Z8 Encore 64K Series product line Table 2 Z8 Encore 64K Series Package Options 40 Pin 44 pin 44 pin 64 pin 68 pin 80 pin Part Number PDIP LQFP PLCC LQFP PLCC QFP Z8F1621 X X X Z8F1622 X X Z8F2421 X X X Z8F2422 X X Z8F3221 X X X Z8F3222 X X Z8F4821 X X X Z8F4822 X X Z8F4823 X Z8F6421 X X X Z8F6422 X X Z8F6423 X PS019915 1005 Signal and Pin Descriptions htt p ww xi npi an net utu ee ee EU og 010 62245566 13810019655 Pin Configurations Z8 Encore 64K Series Product Specification ZiLOG Figures 2 through 7 illustrate the pin configurations for all of the packages available in the 64K Series Refer to Table 3 for a description of the signals Timer 3 is not available in the 40 pin and 44 pin packages PA1 TOOUT Note Timer 3 is not supported PD4 RXD1 PD3 DE1 PC5 MISO PA3 CTS0 PA2 DEO 5 PAO TOIN PC2 SS RESET VDD VSS PD1 PDO XOUT XIN AVDD PBO ANAO PB1 ANA1 PB4 ANA4 PB5 ANA5 20 15 40 35 30 25 21 PD5 TXD1 PC4 MOSI PA4 RXDO PA5 TXDO PA6 SCL PA7 SDA PD6 CTS1 PC3 S
283. n the ADC Control register can be written simultaneously Write to the ANAIN 3 0 field to select one of the 12 analog input sources Clear CONT to 0 to select a single shot conversion Write to the VREF bit to enable or disable the internal voltage reference generator Set CEN to 1 to start the conversion 3 CEN remains 1 while the conversion is in progress A single shot conversion requires 5129 system clock cycles to complete If a single shot conversion is requested from an ADC powered down state the ADC uses 40 additional clock cycles to power up before beginning the 5129 cycle conversion 4 When the conversion is complete the ADC control logic performs the following operations 10 bit data result written to ADCD_H 7 0 ADCD L 7 6 CEN resets to 0 to indicate the conversion is complete An interrupt request is sent to the Interrupt Controller 5 Ifthe ADC remains idle for 160 consecutive system clock cycles it is automatically powered down Continuous Conversion When configured for continuous conversion the ADC continuously performs an analog to digital conversion on the selected analog input Each new data value over writes the previous value stored in the ADC Data registers An interrupt is generated after each con version AN Caution In CONTINUOUS mode users must be aware that ADC updates are lim ited by the input signal bandwidth of the ADC and the latency of the ADC and its digital filter Step chan
284. ncore 64K Series Product Specification ZiLOG Assembly DESEE Opcode s PRO Fetch Instr Mnemonic Symbolic Operation dst src Hex C Z S V D H Cycles Cycles BTJNZ bit src dst if src bit 1 r F6 o 3 3 PC lt PC X Ir E 3 4 BTJZ bit src dst if src bit O r F6 JE L S LZ 3 3 PC lt PC X Ir 3 4 CALL dst SP lt SP 2 IRR D4 AME o 2 6 M poi DA D6 3 cd CCF C C EF o 0 0 0 c 1 2 CLR dst dst 00H R BO AME o 2 2 IR Bl 2 3 COM dst dst dst R 60 0 2 2 IR 61 2 3 CP dst sre dst src r r A2 WU oes oU ORO xo 2 3 r Ir A3 2 4 R R A4 3 3 R IR AS 3 4 R IM A6 3 3 IR IM A7 3 4 CPC dst src dst src C r r 1F A2 o E DE 0 a 3 3 r Ir IF A3 3 4 R R IF A4 4 3 R IR IF A5 4 4 R IM 1F A6 4 3 IR IM IF A7 4 4 CPCX dst src dst src C ER ER 1F A8 Wo uw OW mS x 5 3 ER IM 1F A9 5 3 Flags Notation Value is a function of the result of the operation 0 Reset to 0 Unaffected I Set to 1 X Undefined PS019915 1005 eZ8 CPU Instruction Set htt p ww xi npi an net o ee ee a og 010 62245566 13810019655 244 Z8 Encore 64K Series Product Specification 245 ZiLOG Table 132 eZ8 CPU Instruction Summary Continued Address Mode Flags Assembly Opc
285. nd AV ss must be properly grounded The DBG pin is open drain and must have an external pull up resistor to ensure proper operation Reset RESET I RESET Generates a Reset when asserted driven Low Power Supply VDD I Power Supply AVDD I Analog Power Supply VSS I Ground AVSS I Analog Ground PS019915 1005 Signal and Pin Descriptions htt p ww xi npi an net o ee ee a og 010 62245566 13810019655 Z8 Encore 64K Series Product Specification VA ZiLOG Pin Characteristics Table 4 provides detailed information on the characteristics for each pin available on the 64K Series products Data in Table 4 is sorted alphabetically by the pin symbol mne monic Table 4 Pin Characteristics of the 64K Series Active Low Internal Schmitt Symbol Reset or Tri State Pull upor Trigger Open Drain Mnemonic Direction Direction Active High Output Pull down Input Output AVSS N A N A N A N A No No N A AVDD N A N A N A N A No No N A DBG I O I N A Yes No Yes Yes VSS N A N A N A N A No No N A PA 7 0 I O I N A Yes No Yes Yes Programmable PB 7 0 IO I N A Yes No Yes Yes Programmable PC 7 0 IO I N A Yes No Yes Yes Programmable PD 7 0 VO I N A Yes No Yes Yes Programmable PE7 0 VO I N A Yes No Yes Yes Programmable PF 7 0 I O I N A Yes No Yes Yes Programmable PG 7 0 IO I N A Yes No Yes Yes Programmable P
286. ng a GPIO port pin transition 48 using watch dog timer time out 48 SUB 239 subtract 239 PS019915 1005 Z8 Encore 64K Series Product Specification L z ZiLOG subtract extended addressing 239 subtract with carry 239 subtract with carry extended addressing 239 SUBX 239 SWAP 242 swap nibbles 242 symbols additional 236 system and core resets 44 T TCM 239 TCMX 239 test complement under mask 239 test complement under mask extended addressing 239 test under mask 239 test under mask extended addressing 239 timer signals 14 timers 5 75 architecture 75 block diagram 76 capture mode 80 89 capture compare mode 83 89 compare mode 81 89 continuous mode 77 89 counter mode 78 counter modes 89 gated mode 82 89 one shot mode 76 89 operating mode 76 PWM mode 79 89 reading the timer count values 84 reload high and low byte registers 85 timer control register definitions 84 timer output signal operation 84 timers 0 3 control 0 registers 88 control 1 registers 88 high and low byte registers 84 87 TM 239 TMX 239 transmit IrDA data 121 Index htt p ww xi npi an net DEL EY EC BRE UE IMOO000000 010 62245566 13810019655 transmit interrupt 141 transmitting UART data interrupt driven method 101 transmitting UART data polled method 100 TRAP 241 U UART 4 architecture 98 asynchronous data format without with parity 100 baud rate generator 108 baud rates table 117 cont
287. ng is the default for unprogrammed erased Flash VBO AO Voltage Brown Out Protection Always On 0 Voltage Brown Out Protection is disabled in STOP mode to reduce total power con sumption 1 Voltage Brown Out Protection is always enabled including during STOP mode This setting is the default for unprogrammed erased Flash RP Read Protect 0 User program code is inaccessible Limited control features are available through the On Chip Debugger PS019915 1005 Option Bits htt p ww xi npi an net LEE EB DRE EL EE EGET ET VE Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 192 ZiLOG 1 User program code is accessible All On Chip Debugger commands are enabled This setting is the default for unprogrammed erased Flash Reserved These Option Bits are reserved for future use and must always be 1 This setting is the default for unprogrammed erased Flash FWP Flash Write Protect Flash version only FWP Description 0 Programming Page Erase and Mass Erase through User Code is disabled Mass Erase is available through the On Chip Debugger 1 Programming and Page Erase are enabled for all of Flash Program Memory Flash Memory Address 0001H Table 98 Options Bits at Flash Memory Address 0001H BITS 7 6 5 4 3 2 1 0 FIELD Reserved RESET U R W R W ADDR Program Memory 0001H Note U
288. not occur in the not acknowledge case because the STOP bit was set I2C Controller HHHEHEHIGBUHBBHBHH 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 145 ZiloaoG Write Transaction with a 7 Bit Address Figure 29 illustrates the data transfer format for a 7 bit addressed slave Shaded regions indicate data transferred from the C Controller to slaves and unshaded regions indicate data transferred from the slaves to the I7C Controller S Slave Address W 0 A Data A Data A Data A A P S Figure 29 7 Bit Addressed Slave Data Transfer Format The procedure for a transmit operation to a 7 bit addressed slave is as follows 1 Software asserts the IEN bit in the I C Control register 2 Software asserts the TXI bit of the IC Control register to enable Transmit interrupts 3 The C interrupt asserts because the PC Data register is empty 4 Software responds to the TDRE bit by writing a 7 bit slave address plus write bit 20 to the C Data register e Software asserts the START bit of the C Control register The IC Controller sends the START condition to the IC slave 7 The PC Controller loads the C Shift register with the contents of the PC Data register 8 After one bit of address has been shifted out by the SDA signal the Transmit interrupt is asserted TDRE 1 9 Software responds by writing the transmit data into the PC Data register 10 The C Co
289. nowledge the first address byte the PC Controller sets the NCKI bit and clears the ACK bit in the 7C Status register Software responds to the Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI bit The I2C Controller sends the STOP condition on the bus and clears the STOP and NCKI bits The transaction is complete ignore the following steps The C Controller loads the C Shift register with the contents of the PC Data register The I C Controller shifts the second address byte out the SDA signal After the first bit has been sent the Transmit interrupt is asserted Software responds by writing a data byte to the PC Data register The C Controller completes shifting the contents of the shift register on the SDA signal I2C Controller htt p ww xi npi an net COA ee ee DELI 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 149 ZiLOoG 16 If the C slave sends an acknowledge by pulling the SDA signal low during the next high period of SCL the PC Controller sets the ACK bit in the I7C Status register Continue with step 17 If the slave does not acknowledge the second address byte or one of the data bytes the PC Controller sets the NCKI bit and clears the ACK bit in the I7C Status register Software responds to the Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI bit The I2C Controller sends the STOP condition on the bus
290. ns FFH for the data DBG lt ODH DBG lt Data Memory Address 15 8 DBG lt Data Memory Address 7 0 DBG Size 15 8 DBG Size 7 0 DBG 1 65536 data bytes Read Program Memory CRC 0EH The Read Program Memory CRC command computes and returns the CRC cyclic redundancy check of Program Memory using PS019915 1005 On Chip Debugger htt p ww xi npi an net DOT 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 202 ZiLOG the 16 bit CRC CCITT polynomial If the device is not in DEBUG mode this command returns FFFFH for the CRC value Unlike most other OCD Read commands there is a delay from issuing of the command until the OCD returns the data The OCD reads the Program Memory calculates the CRC value and returns the result The delay is a function of the Program Memory size and is approximately equal to the system clock period multiplied by the number of bytes in the Program Memory DBG lt OEH DBG CRC 15 8 DBG CRC 7 0 Step Instruction 10H The Step Instruction command steps one assembly instruction at the current Program Counter PC location If the device is not in DEBUG mode or the Read Protect Option Bit is enabled the OCD ignores this command DBG 10H Stuff Instruction 11H The Stuff Instruction command steps one assembly instruction and allows specification of the first byte of the instruction The remain
291. nt bits of the 10 bit address The lowest bit of the first byte transferred is the read write control bit 20 The transmit operation is carried out in the same manner as 7 bit addressing The procedure for a transmit operation on a 10 bit addressed slave is as follows 1 2 3 4 ea 10 11 12 13 14 15 PS019915 1005 Software asserts the IEN bit in the I C Control register Software asserts the TXI bit of the C Control register to enable Transmit interrupts The PC interrupt asserts because the PC Data register is empty Software responds to the TDRE interrupt by writing the first slave address byte to the PC Data register The least significant bit must be 0 for the write operation Software asserts the START bit of the I C Control register The I C Controller sends the START condition to the IC slave The PC Controller loads the C Shift register with the contents of the PC Data register After one bit of address is shifted out by the SDA signal the Transmit interrupt is asserted Software responds by writing the second byte of address into the contents of the re Data register The C Controller shifts the rest of the first byte of address and write bit out the SDA signal If the C slave acknowledges the first address byte by pulling the SDA signal low during the next high period of SCL the PC Controller sets the ACK bit in the C Status register Continue with step 12 If the slave does not ack
292. ntrol section for more information on operation of the PHASE bit CLKPOL Clock Polarity 0 SCK idles Low 0 1 SCK idle High 1 WOR Wire OR Open Drain Mode Enabled 0 SPI signal pins not configured for open drain 1 All four SPI signal pins SCK SS MISO MOSI configured for open drain function This setting is typically used for multi master and or multi slave configurations MMEN SPI Master Mode Enable 0 SPI configured in Slave mode 1 SPI configured in Master mode SPIEN SPI Enable 0 SPI disabled 1 SPI enabled Serial Peripheral Interface IG1 D U DLE 010 62245566 13810019655 Z8 Encore 64K Series Product Specification L ZiLOG SPI Status Register The SPI Status register Table 64 indicates the current state of the SPI All bits revert to their reset state if the SPIEN bit in the SPICTL register 0 Table 64 SPI Status Register SPISTAT BITS 7 6 5 4 3 2 1 0 FIELD IRQ OVR COL ABT Reserved TXST SLAS RESET 0 l R W R W R ADDR F62H R W Read access Write a to clear the bit to 0 PS019915 1005 htt p ww xi npi an net Hg g dg p B m IRQ Interrupt Request If SPIEN 1 this bit is set if the STR bit in the SPICTL register is set or upon completion of an SPI master or slave transaction This bit does not set if SPIEN 0 and the SPI Baud Rate Generator is used as a
293. ntroller shifts the rest of the address and write bit out by the SDA signal 11 If the C slave sends an acknowledge by pulling the SDA signal low during the next high period of SCL the C Controller sets the ACK bit in the IC Status register Continue with step 12 If the slave does not acknowledge the Not Acknowledge interrupt occurs NCKI bit is set in the Status register ACK bit is cleared Software responds to the Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI bit The I2C Controller sends the STOP condition on the bus and clears the STOP and NCKI bits The transaction is complete ignore following steps 12 The IC Controller loads the contents of the I7C Shift register with the contents of the PC Data register PS019915 1005 I2C Controller htt p ww xi npi an net ugagamBpmmuagdisqiaudtt Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 146 ZiloaoG 13 The IC Controller shifts the data out of using the SDA signal After the first bit is sent the Transmit interrupt is asserted 14 If more bytes remain to be sent return to step 9 15 Software responds by setting the STOP bit of the PC Control register or START bit to initiate a new transaction In the STOP case software clears the TXI bit of the PC Control register at the same time 16 The C Controller completes transmission of the data on the SDA signal 1
294. ock command 8CH Second unlock command 95H Page erase command 63H Mass erase command SEH Flash Sector Protect register select All other commands or any command out of sequence lock the Flash Controller Flash Memory htt p ww xi npi an net utu ee ee EU og 010 62245566 13810019655 Flash Status Register Table 92 Flash Status Register FSTAT Z8 Encore 64K Series Product Specification ZiLOG The Flash Status register Table 92 indicates the current state of the Flash Controller This register can be read at any time The Read only Flash Status Register shares its Register File address with the Write only Flash Control Register BITS 7 6 4 1 0 FIELD Reserved FSTAT RESET 0 R W R ADDR FF8H Reserved These bits are reserved and must be 0 FSTAT Flash Controller Status 00_0000 Flash Controller locked 00_0001 First unlock command received 00_0010 Second unlock command received 00_0011 Flash Controller unlocked 00_0100 Flash Sector Protect register selected 00_1xxx Program operation in progress 01_Oxxx Page erase operation in progress 10 Oxxx Mass erase operation in progress PS019915 1005 Flash Memory htt p ww xi npi an net BO Pea ET EUR Ooo 010 62245566 13810019655 186 Page Select Register Table 93 Page Select Register FPS
295. ode s Fetch Instr Mnemonic Symbolic Operation dst src Hex C Z S V D H Cycles Cycles CPX dst src dst src ER ER A8 koko oko L 4 3 ER IM A9 4 3 DA dst dst DA dst R 40 O Xos 2 2 IR 41 2 3 DEC dst dst lt dst 1 R 30 a CRO ROO 2 2 IR 31 2 3 DECW dst dst lt dst 1 RR 80 RR 2 5 IRR 81 2 6 DI IRQCTL 7 lt 0 8F AME o 1 2 DJNZ dst RA dst lt dst 1 r OA FA AME o 2 3 if dst 0 PC lt PC X EI IRQCTL 7 lt 1 OF AME o 1 2 HALT HALT Mode 7F AME o 1 2 INC dst dst lt dst 1 R 20 wo OR OE OA m s 2 2 IR 21 2 3 r OE FE 1 2 INCW dst dst lt dst 1 RR AO RR 2 5 IRR Al 2 6 IRET FLAGS lt SP BF E EM ME R 1 5 SP SP 1 PC Q SP SP SP 2 IRQCTL 7 lt 1 JP dst PC lt dst DA 8D JEN S 3 2 IRR C4 2 3 JP cc dst if cc is true DA OD FD 3 2 PC lt dst Flags Notation Value is a function of the result of the operation 0 Reset to 0 Unaffected 1 Set to 1 X Undefined PS019915 1005 htt p ww xi npi an net o D U Uu UU eZ8 CPU Instruction Set 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 246 ziLog Table 132 eZ8 CPU Instruction Summary Continued Assembly IRIURE UE Opcode s PRO Fetch Instr Mnemonic Symbolic Operation dst src Hex C Z S V D H Cycles Cycles JR dst PC lt PC X DA 8
296. of the 1 6us minimum width pulses allowed by the IrDA standard Endec Receiver Synchronization The IrDA receiver uses a local baud rate clock counter 0 to 15 clock periods to generate an input stream for the UART and to create a sampling window for detection of incoming pulses The generated UART input UART RXD is delayed by 8 baud rate clock periods with respect to the incoming IrDA data stream When a falling edge in the input data stream is detected the Endec counter is reset When the count reaches a value of 8 the UART RXD value is updated to reflect the value of the decoded data When the count reaches 12 baud clock periods the sampling window for the next incoming pulse opens The window remains open until the count again reaches 8 or in other words 24 baud clock periods since the previous pulse was detected This gives the Endec a sampling window of minus four baudrate clocks to plus eight baudrate clocks around the expected time of an incoming pulse If an incoming pulse is detected inside this window this process is repeated If the incoming data is a logical 1 no pulse the Endec returns to the initial state and waits for the next falling edge As each falling edge is detected the Endec clock counter is reset resynchronizing the Endec to the incoming signal This action allows the Endec to tolerate jitter and baud rate errors in the incoming data stream Resynchronizing the Endec does not alter the operation of the UART which ulti
297. onic devices and sensors Features e 20 MHz eZ8 CPU e Up to 64 KB Flash with in circuit programming capability e Upto 4 KB register RAM e 12 channel 10 bit analog to digital converter ADC e Two full duplex 9 bit UARTs with bus transceiver Driver Enable control e PC e Serial Peripheral Interface e Two Infrared Data Association IrDA compliant infrared encoder decoders e Up to four 16 bit timers with capture compare and PWM capability e Watch Dog Timer WDT with internal RC oscillator e 3 channel DMA e Upto 60 I O pins e 24 interrupts with configurable priority e On Chip Debugger e Voltage Brown out Protection VBO Power On Reset POR PS019915 1005 Introduction htt p ww xi npi an net DOT 010 62245566 13810019655 Z8 Encore 64K Series Product Specification ZiLOG e 3 0 3 6V operating voltage with 5V tolerant inputs e 0 to 70 C 40 to 105 C and 40 to 125 C operating temperature ranges Part Selection Guide Table 1 identifies the basic features and package styles available for each device within the Z8 Encore product line Table 1 Z8 Encore 64K Series Part Selection Guide Part Flash RAM 16 bit Timers ADC UARTS 40 44 pin 64 68 pin 80 pin Number KB KB LO withPWM Inputs with IrDA PC SPI packages packages package Z8F1621 16 2 31 3 8 2 1 1 X Z8F1622 16 2 46 4 12 2 1 1 X Z8F2421 24 2 31 3 8 2 1 1 X Z8F2422
298. ontroller in the 64K Series products does not operate in Slave mode PS019915 1005 12C Controller htt p ww xi npi an net uggamBpmmuagdrqiudtut Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Zi ZiLOoG Architecture Figure 27 illustrates the architecture of the PC Controller SDA SCL Shift ISHIFT Load IICDATA I CBRH Receive I CBRL Baud Rate Generator Tx Rx State Machine YY a Register Bus IC Interrupt Figure 27 PC Controller Block Diagram Operation The I7C Controller operates in MASTER mode to transmit and receive data Only a single master is supported Arbitration between two masters must be accomplished in software PC supports the following operations e Master transmits to a 7 bit slave e Master transmits to a 10 bit slave PS019915 1005 I2C Controller htt p ww xi npi an net o ee ee a og 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 141 ZiLOoGG e Master receives from a 7 bit slave e Master receives from a 10 bit slave SDA and SCL Signals PC sends all addresses data and acknowledge signals over the SDA line most significant bit first SCL is the common clock for the C Controller When the SDA and SCL pin alternate functions are selected for their resp
299. ort G Control PGCTL 00 56 FEA Port G Input Data PGIN XX 60 FEB Port G Output Data PGOUT 00 61 XX Undefined PS019915 1005 Register File Address Map htt p ww xi npi an net T ORHAND L i 010 62245566 13810019655 Z8 Encore 64K Series Product Specification ZI ZiLOG Table 7 64K Series Register File Address Map Continued Address Hex Register Description Mnemonic Reset Hex Page GPIO Port H FEC Port H Address PHADDR 00 55 FED Port H Control PHCTL 00 56 FEE Port H Input Data PHIN XX 60 FEF Port H Output Data PHOUT 00 61 Watch Dog Timer WDT FFO Watch Dog Timer Control WDTCTL XXX00000b 94 FF1 Watch Dog Timer Reload Upper Byte WDTU FF 95 FF2 Watch Dog Timer Reload High Byte WDTH FF 95 FF3 Watch Dog Timer Reload Low Byte WDTL FF 95 FF4 FF7 Reserved XX Flash Memory Controller FF8 Flash Control FCTL 00 185 FF8 Flash Status FSTAT 00 186 FF9 Page Select FPS 00 187 FF9 if enabled Flash Sector Protect FPROT 00 188 FFA Flash Programming Frequency High Byte FFREQH 00 189 FFB Flash Programming Frequency Low Byte FFREQL 00 189 FF4 FF8 Reserved XX Read Only Memory Controller FF9 Page Select RPS 00 FFA FFB Reserved XX eZ8 CPU FFC Flags XX Refer to the eZ8 FFD Register Pointer RP XX CPU User FFE Stack Pointer High Byte SPH XX Manual FFF Stack Pointer Low Byte SPL XX XX Undefined P
300. otect register shares its Regis ter File address with the Page Select register The Flash Sector protect register can be accessed only after writing the Flash Control register with 5EH User code can only write bits in this register to 1 bits cannot be cleared to 0 by user code Table 94 Flash Sector Protect Register FPROT BITS 7 6 5 4 3 2 1 0 FIELD SECT7 SECT6 SECT5 SECT4 SECT3 SECT2 SECT1 SECTO RESET 0 R W R WI ADDR FF9H R W1 Register is accessible for Read operations Register can be written to 1 only via user code PS019915 1005 htt p ww xi npi an net u Donna O0 SECTn Sector Protect 0 Sector n can be programmed or erased from user code 1 Sector n is protected and cannot be programmed or erased from user code User code can only write bits from O to 1 Flash Memory 010 62245566 13810019655 Z8 Encore 64K Series Product Specification ZiLOG Flash Frequency High and Low Byte Registers The Flash Frequency High and Low Byte registers Tables 95 and 96 combine to form a 16 bit value FFREQ to control timing for Flash program and erase operations The 16 bit Flash Frequency registers must be written with the system clock frequency in KHz for Program and Erase operations Calculate the Flash Frequency value using the following equation FFREQ 15 0 FFREQH 7 0 FFREQL 7 0 System E dcn
301. ource Reset Type Normal or HALT Power On Reset Voltage Brown Out System Reset modes Watch Dog Timer time out System Reset when configured for Reset RESET pin assertion System Reset On Chip Debugger initiated Reset System Reset except the On Chip Debugger is OCDCTL 0 set to 1 unaffected by the reset STOP mode Power On Reset Voltage Brown Out System Reset RESET pin assertion System Reset DBG pin driven Low System Reset Power On Reset Each device in the 64K Series contains an internal Power On Reset POR circuit The POR circuit monitors the supply voltage and holds the device in the Reset state until the supply voltage reaches a safe operating level After the supply voltage exceeds the POR PS019915 1005 Reset and STOP Mode Recovery htt p ww xi npi an net HEEL E HEP ELE FEE DE ELE HH BE EUH 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 45 ZiLOG voltage threshold Vpop the POR Counter is enabled and counts 66 cycles of the Watch Dog Timer oscillator After the POR counter times out the XTAL Counter is enabled to count a total of 16 system clock pulses The devices are held in the Reset state until both the POR Counter and XTAL counter have timed out After the 64K Series devices exit the Power On Reset state the eZ8 CPU fetches the Reset vector Following Power On Reset the POR status bit in the Watch Dog Timer Control
302. p ww xi npi an net DOT 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 78 ZiLOG If using the Timer Output alternate function set the initial output level High or Low 2 Write to the Timer High and Low Byte registers to set the starting count value usually 0001H affecting only the first pass in CONTINUOUS mode After the first timer Reload in CONTINUOUS mode counting always begins at the reset value of 0001H Write to the Timer Reload High and Low Byte registers to set the Reload value 4 If desired enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers 5 Ifusing the Timer Output function configure the associated GPIO port pin for the Timer Output alternate function 6 Write to the Timer Control 1 register to enable the timer and initiate counting In CONTINUOUS mode the system clock always provides the timer input The timer period is given by the following equation Reload Value x Prescale Continuous Mode Time Out Period s System Clock Frequency Hz If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers the ONE SHOT mode equation must be used to determine the first time out period COUNTER Mode In COUNTER mode the timer counts input transitions from a GPIO port pin The timer input is ta
303. p PS019915 1005 htt p ww xi npi an net 2 8 MULT RR1 3 3 LD R2 IR1 3 3 3 4 BTJ p b Ir1 X A UU B Z8 Encore 64K Series Product Specification 255 ZiLOG Opcode Maps 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Zi ZiLOG Lower Nibble Hex Upper Nibble Hex 5 3 CPCX ER2 ER1 5 4 LDWX ER2 ER1 Figure 61 Second Opcode Map after 1FH PS019915 1005 Opcode Maps htt p ww xi npi an net Iq 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 257 ZiLOG Packaging Figure 62 illustrates the 40 pin PDIP plastic dual inline package available for the Z8X1601 Z8X2401 Z8X3201 Z8X4801 and Z8X6401 devices Figure 62 40 Lead Plastic Dual Inline Package PDIP PS019915 1005 Packaging htt p ww xi npi an net ugagamBpmmuagdisqiaudtt Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z z ZiLOG Figure 63 illustrates the 44 pin LQFP low profile quad flat package available for the Z8X1621 Z8X2421 Z8X3221 Z8X4821 and Z8X6421 devices MI
304. pacitively coupled to analog ground if the internal voltage reference is selected as the ADC reference voltage Oscillators XIN I External Crystal Input This is the input pin to the crystal oscillator A crystal can be connected between it and the XOUT pin to form the oscillator This signal is usable with external RC networks and an external clock driver PS019915 1005 Signal and Pin Descriptions htt p ww xi npi an net o ee ee a og 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 15 ZiLOG Table 3 Signal Descriptions Continued Signal Mnemonic VO Description XOUT O External Crystal Output This pin is the output of the crystal oscillator A crystal can be connected between it and the XIN pin to form the oscillator When the system clock is referred to in this manual it refers to the frequency of the signal at this pin This pin must be left unconnected when not using a crystal RCOUT O RC Oscillator Output This signal is the output of the RC oscillator It is multiplexed with a general purpose I O pin This signal must be left unconnected when not using a crystal On Chip Debugger DBG IO Debug This pin is the control and data input and output to and from the On Chip Debugger This pin is open drain Caution For operation of the On Chip Debugger all power pins Vpp and AVpp must be supplied with power and all ground pins V ss a
305. ption Bits chapter for more information Byte Programming When the Flash Controller is unlocked writes to Flash Memory from user code will pro gram a byte into the Flash if the address is located in the unlocked page An erased Flash byte contains all ones FFH The programming operation can only be used to change bits from one to zero To change a Flash bit or multiple bits from zero to one requires a Page Erase or Mass Erase operation Byte Programming can be accomplished using the eZ8 CPU s LDC or LDCI instructions Refer to the eZ8 CPU User Manual for a description of the LDC and LDCI instructions PS019915 1005 Flash Memory htt p ww xi npi an net DOT 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 183 ZiLOG While the Flash Controller programs the Flash memory the eZ8 CPU idles but the system clock and on chip peripherals continue to operate Interrupts that occur when a Program ming operation is in progress are serviced once the Programming operation is complete To exit Programming mode and lock the Flash Controller write 00H to the Flash Control register User code cannot program Flash Memory on a page that lies in a protected sector When user code writes memory locations only addresses located in the unlocked page are pro grammed Memory writes outside of the unlocked page are ignored UN Caution Each memory location must not be programmed more than
306. pts 141 operation 140 SDA and SCL signals 141 stop and start conditions 143 Index htt p ww xi npi an net DEL EY EC BRE UE FER DL ED ERE E EL EH 010 62245566 13810019655 DCBRH register 157 158 160 I2CBRL register 157 I2CCTL register 155 I2CDATA register 153 I2CSTAT register 153 IM 235 immediate data 235 immediate operand prefix 236 INC 238 increment 238 increment word 238 INCW 238 indexed 235 indirect address prefix 236 indirect register 235 indirect register pair 235 indirect working register 235 indirect working register pair 235 infrared encoder decoder IrDA 120 instruction set ez8 CPU 233 instructions ADC 238 ADCX 238 ADD 238 ADDX 238 AND 241 ANDX 241 arithmetic 238 BCLR 239 BIT 239 bit manipulation 239 block transfer 239 BRK 241 BSET 239 BSWAP 239 242 BTJ 241 BTJNZ 241 BTJZ 241 CALL 241 CCF 239 240 CLR 240 COM 241 CP 238 CPC 238 PS019915 1005 Z8 Encore 64K Series Product Specification ZI ZiLOG CPCX 238 CPU control 240 CPX 238 DA 238 DEC 238 DECW 238 DI 240 DJNZ 241 EI 240 HALT 240 INC 238 INCW 238 IRET 241 JP 241 LD 240 LDC 240 LDCI 239 240 LDE 240 LDEI 239 LDX 240 LEA 240 load 240 logical 241 MULT 238 NOP 240 OR 241 ORX 241 POP 240 POPX 240 program control 241 PUSH 240 PUSHX 240 RCF 239 240 RET 241 RL 242 RLC 242 rotate and shift 242 RR 242 RRC 242 SBC 239 SCF 239 240 SRA 242 SRL 242
307. put Ports B and H RESET and where noted otherwise PS019915 1005 htt p ww xi npi an net LI E Hu Uu UU Electrical Characteristics 010 62245566 13810019655 Z8 Encore 64K Series Product Specification L zo ZiLOG Table 104 Absolute Maximum Ratings Continued Parameter Minimum Maximum Units Notes Total power dissipation 500 mW Maximum current into Vpp or out of Vss 140 mA 64 Pin LQFP Maximum Ratings at 40 C to 70 C Total power dissipation 1000 mW Maximum current into Vpp or out of Vss 275 mA 64 Pin LQFP Maximum Ratings at 70 C to 125 C Total power dissipation 540 mW Maximum current into Vpp or out of Vss 150 mA 44 Pin PLCC Maximum Ratings at 40 C to 70 C Total power dissipation 750 mW Maximum current into Vpp or out of Vss 200 mA 44 Pin PLCC Maximum Ratings at 70 C to 125 C Total power dissipation 295 mW Maximum current into Vpp or out of Vss 83 mA 44 pin LQFP Maximum Ratings at 40 C to 70 C Total power dissipation 750 mW Maximum current into Vpp or out of Vss 200 mA 44 pin LQFP Maximum Ratings at 70 C to 125 C Total power dissipation 360 mW Maximum current into Vpp or out of Vss 100 mA 40 pin PDIP Maximum Ratings at 40 C to 70 C Total power dissipation 1000 mW Maximum current into Vpp or out of Vss 275 mA 40 pin PD
308. r The Interrupt Control IRQCTL register Table 38 contains the master enable bit for all interrupts Table 38 Interrupt Control Register IRQCTL BITS 7 6 5 4 3 2 1 0 FIELD IRQE Reserved RESET 0 R W R W R ADDR FCFH IRQE Interrupt Request Enable This bit is set to 1 by execution of an EI Enable Interrupts or IRET Interrupt Return instruction or by a direct register write of a 1 to this bit It is reset to 0 by executing a DI instruction eZ8 CPU acknowledgement of an interrupt request or Reset 0 Interrupts are disabled 1 Interrupts are enabled Reserved Must be 0 PS019915 1005 Interrupt Controller htt p ww xi npi an net o CO FSEPET EU og 010 62245566 13810019655 Timers Overview Z8 Encore 64K Series Product Specification 75 ZiLOG The 64K Series products contain up to four 16 bit reloadable timers that can be used for timing event counting or generation of pulse width modulated PWM signals The tim ers features include 16 bit reload counter Programmable prescaler with prescale values from 1 to 128 PWM output generation Capture and compare capability External input pin for timer input clock gating or capture signal External input pin signal frequency is limited to a maximum of one fourth the system clock frequency Timer output pin Timer interrupt In addition to the
309. rmine the source of the interrupt error break or received data 2 If the interrupt was caused by data available read the data from the UART Receive Data register If operating in MULTIPROCESSOR 9 bit mode further actions may be required depending on the MULTIPROCESSOR Mode bits MPMD 1 0 3 Clear the UART Receiver interrupt in the applicable Interrupt Request register PS019915 1005 UART htt p ww xi npi an net DOT 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z ZiLOG 4 Execute the IRET instruction to return from the interrupt service routine and await more data Clear To Send CTS Operation The CTS pin if enabled by the CTSE bit of the UART Control 0 register performs flow control on the outgoing transmit datastream The Clear To Send CTS input pin is sam pled one system clock before beginning any new character transmission To delay trans mission of the next data character an external receiver must deassert CTS at least one system clock cycle before a new data transmission begins For multiple character trans missions this would typically be done during Stop Bit transmission If CTS deasserts in the middle of a character transmission the current character is sent completely MULTIPROCESSOR 9 bit Mode The UART has a MULTIPROCESSOR 9 bit mode that uses an extra 9th bit for selec tive communication when a number of processors share a common UART b
310. rogram Memory Address 15 8 DBG lt Program Memory Address 7 0 DBG lt Size 15 8 DBG Size 7 0 DBG lt 1 65536 data bytes e Read Program Memory 0BH The Read Program Memory command reads data from Program Memory This command is equivalent to the LDC and LDCI instructions Data can be read 1 65536 bytes at a time 65536 bytes can be read by setting size to zero If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled this command returns FFH for the data DBG lt OBH DBG lt Program Memory Address 15 8 DBG lt Program Memory Address 7 0 DBG Size 15 8 DBG Size 7 0 DBG 1 65536 data bytes e Write Data Memory 0CH The Write Data Memory command writes data to Data Memory This command is equivalent to the LDE and LDEI instructions Data can be written 1 65536 bytes at a time 65536 bytes can be written by setting size to zero If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled the data is discarded DBG lt OCH DBG lt Data Memory Address 15 8 DBG lt Data Memory Address 7 0 DBG Size 15 8 DBG Size 7 0 DBG lt 1 65536 data bytes e Read Data Memory 0DH The Read Data Memory command reads from Data Memory This command is equivalent to the LDE and LDEI instructions Data can be read 1 65536 bytes at a time 65536 bytes can be read by setting size to zero If the device 1s not in DEBUG mode this command retur
311. rol of ADC 174 control register 163 control register definitions 163 controller 5 DMA_ADC address register 167 DMA ADC control register 168 DMA ADC operation 162 end address low byte register 166 I O address register 165 operation 161 start current address low byte register 166 status register 169 DMAA STAT register 169 DMAACTL register 168 DMAXCTL register 164 DMAXEND register 167 DMAXH register 165 DMAXI O address DMAxIO 165 DMAXIO register 165 DMAXxSTART register 166 document number description 268 dst 236 E EI 240 electrical characteristics 209 ADC 222 flash memory and timing 221 GPIO input data sample timing 225 watch dog timer 221 enable interrupt 240 ER 235 extended addressing register 235 external pin reset 46 external RC oscillator 220 Index htt p ww xi npi an net DEGERE EY EC BRE UE IMOO000000 010 62245566 13810019655 eZ8 CPU features 3 eZ8 CPU instruction classes 238 eZ8 CPU instruction notation 234 eZ8 CPU instruction set 233 eZ8 CPU instruction summary 242 F FCTL register 185 features Z8 Encore 1 first opcode map 255 FLAGS 236 flags register 236 flash controller 4 option bit address space 190 option bit configuration reset 190 program memory address 0001H 192 flash memory arrangement 179 byte programming 182 code protection 181 configurations 178 control register definitions 185 controller bypass 184 electrical characteristics and timing 221 fla
312. rol register definitions 109 controller signals 14 data format 99 interrupts 106 multiprocessor mode 104 receiving data using interrupt driven method 103 receiving data using the polled method 102 transmitting data using the interrupt driven method 101 transmitting data using the polled method 100 x baud rate high and low registers 115 x control 0 and control 1 registers 112 x status 0 and status 1 registers 110 112 UxBRH register 116 JxBRL register 116 xCTLO register 112 115 xCTLI register 113 JxRXD register 110 JxSTATO register 110 XSTATI register 112 xTXD register 109 cad Cic GG V vector 235 voltage brown out reset VBR 45 PS019915 1005 Z8 Encore 64K Series Product Specification Zi ZiLOG W watch dog timer approximate time out delay 92 approximate time out delays 91 CNTL 46 control register 94 electrical characteristics and timing 221 interrupt in normal operation 92 interrupt in STOP mode 92 operation 91 refresh 92 240 reload unlock sequence 93 reload upper high and low registers 95 reset 46 reset in normal operation 93 reset in STOP mode 93 time out response 92 WDTCTL register 94 WDTH register 96 WDTL register 97 working register 235 working register pair 235 WTDU register 96 X X 235 XOR 241 XORX 241 Z Z8 Encore block diagram 3 features 1 introduction 1 part selection guide 2 Index htt p ww xi npi an net DEGERE EY EC BRE UE IMOO000000
313. s 111 7 bits L Diagnostic Mode Control 0 Reading from SPIBRH SPIBRL returns reload values 1 Reading from SPIBRH SPIBRL returns current BRG count value PS019915 1005 htt p ww xi npi an net DEL EY EC BRE UE Reserved Z8 Encore 64K Series Z8 Encore 34 ZiLOG SPI Diagnostic State SPIDST F64H Read Only D7 D6 D5S D4 D3 D2 D1 DO L SPI State Transmit Clock Enable 0 Internal transmit clock enable signal is deasserted 1 Internal transmit clock enable signal is asserted Shift Clock Enable 0 Internal shift clock enable signal is deasserted 1 Internal shift clock enable signal is asserted SPI Baud Rate Generator High Byte SPIBRH F66H Read Write D7ID6 D5 DA4 D3 D2 D1 DO ____________ SPI Baud Rate divisor 15 8 SPI Baud Rate Generator Low Byte SPIBRL F67H Read Write D7 D6 D5 D4 D3D2 DI DO ____________ SPI Baud Rate divisor 7 0 ADC Control ADCCTL F70H Read Write D7 D6 D5IDA4D3 D2ID1 DO Analog Input Select 0000 ANAO 0001 ANAI 00102 ANA2 0011 ANA3 01002 ANA4 0101 ANAS 01102 ANAG 0111 ANA7 1000 ANA8 1001 ANA9 10102 ANAIO 1011 ANA11 11xx Reserved L Continuous Mode Select 0 Single shot conversion 1 Continuous conversion LL
314. s peripheral control registers and general purpose RAM The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H and loads that value into the Program Counter Program execution begins at the Reset vec tor address Following STOP Mode Recovery the STOP bit in the Watch Dog Timer Con trol Register is set to 1 Table 10 lists the STOP Mode Recovery sources and resulting actions The text following provides more detailed information on each of the STOP Mode Recovery sources Table 10 STOP Mode Recovery Sources and Resulting Action Operating Mode STOP Mode Recovery Source Action STOP mode Watch Dog Timer time out STOP Mode Recovery when configured for Reset Watch Dog Timer time out STOP Mode Recovery followed by interrupt if when configured for interrupt interrupts are enabled Data transition on any GPIO Port pin STOP Mode Recovery enabled as a STOP Mode Recovery source PS019915 1005 Reset and STOP Mode Recovery htt p ww xi npi an net EE HHHEHEHIGBUHBBHBHH 010 62245566 13810019655 47 Z8 Encore 64K Series Product Specification 48 ZiLOG STOP Mode Recovery Using Watch Dog Timer Time Out If the Watch Dog Timer times out during STOP mode the device undergoes a STOP Mode Recovery sequence In the Watch Dog Timer Control register the WDT and STOP bits are set to 1 If the Watch Dog Timer is configured to generate an interrupt upon time
315. s 195 OCD Data Format 196 Recommended 20MHz Crystal Oscillator Configuration 206 Connecting the On Chip Oscillator to an External RC Network 207 Typical RC Oscillator Frequency as a Function of the External Capacitance with a 45kW Resistor 000 4 208 Typical Active Mode Idd Versus System Clock Frequency 213 Maximum Active Mode Idd Versus System Clock Frequency 214 Typical HALT Mode Idd Versus System Clock Frequency 215 Maximum HALT Mode Icc Versus System Clock Frequency 216 Maximum STOP Mode Idd with VBO enabled versus Power Supply Voltage 0 0 cece eee eee eee 217 Maximum STOP Mode Idd with VBO Disabled versus Power Supply Voltage 0 0 0 cee eee eee eee 218 Analog to Digital Converter Frequency Response 223 Port Input Sample Timing 0 0 0 0 eee cece 225 GPIO Port Output Timing 0 0 0 0 eee eee eee 226 On Chip Debugger Timing 0 cee eee eee ee 227 SPI Master Mode Timing 0 cee eee eee eee 228 SPI Slave Mode Timing 0 0 0 0 cece cece eee nee 229 I2C Timing 2 04 bee ca eee bee ea a ee Vr kee ed 230 UART Timing with CTS eeren nei E a E E eee eee 231 UART Timing without CTS 1 0 2 0 0 eee eee 232 Flags Register 2 1 cence eens 252 Opcode Map Cell Description 0 0 eee eee eee 253 First Opcode Map acai ssewsansiis deka sidlede data tate Wade dac eas 255
316. s an acknowledge by pulling the SDA signal Low during the next high period of SCL If the slave were to Not Acknowledge at this point this should not happen because the slave did acknowledge the first two address bytes software would respond by setting the STOP and FLUSH bits and clearing the TXI bit The I2C Controller sends the STOP condition on the bus and clears the STOP and NCKI bits The transaction is complete ignore the following steps The I C Controller shifts in a byte of data from the PC slave on the SDA signal The IC Controller sends a Not Acknowledge to the PC slave if the NAK bit is set last byte else it sends an Acknowledge The I C Controller asserts the Receive interrupt RDRF bit set in the Status register Software responds by reading the PC Data register which clears the RDRF bit If there is only one more byte to receive set the NAK bit of the PC Control register If there are one or more bytes to transfer return to step 19 After the last byte is shifted in a Not Acknowledge interrupt is generated by the PC Controller Software responds by setting the STOP bit of the PC Control register A STOP condition is sent to the IC slave and the STOP and NCKI bits are cleared I C Control Register Definitions IC Data Register The C Data register Table 69 holds the data that is to be loaded into the PC Shift regis ter during a write to a slave This register also holds data that is loaded from the PC Shift
317. s are generated on the rising edge of the Timer Input CAPTURE COMPARE mode 0 Counting is started on the first rising edge of the Timer Input signal The current count is captured on subsequent rising edges of the Timer Input signal 1 Counting is started on the first falling edge of the Timer Input signal The current count is captured on subsequent falling edges of the Timer Input signal PS019915 1005 Timers htt p ww xi npi an net DOT 010 62245566 13810019655 PS019915 1005 htt p ww xi npi an net EE Z8 Encore 64K Series Product Specification Z ZiLOG When the Timer Output alternate function TxOUT on a GPIO port pin is enabled TXOUT will change to whatever state the TPOL bit is in The tim er does not need to be enabled for that to happen Also the Port data direc tion sub register is not needed to be set to output on TXOUT Changing the TPOL bit with the timer enabled and running does not immediately change the TxOUT PRES Prescale value The timer input clock is divided by 2PRES where PRES can be set from 0 to 7 The prescaler is reset each time the Timer is disabled This insures proper clock division each time the Timer is restarted 000 Divide by 1 001 Divide by 2 010 Divide by 4 011 Divide by 8 100 Divide by 16 101 Divide by 32 110 Divide by 64 111 Divide by 128 TMODE TIMER mode 000 ONE SHOT mode 001 CONTINUOUS mode
318. s both the outgoing transmit data and the incoming receive data Reads from the SPI Data register always return the current contents of the 8 bit shift register Data is shifted out starting with bit 7 The last bit received resides in bit position 0 With the SPI configured as a Master writing a data byte to this register initiates the data transmission With the SPI configured as a Slave writing a data byte to this register loads the shift register in preparation for the next data transfer with the external Master In either the Master or Slave modes if a transmission is already in progress writes to this register are ignored and the Overrun error flag OVR is set in the SPI Status register When the character length is less than 8 bits as set by the NUMBITS field in the SPI Mode register the transmit character must be left justified in the SPI Data register A received character of less than 8 bits is right justified last bit received is in bit position 0 For example if the SPI is configured for 4 bit characters the transmit characters must be writ ten to SPIDATA 7 4 and the received characters are read from SPIDATA 3 0 Table 62 SPI Data Register SPIDATA BITS 7 6 5 4 3 2 1 0 FIELD DATA RESET X R W R W ADDR F60H DATA Data Transmit and or receive data SPI Control Register The SPI Control register Table 63 configures the SPI for transmit and receive operations
319. s is not being transferred 1 Address is being transferred Read 0 Write operation 1 Read operation 10 Bit Address 0 7 bit address being transmitted 1 10 bit address being transmitted Acknowledge 0 Acknowledge not transmitted received 1 For last byte Acknowledge was transmitted received Receive Data Register Full 0 2 I2C has not received data 1 Data register contains received data Transmit Data Register Empty 0 Data register is full 1 Data register is empty Control Register Summary htt p ww xi npi an net DEL EY EC BRE UE FER DL ED ERE E EL EH 010 62245566 13810019655 I2C Control I2CCTL F52H Read Write D7 D6 D5 D4 D3 D2DD1 DO L 2C Signal Filter Enable 0 Digital filtering disabled 1 Low pass digital filters enabled on SDA and SCL input signals L Flush Data 0 No effect 1 Clears I2C Data register Send NAK 0 Do not send NAK 1 Send NAK after next byte received from slave Enable TDRE Interrupts 0 Do not generate an interrupt when the I2C Data register is empty 1 Generate an interrupt when the I2C Transmit Data register is empty Baud Rate Generator Interrupt Request 0 Interrupts behave as set by I2C control 1 BRG generates an interrupt when it counts down to zero L Send Stop Condition 0 Do not issue Stop condition after data transmission is complete 1 Iss
320. sembly Language Syntax Example 1 Assembly Language Code ADD 43H 08H ADD dst src Object Code 04 08 43 OPC src dst Example 2 In general when an instruction format requires an 8 bit register address that address can specify any register location in the range 0 255 or using Escaped Mode Addressing a Working Register RO R15 If the contents of Register 43H and Working Register R8 are added and the result is stored in 43H the assembly syntax and resulting object code is Assembly Language Syntax Example 2 Assembly Language Code ADD 43H R8 ADD dst src Object Code 04 E8 43 OPC src dst See the device specific Product Specification to determine the exact register file range available The register file size varies depending on the device type eZ8 CPU Instruction Notation In the eZ8 CPU Instruction Summary and Description sections the operands condition codes status flags and address modes are represented by a notational shorthand that is described in Table 121 PS019915 1005 eZ8 CPU Instruction Set htt p ww xi npi an net DOT 010 62245566 13810019655 Table 121 Notational Shorthand Z8 Encore 64K Series Product Specification Zi ZiLOG Notation Description Operand Range b Bit b b represents a value from 0 to 7 000B to 111B cc Condition Code See Condition Codes overview in the eZ8 CPU User Manual DA D
321. ses the DBG pin for communication with an external host This one pin interface is a bi directional open drain interface that transmits and receives data Data transmission is half duplex in that transmit and receive cannot occur simultaneously The serial data on the DBG pin is sent using the standard asynchronous data format defined in RS 232 This pin can interface the 64K Series products to the serial port of a host PC using minimal external hardware Two different methods for connecting the DBG pin to an RS 232 interface are depicted in Figures 37 and 38 UN Caution For operation of the On Chip Debugger all power pins Vpp and AVpp must be supplied with power and all ground pins Vss and AV ss must be properly grounded The DBG pin is open drain and must always be connected to Vpp through an external pull up resistor to ensure proper operation Vpp RS 232 Transceiver 10K Ohm Diode RS 232 TX DBG Pin RS 232 RX E Figure 37 Interfacing the On Chip Debugger s DBG Pin with an RS 232 Interface 1 PS019915 1005 On Chip Debugger HHHEHEHIGBUHBBHBHH 010 62245566 13810019655 htt p ww xi npi an net EE Z8 Encore 64K Series Product Specification Zi ZiLOG VDD RS 232 Transceiver Open Drain 10K Ohm Buffer RS 232 TX gt DBG Pin RS 232 RX BC Figure 38 Interfacing the On Chip Debugger s DBG Pin with an RS 232 Interface 2 Debug Mod
322. set to 0001H and counting resumes If the TPOL bit in the Timer Control 1 register is set to 1 the Timer Output signal begins as a High 1 and then transitions to a Low 0 when the timer value matches the PVM value The Timer Output signal returns to a High 1 after the timer reaches the Reload value and is reset to 0001H If the TPOL bit in the Timer Control 1 register is set to O the Timer Output signal begins as a Low 0 and then transitions to a High 1 when the timer value matches the PVM value The Timer Output signal returns to a Low 0 after the timer reaches the Reload value and is reset to 0001H The steps for configuring a timer for PWM mode and initiating the PWM operation are as follows PS019915 1005 Timers HHHEHEHIGBUHBBHBHH 010 62245566 13810019655 htt p ww xi npi an net EE Z8 Encore 64K Series Product Specification L a ZiLOG 1 Write to the Timer Control 1 register to Disable the timer Configure the timer for PWM mode Set the prescale value Set the initial logic level High or Low and PWM High Low transition for the Timer Output alternate function 2 Write to the Timer High and Low Byte registers to set the starting count value typically 0001H This only affects the first pass in PWM mode After the first timer reset in PWM mode counting always begins at the reset value of 0001H 3 Write to the PWM High and Low Byte registers to set the
323. sh Memory The ability to prevent accidental programming and erasure of the user code in Flash Memory Voltage Brown Out configuration always enabled or disabled during STOP mode to reduce STOP mode power consumption Oscillator mode selection for high medium and low power crystal oscillators or external RC oscillator Option Bit Configuration By Reset Each time the Option Bits are programmed or erased the device must be Reset for the change to take place During any reset operation System Reset Reset or STOP Mode Recovery the Option Bits are automatically read from the Flash Memory and written to Option Configuration registers The Option Configuration registers control operation of the devices within the 64K Series Option Bit control is established before the device exits Reset and the eZ8 CPU begins code execution The Option Configuration registers are not part of the Register File and are not accessible for read or write access Option Bit Address Space The first two bytes of Flash Memory at addresses 0000H Table 97 and 0001H Table 98 are reserved for the user Option Bits The byte at Flash Memory address 0000H configures user options The byte at Flash Memory address 0001H is reserved for future use and must remain unprogrammed PS019915 1005 htt p ww xi npi an net EE Option Bits HHHEHEHIGBUHBBHBHH 010 62245566 13810019655 Z8 Encore 64K Series Product Specification
324. sh control register 185 flash status register 186 frequency high and low byte registers 189 mass erase 184 operation 180 operation timing 181 page erase 183 page select register 187 FPS register 187 FSTAT register 186 G gated mode 89 general purpose I O 51 GPIO 4 51 alternate functions 52 architecture 52 PS019915 1005 Z8 Encore 64K Series Product Specification L a ZiLOG control register definitions 54 input data sample timing 225 interrupts 54 port A H address registers 55 port A H alternate function sub registers 57 port A H control registers 56 port A H data direction sub registers 57 port A H high drive enable sub registers 59 port A H input data registers 60 port A H output control sub registers 58 port A H output data registers 61 port A H STOP mode recovery sub registers 59 port availability by device 51 port input timing 225 port output timing 226 H H 236 HALT 240 halt mode 50 240 hexadecimal number prefix suffix 236 I I2C 4 10 bit address read transaction 150 10 bit address transaction 147 10 bit addressed slave data transfer format 147 10 bit receive data format 150 7 bit address transaction 145 7 bit address reading a transaction 149 7 bit addressed slave data transfer format 144 145 146 7 bit receive data transfer format 149 baud high and low byte registers 156 158 160 C status register 153 control register definitions 152 controller 139 controller signals 13 interru
325. ssigned to this pin Table 12 lists the alternate functions associated with each port pin Table 12 Port Alternate Function Mapping Port Pin Mnemonic Alternate Function Description PortA PAO TOIN Timer 0 Input PAI TOOUT Timer 0 Output PA2 DEO UART 0 Driver Enable PA3 CTSO UART 0 Clear to Send PA4 RXDO IRRXO UART 0 IrDA 0 Receive Data PAS TXDO IRTXO UART 0 IrDA 0 Transmit Data PA6 SCL PC Clock automatically open drain PA7 SDA PC Data automatically open drain PortB PBO ANAO ADC Analog Input 0 PB1 ANAI ADC Analog Input 1 PB2 ANA2 ADC Analog Input 2 PB3 ANA3 ADC Analog Input 3 PB4 ANA4 ADC Analog Input 4 PBS ANAS ADC Analog Input 5 PB6 ANA6 ADC Analog Input 6 PB7 ANA7 ADC Analog Input 7 PortC PCO T1IN Timer 1 Input PCI TIOUT Timer 1 Output PC2 SS SPI Slave Select PC3 SCK SPI Serial Clock PC4 MOSI SPI Master Out Slave In PC5 MISO SPI Master In Slave Out PC6 T2IN Timer 2 In PC7 T20UT Timer 2 Out PS019915 1005 General Purpose I O htt p ww xi npi an net LEE EB DRE EL EE EGET ET VE Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z ZiLOG Table 12 Port Alternate Function Mapping Continued Port Pin Mnemonic Alternate Function Description PortD PDO T3IN Timer 3 In unavailable in 44 pin packages PD1 T3OUT Timer 3 Out unava
326. ster The timer input is the system clock Every subsequent desired transition after the first of the Timer Input signal captures the current count value The Capture value is written to the Timer PWM High and Low Byte Registers When the Capture event occurs an interrupt is generated the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes If no Capture event occurs the timer counts up to the 16 bit Compare value stored in the Timer Reload High and Low Byte registers Upon reaching the Compare value the timer generates an interrupt the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes The steps for configuring a timer for CAPTURE COMPARE mode and initiating the count are as follows 1 Write to the Timer Control 1 register to Disable the timer Configure the timer for CAPTURE COMPARE mode Set the prescale value Set the Capture edge rising or falling for the Timer Input 2 Write to the Timer High and Low Byte registers to set the starting count value typically 0001H PS019915 1005 Timers htt p ww xi npi an net DOT 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z ZiLOG Write to the Timer Reload High and Low Byte registers to set the Compare value 4 If desired enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers
327. ster Summary htt p ww xi npi an net EE TENENT IMOQOO000000 010 62245566 13810019655 Port E Address PEADDR FEOH Read Write D7 D6 D5 DA4 D3 D2DD1 DO Port E Address 7 0 Selects Port Sub Registers 00H No function 01H Data direction 02H Alternate function 03H z Output control open drain 04H High drive enable 05H STOP mode recovery enable 06H FFH No function Port E Control PECTL FEIH Read Write D7 D6 D5 D4 D3 D2DD1 DO Port E Control 7 0 Provides Access to Port Sub Registers Port E Input Data PEIN FE2H Read Only D7 D6 D5 D4ID3 D2DD1 DO Port E Input Data 7 0 Port E Output Data PEOUT FE3H Read Write D7 D6 D5 D4ID3 D2ID1 DO Port E Output Data 7 0 Port F Address PFADDR FE4H Read Write D7 ID6 ID5 DAID3ID2DIIDO Port F Address 7 0 Selects Port Sub Registers 00H No function 01H Data direction 02H Alternate function 03H z Output control open drain 04H High drive enable 05H STOP mode recovery enable 06H FFH No function Port F Control PFCTL FESH Read Write D7 D6 D5 D4 D3 D2 D 1 DO Port F Control 7 0 Provides Access to Port Sub Registers PS019915 1005 Z8 Encore 64K Series Z8 Encore
328. ster to reset the Flash Controller 2 Write the page to be erased to the Page Select register 3 Write the first unlock command 73H to the Flash Control register 4 Write the second unlock command 8CH to the Flash Control register PS019915 1005 Flash Memory htt p ww xi npi an net COA ee ee DELI 010 62245566 13810019655 Z8 Encore 64K Series Product Specification L ZiLOG 5 Re write the page written in step 2 to the Page Select register 6 Write the Page Erase command 95H to the Flash Control register Mass Erase The Flash memory cannot be Mass Erased by user code Flash Controller Bypass The Flash Controller can be bypassed and the control signals for the Flash memory brought out to the GPIO pins Bypassing the Flash Controller allows faster Programming algorithms by controlling the Flash programming signals directly Flash Controller Bypass is recommended for gang programming applications and large volume customers who do not require in circuit programming of the Flash memory Refer to the document entitled Third Party Flash Programming Support for Z8 Encore 8 for more information on bypassing the Flash Controller This document is available for download at www zilog com Flash Controller Behavior in Debug Mode The following changes in behavior of the Flash Controller occur when the Flash Control ler is accessed using the On Chip Debugger The Flash Write Protect option bit is ignor
329. t 0 and then progresses sequentially through the other selected ADC Analog Inputs 0000 ADC Analog Input 0 updated 0001 ADC Analog Inputs 0 1 updated 0010 ADC Analog Inputs 0 2 updated 0011 ADC Analog Inputs 0 3 updated 0100 ADC Analog Inputs 0 4 updated 0101 ADC Analog Inputs 0 5 updated 0110 ADC Analog Inputs 0 6 updated 0111 ADC Analog Inputs 0 7 updated 1000 ADC Analog Inputs 0 8 updated 1001 ADC Analog Inputs 0 9 updated 1010 ADC Analog Inputs 0 10 updated 1011 ADC Analog Inputs 0 11 updated 1100 1111 Reserved DMA Status Register The DMA Status register Table 84 indicates the DMA channel that generated the inter rupt and the ADC Analog Input that is currently undergoing conversion Reads from this register reset the Interrupt Request Indicator bits IRQA IRQ1 and IRQO to 0 There PS019915 1005 Direct Memory Access Controller htt p ww xi npi an net LEE EB DRE EL EE EGET ET VE Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 170 ZiLOG fore software interrupt service routines that read this register must process all three inter rupt sources from the DMA Table 84 DMA ADC Status Register DMAA STAT BITS 7 6 5 4 3 2 1 0 FIELD CADC 3 0 Reserved IRQA IRQI IRQO RESET 0 R W R ADDR FBFH PS019915 1005 htt p ww xi npi an net Hg g d
330. t Timing 0 0 0 eee eee eee 225 Table 116 GPIO Port Output Timing 0 0 eee RII 226 Table 117 On Chip Debugger Timing 0 0 cece eee eee 227 Table 118 SPI Master Mode Timing sees 228 Table 119 SPI Slave Mode Timing 0 0 00 ccc IA 229 Table 120 DC TIMIDE eeepc err Ren etc date ace New we 230 Table 121 UART Timing with CTS 0 00 0 eee IA 231 Table 122 UART Timing without CTS 0 0 0 232 Table 123 Notational Shorthand 0 0 0 0 ccc e ee 235 Table 124 Additional Symbols 0 0 cece cece eee 236 Table 125 Condition Codes 0 eects 237 Table 126 Arithmetic Instructions 0 cece eee eee nee 238 Table 127 Bit Manipulation Instructions 0 0 0 cee eee eee 239 Table 128 Block Transfer Instructions llle 239 Table 129 CPU Control Instructions 0 0 0 240 Table 130 Load Instructions 0 0 cece III 240 Table 131 Logical Instructions 0 0 0 0 eee cece eens 241 Table 132 Program Control Instructions 0 0 eee ee eee eee 241 Table 133 Rotate and Shift Instructions llle 242 Table 134 eZ8 CPU Instruction Summary 0 0 eee eee eee 242 Table 135 Opcode Map Abbreviations 0 0 0 e eee ee eee eee 254 PS019915 1005 List of Tables htt p ww xi npi an net DOT 010 62245566 13810019655 Z8 Encore 64
331. t period is given by the following equation WDT Reload Value WDT Time out Period ms 10 where the WDT reload value is the decimal value of the 24 bit value given by WDTU 7 0 WDTH 7 0 WDTL 7 0 and the typical Watch Dog Timer RC oscillator frequency is 10kHz The Watch Dog Timer cannot be refreshed once it reaches 000002H The WDT Reload Value must not be set to values below 000004H Table 46 provides information on approximate time out delays for the minimum and maximum WDT reload values PS019915 1005 Watch Dog Timer htt p ww xi npi an net DOT 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z ZiLOG Table 46 Watch Dog Timer Approximate Time Out Delays Approximate Time Out Delay WDT Reload Value WDT Reload Value with 10kHz typical WDT oscillator frequency Hex Decimal Typical Description 000004 4 400us Minimum time out delay FFFFFF 16 777 215 1677 58 Maximum time out delay Watch Dog Timer Refresh When first enabled the Watch Dog Timer is loaded with the value in the Watch Dog Timer Reload registers The Watch Dog Timer then counts down to 000000H unless a WDT instruction is executed by the eZ8 CPU Execution of the WDT instruction causes the downcounter to be reloaded with the WDT Reload value stored in the Watch Dog Timer Reload registers Counting resumes following the reload operation When the 64K Series devices are operating in Debug
332. t r 4 bit Working Register DA Destination address R 8 bit register ER Extended Addressing register rl R1 Irl Irrl IR1 rr Destination address RR1 IRRI ERI IM Immediate data value r2 R2 Ir2 Irr2 IR2 rr2 Source address RR2 IRR2 ER2 Ir Indirect Working Register RA Relative IR Indirect register IT Working Register Pair Irr Indirect Working Register Pair RR Register Pair PS019915 1005 Opcode Maps htt p ww xi npi an net CUO OE eo oo 010 62245566 13810019655 2 3 ADD ri 2 2 4 ADD r1 lr2 3 3 ADD R2 R 3 4 ADD IR2 R Lower Nibble Hex 6 3 3 ADD R1 IM 7 3 4 ADD R1 IM 8 4 3 ADDX ER2 ER 9 4 3 M ER 2 3 ADC ri 2 2 4 ADC r1 lr2 3 3 ADC R2 R 3 4 ADC IR2 R 3 3 ADC R1 IM 3 4 ADC R1 IM 4 3 ADCX ER2 ER 4 3 R 2 3 SUB r2 2 4 SUB r1 lr2 3 3 SUB R2 R 3 4 SUB IR2 R 3 3 SUB R1 IM 3 4 SUB R1 IM 4 3 SUB ER2 E 4 3 M ER 2 3 SBC r2 2 4 SBC r1 lr2 3 3 SBC R2 R 3 4 SBC IR2 R 3 3 SBC R1 IM 3 4 SBC R1 IM 4 3 SBC ER2 E 4 3 M ER 2 3 OR ri 2 2 4 OR r1 lr2 3 3 OR R2 R 3 4 OR IR2 R 3 3 OR R1 IM 3 4 OR R1 IM 4 3 ORX ER2 ER 4 3 ORX M ER 2 3 AND ri 2 2 4 AND r1 lr2 3 3 AND R2 R 3 4 AND IR2 R 3 3 AND R1 IM 3 4 AND R1 IM 4 3 ANDX ER2 ER 4 3 ANDX M ER 2 3 TCM
333. ter bits from O through 7 Table 28 IRQO Enable High Bit Register IRQOENH BITS 7 6 5 4 3 2 1 0 FIELD T2ENH TIENH TOENH UORENH UOTENH I2CENH SPIENH ADCENH RESET 0 R W R W ADDR FCIH PS019915 1005 Interrupt Controller htt p ww xi npi an net utu Oe PSEPED EU og 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Lin ZiLOG T2ENH Timer 2 Interrupt Request Enable High Bit TIENH Timer 1 Interrupt Request Enable High Bit TOENH Timer 0 Interrupt Request Enable High Bit UORENH UART 0 Receive Interrupt Request Enable High Bit UOTENH UART 0 Transmit Interrupt Request Enable High Bit I2CENH P C Interrupt Request Enable High Bit SPIENH SPI Interrupt Request Enable High Bit ADCENH ADC Interrupt Request Enable High Bit Table 29 IRQO Enable Low Bit Register IRQOENL BITS 7 6 5 4 3 2 1 0 FIELD T2ENL TIENL TOENL UORENL UOTENL I2CENL SPIENL ADCENL RESET 0 R W R W ADDR FC2H T2ENL Timer 2 Interrupt Request Enable Low Bit TIENL Timer 1 Interrupt Request Enable Low Bit TOENL Timer 0 Interrupt Request Enable Low Bit UORENL UART 0 Receive Interrupt Request Enable Low Bit UOTENL UART 0 Transmit Interrupt Request Enable Low Bit I2CENL I C Interrupt Request Enable Low Bit SPIENL SPI Interrupt Request Enable Low Bit ADCENL ADC
334. ters Port Register Mnemonic Port Register Name PxADDR Port A H Address Register Selects sub registers PxCTL Port A H Control Register Provides access to sub registers PxIN Port A H Input Data Register PxOUT Port A H Output Data Register Port Sub Register Mnemonic Port Register Name PxDD Data Direction PxAF Alternate Function PxOC Output Control Open Drain PxDD High Drive Enable PxSMRE STOP Mode Recovery Source Enable Port A H Address Registers The Port A H Address registers select the GPIO Port functionality accessible through the Port A H Control registers The Port A H Address and Control registers combine to pro vide access to all GPIO Port control Table 14 Table 14 Port A H GPIO Address Registers Px ADDR BITS y 6 5 4 3 2 1 0 FIELD PADDR 7 0 RESET 00H R W R W ADDR FDOH FD4H FD8H FDCH FEOH FE4H FE8H FECH PS019915 1005 General Purpose I O htt p ww xi npi an net D U 010 62245566 13810019655 Uu UU Z8 Encore 64K Series Product Specification 56 ZiLOG PADDR 7 0 Port Address The Port Address selects one of the sub registers accessible through the Port Control reg ister PADDR 7 0 Port Control sub register accessible using the Port A H Control Registers 00H No
335. the PS019915 1005 Timers htt p ww xi npi an net ugagamBpmmuagdisqiaudtt Ooo 010 62245566 13810019655 htt p ww xi npi an net EE Z8 Encore 64K Series Product Specification ZiLOG Timer Input signal When the Capture event occurs an interrupt is generated and the timer continues counting The timer continues counting up to the 16 bit Reload value stored in the Timer Reload High and Low Byte registers Upon reaching the Reload value the timer generates an interrupt and continues counting The steps for configuring a timer for CAPTURE mode and initiating the count are as fol lows 1 Write to the Timer Control 1 register to Disable the timer Configure the timer for CAPTURE mode Set the prescale value Set the Capture edge rising or falling for the Timer Input 2 Write to the Timer High and Low Byte registers to set the starting count value typically 0001H Write to the Timer Reload High and Low Byte registers to set the Reload value 4 Clearthe Timer PWM High and Low Byte registers to 0000H This allows user software to determine if interrupts were generated by either a capture event or a reload If the PWM High and Low Byte registers still contain 0000H after the interrupt then the interrupt was generated by a Reload 5 If desired enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers 6 Confi
336. the contents of the PC Data register 2nd byte of address 13 The IC Controller shifts the second address byte out the SDA signal After the first bit has been sent the Transmit interrupt is asserted 14 Software responds by setting the STOP bit in the I2C Control register The TXI bit can be cleared at the same time 15 Software polls the STOP bit of the PC Control register Hardware deasserts the STOP bit when the transaction is completed STOP condition has been sent 16 Software checks the ACK bit of the C Status register If the slave acknowledged the ACK bit is 1 If the slave does not acknowledge the ACK bit is 0 The NCKI interrupt do not occur because the STOP bit was set Write Transaction with a 10 Bit Address Figure 31 illustrates the data transfer format for a 10 bit addressed slave Shaded regions indicate data transferred from the C Controller to slaves and unshaded regions indicate data transferred from the slaves to the I7C Controller Slave Address Slave Address S ist7 bits 70 2nd Byte A Data A Data A A P S Figure 31 10 Bit Addressed Slave Data Transfer Format PS019915 1005 12C Controller htt p ww xi npi an net ugagamBmgmuagdisqiudtut Ooo 010 62245566 13810019655 Z8 Encore 64K Series Product Specification 148 ZiLOoGG The first seven bits transmitted in the first byte are 11110xx The two bits XX are the two most significa
337. timer to generate the SPI interrupt 0 No SPI interrupt request pending 1 SPI interrupt request is pending OVR Overrun 0 An overrun error has not occurred 1 An overrun error has been detected COL Collision 0 A multi master collision mode fault has not occurred 1 A multi master collision mode fault has been detected ABT Slave mode transaction abort This bit is set if the SPI is configured in slave mode a transaction is occurring and SS deasserts before all bits of a character have been transferred as defined by the NUMBITS field of the SPIMODE register The IRQ bit also sets indicating the transaction has com pleted 0 A slave mode transaction abort has not occurred 1 A slave mode transaction abort has been detected Reserved Must be 0 TXST Transmit Status 0 No data transmission currently in progress 1 Data transmission currently in progress Serial Peripheral Interface IG1 D U DLE 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Zi ZiLOG SLAS Slave Select If SPI enabled as a Slave 0 SS input pin is asserted Low 1 SS input is not asserted High If SPI enabled as a Master this bit is not applicable SPI Mode Register The SPI Mode register Table 65 configures the character bit width and the direction and value of the SS pin Table 65 SPI Mode Register SPIMODE
338. tiprocess Mode bit 0 00 Interrupt on all received bytes 01 Interrupt only on address bytes 10 Interrupt on address match and following data 11 Interrupt on data following an address match UARTI Status 1 UOSTAT1 FACH Read Only D7ID6 ID5 D4D3D2DDI DO L Mulitprocessor Receive Returns value of last multiprocessor bit L New Frame 0 Current byte is not start of frame 1 Current byte is start of new frame Reserved UARTI Address Compare UOADDR FADH Read Write D7 D6 ID5 ID4ID3D2ID1 DO UARTI Address Compare 7 0 PS019915 1005 Z8 Encore 64K Series Z8 Encore 32 ZiLOG UARTI Baud Rate Generator High Byte UOBRH F4EH Read Write D7 D6 D5 D4 D3 D2 DI DO UARTI Baud Rate divisor 15 8 UARTI Baud Rate Generator Low Byte UIBRL F4FH Read Write D7 D6 D5 D4 D3 D2 DI DO UARTI Baud Rate divisor 7 0 I2C Data I2CDATA F50H Read Write D7 D6 D5IDA4D3 D2IDI1 DO I2C data 7 0 I2C Status I2CSTAT F51H Read Only D7 D6 DSIDAID3ID2IDI DO L NACK Interrupt 0 No action required to service NAK 1 START STOP not set after NAK L Data Shift State 0 Data is not being transferred 1 Data is being transferred Transmit Address State 0 Addres
339. transmitting 0 CTS signal has no effect on the 1 Transmission is complete transinitter 1 UART recognizes CTS signal as a Transmitter Data Register Empty transmit able control gnal 0 Transmit Data Register is full 1 Transmit Data register is empty Receive Enable Break Detect 0 Receiver disabled 0 No break occurred 1 Receiver enabled 1 A break occurred Transmit Enable 0 Transmitter disabled 1 Transmitter enabled Framing Error 0 No framing error occurred 1 A framing occurred Overrun Error 0 No overrun error occurred 1 An overrun error occurred Parity Error 0 No parity error occurred 1 A parity error occurred Receive Data Available 0 Receive Data Register is empty 1 A byte is available in the Receive Data Register PS019915 1005 Control Register Summary htt p ww xi npi an net COA ee ee DELI 010 62245566 13810019655 UARTO Control 1 UOCTLI F43H Read Write D7ID6 ID5 D4D3DD2DDI DO L Infrared Encoder Decoder Enable 0 Infrared endec is disabled 1 Infrared endec is enabled L Received Data Interrupt Enable 0 Received data and errors generate interrupt requests 1 Only errors generate interrupt requests Received data does not Baud Rate Registers Control Refer to UART chapter for operation Driver Enable Polarity 0 DE signal is active High 1 DE signal is active Lo
340. tten to the UART Transmit Data register The Driver Enable signal asserts at least one UART bit period and no greater than two UART bit periods before the PS019915 1005 UART htt p ww xi npi an net DOT 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z ZiLOG Start bit is transmitted This timing allows a setup time to enable the transceiver The Driver Enable signal deasserts one system clock period after the last Stop bit is transmit ted This one system clock delay allows both time for data to clear the transceiver before disabling it as well as the ability to determine if another character follows the current character In the event of back to back characters new data must be written to the Trans mit Data Register before the previous character is completely transmitted the DE signal is not deasserted between characters The DEPOL bit in the UART Control Register 1 sets the polarity of the Driver Enable signal a 2 lt Data Field Stop Bit Idle State of Line Isb msb 1 T Start Bito l Biti Bit2 Bit3 i Bit4 Bit5 K Bit6 y Bit7 Y Pari 0 Pt Figure 17 UART Driver Enable Signal Timing shown with 1 Stop Bit and Parity The Driver Enable to Start bit setup time is calculated as follows mmn DE to Start Bit Setup Time s P Baud Rate Hzy P Baud Rate Hz UART Interrupts The UART features separate interrupts for the
341. ue Stop condition after data transmission is complete Send Start Condition 0 Do not send Start Condition 1 Send Start Condition I2C Enable 0 12C is disabled 1 DC is enabled Z8 Encore 64K Series Z8 Encore 33 ZiLOG SPI Data SPIDATA F60H Read Write D7 D6ID5 D4ID3 D2ID1 DO L SPI Data 7 0 SPI Control SPICTL F61H Read Write D7 D6 DSIDAID3ID2IDI DO L SPI Enable 0 SPI disabled 1 SPI enabled ___ Master Mode Enabled 0 SPI configured in Slave mode 1 SPI configured in Master mode Wire OR open drain Mode Enabled 0 SPI signals not configured for open drain m 1 SPI signals SCK SS MISO and MOST configured for open drain Clock Polarity 0 SCK idles Low 1 SPI idles High Phase Select Sets the phase relationship of the data to the clock BRG Timer Interrupt Request 0 BRG timer function is disabled 1 BRG time out interrupt is enabled Start an SPI Interrupt Request 0 No effect 2 Generate an SPI interrupt request Interrupt Request Enable 0 SPI interrupt requests are disabled 1 SPI interrupt requests are enabled I2C Baud Rate Generator High Byte DCBRH F53H Read Write D7 D6 D5 D4 D3 D2 D1 Do I2C Baud Rate divisor 15 8 I2C Baud Rate Generator Low Byte DCBRL F54H Read Write
342. ues to run 0 DMAO is disabled 1 DMAO is enabled DMAO I O Address DMAOIO FB1H Read Write D7 D6 D5 D4 D3 D2 D1 DO DMAO Peripheral Register Address Low byte of on chip peripheral control registers on Register File page FH PS019915 1005 htt p ww xi npi an net Z8 Encore 64K Series DMAO Address High Nibble DMAOH FB2H Read Write D7 D6 D5 D4 D3 D2 D1 D0 Z8 Encore 35 ZiLOG DMAO Start Address 11 8 DMAO End Address 11 8 DMAO Start Current Address Low Byte DMAOSTART FB3H Read Write D7 D6ID5 D4ID3 D2ID1 DO DMAO End Address Low Byte DMAOEND FB4H Read Write D7 D6 D5 D4 D3 D2 DI DO DMAI Control DMAICTL FB8H Read Write D7 D6 DSIDA4D3 D2IDI1 DO 000 Timer 0 001 Timer 1 010 2 Timer 2 011 2 Timer 3 is empty 1s empty is empty 111 Reserved Word Select DMAI Loop Enable DMAI Enable 0 DMA is disabled 1 DMAI is enabled L DMAO Start Address 7 0 L DMAO0 End Address 7 0 L Request Trigger Source Select 100 UARTO Transmit Data register 101 UARTI Transmit Data register 110 I2C Transmit Data register 0 DMA transfers 1 byte per request 1 DMA transfers 2 bytes per request DMAI Interrupt Ena
343. uming the Timer Input signal is still asserted Also if the Timer Output alternate function is enabled the Timer Output pin changes state from Low to High or from High to Low at timer reset PS019915 1005 Timers HHHEHEHIGBUHBBHBHH 010 62245566 13810019655 htt p ww xi npi an net EE Z8 Encore 64K Series Product Specification 83 ZiLOG The steps for configuring a timer for GATED mode and initiating the count are as follows 1 Write to the Timer Control 1 register to Disable the timer Configure the timer for GATED mode Set the prescale value 2 Write to the Timer High and Low Byte registers to set the starting count value This only affects the first pass in GATED mode After the first timer reset in GATED mode counting always begins at the reset value of 0001H Write to the Timer Reload High and Low Byte registers to set the Reload value 4 If desired enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers 5 Configure the associated GPIO port pin for the Timer Input alternate function 6 Write to the Timer Control 1 register to enable the timer 7 Assert the Timer Input signal to initiate the counting CAPTURE COMPARE Mode In CAPTURE COMPARE mode the timer begins counting on the first external Timer Input transition The desired transition rising edge or falling edge is set by the TPOL bit in the Timer Control 1 Regi
344. us In MULTI PROCESSOR mode also referred to as 9 Bit mode the multiprocessor bit MP is transmitted immediately following the 8 bits of data and immediately preceding the Stop bit s as illustrated in Figure 16 The character format is S Data Field p Stop Bit s Idle State B of Line Isi si b m 1 T A Sen Bito y Bit1 Bit2 Y Bit3 l Bit4 l Bit5 Bit6 y Bit7 y MP 0 Figure 16 UART Asynchronous MULTIPROCESSOR Mode Data Format In MULTIPROCESSOR 9 bit mode the Parity bit location 9th bit becomes the MUL TIPROCESSOR control bit The UART Control 1 and Status 1 registers provide MULTI PROCESSOR 9 bit mode control and status information If an automatic address matching scheme is enabled the UART Address Compare register holds the network address of the device MULTIPROCESSOR 9 bit Mode Receive Interrupts When MULTIPROCESSOR mode is enabled the UART only processes frames addressed to it The determination of whether a frame of data is addressed to the UART can be made in hardware software or some combination of the two depending on the multiprocessor configuration bits In general the address compare feature reduces the load on the CPU since it does not need to access the UART when it receives data directed to other devices PS019915 1005 UART htt p ww xi npi an net ugagamBpmmuagdisqiaudtt Ooo 010 62245566 13810019655 Z8 Encore 64K Series
345. vice UOTXI UART 0 Transmitter Interrupt Request 0 No interrupt request is pending for the UART 0 transmitter 1 An interrupt request from the UART 0 transmitter is awaiting service POLITIC Interrupt Request 0 No interrupt request is pending for the PC 1 An interrupt request from the IC is awaiting service SPII SPI Interrupt Request 0 No interrupt request is pending for the SPI 1 An interrupt request from the SPI is awaiting service ADCI ADC Interrupt Request 0 No interrupt request is pending for the Analog to Digital Converter 1 An interrupt request from the Analog to Digital Converter is awaiting service Interrupt Request 1 Register The Interrupt Request 1 IRQ1 register Table 25 stores interrupt requests for both vec tored and polled interrupts When a request is presented to the interrupt controller the cor responding bit in the IRQ register becomes 1 If interrupts are globally enabled vectored interrupts the interrupt controller passes an interrupt request to the eZ8 CPU If interrupts are globally disabled polled interrupts the eZ8 CPU can read the Interrupt Request 1 register to determine if any interrupt requests are pending PS019915 1005 Interrupt Controller htt p ww xi npi an net DOT 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z ZILOG Table 25 Interrupt Request 1 Register
346. vices data is shifted on one edge of the SCK and is sam pled on the opposite edge where data is stable Edge polarity is determined by the SPI phase and polarity control Slave Select The active Low Slave Select SS input signal selects a Slave SPI device SS must be Low prior to all data communication to and from the Slave device SS must stay Low for the full duration of each character transferred The SS signal may stay Low during the transfer of multiple characters or may deassert between each character When the SPI is configured as the only Master in an SPI system the SS pin can be set as either an input or an output For communication between the Z8F642x familyZ8R642x family device s SPI Master and external Slave devices the SS signal as an output can assert the SS input pin on one of the Slave devices Other GPIO output pins can also be employed to select external SPI Slave devices When the SPI is configured as one Master in a multi master SPI system the SS pin must be set as an input The SS input signal on the Master must be High If the SS signal goes Low indicating another Master is driving the SPI bus a Collision error flag is set in the SPI Status register SPI Clock Phase and Polarity Control The SPI supports four combinations of serial clock phase and polarity using two bits in the SPI Control register The clock polarity bit CLKPOL selects an active high or active low clock and has no effect on the transfer form
347. w Multiprocessor Bit Transmit 0 Send a 0 as the multiprocessor bit 1 Senda 1 as the multiprocessor bit Multiprocessor Mode 0 See Multiprocessor Mode 1 below Multiprocessor 9 bit Enable 0 Multiprocessor mode is disabled 1 Multiprocessor mode is enabled Multiprocessor Mode 1 with Multiprocess Mode bit 0 00 Interrupt on all received bytes 01 Interrupt only on address bytes 10 Interrupt on address match and following data 11 Interrupt on data following an address match UARTO Status 1 UOSTATI F44H Read Only D7ID6 ID5 D4D3DD2DDI DO L Mulitprocessor Receive Returns value of last multiprocessor bit L New Frame 0 Current byte is not start of frame 1 Current byte is start of new frame Reserved UARTO Address Compare UOADDR F45H Read Write D7 D6 D5 D4ID3D2ID1 DO UARTO Address Compare 7 0 PS019915 1005 Z8 Encore 64K Series Z8 Encore ZiLOG UARTO Baud Rate Generator High Byte UOBRH F46H Read Write D7 D6 D5 D4 D3 D2 D1 DO UARTO Baud Rate divisor 15 8 UARTO Baud Rate Generator Low Byte UOBRL F47H Read Write D7 D6 D5 D4 D3D2DI DO UARTO Baud Rate divisor 7 0 UARTI Transmit Data UITXD F48H Write Only D7 D6 D5 D4 D3 D2 D1 DO U
348. w xi npi an net DOT 010 62245566 13810019655 vi ZiLOG Clear To Send CTS Operation ssssssseleeee eA 104 MULTIPROCESSOR 9 bit Mode 2 0 cee eee eee 104 External Driver Enable waded a ieee hia oM RR ee re ad 105 UART Interrupts corren eben er E doble due 106 UART Baud Rate Generator lleeeeeeeeeee eee nee 108 UART Control Register Definitions 0 0 0 cece eee eee 109 UART Transmit Data Register 0 0 eect eee 109 UART Receive Data Register 0 0 ce eee cette 110 UART Stat s O Register oes Rt EUER ek begs 110 UART Status 1 Register secas bbe em bon dew chageaa ahae rea whaaeda 112 UART Control 0 and Control 1 Registers llle eese 112 UART Address Compare Register 0 0 eee eee 115 UART Baud Rate High and Low Byte Registers 0 00005 115 Infrared Encoder Decoder 4064 cscin kk b RR EREROP ER TERRE RTT ET EFE E 120 OVerVieW suicide et bte ore dibs oleae ene eol d dele oa e RE o 120 Architecture lel a tech v RR SOR cede e Rr AERE cee goals 120 Operation used oco eub Gants ala eee anal A 121 Transmitting IrDA Data cerie ie eaae a a E A A E E K S 121 Receiving IrDA Data 0 0 cette eens 122 Infrared Encoder Decoder Control Register Definitions 000 124 Serial Peripheral Interface 0 cece cece cece eee eee e eee ehh nn nn 125 OVEIVIEW PEE Seo Ow PA AL Sod ea
349. ystal Oscillator Configuration Table 103 Recommended Crystal Oscillator Specifications 20MHz Operation Parameter Value Units Comments Frequency 20 MHz Resonance Parallel Mode Fundamental Series Resistance Rs 25 Q Maximum Load Capacitance C 20 pF Maximum Shunt Capacitance Co 7 pF Maximum Drive Level 1 mW Maximum PS019915 1005 On Chip Oscillator htt p ww xi npi an net utu ee ee EU og 010 62245566 13810019655 Z8 Encore 64K Series Product Specification Z 207 ZiLOG Oscillator Operation with an External RC Network The External RC oscillator mode is applicable to timing insensitive applications Figure 41 illustrates a recommended configuration for connection with an external resis tor capacitor RC network Vpp Figure 41 Connecting the On Chip Oscillator to an External RC Network An external resistance value of 45k 2 is recommended for oscillator operation with an external RC network The minimum resistance value to ensure operation is 40kQ The typical oscillator frequency can be estimated from the values of the resistor R in kQ and capacitor C in pF elements using the following equation 1x10 Oscillator Frequency kHz 04 xRx C 4xC Figure 42 illustrates the typical 3 3V and 25 C oscillator frequency as a function of the capacitor C in pF employed in the RC network assuming a 45kQ externa

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