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SECTION 9 EXTERNAL BUS INTERFACE

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1. Note the delay for the internal to external cycle may be one clock or greater Figure 9 38 Retry of External Master Access Internal Arbiter 9 5 13 Show Cycle Transactions Show cycles are accesses to the CPU s internal bus devices These accesses are driven externally for emulation visibility and debugging purposes A show cycle can have one address phase and one data phase or just an address phase in the case of instruction show cycles The cycle can be a write or a read access The data for both the read and write accesses should be driven by the bus master This is different from normal bus read and write accesses The address and data of the show cycle must each be valid on the bus for one clock The data phase must not require a transfer MOTOROLA EXTERNAL BUS INTERFACE MPC555 9 54 Rev 15 Nov 98 USER S MANUAL acknowledge to terminate the bus show cycle In a burst show cycle only the first data beat is shown externally Refer to Table 9 9 for show cycle transaction encodings Instruction show cycle bus transactions have the following characteristics see Figure 9 39 e One clock cycle e Address phase only e STS assertion only no TA assertion ADDR 0 31 ADDR1 i RD WR TSIZ 0 1 Normal Non Show Cycle Bus Transaction Instruction Show Cycle Bus Transactio Figure 9 39 Instruction Show Cycle Transaction MPC555 EXTERNAL BUS INTERFACE MOTOROLA USER S MANUAL Rev 15
2. CLKOUT ADDR 0 31 i a le 2 i RD WR 3 h X seon V le Y gt lt gt gt lt gt Slave 1 Slave 1 Slave 2 Slave 2 allowed to drive negates acknowledge allowed to drive negates acknowledge acknowledge signals signals and turns off acknowledge signals signals and turns off Figure 9 27 Termination Signals Protocol Timing Diagram 9 5 9 Storage Reservation The MPC555 storage reservation protocol supports a multi level bus structure For each local bus storage reservation is handled by the local reservation logic The protocol tries to optimize reservation cancellation such that a PowerPC processor is notified of storage reservation loss on a remote bus only when it has issued a stwcx cycle to that address That is the reservation loss indication comes as part of the stwcx cycle This method avoids the need to have very fast storage reservation loss indication signals routed from every remote bus to every PowerPC master The storage reservation protocol makes the following assumptions e Each processor has at most one reservation flag e lwarx sets the reservation flag e lwarx by the same processor clears the reservation flag related to a previous lwarx instruction and again sets the reservation flag e stwcx by the same processor clears the reservation flag e Store by the same processor d
3. lt D ADDR 30 31 RD WR TSI2 0 1 oO oO BURST has ae z BURST and BDIP will be asserted for one cycle if the RCPU core requests a burst but the USIU splits it into a sequence of normal cycles Figure 9 18 Burst Inhibit Cycle 32 Bit Port Size Emulated Burst MPC555 EXTERNAL BUS INTERFACE MOTOROLA USER S MANUAL Rev 15 Nov 98 9 25 ADDR 0 29 n n mbdulo 4 1 ADDR 30 31 RD WR TSIZ 0 1 Data Figure 9 19 Non Wrap Burst with Three Beats MOTOROLA EXTERNAL BUS INTERFACE MPC555 9 26 Rev 15 Nov 98 USER S MANUAL CLKOUT ADDR 0 29 n n modulo 4 3 RD WR BDIP i Is Never Asserted First and Last Beat TA DATA is Sampled Figure 9 2 Non Wrap Burst with One Data Beat MPC555 EXTERNAL BUS INTERFACE MOTOROLA USER S MANUAL Rev 15 Nov 98 9 27 9 5 5 Alignment and Packaging of Transfers The MPC555 external bus requires natural address alignment e Byte accesses allow any address alignment e Half word accesses require address bit 31 to equal zero e Word accesses require address bits 30 31 to equal zero e Burst accesses require address bits 30 31 to equal zero The MPC555 performs operand transfers through its 32 bit data port If the transfer is controlled by the internal memory controller the MPC555 can support 8 and 16 bit data port sizes The bus requires that the portion of the data b
4. BURST eww T i i i La a TS A o i i i l i i i Last Beat Expects Another Data 1 Nou N i minis nee SS Data Data Data Data Wait State is Valid is Valid is Valid is Valid lt Figure 9 13 Burst Read Cycle 32 Bit Port Size One Wait State MOTOROLA EXTERNAL BUS INTERFACE MPC555 9 20 Rev 15 Nov 98 USER S MANUAL CLKOUT ADDR 0 31 ADDR 28 51 0000 RD WR F Lag ee E ate Expects Another Data be i Vi Data Data Data Data Data is Valid is Valid is Valid is Valid Wait State Figure 9 14 Burst Read Cycle 32 Bit Port Size Wait States Between Beats MPC555 EXTERNAL BUS INTERFACE MOTOROLA USER S MANUAL Rev 15 Nov 98 9 21 CLKOUT ADDR 0 31 ADDR 28 31 0000 RD WR TSIZ 0 1 00 BURST cp N Data 0 15 X TA TE Figure 9 15 Burst Read Cycle 16 Bit Port Size SEGaen s EE FE Wiiiiii MOTOROLA EXTERNAL BUS INTERFACE MPC555 9 22 Rev 15 Nov 98 USER S MANUAL Master Request Bus BR Receive Bus Grant BG from Arbiter Assert Bus Busy BB if No Other Master is Driving Assert Transfer Start TS Drive Address and Attributes Drive BURST Asserted Slave
5. Drive data Receive Address ADDR 28 29 mod 4 77 Assert BDIP Y Sample Data Assert Transfer Acknowledge TA y Drive Data 1 gt Assert BDIP Assert Transfer Acknowledge TA I BNIp o Don t Sample BDIP Asserted Next Data Yes Sample Data y Drive Data a Assert BDIP Assert Transfer Acknowledge TA I No x Don t Sample Next Data BDIP Asserted Yes Sample Data T Drive Data 3 o Negate Burst Data in Progress BDIP o Don t Sample Sil Next Data BDIP Asserted Yes Sample Data _ Assert Transfer Acknowledge TA Y Stop Driving Data i Don t Sample Next Data BDIP Asserted Yes Figure 9 16 Basic Flow Diagram of a Burst Write Cycle MPC555 EXTERNAL BUS INTERFACE Rev 15 Nov 98 9 23 USER S MANUAL MOTOROLA CLKOUT ADDR 0 31 ADDR 28 29 RD WR TSIZ 0 1 ae BURST LIL Last Beat Will Drive Another Data 7 i N o CET o ia Sampled is Tana ie Snes is Sampled aa Figure 9 17 Burst Write Cycle 32 Bit Port Size Zero Wait States MOTOROLA EXTERNAL BUS INTERFACE MPC555 9 24 Rev 15 Nov 98 USER S MANUAL CLKOUT ADDR 0 27 ADDR 28 29
6. Indicates the start of a transaction on the external bus or signals the beginning of an internal transaction in show cycle mode Reservation Protocol CR Each PowerPC CPU has its own CR signal Assertion of CR instructs the bus master to clear its reservation 1 EOW some other master has touched its reserved space Cancel reservation Sin i This is a pulsed signal In case of a bus cycle initiated by a STWCX instruc KR tion issued by the RCPU to a non local bus on which 1 Low I the storage reservation has been lost this signal is Kill reservation used by the non local bus interface to backoff the cy cle Refer to 9 5 9 Storage Reservation for details MPC555 USER S MANUAL EXTERNAL BUS INTERFACE Rev 15 Nov 98 MOTOROLA 9 5 Table 9 1 MPC555 SIU Signals Continued Signal Name Pins Active 1 0 Description Data DATAI0 31 Data bus 32 High The data bus has the following byte lane assign ments Data Byte Byte Lane DATAJ 0 7 0 DATA 8 15 1 DATA 16 23 2 DATA 24 31 3 Driven by the MPC555 when it owns the external bus and it initiated a write transaction to a slave device For single beat transactions the byte lanes not select ed for the transfer by ADDR 30 31 and TSIZ 0 1 do not supply valid data In addition the MPC555 drives DATA 0 31 when an external master owns the external bus and initiated a read transaction to an intern
7. attached pullup The MPC555 asserts the RETRY signal for one clock in order to retry the external master access If the address of the external access does not match the internal memory space the internal memory controller can provide the chip select and control signals for accesses that belong to one of the memory controller regions This feature is explained in SEC TION 10 MEMORY CONTROLLER Figure 9 33 and Figure 9 36 illustrate the basic flow of read and write external master accesses MPC555 EXTERNAL BUS INTERFACE MOTOROLA USER S MANUAL Rev 15 Nov 98 9 47 External Master MPC555 Request Bus BR Y Receives Bus Grant BG From Arbiter Y Asserts Bus Busy BB if No Other Master is Driving Assert Transfer Start TS Drives Address and Attributes Receives Address Y Address in Interna Memory Map Memory Controller Returns Data Asserts CSx I lf In Range Asserts Transfer Acknowledge TA Receives Data Figure 9 33 Basic Flow of an External Master Read Access MOTOROLA EXTERNAL BUS INTERFACE MPC555 9 48 Rev 15 Nov 98 USER S MANUAL External Master MPC555 Request Bus BR Y Receives Bus Grant BG From Arbiter Y Asserts Bus Busy BB if No Other Master is Driving Assert Transfer Start TS Drives Address and Attributes Receives Address Y Drives Data Address in Interna Memory Map Mem
8. 31 RD WR TSIZ 0 1 Stel ae 21 y J 7 3 sn y C Figure 9 8 Single Beat Basic Write Cycle Timing Zero Wait States Data is sampled MPC555 EXTERNAL BUS INTERFACE MOTOROLA USER S MANUAL Rev 15 Nov 98 9 13 CLKOUT BR BG Z Receive bus grant and bus busy negated Assert BB drive address and assert TS O ADDR 0 31 RD WR TSIZ 0 1 NDK 7 1 OC lt gt AAA v AHOL Wait state Data is sampled Figure 9 9 Single Beat Basic Write Cycle Timing One Wait State 9 5 2 3 Single Beat Flow with Small Port Size The general case of single beat transfers assumes that the external memory has a 32 bit port size The MPC555 provides an effective mechanism for interfacing with 16 bit and 8 bit port size memories allowing transfers to these devices when they are con trolled by the internal memory controller In this case the MPC555 attempts to initiate a transfer as in the normal case If the bus interface receives a small port size 16 or 8 bits indication before the transfer acknowledge to the first beat through the internal memory controller the MCU ini tiates successive transactions until the completion of the data transfer Note that all the transactions initiated to complete the data transfer are considered
9. 9 21 Interface To Different Port Size Devices Table 9 3 lists the bytes required on the data bus for read cycles MPC555 EXTERNAL BUS INTERFACE MOTOROLA USER S MANUAL Rev 15 Nov 98 9 29 a Table 9 3 Data Bus Requirements For Read Cycles 8 bit Address 32 bit Port Size 16 bit Port Size Port Transfer TSIZE Size Size 0 1 ADDR DATA DATA DATA DATA DATA DATA DATA 30 31 0 7 8 15 16 23 24 31 0 7 8 15 0 7 01 00 OPO OPO OPO 01 01 OP1 OP1 OP1 Byte 01 10 OP2 OP2 OP2 01 11 OP3 OP3 OP3 10 00 OPO OP1 OPO OP1 OPO Half word 10 10 OP2 OP3 OP2 OP3 OP2 Word 00 00 OPO OP1 OP2 OP3 OPO OP1 OPO NOTE denotes a byte not required during that read cycle Table 9 4 lists the patterns of the data transfer for write cycles when the MPC555 ini tiates an access Table 9 4 Data Bus Contents for Write Cycles Address External Data Bus Pattern Transfer y Size TS ZE 0 1 ADDR DATA DATA DATA DATA 30 31 0 7 8 15 16 23 24 31 01 00 OPO 01 01 OP1 OP1 Byte 01 10 OP2 OP2 01 11 OP3 OP3 OP3 10 00 OPO OP1 Half word 10 10 OP2 OP3 OP2 OP3 Word 00 00 OPO OP1 OP2 OP3 NOTE denotes a byte not driven during that write cycle 9 5 6 Arbitration Phase The external bus design provides f
10. Nov 98 9 55 Both read and write data show cycles have the following characteristics see Figure 9 40 e Two clock cycle duration e Address valid for two clock cycles e Data is valid only in the second clock cycle e STS signal only is asserted no TA or TS ADDR 0 31 ADDRI1 ADDR2 RD WR TSIZ 0 1 BURST Fa HE ie TA Read Data Show Cycle Bus Transaction Write Data Show Cycle Bus Transaction Figure 9 40 Data Show Cycle Transaction MOTOROLA EXTERNAL BUS INTERFACE MPC555 9 56 Rev 15 Nov 98 USER S MANUAL
11. S MANUAL Rev 15 Nov 98 9 7 9 5 1 Basic Transfer Protocol The basic transfer protocol defines the sequence of actions that must occur on the MPC555 bus to perform a complete bus transaction A simplified scheme of the basic transfer protocol is illustrated in Figure 9 3 a Arbitration Address Transfer Data Transfer Termination Figure 9 3 Basic Transfer Protocol The basic transfer protocol provides for an arbitration phase and an address and data transfer phase The address phase specifies the address for the transaction and the transfer attributes that describe the transaction The data phase performs the transfer of data if any is to be transferred The data phase may transfer a single beat of data 4 bytes or less for nonburst operations a 4 beat burst of data 4 x 4 bytes an 8 beat burst of data 8 x 2 bytes or a 16 beat burst of data 16 x 1 bytes 9 5 2 Single Beat Transfer During the data transfer phase the data is transferred from master to slave in write cycles or from slave to master on read cycles During a write cycle the master drives the data as soon as it can but never earlier than the cycle following the address transfer phase The master has to take into consider ation the one dead clock cycle switching between drivers to avoid electrical contentions The master can stop driving the data bus as soon as it samples the TA line asserted on the rising edge of the CLKOUT Durin
12. addressed device does al not have burst capability If this signal is asserted the master must transfer in multiple cycles and increment the address for the slave to complete the burst transfer For a system that does not use the burst mode at all this signal can be tied low permanently 9 5 8 3 Transfer Error Acknowledge The TEA signal terminates a bus cycle under one or more bus error conditions The current bus cycle must be aborted This signal overrides any other cycle termination signals such as transfer acknowledge 9 5 8 4 Termination Signals Protocol The transfer protocol was defined to avoid electrical contention on lines that can be driven by various sources To this end a slave must not drive signals associated with the data transfer until the address phase is completed and it recognizes the address as its own The slave must disconnect from signals immediately after it has acknowl edged the cycle and no later than the termination of the next address phase cycle This means that the termination signals must be connected to power through a pull up resistor to avoid the situation in which a master samples an undefined value in any of these signals when no real slave is addressed Refer to Figure 9 26 and Figure 9 27 Slave 1 External Bus Acknowledge Signals Slave 2 Figure 9 26 Termination Signals Protocol Basic Connection MPC555 EXTERNAL BUS INTERFACE MOTOROLA USER S MANUAL Rev 15 Nov 98 9 39
13. it owns the exter nal bus Driven low indicates that a burst transfer is in progress Driven high indicates that the current trans fer is not a burst The MPC555 does not support burst accesses to internal slaves TSI2 0 1 Transfer size High Driven by the MPC555 along with the address when it owns the external bus Specifies the data transfer size for the transaction Driven by an external master when it owns the exter nal bus Specifies the data transfer size for the trans action AT 0 3 Address type High Driven by the MPC555 along with the address when it owns the external bus Indicates additional informa tion about the address on the current transaction Only for testing purposes RSV Reservation transfer Low Driven by the MPC555 along with the address when it owns the external bus Indicates additional informa tion about the address on the current transaction Only for testing purposes PTR Program trace High Driven by the MPC555 along with the address when it owns the external bus Indicates additional informa tion about the address on the current transaction Only for testing purposes Low In the case of regular transaction this signal is driven by the slave device to indicate that the MPC555 must relinquish the ownership of the bus and retry the cy cle When an external master owns the bus and the inter nal MPC555 bus init
14. supplied by the MPC555 remain stable during the transfers The selected device terminates each transfer by driving or sampling the word on the data bus and asserting TA The MPC555 also supports burst inhibited transfers for slave devices that are unable to support bursting For this type of bus cycle the selected slave device supplies or samples the first word the MPC555 points to and asserts the burst inhibit signal with TA for the first transfer of the burst access The MPC555 responds by terminating the burst and accessing the remainder of the 16 byte block These remaining accesses use up to three read write bus cycles each one for a word in the case of a 32 bit port width slave up to seven read write bus cycles in the case of a 16 bit port width slave or up to fifteen read write bus cycles in the case of a 8 bit port width slave The general case of burst transfers assumes that the external memory has a 32 bit port size The MPC555 provides an effective mechanism for interfacing with 16 bit port size memories and 8 bit port size memories allowing bursts transfers to these devices when they are controlled by the internal memory controller In this case the MPC555 attempts to initiate a burst transfer as in the normal case If the memory controller signals to the bus interface that the external device has a small port size 8 or 16 bits and if the burst is accepted the bus interface completes a burst of 8 or 16 beats Each of the da
15. the MPC555 when the slave device is con trolled by the on chip memory controller the MPC555 also asserts BI for any external master burst access to internal MPC555 memory space MOTOROLA 9 6 EXTERNAL BUS INTERFACE MPC555 Rev 15 Nov 98 USER S MANUAL Table 9 1 MPC555 SIU Signals Continued Signal Name Pins Active 1 0 Description ARBITRATION When the internal arbiter is enabled BR assertion in dicates that an external master is requesting the bus Driven by the MPC555 when the internal arbiter is dis abled and the chip is not parked When the internal arbiter is enabled the MPC555 as serts this signal to indicate that an external master may assume ownership of the bus and begin a bus a o _ transaction The BG signal should be qualified by the BG master requesting the bus in order to ensure it is the 1 Low bus owner Qualified bus grant BG amp BB When the internal arbiter is disabled BG is sampled I and properly gualified by the MPC555 when an exter nal bus transaction is to be executed by the chip When the internal arbiter is enabled the MPC555 as serts this signal to indicate that it is the current owner of the bus O When the internal arbiter is disabled the MPC555 as serts this signal after the external arbiter has granted BB the ownership of the bus to the chip and it is ready to 1 Low start the transaction Bus busy When the internal arbiter is enabled the MPC555 samples this sig
16. the initiated transfer Table 9 10 Termination Signals Protocol TEA TA RETRY Action Asserted X X Transfer error termination Negated Asserted X Normal transfer termination Negated Negated Asserted Retry transfer termination 9 5 11 Bus Operation in External Master Modes When an external master takes ownership of the external bus and the MPC555 is pro grammed for external master mode operation the external master can access the internal space of the MPC555 see 6 2 External Master Modes In an external mas ter mode the external master owns the bus and the direction of most of the bus signals is inverted relative to its direction when the MPC555 owns the bus The external master gets ownership of the bus and asserts TS in order to initiate an external master access The access is directed to the internal bus only if the input address matches the internal address space The access is terminated with one of the followings outputs TA TEA or RETRY If the access completes successfully the MPC555 asserts TA and the external master can proceed with another external mas ter access or relinquish the bus If an address or data error is detected internally the MPC555 asserts TEA for one clock TEA should be negated before the second rising edge after it is sampled asserted in order to avoid the detection of an error for the next bus cycle initiated TEA is an open drain pin and the negation timing depends on the
17. to be part of an atomic transaction so the MCU does not allow other unrelated master accesses or MOTOROLA EXTERNAL BUS INTERFACE MPC555 9 14 Rev 15 Nov 98 USER S MANUAL first is re tried during an access to a small port then an exception is generated to the bus arbitration to intervene between the transfers If any of the transactions except the EI xl RCPU CLKOUT RD WR TSIZ O 1 w Kim BURST BDIP a a SOU STS FA a i IRA EA w i Figure 9 10 Single Beat 32 Bit Data Write Cycle Timing 16 Bit Port Size 9 5 3 Burst Transfer The MPC555 uses non wrapping burst transfers to access operands of up to 16 bytes four words A non wrapping burst access stops accessing the external device when the word address is modulo four The MPC555 begins the access by supplying a start ing address that points to one of the words and requiring the memory device to seguentially drive or sample each word on the data bus The selected slave device MPC555 EXTERNAL BUS INTERFACE MOTOROLA USER S MANUAL Rev 15 Nov 98 9 15 must internally increment ADDR28 and ADDR29 and ADDR30 in the case of a 16 bit port slave device and also ADDR31 in the case of an 8 bit port slave device of the supplied address for each transfer causing the address to reach a four word bound ary and then stop The address and transfer attributes
18. 0 MPC555 Internal Master With Higher Priority than the External Device Requires the Bus External Master Requests Bus Ext Master Release Bus B 0 MCU Needs the Bus MPC555 No Longer Needs the Bus BR 0 External Device With Higher Priority than the Current Internal Bus Master Requests the Bus MPC555 Still Needs the Bus Figure 9 25 Internal Bus Arbitration State Machine 9 5 7 Address Transfer Phase Signals Address transfer phase signals include the following e Transfer start e Address bus e Transfer attributes Transfer attributes signals include RD WR BURST TSIZ 0 1 AT 0 3 STS and BDIP With the exception of the BDIP these signals are available at the same time as the address bus MPC555 EXTERNAL BUS INTERFACE MOTOROLA USER S MANUAL Rev 15 Nov 98 9 35 9 5 7 1 Transfer Start This signal TS indicates the beginning of a transaction on the bus addressing a slave al device This signal should be asserted by a master only after the ownership of the bus was granted by the arbitration protocol This signal is asserted for the first cycle of the transaction only and is negated in successive clock cycles until the end of the trans action The master should three state this signal when it relinquishes the bus to avoid contention between two or more masters in this line This situation indicates that an external pull up resistor should be connected to the TS signal to avoid having a slave recogniz
19. 5 internal bus can be terminated with relinquish and retry in order to allow a pending internal to external access to be executed The RETRY signal functions as an output that signals the external master to release the bus ownership and retry the access after one clock a Figure 9 37 describes the flow of an external master retried access Figure 9 38 shows the timing when an external access is retried and a pending internal to external access follows MOTOROLA EXTERNAL BUS INTERFACE MPC555 9 52 Rev 15 Nov 98 USER S MANUAL External Master MPC555 Request Bus BR Y Receives BusGrant BG from Arbiter Y Asserts Bus Busy BB if No Other Master is Driving Assert Transfer Start TS Drives Address and Attributes Assert Retry y Release Bus Request BR for One Clock and Request Bus BR Again Wait Until Bus Busy Negated No Other Master is Driving Assert Bus Busy BB Assert Transfer Start TS Drives Address and Attributes Receives Address Address in Interna Memory Map Memory Controller Asserts CSx Returns Data If In Range Asserts Transfer Acknowledge TA A Receives Data Figure 9 37 Flow of Retry of External Master Read Access MPC555 EXTERNAL BUS INTERFACE MOTOROLA USER S MANUAL Rev 15 Nov 98 9 53 Allow Internal Access to Gain the Bus ADDR 0 31 ADDR internal RD WR TSIZ 0 1 Data
20. B and initiate the trans action without waiting for BG from the arbiter The priority of the external device relative to the internal MPC555 bus masters is pro grammed in the SIU module configuration register If the external device requests the bus and the MPC555 does not require it or if the external device has higher priority than the current internal bus master the MPC555 grants the bus to the external device Table 9 5 describes the priority mechanism used by the internal arbiter MPC555 EXTERNAL BUS INTERFACE MOTOROLA USER S MANUAL Rev 15 Nov 98 9 33 Table 9 5 Priority Between Internal and External Masters over External Bus Type Direction Priority Parked access Internal gt external 0 Instruction access Internal external 3 Data access Internal external 4 External access external external internal EARP could be programmed to 0 7 NOTES 1 External master will be granted external bus ownership if EARP is greater than the internal access pri ority 2 Parked access is instruction or data access from the RCPU which is initiated on the internal bus without requesting it first in order to improve performance 3 Refer to 6 13 1 1 SIU Module Configuration Register Figure 9 25 illustrates the internal finite state machine that implements the arbiter protocol MOTOROLA EXTERNAL BUS INTERFACE MPC555 9 34 Rev 15 Nov 98 USER S MANUAL External Owner BG
21. BG Acknowledge Bus Mastership e 1 Wait for BB to be negated 2 Assert BB to becom enext master 3 Negate BR y Terminate Arbitration 1 Negate BG or keep asserted to park xx bus master Operate as bus Master 1 Perform data transfer Release Bus Mastership 1 Negate BB Figure 9 22 Bus Arbitration Flowchart 9 5 6 1 Bus Request The potential bus master asserts BR to request bus mastership BR should be negated as soon as the bus is granted the bus is not busy and the new master can drive the bus If more requests are pending the master can keep asserting its bus request as long as needed When configured for external central arbitration the MPC555 drives this signal when it requires bus mastership When the internal on chip arbiter is used this signal is an input to the internal arbiter and should be driven by the external bus master 9 5 6 2 Bus Grant The arbiter asserts BG to indicate that the bus is granted to the requesting device This signal can be negated following the negation of BR or kept asserted for the current master to park the bus MPC555 EXTERNAL BUS INTERFACE MOTOROLA USER S MANUAL Rev 15 Nov 98 9 31 When configured for external central arbitration BG is an input signal to the MPC555 from the external arbiter When the internal on chip arbiter is used this signal is an out put from the internal arbiter to the external bus mas
22. Drive BURST Asserted ADDR 28 29 mod 4 7 Assert BDIP alu Data Assert Transfer Acknowledge TA I Receive Data aceive Ad iosa O _ Drive Last Data 1 i amp Assert TA gt Assert BDIP Return Data Assert Transfer Acknowledge TA I I Receive Data Drive Last Data 2 amp Assert TA gt Assert BDIP Return Data Assert Transfer Acknowledge TA I BDIP Asserted Receive Data Drive Last Data 3 amp Assert TA Sh Yes Return Data o Negate Burst Data in Progress BDIP Assert Transfer Acknowledge TA Y Receive Sata Drive Last Data amp Assert TA BDIP Asserted Yes Figure 9 11 Basic Flow Diagram Of A Burst Read Cycle MOTOROLA EXTERNAL BUS INTERFACE MPC555 9 18 Rev 15 Nov 98 USER S MANUAL CLKOUT ADDR 0 31 ADDR 28 31 0000 RD WR TSIZ 0 1 66 BURST ini TS Last Beat Expects Another Data BDIP o wn 7 Data TA Data Data Data Data is Valid is Valid is Valid is Valid Figure 9 12 Burst Read Cycle 32 Bit Port Size Zero Wait State MPC555 EXTERNAL BUS INTERFACE MOTOROLA USER S MANUAL Rev 15 Nov 98 9 19 CLKOUT ADDR 0 31 ADDR 28 31 0000 RD WR TSI2I0 1
23. SECTION 9 EXTERNAL BUS INTERFACE XI The MPC555 bus is a synchronous burstable bus Signals driven on this bus are required to make the setup and hold time relative to the bus clock s rising edge The bus has the ability to support multiple masters The MPC555 architecture supports byte half word and word operands allowing access to 8 16 and 32 bit data ports through the use of synchronous cycles controlled by the size outputs TSIZO TSIZ1 For accesses to 16 and 8 bit ports the slave must be controlled by the memory controller 9 1 Features The external bus interface features are listed below e 32 bit address bus with transfer size indication only 24 available on pins e 32 bit data bus e Bus arbitration logic on chip supports an external master e Internal chip select and wait state generation to support peripheral or static mem ory devices through the memory controller e Supports various memory SRAM EEPROM types synchronous and asynchro nous burstable and non burstable e Supports non wrap bursts e Flash ROM programming support e Compatible with PowerPC architecture e Easy to interface to slave devices e Bus is synchronous all signals are referenced to rising edge of bus clock e Bus can operate at the same frequency as the MPC555 or half the frequency 9 2 Bus Transfer Signals The bus transfers information between the MPC555 and external memory of a periph eral device External devices can accept or provid
24. U The reservation protocol for a multi level local bus is illustrated in Figure 9 29 The system describes the situation in which the reserved location is sited in the remote bus MPC555 EXTERNAL BUS INTERFACE MOTOROLA USER S MANUAL Rev 15 Nov 98 9 41 ia External Bus Local Bus External Bus Interface AT 0 3 RSV RAW TS ADDR 0 29 Local Master Accesseses with Iwarx to Remove Bus Address Buses Interface A Master in the Remote Bus Write L to the Reserved Location Remote Bus Figure 9 29 Reservation On Multilevel Bus Hierarchy In this case the bus interface block implements a reservation flag for the local bus master The reservation flag is set by the bus interface when a load with reservation is issued by the local bus master and the reservation address is located on the remote bus The flag is reset when an alternative master on the remote bus accesses the same location in a write cycle If the MPC555 begins a memory cycle to the previously reserved address located in the remote bus as a result of an stwex instruction the following two cases can occur e If the reservation flag is set the buses interface acknowledges the cycle in a nor mal way e If the reservation flag is reset the bus interface should assert the KR However MOTOROLA EXTERNAL BUS INTERFACE MPC555 9 42 Rev 15 Nov 98 USER S MANUAL remote bus supports aborted cycles In this ca
25. UAL CLKOUT BR BG Receive bus grant and bus busy negated assert BB drive address and assert TS ADDR 0 31 RD WR TSI2 0 1 BURST BDIP N DK J Ps 2 TH TS ENI MH oy o un Wait state Data is valid Figure 9 6 Single Beat Read Cycle Basic Timing One Wait State 9 5 2 2 Single Beat Write Flow The basic write cycle begins with a bus arbitration followed by the address transfer then the data transfer The handshakes are illustrated in the following flow and timing diagrams as applicable to the fixed transaction protocol MPC555 EXTERNAL BUS INTERFACE MOTOROLA USER S MANUAL Rev 15 Nov 98 9 11 Master Slave Y Request bus BR y Receive bus grant BG from arbiter Assert bus busy BB if no other master is driving bus Assert transfer start TS Drive address and attributes Drive data Y Assert transfer acknowledge TA y Interrupt data driving Figure 9 7 Basic Flow Diagram of a Single Beat Write Cycle MOTOROLA EXTERNAL BUS INTERFACE Rev 15 Nov 98 USER S MANUAL 9 12 MPC555 CLKOUT BR BG Z Receive bus grant and bus busy negated Assert BB drive address and assert TS ADDR O
26. al slave module Driven by the slave in a read transaction For single beat transactions the MPC555 does not sample byte lanes that are not selected for the transfer by ADDR 30 31 and TSIZ 0 1 In addition an external master that owns the bus and initiated a write transaction to an internal slave mod ule drives DATA 0 31 Transfer Cycle Termination TA Transfer acknowledge LOW Driven by the slave device to which the current trans action was addressed Indicates that the slave has re ceived the data on the write cycle or returned data on the read cycle If the transaction is a burst TA should be asserted for each one of the transaction beats Driven by the MPC555 when the slave device is con trolled by the on chip memory controller or when an external master initiated a transaction to an internal slave module TEA Transfer error acknowledge Low Driven by the slave device to which the current trans action was addressed Indicates that an error condi tion has occurred during the bus cycle Driven by the MPC555 when the internal bus monitor detected an erroneous bus condition or when an ex ternal master initiated a transaction to an internal slave module and an internal error was detected BI Burst inhibit Low Driven by the slave device to which the current trans action was addressed Indicates that the current slave does not support burst mode Driven by
27. e 0 1 1 1 RCPU show cycle address instruction supervisor mode i 0 1 0 RCPU reservation show cycle data supervisor mode 0 1 1 1 RCPU show cycle data supervisor mode 1 0 0 4 RCPU show cycle address instruction program trace user 0 mode 1 1 1 RCPU show cycle address instruction user mode i 0 1 0 RCPU reservation show cycle data user mode 1 1 1 RCPU show cycle data user mode 1 1 1 Reserved NOTES 1 Cases in which both TS and STS are asserted indicate normal cycles with the show cycle attribute 9 5 7 7 Burst Data in Progress This signal is sent from the master to the slave to indicate that there is a data beat fol lowing the current data beat The master uses this signal to give the slave advance warning of the remaining data in the burst BDIP can also be used to terminate the burst cycle early Refer to 9 5 3 Burst Transfer and 9 5 4 Burst Mechanism for more information 9 5 8 Termination Signals The EBI uses three termination signals e Transfer acknowledge TA Burst inhibit Bl e Transfer error acknowledge TEA 9 5 8 1 Transfer Acknowledge Transfer acknowledge indicates normal completion of the bus transfer During a burst cycle the slave asserts this signal with every data beat returned or accepted MOTOROLA EXTERNAL BUS INTERFACE MPC555 9 38 Rev 15 Nov 98 USER S MANUAL 9 5 8 2 Burst Inhibit A slave sends the BI signal to the master to indicate that the
28. e 8 16 and 32 bits in parallel and must follow the handshake protocol described in this section The maximum number of bits accepted or provided during a bus transfer is defined as the port width The MPC555 contains an address bus that specifies the address for the transfer and a data bus that transfers the data Control signals indicate the beginning and type of the cycle as well as the address space and size of the transfer The selected device then controls the length of the cycle with the signal s used to terminate the cycle A strobe signal for the address bus indicates the validity of the address and provides tim ing information for the data The MPC555 bus is synchronous The bus and control input signals must be timed to setup and hold times relative to the rising edge of the clock Bus cycles can be com pleted in two clock cycles For all inputs the MPC555 latches the level of the input during a sample window around the rising edge of the clock signal This window is illustrated in Figure 9 1 where tsu and tho are the input setup and hold times respectively To ensure that an MPC555 EXTERNAL BUS INTERFACE MOTOROLA USER S MANUAL Rev 15 Nov 98 9 1 input signal is recognized on a specific falling edge of the clock that input must be sta ble during the sample window If an input makes a transition during the window time period the level recognized by the MPC555 is not predictable however the MPC555 always resolves the latch
29. e this signal as asserted when no master drives it Refer to Figure 9 23 9 5 7 2 Address Bus The address bus consists of 32 bits with ADDRO the most significant bit and ADDR31 the least significant bit The bus is byte addressable so each address can address one or more bytes The address and its attributes are driven on the bus with the trans fer start signal and kept valid until the bus master receives the transfer acknowledge signal from the slave To distinguish the individual byte the slave device must observe the TSIZ signals 9 5 7 3 Read Write A high value on the RD WR line indicates a read access A low value indicates a write access 9 5 7 4 Burst Indicator BURST is driven by the bus master at the beginning of the bus cycle along with the address to indicate that the transfer is a burst transfer The MPC555 supports a non wrapping four beat maximum critical word first burst type The maximum burst size is 16 bytes For a 32 bit port the burst includes four beats For a 16 bit port the burst includes 8 beats For an 8 bit port the burst includes 16 beats at most Note that 8 and 16 bit ports must be controlled by the memory controller The actual size of the burst is determined by the address of the starting word of the burst Refer to Table 9 6 and Table 9 7 Table 9 6 Burst Length and Order Starting Burst Order Assuming BurstLengthin Burst Length Address A Com
30. ed level to either a logic high or low before using it In addition to meeting input setup and hold times for deterministic operation all input signals must obey the protocols described in this section tho gt gt tsu Clock s Sample Window Figure 9 1 Input Sample Window 9 3 Bus Control Signals The MPC555 initiates a bus cycle by driving the address size address type cycle type and read write outputs At the beginning of a bus cycle TSIZO and TSIZ1 are driven with the address type signals TSIZO and TSIZ1 indicate the number of bytes remaining to be transferred during an operand cycle consisting of one or more bus cycles These signals are valid at the rising edge of the clock in which the transfer start TS signal is asserted The read write RD WR signal determines the direction of the transfer during a bus cycle Driven at the beginning of a bus cycle RD WR is valid at the rising edge of the clock in which TS is asserted The logic level of RD WR only changes when a write cycle is preceded by a read cycle or vice versa The signal may remain low for con secutive write cycles MOTOROLA EXTERNAL BUS INTERFACE MPC555 9 2 Rev 15 Nov 98 USER S MANUAL ADDR 0 31 RD WR gt BURST TSIZ 0 1 Address ATI0 3 and i Transfer zil gt Attributes STS Bl BDIP gt TS Transfer Start RSV gt KR R
31. es BDIP to indicate to the slave that the next data beat transfer is the last data of the burst write transfer BDIP has two basic timings normal and late see Figure 9 13 and Figure 9 14 In the late timing mode assertion of BDIP is delayed by the number of wait states in the first data beat This implies that for zero wait state cycles BDIP assertion time is identical in normal and late modes Cycles with late BDIP generation can occur only during cycles for which the memory controller generates TA internally Refer to SECTION 10 MEMORY CONTROLLER for more information In the MPC555 no internal master initiates write bursts The MPC555 is designed to perform this kind of transaction in order to support an external master that is using the memory controller services Refer to 10 7 Memory Controller External Master Support During the data phase of a burst read cycle the master receives data from the addressed slave If the master needs more than one data beat it asserts BDIP Upon receiving the second to last data beat the master negates BDIP The slave stops driv ing new data after it receives the negation of the BDIP signal at the rising edge of the clock MPC555 EXTERNAL BUS INTERFACE MOTOROLA USER S MANUAL Rev 15 Nov 98 9 17 Master Slave Request Bus BR Receive bus grant BG from arbiter Assert Bus Busy BB if No Other Master is Driving Assert Transfer Start TS Drive Address and Attributes
32. eservation CR Protocol DATA 0 31 b ata RETRY BI STS gt I ST TA ail Transfer gt Cycle TEA Termination BR E BG gt Arbitration BB gt Figure 9 2 MPC555 Bus Signals 9 4 Bus Interface Signal Descriptions Table 5 1 diatribes each signal in the bus interface unit More detailed descriptions can be found in subsequent subsections MPC555 EXTERNAL BUS INTERFACE MOTOROLA USER S MANUAL Rev 15 Nov 98 9 3 Table 9 1 MPC555 SIU Signals Signal Name Pins Active 1 0 Description Address and Transfer Attributes ADDR 0 31 Address bus 24 8 31 High O Specifies the physical address of the bus transaction Driven by an external bus master when it owns the ex ternal bus Only for testing purposes RD WR Read write High Driven by the MPC555 along with the address when it owns the external bus Driven high indicates that a read access is in progress Driven low indicates that a write access is in progress Driven by an external master when it owns the exter nal bus Driven high indicates that a read access is in progress Driven low indicates that a write access is in progress BURST Burst transfer Low Driven by the MPC555 along with the address when it owns the external bus Driven low indicates that a burst transfer is in progress Driven high indicates that the current transfer is not a burst Driven by an external master when
33. g a read cycle the master accepts the data bus contents as valid at the rising edge of the CLKOUT in which the TA signal is sampled asserted 9 5 2 1 Single Beat Read Flow The basic read cycle begins with a bus arbitration followed by the address transfer then the data transfer The handshakes are illustrated in the following flow and timing diagrams as applicable to the fixed transaction protocol MOTOROLA EXTERNAL BUS INTERFACE MPC555 9 8 Rev 15 Nov 98 USER S MANUAL Master Slave Y duain Reguest bus BR y Receive bus grant BG from arbiter y Assert bus busy BB if no other master is driving bus Assert transfer start TS Drive address and attributes y Receive address Y Return data y Assert transfer acknowledge TA Receive data Figure 9 4 Basic Flow Diagram of a Single Beat Read Cycle MPC555 EXTERNAL BUS INTERFACE MOTOROLA USER S MANUAL Rev 15 Nov 98 9 9 CLKOUT BR BG Receive bus grant and bus busy negated Assert BB drive address and assert TS ADDR 0 31 RD WR TSIZ 0 1 BURST BDIP N DK J Ps 2 x T 7 3 TS BEI T0 a Figure 9 5 Single Beat Read Cycle Basic Timing Zero Wait States Data is valid MOTOROLA EXTERNAL BUS INTERFACE MPC555 9 10 Rev 15 Nov 98 USER S MAN
34. he MPC555 initiates a burst access the bus interface recognizes the RETRY assertion as a retry termination only if it detects it before the first data beat was acknowledged by the slave device When the RETRY signal is asserted as a termina tion signal on any data beat of the access after the first being the first data beat acknowledged by a normal TA assertion the MPC555 recognizes RETRY as a trans fer error acknowledge MPC555 EXTERNAL BUS INTERFACE MOTOROLA USER S MANUAL Rev 15 Nov 98 9 45 Allow Externtl Master to Gainthe Bus ADDR 0 31 RD WR TSI2 0 1 Data l Asserted Will Cause Transfer Error Figure 9 32 Retry On Burst Cycle If a burst access is acknowledged on its first beat with a normal TA but with the BI sig nal asserted the following single beat transfers initiated by the MPC555 to complete the 16 byte transfer recognizes the RETRY signal assertion as a transfer error acknowledge In the case in which a small port size causes the MPC555 to break a bus transaction into several small transactions terminating any transaction with RETRY causes a transfer error acknowledge See 9 5 2 3 Single Beat Flow with Small Port Size MOTOROLA EXTERNAL BUS INTERFACE MPC555 9 46 Rev 15 Nov 98 USER S MANUAL 9 5 10 2 Termination Signals Protocol Summary Table 5 2 summarizes how the MPC555 recognizes the termination signals provided xi by the slave device that is addressed by
35. he PTR and RSV signals is for the reservation protocol described in 9 5 9 Storage Reservation Refer to 9 5 13 Show Cycle Transactions for informa tion on show cycles Table 9 8 summarizes the pins used to define the address type Table 9 9 lists all the definitions achieved by combining these pins Table 9 8 Address Type Pins Pin Function ore 0 Special transfer STS 1 Normal transfer TS 0 Start of transfer 1 No transfer ATO Must equal zero on MPC555 0 Supervisor mode AM 1 User mode 0 Instruction Ala 1 Data AT3 Reservation Program Trace DTD 0 Program trace PTR 1 No program trace RSV 0 Reservation data 1 No reservation MPC555 EXTERNAL BUS INTERFACE MOTOROLA USER S MANUAL Rev 15 Nov 98 9 37 Table 9 9 Address Types Definition STS TS ATO AT1 AT2 AT3 PTR RSV Address Space Definitions 1 x x x x x 1 1 No transfer 0 0 0 1 RCPU normal instruction program trace supervisor mode 1 1 1 RCPU normal instruction supervisor mode 5 i 0 1 0 RCPU reservation data supervisor mode 1 1 1 RCPU normal data supervisor mode 01 i 0 0 0 1 RCPU normal instruction program trace user mode 1 1 1 RCPU normal instruction user mode i 4 0 1 0 RCPU reservation data user mode 1 1 1 RCPU normal data user mode 1 1 1 Reserved 0 0 0 4 RCPU show cycle address instruction program trace su 0 pervisor mod
36. he same address address attributes and data in the case of a write cycle Figure 9 30 illustrates the behavior of the MPC555 when the RETRY signal is detected as a termination of a transfer As seen in this figure in the case when the internal arbiter is enabled the MPC555 negates BB and asserts BG in the clock cycle following the retry detection This allows any external master to gain bus ownership In the next clock cycle a normal arbitration procedure occurs again As shown in the figure the external master did not use the bus so the MPC555 initiates a new transfer with the same address and attributes as before In Figure 9 31 the same situation is shown except that the MPC555 is working with an external arbiter In this case in the clock cycle after the RETRY signal is detected asserted BR is negated together with BB One clock cycle later the normal arbitration procedure occurs again MPC555 EXTERNAL BUS INTERFACE MOTOROLA USER S MANUAL Rev 15 Nov 98 9 43 BG output BB i i Allow External Master to Gain the Bug ADDR 0 31 ADDR f ADDR RD WR TSIZ 0 1 Data Figure 9 30 Retry Transfer Timing Internal Arbiter MOTOROLA EXTERNAL BUS INTERFACE MPC555 Rev 15 Nov 98 USER S MANUAL A Allow External Master to Gain the Bus ADDR 0 31 RD WR TSIZ 0 1 Data Figure 9 31 Retry Transfer Timing External Arbiter When t
37. iates access to the external bus at the same time this signal is used to cause the ex ternal master to relinquish the bus for one clock to solve the contention MOTOROLA EXTERNAL BUS INTERFACE Rev 15 Nov 98 MPC555 USER S MANUAL Table 9 1 MPC555 SIU Signals Continued Signal Name Pins Active 1 0 Description Burst data in progress Low Driven by the MPC555 when it owns the external bus It is part of the burst protocol When BDIP is asserted the second beat in front of the current one is request ed by the master This signal is negated prior to the end of a burst to terminate the burst data phase early Driven by an external master when it owns the exter nal bus When BDIP is asserted the second beat in front of the current one is requested by the master This signal is negated prior to the end of a burst to ter minate the burst data phase early The MPC555 does not support burst accesses to internal slaves Transfer Start TS Transfer start Low O Driven by the MPC555 when it owns the external bus Indicates the start of a transaction on the external bus Driven by an external master when it owns the exter nal bus It indicates the start of a transaction on the external bus or in show cycle mode signals the be ginning of an internal transaction STS Special transfer start Low O Driven by the MPC555 when it owns the external bus
38. ments ADDR 28 29 32 bit Port Size Words Beats in Bytes word 0 word 1 gt np word 2 word 3 i Ie 01 word 1 word 2 word 3 3 12 10 word 2 word 3 2 8 11 word 3 1 4 BDIP never asserted MOTOROLA EXTERNAL BUS INTERFACE MPC555 9 36 Rev 15 Nov 98 USER S MANUAL 9 5 7 5 Transfer Size The transfer size signals TSIZ 0 1 indicate the size of the requested data transfer al During each transfer the TSIZ signals indicate how many bytes are remaining to be transferred by the transaction The TSIZ signals can be used with BURST and ADDR 30 31 to determine which byte lanes of the data bus are involved in the trans fer For nonburst transfers the TSIZ signals specify the number of bytes starting from the byte location addressed by ADDR 30 31 In burst transfers the value of TSIZ is always 00 Table 9 7 BURST TSIZE Encoding BURST TSIZ 0 1 Transfer Size Negated 01 Byte Negated 10 Half word Negated 11 Xx Negated 00 Word Asserted 00 Burst 16 bytes 9 5 7 6 Address Types The address type AT 0 3 program trace PTR and reservation transfer RSV sig nals are outputs that indicate one of 16 address types These types are designated as either a normal or alternate master cycle user or supervisor and instruction or data type The address type signals are valid at the rising edge of the clock in which the special transfer start STS signal is asserted A special use of t
39. nal to get indication of when the exter nal master ended its bus tenure BB negated BR l 1 Low Bus request O Bus grant When the internal arbiter is disabled the BB is sam pled to properly qualify the BG line when an external bus transaction is to be executed by the chip 9 5 Bus Operations This section provides a functional description of the system bus the signals that con trol it and the bus cycles provided for data transfer operations It also describes the error conditions bus arbitration and reset operation The MPC555 generates a system clock output CLKOUT This output sets the fre quency of operation for the bus interface directly Internally the MPC555 uses a phase lock loop PLL circuit to generate a master clock for all of the CPU circuitry including the bus interface which is phase locked to the CLKOUT output signal All signals for the MPC555 bus interface are specified with respect to the rising edge of the external CLKOUT and are guaranteed to be sampled as inputs or changed as outputs with respect to that edge Since the same clock edge is referenced for driving or sampling the bus signals the possibility of clock skew could exist between various modules in a system due to routing or the use of multiple clock lines It is the respon sibility of the system to handle any such clock skew problems that could occur MPC555 EXTERNAL BUS INTERFACE MOTOROLA USER
40. oes not clear the reservation flag e Some other processor or other mechanism store to the same address as an ex isting reservation clears the reservation flag e In case the storage reservation is lost it is guaranteed that stwex will not modify the storage MOTOROLA EXTERNAL BUS INTERFACE MPC555 9 40 Rev 15 Nov 98 USER S MANUAL The reservation protocol for a single level local bus is illustrated in Figure 9 28 The protocol assumes that an external logic on the bus carries out the following functions e Snoops accesses to all local bus slaves e Holds one reservation for each local master capable of storage reservations e Sets the reservation when that master issues a load and reserve request e Clears the reservation when some other master issues a store to the reservation address MPC555 External Bus External Bus Interface Master Bus AT 0 3 RSV R W TS ADDR 0 29 external stwex access Reservation Logic CLKOUT Figure 9 28 Reservation On Local Bus The MPC555 samples the CR line at the rising edge of CLKOUT When this signal is asserted the reservation flag is reset The EBI samples the logical value of the reservation flag prior to externally starting a bus cycle initiated by the RCPU stwex instruction If the reservation flag is set the EBI begins with the bus cycle If the reservation flag is reset no bus cycle is initiated exter nally and this situation is reported to the RCP
41. or a single bus master at any one time either the MPC555 or an external device One or more of the external devices on the bus can have the capability of becoming bus master for the external bus Bus arbitration may be handled either by an external central bus arbiter or by the internal on chip arbiter In the latter case the system is optimized for one external bus master besides the MPC555 The arbitration configuration external or internal is set at system reset Each bus master must have bus request BR bus grant BG and bus busy BB sig nals The device that needs the bus asserts BR The device then waits for the arbiter to assert BG In addition the new master must look at BB to ensure that no other mas ter is driving the bus before it can assert BB to assume ownership of the bus Any time the arbiter has taken the bus grant away from the master and the master wants to exe cute a new cycle the master must re arbitrate before a new cycle can be executed MOTOROLA EXTERNAL BUS INTERFACE MPC555 9 30 Rev 15 Nov 98 USER S MANUAL The MPC555 however guarantees data coherency for access to a small port size and for decomposed bursts This means that the MPC555 will not release the bus before the completion of the transactions that are considered atomic Figure 9 22 describes the basic protocol for bus arbitration Requesting Device Arbiter Request the Bus 1 Assert BR __ GRANT Bus arbitration 1 Assert
42. ory Controller Asserts CSx If In Range Receives Data Asserts Transfer Acknowledge TA Figure 9 34 Basic Flow of an External Master Write Access Figure 9 35 Figure 9 35 and Figure 9 36 describe read and write cycles from an external master accessing internal space in the MPC555 Note that the minimum num MPC555 EXTERNAL BUS INTERFACE MOTOROLA USER S MANUAL Rev 15 Nov 98 9 49 ber of wait states for such access is two clocks The accesses in these figures are valid for both peripheral mode and slave mode Use the Internal Arbiter BG Receive Bus Grant and Bus Busy Negated Assert BB Drive Address and Assert TS ADDR 0 31 ee o O O RD WR mi 0 e E E mY TA output Hm Minimum 2 Wait States DATA is valid Figure 9 35 Peripheral Mode External Master Reads from MPC555 Two Wait States MOTOROLA EXTERNAL BUS INTERFACE MPC555 9 50 Rev 15 Nov 98 USER S MANUAL Use the Internal Arbiter BG Receive Bus Grant and Bus Busy Negated Assert BB Drive Address and Assert TS ADDR 0 31 ee EN NEE RD WR DC TA output Minimum 2 Wait States DATA is sampled Figure 9 36 Peripheral Mode External Master Writes to MPC555 Two Wait States MPC555 EXTERNAL BUS INTERFACE MOTOROLA USER S MANUAL Rev 15 Nov 98 9 51 9 5 12 Contention Resolution on External Bus When the MPC555 is in slave mode external master access to the MPC55
43. se the failure of the stwex instruc the bus interface should not perform the remote bus write access or abort it if the EI u tion is reported to the RCPU 9 5 10 Bus Exception Control Cycles The MPC555 bus architecture requires assertion of TA from an external device to sig nal that the bus cycle is complete TA is not asserted in the following cases e The external device does not respond e Various other application dependent errors occur External circuitry can provide TEA when no device responds by asserting TA within an appropriate period of time after the MPC555 initiates the bus cycle it can be the inter nal bus monitor This allows the cycle to terminate and the processor to enter exception processing for the error condition each one of the internal masters causes an internal interrupt under this situation To properly control termination of a bus cycle for a bus error TEA must be asserted at the same time or before TA is asserted TEA should be negated before the second rising edge after it was sampled as asserted to avoid the detection of an error for the next initiated bus cycle TEA is an open drain pin that allows the wired or of any different sources of error generation 9 5 10 1 Retrying a Bus Cycle When an external device asserts the RETRY signal during a bus cycle the MPC555 enters a sequence in which it terminates the current transaction relinquishes the own ership of the bus and retries the cycle using t
44. ta beats of the burst transfers effectively only one or two bytes Note that this burst of 8 or 16 beats is considered an atomic transaction so the MPC555 does not allow other unrelated master accesses or bus arbitration to intervene between the transfers 9 5 4 Burst Mechanism In addition to the standard bus signals the MPC555 burst mechanism uses the follow ing signals e The BURST signal indicates that the cycle is a burst cycle e The burst data in progress BDIP signal indicates the duration of the burst data e The burst inhibit BI signal indicates whether the slave is burstable At the start of the burst transfer the master drives the address the address attributes and the BURST signal to indicate that a burst transfer is being initiated and asserts TS If the slave is burstable it negates the burst inhibit Bl signal If the slave cannot burst it asserts BI During the data phase of a burst write cycle the master drives the data It also asserts BDIP if it intends to drive the data beat following the current data beat When the slave has received the data it asserts the signal transfer acknowledge to indicate to the master that it is ready for the next data transfer The master again drives the next data and asserts or negates the BDIP signal If the master does not intend to drive another MOTOROLA EXTERNAL BUS INTERFACE MPC555 9 16 Rev 15 Nov 98 USER S MANUAL data beat following the current one it negat
45. ter 9 5 6 3 Bus Busy BB assertion indicates that the current bus master is using the bus New masters should not begin transfer until this signal is negated The bus owner should not relin quish or negate this signal until the transfer is complete To avoid contention on the BB line the master should three state this signal when it gets a logical one value This requires the connection of an external pull up resistor to ensure that a master that acquires the bus is able to recognize the BB line negated regardless of how many cycles have passed since the previous master relinquished the bus Refer to Figure 9 23 Master External Bus MPC555 Slave 2 Figure 9 23 Masters Signals Basic Connection MOTOROLA EXTERNAL BUS INTERFACE MPC555 9 32 Rev 15 Nov 98 USER S MANUAL CLKOUT BRO ADDR Attr pem AS Ea aes TA gt lt gt gt Master 0 esa ae T sh d Turns On an Turns On and and Turns Off Drives Signals Three state Controls es Signals Figure 9 24 Bus Arbitration Timing Diagram 9 5 6 4 Internal Bus Arbiter The MPC555 can be configured at system reset to use the internal bus arbiter In this case the MPC555 will be parked on the bus The parking feature allows the MPC555 to skip the bus request phase and if BB is negated assert B
46. us used for a transfer to or from a par ticular port size be fixed A 32 bit port must reside on DATA 0 31 a 16 bit port must reside on DATA 0 15 and an 8 bit port must reside on DATA 0 7 The MPC555 always tries to transfer the maximum amount of data on all bus cycles For a word operation it always assumes that the port is 32 bits wide when beginning the bus cycle In Figure 9 20 Figure 9 21 Table 9 3 and Table 9 4 the following conventions are used e OPO is the most significant byte of a word operand and OP3 is the least signifi cant byte e The two bytes of a half word operand are either OPO most significant and OP1 or OP2 most significant and OP3 depending on the address of the access e The single byte of a byte length operand is OPO OP1 OP2 or OP3 depending on the address of the access 0 31 OPO OP1 OP2 OP3 Word OPO OP1 Half word OP2 OP3 OPO OP1 Byte OP2 OP3 Figure 9 20 Internal Operand Representation Figure 9 21 illustrates the device connections on the data bus MOTOROLA EXTERNAL BUS INTERFACE MPC555 9 28 Rev 15 Nov 98 USER S MANUAL 0 31 Interface Sr ae OPO OP1 OP2 OP3 F Output Register DATA O0 7 DATA 8 15 DATA 16 23 DATA 24 31 OPO OP1 OP2 OP3 32 bit Port Size OPO OP1 16 bit Port Size OP2 OP3 OPO OP1 8 bit Port Size OP2 OP3 Figure

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