QFN16EVB Evaluation Board Manual for High Frequency QFN-16
Contents
1. Each input and output requires one SMA connector Install all the required SMA connectors onto the board and solder the center signal conductor pin to the board on J1 through J16 Please note that the alignment of the signal connector pin of the SMA connector to the metal trace on the board can influence lab results The launch and reflection of the signals are largely influenced by imperfect alignment and soldering of the SMA connector Validating the Assembled Board After assembling the evaluation board it is recommended to perform continuity checks on all soldered areas before commencing with the evaluation process Time Domain Reflectometry TDR is another highly recommended validation test http onsemi com 4 QFN16EVB Table 1 EXAMPLE CONFIGURATION Device NB6L14M mma f DO SD I CR CR RC A e CN IR CN RC eonnestor ves ves Yoo veo vos Yeo No Yoo ves Yoo vos voo No Wo vs vos wre no n ne No no no ves ne No no no no ono Vor ne no_ NOTE Dut GND Exposed Pad and should be tied to Vee DUTGND CONFIGURATIONS Top View Verify Pinout on Datasheet DUT_GND Install 0 1 uF Decoupling Capaci Bottom View tor Here and At Package Pins Figure 6 Example of Power Supply Configuration for Device i e NB6L14M http onsemi com 5 QFN16EVB Power Supply Voc VEE DUTGND Differential Digital Oscilloscope or Signal Frequency Counter Generat2. QFN16EVB Evaluation Board Manual for High Frequency QFN 16 Prepared by Casey Stys ON Semiconductor Introduction ON Semiconductor has developed the QFN16EVB evaluation board for its high performance devices packaged in the 16 Pin OFN This evaluation board was designed to provide a flexible and convenient platform to quickly evaluate characterize and verify the operation of various ON Semiconductor products Many QFN16EVBs are dedicated with a device already installed and can be ordered from www onsemi com at the specific device web page This evaluation board manual contains e Information on 16 lead QFN Evaluation Board e Assembly Instructions e Appropriate Lab Setup Bill of Materials This user s manual provides detailed information on board contents layout and its use It should be used in conjunction with an appropriate ON Semiconductor device Top View ON Semiconductor http onsemi com EVALUATION BOARD MANUAL datasheet located at www onsemi com The datasheet contains the technical device specifications Board Layout The QFN16 Evaluation Board provides a high bandwidth 50 controlled impedance environment and is implemented in four layers The first layer or primary trace layer is 0 008 thick Rogers RO4003 material and is designed to have equal electrical length on all signal traces from the device under test DUT pins to the SMA connectors The second layer is the 1 0 oz copper ground pla
3. arranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use
4. ecommended enabling the 50 Q internal impedance in the oscilloscope or other measuring instrument to be used as an ECL output load termination By offsetting Voc 2 0 V SMAGND Vcc 2 0 V SMAGND is the system ground OV Vcc is 2 0 V and VEE DUTGND is 3 0 V 1 3 V or 0 5 V see Table 2 Power Supply Levels CML Outputs Likewise CML outputs need to be terminated to Vcc via a 50 Q resistor If no internal resistors are provided on the http onsemi com 3 QFN16EVB device 0402 chip resistor pads are provided on the bottom side of the evaluation board to terminate the CML driver If internal resistors are provided the Vr pins should be wired to Vcc For CML lab setup and test operation with negative supply voltages is recommended to enable the 50 Q internal impedance in the oscilloscope or other measuring instrument to be used as a CML output termination Vcc 0 V SMAGND 0 V and Vgg DUTGND 5 0 V 3 3 V 2 5 V or 1 8 V LVDS Outputs LVDS outputs are typically terminated with 100 Q across the Q Q output pair The 100 Q can be added on the QFN16EVB but it is not provided on the board since there are several user dependent LVDS output measurement techniques For LVDS lab setup and test a single supply is typically used ie Vcc 3 3 V and DUTGND 0 V Installing the SMA Connectors Each configuration indicates the number of SMA connectors needed to populate an evaluation board for a given device
5. even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT N American Technical Support 800 282 9855 Toll Free ON Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 5163 Denver Colorado 80217 USA Europe Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421 33 790 2910 Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Japan Customer Focus Center Email orderlit onsemi com Phone 81 3 5773 3850 For additional information please contact your local Sales Representative QFN16EVB D
6. n Board Assembly Instructions The QFN 16 evaluation board is designed for characterizing devices in a 50 Q laboratory environment using high bandwidth equipment Each signal trace on the board has a via at the DUT pin which provides an option of placing a termination resistor on the board bottom depending on the input output configuration see Table 1 Example Configuration List Table 6 contains the Bill of Materials for this evaluation board The QFN16EVB was designed to accommodate a custom QFN 16 socket Therefore some external components are installed on the bottom side of the board Solder the Device on the Evaluation Board The soldering of a device to the evaluation board can be accomplished by hand soldering or solder reflow techniques using solder paste Make sure pin 1 of the device is located properly and all the pins are aligned to the footprint pads Solder the QFN 16 device to the evaluation board As mentioned earlier many QFN16EVBs are dedicated with a device already installed and can be ordered from onsemi com at the specific device web page Connecting Power and Ground On the top side of the evaluation board solder the four surface mount test point clips anvils to the pads labeled Vcc Veg DUTGND SMAGND and ExPad ExPad is connected to the exposed flag of the QFN package For proper operation the exposed flag is typically recommended to be tied to Vgp DUTGND the negative supply of the device The positive po
7. ne and is primarily dedicated for the SMA connector ground plane FR4 dielectric material is placed between the second and third layers and between third and fourth layers The third layer is also 1 0 oz copper plane A portion of this layer is designated for the device Vcc and DUTGND power planes The fourth layer is the secondary trace layer P N IMOOAB2 REV B Bottom View Figure 1 Top and Bottom View of the 16 QFN Evaluation Board Semiconductor Components Industries LLC 2007 November 2007 Rev 0 Publication Order Number QFN16EVB D QFN16EVB Pin 13 Pin 14 Pin 15 Pin 16 VEE DUTGND VCC SMA_GND YY yY y Pin 12 Pin 1 Pin 11 Pin 2 DUT_GND Pin 10 Pin 9 Pin 3 Pin 4 VV y y AA A A SMA_GND Pin 8 Pin 7 Pin 6 Pin 5 Figure 2 Enlarged Bottom View Figure 3 Enlarged Bottom View of the Evaluation Board SILKSCREEN TOP SIDE LAYER 1 TOP SIDE 1 OZ 7 Z ROGERS 4003 0 008in 7 77 LAYER 2 GROUND PLANE P1 1 OZ 7 7 aoon 777 0 062 0 007 LAYER 3 GROUND VCC amp VEE PLANE P2 1 OZ FR 40 025in Z f f LAYER 4 BOTTOM SIDE 1 OZ Figure 4 Evaluation Board Layout 4 Layer http onsemi com 2 QFN16EVB Top View Evaluatio
8. or Trigger Trigger 50 Q 1 Connect appropriate power supplies to Vcc VEE DUTGND SMA GND 2 Connect a signal generator to the input SMA connectors Setup input signal according to the device data sheet 3 Connect a test measurement device to the device output SMA connectors NOTE The test measurement device must contain 50 Q termination Figure 7 Lab Setup Table 2 POWER SUPPLY LEVELS http onsemi com 6 QFN16EVB Table 3 NB6xxxM CML OUTPUTS SPLIT POWER Dual Power Supplies SUPPLY CONFIGURATION Device Pin Power Supply Convertor Spilt Power Supply Vcc B Voc DUTGND DUTGND 2 5 V or 3 3 V SMAGND DUTGND 2 5 V Figure 8 Split or Dual Power Supply Connections Table 4 NB6xxx LVPECL OUTPUTS SPLIT Dual Power Supplies POWER SUPPLY CONFIGURATION Device Pin Power Supply Convertor Spilt Power Supply Wee DUTGND DUTGND DUTGND 0 5 V or 1 3 V SMAGND 3 3 V Figure 9 Split or Dual Power Supply Connections Table 5 NB6xxxS LVDS OUTPUTS SINGLE POWER Single Power Supplies SUPPLY CONFIGURATION Device Pin Power Supply Convertor Single Power Supply Voc Voc 3 83 V V DUTGND SMAGND DUTGND DUTGND 0V C 3 3 V Figure 10 Single Power Supply Connections http onsemi com 7 QFN16EVB Table 6 BILL OF Cesar Components Description Part Number Number Ku Connector IE E _ Connector Side Launch Mii E 40ME3 ht
9. tp a rosenberger de Gold Plated http www rosenbergerna com Surface Mount Keystone SMT Miniature Test Point 5015 http www keyelco com Test Point Peeves SMT Compact Test Point 5016 Chip Capacitor AVC Corporation 0603 0 01 uF 10 06035C103KAT2A http www avxcorp com 0603 0 1 uF 10 0603C104KAT2A Chip Resistor Panasonic 0402 50 Q 1 Precision n o 2RKF49R9X http www panasonic com Thick Film Chip Resistor Evaluation Board ON Semiconductor QFN 16 Evaluation Board ECLQFN16EVB http www onsemi com Device Samples ON Semiconductor QFN 16 Package Device http www onsemi com Components are available through most distributors i e www newark com www digikey com http onsemi com 8 QFN16EVB DUT _GHD SHA_GHO Second Layer SMA_GND Plane Figure 11 Gerber Files http onsemi com 9 QFN16EVB o mg a Tp we oe VEE i 6 dIa 12 o Ecr 07 05 N db SMA_GND i TE 9 si TRS TP4 7 a hag JE a j JB 4 d0 Third Layer DUT_GND Trace JH Semiconductor TEMPE AZ 85282 U S A a INT 1 E02 438 1112 ERI z FAX INT 1 602 431 9633 gt P N 1N00A82 21835 Bottom Layer Figure 12 Gerber Files http onsemi com 10 QFN16EVB ON Semiconductor and ON are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no w
10. wer supply connector is labeled Vcc Depending on the device the negative power supply nomenclature is labeled either GND or Vgr To help avoid confusion with the use of this board the negative supply Figure 5 Evaluation Board Layout TEMPE AZ ASSI Wh KT 1 fant 43A ti a FAK HT 1 B02 457 033 P N IMOGABIC21B35 REY Bottom View connector is labeled Vep DUTGND SMAGND is the ground for the SMA connectors and is not to be confused with the device ground Vgp DUTGND SMAGND and DUTGND can be connected in single supply applications The power pin layout and typical connection of the evaluation board is shown in Figure 6 It is recommended to add bypass capacitors to reduce unwanted noise from the power supplies Connect 0 1uF capacitors from Vcc and Vgg DUTGND to SMA GND Output Loading Termination ECL PECL LVPECL Outputs Most ECL outputs are open emitter and need to be DC loaded and AC terminated to Vcc 2 0 V via a 50 Q resistor If no internal resistors are provided on the device 0402 chip resistor pads are provided on the bottom side of the evaluation board to terminate the ECL driver Solder the chip resistors to the bottom side of the board between the appropriate input device pads and the ground pads If internal resistors are provided the VT pins should be wired to SMAGND More information on termination is provided in AND8020 For standard ECL lab setup and test a split dual power supply is r
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