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P89LPC932A1 8-bit microcontroller with accelerated two

1. 23 80 0 3Vpp 0 7Vpp 5 5 1 0 0 3 4 0 45 5 Unit mA mA mA mA uA uA mV us mV us lt lt lt lt lt lt lt V V pF uA uA NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 46 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core Table8 Static characteristics continued Vpp 2 4 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial applications unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit lr logical 1 to 0 transition current Vi lt 1 5VatVpp 36V BI 30 450 uA all ports Rnsr n internal pull up resistance on pin 10 30 kQ RST Vbo brownout trip voltage 2 4 V lt Vpp lt 3 6 V with 2 40 2 70 V BOV 1 BOPD 0 Vref bg band gap reference voltage 1 19 1 23 1 27 V TCpg band gap temperature 10 20 ppm C coefficient 1 Typical ratings are not guaranteed The values listed are at room temperature 3 V 2 The lpp oper Ipp die and Ipp pa specifications are measured using an external clock with the following functions disabled comparators real time clock and watchdog timer 3 The Ipp tpay Specification is measured using an external clock with the following functions disabled comparators real time clock brownout detect and watchdog timer 4 See Section 8 Limiting values on page 45 for steady
2. If double buffering is disabled TB8 can be written before or after SBUF is written as long as TB8 is updated some time before that bit is shifted out TB8 must not be changed until the bit is shifted out as indicated by the Tx interrupt If double buffering is enabled TB8 must be updated before SBUF is written as TB8 will be double buffered together with SBUF data NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 32 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core 7 21 I C bus serial interface The I C bus uses two wires SDA and SCL to transfer information between devices connected to the bus and it has the following features Bidirectional data transfer between masters and slaves Multi master bus no central master Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer s The I2C bus may be used for test and diagnostic purposes A typical I C bus configuration is shown in Figure 14 The P89LPC932A1 device provides a byte oriented I2C bus interface that supports data transfers up to 400 kHz Rp om fp SCL P1 3 SDA P1 2 SCL
3. 2 L U E 0 P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core 8 kB 3 V byte erasable flash with 512 byte data EEPROM Rev 03 12 March 2007 Product data sheet 1 General description 2 Features 2 1 2 2 The P89LPC932A1 is a single chip microcontroller available in low cost packages based on a high performance processor architecture that executes instructions in two to four clocks six times the rate of standard 80C51 devices Many system level functions have been incorporated into the P89LPC932A1 in order to reduce component count board space and system cost Principal features 8 kB byte erasable flash code memory organized into 1 kB sectors and 64 byte pages Single byte erasing allows any byte s to be used as non volatile data storage 256 byte RAM data memory 512 byte auxiliary on chip RAM 512 byte customer data EEPROM on chip allows serialization of devices storage of set up parameters etc Two analog comparators with selectable inputs and reference source Two 16 bit counter timers each may be configured to toggle a port output upon timer overflow or to become a PWM output and a 23 bit system timer that can also be used as a RTC Enhanced UART with fractional baud rate generator break detect framing error detection and automatic address detection 400 kHz byte wide I C bus communication port and SPI communication port CCU prov
4. All pins have Schmitt trigger inputs Port 3 also provides various special functions as described below P3 0 Port 3 bit 0 XTAL2 Output from the oscillator amplifier when a crystal oscillator option is selected via the flash configuration CLKOUT CPU clock divided by 2 when enabled via SFR bit ENCLK TRIM 6 It can be used if the CPU clock is the internal RC oscillator watchdog oscillator or external clock input except when XTAL1 XTAL2 are used to generate clock source for the RTC system timer P3 1 Port 3 bit 1 XTAL1 Input to the oscillator circuit and internal clock generator circuits when selected via the flash configuration It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source and if XTAL1 XTAL2 are not used to generate the clock for the RTC system timer Ground 0 V reference Power supply This is the power supply voltage for normal operation as well as Idle and Power down modes 1 Input Output for P1 0 to P1 4 P1 6 P1 7 Input for P1 5 P89LPC932A1_3 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 10 of 64 P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core NXP Semiconductors 7 Functional description Remark Please refer to the P89LPC932A1 User manual for a more detailed functional description 7 1 Special function registers Remark Special Function Regis
5. N MOV WFEED2 05AH 8 BIT DOWN 1 O 32 PRESCALER m COUNTER reset A A i wocon ie SS ener PRED J Tonos woroF woei feed sequence 1 Watchdog reset can also be caused by an invalid feed sequence or by writing to WDCON not immediately followed by a Fig 21 Watchdog timer in Watchdog mode WDTE 1 002aaa905 7 26 7 26 1 7 26 2 P89LPC932A1_3 Additional features Software reset The SRST bit in AUXR1 gives software the opportunity to reset the processor completely as if an external reset or watchdog reset had occurred Care should be taken when writing to AUXR1 to avoid accidental software resets Dual data pointers The dual Data Pointers DPTR provides two different Data Pointers to specify the address used with certain instructions The DPS bit in the AUXR1 register selects one of the two Data Pointers Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may be toggled thereby switching Data Pointers simply by incrementing the AUXR1 register without the possibility of inadvertently altering other bits in the register NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 40 of 64 NXP Semiconductors P89LPC932A1 7 27 7 28 7 28 1 7 28 2 P89LPC932A1_3 8 bit microcontroller with accelerated two clock 80C51 core Data EEPROM The P89LPC932A1 has 512 B of on chip data EEPROM The data EEPROM
6. Rev 03 12 March 2007 42 of 64 NXP Semiconductors P89LPC932A1 7 28 8 7 28 9 7 28 10 P89LPC932A1 3 8 bit microcontroller with accelerated two clock 80C51 core In addition IAP operations can be accomplished through the use of four SFRs consisting of a control status register a data register and two address registers Additional details may be found in the P89LPC932A1 User manual In system programming ISP is performed without removing the microcontroller from the system The ISP facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89LPC932A1 through the serial port This firmware is provided by NXP and embedded within each P89LPC932A1 device The ISP facility has made ISP in an embedded application possible with a minimum of additional expense in components and circuit board area The ISP function uses five pins Vpp Vss TXD RXD and RST Only a small connector needs to be available to interface your application to an external circuit in order to use this feature Power on reset code execution The P89LPC932A1 contains two special flash elements the Boot Vector and the Boot Status Bit Following reset the P89LPC932A1 examines the contents of the Boot Status Bit If the Boot Status Bit is set to zero power up execution starts at location 0000H which is the normal start address of the user s application code When the Boot Status Bit is
7. 2 4 V to 3 6 V unless otherwise specified Tamp 40 C to 85 C for industrial applications unless otherwise specified 112 Symbol Parameter Conditions Variable clock fosc 12 MHz Unit Min Max Min Max tsPILAG SPI enable lag time see Figure 26 27 2 0 MHz slave 250 P 250 S ns tsPICLKH SPICLK HIGH time see Figure 24 25 master 26 27 2 CCLK 165 ns slave 3CCLK 250 ns tsPICLKL SPICLK LOW time see Figure 24 25 master 26 27 2 CCLK 165 ns slave 3CCLK 250 ns tspipsu SPI data set up time master or see Figure 24 25 100 100 ns slave 26 27 tsPIDH SPI data hold time master or see Figure 24 25 100 100 ns slave 26 27 tspia SPI access time slave see Figure 26 27 0 120 0 120 ns tspipis SPI disable time slave see Figure 26 27 0 240 240 ns tspipv SPI enable to output data valid see Figure 24 25 time 26 27 2 0 MHz 240 240 ns 3 0 MHz 167 167 ns SPIOH SPI output data hold time see Figure 24 25 0 0 ns 26 27 tspiR SPI rise time see Figure 24 25 SPI outputs 26 27 lt 100 100 ns SPICLK MOSI MISO SPI inputs p 2000 2000 ns SPICLK MOSI MISO SS tspiF SPI fall time see Figure 24 25 SPI outputs 26 27 100 100 ns SPICLK MOSI MISO SPI inputs 2000 2000 ns SPICLK MOSI MISO SS 1 Parts are tested to 2 MHz but are guaranteed to operate down to 0 Hz 2 Parameters are valid over operating temperature range unless otherwise specified P
8. 4 TRIM 3 TRIM 2 TRIM 1 TRIM O 51 4 Watchdog control register A7H PRE2 PRE1 PREO S S WDRUN WDTOF WDCLK 6 4 Watchdog load C1H FF 1111 1111 Watchdog feed 1 C2H Watchdog feed 2 C3H 1 BRGR1 and BRGRO must only be written if BRGEN in BRGCON SFR is logic 0 If any are written while BRGEN 1 the result is unpredictable 2 All ports are in input only high impedance state after power up 3 The RSTSRC register reflects the cause of the P89LPC932A1 reset Upon a power up reset all reset source flags are cleared except POF and BOF the power on reset value is xx11 0000 4 The only reset source that affects these SFRs is power on reset 5 On power on reset the TRIM SFR is initialized with a factory preprogrammed value Other resets will not cause initialization of the TRIM register 6 After reset the value is 1110 01x1 i e PRE2 to PREO are all logic 1 WORUN 1 and WDCLK 1 WDTOF bit is logic 1 after watchdog reset and is logic 0 after power on reset Other resets will not affect WDTOF 9109 16209 490 9 OM p918J9 929 YIM 19 011u020J91UI 1q 8 LVc amp 60d 168d SIOJONPUODIWIIBS dXN NXP Semiconductors P89LPC932A1 7 2 7 3 7 3 1 7 3 2 7 3 3 7 3 4 7 3 5 7 3 6 P89LPC932A1_3 8 bit microcontroller with accelerated two clock 80C51 core Enhanced CPU The P89LPC932A1 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices A machine cycle consists of
9. C control ECH register Capture compare D control EDH register Comparator 1 control register ACH Comparator 2 control register ADH Data EEPROM control F1H register Data EEPROM data register F2H Data EEPROM address F3H register CPU clock divide by M 95H control Data pointer 2 bytes Data pointer high 83H Data pointer low 82H 12C slave address register DBH Bit address 12C control register D8H Bit functions and addresses Reset value MSB LSB Hey Binary E7 E6 E5 E4 E3 E2 E1 EO 00 0000 0000 CLKLP EBRR ENT1 ENTO SRST 0 DPS 00 0000 00x0 F7 F6 F5 F4 F3 F2 F1 FO 00 0000 0000 ool 0000 0000 ool 0000 0000 SBRGS BRGEN lool xxx xx00 ICECA2 ICECA1 ICECAO ICESA ICNFA FCOA OCMA1 OCMAO 00 0000 0000 ICECB2 ICECB1 ICECBO ICESB ICNFB FCOB OCMB1 OCMBO 00 0000 0000 FCOC OCMC1 OCMCO 00 xxxx x000 FCOD OCMD1 OCMDO 00 xxxx x000 CE1 CP1 CN1 OE1 CO1 CMF1 0012 xx00 0000 CE2 CP2 CN2 OE2 CO2 CMF2 o0 xx00 0000 EEIF HVERR ECTL1 ECTLO EADR8 0E 0000 1110 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 I2ADR 6 I2ADR 5 I2ADR 4 I2ADR 3 I2ADR 2 I2ADR 1 I2ADR 0O GC 00 0000 0000 DF DE DD DC DB DA D9 D8 I2EN STA STO SI AA CRSEL 00 x000 00x0 9109 16209 490 9 OM p91819 929 YIM 19 011U020J91UI 1Iq 9 LVc amp 60d 168d SIOJONPUODIWIS dXN Jays Lep 19npoud 2002 421e ZL 0 ed 9 J0 CL LW2E6Od 168d peAJese
10. Hex Binary 00 0000 0000 00 0000 0000 F8 1111 1000 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 oo 00x0 0000 ool x000 0000 ool x000 0000 ool2 00x0 0000 ool 00x0 0000 O0l2 xxxx xx00 00 0000 0000 FF 1111 1111 00 0000 0000 00 0000 0000 9109 16209 490 9 OM p918J9 929 YIM 19 0J1u020J91UI 1Iq 9 LVc amp 60d 168d SIOJONPUODIWIS dXN Jays Lep 19npoud 2002 421e ZL 0 eH 9 40 HL LW2E6Od 168d peAJese SIUDU IY 002 8 dXN Table3 Special function registers continued indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr wsp LSB Hex Binary OCRBH Output compare B register FBH 00 0000 0000 high OCRBL Output compare B register FAH 00 0000 0000 low OCRCH Output compare C register FDH 00 0000 0000 high OCRCL Output compare C register FCH 00 0000 0000 low OCRDH Output compare D register FFH 00 0000 0000 high OCRDL Output compare D register FEH 00 0000 0000 low Bit address 87 86 85 84 83 82 81 80 PO Port 0 80H T1 KB7 CMP1 CMPREF CINTA CIN1B CIN2A CIN2B CMP2 2 KB6 KB5 KB4 KB3 KB2 KB1 KBO Bit address 97 96 95 94 93 92 91 90 P1 Port 1 90H OCC OCB RST INT1 INTO TO SCL RXD TXD 2 SDA Bit address 97 96 95 94 93 92 91 90 P2 Port 2 AOH ICA OCA SPICLK SS MISO MOSI OCD ICB 2 Bit address B7 B6 B5 B4 B3 B2 B1 BO P3 Port 3 BOH XTAL1 XTAL2 2 POM1 Port 0 outp
11. P0 3 Port 0 bit 3 KBI3 P89LPC932A1_3 CIN1B Comparator 1 positive input B KBI3 Keyboard input 3 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 7 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core Table 2 Pin description continued Symbol Pin Type Description TSSOP28 HVQFN28 PLCC28 DIP28 PO 4 CINTA 23 19 lO P0 4 Port O bit 4 KBI4 l CIN1A Comparator 1 positive input A l KBI4 Keyboard input 4 P0 5 22 18 lO P0 5 Port O bit 5 iE l CMPREF Comparator reference negative input l KBI5 Keyboard input 5 P0 6 CMP1 20 16 lO P0 6 Port 0 bit 6 KBI6 O CMP1 Comparator 1 output l KBI6 Keyboard input 6 PO 7 T1 KBI7 19 15 lO P0 7 Port O bit 7 lO T1 Timer counter 1 external count input or overflow output l KBI7 Keyboard input 7 P1 0 to P1 7 l O Port 1 Port 1 is an 8 bit I O port with a user configurable output type Lu except for three pins as noted below During reset Port 1 latches are configured in the input only mode with the internal pull up disabled The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected Each of the configurable port pins are programmed independently Refer to Section 7 13 1 Port configurations and Table 8 Static characteristics for details P1 2 and P1 3 are open dr
12. carrier 28 leads SOT261 2 Aa dis detail X scale DIMENSIONS mm dimensions are derived from the original inch dimensions A A 1 Ag 4 b max p by D D ED e ep eg Hp UNIT A 11 58 11 58 11 43 11 43 0 456 0 456 0 450 0 450 3 05 inches 0 j lj 0 12 Note 1 Plastic or metal protrusions of 0 25 mm 0 01 inch maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC JEITA PROJECTION SOT261 2 112E08 MS 018 EDR 7319 E ie p ISSUE DATE Fig 29 Package outline SOT261 2 PLCC28 P89LPC932A1 3 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 56 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core TSSOP28 plastic thin shrink small outline package 28 leads body width 4 4 mm SOT361 1 a L detail X DIMENSIONS mm are the original dimensions UNIT A1 A2 A3 bp c D E mm
13. is SFR based byte readable byte writable and erasable via row fill and sector fill The user can read write and fill the memory via SFRs and one interrupt This data EEPROM provides 400000 minimum erase program cycles for each byte Byte mode In this mode data can be read and written one byte at a time Row fill In this mode the addressed row 64 bytes is filled with a single value The entire row can be erased by writing OOH Sector fill In this mode all 512 bytes are filled with a single value The entire sector can be erased by writing OOH After the operation finishes the hardware will set the EEIF bit which if enabled will generate an interrupt The flag is cleared by software Flash program memory General description The P89LPC932A1 flash memory provides in circuit electrical erasure and programming The flash can be erased read and written as bytes The Sector and Page Erase functions can erase any flash sector 1 kB or page 64 bytes The Chip Erase operation will erase the entire program memory ICP using standard commercial programmers is available In addition IAP and byte erase allows code memory to be used for non volatile data storage On chip erase and write timing generation contribute to a user friendly programming interface The P89LPC932A1 flash reliably stores memory contents even after 400000 erase and program cycles The cell is designed to optimize the erase and programming mechanisms The P8
14. mode voltage comparators powered down IDD tpa total Power down mode supply current dV dt rise rate dV dt X fall rate VppR data retention voltage Vth HL HIGH LOW threshold voltage Vit LOW level input voltage Vih LH LOW HIGH threshold voltage Vin HIGH level input voltage Vhys hysteresis voltage VoL LOW level output voltage Vou HIGH level output voltage Vxtal voltage on XTAL1 XTAL2 pins Va voltage on any pin except XTAL1 XTAL2 Vpp Ciss input capacitance lit logical 0 input current lii input leakage current P89LPC932A1 3 Conditions Vpp 3 6 V fos 12 MHz Vpp 3 6 V fose 18 MHz Vpp 3 6 V fos 12 MHz Vpp 3 6 V fos 18 MHz Von 3 6 V Vpop 3 6 V of Vpp of Vpp except SCL SDA SCL SDA only except SCL SDA SCL SDA only Port 1 lo 20 mA Vpp 2 4 V to 3 6 V all ports all modes except high Z lot 3 2 mA Vpp 2 4 V to 3 6 V all ports all modes except high Z lon 20 pA Vpp 2 4 V to 3 6 V all ports quasi bidirectional mode lou 3 2 mA Vpp 2 4 V to 3 6 V all ports push pull mode with respect to Vss with respect to Vss Vi 2 0 4 V Vi Vi Vig OF Viu 2 2 2 3 4 4 5I 6 Ul 8 Min 1 5 0 22Vpp 0 5 0 7Vpp Vpp 0 3 Vbo 0 7 0 5 0 5 Typi 11 3 25 55 0 5 0 4Vpp 0 6Vpp 0 2Vpp 0 6 0 2 Vpop 0 2 Vnan od Max 18
15. of different configurations Comparator operation is such that the output is a logic 1 which may be read in a register and or routed to a pin when the positive input one of two selectable pins is greater than the negative input selectable from a pin or an internal reference voltage Otherwise the output is a zero Each comparator may be configured to cause an interrupt when the output value changes The overall connections to both comparators are shown in Figure 20 The comparators function to Vpp 2 4 V When each comparator is first enabled the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds The corresponding comparator interrupt should not be enabled during that time and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service CP1 P0 4 CINTA comparator 1 xi P0 3 CIN1B CMP 1 P0 6 P0 5 CMPREF Vref bg E CNI gt interrupt change detect CP2 EC P0 2 CIN2A comparator 2 P0 1 CIN2BB 4 4 ius D o7 CMP2 P0 0 I CO2 OE2 CN2 002aaa904 Fig 20 Comparator input and output connections 7 23 1 7 23 2 P89LPC932A1 3 Internal reference voltage An internal reference voltage generator may supply a default reference when a single comparator input pin is used The value of the internal reference voltage referred to as VREF is 1 23 V 10 Comparator inte
16. power consumption further On any reset CLKLP is logic 0 allowing highest performance access This bit can then be set in software if CCLK is running at 8 MHz or slower Memory organization The various P89LPC932A1 memory spaces are as follows DATA 128 bytes of internal data memory space 00H 7FH accessed via direct or indirect addressing using instructions other than MOVX and MOVC All or part of the Stack may be in this area DATA Indirect Data 256 bytes of internal data memory space 00H FFH accessed via indirect addressing using instructions other than MOVX and MOVC All or part of the Stack may be in this area This area includes the DATA area and the 128 bytes immediately above it SFR Special Function Registers Selected CPU registers and peripheral control and status registers accessible only via direct addressing XDATA External Data or Auxiliary RAM Duplicates the classic 80C51 64 kB memory space addressed via the MOVX instruction using the SPTR RO or R1 All or part of this space could be implemented on chip The P89LPC932A1 has 512 bytes of on chip XDATA memory NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 19 of 64 NXP Semiconductors P89LPC932A1 7 11 7 12 7 12 1 P89LPC932A1 3 8 bit microcontroller with accelerated two clock 80C51 core CODE 64 kB of Code memory space accessed as part of program execution and via the MOVC instruc
17. speed oscillator option This option supports an external crystal in the range of 100 kHz to 4 MHz Ceramic resonators are also supported in this configuration High speed oscillator option This option supports an external crystal in the range of 4 MHz to 18 MHz Ceramic resonators are also supported in this configuration Clock output The P89LPC932A1 supports a user selectable clock output function on the XTAL2 CLKOUT pin when crystal oscillator is not being used This condition occurs if another clock source has been selected on chip RC oscillator watchdog oscillator external clock input on X1 and if the RTC is not using the crystal oscillator as its clock source This allows external devices to synchronize to the P89LPC932A1 This output is enabled by the ENCLK bit in the TRIM register NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 17 of 64 NXP Semiconductors P89LPC932A1 P89LPC932A1 3 7 4 7 5 7 6 8 bit microcontroller with accelerated two clock 80C51 core The frequency of this clock output is that of the CCLK If the clock output is not needed in Idle mode it may be turned off prior to entering Idle saving additional power On chip RC oscillator option The P89LPC932A1 has a 6 bit TRIM register that can be used to tune the frequency of the RC oscillator During reset the TRIM value is initialized to a factory preprogrammed value to adjust the oscillator frequency
18. this pin is output when configured as slave this pin is input P2 3 MISO 14 10 lO P2 3 Port 2 bit 3 lO MISO When configured as master this pin is input when configured as slave this pin is output P2 4 SS 15 11 lO P2 4 Port 2 bit 4 SS SPI Slave select P2 5 SPICLK 16 12 lO P2 5 Port 2 bit 5 lO SPICLK SPI clock When configured as master this pin is output when configured as slave this pin is input P2 6 0CA 27 23 lO P2 6 Port 2 bit 6 O OCA Output Compare A P89LPC932A1_3 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 9 of 64 NXP Semiconductors P89LPC932A1 Table 2 Pin description continued 8 bit microcontroller with accelerated two clock 80C51 core Symbol P2 7 ICA P3 0 to P3 1 P3 0 XTAL2 CLKOUT P3 1 XTAL1 Vss Vpp Pin TSSOP28 HVQFN28 PLCC28 DIP28 28 24 9 5 8 4 7 3 21 17 Type Description 1 0 UO UO UO P2 7 Port 2 bit 7 ICA Input Capture A Port 3 Port 3 is a 2 bit I O port with a user configurable output type During reset Port 3 latches are configured in the input only mode with the internal pull up disabled The operation of Port 3 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 7 13 1 Port configurations and Table 8 Static characteristics for details
19. to 7 373 MHz 1 at room temperature End user applications can write to the TRIM register to adjust the on chip RC oscillator to other frequencies Watchdog oscillator option The watchdog has a separate oscillator which has a frequency of 400 kHz This oscillator can be used to save power when a high clock frequency is not needed External clock input option In this configuration the processor clock is derived from an external source driving the P3 1 XTAL1 pin The rate may be from 0 Hz up to 18 MHz The P3 0 XTAL2 pin may be used as a standard port pin or a clock output When using an oscillator frequency above 12 MHz the reset input function of P1 5 must be enabled An external circuit is required to hold the device in reset at power up until Vpp has reached its specified level When system power is removed Vpp will fall below the minimum specified operating voltage When using an oscillator frequency above 12 MHz in some applications an external brownout detect circuit may be required to hold the device in reset when Vpp falls below the minimum specified operating voltage XTAL1 HIGH FREQUENCY MEDIUM FREQUENCY RTC XTAL2 lt LOW FREQUENCY m OSCCLK CCLK Dive CPU RC RCCLK E OSCILLATOR 7 3728 MHz 1 PCLK WDT WATCHDOG OSCILLATOR 5 PCLK 400 kHz 20 BRE 32 x PLL CCU Mae T I C BUS UART P89LPC932A1 002aaa891 Fig 7 Block diagram of oscillator control NXP B V 200
20. two CPU clock cycles and most instructions execute in one or two machine cycles Clocks Clock definitions The P89LPC932A1 device has several internal clocks as defined below OSCCLK Input to the DIVM clock divider OSCCLK is selected from one of four clock sources see Figure 7 and can also be optionally divided to a slower frequency see Section 7 8 CCLK modification DIVM register Note fosc is defined as the OSCCLK frequency CCLK CPU clock output of the clock divider There are two CCLK cycles per machine cycle and most instructions are executed in one to two machine cycles two or four CCLK cycles RCCLK The internal 7 373 MHz RC oscillator output PCLK Clock for the various peripheral devices and is CCLK CPU clock OSCCLK The P89LPC932A1 provides several user selectable oscillator options in generating the CPU clock This allows optimization for a range of needs from high precision to lowest possible cost These options are configured when the flash is programmed and include an on chip watchdog oscillator an on chip RC oscillator an oscillator using an external crystal or an external clock source The crystal oscillator can be optimized for low medium or high frequency crystals covering a range from 20 kHz to 18 MHz Low speed oscillator option This option supports an external crystal in the range of 20 kHz to 100 kHz Ceramic resonators are also supported in this configuration Medium
21. 0 15 0 95 0 30 02 9 8 45 0 05 0 80 0 19 0 1 9 6 4 3 Notes 1 Plastic or metal protrusions of 0 15 mm maximum per side are not included 2 Plastic interlead protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC JEITA PROJECTION SOT361 1 MO 153 E dee S ISSUE DATE Fig 30 Package outline SOT361 1 TSSOP28 P89LPC932A1 3 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 57 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core HVQFN28 plastic thermal enhanced very thin quad flat package no leads 28 terminals body 6 x 6 x 0 85 mm SOT788 1 terminal 1 4 index area i A A detail X terminal 1 index area 28 Dh DIMENSIONS mm are the original dimensions A0 UNIT max A1 b c DU Dh E En mm 4 005 035 go 61 4 25 61 425 0 00 0 25 5 9 3 95 59 3 95 Note 1 Plastic or metal protrusions of 0 075 mm maximum per side are not included OUTLINE REFERE
22. 00 PLEEN HLTRN HLTEN ALTCD ALTAB TDIR2 TMOD21 TMOD20 00 0000 0000 TCOU2 PLLDV 3 PLLDV 2 PLLDV 1 PLLDV O 00 Oxxx 0000 00 0000 0000 00 0000 0000 00 0000 0000 TOIE2 TOCIE2D TOCIE2C TOCIE2B TOCIE2A TICIE2B TICIE2A 00 0000 0x00 TOIF2 TOCF2D TOCF2C TOCF2B TOCF2A TICF2B TICF2A 00 0000 0x00 9109 16209 490 9 OM p918J9 929 YIM 19 0J1u020J91UI 1Iq 9 LVc amp 60d 168d SIOJONPUODIWIBS dXN 1394S Lep 19npoJd 2002 421e ZL 0 AY v9 Jo OL IVe 6Od 68d peAJesei SIUDU IY 2002 8 dXN Table 3 Special function registers continued indicates SFRs that are bit addressable Name TISE2 TLO TL1 TL2 TMOD TOR2H TOR2L TPCR2H TPCR2L TRIM WDCON WDL WFEED1 WFEED2 Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary CCU interrupt status encode DEH lt z c ENCINT ENCINT ENCINT 00 Xxxx x000 register 2 1 0 Timer 0 low 8AH 00 0000 0000 Timer 1 low 8BH 00 0000 0000 CCU timer low CCH 00 0000 0000 Timer 0 and 1 mode 89H T4GATE T1C T T1M1 T1MO TOGATE TOC T TOM1 TOMO 00 0000 0000 CCU reload register high CFH 00 0000 0000 CCU reload register low CEH 00 0000 0000 Prescaler control register CBH TPCR2H TPCR2H 00 XXXX xx00 high 1 0 Prescaler control register low CAH TPCR2L TPCR2L TPCR2L TPCR2L TPCR2L TPCR2L TPCR2L TPCR2L 00 0000 0000 7 6 5 4 3 2 1 0 Internal oscillator trim register 96H RCCLK ENCLK TRIM 5 TRIM
23. 03 12 March 2007 27 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core 7 19 6 PWM operation P89LPC932A1_3 PWM operation has two main modes symmetrical and asymmetrical In asymmetrical PWM operation the CCU Timer operates in down counting mode regardless of the direction control bit In symmetrical mode the timer counts up down alternately The main difference from basic timer operation is the operation of the compare module which in PWM mode is used for PWM waveform generation As with basic timer operation when the PWM compare pins are connected to the compare logic their logic state remains unchanged However since bit FCO is used to hold the halt value only a compare event can change the state of the pin TOR2 compare value timer value 0x0000 non inverted inverted 002aaa893 Fig 9 Asymmetrical PWM down counting TOR2 compare value timer value 0 non inverted inverted 002aaa894 Fig 10 Symmetrical PWM NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 28 of 64 NXP Semiconductors P89LPC932A1 7 19 7 7 19 8 P89LPC932A1 3 8 bit microcontroller with accelerated two clock 80C51 core Alternating output mode In asymmetrical mode the user can set up PWM channels A B and C D as alterna
24. 26 27 tePipH SPI data hold time master or see Figure 24 100 100 ns slave 25 26 27 tsPIA SPI access time slave see Figure 26 27 0 80 0 80 ns tspipis SPI disable time slave see Figure 26 27 0 160 160 ns tspipv SPI enable to output data valid see Figure 24 time 25 26 27 2 0 MHz 160 160 ns 3 0 MHz 111 111 ns tePioH SPI output data hold time see Figure 24 0 0 ns 25 26 27 tspiR SPI rise time see Figure 24 SPI outputs 25 26 27 100 100 ns SPICLK MOSI MISO SPI inputs E 2000 2000 ns SPICLK MOSI MISO SS tspiF SPI fall time see Figure 24 SPI outputs 25 26 27 100 100 ns SPICLK MOSI MISO SPI inputs 2000 2000 ns SPICLK MOSI MISO SS 1 Parts are tested to 2 MHz but are guaranteed to operate down to 0 Hz 2 Parameters are valid over operating temperature range unless otherwise specified P89LPC932A1 3 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 51 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core 10 1 Waveforms I TxLXL gt l output data write to SBUF a txHDx txHDV gt set TI PUM QU CX Ka XeoX eX Ka KX gt clear RI i set RI 002aaa906 Fig 22 Shift register mode timing Vpp 0 5 V 0 2Vpp 0 9 V 0 2Vpp 0 1 V 0 45 V DO tCHCL tcLex Tey clk 002aaa907 Fig 23 Extern
25. 32A1 3 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 4 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core 5 Functional diagram 6 Pinning information P89LPC932A1_3 VoD Vss KBIO CMP2 lt gt gt TXD KBI1 CIN2B gt RXD KBI2 gt CIN2A gt T0 SCL KBI3 CIN1B gt lt lt INTO SDA sped CINA c FORT 0 NO PORT irj KBI5 CMPREF gt RST KBI6 gt CMP1 aK lt gt OCB KB Tics gt P89LPC932A1 R OLE CLKOUT 4 XTAL2 pan ICB PORT 3 4 gt OCD XTAL1 K LE AK MOSI ana l pontra nd MiSo gt 4 55 gt lt gt SPICLK lt gt OCA 4 ICA 002aaa890 Fig 2 Functional diagram of P89LPC932A1 6 1 Pinning P2 0 ICB P2 7 ICA P2 1 OCD C P2 6 OCA P0 0 CMP2 KBIO P0 1 CIN2B KBI1 P1 7 0CC P0 2 CIN2A KBI2 P1 6 0CB P0 3 CIN1B KBI3 P1 5 RST PO 4 CIN1A KBI4 Vss P0 5 CMPREF KBI5 P89LPC932A1FDH P3 1 XTAL1 VDD P3 0 XTAL2 CLKOUT P0 6 CMP1 KBI6 P1 4 INT1 P0 7 T1 KBI7 P1 3 INTO SDA P1 0 TXD P1 2 TO SCL P1 1 RXD P2 2 MOSI P2 5 SPICLK P2 3 MISO P2 4 SS 002aaa886 Fig 3 P89LPC932A1 TSSOP28 pin configuration NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 5 of 64 N
26. 7 All rights reserved Product data sheet Rev 03 12 March 2007 18 of 64 NXP Semiconductors P89LPC932A1 7 7 7 8 7 9 7 10 P89LPC932A1_3 8 bit microcontroller with accelerated two clock 80C51 core CCLK wake up delay The P89LPC932A1 has an internal wake up timer that delays the clock until it stabilizes depending on the clock source used If the clock source is any of the three crystal selections low medium and high frequencies the delay is 992 OSCCLK cycles plus 60 us to 100 us If the clock source is either the internal RC oscillator watchdog oscillator or external clock the delay is 224 OSCCLK cycles plus 60 us to 100 us CCLK modification DIVM register The OSCCLK frequency can be divided down up to 510 times by configuring a dividing register DIVM to generate CCLK This feature makes it possible to temporarily run the CPU at a lower rate reducing power consumption By dividing the clock the CPU can retain the ability to respond to events that would not exit Idle mode by executing its normal program at a lower rate This can also allow bypassing the oscillator start up time in cases where Power down mode would otherwise be used The value of DIVM may be changed by the program at any time without interrupting code execution Low power select The P89LPC932A1 is designed to run at 12 MHz CCLK maximum However if CCLK is 8 MHz or slower the CLKLP SFR bit AUXR1 7 can be set to logic 1 to lower the
27. 89LPC932A1 3 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 49 of 64 NXP Semiconductors P89LPC932A1 Table 10 Dynamic characteristics 18 MHz Vpp 3 0 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial applications unless otherwise specified J 8 bit microcontroller with accelerated two clock 80C51 core Symbol fosc Ro fosc wD fosc Tey CLK foLKLP Glitch filter lor tsa Parameter internal RC oscillator frequency internal watchdog oscillator frequency oscillator frequency clock cycle time low power select clock frequency glitch rejection signal acceptance External clock tcHcx tcLcx tci cH tcHCL clock HIGH time clock LOW time clock rise time clock fall time Shift register UART mode 0 tXLXL tavxH txHax txHDx XHDV serial port clock cycle time output data set up to clock rising edge time output data hold after clock rising edge time input data hold after clock rising edge time input data valid to clock rising edge time SPI interface spi Tspicyc tsPILEAD tsPILAG P89LPC932A1_3 SPI operating frequency slave master SPI cycle time slave master SPI enable lead time 2 0 MHz slave SPI enable lag time 2 0 MHz slave Conditions see Figure 23 P1 5 RST pin any pin except P1 5 RST P1 5 RST pin any pin except P1 5 RST see Figure 23 see Figu
28. 9LPC932A1 uses Vpp as the supply voltage to perform the Program Erase algorithms Features Programming and erase over the full operating voltage range Byte erase allows code memory to be used for data storage Read Programming Erase using ISP IAP ICP e Internal fixed boot ROM containing low level IAP routines available to user code Default loader providing ISP via the serial port located in upper end of user program memory Boot vector allows user provided flash loader code to reside anywhere in the flash memory space providing flexibility to the user e Any flash program erase operation in 2 ms Programming with industry standard commercial programmers Programmable security for the code in the flash for each sector 400000 typical erase program cycles for each byte 20 year minimum data retention NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 41 of 64 NXP Semiconductors P89LPC932A1 7 28 3 7 28 4 7 28 5 7 28 6 7 28 7 P89LPC932A1 3 8 bit microcontroller with accelerated two clock 80C51 core Flash organization The program memory consists of eight 1 kB sectors on the P89LPC932A1 device Each sector can be further divided into 64 byte pages In addition to sector erase page erase and byte erase a 64 byte page register is included which allows from 1 byte to 64 bytes of a given page to be programmed at the same time substantially reducin
29. A B5H Bit address Program status word DOH Port 0 digital input disable F6H Reset source register DFH Real time clock control D1H Real time clock register high D2H Real time clock register low D3H Serial port address register A9H Serial port address enable B9H Serial Port data buffer 99H register Bit address Serial port control 98H Serial port extended status BAH register Stack pointer 81H SPI control register E2H SPI status register E1H SPI data register E3H Timer 0 and 1 auxiliary mode 8FH Bit address Timer 0 and 1 control 88H CCU control register 0 C8H CCU control register 1 F9H Timer 0 high 8CH Timer 1 high 8DH CCU timer high CDH CCU interrupt control register C9H CCU interrupt flag register E9H Bit functions and addresses Reset value MSB LSB Hey Binary RTCPD DEEPD VCPD I2PD SPPD SPD CCUPD 002 0000 0000 D7 D6 D5 D4 D3 D2 D1 DO CY AC FO RS1 RSO OV F1 P 00 0000 0000 PTOAD 5 PTOAD 4 PTOAD 3 PTOAD 2 PTOAD 1 00 xx00 000x BOF POF R_BK R_WD R_SF R_EX 3 RTCF RTCS1 RTCSO ERTC RTCEN 60824 011x xx0O ool 0000 0000 oo 0000 0000 00 0000 0000 00 0000 0000 XX XXXX XXXX 9F 9E 9D 9C 9B 9A 99 98 SMO FE SM1 SM2 REN TB8 RB8 TI RI 00 0000 0000 DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 0000 0000 07 0000 0111 SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPRO 04 0000 0100 SPIF WCOL 00 00xx xxxx 00 0000 0000 T1M2 S TOM2 00 Xxx0 xxxO 8F 8E 8D BC 8B 8A 89 88 TF1 TR1 TFO TRO IE1 IT1 IEO ITO 00 0000 00
30. D P2 6 0CA P0 0 CMP2 KBIO PO 1 CIN2B KBI1 P1 7 OCC P0 2 CIN2A KBI2 P1 6 OCB P0 3 CIN1B KBI3 P1 5 RST PO 4 CIN1A KBl4 Vss P0 5 CMPREF KBI5 RSE P89LPC932A1FN Von P3 0 XTAL2 CLKOUT P0 6 CMP1 KBI6 P1 4 INT1 P0 7 T1 KBI7 P1 3 INTO SDA P1 0 TXD P1 2 TO SCL P1 1 RXD P2 2 MOSI P2 5 SPICLK P2 3 MISO P2 4 SS 002aac785 Fig 6 P89LPC932A1 DIP28 pin configuration 6 2 Pin description Table 2 Pin description Symbol Pin Type Description TSSOP28 HVQFN28 PLCC28 DIP28 P0 0 to PO 7 lO Port 0 Port 0 is an 8 bit I O port with a user configurable output type During reset Port 0 latches are configured in the input only mode with the internal pull up disabled The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 7 13 1 Port configurations and Table 8 Static characteristics for details The Keypad Interrupt feature operates with Port 0 pins All pins have Schmitt trigger inputs Port 0 also provides various special functions as described below PO 0 CMP2 3 27 lO P0 0 Port 0 bit 0 KBIO O CMP2 Comparator 2 output l KBIO Keyboard input 0 PO 1 CIN2B 26 22 lO P0 1 Port bit 1 KBH l CIN2B Comparator 2 positive input B l KBI1 Keyboard input 1 P0 2 CIN2A 25 21 lO P0 2 Port 0 bit 2 KBI2 l CIN2A Comparator 2 positive input A l KBI2 Keyboard input 2 P0 3 CIN1B 24 20 lO
31. GISTER MOSI MOSI REGISTER SPI CLOCK 2 GENERATOR PORT SS J SPICLK SPICLK T 002aaa901 Fig 17 SPI single master single slave configuration master slave MISO 8 BIT SHIFT gt 8 BIT SHIFT REGISTER MS REGISTER SPI CLOCK zh SPI CLOCK GENERATOR SS GENERATOR SPICLK T 002aaa902 Fig 18 SPI dual device configuration where either can be a master or a slave P89LPC932A1_3 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 36 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core I master l slave I MISO MISO 8 BIT SHIFT N 8 BIT SHIFT REGISTER MOSI l MOSI REGISTER SPICLK SPICLK SPI CLOCK T pas GENERATOR port SS l 8 BIT SHIFT REGISTER SPICLK port 002aaa903 Fig 19 SPI single master multiple slaves configuration P89LPC932A1_3 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 37 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core 7 23 Analog comparators Two analog comparators are provided on the P89LPC932A1 Input and output options allow use of the comparators in a number
32. LEAD tsPIF E a tsPIR tsPILAG e gt tSPICLKL tSPICLKH SPICLK A N f N L N CPOL 0 input tSPIF I tsPIR tSPICLKL e a SPICLK SPICLKH CPOL 1 input N Y y N l tsPIA I tsPIOH tSPIOH tsPIOH tsPIDIS tsPIDV tsPIDv 74 y y MISO slave MSB LSB out X N slave LSB MSB out Khot defined output Z N LN ZN ja La a tspipsu tsPIDH tsPIDSU tsPIDSU tsPIDH NB GIA X X seem X input A MSB LSB in A A LSB MSB in AN 002aaa910 Fig 26 SPI slave timing CPHA 0 P89LPC932A1_3 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 53 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core a tsPIR e TsPICYC I tsPIR tSPILEAD tsPIF a tSPICLKH pa tSPICLKL j lt t aR SPIR tsPILAG SPICLK N N CPOL 0 input tsPIF La tsPIR tSPICLKL SPICLK tsPICLKH CPOL 1 input J N y tsPIOH tsPIOH tsPIDV tsPIDV gt tsPIDIS tSPIA gt nan not defined X slave MSB LSB out B MSB out p tsPIDSU tsPIDH isPipsU MOSI V N V V naut X sensein XX K 002aaa911 Fig 27 SPI slave timing CPHA 1 10 2 ISP entry mode Table 11 Dynamic characteristics ISP entry mode Vpp 2 4 V to 3 6 V unl
33. NCES EUROPEAN VERSION JEDEC JEITA PROJECTION SOT788 1 an MO 220 ig E 02 10 22 ISSUE DATE Fig 31 Package outline SOT788 1 HVQFN28 PB9LPC932A1 3 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 58 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core DIP28 plastic dual in line package 28 leads 600 mil SOT117 1 4 seating plane LT CL L pin 1 index LALJALJLJ CO L 0 5 gp coge aes yep scale DIMENSIONS mm dimensions are derived from the original inch dimensions A Ay A2 1 1 UNIT max mil b by c D E 1 7 36 14 1 a 9e 1 3 35 13 7 1 41 0 56 inches 0 2 0 02 1 34 0 54 Note 1 Plastic or metal protrusions of 0 25 mm 0 01 inch maximum per side are not included REFERENCES EUROPEAN OUTLINE PROJECTION VERSION IEC JEDEC JEITA SOT117 1 051G05 MO 015 SC 510 28 E 03 02 13 ISSUE DATE Fig 32 Package outline SOT117 1 DIP28 P89LPC932A1_3 Product data sheet Rev 03 12 March 2007 59 of 64 NXP B V 2007 All rights reserved NXP Semiconductors P89LPC932A1 13 Abbreviations P89LPC932A1_3 8 bit microcontroller with accelerated two clock 80C51 core Table 13 Acronym
34. OTHER DEVICE OTHER DEVICE WITH I C BUS WITH I2C BUS P89LPC932A1 IN TEEREACIS INTERFACE 002aaa898 Fig 14 I2C bus configuration P89LPC932A1_3 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 33 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core 8 Ny INPUT FILTER P1 3 SDA OUTPUT STAGE gt BIT COUNTER ARBITRATION lt CCLK 2 INPUT AND SYNC LOGIC TIMING a FILTER AND z CONTROL z P1 2 SCL SERIAL CLOCK LOGIC w OUTPUT interrupt z STAGE GENERATOR timer 1 T overflow P1 2 I2CON CONTROL REGISTERS AND I2SCLH SCL DUTY CYCLE REGISTERS I2SCLL STATUS status bus DECODER I2STAT STATUS REGISTER NY 002aaa899 Fig 15 I2C bus serial interface block diagram P89LPC932A1 3 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 34 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core 7 22 Serial Peripheral Interface SPI The P89LPC932A1 provides another high speed serial communication interface the SPI interface SPI is a full duplex high speed synchronous communication bus with two operation modes Master mode and Slave mode Up to 3 Mbit s can be supported in Master mode or up to 2 Mbit s in Slave mode It has a Transfer Completion Flag and Write Collision Flag Prote
35. SIUDU IY 2002 8 dXN Table3 Special function registers continued indicates SFRs that are bit addressable Bit functions and addresses Reset value Name Description SFR addr I2DAT 12C data register DAH I2SCLH Serial clock generator SCL DDH duty cycle register high I2SCLL Serial clock generator SCL DCH duty cycle register low I2STAT I2C status register D9H ICRAH Input capture A register high ABH ICRAL Input capture A register low AAH ICRBH Input capture B register high AFH ICRBL Input capture B register low AEH Bit address IENO Interrupt enable 0 A8H Bit address IEN1 Interrupt enable 1 E8H Bit address IPO Interrupt priority O B8H IPOH Interrupt priority 0 high B7H Bit address IP1 Interrupt priority 1 F8H IP1H Interrupt priority 1 high F7H KBCON Keypad control register 94H KBMASK Keypad interrupt mask 86H register KBPATN Keypad pattern register 93H OCRAH Output compare A register EFH high OCRAL Output compare A register EEH low MSB STA 4 STA 3 STA 2 AF AE AD EA EWDRT EBO EF EE ED EIEE EST BF BE BD E PWDRT PBO PWDRT PBOH H FF FE FD PIEE PST PIEEH PSTH STA 1 AC ES ESR EC ECCU BC PS PSR PSH PSRH FC PCCU PCCUH STA 0 AB ET EB ESPI BB PT1 PT1H FB PSPI PSPIH AA EX1 EA EC BA PX1 PX1H FA PC PCH A9 ETO E9 EKBI B9 PTO PTOH F9 PKBI PKBIH PATN _SEL LSB A8 EXO E8 EI2C B8 PXO PXOH F8 PI2C PI2CH KBIF
36. Tamb bias operating bias ambient temperature 55 125 C Tstg storage temperature range 65 150 C lon o HIGH level output current per I O pin 20 mA loLvo LOW level output current per I O pin 20 mA lyo to max maximum total I O current 100 mA Vn voltage on any pin except Vss with respect to Vpp 3 5 V Ptot pack total power dissipation per package based on package heat 1 5 W transfer not device power consumption 1 The following applies to Table 7 Limiting values a This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge Nonetheless it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum b Parameters are valid over operating temperature range unless otherwise specified All voltages are with respect to Vss unless otherwise noted P89LPC932A1_3 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 45 of 64 NXP Semiconductors P89LPC932A1 9 Static characteristics Table 8 Static characteristics 8 bit microcontroller with accelerated two clock 80C51 core Vpp 2 4 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial applications unless otherwise specified Symbol Parameter Ipo ope Operating supply current Ipp dle Idle mode supply current IDD pd power supply current Power down
37. XP Semiconductors P89LPC932A1 P89LPC932A1_3 8 bit microcontroller with accelerated two clock 80C51 core P2 0 ICB 28 P2 7 ICA 27 P2 6 OCA 3 PO 0 CMP2 KBIO 2 P2 1 OCD 26 P0 1 CIN2B KBI1 4 P1 7 OCC P1 6 OCB P1 5 RST 6 P3 1 XTAL1 8 P89LPC932A1FA P3 0 XTAL2 CLKOUT 9 P1 4 INT1 P1 3 INTO SDA 11 12 13 14 16 17 P1 2 TO SCL P2 2 MOSI P2 3 MISO P2 4 SS P2 5 SPICLK P1 1 RXD P1 0 TXD Fig 4 P89LPC932A1 PLCC28 pin configuration P0 2 CIN2A KBI2 P0 3 CIN1B KBI3 P0 4 CIN1A KBI4 P0 5 CMPREF KBI5 VDD P0 6 CMP1 KBI6 P0 7 T1 KBI7 002aaa887 o a g x ofa X lt x Q Z QN gt Q Z R GRS S R j SS c O de XD oov terminal 1 rON NAAN CO oaaoaoaoad index area el T eG 24 23 22 P1 6 O0CB P1 5 RST Vss P3 1 XTAL1 P3 0 XTAL2 CLKOUT P1 4 INT1 P1 3 INTO SDA P89LPC932A1FHN f fe d go WQ QQ 97 SIR 39 2 o zs oct o2zt E NSE A AN A baa r amp a a o Transparent top view Fig 5 P89LPC932A1 HVQFN28 pin configuration P0 2 CIN2A KBI2 P0 3 CIN1B KBI3 PO 4 CIN1A KBIA4 P0 5 CMPREF KBI5 P0 6 CMP1 KBI6 P0 7 T1 KBI7 002aaa889 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 6 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core P2 0 ICB P2 7 ICA P2 1 OC
38. ain when used as outputs P1 5 is input only All pins have Schmitt trigger inputs Port 1 also provides various special functions as described below P1 0 TXD 18 14 lO P1 0 Port 1 bit 0 O TXD Transmitter output for the serial port P1 1 RXD 17 13 lO P1 1 Port 1 bit 1 l RXD Receiver input for the serial port P1 2 TO SCL 12 8 lO P1 2 Port 1 bit 2 open drain when used as output lO TO Timer counter 0 external count input or overflow output open drain when used as output lO SCL l C serial clock input output P1 3 INTO 11 7 lO P1 3 Port 1 bit 3 open drain when used as output SDA l INTO External interrupt 0 input O SDA C serial data input output P1 4 INT1 10 6 l P1 4 Port 1 bit 4 P89LPC932A1_3 INT1 External interrupt 1 input NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 8 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core Table 2 Pin description continued Symbol Pin Type Description TSSOP28 HVQFN28 PLCC28 DIP28 P1 5 RST 6 2 l P1 5 Port 1 bit 5 input only l RST External Reset input during power on or if selected via UCFG1 When functioning as a reset input a LOW on this pin resets the microcontroller causing I O ports and peripherals to take on their default states and the processor begins execution at address 0 Also used during a
39. al clock timing La TsPICcYC tspiE gt gt lt tsPIR le gt l lsPICLKL tSPICLKH SPICLK CPOL 0 N NF CX output tsPIF tsPIR tSPICLKL a l tSPICLKH SPICLK CPOL 1 N y N A Ne output gt tspipsu tsPIDH MISO MSB LSB in P tsPIDV tSPIOH gt input tsPIDV I sPIR MOSI tsPIF output NP master MSB LSB out master LSB MSB out AN LN 002aaa908 Fig 24 SPI master timing CPHA 0 P89LPC932A1 3 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 52 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core SS m Tspicyc tSPIF e je tSPIR tSPICLKL he tSPICLKH SPICLK A T CPOL 0 output tspiF Brem SPIR SPICLKL P8 SPICLK tSPICLKH CPOL 1 output Y tsPIDSU tsPIDH MISO S input MSB LSB in p LSB MSB in tsPIDV tsPIOH tsPIDV tsPIDV tsPIF tsPIR MOSI N E output master MSB LSB out X N master LSB MSB out N LN 002aaa909 Fig 25 SPI master timing CPHA 1 ss a SPIR m tsPIR TsPICYc tsPI
40. applies 5 V on the pin there will be a current flowing from the pin to Vpp causing extra power consumption Therefore applying 5 V in quasi bidirectional mode is discouraged A quasi bidirectional port pin has a Schmitt trigger input that also has a glitch suppression circuit Open drain output configuration The open drain output configuration turns off all pull ups and only drives the pull down transistor of the port driver when the port latch contains a logic 0 To be used as a logic output a port configured in this manner must have an external pull up typically a resistor tied to Vpp An open drain port pin has a Schmitt trigger input that also has a glitch suppression circuit Input only configuration The input only port configuration has no output drivers It is a Schmitt trigger input that also has a glitch suppression circuit NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 22 of 64 NXP Semiconductors P89LPC932A1 7 13 1 4 7 13 2 7 13 3 7 14 7 14 1 P89LPC932A1 3 8 bit microcontroller with accelerated two clock 80C51 core Push pull output configuration The push pull output configuration has the same pull down structure as both the open drain and the quasi bidirectional output modes but provides a continuous strong pull up when the port latch contains a logic 1 The push pull mode may be used when more source current is needed from a port output A push pull
41. are transmitted or received LSB first The baud rate is fixed at 1 45 of the CPU clock frequency Mode 1 10 bits are transmitted through TXD or received through RXD a start bit logic 0 8 data bits LSB first and a stop bit logic 1 When data is received the stop bit is stored in RB8 in Special Function Register SCON The baud rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator described in Section 7 20 5 Baud rate generator and selection NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 30 of 64 NXP Semiconductors P89LPC932A1 7 20 3 7 20 4 7 20 5 7 20 6 7 20 7 P89LPC932A1 3 8 bit microcontroller with accelerated two clock 80C51 core Mode 2 11 bits are transmitted through TXD or received through RXD start bit logic 0 8 data bits LSB first a programmable 9th data bit and a stop bit logic 1 When data is transmitted the 9 data bit TB8 in SCON can be assigned the value of logic 0 or logic 1 Or for example the parity bit P in the PSW could be moved into TB8 When data is received the 9 data bit goes into RB8 in Special Function Register SCON while the stop bit is not saved The baud rate is programmable to either las or 1 2 of the CPU clock frequency as determined by the SMOD bit in PCON Mode 3 11 bits are transmitted through TXD or received through RXD a start bit logic 0 8 d
42. are a common interrupt vector EA IENO 7 ECCU IEN1 4 TOIE2 TICR2 7 TOIF2 TIFR2 7 TICIE2A TICR2 0 TICF2A TIFR2 0 TICIE2B TICR2 1 TICF2B TIFR2 1 TOCIE2A TICR2 3 TOCF2A TIFR2 3 T TOCIE2B TICR2 4 T 24 49 3 TOCF2B TIFR2 4 TOCIE2C TICR2 5 TOCF2C TIFR2 5 TOCIE2D TICR2 6 TOCF2D TIFR2 6 AFi 2 3 zN E S SR other interrupt Sources interrupt to CPU gt ENCINT O PRIORITY gt ENCINT 1 ENCODER gt ENCINT 2 002aaa896 Fig 12 Capture compare unit interrupts P89LPC932A1 3 7 20 7 20 1 7 20 2 UART The P89LPC932A1 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source The P89LPC932A1 does include an independent Baud Rate Generator The baud rate can be selected from the oscillator divided by a constant Timer 1 overflow or the independent Baud Rate Generator In addition to the baud rate generation enhancements over the standard 80C51 UART include Framing Error detection automatic address recognition selectable double buffering and several interrupt options The UART can be operated in four modes shift register 8 bit UART 9 bit UART and CPU clock 32 or CPU clock 16 Mode 0 Serial data enters and exits through RXD TXD outputs the shift clock 8 bits
43. ata bits LSB first a programmable 9 data bit and a stop bit logic 1 In fact Mode 3 is the same as Mode 2 in all respects except baud rate The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator described in Section 7 20 5 Baud rate generator and selection Baud rate generator and selection The P89LPC932A1 enhanced UART has an independent Baud Rate Generator The baud rate is determined by a baud rate preprogrammed into the BRGR1 and BRGRO SFRs which together form a 16 bit baud rate divisor value that works in a similar manner as Timer 1 but is much more accurate If the baud rate generator is used Timer 1 can be used for other timing functions The UART can use either Timer 1 or the baud rate generator output see Figure 13 Note that Timer T1 is further divided by 2 if the SMOD bit PCON 7 is cleared The independent Baud Rate Generator uses OSCCLK timer 1 overflow SMOD1 1 PCLK based SBRGS 0 Lg 0 baud rate modes 1 and 3 SMOD1 0 baud rate generator SBRGS 1 CCLK based 002aaa897 Fig 13 Baud rate sources for UART Modes 1 3 Framing error Framing error is reported in the status register SSTAT In addition if SMODO PCON 6 is logic 1 framing errors can be made available in SCON 7 respectively If SMODO is logic 0 SCON 7 is SMO It is recommended that SMO and SM1 SCON 7 6 are set up when SMODO is logic 0 Break
44. ction MISO P2 3 CPU clock 8 BIT SHIFT REGISTER MOSI READ DATA BUFFER Pee SPICLK P2 5 DIVIDER BY 4 16 64 128 SS P2 4 SPI clock master gt CLOCK LOGIC A A A SPI CONTROL REGISTER SPI internal interrupt y data request bus 002aaa900 Fig 16 SPI block diagram The SPI interface has four pins SPICLK MOSI MISO and SS SPICLK MOSI and MISO are typically tied together between two or more SPI devices Data flows from master to slave on MOSI Master Out Slave In pin and flows from slave to master on MISO Master In Slave Out pin The SPICLK signal is output in the master mode and is input in the slave mode If the SPI system is disabled i e SPEN SPCTL 6 0 reset value these pins are configured for port functions e SS is the optional slave select pin In a typical configuration an SPI master asserts one of its port pins to select one SPI device as the current slave An SPI slave device uses its SS pin to determine whether it is selected Typical connections are shown in Figure 17 through Figure 19 P89LPC932A1 3 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 35 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core 7 22 4 Typical SPI configurations master slave MISO MISO 8 BIT SHIFT N 8 BIT SHIFT RE
45. ction similar to the brownout detect but is designed to work as power comes up initially before the power supply voltage reaches a level where brownout detect can work The POF flag in the RSTSRC register is set to indicate an initial power up condition The POF flag will remain set until cleared by software Power reduction modes The P89LPC932A1 supports three different power reduction modes These modes are Idle mode Power down mode and Total Power down mode Idle mode Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated Any enabled interrupt source or reset may terminate Idle mode Power down mode The Power down mode stops the oscillator in order to minimize power consumption The P89LPC932A1 exits Power down mode via any reset or certain interrupts In Power down mode the power supply voltage may be reduced to the data retention voltage Vppr This retains the RAM contents at the point where Power down mode was entered SFR contents are not guaranteed after Vpp has been lowered to Vppr therefore it is highly recommended to wake up the processor via reset in this case Vpp must be raised to within the operating range before the Power down mode is exited Some chip functions continue to operate and draw power during Power down mode increasing the total power used during power down These include Brownout detect watchdog timer Comparators note that Comparators can b
46. detect Break detect is reported in the status register SSTAT A break is detected when 11 consecutive bits are sensed LOW The break detect can be used to reset the device and force the device into ISP mode NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 31 of 64 NXP Semiconductors P89LPC932A1 7 20 8 7 20 9 7 20 10 P89LPC932A1 3 8 bit microcontroller with accelerated two clock 80C51 core Double buffering The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the first character is being transmitted Double buffering allows transmission of a string of characters with only one stop bit between any two characters as long as the next character is written between the start bit and the stop bit of the previous character Double buffering can be disabled If disabled DBMOD i e SSTAT 7 0 the UART is compatible with the conventional 80C51 UART If enabled the UART allows writing to SnBUF while the previous data is being shifted out Double buffering is only allowed in Modes 1 2 and 3 When operated in Mode 0 double buffering must be disabled DBMOD 0 Transmit interrupts with double buffering enabled modes 1 2 and 3 Unlike the conventional UART in double buffering mode the Tx interrupt is generated when the double buffer is ready to receive new data The 9th bit bit 8 in double buffering modes 1 2 and 3
47. e powered down separately and RTC System Timer The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled Total Power down mode This is the same as Power down mode except that the brownout detection circuitry and the voltage comparators are also disabled to conserve additional power The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled If the internal RC oscillator is used to clock the RTC during power down there will be high power consumption Please use an external low frequency clock to achieve low power with the RTC running during power down Reset The P1 5 RST pin can function as either an active LOW reset input or as a digital input P1 5 The RPE Reset Pin Enable bit in UCFG1 when set to logic 1 enables the external reset input function on P1 5 When cleared P1 5 may be used as an input pin Remark During a power up sequence The RPE selection is overridden and this pin will always functions as a reset input An external circuit connected to this pin should not hold this pin LOW during a power on sequence as this will keep the device in reset NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 24 of 64 NXP Semiconductors P89LPC932A1 7 16 1 7 17 7 17 1 P89LPC932A1 3 8 bit microcontroller with accelerated two clock 80C51 c
48. e the processor to wake up and resume operation Refer to Section 7 15 Power reduction modes for details X Ll EXO LL 3 EX1 D EBO ke wake up RTCF _ gt KBIF if in power down ERTC EKBI RTCCON 1 2 WDOVF EWDRT e CMF2 CMF1 EC EA IEO 7 TF1 DII e Ll 94 ES ESR TFO ETO fj interrupt EST to CPU EI2C m D ESPI any CCU interrupt j ECCU EEIF EIEE 002aaa892 1 See Section 7 19 CCU Fig 8 Interrupt sources interrupt enables and power down wake up sources 7 13 UO ports The P89LPC932A1 has four I O ports Port 0 Port 1 Port 2 and Port 3 Ports 0 1 and 2 are 8 bit ports and Port 3 is a 2 bit port The exact number of I O pins available depends upon the clock and reset options chosen as shown in Table 5 Table 5 Number of I O pins available Clock source Reset option Number of I O pins 28 pin package On chip oscillator or watchdog oscillator No external reset except during power up 26 External RST pin supported 25 P89LPC932A1 3 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 21 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core Table 5 Number of I O pins available continued Clock source Reset option Number of I O pins 28 pin package External clock input N
49. er with accelerated two clock 80C51 core 15 Legal information 15 1 Data sheet status Document status I2 Product status Definition Objective short data sheet Development Preliminary short data sheet Qualification Product short data sheet Production This document contains data from the objective specification for product development This document contains data from the preliminary specification This document contains the product specification 1 Please consult the most recently issued document before initiating or completing a design 2 The term short data sheet is explained in section Definitions 3 The product status of device s described in this document may have changed since this document was published and may differ in case of multiple devices The latest product status information is available on the Internet at URL http www nxp com 15 2 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information Short data sheet A short data sheet is an extract from a full data sheet with the same product type number s and title A short data sheet is intended for quick re
50. ess otherwise specified Tamb 40 C to 85 C for industrial applications unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit tyr Vpp active to RST active delay time 50 us tRH RST HIGH time 1 32 us tn RST LOW time 1 us Vpp aia tRH RST TRL n2 002aaa912 Fig 28 ISP entry waveform P89LPC932A1 3 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 54 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core 11 Other characteristics 11 1 Comparator electrical characteristics Table 12 Comparator electrical characteristics Vpp 2 4 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial applications unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Vio input offset voltage 10 mV Vic common mode input voltage 0 Vpp O3 V CMRR common mode rejection ratio i 50 dB tres tot total response time 250 500 ns lcE ov chip enable to output valid time 10 us lui input leakage current 0 V Vi Vpp 10 uA 1 This parameter is characterized but not tested in production P89LPC932A1_3 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 55 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core 12 Package outline PLCC28 plastic leaded chip
51. ference only and should not be relied upon to contain detailed and full information For detailed and full information see the relevant full data sheet which is available on request via the local NXP Semiconductors sales office In case of any inconsistency or conflict with the short data sheet the full data sheet shall prevail 15 3 Disclaimers General Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in medical military aircraft space or life support equipment nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to 16 Contact information result in personal injury death or severe property or environmental damage NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors
52. g of the P89LPC932A1 through a two wire serial interface The ICP facility has made ICP in an embedded application using commercially available programmers possible with a minimum of additional expense in components and circuit board area The ICP function uses five pins Only a small connector needs to be available to interface your application to a commercial programmer in order to use this feature Additional details may be found in the P89LPC932A1 User manual In application programming IAP is performed in the application under the control of the microcontroller s firmware The IAP facility consists of internal hardware resources to facilitate programming and erasing The IAP facility has made IAP in an embedded application possible without additional components Two methods are available to accomplish IAP A set of predefined IAP functions are provided in a Boot ROM and can be called through a common interface PGM_MTP Several IAP calls are available for use by an application program to permit selective erasing and programming of flash sectors pages security bits configuration bytes and device ID These functions are selected by setting up the microcontroller s registers before making a call to PGM_MTP at FFOOH The Boot ROM occupies the program memory space at the top of the address space from FFOOH to FEFFH thereby not conflicting with the user program memory space NXP B V 2007 All rights reserved Product data sheet
53. g overall programming time Using flash as data storage The flash code memory array of this device supports individual byte erasing and programming Any byte in the code memory array may be read using the MOVC instruction provided that the sector containing the byte has not been secured a MOVC instruction is not allowed to read code memory contents of a secured sector Thus any byte in a non secured sector may be used for non volatile data storage Flash programming and erasing Four different methods of erasing or programming of the flash are available The flash may be programmed or erased in the end user application IAP under control of the application s firmware Another option is to use the ICP mechanism This ICP system provides for programming through a serial clock serial data interface As shipped from the factory the upper 512 bytes of user code space contains a serial ISP routine allowing for the device to be programmed in circuit through the serial port The flash may also be programmed or erased using a commercially available EPROM programmer which supports this device This device does not provide for direct verification of code memory contents Instead this device provides a 32 bit CRC result on either a sector or the entire user code space In circuit programming ICP is performed without removing the microcontroller from the system The ICP facility consists of internal hardware resources to facilitate remote programmin
54. gure 23 83 ns foLKLP low power select clock frequency 0 8 MHz Glitch filter tor glitch rejection P1 5 RST pin 50 50 ns any pin except 15 15 ns P1 5 RST tsa signal acceptance P1 5 RST pin 125 125 ns any pin except 50 50 ns P1 5 RST External clock tcHcx clock HIGH time see Figure 23 33 Tey cLk tctcx 33 ns tcLcx clock LOW time see Figure 23 33 Toycux tcHcx 33 ns tcLcH clock rise time see Figure 23 8 8 ns tcHcL clock fall time see Figure 23 8 8 ns Shift register UART mode 0 txLxL serial port clock cycle time see Figure 22 16TeycLk 1333 ns tavxH output data set up to clock rising see Figure 22 13Tey cLK 1083 ns edge time txHQX output data hold after clock rising see Figure 22 Tey cLK 20 103 ns edge time XHDX input data hold after clock rising see Figure 22 0 0 ns edge time txHpv input data valid to clock rising see Figure 22 150 150 ns edge time SPI interface lap SPI operating frequency slave 0 CCLK6 0 20 MHz master CCLKA 30 MHz Tspicyc SPI cycle time see Figure 24 25 slave 26 27 6 CCLK 500 ns master 4CCLK 333 ns tsPILEAD SPI enable lead time see Figure 26 27 2 0 MHz slave 250 250 S ns P89LPC932A1 3 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 48 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core Table 9 Dynamic characteristics 12 MHz continued Vpp
55. ides PWM input capture and output compare functions High accuracy internal RC oscillator option allows operation without external oscillator components The RC oscillator option is selectable and fine tunable 2 4 V to 3 6 V Vpp operating range I O pins are 5 V tolerant may be pulled up or driven to 5 5 V 28 pin TSSOP PLCC HVQFN and DIP packages with 23 I O pins minimum and up to 26 I O pins while using on chip oscillator and reset options Additional features A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz This is six times the performance of the standard 80C51 running at the same clock frequency A lower clock frequency for the same performance results in power savings and reduced EMI founded by Philips NXP Semiconductors P89LPC932A1 2 3 P89LPC932A1 3 8 bit microcontroller with accelerated two clock 80C51 core In Circuit Programming ICP allows simple production coding with commercial EPROM programmers Flash security bits prevent reading of sensitive application programs Serial flash In System Programming ISP allows coding while the device is mounted in the end application In Application Programming IAP of the flash code memory This allows changing the code in a running application Watchdog timer with separate on chip oscillator requiring no external components The watchdog prescaler is selectab
56. its associated SFRs to the default state NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 26 of 64 NXP Semiconductors P89LPC932A1 7 19 7 19 1 7 19 2 7 19 3 7 19 4 7 19 5 P89LPC932A1 3 8 bit microcontroller with accelerated two clock 80C51 core CCU This unit features A 16 bit timer with 16 bit reload on overflow e Selectable clock with prescaler to divide clock source by any integral number between 1 and 1024 Four Compare PWM outputs with selectable polarity e Symmetrical Asymmetrical PWM selection Two Capture inputs with event counter and digital noise rejection filter Seven interrupts with common interrupt vector one Overflow two Capture four Compare e Safe 16 bit read write via shadow registers CCU clock The CCU runs on the CCU Clock CCUCLK which is either PCLK in basic timer mode or the output of a Phase Locked Loop PLL The PLL is designed to use a clock source between 0 5 MHz to 1 MHz that is multiplied by 32 to produce a CCUCLK between 16 MHz and 32 MHz in PWM mode asymmetrical or symmetrical The PLL contains a 4 bit divider to help divide PCLK into a frequency between 0 5 MHz and 1 MHz CCUCLK prescaling This CCUCLK can further be divided down by a prescaler The prescaler is implemented as a 10 bit free running counter with programmable reload at overflow Basic timer operation The Timer is a free running up down co
57. ization a an 19 74209 Transmit interrupts with double buffering 7 11 Data RAM arrangement 20 enabled modes 1 2 and3 32 7 12 Interrupts osier caa Rg e R Ra Re E d eee 20 7 20 10 The 9 bit bit 8 in double buffering 7 12 1 External interrupt inputs 20 modes 1 2 and S 32 743 UO porte 21 7 21 C bus serial interface 33 7 13 1 Port configurations 22 722 Serial Peripheral Interface SPI 35 7 13 1 1 Quasi bidirectional output configuration 22 7 22 1 Typical SPI configurations 36 7 13 1 2 Open drain output configuration 22 7 23 Analog comparators 4 38 7 13 1 3 Input only configuration 22 Pen Internal reference voltage 55s ene an 38 7 13 1 4 Push pull output configuration 23 7 23 2 Comparator interrupt MM 38 7 13 2 Port 0 analog functions n sassaaaaaa 23 7 23 3 Comparators and power reduction modes 39 7 13 3 Additional port features 23 7 24 Keypad interrupt T 39 7 14 Power monitoring functions 23 7 25 Watchdog AME RS 9 0 kas eo iocis ini 40 7 14 1 Brownout detection sasa saaa eaan 23 7 26 Additional features L L L L 40 7 14 2 Power on detection na sana nnnnnn 24 te Software reset NT DOLCE 40 7 15 Power reduction modes L LL 24 7 26 2 Dual data pointers 4 40 7145 1 Ide mode 24 MEL EEPROM
58. le from eight values Low voltage reset brownout detect allows a graceful system shutdown when power fails May optionally be configured as an interrupt Idle and two different power down reduced power modes Improved wake up from Power down mode a LOW interrupt input starts execution Typical power down current is 1 uA total power down with voltage comparators disabled Active LOW reset On chip power on reset allows operation without external reset components A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets A software reset function is also available Configurable on chip oscillator with frequency range options selected by user programmed flash configuration bits Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 18 MHz Oscillator fail detect The watchdog timer has a separate fully on chip oscillator allowing it to perform an oscillator fail detect function Programmable port output configuration options quasi bidirectional open drain push pull input only Port input pattern match detect Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern LED drive capability 20 mA on all port pins A maximum limit is specified for the entire chip Controlled slew rate port outputs to reduce EMI Outputs have approximately 10 ns minimum ramp times Only power and ground connections are required to o
59. list Acronym CCU CPU CRC EPROM EEPROM EMI LED PLL PWM RAM RC RTC SFR SPI UART Description Capture Compare Unit Central Processing Unit Cyclic Redundancy Check Erasable Programmable Read Only Memory Electrically Erasable Programmable Read Only Memory ElectroMagnetic Interference Light Emitting Diode Phase Locked Loop Pulse Width Modulator Random Access Memory Resistance Capacitance Real Time Clock Special Function Register Serial Peripheral Interface Universal Asynchronous Receiver Transmitter NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 60 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core 14 Revision history Table 14 Revision history Document ID Release date Data sheet status Change notice P89LPC932A1 3 20070312 Product data sheet Modifications Supersedes P89LPC932A1 2 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors Legal texts have been adapted to the new company name where appropriate Added new part type P89LPC932A1FN P89LPC932A1 2 20050510 Product data sheet P89LPC932A1 1 P89LPC932A1 1 20040720 Product data sheet P89LPC932A1 3 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 61 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroll
60. mally execute user code but can be manually forced into ISP operation If the factory default setting for the Boot Vector 1FH is changed it will no longer point to the factory preprogrammed ISP boot loader code After programming the flash the status byte should be programmed to zero in order to allow execution of the user s application code beginning at address 0000H NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 43 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core 7 29 User configuration bytes Some user configurable features of the P89LPC932A1 must be defined at power up and therefore cannot be set by the program after start of execution These features are configured through the use of the flash byte UCFG1 Please see the P89LPC932A1 User manual for additional details 7 30 User sector security bytes There are eight User Sector Security Bytes on the P89LPC932A1 device Each byte corresponds to one sector Please see the P89LPC932A1 User manual for additional details P89LPC932A1 3 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 44 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core 8 Limiting values Table 7 Limiting values In accordance with the Absolute Maximum Rating System IEC 60134 Symbol Parameter Conditions Min Max Unit
61. nformation Type number Package Name Description Version P89LPC932A1FA PLCC28 plastic leaded chip carrier 28 leads SOT261 2 P89LPC932A1FDH TSSOP28 plastic thin shrink small outline package 28 leads body width SOT361 1 4 4 mm P89LPC932A1FHN HVQFN28 plastic thermal enhanced very thin quad flat package no leads SOT788 1 28 terminals body 6 x 6 x 0 85 mm P89LPC932A1FN DIP28 plastic dual in line package 28 leads 600 mil SOT117 1 P89LPC932A1 3 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 3 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core 4 Block diagram P89LPC932A1 ACCELERATED 2 CLOCK 80C51 CPU Pa TXD 8 kB I Bem internal bus SCL 256 BYTE 2 9 e EI SPICLK 512 BYTE MISO ya 7 ees SS 512 BYTE c y REAL TIME CLOCK DATA EEPROM SYSTEM TIMER PORT 3 TIMER 0 TO xl am fete c ee ee CMP2 l PORT 2 CIN2A a conFIGURABLE 10s Sees E SE CIN1A CIN1B PORT 1 P1 7 0 T CONFIGURABLE l Os LI OcA CCU CAPTURE OCC f PORT 0 PO 7 im CONFIGURABLE l Os COMPARE UNIT ICB KEYPAD INTERRUPT POWER MONITOR WATCHDOG TIMER POWER ON RESET AND OSCILLATOR BROWNOUT RESET PROGRAMMABLE epu S OSCILLATOR DIVIDER Sock XTAL1 CRYSTAL ERE CONFIGURABLE P OR OSCILLATOR RESONATOR xTAL2 OSCILLATOR 002aaa885 Fig 1 Block diagram P89LPC9
62. nters 0 and 1 The P89LPC932A1 has two general purpose counter timers which are upward compatible with the standard 80C51 Timer 0 and Timer 1 Both can be configured to operate either as timers or event counter An option to automatically toggle the TO and or T1 pins upon timer overflow has been added In the Timer function the register is incremented every machine cycle In the Counter function the register is incremented in response to a 1 to 0 transition at its corresponding external input pin TO or T1 In this function the external input is sampled once during every machine cycle Timer 0 and Timer 1 have five operating modes modes 0 1 2 3 and 6 Modes 0 1 2 and 6 are the same for both Timers Counters Mode 3 is different Mode 0 Putting either Timer into Mode 0 makes it look like an 8048 Timer which is an 8 bit Counter with a divide by 32 prescaler In this mode the Timer register is configured as a 13 bit register Mode 0 operation is the same for Timer 0 and Timer 1 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 25 of 64 NXP Semiconductors P89LPC932A1 7 17 2 7 17 3 7 17 4 7 17 5 7 17 6 7 18 P89LPC932A1 3 8 bit microcontroller with accelerated two clock 80C51 core Mode 1 Mode 1 is the same as Mode 0 except that all 16 bits of the timer register are used Mode 2 Mode 2 configures the Timer register as an 8 bit Counter with automatic
63. o external reset except during power up 25 External RST pin supported 24 Low medium high speed oscillator No external reset except during power up 24 external crystal or resonator External RST pin supported 23 1 Required for operation above 12 MHz 7 13 1 7 13 1 1 7 13 1 2 7 13 1 3 P89LPC932A1_3 Port configurations All but three I O port pins on the P89LPC932A1 may be configured by software to one of four types on a bit by bit basis These are quasi bidirectional standard 80C51 port outputs push pull open drain and input only Two configuration registers for each port select the output type for each port pin 1 P1 5 RST can only be an input and cannot be configured 2 P1 2 SCL TO and P1 3 SDA INTO may only be configured to be either input only or open drain Quasi bidirectional output configuration Quasi bidirectional output type can be used as both an input and output without the need to reconfigure the port This is possible because when the port outputs a logic HIGH it is weakly driven allowing an external device to pull the pin LOW When the pin is driven LOW it is driven strongly and able to sink a fairly large current These features are somewhat similar to an open drain output except that there are three pull up transistors in the quasi bidirectional output that serve different purposes The P89LPC932A1 is a 3 V device but the pins are 5 V tolerant In quasi bidirectional mode if a user
64. ore After power up this input will function either as an external reset input or as a digital input as defined by the RPE bit Only a power up reset will temporarily override the selection defined by RPE bit Other sources of reset will not override the RPE bit Reset can be triggered from the following sources External reset pin during power up or if user configured via UCFG1 Power on detect Brownout detect e Watchdog timer Software reset UART break character detect reset For every reset source there is a flag in the Reset Register RSTSRC The user can read this register to determine the most recent reset source These flag bits can be cleared in software by writing a logic 0 to the corresponding bit More than one flag bit may be set During a power on reset both POF and BOF are set but the other flag bits are cleared For any other reset previously set flag bits that have not been cleared will remain set Reset vector Following reset the P89LPC932A1 will fetch instructions from either address 0000H or the Boot address The Boot address is formed by using the Boot Vector as the high byte of the address and the low byte of the address OOH The Boot address will be used if a UART break reset occurs or the non volatile Boot Status bit BOOTSTAT 0 1 or the device is forced into ISP mode during power on see P89LPC932A1 User manual Otherwise instructions will be fetched from address 0000H Timers cou
65. own modes This feature is particularly useful in handheld battery powered systems that need to carefully manage power consumption yet also need to be convenient to use In order to set the flag and cause an interrupt the pattern on Port 0 must be held longer than six CCLKs NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 39 of 64 NXP Semiconductors P89LPC932A1 7 25 8 bit microcontroller with accelerated two clock 80C51 core Watchdog timer The watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching its terminal count It consists of a programmable 12 bit prescaler and an 8 bit down counter The down counter is decremented by a tap taken from the prescaler The clock source for the prescaler is either the PCLK or the nominal 400 kHz watchdog oscillator The watchdog timer can only be reset by a power on reset When the watchdog feature is disabled it can be used as an interval timer and may generate an interrupt Figure 21 shows the watchdog timer in Watchdog mode Feeding the watchdog requires a two byte sequence If PCLK is selected as the watchdog clock and the CPU is powered down the watchdog is disabled The watchdog timer has a time out period that ranges from a few us to a few seconds Please refer to the P89LPC932A1 User manual for more details watchdog oscillator PCLK MOV WFEED 1 0A5H
66. perate the P89LPC932A1 when internal reset option is selected Four interrupt priority levels Eight keypad interrupt inputs plus two additional external interrupt inputs Schmitt trigger port inputs Second data pointer Emulation support Comparison to the P89LPC932 The P89LPC932A1 includes several improvements compared to the P89LPC932 Please see P89LPC932A1 User manual for additional detailed information Byte erasability has been added to the user code memory space All of the errata described in the P89LPC932 Errata sheet have been fixed Serial ICP has been added NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 2 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core B The RCCLK bit has been added to the TRIM register allowing the RCCLK to be selected as the CPU clock CCLK regardless of the settings in UCFG1 allowing the internal RC oscillator to be selected as the CPU clock without the need to reset the device B Enhancements added to the ISP IAP code to improve code safety and increase ISP IAP functionality This may require slight changes to original P89LPC932 code using IAP function calls Some ISP IAP settings are different than the original P89LPC932 Tools designed to support the P89LPC932A1 should be used to program this device such as Flash Magic version 1 98 or later 3 Ordering information Table 1 Ordering i
67. porates power monitoring functions designed to prevent incorrect operation during initial power up and power loss or reduction during operation This is accomplished with two hardware functions Power on detect and brownout detect Brownout detection The brownout detect function determines if the power supply voltage drops below a certain level The default operation is for a brownout detection to cause a processor reset however it may alternatively be configured to generate an interrupt Brownout detection may be enabled or disabled in software If brownout detection is the brownout condition occurs when Vpp falls below the brownout trip voltage Vbo see Table 8 Static characteristics and is negated when Vpp rises above Vp If the P89LPC932A1 device is to operate with a power supply that can be below 2 7 V BOE should be left in the unprogrammed state so that the device can operate at 2 4 V otherwise continuous brownout reset may prevent the device from operating NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 23 of 64 NXP Semiconductors P89LPC932A1 7 14 2 7 15 7 15 1 7 15 2 7 15 3 7 16 P89LPC932A1 3 8 bit microcontroller with accelerated two clock 80C51 core For correct activation of brownout detect the Vpp rise and fall times must be observed Please see Table 8 Static characteristics for specifications Power on detection The Power on detect has a fun
68. port pin has a Schmitt trigger input that also has a glitch suppression circuit Port 0 analog functions The P89LPC932A1 incorporates two Analog Comparators In order to give the best analog function performance and to minimize power consumption pins that are being used for analog functions must have the digital outputs and digital inputs disabled Digital outputs are disabled by putting the port output into the Input only high impedance mode Digital inputs on Port 0 may be disabled through the use of the PTOAD register bits 1 5 On any reset PTOAD 1 5 defaults to logic Os to enable digital functions Additional port features After power up all pins are in Input only mode Please note that this is different from the LPC76x series of devices e After power up all I O pins except P1 5 may be configured by software e Pin P1 5 is input only Pins P1 2 and P1 3 and are configurable for either input only or open drain Every output on the P89L PC932A1 has been designed to sink typical LED drive current However there is a maximum total output current for all ports which must not be exceeded Please refer to Table 8 Static characteristics for detailed specifications All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals The slew rate is factory set to approximately 10 ns rise and fall times Power monitoring functions The P89LPC932A1 incor
69. power on sequence to force ISP mode When using an oscillator frequency above 12 MHz the reset input function of P1 5 must be enabled An external circuit is required to hold the device in reset at power up until Vpp has reached its specified level When system power is removed Vpp will fall below the minimum specified operating voltage When using an oscillator frequency above 12 MHz in some applications an external brownout detect circuit may be required to hold the device in reset when Vpp falls below the minimum specified operating voltage P1 6 OCB 5 1 lO P1 6 Port 1 bit 6 O OCB Output Compare B P1 7 0CC 4 28 lO P1 7 Port 1 bit 7 O OCC Output Compare C P2 0 to P2 7 lO Port 2 Port 2 is an 8 bit I O port with a user configurable output type During reset Port 2 latches are configured in the input only mode with the internal pull up disabled The operation of Port 2 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 7 13 1 Port configurations and Table 8 Static characteristics for details All pins have Schmitt trigger inputs Port 2 also provides various special functions as described below P2 0 ICB 1 25 lO P2 0 Port 2 bit 0 l ICB Input Capture B P2 1 OCD 2 26 lO P2 1 Port 2 bit 1 O OCD Output Compare D P2 2 MOSI 13 9 lO P2 2 Port 2 bit 2 UO MOS SPI master out slave in When configured as master
70. products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Limiting values Stress above one or more limiting values as defined in the Absolute Maximum Ratings System of IEC 60134 may cause permanent damage to the device Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied Exposure to limiting values for extended periods may affect device reliability Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale as published at http www nxp com profile terms including those pertaining to warranty intellectual property rights infringement and limitation of liability unless explicitly otherwise agreed to in writing by NXP Semiconductors In case of any inconsistency or conflict between information in this document and such terms and conditions the latter will prevail No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or
71. re 23 see Figure 23 see Figure 23 see Figure 22 see Figure 22 see Figure 22 see Figure 22 see Figure 22 see Figure 24 25 26 27 see Figure 26 27 see Figure 26 27 Variable clock fosc 18 MHz Unit Min Max Min Max 7 189 7 557 7 189 7 557 MHz 280 480 280 480 kHz 0 18 MHz 55 ns 0 8 MHz 50 50 ns 15 15 ns 125 125 ns 50 50 ns 22 Tey CLk tcLCX 22 ns 22 Tey CLK tcHcex 22 ns 5 5 ns 5 5 ns 16Tcy cLk 888 ns 1 3Tey CLk 722 ns Tey CLK 20 75 ns 0 0 ns 150 150 ns 0 CCLK6 0 30 MHz CCLKA 45 MHz 6CCLK 333 ns 4CCLK 222 ns 250 250 ns 250 250 ns NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 50 of 64 P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core NXP Semiconductors Table 10 Dynamic characteristics 18 MHz continued Vpp 3 0 V to 3 6 V unless otherwise specified Tamp 40 C to 85 C for industrial applications unless otherwise specified 112 Symbol Parameter Conditions Variable clock fosc 18 MHz Unit Min Max Min Max tsPICLKH SPICLK HIGH time see Figure 24 master 25 26 27 2CCLK 111 7 ns slave 3CCLK 167 ns tsPICLKL SPICLK LOW time see Figure 24 master 25 26 27 2 CCLK 111 ns slave 3CCLK 167 ns tePIDSU SPI data set up time master or see Figure 24 100 100 ns slave 25
72. reload Mode 2 operation is the same for Timer 0 and Timer 1 Mode 3 When Timer 1 is in Mode 3 it is stopped Timer 0 in Mode 3 forms two separate 8 bit counters and is provided for applications that require an extra 8 bit timer When Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator Mode 6 In this mode the corresponding timer can be changed to a PWM with a full period of 256 timer clocks Timer overflow toggle output Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs The same device pins that are used for the TO and T1 count inputs are also used for the timer toggle outputs The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on RTC system timer The P89LPC932A1 has a simple RTC that allows a user to continue running an accurate timer while the rest of the device is powered down The RTC can be a wake up or an interrupt source The RTC is a 23 bit down counter comprised of a 7 bit prescaler and a 16 bit loadable down counter When it reaches all logic Os the counter will be reloaded again and the RTCF flag will be set The clock source for this counter can be either the CCLK or the XTAL oscillator provided that the XTAL oscillator is not being used as the CPU clock If the XTAL oscillator is used as the CPU clock then the RTC will use CCLK as its clock source Only power on reset will reset the RTC and
73. rrupt Each comparator has an interrupt flag contained in its configuration register This flag is set whenever the comparator output changes state The flag may be polled by software or may be used to generate an interrupt The two comparators use one common interrupt vector If both comparators enable interrupts after entering the interrupt service routine the user needs to read the flags to determine which comparator caused the interrupt NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 38 of 64 NXP Semiconductors P89LPC932A1 7 23 3 7 24 P89LPC932A1 3 8 bit microcontroller with accelerated two clock 80C51 core Comparators and power reduction modes Either or both comparators may remain enabled when Power down or Idle mode is activated but both comparators are disabled automatically in Total Power down mode If a comparator interrupt is enabled except in Total Power down mode a change of the comparator output state will generate an interrupt and wake up the processor If the comparator output to a pin is enabled the pin should be configured in the push pull mode in order to obtain fast switching times while in Power down mode The reason is that with the oscillator stopped the temporary strong pull up that normally occurs during switching on a quasi bidirectional port pin does not take place Comparators consume power in Power down and Idle modes as well as in the normal opera
74. s Gadecana baw dd eden 27 6 2 Pin description 0 0 0 c eee eee 7 7 19 2 CCUCLK prescaling llle 27 7 Functional description 11 7 19 3 Basic timer Operation 27 7 1 Special function registers 11 7 19 4 Output compare L L L sees 27 72 Enhanced CPU lt lt ccccccccccecuce 17 7 19 5 Input capture 6 2 eee 27 73 Cloche ooann aaeeea raan 17 7419 6 PWM operation E 28 7 3 1 Clock definitions o n nnno nnna 47 719 7 Alternating output mode 29 732 CPU clock OSCCLK esses 17 7 19 8 PLL operation T 29 733 Low speed oscillator option 17 7 19 9 CCU interrupts 000 eee eee 30 7 3 4 Medium speed oscillator option 17 7 20 UART n n 6n 30 7 3 5 High speed oscillator option 17 7 20 1 Mode 0 2 e sete seer eee eee 30 7 3 6 Clock output llle 17 7 20 2 Model 30 74 On chip RC oscillator option 18 7 20 3 Mode2 o pe eL eR eq er PESE YS 31 75 Watchdog oscillator option 18 7 20 4 Mode 2 eene 31 7 6 External clock input option 18 7 20 5 Baud rate generator and selection 31 77 CCLK wake up delay 000 19 7 20 6 Framing error 0 0 0 e eee 31 78 CCLK modification DIVM register 19 7 20 7 Break detect L 31 79 Low power select 00eeeeeee 19 7 20 8 Double buffering ZELLE eet 32 7 10 Memory organ
75. set to a value other than zero the contents of the Boot Vector are used as the high byte of the execution address and the low byte is set to OOH Table 6 shows the factory default Boot Vector settings for these devices Note These settings are different than the original P89LPC932 Tools designed to support the P89LPC932A1 should be used to program this device such as Flash Magic version 1 98 or later A factory provided boot loader is preprogrammed into the address space indicated and uses the indicated boot loader entry point to perform ISP functions This code can be erased by the user Users who wish to use this loader should take precautions to avoid erasing the 1 kB sector that contains this boot loader Instead the page erase function can be used to erase the first eight 64 byte pages located in this sector A custom boot loader can be written with the Boot Vector set to the custom boot loader if desired Table 6 Default Boot Vector values and ISP entry points Device Default Default Default boot loader 1 kB sector Boot Vector boot loader code range range entry point P89LPC932A1 1FH 1FOOH 1E00H to 1FFFH 1COOH to 1FFFH Hardware activation of the boot loader The boot loader can also be executed by forcing the device into ISP mode during a power on sequence see the P89LPC932A1 User manual for specific information This has the same effect as having a non zero status byte This allows an application to be built that will nor
76. sse RM I E 2 7 15 2 Power down mode 24 7 28 Flash program memory sss 41 7 15 3 Total Power down mode 24 7 28 1 General description llus 41 746 Hed llle snc pau E ates 24 7 28 2 F atUreS 2s sa leri ege Re uns 41 continued gt gt P89LPC932A1_3 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 63 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core 7 28 3 Flash organization 42 7 28 4 Using flash as data storage 42 7 28 5 Flash programming and erasing 42 7 28 6 In circuit programming lesse 42 7 28 7 In application programming 42 7 28 8 In system programming sss 43 7 28 9 Power on reset code execution 43 7 28 10 Hardware activation of the boot loader 43 7 29 User configuration bytes 44 7 30 User sector security bytes 44 8 Limiting values sss s x e x e e x e x ee 45 9 Static characteristics Ls 46 10 Dynamic characteristics 48 10 1 Waveforms cee eee eee 52 10 2 ISP entry mode eee eee 54 11 Other characteristics 000005 55 11 1 Comparator electrical characteristics 55 12 Package outline lesus 56 13 Abbreviations llle 60 14 Revision history s eese 61 15 Legal information sse x e x e x x x e 62 15 1 Da
77. state non transient limits on lo or lox If loL lo exceeds the test condition Voi Vou may exceed the related specification 5 This specification can be applied to pins which have analog comparator input functions when the pin is not being used for those analog functions When the pin is being used as an analog input pin the maximum voltage on the pin must be limited to 4 0 V with respect to Vss 6 Pin capacitance is characterized but not tested 7 Measured with port in quasi bidirectional mode 8 Measured with port in high impedance mode 9 Port pins source a transition current when used in quasi bidirectional mode and externally driven from logic 1 to logic 0 This current is highest when V is approximately 2 V P89LPC932A1 3 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 47 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core 10 Dynamic characteristics Table 9 Dynamic characteristics 12 MHz Vpp 2 4 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial applications unless otherwise specified 112 Symbol Parameter Conditions Variable clock fosc 12 MHz Unit Min Max Min Max fosc Ro internal RC oscillator frequency 7 189 7 557 7 189 7 557 MHz fosc wp internal watchdog oscillator 280 480 280 480 kHz frequency fosc oscillator frequency 0 12 MHz Toy CLK clock cycle time see Fi
78. ta sheet status uuu uauauaaaauan 62 15 2 Definitions a 0 59 6 coh aad ee ve ce 62 15 3 Disclaimers ecr erkekte pecute f audi RR T 62 15 4 Trademarks 52a eR Li oes 62 16 Contact information e x x 62 17 Contents Ri pr UR x ups 63 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information founded by NXP B V 2007 All rights reserved For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 12 March 2007 Document identifier PS9LPC932A1 3
79. ters SFRs accesses are restricted in the following ways User must not attempt to access any SFR locations not defined Accesses to any defined SFR locations must be strictly for the functions for the SFRs SFR bits labeled logic 0 or logic 1 can only be written and read as follows Unless otherwise specified must be written with logic 0 but can return any value when read even if it was written with logic O It is a reserved bit and may be used in future derivatives Logic 0 must be written with logic 0 and will return a logic 0 when read Logic 1 must be written with logic 1 and will return a logic 1 when read P89LPC932A1 3 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 11 of 64 199usS ejep 19npoJd 2002 421e ZL 0 AY v9 40 ZL IVe 6Od 68d peAJese SIUDU IY 002 8 dXN Table 3 Special function registers indicates SFRs that are bit addressable Name ACC AUXR1 Be BRGRO BRGR1 BRGCON CCCRA CCCRB CCCRC CCCRD CMP1 CMP2 DEECON DEEDAT DEEADR DIVM DPTR DPH DPL I2ADR I2CON Description SFR addr Bit address Accumulator EOH Auxiliary function register A2H Bit address B register FOH Baud rate generator rate low BEH Baud rate generator rate high BFH Baud rate generator control BDH Capture compare A control EAH register Capture compare B control EBH register Capture compare
80. the grant conveyance or implication of any license under any copyrights patents or other industrial or intellectual property rights 15 4 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners I C bus logo is a trademark of NXP B V For additional information please visit http www nxp com For sales office addresses send an email to salesaddresses nxp com P89LPC932A1 3 NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 62 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core 17 Contents 1 General description 1 7 16 1 Reset vector 20000 cece eee 25 2 Features sessi 1 7 17 Timers counters 0 and 1 25 2 1 Principal features 0000000 ue 1 7171 Mode 0 0 eee reece teers 25 2 2 Additional features 1 7172 Mode T 26 23 Comparison to the P89LPC932 2 ie i S L S M l 17 de 3 cis eee du ERI UE d Gaal INTO BRUDER a cons Usi applied iod STATS Mode8 eie retetrere tee etes 26 4 Block diagram esee 4 7476 Timeroverflow toggle output 26 5 Functional diagram sx e K e gt C K gt C gt 5 7 189 RTC system mer 26 6 Pinning information lesse 5 7 19 puel 27 6 1 PINNING ae iue deme ete pede Ee rep ds 5 7 19 1 CCW ele ves acc aeon
81. ting pairs for bridge drive control In this mode the output of these PWM channels are alternately gated on every counter cycle TOR2 COMPARE VALUE A or C COMPARE VALUE B or D 4 TIMER VALUE 0 I7T71 T7T 7 U 4 l I PWM OUTPUT OCA or OCC on PWM OUTPUT OCB or OCD 002aaa895 Fig 11 Alternate output mode PLL operation The PWM module features a PLL that can be used to generate a CCUCLK frequency between 16 MHz and 32 MHZ At this frequency the PWM module provides ultrasonic PWM frequency with 10 bit resolution provided that the crystal frequency is 1 MHz or higher The PLL is fed an input signal from 0 5 MHz to 1 MHz and generates an output signal of 32 times the input frequency This signal is used to clock the timer The user will have to set a divider that scales PCLK by a factor from 1 to 16 This divider is found in the SFR register TCR21 The PLL frequency can be expressed as shown in Equation 1 PCLK N 1 1 Where N is the value of PLLDV 3 0 PLL frequency Since N ranges from 0 to 15 the CCLK frequency can be in the range of PCLK to POLK NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 29 of 64 NXP Semiconductors P89LPC932A1 7 19 9 8 bit microcontroller with accelerated two clock 80C51 core CCU interrupts There are seven interrupt sources on the CCU which sh
82. ting mode This fact should be taken into account when system power consumption is an issue To minimize power consumption the user can disable the comparators via PCONA 5 or put the device in Total Power down mode Keypad interrupt The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern This function can be used for bus address recognition or keypad recognition The user can configure the port via SFRs for different tasks The Keypad Interrupt Mask Register KBMASK is used to define which input pins connected to Port 0 can trigger the interrupt The Keypad Pattern Register KBPATN is used to define a pattern that is compared to the value of Port 0 The Keypad Interrupt Flag KBIF in the Keypad Interrupt Control Register KBCON is set when the condition is matched while the Keypad Interrupt function is active An interrupt will be generated if enabled The PATN SEL bit in the Keypad Interrupt Control Register KBCON is used to define equal or not equal for the comparison In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series the user needs to set KBPATN OFFH and PATN SEL 1 not equal then any key connected to Port 0 which is enabled by the KBMASK register will cause the hardware to set KBIF and generate an interrupt if it has been enabled The interrupt may be used to wake up the CPU from Idle or Power d
83. tion The P89LPC932A1 has 8 kB of on chip Code memory The P89LPC932A1 also has 512 bytes of on chip Data EEPROM that is accessed via SFRs see Section 7 27 Data EEPROM Data RAM arrangement The 768 bytes of on chip RAM are organized as shown in Table 4 Table 4 On chip data memory usages Type Data RAM Size bytes DATA Memory that can be addressed directly and indirectly 128 IDATA Memory that can be addressed indirectly 256 XDATA Auxiliary External Data on chip memory that is accessed 512 using the MOVX instructions Interrupts The P89LPC932A1 uses a four priority level interrupt structure This allows great flexibility in controlling the handling of the many interrupt sources The P89LPC932A1 supports 15 interrupt sources external interrupts 0 and 1 timers 0 and 1 serial port Tx serial port Rx combined serial port Rx Tx brownout detect watchdog RTC I2C bus keyboard comparators 1 and 2 SPI CCU and data EEPROM write completion Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IENO or IEN1 The IENO register also contains a global disable bit EA which disables all interrupts Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IPO IPOH IP1 and IP1H An interrupt service routine in progress can be interrupted by a higher priori
84. ty interrupt but not by another interrupt of the same or lower priority The highest priority interrupt service cannot be interrupted by any other interrupt source If two requests of different priority levels are pending at the start of an instruction the request of higher priority level is Serviced If requests of the same priority level are pending at the start of an instruction an internal polling sequence determines which request is serviced This is called the arbitration ranking Note that the arbitration ranking is only used to resolve pending requests of the same priority level External interrupt inputs The P89LPC932A1 has two external interrupt inputs as well as the Keypad Interrupt function The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers These external interrupts can be programmed to be level triggered or edge triggered by setting or clearing bit IT1 or ITO in Register TCON NXP B V 2007 All rights reserved Product data sheet Rev 03 12 March 2007 20 of 64 NXP Semiconductors P89LPC932A1 8 bit microcontroller with accelerated two clock 80C51 core In edge triggered mode if successive samples of the INTn pin show a HIGH in one cycle and a LOW in the next cycle the interrupt request flag IEn in TCON is set causing an interrupt request If an external interrupt is enabled when the P89LPC9324A1 is put into Power down or Idle mode the interrupt will caus
85. unter with a direction control bit If the timer counting direction is changed while the counter is running the count sequence will be reversed The timer can be written or read at any time When a reload occurs the CCU Timer Overflow Interrupt Flag will be set and an interrupt generated if enabled The 16 bit CCU Timer may also be used as an 8 bit up down timer Output compare There are four output compare channels A B C and D Each output compare channel needs to be enabled in order to operate and the user will have to set the associated I O pin to the desired output mode to connect the pin When the contents of the timer matches that of a capture compare control register the Timer Output Compare Interrupt Flag TOCFx becomes set An interrupt will occur if enabled Input capture Input capture is always enabled Each time a capture event occurs on one of the two input capture pins the contents of the timer is transferred to the corresponding 16 bit input capture register The capture event can be programmed to be either rising or falling edge triggered A simple noise filter can be enabled on the input capture by enabling the Input Capture Noise Filter bit If set the capture logic needs to see four consecutive samples of the same value in order to recognize an edge as a capture event An event counter can be set to delay a capture by a number of capture events NXP B V 2007 All rights reserved Product data sheet Rev
86. ut mode 1 84H POM1 7 POM1 6 POM1 5 POM1 4 POM1 3 POM1 2 POM1 1 POM1 0 FFB 11111111 POM2 Port 0 output mode 2 85H POM2 7 POM2 6 POM2 5 POM2 4 POM2 3 POM2 2 POM2 1 POM2 0 O0l2 0000 0000 P1M1 Port 1 output mode 1 91H P1M1 7 P1M1 6 P1M1 4 P1M1 3 P1M1 2 P1M1 1 P1M1 0 D3l2 11x1 xx11 P1M2 Port 1 output mode 2 92H P1M2 7 P1M2 6 P1M2 4 P1M2 3 P1M2 2 P1M2 1 P1M2 0 00l2 00x0 xx00 P2M1 Port 2 output mode 1 A4H P2M1 7 P2M1 6 P2M1 5 P2M1 4 P2M1 3 P2M1 2 P2M1 1 P2M1 0 FF 11111111 P2M2 Port 2 output mode 2 A5H P2M2 7 P2M2 6 P2M2 5 P2M2 4 P2M2 3 P2M2 2 P2M2 1 P2M2 0 002l 0000 0000 P3M1 Port 3 output mode 1 B1H E S S P3M1 1 P3M1 0 0312 XXXX xx11 P3M2 Port 3 output mode 2 B2H P3M2 1 P3M2 0 002 Xxxx xx00 PCON Power control register 87H SMOD1 SMODO BOPD BOI GF1 GFO PMOD1 PMODO 00 0000 0000 9109 16209 490 9 OM p91819 929 YIM 19 0J1u020491UI 1Iq 9 LVc amp 60d 168d SIOJONPUODIWIBS dXN 199usS Lep 19npoud 2002 421e ZL 0 eH v9 J0 SL IVe 6O0d 68d peAJese SIUDU IY 002 8 dXN Table 3 Special function registers continued indicates SFRs that are bit addressable Name PCONA PSW PTOAD RSTSRC RTCCON RTCH RTCL SADDR SADEN SBUF SCON SSTAT SP SPCTL SPSTAT SPDAT TAMOD TCON TCR20 TCR21 THO TH1 TH2 TICR2 TIFR2 Description SFR addr Power control register

P89LPC932A1 8-bit microcontroller with accelerated two

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