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73S8009C Demo Board User Manual

1. US DIAN SEMICONDUCTOR CORP Simplifying System Integration 7358009C Demo Board User Manual February 10 2010 Rev 1 3 UM_8009C_059 73S8009C Demo Board User Manual UM_8009C_059 2010 Teridian Semiconductor Corporation All rights reserved Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation Simplifying System Integration is a trademark of Teridian Semiconductor Corporation All other trademarks are the property of their respective owners Teridian Semiconductor Corporation makes no warranty for the use of its products other than expressly contained in the Company s warranty detailed in the Teridian Semiconductor Corporation standard Terms and Conditions The company assumes no responsibility for any errors which may appear in this document reserves the right to change devices or specifications detailed herein at any time without notice and does not make any commitment to update the information contained herein Accordingly the reader is cautioned to verify that this document is current by comparing it to the latest version on http Awww teridian com or by checking with your sales representative Teridian Semiconductor Corp 6440 Oak Canyon Suite 100 Irvine CA 92618 TEL 714 508 8800 FAX 714 508 8877 http www teridian com 2 Rev 1 3 UM 8009C 059 73S8009C Demo Board User Manual Table of Contents 1 ue He e PEE 5 171 Package Contents anal tes 5
2. e Power Supplies Apply 3 3 V to pin 10 of J4 or 5 V to pins 9 and 10 of J2 depending on the setting of JP2 e Press the ON OFF button e Control signals to the device can be connected through J2 and J4 See Figure 2 and Figure 4 e Apply the clock signal 8 Rev 1 3 UM 8009C 059 73S8009C Demo Board User Manual 3 Jumpers Switches and Test Points The items marked in Figure 3 are described in Table 5 Figure 3 73S8009C Demo Board Description Rev 1 3 co 73S8009C Demo Board User Manual UM 8009C 059 Table 5 7388009C Demo Board Description Item Electrical Figure 3 Schematic amp PCB Silkprint Name Use Reference 1 S1 ON OFF switch Push button switch to turn on off the 73S8009C Note OFF ACK must be set high to turn off 2 JP3 ON OFF Jumper When set to 1 2 the ON OFF input is set to ground which turns on the 7388009C when power is applied When set to 2 3 the push button switch is connected to the ON OFF pin When using VBUS as an always on configuration JP3 must be set to the 1 2 position and the OFF ACK input must be grounded 3 JP2 VPC Select The VPC input can select between the VPC IN and the 3 3 V inputs When selecting the VPC IN the VDD output can source the 3 3 V supply on the evaluation board See the description for JP4 Test Points 4 TP1 VBAT Test point VBAT Input 5 TP2 VBUS Test point VBUS Input 6 TP8 C4 7 TP7 CLK Two pin tes
3. Panasonic C11 0 47 uF 603 PCC2275CT ND ECJ 1VBOJ475K Panasonic 4 JP2 JP3 Header 3 3pins 2 54mm pitch S1011E 36 ND PBC36SAAN Sullins JP5 JP6 2 JP4 JP7 Header 2 2pins 2 54mm pitch S1011E 36 ND PBC36SAAN Sullins 2 J1 J3 SSM 110 L SV SSM 110 L SV X SSM 110 L SV Samtec 2 J2 J4 TSM 110 01 L SV TSM 110 01 L SV X TSM 110 01 L SV Samtec 1 J5 Smart Card Connector ITT CCMO2 2504 401 1715 ND CCMO02 2504LFT ITTCannon 1 J6 SIM SAM Connector ITT CCMO03 3754 P CCM03 3754 ITTCannon 1 Li Inductor 445 1998 1 ND SLF7032T TDK 100M1R4 2 PF 2 R7 0 603 PO OGCT ND ERJ 3GEYOROOV Panasonic 1 S1 Switch Panasonic EVQ P8051SCT EVQ PJX05M Panasonic 8 TP1 TP2 TP 2X1 Header 1011E 36 ND PBC36SAAN Sullins TP3 TP4 TP5 TP6 TP7 TP8 1 U1 73S8009C 32QFN X 73S8009C Teridian Note The resistors noted Ru and Rd in the schematic are not populated on the board They can be implemented to adjust the features of the smart card reader 6 Errata The 73S8009C Demo Board contains a silk screen error on JP6 The VDD and GND are reversed and have corrective decals attached to show the proper labeling Rev 1 3 UM 8009C 059 73S8009C Demo Board User Manual 7 Ordering Information Table 7 lists the order number used to identify the 73S8009C Demo Board Table 7 73S8009C Demo Board Order Number Part Description Order Number 7388009C 32 Pin QFN Demo Board 7358009C DB 8 Related Documentation Th
4. state The OFF REQ output follows this toggling If the OFF REQ output is high when VBUS power is removed and the OFF ACK is high the 73S8009C shuts off Rev 1 3 13 73S8009C Demo Board User Manual UM 8009C 059 5 73S8009C Demo Board Schematics PCB Layouts and Bill of Materials 5 1 Schematics Ji aa JP VPCIN SCLK VPC SIO gt a soa 3 SELECT ses 4 P 3 3V OFF 5 E GND amp GND H 1 gt Note JP4 pins 1 3 3V cr tour GND 8 and 2 must not be L1 JN VPCIN E connected with JP AM AL GG Q 1uF Cl C2 C3 and Ll must be placed VPCIN 10 com pine 1 gad Sat thie Ve within 5mm of the Ul pins and 1 connected by thick track wider e time SSM 110 L SV same time Hae Muro s NS E Note VPCIN i Note JP4 pins 1 Ol mu
5. 1 2 Safety and ESD Notes viii oa nas eec ege 5 1 3 Recommended Operating Conditions and Absolute Maximum Hatmgs 6 1 4 Notes When Using a 73512xxF Evaluation Board 6 2 Connections iii RR 7 3 Jumpers Switches and Test Points oonnnnnnccccnnnnnnnnncnccncnnnnnnnnnnn acc 9 4 Design Corissiderations EE 12 4 1 General Layout Rules rne eee cea ea ae 12 4 2 Optimization for Compliance with EM 12 4 3 Power Supply Input Configurations sse nnne nnne 12 4 341 e EE 12 4 3 2 Single Supply Power 12 4 4 ON OFF Switch Operatlon rre etre dada 13 5 73S8009C Demo Board Schematics PCB Layouts and Bill of Materials 14 E e nina DLE 14 Bio 73999009 P Ee EE 15 5 3 7358009C Demo Board Bill of Materas reter eene 18 LH EA 18 7 Ordering UU tel ul ET 19 8 Related DocumentatiON ocoommnnnnnccccnnccnnnnnncnccrrrnnncccr rr 19 9 Contact Information 2 22 022 02 02 0c 20ea20a oi eAP P edd 19 Revision Eege See 20 Rev 1 3 3 73S8009C Demo Board User Manual UM 8009C 059 Figures Figure 739S9009C Demo Board eee e m va n 5 Figure 2 7358009C Demo Board External Connechors aaa nnne 7 Figure 3 7388009C Demo Board Descriotton nennen nnne 9 Figure 4 7358009C Electrical Schematic sssssssssssssssseseeeeeeen eene nnns 14 Figure 5 7388009C Demo Board Top View 15 Figure 6 7388009C Demo Board Bottom View 15 Figure 7 7388009C
6. A 73S8009C Demo Board Rev 1 e The following documents e 7358009C Data Sheet e 73S8009C Demo Board User Manual this document 1 2 Safety and ESD Notes Connecting live voltages to the 73S8009C Demo Board system will result in potentially hazardous voltages on the boards Extreme caution should be taken when handling the 73S8009C Demo Board after connection to live voltages The 73S8009C Demo Board is ESD sensitive ESD precautions should be taken when handling this board Rev 1 3 5 73S8009C Demo Board User Manual UM_8009C_059 1 3 Recommended Operating Conditions and Absolute Maximum Ratings Table 1 Recommended Operating Conditions Parameter Rating Supply Voltage Vpc 2 7 to 6 5 VDC Supply Voltage Vos 4 4 to 5 5 VDC Supply Voltage Vgar 4 0 to 6 5 C Ambient Operating Temperature 40 C to 85 C Table 2 Absolute Maximum Ratings Parameter Rating Supply Voltage Vous 0 5 to 6 6 VDC Supply Voltage Vgar 0 5 to 6 6 VDC Supply Voltage Vpc 0 5 to 6 6 VDC Input Voltage for Digital Inputs 0 3 to Vpp 0 5 VDC Storage Temperature 60 to 150 C Pin Voltage except card interface 0 3 to Vpp 0 5 VDC Pin Voltage card interface 0 3 to Vcc 0 3 VDC Pin Voltage LIN pin 0 3 to 6 5 VDC ESD Tolerance Card interface pins 6 kV ESD Tolerance Other pins 2 kV Pin Current 200 mA Operation outside these rating limit
7. Demo Board Top Signal Layer 16 Figure 8 7358009C Demo Board Middle Layer 1 Ground Plane cnn 16 Figure 9 73S8009C Demo Board Middle Layer 2 Supply Plane naar cnnnannn nn 17 Figure 10 7358009C Demo Board Bottom Signal Layer 17 Tables Table 1 Recommended Operating Conditions 6 Table 2 Absolute Maximum Ratings terra nn n cnn nn cnn nan nr nn cnn nr rra nennen nennen rines 6 Tabl 3 J4 Pin Desenptions ebe oerte taedet iE EUREN EUREN EE be gege ee 7 Table A Pin Deseriptions ieee Son Soa atos PA 8 Table 5 7388009C Demo Board Description cnn annnn nn cnn nan rr nan rn rn cnn 10 Table 6 73S8009C Demo Board Bill of Materials no nannrrrn cnn narco nana rn 18 Table 7 73S8009C Demo Board Order Number 19 Rev 1 3 UM 8009C 059 73S8009C Demo Board User Manual 1 Introduction The Teridian Semiconductor Corporation 73S8009C Demo Board is a platform for evaluating the Teridian 73S8009C 32 pin QFN Smart Card Interface IC It incorporates the 73S8009C integrated circuit and it is designed to operate either as a standalone platform to be used in conjunction with an external microcontroller or as a daughter card to be used in conjunction with the 73512xxF evaluation platform 1 4 Package Contents 1 ON OFF eg o gt ZE oa AE a RG um ww RS x x Cater Dgo09cn9a1 MAYA REV 1 dal fe ki ka 3 I de Figure 1 73S8009C Demo Board The 73S8009C Demo Board Kit includes e
8. TECT 4 4 4 POLARITY JP6 VDD VDD 4 d SELECT 1 c12 co cit d JT 30pF 30pF 0 47uF 4 GND sa coin deo edel E Y Vr corasxc o V z 65220490 E E 26 oc9 E o J5 J6 Smart Card Connector SIM SAM Connector Figure 4 73S8009C Electrical Schematic 14 Rev 1 3 UM 8009C 059 73S8009C Demo Board User Manual 5 2 73S8009C PCB Layouts annm gge O 3P3 U mon m C4 CLKRSTVIC CONZOFE l gt gt TI 19 E L1 200 N E eli ETE RC um 2 7 qn duet We y 34 om a e roe gt PS nam Oo ca a gt m CB 4 Figure 6 7358009C Demo Board Bottom View Rev 1 3 15 73S8009C Demo Board User Manual UM_8009C_059 Figure 7 7358009C Demo Board Top Signal Layer Figure 8 7358009C Demo Board Middle Layer 1 Ground Plane 16 Rev 1 3 UM 8009C 059 73S8009C Demo Board User Manual Figure 10 7388009C Demo Board Bottom Signal Layer Rev 1 3 17 73S8009C Demo Board User Manual UM 8009C 059 5 3 73S8009C Demo Board Bill of Materials Table 6 73S8009C Demo Board Bill of Materials Qnt Reference Part PCB Footprint dd Part Number Manufacturer 1 ICH 10 uF 805 PCC2225CT ND ECJ 2FB0J106M Panasonic 2 C2 C3 0 1 uF 603 PCC1762CT ND ECJ 1VB1C104K Panasonic 1 C4 4 7 uF 603 PCC2396CT ND ECJ 1VBOJ475K Panasonic 2 C9 C12 27 pF 603 Rai DE ECJ 1VC1H270J
9. bends in the trace If possible keep routing of the CLK trace to one layer avoid vias to other layers Keep CLK trace away from other traces especially RST I O and VCC Filtering of the CLK trace is allowed for noise purposes Up to 30 pF to ground is allowed at the CLK pin of the smart card connector Also the zero O series resistor R7 can be replaced with a small resistor for additional filtering no more than 100 Q e Keep VCC trace as short as possible Make trace a minimum of 0 5 mm thick Also keep VCC away from other traces especially RST and CLK e Keep RST trace away from VCC and CLK traces Up to 30 pF to ground is allowed for filtering e Keep 0 1 uF close to VDD pin of the device and directly take other end to ground e Keep 0 1 uF and 10 uF close to VPC pin of the device and directly take other end to ground e Keep 4 7 uF close to VP pin of the device and directly take other end to ground e Keep 0 47 uF close to VCC pin of the smart card connector and directly take other end to ground 4 2 Optimization for Compliance with EMV Default configuration of the Demo board contains a 27 pF capacitor C12 from the CLK pin of the smart connector to ground and a 27 pF capacitor C13 from the RST pin of the smart connector to ground These capacitors serve as filters for CLK and RST signals in the case of long traces or test equipment perturbations The capacitor on CLK reduces ringing on the trace reduces coupling to other traces an
10. d slows down the edge of the CLK signal The capacitor on RST helps the perturbation specification in a noisy environment The filter capacitors can be useful in the EMV test environment and have no effect on NDS testing C12 and C13 are represented on both schematic and BOM These capacitors are optional filter capacitors on the smart card lines CLK and RST respectively for each card interface These capacitors may be adjusted value not to exceed 30 pF or removed to optimize performance in each specific application PCB card clock frequency compliance with applicable standards etc 4 3 Power Supply Input Configurations 4 3 1 USB Power The USB configuration uses the power supplied by the VBUS 4 4 to 5 5 V and an optional VBAT input that automatically switches from the VBUS to VBAT when the VBUS power is removed This switch over is done smoothly and does not cause any disruption of the operation of the 73S8009C and the VDD output supply The operation of the ON OFF switch is overridden when VBUS is applied The 73S8009C and VDD output will always be active while the VBUS voltage is applied The ON OFF switch is enabled when running off VBAT When using this configuration the VPC input should not be connected to any other power source 4 3 2 Single Supply Power The single supply configuration should leave the VBUS and VBAT pins unconnected and only connect the power supply to VPC 2 7 to 6 0 V 12 Rev 1 3 UM 8009C 059 73S8009C D
11. e following 73S8009C documents are available from Teridian Semiconductor Corporation 73S8009C Data Sheet 7358009C Demo Board User Manual 9 Contact Information For more information about Teridian Semiconductor products or to check the availability of the 73580096 contact us at 6440 Oak Canyon Road Suite 100 Irvine CA 92618 5201 Telephone 714 508 8800 FAX 714 508 8878 Email scr support teridian com For a complete list of worldwide sales offices go to http www teridian com Rev 1 3 19 73S8009C Demo Board User Manual UM_8009C_059 Revision History Revision Date Description 1 0 5 22 2007 First publication 1 1 8 9 2007 Corrected schematic error 1 2 9 6 2007 Corrected pin number for OFF_ACK in pin description 1 3 2 10 2010 Formatted in the new Teridian style Added Section 1 1 Package Contents Added Section 1 2 Safety and ESD Notes Added Table 3 J4 Pin Descriptions Added Table 4 J2 Pin Descriptions Added Section 7 Ordering Information Added Section 8 Related Documentation Added Section 9 Contact Information Miscellaneous editorial corrections 20 Rev 1 3
12. emo Board User Manual 4 4 ON OFF Switch Operation The ON OFF switch uses a pushbutton to toggle between turning the 73S8009C on and off The switch input contains a debounce circuit for protection The 73S8009C defaults to the OFF state when the power source is applied When the 8009C is in the OFF state a switch closure turns on the 73S8009C When the 73S8009C is ON a switch closure does not turn off the 73S8009C by itself but it activates the OFF_REQ signal by setting it high The 73S8009C does not shut off until the OFF_ACK is set high The purpose of this sequence is to allow the host processor to perform any necessary shut down tasks before losing power When the host is finished it can set the OFF_ACK signal high to shut off the 73S8009C If there is no need for the host to perform any shutdown tasks the OFF_ACK pin can be left open and it follows the state of the OFF_REQ output by means of an internal resistor connection between the OFF_REQ and OFF_ACK pins When power is applied to VBUS the 73S8009C automatically turns on and the ON OFF switch is overidden However care must be taken as the ON OFF input is internally latched while the VBUS is applied When VBUS is removed the latched state of the ON OFF switch input dictates the state of the 73S8009C If the switch input was not closed the state of this latch will not change It will be in the same state before the VBUS power was applied If it has changed it holds the last toggled
13. gure 2 73S8009C Demo Board External Connectors Table 3 describes the pins for the J4 connector There is one power pin Pin 1 and one ground pin Pin 9 Table 3 J4 Pin Descriptions Pin Pin Name Function Sc Controls the tum on output voltage value and turn off of Vcc 2 CMDVCC3 3 RSTIN Controls the card reset signal 4 RDY Indicates when smart card power supply is stable and ready 5 OFF ACK Setting OFF_ACK high powers off all analog functions and disconnects the 73S8009C from Vegar or Vpc 6 OFF REQ mo ea te to the host system controller to turn 7 CS Chip Select active high 8 N C No Connect 9 GND Ground 10 VDD System interface supply voltage and supply voltage for companion controller circuitry Rev 1 3 7 73S8009C Demo Board User Manual UM_8009C_059 Table 4 describes the J2 connector pins Table 4 J2 Pin Descriptions Pin Pin Name Function 1 SCLK Clock source input 2 l OUC System controller data I O to from the card 3 SC4 System controller auxiliary data C4 to from the card 4 SC8 System controller auxiliary data C8 to from the card 5 OFF Interrupt signal to the processor Indicator of card presence and any card fault conditions 6 GND Ground 7 GND Ground 8 GND Ground 9 VPC IN Must be between 2 7 V and 6 5 V 10 VPC IN Must be between 2 7 V and 6 5 V Connections should be made in this order
14. itch input of the 73S8009C is used In this demo board the switch is nominally open The jumpers can be set in one of two ways 1 Default setting Use of PRES JP5 must be set to PRES and JP6 set to VDD 2 Alternative use Use of PRES JP5 must be set to PREB and JP6 set to GND Note see board errata in the appendix for JP6 J5 Smart Card Connector Smart card connector When inserting a card credit card size format contacts must face up 17 JP7 CS Disable CS Disable Jumper Insertion of jumper disables the 73S8009CN The state of the CMDVCCS CMDVCC5 and RSTIN inputs will be latched and the l OUC AUX1UC and AUX2UC are tri stated The OFF and RDY outputs are also tri stated 19 TP9 Vp Test Point Test point to monitor the internal intermediate voltage regulator This regulator output takes the VPC voltage and step it up to more than 5 V if necessary as the input source for the VCC and VDD output regulators 20 J3 Board VPC_IN supply smart card data signals and OFF Connector that supplies the VPC input supply voltage the smart card data interface signals and the OFF interrupt output Rev 1 3 11 73S8009C Demo Board User Manual UM 8009C 059 4 Design Considerations 4 1 General Layout Rules Follow these layout rules e Route I O and auxiliary signals away from card interface signals e Keep CLK trace as short as possible and with minimal
15. s may cause permanent damage to the device ESD testing on Card pins is HBM condition 3 pulses each polarity referenced to ground 1 4 Notes When Using a 73S12xxF Evaluation Board The 73S12xxF Evaluation Board has two power supplies 3 3 V and 5 0 V Normally the 5 0 V supply is tied to VPC IN on the 73S8009C board The 73S8009C can supply the 3 3 V to the remainder of the system by configuring the jumpers accordingly The 73S8009C VDD output can be disconnected from the rest of the evaluation board if desired and the 3 3 V supply on the 73512xxF Evaluation Board can be used See the jumper descriptions for more details Rev 1 3 UM 8009C 059 73S8009C Demo Board User Manual 2 Connections This section describes the 73S8009C Demo Board external connectors All the digital signals and power supply connections are made through 10 pin header connectors labeled J2 and J4 in Figure 2 Mous Power z Veat Power F Supply e o se a 4 4V to 5 5V 0V to gt gt 5V Typ 200mA 200mA Vbo Power EJE EUNETAN Supply Output Hs Eom FEFFEE 3 3V Typ JP3 y no m C4 CLK RSTVCC 40mA Max SCLK ONZOFF gt I gt gt IHE 10 VDD L1 200 D SCA SS et SCH af De 2 bg cs TeS D GND J2 R7 q OFF ACK GND cite a Ji q roy GND VP ag RSTN E peoo9cn9a 1 MN o OMDVCOS REV 1 A Vpc Power n wa M Supply JP7 E E Sm CBI D 2 7V to 6 0V a 6 JP4 q et Dm E a 5V Typ SL IS z al l E 200mA Fi
16. st be 2 and 2 should only y ri petween 2 7 3 be connected when and 6 5V 4 3 3V is not sourced T 1 5 from the mating H L board if a dad sZ pplicable Ut E JP3 VPCIN GER eo LONDOzZORr 9 EE Jas Ea Ww 166598258 is S1 Su 10UC e TSM 110 O1 L SV IUS S iouc onjore L i e AUX2UC 3 AUXIUC VBUS 22 10 CMDVOCS EE Io AUX AUXQUC _ E cunuccs 1 He Sie 29 CMDVCCS auxi Hat AC SS CMDVCC3 Sieg T ASTIN e CMDVCC3 AUX2 Hg VCC RSTIN 3 CLKIN 7 RSTIN vec H AST RDY 4 RDY BI CLKIN x o RST 47 OFF_ACK 5 RDY Q GND OFF REO 6 F no n8 HB cs 7 K dee S Ru Ru USR7 8 oroodaa o Es DNI DNI GND E 7388009 C SA 3 3V 10 erste Es E SSM 110 L SV R7 0 RS to R13 and C36 to be CLK E 4 placed within 1cm of J4 3 1 ins t 4 2 3 4 OFF ACK Rit R12 S Es OFF REQ 4 7UF Rd Rd 7 4 US e SE DNI DNI 8 9 JP7 0p Y s 4 TSM 110 01 L SV at i 1 a Disable 2 Ri Ru Ke DNI TP3 4 dl Jl and J3 are placed on the bottom J2 and J4 E vec are placed on the top side TP4 Ri H Ma Jl and J3 must be aligned with J8 and J9 on the Rd 1 0 a 4 1 1121 evaluation board 1121T8 respectivly in DNI 2 RST order for this board to be stacked on it TF6 3 J TPZ c8 iL 1 Jl must be aligned with J2 and J3 must be TS 1 2 CLK aligned with J4 in order for this daughter JP5 RES PUR TP3 to TP8 C9 Cll and board to be stacked on another 1 PRES V T8 C12 are to be placed 2 1 very close to the pads 3 T 2 c4 of J5 PRES i CARD DE
17. t points for each respective smart card 8 TP5 RST signal The pin label name is the respective signal 9 TP3 VCC i e VCC CLK and the other pin is GND 12 TP4 1 0 13 TP6 C8 10 J4 Board 3 3 V Connector that either gathers or supplies the 3 3 V supply and digital supply It includes the 73S8009C host control control signals signal pins RDY CS OFF REQ OFF ACK CMDVCC5 CMDVCCS and RSTIN 11 J6 Smart Card SIM SAM smart card format connector Connector Note that J6 is wired in parallel to the smart card connector J5 underneath the PCB J5 and J6 are never to be used at the same time 14 JP4 VDD Select When the jumper is inserted the 7388009C VDD output is connected to the 3 3 V power plane When using in conjunction with a 73812xxF Evaluation Board or other host it supplies the 3 3 V source on the on that platform if it is so configured Caution must be taken as damage could occur if the 73812xxF Evaluation Board or host is sourcing 3 3 V with this jumper inserted Removal of the jumper provides proper isolation with any host platform Rev 1 3 UM 8009C 059 73S8009C Demo Board User Manual ltem Figure 3 Electrical Schematic amp PCB Silkprint Reference Name Use 15 18 JP6 JP5 Card Polarity detect select The setting of these two jumpers depends on the type of smart card connector used whether switch is nominally open or closed and which of the card presence sw

73S8009C Demo Board User Manual

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