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1. FB BE23 16 b FB CS4 b 16 PTC17 DISABLED PTC17 CAN1 TX UART3 TX a FB TSIZO NFC CEO b FB_BE31_24_b 17 PTC14 DISABLED PTC14 UARTA_RX FB AD25 18 PTC15 DISABLED PTC15 UART4 TX FB AD24 19 PTC12 DISABLED PTC12 UART4 RTS b FB AD27 FTM3_FLTO 20 PTC13 DISABLED PTC13 UARTA_CTS_b FB_AD26 21 PTC10 ADC1 SE6b ADC1 SE6b PTC10 I2C1 SCL FTM3 CH6 I250 RX FS FB_ADS 1251 MCLK zu a 7 NFC_DATA2 PTC11 FB RW b 22 PTC11 ADC1 SE7b ADC1 SE7b LLWU P11 12C1_SDA FTM3_CH7 250 RXD1 NFC WE ADC1 SE4b ADC1 SE4b FB AD7 2 a 3 PTC8 CMPO IN ao PTC8 FTM3_CH4 I2S0 MCLK NIM ADC1 SE5b ADC1_SE5b 250 BN FB_AD6 BIE CMPO_IN3 CMPO_IN3 Ele EUR BCLK NFC_DATA3 MZR 25 CLK 26 14 un Default ALTO ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 1 GND 2 V 3 PTC7 CMPO_IN1 CMPO_IN1 PTC7 SPIO_SIN USB SOF OUT I2S0 RX E Es ne zn NFC_DATAS PTC6 1250_RX_ FB_AD9 4 PTC6 CMPO_INO CMPO_INO u SPIO SOUT PDBO EXTRG K NEC DATAE 1250_MCLK 5 PTC5 DISABLED PTC5 SPIO SCK LPTMRO ALT2 1250_RXDO a CMPO_OUT 251 TX FS 4 NFC_DATA7 En 6 PTCA DISABLED PTCA SPIO_PCSO UART1_TX FTMO_CH3 FERIEN CMP1_OUT 251 TX BCLK z NFC_DATA8 gt RTE PTC3 7 PTC3 CMP1_IN1 CMP1_IN1 np SRi UART1_RX FTMO_CH2 CLKOUT 1250_TX_ BCLK ADCO SE4b ADCO SE4b 8 PTC2 CMP1_INO CMP1_INO PTC2 SPIO_PCS2 UART1 CTS b FTMO CH1 NA NE 1250_TX_FS TSIO_CH15 TSIO_CH15 ADCO SE15 ADCO SE15 PTC1 9 PTC1 SOM 2 au pe SPIO_PCS3 UART1 RTS b FTMO_CHO FB AD13 1250_TXDO ADCO SE14
2. The Bilbao Bizkaia minimodule can be programmed using a specialized interface such as the SEGGER J Link 6 which is the most widely used line of debug probes available today due to impressive performance extensive feature set large number of supported CPUs and compatibility with all popular development environments With up to 3 MBytes s download speed to RAM and record breaking flashloaders as well as the ability to set an unlimited number of breakpoints n flash memory of MCUs the J Link Fig 8 debug probes are undoubtedly the best choice to optimize debugging and flash programming experience KE MM BEE a a Co Ee ti lelelelolalolslelolslelelalelelolelololololol ls Fig Bilbao Bizkaia minimodule connected to J Link EDU 10 In order to start programming the minimodule has to be connected to the programmer using an IDC connector The module uses a 10 pin IDC socket and J Link uses a 20 p n IDC socket This dictates the need to use some form of an adapter as shown in Fig 8 J Link has to be connected to a PC running software compatible with Freescale Kinetis MCUs such as CodeWarrior Development Studio 3 at least version 10 X which features e Eclipse IDE e Build system with optimizing C C compilers for RS08 HCS08 ARM and ColdFire processors e Extensions to Eclipse C C Development Tools CDT to provide sophisticated features to troubleshoot and repair embedded applications Another useful tool when beginning to
3. BILBAO BIZKAIA minimodule SS 399 SE 2 A 2 Y PAD eh BO er ml ro 4 em 07 na in e z EN a e t lt o 5 all E Wroc aw University of Technology Wroctaw 17 12 2013 The module along with the documentation have been developed by Mateusz Cholewinski Michal Dziergwa Pawel Kaczmarek Jan Kedzierski Marek Wnuk Department of Fundamental Cybernetics and Robotics Wroclaw University of Technology Wroclaw 2013 The documentation consists of this manual and a project created using EAGLE ver 6 5 0 software from CadSoft This project can be obtained from the authors of the module It can be used for educational purposes only EAGLE www cadsoft de Bilbao is a city in Spain the capital of the province of Biscay The population proper is just over 372 000 Nowadays Bilbao 15 3 vigorous service city that is experiencing an ongoing social economic and aesthetic revitalisation process started by the iconic Bilbao Guggenheim Museum and continued b Y Infrastructure Investments Contents 1 A 5 ee TEE 5 3 FEGUIESOLTMKCOOPSJTZYLO EE 6 Aa COCK RTE de dE EE 7 5 SCHEMIAUCANAASSEMDI a 8 O Ge ee 10 3 4444 o COOP a E TO 10 8 EConmecio sana SO sas 12 o ehe ee 17 1 Introduction The minimodule described in this document is based on a 32 bit MK60FX512 microcontroller from Freescale s Kinetis fam ly 1 It co
4. ADC3 SE9 TSIO_CH6 TSIO_CH6 ADCO SE8 ADCO SE8 ADC1 SE8 ADC1 SE8 RMIIO_MDI 30 PTBO ADC2 SE8 ADC2 SE8 PTBO DCH 56 FTM1_CHO one FTM1_QD_ PHA ADC3 SE8 ADC3 SE8 TSIO_CHO TSIO_CHO 31 PTA29 ADC2 SE12 ADC2 SE12 PTA29 ULPI DATA7 MIIO COL FB A24 32 PTA28 ADC2 SE13 ADC2 SE13 PTA28 ULPI DATA6 MIIO TXER FB A25 33 PTA27 ADC2 SE14 ADC2 SE14 PTA27 ULPI_DATA5 MIIO_CRS FB_A26 34 PTA26 ADC2 SE15 ADC2 SE15 PTA26 ULPI DATA4 MIIO_TXD3 FB A27 35 PTA25 CMP3_IN5 CMP3_IN5 PTA25 ULPI_DATA3 MIIO_TXCLK FB A28 36 PTA24 CMP3 IN4 CMP3 IN4 PTA24 ULPI DATA2 MIIO_TXD2 FB A29 37 RESET RESET b RESET b 38 PTA19 XTALO XTALO PTA19 FTM1 FLTO FTM_CLKIN1 LPTMRO_ ALT1 39 PTA17 ADC1 SEI ADC1 SE17 PTA17 SPIO SIN UARTO RTS b GE 1250_MCLK UARTO CTS b RMIIO TXDO Ji CTS amp O PTA16 CMP3 IN2 CMP3 IN2 PTA16 SPIO SOUT or one 1250_RX_FS 1250_RXD1 Table 4 SVR Connector 15 41 42 43 44 45 46 47 48 PTA15 PTA14 PTA13 PTA12 PTA11 PTA10 PTA9 PTA8 CMP3 IN1 CMP3 INO CMP2 IN1 CMP2 INO ADC3 SE15 ADC3 SE4a ADC3_SE5a ADCO SE11 CMP3 IN1 CMP3 INO CMP2 IN1 CMP2 INO ADC3 SE15 ADC3 SE4a ADC3_SE5a ADCO SE11 PTA15 PTA14 PTA13 LLWU_P4 PTA12 PTA11 PTA10 PTA9 PTA8 SPIO_SCK SPIO_PCSO CANO_RX CANO TX ULPI DATA1 ULPI DATAO ULPI STP ULPI NXT UARTO RX UARTO TX FTM1 CH1 FTM1 CHO FTM2 CH1 FTM2 CHO FTM1 CH1 FTM1 CHO 16 RMIIO TXEN MIIO_TXEN RMIIO_CRS_ RMIIO_RXDO MIIO_RXDO RMI
5. OSCERCLK for on chip peripherals and OSC32KCLK On Bilbao Bizkaia minimodule OSC is omitted and an external 50 MHz crystal oscillator Q1 and a small set of necessary components 15 used as a clock source e RTC Oscillator RTC OSC provides a clock source for the Real Time Clock RTC module It is used in conjunction with an external 32 kHz crystal Q2 The following are a few of the more common clock configurations for this device Option Option 2 Core clock 120 MHz 150 MHz System clock 120 MHz 150 MHz Bus clock 60 MHz 75 MHz FlexBus clock 40 MHz 50 MHz Flash clock 20 MHz 25 MHz 5 Schematic and assembly Module schematic is presented on page 9 The placement of components on top and bottom side of the module is shown in Fig 6 and Fig 7 respectively The components needed to assemble the module are listed in Table 1 Components mounted on the board include MK60FX512VL015 microcontroller in LQFP144 package U1 a 50Mhz crystal oscillator 01 along with accompanying components RI R2 68 Q an 32kMHz oscillator Q2 power supply filtering capacitors C1 C2 C3 C18 100nF C5 22uF power supply filtering chokes L1 L7 100MHz micro USB B connector along with accompanying components R4 R5 33Q and a safety diode D1 Table 1 Bill of materials Qty Parts Value Package 1 USB SMD 1 PWR LED0603 1 J LINK ML10 2 SVL SVR 1 SVT 7 LI L2 L3 L4 L5 L6 L7 100MHz M0805 12 CI CZ C3 C4
6. ADCO SE14 FB AD14 10 PTCO O oda PTCO SPIO 0654 PDBO EXTRG NFC DATAJI 120 1701 FB AD28 11 PTB23 DISABLED PTB23 SPI2 SIN SPIO PCS5 NEC DATAJ2 SMP3 0UT FB AD29 12 am PTB22 DISABLED PTB22 SPI2_SOUT NFC DATA13 lt MP2_OUT FB_AD30 13 z PTB21 ADC2 SE5a ADC2_SE5a PTB21 SPI2_SCK NEC parara CMP1OUT 14 PTB20 ADC2_SE4a ADC2_SE4a PTB20 SPI2 PCSO PP ADSI CMPO_OUT ADC2_SE4a gt NFC_DATA15 15 PTB19 TSIO CH12 TSIO_CH12 PTB19 CANO_RX FTM2_CH1 1250_TX_FS FB OE b FTM2 OD PHB 16 PTB18 TSIO CH11 TSIO CH11 PTB18 CANO TX FTM2 CHO O FB AD15 FTM2 OD PHA 17 PTB17 TSIO CH10 TSIO CH10 PTB17 SPI1 SIN UARTO TX 1251 TXD1 FB AD16 EWM OUT b 18 PTB16 180 CH9 150 CH9 PTB16 SPI SOUT UARTO RX 251 TXDO FB AD17 EWM IN 19 PTB11 ADC1 SE15 ADC1 SE15 PTB11 SPI SCK UART3 TX 251 TX FS FB AD18 FTMO FLT2 20 PTB10 ADC1 SE14 ADC1 SE14 PTB10 SPI1_PCSO UART3_RX ne FB AD19 FTMO FLT1 21 PTB9 DISABLED PTB9 SPI1 PCS1 UART3 CTS b FB AD20 22 PTB8 DISABLED PTB8 UART3 RTS b FB AD21 23 PTB7 ADC1 SE13 ADC1 SE13 PTB7 FB AD22 24 PTB6 ADC1 SE12 ADC1 SE12 PTB6 FB AD23 25 PTB5 ADC1 SE11 ADC1 SE11 PTBS ne FTM2_FLTO 26 0184 4061 SE10 4061 SE10 5184 2 FTM1 FLTO ADCO SE13 ADCO SE13 UARTO CTS bh ENETO 1588 27 rx PTBA TSIO_CH8 TSIO_CH8 A EGO DA UARTO COL b TMR1 ak ADCO SE12 ADCO SE12 ENETO 1588 2 8 PTB2 EE SIGN PTB2 I2C0_SCL UARTO_RTS_b poe FTMO FLT3 ADCO SE9 ADCO SE9 ADC1 SE9 ADC1 SE9 29 0181 4062 569 4062 569 5181 DCH 504 FTM1 CH1 oc FTM1 OD PHB ADC3 SE9
7. interface TSI General purpose input output e Analog modules Four 16 bit SAR ADCs Programmable gain amplifier PGA up to x64 integrated into each ADC Two 12 bit DACs Four analog comparators CMP containing a 6 bit DAC and programmable reference input Voltage reference e Timers Programmable delay block Two 8 channel motor control general purpose PWM timers Two 2 channel quadrature decoder general purpose timers IEEE 1588 timers Periodic interrupt timers 16 bit low power timer Carrier modulator transmitter Real time clock Communication interfaces Ethernet controller with MII and RMII interface to external PHY and hardware IEEE 1588 capability USB high full low speed On the Go controller with ULPI interface USB high full low speed On the Go controller with on chip high speed transceiver USB full low speed On the Go controller with on chip transceiver USB Device Charger detect Two Controller Area Network CAN modules Three SPI modules Two I2C modules Six UART modules Secure Digital host controller SDHC Two I2S modules A Clock Distribution The Multipurpose Clock Generator MCG 1 module controls which clock source is used to derive the system clocks The clock generation logic divides the selected clock source into a variety of clock domains including the clocks for the system bus masters system bus slaves and flash memory The clock generation logic also implements module specific cl
8. r C9 C8 C6 C4 L C2 a Es PICI he BS 100n 100n 100n 100n 100n 100n 100n BGARZDM 2 PGA3 DP ADC3 DPO ADC2 DP3 ADC1 DP1 PTC2 GE GND GND GA3_ PGA3 DM ADC3 DMO ADC2 DM3 ADC1 DM PTC3 LLWU P7 C3 EN z PTC4 LLWU P8 PTC4 GND GND GND GND GND GND GND PTC5 LLWU_P9 PICS bi PTC6 LLWU_P10 PRZ USBO_ PTC7 IC USBO DM PTC8 PTC8 207 USBO DP PTC9 PIC9 USBO_DM PTC10 PTC10 g PTC11 LLWU_P1 BIC O u PTC12 PTC12 PTC13 PTC13 x PTC14 PTC14 RESET ru zi PTC15 PIC15 RESET_B PTC16 PTC16 PTC17 BICIE ki PTC18 IC18 5 5 PTC19 PTC19 GND aN PTDO LLWU_P12 PTDO L5 L3 T Sje 41 EXTALS2 TD1 PIDI Ee XTAL32 PTD2 LLWU Pra ETEA Jets cra cl c1 100MHz PIDA RIBAH PID5 ee bi JS lu 2 PTD6 LLWU_P15 ETDS Deg a TD7 EI 100MHz SNE vss1 TD8 1198 gt 17 au PID9 gt e VSS2 D9 44 yss3 PTD10 PID10 PA 57 VSS4 PTD11 PTD11 4 VSS5 PTD12 PTD12 VSS6 PTD13 PTD13 100n 7 vss7 PTD14 PTD14 cig INH VDD VSS8 PTD15 PID15 R1 134 1559 vss OUT E PTEO ei 68 PTE1 LLWU_PO R3 34 yssa PTE2 LLWU_P1 BIES GND E 3 PTE3 68 i PTE4 LLWU_P2 PTE4 CLK 1 VSSUSB PTE5 PTES JA PTE6 RE PTE7 PTE8 _ PTE8 GND B PTE9 Close J1 to supply from USB PTE10 PTE10 PTE11 Ge PTE12 TE12 PTE24 PTE24 PTE25 PTE25 PTE26 PTE26 PTE27 PTE27 PTE28 PTE28 MK60FX512VLQ15 M Cholewinski M Dziergwa P Kaczmarek J Kedzierski Wroclaw University of Technology TITLE K6B_module BILBAO Mini ce inimodule Bilbao is a city in Spain the capital of the prov
9. 2 ND DDA R H R A ADCO AD DA DA PGAO DPPGAO DM PGA DPPGA A DM USBO DP USBO DM RESET V CLK SVL 1 2 1 2 OO OO 38 38 3 N U1 K60 94 GU 35 510 11 12 11 12 5 T voni STAG BO 81 iso Su EN e TAR 189 616 185 316 a3 175 618 15 818 Bali PTAS 195 620 195 620 70 21 22 21 22 4 VDD5 PTA4 LLWU_P3 20 0 SO Of VDD6 PTA5 OO OO 108 vob TAG 258 92 288 92 1227 pe STA 218 92 218 92 SE ma 39 05 zo 05 VDDA SAY 339 Q34 339 934 31 vDDA PTA11 359 O36 385 036 VREFH 37 38 37 38 PTA12 OO OO VREFL PTA13 LLWU_P4 335 01 395 040 32 VREFH PTA14 445 oz 419 04 4 33 VREFL PTA15 ZO on 20 on PTA16 O O OO gt SA Ze 48 Ze 98 L42 vBAT PTA18 PTA19 Bat PTA24 5V_USB 4 22 VREGIN PTA25 PTA25 PTA26 PTA26 i PTA27 PTA27 VOUT33 VOUT33 PTA28 PTA28 S PTA29 PTA29 Our A 37 VREF_OUT CMP1_IN5 CMPO_IN5 ADC1_SE18 PTBO LLWU_P5 Br PTB1 ADCO GND 30 ADCO SE16 CMP1 IN2 ADCO SE21 PTB3 PTB3 ADC1 ADC1 SE16 CMP2 IN2 ADC0 SE22 PTB4 Grae PTB5 i PTB6 PTBG DACO 3 DACO_OUT CMP1_IN3 ADCO_SE23 PTB7 PTB7 DAC1 DACH OUT CMPO IN4 CMP2 IN3 ADC1 SE23 PTB8 SETI amp PTB9 E PTB10 PTB10 100MHz d PGAO DP 5 PGAO_DP ADCO_DPO ADC1_DP3 PTB11 PTB11 V PGAO_DM PGAO_DM ADCO_DMO ADC1_DM3 PTB16 PTB16 L1 PTB17 PTB17 PGA1_DP 29 Se 51819 ee PGA1 DP ADC1 DPO ADCO DP3 PTB19 m PGA1 DM 30 PGAT DM ADC1 DMO ADCO DM3 PTB20 BEN 22uF PTB21 a PGA2 DP ADC2 DPO ADC3 DP3 ADCO DP1 PTB23 2 PGA2 DM 24 PGA2 DM ADC2 DMO ADC3 DM3 ADCO DM p
10. ADC3 SE17 ADC3 SE17 PTE12 1250_TX_ BCLK FTM3 CH7 19 V OUT33 VOUT33 VOUT33 20 USBO DM USBO DM USBO DM PGA2 DP PGA2 DP ADC2 DPO ADC2 DPO 21 PGA2 DP ADC3 083 ADC3 DP3 ADCO DP1 ADCO DP1 22 5V USB PGA3_DP PGA3_DP ADC3_DPO ADC3_DPO 23 PGA3_DP Anc 083 ADC2_DP3 ADC1 DP1 ADC1 DP1 PGA2 DM PGA2 DM ADC2_DMO ADC2 DMO 24 PGA2 DM vc DM3 ADC3 DM3 ADCO DM1 ADCO DM1 PGAO DP PGAO DP 25 0640 DP ADCO DPO ADCO DPO ADC1 DP3 ADC1 DP3 PGA3 DM PGA3 DM ADC3 DMO ADC3 DMO 26 PGA3_DM vc DM3 ADC2 DM3 ADC1 DM1 ADC1 DM1 PGA1 DP PGA1 DP 27 8641 DP ADC1 DPO ADC1 DPO ADCO DP3 ADCO DP3 PGA1 DM PGA1 DM 28 PGAO DM ADC1 DMO 4061 DMO ADCO DM3 ADCO DM3 ADC1 SE16 ADC1 SE16 29 ADC1 CMP2 IN2 CMP2 IN2 ADCO SE22 ADCO SE22 PGA1 DP PGA1 DP 30 8641 DM ADC1_DPO ADC1 DPO ADCO DP3 ADCO DP3 DACO OUT DACO OUT 31 DACO CMP1 IN3 CMP1 IN3 ADCO SE23 ADCO SE23 ADCO SE16 ADCO SE16 32 ADCO CMP1 IN2 CMP1 IN2 ADCO SE21 ADCO SE21 Em ADCO SE17 ADCO SE17 PTE24 CAN1 TX UART4 TX 251 TX FS EWM OUT b 251 RXD1 EXTAL1 EXTAL1 DAC1 OUT DAC1 OUT CMPO IN4 CMPO IN4 Se APA CMP2_IN3 CMP2_IN3 ADC1_SE23 ADC1_SE23 35 PTE26 ADC3_SE5b ADC3_SE5b PTE26 a UART4 615 b 12S1_TXDO RTC CLKOUT USB CLKIN ADCO SE18 ADCO SE18 36 PTE25 a TA PTE25 CAN1_RX UART4_RX 251 TX BCLK EWM IN 251 TXD1 Table 2 SVL Connector 13 37 PTE23 ADC3_SE7a ADC3_SE7a PTE28 38 PTE27 ADC3_SE4b ADC3_SE4b PTE27 UART4 RTS b 251 MCLK RMIIO_RXER CMP2_ 39 PTA5 DISA
11. BLED PTA5 USB_CLKIN FTMO_CH2 MIIO_RXER OUT 1250_TX_ BCLK JTAG_TRST_b NMI_b PTA4 i 0 PTA4 EZP CS b TSIO_CH5 LLWU_P3 FTMO_CH1 NMI_b 41 PTA7 ADCO_SE10 ADCO_SE10 PTA7 ULPI_DIR FTMO_CH4 251 RX BCLK TRACE_D3 42 PTA6 ADC3_SE6a ADC3_SE6a PTA6 ULPI_CLK FTMO_CH3 I251_RXDO en 43 VREFL VREFL VREFL 44 VREFH VREFH VREFH 45 VSSA VSSA VSSA 46 VDDA VDDA VDDA 47 V 48 GND Table 3 SVT Connector jaa Default ALTO ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 FB_A18 8 z PTD10 DISABLED PTD10 UART5_RTS_ b NEC RE SDHCO 2 PTD11 DISABLED PTD11 SPI2 PCSO UART5 CTS b CLKIN FB A19 FB A16 3 PTD8 DISABLED PTD8 I2C0 SCL UART5 RX NEC CLE FB A17 4 PTD9 DISABLED PTD9 I2C0 SDA UART5 TX NEC ALE PTD6 5 PTD6 ADCO SE7b ADCO SE7b LLWU P15 SPIO PCS3 UARTO RX FTMO_CH6 FB_ADO FTMO_FLTO 6 PTD7 DISABLED PTD7 CMT_IRO UARTO_TX FTMO_CH7 FTMO_FLT1 7 PTD4 UARTO_CTS_b FB_AD1 8 PTD5 ADCO_SE6b ADCO_SE6b PTD5 SPIO_PCS2 UARTO COL b FTMO_CH5 NFC_DATAO EWM_OUT_b 9 PTD2 DISABLED PTD2 SPIO SOUT UART2_RX FTM3_CH2 FB AD4 I251_RX_FS 10 PTD3 DISABLED PTD3 SPIO_SIN UART2_TX FTM3_CH3 FB_AD3 251 RX BCLK 11 PTDO DISABLED PTDO SPIO PCSO UART2 RTS b FTM3 CHO FB ALE 1251 RXD1 12 PTD1 ADCO_SE5b ADCO_SE5b PTD1 SPIO_SCK UART2_CTS_b FTM3_CH1 FB CSO b 1251 RXDO ADCO_SE5b FB_TBST_b 13 PTC18 DISABLED PTC18 UART3 RTS b GO FB_CS2_b NFC_CE1_b FB_BE15_8_b ENETO_1588 FB_CS3_b 14 PTC19 DISABLED PTC19 UART3_CTS_b _TMR3 FB BE7 O b FB TA b FB CS5 b 15 PTC16 DISABLED PTC16 CAN1 RX UART3 RX a FB_TSIZ1 NFC_RB
12. C6 CS C9 100nF C0603 C10 C11 C13 C17 C18 1 C15 10nF C0603 2 C14 C16 luF C0603 1 C12 22uF SMCB 1 R2 Ik R0603 2 R4 R5 33 R0603 2 RI R3 68 R0603 1 R6 510 R0603 1 QI 50MHz DXO 57 1 Q2 32768Hz 2 POLE SMD 1 Ul MK60FX512VLQ15 LQFP144 1 DI SOD523 1 JI N A y Y e s Description micro USB connector LED 2x5 connector 2x24 pin header 2x13 pin header inductor capacitor capacitor capacitor polarized capacitor resistor resistor resistor resistor crystal oscillator crystal Freescale Kinetis K60 microcontroler schottky diode NOT A PART gt resistor capacitor LED ductor polarized capacitor diode crystal oscillator 2 pole crystal Freescale Kinetis K60 pin headers 2x5 connector micro USB connector 1 2 3 4 5 6 7 8 PTAIA PTA19 PTAIDA PTRIO PTRI16 D O PTD IO D d
13. IO_RXD1 MIIO_RXD1 MIIO_RXCLK MIIO_RXD2 MIIO_RXD3 1251_RX_FS 1250_RXDO 1250_RX_ BCLK 1250_TX_FS 1250_TXDO FTM2_QD_ PHB FTM2_QD_ PHA FTM1_QD_ PHB FTM1_QD_ PHA 1250_TXD1 FTM1 OD PHB FTM1 OD PHA TRACE DO TRACE D1 TRACE D2 Bibliography 1 K60 Sub Family Reference Manual K60P144M150SF3RM Freescale Semiconductor Inc 2011 2 K60 Family Product Brief K6OPB Freescale Semiconductor Inc 2011 3 CodeWarrior Development Studio for Microcontrollers V10 x Getting Started Guide Freescale Semiconductor Inc 2011 4 CodeWarrior for Microcontrollers V10 x Processor Expert User Manual Freescale Semiconductor Inc 2011 5 J Kedzierski M Wnuk Programowanie mikrokontrolera z rodziny Kinetis K40 w srodowisku CodeWarrior Development Studio Wroctaw 2013 6 J Link J Trace User Guide UM08001 SEGGER Microcontroller GmbH amp Co KG 2013 17
14. ama mama 4 Clock configurations 1 SIM_SCGC2 00000000 4004 mw d CRC DACO DAC DAC6bO ADC SEA ee SIM_SCGC3 00000000 4004 DACI DMA nae SEE a Clack configuantion Z ET we Very low power mode Disabled SIM_SCGC4 F0100030 4004 ET uxt FB ae gt SIM_SCGCS 00040380 4004 PIT DMAMI ENET EWM FIFE us 7 Tr kdo configuration 0 SIM_SCGC6 40000001 4004 c FIMO FTM2 FTM3 260 e B o A z SIM_SCGC7 00000007 4004 Wen HCH 1250 1251 LPTMRO MCM we Q aan er 20 97 tni gt MCGIRCLK clock MH 0 032768 MHz WDOG STCTRIH 0103 4005 e PGA zeien MCG CI 4006 o mm A OSCERCLK clock MH 0 MHz System Oscillator 0 is MCG_C UND a ak Ci ck Tbe O MHz lt e is OG CZ PGA PGA PIT PTA PTR vese ERCLK32K clock kHz O MHz System oscillator 0 is MCG C4 4006 vom PTC PTD PTE RNG RTC ADC SEP O MCGFFCLK kHz 16 384 kHz MCG 0 A s ce ml System docks MCG C5 4006 rg SOHC SPO SPH SPI2 SysTick ANA 4 a pub C lock prescaler Auto select 1 MCG_C6 4006 end rap UARTO UARTI UART2 UART3 CR 90 4006 SZE p Core clock 20 97152 20 97152 MHz LLW U F1 00 4007 AD UART4 UARTS USBO USBDCD USBHS Bus clock prescaler Auto select 1 v 1 1 5 77 772 VREF WDOG ACHEN Bus clock 20 97152 20 97152 MHz LLWU_F2 00 400 ser ADCS ES m External clock prescale Auto select 2 4007 PA DNA MA gt clock presc gt ms ec 2
15. er Memories Communication Interfaces 3 Features of MK60FX512VLQ15 e Operating Characteristics Voltage range 1 71 to 3 6 V Flash write voltage range 1 71 to 3 6 V Temperature range ambient 40 to 105 C e Performance Up to 150 MHz ARM Cortex M4 core w th DSP instructions delivering 1 25 Dhrystone MIPS per MHz e Memories and memory interfaces Up to 1024 KB program flash memory on non FlexMemory devices Up to 512 KB program flash memory on FlexMemory devices Up to 512 KB FlexNVM on FlexMemory devices 16 KB FlexRAM on FlexMemory devices Up to 128 KB RAM Serlal programming interface EzPort FlexBus external bus interface NAND flash controller interface Clocks 3 to 32 MHz crystal oscillator 32 kHz crystal oscillator Multi purpose clock generator e System peripherals Multiple low power modes to provide power optimization based on application requirements Memory protection unit with multi master protection 32 channel DMA controller supporting up to 128 request sources External watchdog monitor Software watchdog Low leakage wakeup unit e Security and integrity modules Hardware CRC module to support fast cyclic redundancy checks Hardware random number generator Hardware encryption supporting DES 3DES AES MD5 SHA 1 and SHA 256 algorithms 128 bit unique identification ID number per chip e Human machine interface Low power hardware touch sensor
16. ince of Biscay The population proper is just over 372 000 Nowadays Bilbao is a vigorous service BILBAO Document Number REV city that is experiencing an ongoing social economic and aesthetic revitalisation process started by the iconic Bilbao Guggenheim Museum BIZKAIA and continued by infrastructure investments Date 2813 12 12 17 15 54 Sheet 1 1 1 2 3 4 5 6 7 8 00000000000000000 00000000000000000 OO ki a Close J1 to supply from UsB O O 00 00 oo slej oo OO 6 00 oor 8 5 8 00 00 5 P OO 00 ee 00 OO cum pos E OO 00 C12 SED 00 00 05 oo OO O e 5 ua C13 OO Von 5 a DO 00 00 oo GP 8 com 2 og 60 e OO 00 00 OO Boe 60 G Dooooo gt 00 00000 Doo 22 58858 Fig 6 Placement of components top Fig 7 Placement of components bottom 6 Power supply The minimodule is powered from an external 3 3V power source It s also possible to power the K60 microcontroller directly from USB In order to achieve this J1 jumper has to be shorted This will cause the internal voltage regulator to be used to supply power to the MCU Please note that it is not allowed to exceed 290mA load Also when using USB to power the module DO NOT apply any other external power source to the module Moreover the MCU peak current consumption can reach 300mA This means that when the MCU is running at full speed it is impossible to power any devices from the internal voltage regulator 7 Programming
17. lect Hardware configuration 11 S Components Library 23 6 When a project is created Processor Expert automatically Categories gt Alphabetical Assistant Processors introduces one or more CPU modules These can be adjusted to the Component user s needs v a graphical user interface After the CPU has been e me initialized various new components can be added to the project These a 5 CPU Internal Peripherals are divided into the following categories project Fig 9 rej LIL e CPU External Devices components for devices externally s zana controlled to the CPU For example sensors memories gt Memory displays or EVM eguipment No n e CPU Internal Peripherals components using any of on chip D NIM peripherals offered by the CPU gt Communication e Logical Device Drivers developed to offer users the re SE Hardware Abstraction Layer HAL for bare metal applications rej Me on as well as RTOS applications gt Interrupts e Operating systems components related to Processor Expert z interaction with operating system running on the target gt en e SW components encapsulating pure software algorithms or Timer inheriting a hardware dependent components for accessing Es peripherals GB max After double clicking on the selected component PE will add it to the c current project and it will show up in the Components tab Double 4 e dese clicking a component added this way
18. ntains all the necessary components required to communicate with the microcontroller and allow the proper operation of the on board modules JTAG and USB connector 50 MHz 32 kHz clock sources diodes resistors capacitors inductors The main purpose of this project was to design a small and flexible standalone module that would enable the use of the wide range of K60 microcontroller s capabilities in a broad spectrum of educational applications The final version of the board can be seen in Fig 2 and Fig 1 Close Ji to supply from YSE GU Fig 2 Assembled board top Fig 1 Assembled board bottom 2 Overview The Kinetis MCU portfolio consists of multiple pin peripheral and software compatible MCU families based on the ARM Cortex M4 core 2 Families are built from innovative 90 nm thin film storage TES flash technology with unique FlexMemory EEPROM capability and offer industry leading low power and mixed signal analog integration The K60 MCU family includes IEEE 1588 Ethernet Full and High Speed USB 2 0 On The Go with device charger detect capability hardware encryption and tamper detection capabilities Devices start from 256 KB of flash in 100 LQFP packages extending up to 1 MB in a 256 MAPBGA package with a rich suite of analog communication timing and control peripherals High memory density K60 family devices include an optional single precision floating point unit NAND flash controller and DRAM controll
19. ock gating to allow granular shutoff of modules The primary clocks for the system are generated from the MCGOUTCLK clock The clock generation circuitry provides several clock dividers that allow different portions of the device to be clocked at different frequencies This allows for tradeoffs between performance and power dissipation Various modules such as the USB OTG Controller have module specific clocks that can be generated from the MCGPLLCLK or MCGFLLCLK clock In addition there are various other module specific clocks that have other alternate sources Clock selection for most modules is controlled by the SOPT registers in the SIM module The clocking diagram for MCG module can be seen in detail in Fig 3 MCG Be Te J FLL Stee LET Gs Te Mi OSC b XTALO XH logic ah h NS EXTAL32 X XTAL32 X some peripherals Clock options for see note Core system clocks EXTAL1 X Bus clock XTAL1 X FlexBus clock Flash clock EXTALO X Clock options for some peripherals see note PMC logic LPO CG Clock gate Real time clock Note See subsequent sections for details on where these clocks are used Fig 3 Clocking diagram In addition to the MCG module K60 possesses three additional clock modules 1 e Oscillators OSC two high frequency crystal oscillators which generate filtered oscillator clock signals OSCCLK for MCU system
20. osnor E neo PTB7 PTB6 SE SE OBEGEBPPPEREx P PTBA Hi PTB3 PTB2 ADC1 PGA1 DM 0000000000000 PTE PTBO DACO ADCO PTA29 PTA28 PTE24 DAC1 PTA27 PTA26 PTE26 PTE25 PTA25 PTA24 PTE28 PTE27 RESET PTA19 PTAS PTA4 PTA17 PTA16 PTA7 PTA6 PTA15 PTA14 VREFL VREFH PTA13 PTA12 VSSA VDDA PTA11 PTA10 V GND PTAQ PTA8 Fig 10 Pin header overview 12 KS Default ALTO ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 1 PTD13 DISABLED PTD13 SPI2 SOUT SDHCO D5 FB A21 2 PTD12 DISABLED PTD12 SPI2 SCK FTM3 FLTO SDHCO_D4 FB_A20 3 PTD15 DISABLED PTD15 SPI2_PCS1 SDHCO_D7 FB_A23 4 PTD14 DISABLED PTD14 SPI2_SIN SDHCO_D6 FB_A22 5 PTE1 ADC1 SE5a ADC1 SE5a a pg SPIL SOUT UARTI_RX SDHCO_DO DCH 56 SPI1 SIN 6 PTEO ADC1_SE4a ADC1_SE4a PTEO SPI1_PCS1 UART1_TX SDHCO_D1 DCH 504 RTC CLKOUT 7 PTE3 ADC1 SE7a ADC1 SE7a PTE3 SPI1 SIN UART1 RTS b SDHCO CMD SPI SOUT 8 PTE2 ADC1_SE6a ADC1_SE6a W bi SPI SCK UART1 CTS b SDHCO DCLK 9 PTE5 DISABLED PTE5 SPI PCS2 UART3 BN SDHCO D2 FTM3 CHO PTE4 10 PTE4 DISABLED er SPI PCSO UART3 TN SDHCO D3 11 PTE7 DISABLED PTE7 UART3 RTS b Dap RXDO FTM3 CH2 12 PTE6 DISABLED PTE6 SPI PCS3 _ UART3 CTS 250 FTM3_CH1 USB_SOF_ OUT 13 PTE9 ADC2_SE17 ADC2_SE17 PTE9 250 TXD1 UART5_RX I2S0 RX BCLK FTM3 CH4 14 PTE8 ADC2 SE16 ADC2 SE16 PTE8 1250 RXD1 UART5 TX 250 RX FS FTM3 CH3 15 PTE11 ADC3 SE16 ADC3 SE16 PTE11 UART5 RTS I2S0 TX FS FTM3 CH6 16 PTE10 DISABLED PTE10 UART5 CTS b Dap TXDO FTM3 CH5 17 USBO DP USBO DP USBO DP 18 PTE12
21. will open the configuration Tutorials And Demonstrations window for that module Importantly after each change in the module configuration it has to be built again Some configuration options Fig 9 PE module categories may be unavailable depending on how a certain block is set up Unfortunately Processor Expert does not allow to change all available registers fields In such situations it is advisable to use Peripheral Initialization modules which provide only initialization configuration of a function block These modules can be found in the Components library in Processor Internal Peripherals Peripheral Initialization section More detailed information on configuring and adding components can be found in 5 K40 and K60 microcontrollers can be configured using PE n an almost identical manner 8 Connectors and signals In order to allow the user to utilize the full capabilities of the K60 microcontroller all the signals have been connected to two row pin headers SVL SVT SVR This allows for a fast and reliable connection to another custom designed board Numbering and spacing of the pins is shown in Fig 10 A detailed description of pins and along with their various functions is presented in Table 2 Table 3 and Table 4 PTD13 GND V PTD15 PTC7 PTC6 PTE1 PTC5 PTC4 PTE3 PTC3 PTC2 PTE5 PTC1 PTCO PTE7 PTB23 PTB22 PTE9 PTB21 PTB20 PTE11 PTB19 PTB18 PTB17 PTB16 VOUT33 PTB11 PTB10 PGA2_DP PTB9 PTB8 PGA3_DP PGA2_DM Zw
22. work with Freescale microcontrollers is Processor Expert 4 5 which is designed for rapid application development of embedded applications for a wide range of microcontrollers and microprocessor systems It is integrated as a plug in into the CodeWarrior IDE Processor Expert generates code from the Embedded Components and CodeWarrior manages the project files and compilation and debug processes File Edit Search Project MOX Tools ProcessorExpert Run Window Help 4 a Brae S k Acce EC Hardware Configuration Registers Processor 7 f Component Inspector Cpu Basic Advanced pen va CPU v Properties Methods Events Build options Resources Reg name nit value Afterreset Add r a Penpheral regeters 41141111113 PAP a aE ED EO HERNRRHRHZN NR ORS EE pm 9 RTC_CR 00000000 4003 H 333333333 j 334333 3 Fi i ELLE CPU type MKSOFXSIZVLQ15 2 E gt SIM SOPTI 2004 iii ii IT i 17 Clock settings SIM_SOPT2 44001004 4004 5 e aari a3 Initialization prionty minimal priordy x ADC Sia o9 Watchdog disable yes SIM SOPT4 4004 TA wo 9 SOPTS O ner Internal peripherals SIM_SOPTS ADCO ADCI ADC2 ADC3 AIPSO SIM_SOPT6 4004 EZ CPU interrupts resets WS z voos ADCO er SIM SOPT7 00000000 2004 Qo us APSI AXBS CANO CANI CAU saa External Bus Disabled SIM SCGC1 00000020 4004 lt CMPO CMP1 CMP2 CMP3 CMT ee Low power mode settings
23. zi z gt wm ES xternal bus clock ABS 76 10 48576 MHz LLWU_FILT 00 200 m TZ a MK60FX512VLQ1 5 OAA Flash clock prescaler Auto select 2 LLWU_FILT2 00 400 mi A ee weu PM LVOSCI 50 4007 Qo lash clock 0 48576 0 48576 MHz ne i user ne g 4 PLL FLL clock selectic FLL ee gt ma m Clock frequency A 20 97152 MHz PMC_REGSC 04 4007 RE PEN mb nn dm SMC_PMPROT 00 4007 v 3173 SSeSSSREREER gt OSC1_CR 80 400 a 5 g d k H i i i i a Additional registers a D Aas E k ZE ES ib t Fa ZG TIP III FO TITANA JI RE MPU_RGD1_WORD2 00000000 4000 MPU_RGD2_WORD2 00000000 4000 sans ACR IAN lt ANNN v 2 Problems m O items Description Resource Path Location Type Fig 8 Processor Expert plug in In order to start working with a new project a project creation wizard is used Choose File then New and click Bareboard Project A wizard window will show up where the project name and workspace path can be specified Then the following project options need to be configured e Devices select K60FX512 150 Mhz e Connections select unless using a different programmer Segger J Link J Trace SWO SWD based e Language and Build Tools Options o Language leave C o Floating Point leave Hardware mfloat abi hard o ARM Build Tools select Freescale e Rapid Aplication Development o Rapid Aplication Development select Processor Expert o Start with perspective designed for se

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