Digilent Basys Board Reference Manual
Contents
1. ee ESD protection diodes Spartan 3E FPGA JPA 3 3V Power supply jumper i Note Every 6 pin connector has a power supply jumper and ESD diodes although they are only shown for JPA 74 JD 3 98 75 JD1 99 GND VDDO 1 NC VDDAUX VDDO 1 NC___ 127 2 ANE oe Le VDDINT U SLWR MODE2 U SLRD NC U SLCS U D7 U D6 VDDO 2 8 Ne BLUE1 BLUEO CD DP REDO CCLK os MR DONE 96 PS2C CC 47 BTN2 SW3 BTN1 Copyright Digilent Inc 60 MODEI 64 nC 108 TMS TDO 62 MODEO Page 11 12 U D5 26 ic iio TCK m as U PKTD U AD 137 rene Laat 112 Kma VDDO 0 PHH e o TEETH U D1 3 JB 2 117 U SLDE 14 NC JB 4 118 TE 142 U DO 119 143 120 144 HSWAP Doc 502 107 Basys Reference Manual A Digilent www digilentinc com Built in Self Test A demonstration configuration is loaded into the Platform Flash ROM during manufacturing This demo also available on the resource CD and on the Digilent website can serve as a board verification test since it interacts with all devices and ports on the Basys board To configure the FPGA from a bit file stored in Platform Flash set the Mode Jumper to ROM and cycle power or press the FPGA reset button BTNR The self test connects the switches to the LEDs the buttons and PS 2 keyboard if attached to the seven segment display and a VGA monitor if attached will show a color pat2. i DU l l 7 Frequency a Spartan 3E Linear Tech Select 25MHz FPGA LTC6905 Jumper zi Oscillator _ amp SOMHz 54 4 CLK_OUT soon Figure 5 Basys oscillator circuits installed in the IC7 socket For these applications a 25MHz or 50MHz crystal oscillator available from any catalog distributor is recommended see for example part number SG 8002JF PCC at www digikey com Copyright Digilent Inc Page 3 12 Doc 502 107 Basys Reference Manual User I O Four pushbuttons and eight slide switches are provided for circuit inputs Pushbutton inputs are normally low and driven high only when the pushbutton Is pressed Slide switches generate constant high or low inputs depending on position Pushbuttons and slide switches all have series resistors for protection against short circuits a short circuit would occur if an FPGA pin assigned to a pushbutton or slide switch was inadvertently defined as an output Eight LEDs and a four digit seven segment LED display are provided for circuit outputs LED anodes are driven from the FPGA via current limiting resistors so they will illuminate when a logic 1 is written to the corresponding FPGA pin A ninth LED is provided as a power indicator LED and a tenth LED LD D illuminates any time the FPGA has been successfully programmed Seven segment display Each of the four digits of the seven segment LED display is composed of seven LED segments arranged i
3. counter can be used to locate any given row These two continually running counters can be used to form an address into video RAM No time relationship between the onset of the HS pulse and the onset of the VS pulse is specified so the designer can arrange the counters to easily form video RAM addresses or to minimize decoding logic for sync pulse generation o HS Zero Zero CE EA Set Horizontal Horizontal Vertical Vertical Pixel Counter Synch Counter Synch CLK 3 84us 64us Figure 17 Schematic for a VGA controller circuit Copyright Digilent Inc Page 10 12 Doc 502 107 Basys Reference Manual Expansion Connectors 6 pin headers The Basys board provides four 6 pin peripheral module connectors Each connector provides Vdd GND and four unique FPGA signals Several 6 pin module boards that can attach to this connector are available from Digilent including A D converters speaker amplifiers microphones H bridge amplifiers etc Please see www digilentinc com for more information FPGA Pin Definitions The table below shows all pin definitions for the Spartan 3E on the Basys board Pins in grey boxes are not available to the user FPGA pin definition table color key Grey _ Notavailabletouser Green UserV Odevices Yellow_ _ Data ports _ Tan _ Pmod connector signals _ Ble USBsignals GRN2 GRN1 GRNO CLK2 CLK1 A Digilent www digilentinc com Short circuit protection resistors
4. display 4 buttons 8 slide switches l l PS 2 port and 8 bit VGA port amp D A conversion motor drivers sensor User settable clock 25 50 100MHz plus socket for 2 clock inputs and many other features Signals on Four 6 pin header expansion connectors the 6 pin connectors are protected against ESD and short circuit protection on all I O signals ESD damage and short circuits ensuring a long operating life in any environment The Basys board works seamlessly with all versions of the Xilinx ISE tools including the free WebPack It ships with a USB cable that provides power and a programming interface so no other power supplies or programming cables are required Figure 1 Basys board block diagram and features The Basys board can draw power and be programmed via its on board USB2 port Digilent s freely available PC based Adept software automatically detects the Basys board provides a programming interface for the FPGA and Platform Flash ROM and allows user data transfers at up to 400Mbytes sec see www digilentinc com for more information The Basys board can also be programmed from within the Xilinx ISE tool environment using a Digilent JTAG3 or suitable Xilinx cable and a separate power supply The Basys board is designed to work with the free ISE WebPack CAD software from Xilinx WebPack can be used to define circuits using schematics or HDLs to simulate and synthesize circuits and to create programming files Webpack can be
5. downloaded free of charge from www xilinx com ise The Basys board ships with a built in self test stored in its ROM that can be used to test all board features To run the test set the Mode Jumper see below to ROM and apply board power If the test is erased from the ROM it can be downloaded and reinstalled at any time See www digilentinc com basys for the test project as well as further documentation reference designs and tutorials Copyright Digilent Inc All rights reserved 12 pages Doc 502 107 Digilent www digilentinc com Basys Reference Manual A Board Power The Basys board is typically powered from a USB cable but a power jack and battery connector are also provided so that external supplies can be used To use USB power set the power source switch SW8 to USB and attach the USB cable To use an external wall plug power supply set SW8 to EXT and attach a 5VDC to 9VDC supply to the center positive 2 1 5 5mm power jack To use X rae sine com battery power set SW8 to EXT and attach a 4V 9V battery pack to ZT T a the 2 pin 100 mil spaced battery connector four AA cells in series geen P Be Li make a good 6 volt supply Voltages higher than 9V on either power connector may cause permanent damage SW8 can also be used to turn off main power by setting it to the unused power input e g if USB power is used setting SW8 to EXT will shut off board power without unplugging the USB cable Figure 2 Basys
6. is released a FO key up code is sent followed by the scan code of the released key If a key can be shifted to produce a new character like a capital letter then a shift character is sent in addition to the scan code and the host must determine which ASCII character to use Some keys called extended keys send an EO ahead of the scan code and they may send more than one scan code When an extended key is released an EO FO key up code is sent followed by the scan code Scan codes for most keys are shown in the figure A host device can also send data to the keyboard Below is a short list of some common commands a host might send ED Set Num Lock Caps Lock and Scroll Lock LEDs Keyboard returns FA after receiving ED then host sends a byte to set LED status Bit 0 sets Scroll Lock bit 1 sets Num Lock and Bit 2 sets Caps lock Bits 3 to 7 are ignored EE Echo test Keyboard returns EE after receiving EE F3 Set scan code repeat rate Keyboard returns F3 on receiving FA then host sends second byte to set the repeat rate FE Resend FE directs keyboard to re send most recent scan code FF Reset Resets the keyboard The keyboard can send data to the host only when both the data and clock lines are high or idle Since the host is the bus master the keyboard must check to see whether the host is sending data Copyright Digilent Inc Page 6 12 Doc 502 107
7. of 4 lr VA energized electrons from the cathodes and LEE A T those rays are fed by the current that flows High voltage deflection grid gun into the cathodes These particle rays are SUPPIY P AURV Sever conker eau initially accelerated towards the grid but they l soon fall under the influence of the much Figure 14 CRT deflection system Copyright Digilent Inc Page 8 12 Doc 502 107 Basys Reference Manual A Digilent www digilentinc com larger electrostatic force that results from the entire phosphor coated display surface of the CRT being charged to 20kV or more The rays are focused to a fine beam as they pass through the center of the grids and then they accelerate to impact on the phosphor coated display surface The phosphor surface glows brightly at the impact point and it continues to glow for several hundred microseconds after the beam is removed The larger the current fed into the cathode the brighter the phosphor will glow Between the grid and the display surface the beam passes through the neck of the CRT where two coils of wire produce orthogonal electromagnetic fields Because cathode rays are composed of charged particles electrons they can be deflected by these magnetic fields Current waveforms are passed through the coils to produce magnetic fields that interact with the cathode rays and cause them to transverse the display surface in a raster pattern horizontally from left to right and vertical
8. program called Adept can be used to configure the FPGA with any Suitable bit file stored on the computer Adept a uses the USB cable to transfer a selected bit Figure 3 Basys programming circuit locations file from the PC to the FPGA via the FPGA s JTAG programming port Adept can also program a bit file into an on board non volatile ROM called Platform Flash Once programmed the Platform Flash can automatically transfer a stored bit file to the FPGA at a subsequent power on or reset event if the Mode Jumper is set to ROM The FPGA will remain configured until it is reset by a Copyright Digilent Inc Page 2 12 Doc 502 107 Basys Reference Manual power cycle event or by the FPGA reset button BTNR being pressed The Platform Flash ROM will retain a bit file until it is reprogrammed regardless of power cycle events To program the Basys board attach the USB cable to the board if USB power will not be used attach a suitable power supply to the power jack or battery connector on the board and set the power switch to VEXT Start the Adept software and wait for the FPGA and the Platform Flash ROM to be recognized Use the browse function to associate the desired bit file with the FPGA and or the desired mcs file with the Platform Flash ROM Right click on the device to be programmed and select the program Digilent www digilentinc com A Cypress JTAG EZ USB header Mode Pu Jumper d i ROM JTAG USB m
9. Basys Reference Manual A MNE e aa before driving the bus To facilitate this the clock line is used as a clear to send signal If the host pulls the clock line low the keyboard must not send any data until the clock is released The keyboard sends data to the host in 11 bit words that contain a 0 start bit followed by 8 bits of scan code LSB first followed by an odd parity bit and terminated with a 1 stop bit The keyboard generates 11 clock transitions at around 20 30KHz when the data is sent and data is valid on the falling edge of the clock ESC F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 t 76 05 06 04 OC 03 OB 83 OA 01 09 78 07 E075 1 2 3 4 5 6 7 amp 8 9 0 _ BackSpace gt OE 16 1E 26 25 2E 36 3D 3E 46 45 4E 55 66 EO 74 TAB Q W R T Y U O P OD 15 1D 24 2D 2C 35 3C 43 44 4D 54 5B 5D E0 6B Caps Lock A S D F G H J K L of om Enter 58 1C 1B 23 2B 34 33 3B 42 4B 4C 52 5A EO 72 Shift Z X C V B N M lt gt An Shift 12 1Z 22 21 2A 32 31 3A 41 49 4A 59 Ctrl Alt Space Alt Ctrl 14 11 29 EO 11 EO 14 Figure 11 Keyboard scan codes Mouse The mouse outputs a clock and data signal when it is moved otherwise these signals remain at logic 1 Each time the mouse is moved three 11 bit words are sent from the mouse to the host device Each of the 11 bit words contains a 0 start bit followed by 8 bi
10. Digilent Basys Board A DIGILENT Reference Manual war Cig eniinc com Revision August 18 2007 215 E Main Suite D Pullman WA 99163 509 334 6306 Voice and Fax Introduction High Speed Platform Settable Clock The Basys board is a circuit design and USB2 Port lt Flash Source implementation platform that anyone can use JTAG and data transfers config ROM 25 50 100 MHz to gain experience building real digital circuits 20 f a4 Be Built around a Xilinx Spartan 3E Field Programmable Gate Array and a Cypress EZ An USB controller the Basys board provides Xilinx Spartan3E 100 TQ144 complete ready to use hardware suitable for hosting circuits ranging from basic logic 2 2 Bee 4 4 4 devices to complex controllers A large color collection of on board I O devices and all Pp Or y required FPGA support circuits are included WA Js ic ND so countless designs can be created without the need for any other components A PS 2 VGA Port Pmod Connectors I O Devices Port Four standard expansion connectors allow 100 000 gate Xilinx Spartan 3E FPGA designs to grow beyond the Basys board Cypress EZ USB Hi speed USB2 port providing board power using breadboards user designed circuit and programming data transfer interface boards or Pmods Pmods are inexpensive Xilinx Platform Flash ROM to store FPGA configurations analog and digital I O modules that offer A D 8 LEDs 4 digit 7 segment
11. XYIYY P 1 0 X0O X1 X2 X3 X4 X5 X6 X7 P 1 0 YO Y1 Y2 Y3 Y4 Y5 Y6 Y7 P Start bit Stop bit Start bit Stop bit Start bit Stop bit Idle state Idle state Figure 12 Mouse data format Copyright Digilent Inc Page 7 12 Doc 502 107 Basys Reference Manual A Digilent www digilentinc com VGA Port The Basys board uses 10 FPGA signals to create a VGA port with 8 bit color and the two standard sync signals HS Horizontal Sync and VS Vertical Sync The color signals use resistor divider circuits that work in conjunction with the 75 ohm termination resistance of the VGA display to create eight signal levels on the Pin 1 Red Pin 5 GND Pin 2 Grn Pin 6 Red GND Pin 3 Blue Pin 7 Grn GND Pin 13 HS Pin 8 Blu GND Pin 14 VS Pin 10 Sync GND red and green VGA signals and four on blue zg RERO ah the human eye is less sensitive to blue levels Spartan 3E RED1 1KQ This circuit shown in figure 13 produces video FPGA a RED2 510Q color signals that proceed in equal increments 67 between OV fully off and 0 7V fully on A 59 _GRNO 2KQ HD DB15 video controller circuit must be created in the FPGA to drive the sync and color signals with the correct timing in order to produce a working 50 display system 1KQ 51 GRN1 GRN2 5100 1KO 44 BLUEO VGA System Timing 43 BLUE 9100 VGA signal timings are specified published 39 2000 copyrighted and sold by the VESA organization 35 2002
12. cycle or 4ms The controller must assure that the correct cathode Cathodes pattern is present when the corresponding anode signal is driven Figure 8 Multiplexed 7seg display timing To illustrate the process if AN1 is asserted while CB and CC are asserted then a 1 will be displayed in digit position 1 Then if AN2 is asserted while CA CB and CC are asserted then a 7 will be displayed in digit position 2 If A1 and CB CC are driven for 4ms and then A2 and CA CB CC are driven for 4ms in an endless succession the display will show 17 in the first two digits Figure 8 shows an example timing diagram for a four digit seven segment controller PS 2 Port The 6 pin mini DIN connector can accommodate a PS 2 mouse or keyboard Most PS 2 devices can operate from a 3 3V supply but some older devices may require a 5VDC supply A jumper on the Basys board JP1 selects whether 3 3V or VU is supplied to the PS 2 connector For 5V set JP1 to VU and ensure that Basys is powered with a 5VDC wall plug supply For 3 3V set the jumper to 3 3V For 3 3V operation any board power supply including USB can be used Both the mouse and keyboard use a two wire serial bus clock and data to communicate with a host device Both use 11 bit words that include a start stop and odd parity bit but the data packets are organized differently and the keyboard interface allows bi directional data transfers so the host device can illuminate stat
13. e LEDs on the keyboard Bus timings are shown in the figure Copyright Digilent Inc Page 5 12 Doc 502 107 Basys Reference Manual A Digilent www digilentinc com The clock and data signals are only driven when data transfers occur and otherwise they are held in the idle state at logic 1 The timings define signal requirements for mouse to host communications and bi directional keyboard communications A PS 2 interface circuit can be implemented in the FPGA to create a keyboard or mouse interface 3V3 VU PS 2 power VU provided to PS 2 P select jumper Pin1 Data 3 3V provided to PS 2 P pis BRE di Hee 200 Q Pind Vdd 5 gt 13 Pin6 Clock Spartan 3E 96 OO00 Pin8 Clock FPGA 97 8 6 O O 6 pin bottom up mini DIN Figure 9 PS 2 connector and Basys PS 2 circuit Keyboard Edge 0 gt a Edge 10 The keyboard uses open collector drivers so the OSAN a _ lt gt Thid T stop bit keyboard or an attached host device can drive the pk _A_J two wire bus if the host device will not send data to Tsu gt lt the keyboard then the host can use input only ports Symbol Parameter Min Max Clock time PS2 style keyboards use scan codes to Data to clock setup time communicate key press data Each key is assigned a Clock to data hold time code that is sent whenever the key is pressed if the key is held down the scan code will be sent Figure 10 PS 2 signal timing repeatedly about once every 100ms When a key
14. ignal defines the refresh frequency of the display or the frequency at which all information on the display is Vertical Sync Horiz Sync Parameter redrawn The minimum refresh frequency is Time Clocks Lines Time Clks a function of the display s phosphor and Sync pulse 16 7ms 416 800 32 us 800 electron beam intensity with practical Display time 15 36ms 384 000 480 25 6 us 640 refresh frequencies falling in the 50Hz to 120Hz range The number of lines to be displayed at a given refresh frequency defines the horizontal retrace frequency For a 640 pixel by 480 row display using a 25MHz pixel clock and 60 1Hz refresh Figure 16 VGA system timings for 640x480 display the signal timings shown in the table at right can be derived Timings for sync pulse width and front and back porch intervals porch intervals are the pre and post sync pulse times during which information cannot be displayed are based on observations taken from actual VGA displays Pulse width 64 us 1 600 3 84 us Front porch 320 us 8 000 640 ns Back porch 928 us 23 200 1 92 us A VGA controller circuit decodes the output of a horizontal sync counter driven by the pixel clock to generate HS signal timings This counter can be used to locate any pixel location on a given row Likewise the output of a vertical sync counter that increments with each HS pulse can be used to generate VS signal timings and this
15. iniB connector XCF02 FPGA Platform Reset Flash Button BTNR Figure 4 Basys Programming Circuits function The configuration file will be sent to the FPGA or Platform Flash and the software will indicate whether programming was successful The configuration done LED LD_D will also illuminate after the FPGA has been successfully configured For further information on using Adept please see the Adept documentation available at the Digilent website Oscillators The Basys board includes a primary user settable silicon oscillator that produces 25MHz SOMHz or 100MHz based on the position of the clock select jumper at JP4 A socket for a second oscillator is provided at IC7 the IC7 socket can accommodate any 3 3V CMOS oscillator ina half size DIP package The primary and secondary oscillators are connected to global clock input pins at pin 54 and pin 53 respectively Both clock inputs can drive the clock synthesizer DLL on the Spartan 3E allowing for a wide range if internal frequencies from 4 times the input frequency to any integer divisor of the input frequency The primary silicon oscillator is flexible and inexpensive but it lacks the frequency stability of a crystal oscillator Some circuits that drive a VGA monitor may realize a slight improvement in image stability by using a crystal oscillator remenna S gt XILINX SPARTAN XC3S100E TQ1448GQ0533 PETELEERAREPR ERT RO RTE R ERO E SD 1 TRL
16. ly from top to bottom As the cathode ray moves over the surface of the display the current sent to the electron guns can be increased or decreased to change the brightness of the display at the cathode ray impact point Information is only displayed when the beam is moving in the forward direction left to right and top to bottom and not during the time the beam is reset back to the left or top edge of the display Much of the potential display time is therefore lost in blanking periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass The size of the beams the frequency at which the beam can be traced across the display and the frequency at which the electron beam can be modulated determine the display resolution Modern VGA displays can accommodate different resolutions and a VGA controller circuit dictates the resolution by producing timing signals to control the raster patterns The controller must produce synchronizing pulses at 3 3V or 5V to set the frequency at which current flows through the deflection coils and it must ensure that video data is applied to the electron guns at the correct time Raster video displays define a number of rows that corresponds to the number of horizontal passes the cathode makes over the display area and a number of columns that corresponds to an area on each row that is assigned to one picture element or pixel Typical displa
17. n a figure 8 pattern Segment LEDs can be individually illuminated so any one of 128 KX Digilent www digilentinc com Push 3 3V buttons BTNO 69 BTN1 48 BTN2 4r 41 BTN3 Spartan 3E 3 3V FPGA SWO o w 38 SW1 o wW 36 SW2 7 o wv 29 Il Cl I LI LILI SW3 o w 24 SW4 o wv 18 SW5 o w 12 SW6 o wv 10 SW7 o w 6 Slide switches 29 De 7seg Display Figure 6 Basys I O circuits patterns can be displayed on a digit by illuminating certain LED segments and leaving the others dark Of these 128 possible patterns the ten corresponding to the decimal digits are the most useful The anodes of the seven LEDs forming each digit are tied together into one common anode circuit node but the LED cathodes remain separate The common anode signals are available as four digit enable input signals to the 4 digit display The cathodes of similar segments on all four displays are connected into seven circuit nodes labeled CA through CG so for example the four D cathodes from the four digits are grouped together into a single circuit node called CD These seven cathode signals are available as inputs to the 4 digit display This signal connection scheme creates a multiplexed display where the cathode signals are common to all digits but they can only illuminate the segments of the digit whose corresponding anode signal is asserted A scanning display c
18. ontroller circuit can be used to show a four digit number on this display This circuit drives the anode signals and corresponding cathode patterns of each digit in a repeating continuous succession at an update rate that is faster than the human eye response Each digit is Copyright Digilent Inc Page 4 12 Doc 502 107 Digilent www digilentinc com Basys Reference Manual A illuminated just one quarter of the time but because the eye cannot perceive the darkening of a digit before it is illuminated again the digit appears continuously illuminated If the update or refresh rate is slowed to a given point around 45 hertz then most people will begin to see the display flicker Common anode ANI an AN ANA I LILI I Lf l Four digit Seven i DP i i l l Segment Display An un illuminated seven segment display and nine illumination patterns corresponding to decimal digits Individual cathodes Figure 7 Seven segment display For each of the four digits to appear l Refresh period 1ms to 16ms bright and continuously illuminated all four digits should be driven once every 1 lt lt _ _ gt Digit period Refresh 4 to 16ms for a refresh frequency of ANO 1KHz to 60Hz For example in a 60Hz ae T L p refresh scheme the entire display would be refreshed once every 16ms and AN2 w 3 each digit would be illuminated for 1 4 of AN3 ae sa the refresh
19. power circuits Input power is routed through the power switch SW8 to the four 6 pin expansion connectors and to a National Semiconductor LP8345 voltage regulator The LP8345 produces the main 3 3V supply for the board and it also drives secondary regulators to produce the 2 5V and 1 2V supply voltages required by the FPGA Total board current is dependant on FPGA configuration clock frequency and external connections In test circuits with roughly 20K gates routed a 50MHz clock source and all LEDs illuminated about 100mA of current is drawn from the 1 2V supply 50mA from the 2 5V supply and 50mA from the 3 3V supply Required current will increase if larger circuits are configured in the FPGA or if peripheral boards are attached The Basys board uses a four layer PCB with the inner layers dedicated to VCC and GND planes The FPGA and the other ICs on the board have large complements of ceramic bypass capacitors placed as close as possible to each VCC pin resulting in a very clean low noise power supply Configuration After power on the FPGA on the Basys board must be configured before it can perform any ME GEEb 00 3p i useful functions During configuration a bit file is transferred into memory cells within the FPGA to define the logical functions and circuit interconnects The free ISE WebPack CAD software from Xilinx can be used to create bit files from VHDL Verilog or schematic based source files Digilent s PC based
20. tern By interacting with the buttons and switches on the Basys board and the keys on a PS 2 keyboard if attached and watching the LEDs seven segment display and VGA monitor if attached any hardware problems with the Basys board can be readily identified If the self test is not resident in the Platform Flash ROM it can be programmed into the FPGA or reloaded into the ROM using the Adept programming software Copyright Digilent Inc Page 12 12 Doc 502 107
21. ts of data LSB first followed by an odd parity bit and terminated with a 1 stop bit Thus each data transmission contains 33 bits where bits 0 11 and 22 are 0 start bits and bits 11 21 and 33 are 1 stop bits The three 8 bit data fields contain movement data as shown in the figure above Data is valid at the falling edge of the clock and the clock period is 20 to 30KHz The mouse assumes a relative coordinate system wherein moving the mouse to the right generates a positive number in the X field and moving to the left generates a negative number Likewise moving the mouse up generates a positive number in the Y field and moving down represents a negative number the XS and YS bits in the status byte are the sign bits a 1 indicates a negative number The magnitude of the X and Y numbers represent the rate of mouse movement the larger the number the faster the mouse is moving the XV and YV bits in the status byte are movement overflow indicators a 1 means overflow has occurred If the mouse moves continuously the 33 bit transmissions are repeated every 50ms or so The L and R fields in the status byte indicate Left and Right button presses a 1 indicates the button is being pressed m Mouse status byte m X direction byte m Y direction byte 1 0 L R 0O 1 IXS YSI
22. www vesa org The following VGA system timing information is provided as an example of how a VGA monitor might be driven in 640 by Figure 13 VGA pin definitions and Basys circuit 480 mode For more precise information or for information on other VGA frequencies refer to documentation available at the VESA website CRTI based VGA displays use amplitude modulated moving electron beams or cathode rays to display information on a phosphor coated screen LCD displays use an array of switches that can impose a voltage across a small amount of liquid crystal thereby changing light permittivity through the crystal on a pixel by pixel basis Although the following description is limited to CRT displays LCD displays have evolved to use the same signal timings as CRT displays so the signals Anode entire screen discussion below pertains to both CRTs and LCDs Color CRT displays use three electron beams one for red one for blue and one for green to energize the phosphor that coats the inner side of the display end of a cathode ray tube see illustration Electron beams emanate from electron guns which are finely pointed heated cathodes placed in close proximity to a positively charged annular plate called a grid The electrostatic Cathode ray tube Deflection coils Griq Electron guns y Red Blue Green R G B signals 5 force imposed by the grid pulls rays
23. ys use from 240 to 1200 rows and from 320 to 1600 columns The overall size of a display and the number of rows and columns determines the size of each pixel Video data typically comes from a video refresh memory with one or more bytes assigned to each pixel location the Basys uses three bits per pixel The controller must index into video memory as the beams move Copyright Digilent Inc pixel 0 0 pixel 0 639 640 pixels per row are displayed during forward beam trace Retrace no information displayed during this time Display Surface a pixel 479 0 pixel 479 639 Stable current ramp information is displayed during this time r Current waveform through horizontal defletion Total horizontal time E coil Horizontal display time AR i lt pity gt lt gt time HS 3 time t L Horizontal sync signal t front porch sets retrace frequency back porch Figure 15 VGA system signals Page 9 12 Doc 502 107 Basys Reference Manual A Digilent www digilentinc com across the display and retrieve and apply video data to the display at precisely the time the electron beam is moving across a given pixel A VGA controller circuit must generate the T HS and VS timings signals and coordinate lt gt the delivery of video data based on the pixel lt gt Taisp clock The pixel clock defines the time available to display one pixel of information The VS s
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