EVM User`s Guide - Texas Instruments
Contents
1. Transmitter Receiver Board Board e um en 1 FPD LINKII x Digital p Gs uu LVDS Interface 4 B Digital Video Source o mo Cable o L Contents of Demo Kit Logic Analyzer Oscilloscope Figure 3 Typical SERDES Test Setup for Evaluation National Semiconductor Corporation Date 5 8 2008 Page 20 of 36 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual Troubleshooting If the demo boards not performing properly use the following a guide for quick solutions to potential problems Representative for assistance nig CHECKS If the problem persists please contact the local Sales Check that Power and Ground are connected to both Tx AND Rx boards Check the supply voltage typical 3 3V and also current draw with both Tx and Rx boards The Serializer board should draw about 55 65mA with clock and all data bits switching at 43MHz Rpre 9KQ The De serializer board should draw about 5 85mA with clock and all data bits switching at 43MHz m2. 7 T L ay aye sped pue ppe ajejndod un Jarsea 1 jo aspa 10 ase 5 sjoj3edes node Jasn ay ur suomejedos samod pue asaqg 5 sasn ay e si L sped ozis g pue 2090 s1ojaede Buydnosap 959 679 24 2 uonanpal asiou Jasn jou uaee ui Saas Jo 2 53015159 WYO YIM squausunseau smoly Jasn jou jo 5 Asea 20 sped 20 0 Sauos LZA OLY ZLM OLY 6H SNOLLdO S3Hf11 SSA 55 sud gana 372 b Jeau Jnzz 555 lt lt SEDGR JO LL uid ese 1022 PSD 20 0 r 92 uid Jesu daneg 052 TREE sa lt lt o0 SSA OF uid Jeau K T oda ax Date 5 8 2008 Page 29 of 36 National Semiconductor Corporation SERDES Evaluation
3. 13 CONFIGURATION SETTINGS FOR THE DE SERIALIZER BOARD 14 OUTPUT MONITOR PINS FOR THE DE SERIALIZER BOARD 15 DE SERIALIZER LVDS PINOUT AND LVCMOS CONNECTOR 17 BOM MATERIALES DE SERIALIZER 18 TYPICAL CONNECTION AND TEST EQUIPMENIT 19 TEROUDBPEEBSHOOTING 222522550 21 APPENDIX tee 23 SERIALIZER TX PCB SCHEMATIC uuu aa usasqa 23 DE SERIALIZER RX PCB SCHEMATIC 27 SERIALIZER TX PCB E RYOUT 31 SERIALIZER TX PCB STACKUB 34 DESERIALIZER RX PCB OU ini 35 DESERIALIZER RX PCB STACKUPB 38 National Semiconductor Corporation Date 5 8 2008 Page 2 of 36 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual Introductio
4. E x repe HOSS oz uinou Hrt DULA LNO E A HOGA 5 lizino 093 2 D ia re zz unou L zzLnow 9 joe z no SS ezinoy 8 Hno e 5558 008 wn 8 8 88 01108 B E y 5 A a o em 4 0HSSA 5 B SNOMd 8533 2 SNOMdH _ 57 ld fal Z u o 5 e k j L MOL L1 E Ww H G SL gt L iE s em 2 kr 8 3 8 52 m 3 5 5 National Semiconductor Corporation Date 5 8 2008 Page 28 of 36 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual LM 16 65 uid dnee Lf uid Jeau Jjnez 170 lt lt 16 suid Jeau lt lt owg ASN 0660 U Guydnosap pue a3u Jajay
5. 2105 z zo queuoduoo lt S0P H4 sseuxoruL 5700 0 E zo 9 PIS S205 0 6 zo eue d 90 SP00 0 277 UU zo g rl eprs Serializer Tx PCB Schematic xr m r4 Date 5 8 2008 Page 23 of 36 National Semiconductor Corporation SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual gsn 125400650 2591 Jaquinn 225 uo pasinbas sy Guay 40 ON LNOAVT papua 5 wyo os XI SSA E 244420 lt lt 200 aan gt O m 0 m m 401 eprs yusuoduon x gt lt lt jer re gt SSA JION HLd dA LLdSSA 3 7 014554 oM I NAC LISSA i Nag 0659
6. COPYRIGHT 2006 National Semiconductor PRE EMPHASIS AU lt IP E 5 RED m 55 a 01000000005 Ces Ei a 5 P1 du c EB pon 36 1 VSS e Eanzanzcul 000000 F B RH LL Ses nso B SERDESUR 43USB 059008241 TX ASST D590URZ241 USB TX DEMO A L JD _ PRIMARY COMP SIDE SILKSCREEN LAYER 1 SILKSCREEN COMP SIDE SILKSCREEN LAYER 4 National Semiconductor Corporation Date 5 8 2008 Page 33 of 36 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual Serializer Tx PCB Stackup ASSEMBLY SIDE 1 SILKSCREEN ASSY SIDE 1 SOLDERMASK ASSY SIDE 1 COMP SIDE PREPREG 0045 THK GND PLANE 102 LAYER 2 CORE 039 THK PWR PLANE 102 Laver 3 0 06 PREPREG 0045 55 0 SILKSCREEN 55 SIDE 2 ASSEMBLY SUE 2 SOLDERMASK ASSY SIDE 2 12 R TYP 4 PLCS Cn 4 500 450 NATIONAL SEMICONDUCTOR CORP DS90UR241 USB TX DEMO BOARD PWB 059008241 USB TX DEMO REV 1 DRILL DRAWING National Semiconductor Corporation 1 2 07 LAYER 1 SOLDER SIDE 1727 07 LAYER 4 3 lt gt 0045 82 ves 003 BE sssi oos 2 ves o _ A 1 0025 s wo 003 05 o _ 0265 2
7. 10 2 LVCMOS OUTPUTS FUNCTION CONTROLS 4 SUPPLY 3 52 COPYRIGHT C 2006 MADE IN U S A o SER DESUR 43USB D S90UR124 RX e ASSY DS90UR124 RX USB DEMO REV National Semiconductor Corporation Date 5 8 2008 Page 13 of 36 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual Configuration Settings for the De serializer Board S1 S2 De serializer Input Features Selection Input L RPWDNB PTOSEL Progressive Turn On Enabled Disabled SELect Default RESRVD RESeRVeD Reference Description InputzL Input H _ or Falling edge of TCLK Default ENabled Default BIST ENable Note MUST set DS90UR241 ALL DIN 23 0 inputs Low or BISTEN BISTM RAOFF SLEW SLEW rate control for ROUT 23 0 F PoWerDowN Bar floating Use in combination with BIS TM pin BIST Mode Don t care if BISTEN L BISTEN MUST be High enabled for this pin to be functional RAndomizer OFF National Semiconductor Corporation Power Down Normal Disabled Operational Default RPWONB m Don t care Don t care 0 RAOFF 1 SLEW BISTEN 5 Mode Enabled Normal Operating Mode BIST Disabled Default Per Channel RxOUT 7 0 pass fail binary error RxOUT 23 0 counting H pass mode up to RxOUT 23 0 255 errors H
8. BE MICRO MODIFIED IN ORDER TO FABRICATE BOARDS THE REQUIRED IMPEDANCE NOMINALS TO A TOLERANCE OF 5x BOARD BE FABRICATED IN COMPLIANCY TO ROHS REQUIREMENTS Date 5 8 2008 Page 38 of 36 IMPORTANT NOTICE FOR REFERENCE DESIGNS Texas Instruments Incorporated TI reference designs are solely intended to assist designers Buyers who are developing systems that incorporate semiconductor products also referred to herein as components Buyer understands and agrees that Buyer remains responsible for using its independent analysis evaluation and judgment in designing Buyer s systems and products reference designs have been created using standard laboratory conditions and engineering practices has not conducted testing other than that specifically described in the published documentation for a particular reference design may make corrections enhancements improvements and other changes to its reference designs Buyers are authorized to use TI reference designs with the component s identified in each particular reference design and to modify the reference design in the development of their end products HOWEVER NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENSE TO ANY THIRD PARTY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT IS GRANTED HEREIN including but not limited to any patent right copyright mask w
9. HOLES MARKED ARE TOOLING HOLES UNPLATED AND SHALL BE ONCE DRILLED FABRICATE USING MASTER FILM 059008124 RX USB DEMO REV 1 USE BOARD OUTLINE FILE 472 FOR BOARD ROUTE ACCEPTABILITY SHALL BE BASED IPC A 600 CLASS 2 MATERIAL BASE MATERIAL 15 NEMAL 1 GRADE FR 406 COLOR GREEN 0 052 INCH NOM THICKNESS COPPER CLADDING SHALL BE 1 2 07 OUTSIDE LAYERS AND 1 OZ INSIDE LAYERS PLATING ALL HOLES AND CONDUCTIVE SURFACES SHALL BE PLATED WITH MIN OF 001 INCH CU SURFACE FINISH GOLD FLASH 000005 MIN FABRICATION TOLERANCES END PRODUCT CONDUCTOR WIDTHS AND LAND DIAMETERS SHALL NOT VARY MORE THAN 005 INCH FROM THE 1 1 DIMENSIONS OF THE MASTER PATTERN THE CONDUCTIVE PATTERN SHALL BE POSITIONED SO THAT THE LOCATION OF ANY LAND SHALL BE WITHIN 010 INCH DIAMETER TO THE TRUE POSITION OF THE HOLE IT CIRCUMSCRIBES THE MINIMUM ANNULAR RING SHALL BE 002 INCH BOW AND TWIST SHALL EXCEED 010 INCH PER INCH SOLDERMASK BOTH SIDES PER 5 840 A CLASS COLOR GREEN THERE SHALL BE NO SOLDERMASK ON ANY LAND SILKSCREEN THE LEGEND ON BOTH SIDES USING NON CONDUCTIVE EPOXY INK COLOR WHITE THERE SHALL BE NO INK ON ANY LAND THE 008 LAYER 1 TRACES TO 50 OHM SINGLE ENDED IMPEDANCE AND THE 007 TRACES LAYER 1 TO BE 100 OHM DIFFERENTIAL IMPEDANCE AND THE DIELECTRIC REFERENCED IN BOARD STACK DETAIL IS SUGGESTED HOWEVER TRACE WIDTHS AND OR DIELECTRIC THICKNESS
10. mars e e e Nr 6 25 umm 24 DOUT g 5 E Cn on s RID slelelelele e ASSY 059008241 USB TX DEMO S N WZ SSS MADE IN U S A PWE DS90UR241 USB TX DEMO TOP VIEW BOTTOMSIDE VIEW National Semiconductor Corporation Date 5 8 2008 Page 31 of 36 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual SS WY PRIMARY COMPONENT SIDE LAYER 1 SECONDARY COMP SIDE LAYER 4 el GROUND VSS 2 m HM ee oe He nin 9989 KL es g 98 en of e e HUHH PRIMARY SIDE 1 AL 2 National Semiconductor Corporation VDD 3 SECONDARY COMP SIDE SOLDER MASK LAYER 4 Date 5 8 2008 Page 32 of 36 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual 71 L AL _ SIDE 1 SECONDARY COMP SIDE SOLDER PASTE LAYER 4 4 m
11. t 1 m HOSSA ddd lHOLLOd W asn Date 5 8 2008 Page 24 0136 National Semiconductor Corporation SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual owg Asn x1 Lrzunoesa jueuna2oq pue Buidno4B 10 Jasp x wesGeig 1 aes 2 ay Jaye sped pue si0 i3ede3 ppe ue ajejndod un Jaisea si 3 jo aspa J0J pue au ur suogejedas 5 sasn e jou si sped 2215 g pue 2090 sJoyaede 022 92 esiou 10 Jou ui jo 2 510157521 0 1ua44nm3 jenpraipur 5 sasn Jou jo Asea sped 9215 Zoro FHL N
12. fail RxOUT 23 8 normal operation Randomizer OFF Randomizer ON Default Note DS90UR241 RAOFF MUST also be set High Default 2X slew rate 2X drive strength _ ___ Note DS90UR241 HAOFF MUST also be set Low Date 5 8 2008 Page 14 of 36 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual Output Monitor Pins for the De serializer Board JP3 Output Lock Monitor Receiver PLL LOCK Unlocked PLL LOCKED Note LED2 will DO NOT PUT A SHORTING illuminate gt JUMPER IN JP4 PASS Monitor Receiver BIST monitor PASS flag LED1 will Note illuminate if DO NOT PUT A SHORTING JUMPER IN JP1 JP4 JP4 LED a LED a National Semiconductor Corporation Date 5 8 2008 Page 15 of 36 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual JP1 JP2 USB Cable Assembly wire red and black JP1 Red wire in USB cable thru Red wire tied Red wire Red wire JP1 connector tied to VSS floating Jumper red wire to 55 Default not recommended recommended JP1 JP1 CAUTION VDD VDD eara ne HE short can occur VSS VSS Black wire in USB cable Black wire Black wire Black wire thru JP2 connector tied to 1 VSS floating Jumper black wire to VSS Default not recommended JP2 recommended JP2 JP2 CAUTION VDD VDD Jumper settings should be set the BLK BLK same on the DS90UR124 board or a short can occur VSS VSS
13. DESIGNS OR BUYER S USE OF TI REFERENCE DESIGNS TI reserves the right to make corrections enhancements improvements and other changes to its semiconductor products and services per JESD46 latest issue and to discontinue any product or service per JESD48 latest issue Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All semiconductor products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its components to the specifications applicable at the time of sale in accordance with the warranty in Tl s terms and conditions of sale of semiconductor products Testing and other quality control techniques for components are used to the extent deems necessary to support this warranty Except where mandated by applicable law testing of all parameters of each component is not necessarily performed assumes no liability for applications assistance or the design of Buyers products Buyers are responsible for their products and applications using Tl components To minimize the risks associated with Buyers products and applications Buyers should provide adequate design and operating safeguards Reproduction of significant portions of TI information in TI data books data sheets or reference designs is permissible only if reproduction is without alteration and is accompanied by all
14. JP1 and JP2 connections on connector J2 National Semiconductor Corporation Date 5 8 2008 Page 16 of 36 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual De serializer LVDS Pinout and LVCMOS by IDC Connector The following two tables illustrate how the LVDS inputs are mapped to the mini USB connector J2 and the Rx outputs are mapped to the IDC connector J3 Note labels are also printed on the demo boards for both the LVDS inputs and TTL outputs LVDS INPUT LVCMOS OUTPUT name RED ROUTO 3 5 ROUT 7 _ ROUT3 ROUT4 ROUT5 National Semiconductor Corporation Date 5 8 2008 Page 17 of 36 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual BOM Bill of Materials De serializer PCB DS90UR124 Rx USB Demo Board Board Stackup Revised Thursday September 14 2006 DS90UR124 Rx USB Demo Board Revision 1 Bill Of Materials September 14 2006 18 28 58 Item Qty Reference Part 1 2 2 1 0 1uF 2 2 C93 C7 C8 C9 C10 C11 C12 open0402 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C42 3 1 C4 2 2UF 4 1 C5 22uF 5 1 C6 0 1uF 6 8 C32 033 C34 C41 C47 C50 22uF C53 C54 7 8 C35 C38 C40 C43 C46 C48 0 1uF C52 C55 8 8 C36 C37 C39 C44 C45 C49 0 01uF C51 C56 9 2 JP2 JP1 3 Pin Header 10 2 JP4 JP3 2 Pin Header open 11 1 J mini USB 5pin open 12 1 J2 mini USB 5pin 13 1 J3 IDC2X25 Unshrouded 14 2 J4 J5 BANANA 15 1 LED1 0402 oran
15. Kit DS90UR241 124 USB Version 0 1 User Manual PeOR ASN x PZ 0650 153 ll et pepnoJusur Peo og jndjno pazis ppe ZPD LE2 2 2 soy jou aie 5 7 9707 papua ajBurs wyo 06 Bua paysjew W724 EZ 010108 L 310N YISA Ka 037 3207 BLLnOW BLLNOY ELLNON X128 Lino 810108 LAn OM S1nOM LLNOY 55 WM DW WX RRA RAR RRARAAR 32071 SLLNOY FLINOY ELLNOY OLLDOOM s lt SSA Date 5 8 2008 Page 30 of 36 National Semiconductor Corporation SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual Serializer Tx PCB Layout COPYRIGHT 2006 National Semiconductor C SHORT PRE EMPHASIS UR EMPTY m s
16. PC Graphics Board Video Processor Pixel Data DS90UR241 Video gt Serializer Source LVCMOS Video Processor Board Digital TMDS Input Digital Video Analog Input Graphics Controller Video NTSC PAL Input Decoder LVCMOS DS90UR124 y LVCMOS LCD Controller Timing Custom Logic DS90UR241 LCD Drivers Display LCD Monitor LCD TV Digital TV DE DS90UR124 Digital HSYNC _ 2 De Serializer Display HSYNC VSYNC L LVCMOS FPD LINKII LCD Monitor LCD TV Digital TV A Figure 1b Typical SERDES System Diagram National Semiconductor Corporation Date 5 8 2008 Page 4 of 36 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual Figures 1 1b illustrate the use of the Chipset Tx Rx in a Host to Flat Panel Interface The chipsets support up to 18 bit color depth LCD Panels Refer to the proper datasheet information on Chipsets Tx Rx provided on each board for more detailed information National Semiconductor Corporation Date 5 8 2008 Page 5 of 36 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual How to set up the Evaluation Kit The PCB routing for the serializer input pins DIN have been laid out to accept incoming LVCMOS signals from a 50 pin IDC connector The TxOUT RxIN DOUT RIN Interface u
17. be Not allowed tied low for normal operation Default Serializer Output Enabled Data ENabled Default VODSEL LVDS output 2350mV 00mV VOD SELect Default National Semiconductor Corporation Date 5 8 2008 Page 8 of 36 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual JP3 VR1 Pre Emphasis Feature Selection Reference Description OPEN CLOSED MEM floating Path to GND JP3 Pre Emphasis helps to Disabled Enabled increase the eye pattern no jumper With jumper opening in the LVDS stream Default Pre Emphasis adjustment Clockwise Counter via screw Clockwise JP1 MUST have a jumper to use potentiometer VR1 VR1 00 to 20 JP1 6 26 increases decreases 6KQ maximum pre Rpre value Rpre value emphasis to which which 26KQ minimum pre decreases increases emphasis pre pre IpRE 1 2 x 40 emphasis emphasis HPRE minimum gt maximum is based on resistor value In this case 26 value is based on the 6kQ fixed resistor plus 20K maximum potentiometer value User can use hundreds of Kohms to reduce the pre emphasis value Pre emphasis user note Pre emphasis must be adjusted correctly based on application frequency cable quality cable length and connector quality Maximum pre emphasis should only be used under extreme worse case conditions for example at the upper frequency
18. board provides the interface connection to the LVDS signals to the de serializer board 4 J5 Note VDD and VSS MUST be applied externally from here 3 National IW Semiconducto Connect cable USB A side oO to 2 on BACKSIDE 9 RM 5 DOUT g 28 pre D P1 TOPSIDE eto 1 UNSTUFFED R20 Ura eo 5555 ee D LVDS OUTPUTS 2 LVCMOS INPUTS 3 FUNCTION CONTROLS 4 SUPPLY 51 SERDESUR 43USB 059008241 TX ASSY 059018241 USB TX DEMO REV National Semiconductor Corporation Date 5 8 2008 Page 7 of 36 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual Configuration Settings for the Serializer Board Not allowed RESRVDA 1 51 Serializer Input Features Selection Reference Description Input L __ St RESRVDA RESeRVeD MUST be Not allowed tied low for normal operation Default RESRVDB RESeRVeD B MUST be tied low for normal operation Default TPWDNB PoWerDowN Bar Powers Normal Down operation Default TRFB Latch input data Falling Rising on Rising or Edge Edge Falling edge of Default RAOFF RAndomizer OFF Randomizer Randomizer ON OFF Default Note Note DS90UR124 DS90UR124 RAOFF MUST RAOFF MUST also be set also be set Low High RESRVD RESeRVeD MUST
19. specification of the part and or low grade cables at maximum cable lengths Typically all that is needed is minimum pre emphasis Users should start with no pre emphasis first and gradually apply pre emphasis until there is clock lock and no data errors The best way to monitor the pre emphasis effect is to hook up a differential probe to the 1000 termination resistor R1 on the DS90UR124 Rx demo board NOT to R27 on the DS90UR241 Tx demo board The reason for monitoring R1 on the Rx side is because you want to see what the receiver will see the attenuation signal AFTER the cable connector National Semiconductor Corporation Date 5 8 2008 Page 9 of 36 1 JP2 USB Cable Assembly RED wire and BLK wire Reference JP1 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual RED wire in USB cable thru P1 connector Jumper RED to VSS recommended CAUTION Jumper settings should be set the same on the 059008124 board or a short can occur BLACK wire in USB cable thru P1 connector Jumper BLACK to VSS recommended CAUTION Jumper settings should be set the same on the 059008124 board or a short can occur JP1 and JP2 connections on connector P1 HED wire tied to VDD JP VSS BLACK wire tied to VDD VDD 2 BLK VSS National Semiconductor Corporation RED wire tied to VSS Default 2 VDD RED VSS BLACK wire tied to VSS Default RED wire floating no
20. ves 005 WEB el NOTES UNLESS OTHERWISE SPECIFIED 1 4 PRIMARY COMPONENT SIDE IS SHOWN HOLES MARKED ARE TOOLING HOLES UNPLATED AND SHALL BE ONCE DRILLED FABRICATE USING MASTER FILM DS90UR241 USB TX DEMO REV 1 USE GERBER FILE 467 FOR BOARD ROUTE ACCEPTABILITY SHALL BE BASED ON IPC A 600 CLASS 2 MATERIAL BASE MATERIAL IS NEMAL 1 GRADE 406 COLOR GREEN 0 062 INCH NOM THICKNESS COPPER CLADDING SHALL BE 1 2 02 FOR OUTSIDE LAYERS AND 1 OZ FOR INSIDE LAYERS PLATING ALL HOLES AND CONDUCTIVE SURFACES SHALL BE PLATED WITH A MIN OF 001 INCH COPPER SURFACE FINISH ELECTROLESS NICKEL IMMERSION GOLD FABRICATION TOLERANCES END PRODUCT CONDUCTOR WIDTHS AND LAND DIAMETERS SHALL NOT VARY MORE THAN 002 INCH FROM THE 1 1 DIMENSIONS OF THE MASTER PATTERN THE CONDUCTIVE PATTERN SHALL BE POSITIONED SO THAT THE LOCATION OF ANY LAND SHALL BE WITHIN 010 INCH DIAMETER TO THE TRUE POSITION OF THE HOLE IT CIRCUMSCRIBES THE MINIMUM ANNULAR RING SHALL BE 002 INCH BOW AND TWIST SHALL NOT EXCEED 010 INCH PER INCH SOLDERMASK BOTH SIDES PER 5 840 A CLASS COLOR GREEN THERE SHALL NO SOLDERMASK ON ANY LAND SILKSCREEN THE LEGEND ON BOTH SIDES USING NON CONDUCTIVE EPOXY INK COLOR WHITE THERE SHALL BE NO INK ON ANY LAND THE 008 TRACES LAYER 1 TO BE 50 OHM SINGLE ENDED INPEDANCE THE 007 TRACES LAYER 1 TO BE 100 OHM DIFFERENTIAL I
21. 6 T5 u m 22 25 H oe m H I m ee om H i 1 w B H m Zt 85 H 2 ee m eei Ze 99 a Z mes e 5 wass 099001 eccoon es HHR 2 HHPEZ 122 9 00 e e e an D 0430 82U 500220 BW o o SECONDARY COMP SIDE LAYER 4 PRIMARY COMP SIDE SOLDER MASK LAYER 1 SECONDARY COMP SIDE SOLDER MASK LAYER 4 National Semiconductor Corporation Date 5 8 2008 Page 36 of 36 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual T 71 Gb ERE SECONDARY COMP SIDE SOLDER PASTE LAYER 4 L PRIMARY COMP SIDE SOLDER PASTE LAYER 1 ELLE vop 4 33 vss uz National Semiconductor al EM 3 05 eL eL trat ta Tac gar mr i a CATA _ U 53 B How a RRFB iiu m COPYRIGHT C 2006 MADE IN U S A Dk o LEW SERDESUR 4J3USB 059018124 RX S N PRIMARY COMP SIDE SILKSCREEN LAY
22. 90UR124 de serializer board accepts the LVDS serialized data stream with embedded clock and converts the data back into parallel LVCMOS signals and clock Note that NO reference clock is needed to prevent harmonic lock as with other devices currently on the market Suggested equipment to evaluate the chipset an LVCMOS signal source such as a video generator or word generator or pulse generator and oscilloscope with a bandwidth of at least 43 MHz will be needed The user needs to provide the proper LVCMOS RGB inputs and LVCMOS clock to the serializer and also provide a proper interface from the de serializer output to an LCD panel or test equipment The serializer and de serializer boards can also be used to evaluate device parameters A cable conversion board or harness scramble may be necessary depending on type of cable connector interface used on the input to the DS90UR2441 and to the output of the DS90UR124 Example of suggested display setup 1 video generator with LVCMOS output 2 6 bit LCD panel with a LVCMOS input interface National Semiconductor Corporation Date 5 8 2008 Page 3 of 36 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual Contents of the Evaluation Kit 1 One Serializer board with the DS90UR241 2 One De serializer board with the DS90UR124 3 One 2 meter USB 2 0 Hi SPEED cable assembly 4 Evaluation Kit Documentation this manual 5 DS90UR241 124 Datasheet SERDES Typical Application Host
23. B 5pin open USB A 49 90hm open 49 90hm open 5 76 100 0402 0 10 SW 8 DS90UR241 SVR20K 0402 National Semiconductor Corporation PCB Footprint CAP HDC 0402 3528 21 1206 CAP EIA B 3528 21 0603 0603 Header 3P Header 2P IDC 50 CON BANANA S mini USB surface mount USB TYPE 4P RES HDC 0201 RES HDC 0805 RES HDC 0402 RES HDC 0402 RES HDC 0201 RES HDC 0805 DIP 16 48 Id TQFP Surface Mount 4mm Square TP 0402 Date 5 8 2008 Page 12 of 36 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual Rx SERDES De serializer Board The USB connector J2 provides the interface connection for LVDS signals to the serializer board The SERDES de serializer board is powered externally from the J4 VDD and J5 VSS connectors shown below For the de serializer to be operational the Power Down RPWDNB and Receiver Enable REN switches on 51 52 must be set HIGH Rising or falling edge reference clock is also selected by 51 HIGH rising or LOW falling The 50 pin IDC Connector J3 provides access to the 24 bit LVCMOS and clock outputs 4 Ja 5 Note Vcc and Gnd MUST be applied externally here 2 e National Semiconductor 2 Os 33 2 JP3 8 ag is gt un 9 D ye 3 a 2 OD LVDS INPUTS UNSTUFF
24. COPE with a bandwidth of at least 43 MHz for TTL and or 2 GHz for looking at the differential signal LVDS signals may be easily measured with high impedance high bandwidth differential probes such as the P6330 differential probes National Semiconductor Corporation Date 5 8 2008 Page 19 of 36 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual The picture below shows a typical test set up using a Graphics Controller and LCD Panel Transmitter Receiver Board nee r FPD LINKII 5 LCD Panel Digital RGB TTL r4 LVDS interface RGB Contoller Nc me Cable le to L Contents of Demo Kit Graphics Controller Video Processor Board f 1 Figure 2 Typical SERDES Setup of LCD Panel Application The picture below shows a typical test set up using a generator and scope
25. DS90UR241 124 USB Version 0 1 User Manual Note Please note that the following references are supplied only as a courtesy to our valued customers It is not intended to be an endorsement of any particular equipment or hardware supplier Connector References Hirose Electric Europe B V Beech Avenue 46 1119 PV Schiphol Rijk The Netherlands Phone 31 20 655 7467 Fax 31 20 655 7469 www HiroseEurope com Cable References Nissei Electric Co LTD 1509 Okubo Cho Hamamatsu City Shizuoka Pref 432 8006 Japan Phone 81 53 485 4114 Fax 81 53 485 6908 www nissei el co p Cable Recommendations For optimal performance we recommend Shielded Twisted Pair STP 1000 differential impedance cable for high speed data applications Equipment References Astro Systems 425 S Victory Blvd Suite A Burbank CA 91502 Phone 818 848 7722 Fax 818 848 7799 www astro systems com Digital Video Pattern Generator Astro Systems VG 835 or equivalent Extra Component References TDK Corporation of America 1740 Technology Drive Suite 510 san Jose CA 95110 Phone 408 437 9585 Fax 408 437 9591 www component tdk com Optional EMI Filters TDK Chip Beads or equivalent National Semiconductor Corporation Date 5 8 2008 Page 22 of 36 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual gsn xL brewnossd Jequinw mawnog _
26. ER 1 ASSY 059008124 Rx USB DEMO REV JL 5 W 5 u 4 RE m 88 108 e uv T 27 7 d SILKSCREEN COMP SIDE SILKSCREEN LAYER 4 National Semiconductor Corporation Date 5 8 2008 Page 37 of 36 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual Deserializer Rx PCB Stackup SILKSCREEN A55Y SIDE 1 ASSEMBLY SIDE 1 ASSY SIDE 1 COMP SIDE 1 2 02 H 0045 ne PLANE 1 02 LAYER 2 A CORE 0 PWR PLANE TOL LAYER 3 052 007 PREPREG 0045 Z ASSEMBLY SIDE 2 SILKSCREEN 55 SIDE 2 SOLDERMASK ASSY SIDE 2 Lm od 4 500 QOOQO OO OO HO HO OQ HOHO HO HO OHOHOHOHGROROHOHO OR QOO GO OO HOHOHO OO OHO GO HOHOHOHOHOHGHOHGHOHOHOR 490 06 R 4 PLCS 3 000 NATIONAL SEMICONDUCTOR CORP SERDESUR 43USB 059008124 RX USB DEMO BOARD PWE DS90UR124 RX USB DEMO REV 1 DRILL DRAWING 0 450 National Semiconductor Corporation LAYER 1 SOLDER SIDE 72 02 LAYER 4 3 sue to 006 0 ves 005 0035 2 vs o lt gt os se ves 003 zz sz gas E ons 3 wo 4 003 5 20 1 0265 2 ves 005 ER NOTES UNLESS OTHERWISE SPECIFIED 1 2 PRIMARY COMPONENT SIDE 15 SHOWN
27. MPEDANCE AND THE DIELECTRIC REFERENCED IN BOARD STACK DETAIL IS SUGESTED HOWEVER TRACE WIDTHS AND OR DIELECTRIC THICKNESS MAY BE MICRO MODIFIED IN ORDER TO FABRICATE BOARDS TO THE REQUIRED IMPEDANCE NOMINALS TO TOLERANCE OF 5x BOARD TO BE FABRICATED IN COMPLIANCY TO ROHS REQUIREMENTS Date 5 8 2008 Page 34 of 36 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual Deserializer Rx PCB Layout 8111 J6 VD SS um 2 4 LED1 National Semiconductor RENT x VSS VDD eo E cw i eemo e 0 mt e 8 muc e e 8 E e 8 xc 6 vss 00 Ri Hac EE ROO e xc e 8 xc e 27 e i 21 e e 5 COPYRIGHT 2006 xc MADE U S A Eas i 55 32m 32 49 Ca RO cx lt 4 Ca c mk m TOP VIEW BOTTOMSIDE VIEW National Semiconductor Corporation Date 5 8 2008 Page 35 of 36 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual IL d PRIMARY COMPONENT SIDE LAYER 1 GROUND PLANE VSS LAYER 2 POWER PLANE VDD LAYER 3 8 al 00070990 4 H ee ee H 5 S 1 c ci 42 me 2
28. O SNOILdO SIUNL v33 o Suid Jeau aded aaa BJ SSA zz uid 3003010 dange OL bl uid Inge 04d 00A 4 suid Jeau aoe Date 5 8 2008 Page 25 of 36 National Semiconductor Corporation SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual wyo g peog owg gsn x Jaquiny jou Og asinos 05 20 vondo 2 sa3e4 pepua ajBurs wyo 06 Bual payajew 724 62 0 L 310N pepnouusury 121 ATL LZNIO lt lt Eos lt lt SA lt lt T lt lt LINIO lt lt ECTS PINO lt lt lt ZINIO KO lt lt lt lt ening N0 lt NIQ lt lt lt lt lt lt TNI ri r rj rj Date 5 8 2008 Page 26 of 36 National Semiconductor Corporation SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual De serializer Rx PCB S
29. SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual National Semiconductor SERDES Demonstration Kit User Manual Rev 0 2 NSID SERDESUR 43USB National Semiconductor Corporation UU ate 5 8 2008 age 1 of 36 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual Table of Contents TABEE OPCONTENTPS dac u l 2 INTRODUC TION uuu i kuka ai kami iha i hu n O S 3 CONTENTSOFTHEEVALUATION KI GIS 4 SERDES TYPICAL APPLICATION L L 1 L u 4 HOW SET UP THE EVALUATION KIT 6 POWER CONNECTION 6 SERDES SERIALIZER BOARD DESCRIPTION 7 CONFIGURATION SETTINGS FOR THE SERIALIZER BOARD 8 SERIALIZER LVCMOS AND LVDS PINOUT BY IDC CONNECTOR 11 BIL OF VIATERIAUS SERIALIZER PG 12 RX SERDES DE SERIALIZER BOARD
30. associated warranties conditions limitations and notices Tl is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Buyer acknowledges and agrees that it is solely responsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards that anticipate dangerous failures monitor failures and their consequences lessen the likelihood of dangerous failures and take appropriate remedial actions Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any Tl components Buyer s safety critical applications In some cases components be promoted specifically to facilitate safety related applications With such components Tl s goal is to help enable customers to design and create their own end product solutions that meet applicable functional safety standards and requirements Nonetheless such components are subject to these terms No components are authorized for use in FDA Class Ill or similar life critical medical equipment unless authorized officers of the parties have executed an agreement specifically governing such use Only tho
31. chematic 19244 9002 FL Jequejdes E oo Hegg uwag 5 X Pe kf 10650 2105 p n3 zo z I eprs 90P uH4 Pas 4 sseuxoruL 5700 0 zo 9S0P H4 PIS 2 zo eue d 0r ui sseuxoruri 5 00 0 ES 222200 zo L b y E c Date 5 8 2008 Page 27 of 36 National Semiconductor Corporation SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual eouepedu uuo 06 88225244 E x ct 9 Er 5 jc TEPEEPTEFEEERTEF 2 SSSSEESSPOEEEEZ 25080228 22 20 OOCOOUU 5 re eee 0 0 i c e e 9 em O aL simmog 229 2 e O gt 22 g 5 5 ino 1 islinow Ly _tes 5 g E aino SLOH BLLNOY oO of 5170 Shoe slinow a HOSSA gt 85 a ino
32. ge LED 16 1 LED2 0603 green LED 17 1 R1 100 ohm 0402 18 9 R2 R3 R4 R34 R35 R36 R37 10K R38 R39 19 1 S1 SW DIP 3 20 1 52 SW 6 21 1 Ul DS90UR124 National Semiconductor Corporation PCB Footprint CAP HDC 0402 CAP HDC 0402 3528 21 EIA CAP N CAP HDC 1206 CAP EIA B 3528 21 CAP HDC 0603 CAP HDC 0603 Header 3P Header 2P mini USB surface mount mini USB surface mount IDC 50 CON BANANA S 0402 0603 Super Thin RES HDC 0402 RES HDC 0805 DIP 6 DIP 12 64 pin TQFP Date 5 8 2008 Page 18 of 36 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual Typical Connection and Test Equipment The following is a list of typical test equipment that may be used to generate signals for the inputs 1 Digital Video Source for generation of specific display timing such as Digital Video Processor or Graphics Controller with digital RGB LVCMOS output 2 Astro Systems VG 835 This video generator may be used for video signal sources for 6 bit Digital TTL RGB 3 Any other signal video generator that generates the correct input levels as specified the datasheet 4 Optional Logic Analyzer or Oscilloscope The following is a list of typically test equipment that may be used to monitor the output signals from the 1 LCD Display Panel which supports digital RGB LVCMOS inputs 2 National Semiconductor DS90UR241 Serializer Tx 3 Optional Logic Analyzer or Oscilloscope 4 Any S
33. inimum ROUT loading Verify input clock and input data signals meet requirements for VILmin max ViHmin tset thold also that data is strobed on the selected rising falling RFB pin edge of the clock 4 Check that the Jumpers and Switches are set correctly 5 Check that the cable is properly connected TROUBLESHOOTING CHART Problem There is only the output clock There is no output data No output data and clock Power ground input data and input clock are connected correctly but no outputs The devices are pulling more than 1A of current After powering up the demo boards the power supply reads less than when it is set to 3 3V National Semiconductor Corporation Solution Make sure the data is applied to the correct input pin Make sure data is valid at the input Make sure Power is on Input data and clock are active and connected correctly Make sure that the cable is secured to both demo boards Check the Power Down pins of both Serializer and De serializer boards to make sure that the devices are enabled PD Vcc for operation Also check DEN on the Serializer board and REN on the Deserializer board is set HIGH Check for shorts in the cables connecting the TX and RX boards Use a larger power supply that will provide enough current for the demo boards a 500mA minimum power supply is recommended Date 5 8 2008 Page 21 of 36 SERDES Evaluation Kit
34. n National Semiconductors SERDES evaluation kit contains one 1 DS90UR241 Serializer Tx board one 1 DS90UR124 De serializer Rx board and one 1 generic two 2 meter USB 2 0 Hi SPEED cable assembly National is not recommending using the USB 2 0 Hi SPEED cable assembly but is provided in this kit as a generic solution to show the robustness of the chipset Note the demo boards are not for EMI testing The demo boards were designed for easy accessibility to device pins with tap points for monitoring or applying signals additional pads for termination and multiple connector options The DS90UR241 124 chipset supports a variety of display applications The single L VDS interface is well suited for any display system interface Typical applications include navigation displays automated teller machines ATMs POS video cameras global positioning systems GPS portable equipment instruments factory automation etc The 05900 241 059008124 can be used as a 24 bit general purpose LVDS serializer and De serializer chipset designed to transmit data at clocks speeds ranging from 5 to 43 MHz The DS90UR244 serializer board accepts LVCMOS input signals The LVDS Serializer converts the LVCMOS parallel lines into a single serialized LVDS data pair with an embedded LVDS clock The serial data stream toggles at 28 times the base clock rate With an input clock at 43 MHz the transmission rate for the LVDS line is 1 204Gbps The DS
35. ork right or other intellectual property right relating to any combination machine or process in which TI components or services are used Information published by TI regarding third party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI TI REFERENCE DESIGNS ARE PROVIDED AS IS TI MAKES NO WARRANTIES OR REPRESENTATIONS WITH REGARD TO THE REFERENCE DESIGNS OR USE OF THE REFERENCE DESIGNS EXPRESS IMPLIED OR STATUTORY INCLUDING ACCURACY OR COMPLETENESS TI DISCLAIMS ANY WARRANTY OF TITLE AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE QUIET ENJOYMENT QUIET POSSESSION AND NON INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS WITH REGARD TO TI REFERENCE DESIGNS OR USE THEREOF TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY BUYERS AGAINST ANY THIRD PARTY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON A COMBINATION OF COMPONENTS PROVIDED IN A TI REFERENCE DESIGN IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL SPECIAL INCIDENTAL CONSEQUENTIAL OR INDIRECT DAMAGES HOWEVER CAUSED ON ANY THEORY OF LIABILITY AND WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES ARISING IN ANY WAY OUT OF TI REFERENCE
36. ough Power Jack VDD Grounds for both boards are connected through Power Jack VSS see section below Power Connection The serializer and de serializer boards must be powered by supplying power externally through J4 VDD and J5 VSS on serializer Board and J4 VDD and J5 VSS on de serializer board Note 4V is the absolute MAXIMUM voltage not operating voltage that should ever be applied to the SERDES serializer 059008241 or de serializer DS90UR124 VDD terminal Damage to the device s can result if the voltage maximum is exceeded National Semiconductor Corporation Date 5 8 2008 Page 6 of 36 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual SERDES Serializer Board Description 50 pin IDC connector J1 accepts 24 bits of LVCMOS data DIN0 DIN23 along with the clock input TCLK The SERDES serializer board is powered externally from the J4 VDD and J5 VSS connectors shown below For the serializer to be operational the Power Down 51 TPWDNB and Data Enable S1 DEN switches on S1 must be set HIGH Rising or falling edge reference clock is also selected on S1 TRFB HIGH rising or LOW falling FPD LINKII is an AC coupled LVDS series 0 1uF capacitors on each side of the LVDS serializer outputs and de serializer inputs JP1 and JP2 are configured from the factory to be shorted to VSS these are the unused power wires in the cable harness The USB connector P2 on the backside of the
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38. ses a USB connector cable assembly provided The PCB routing for the Rx output pins ROUT are accessed through a 50 pin IDC connector Please follow these steps to set up the evaluation kit for bench testing and performance measurements 1 two 2 meter USB connector cable assembly has been included in the kit Connect 4 pin USB A A side of cable harness to the serializer board and the other side 5 pin mini USB jack to the de serializer board This completes the LVDS interface connection NOTE The DS90C241 and DS90C124 are NOT USB compliant and should not be plugged into a USB device nor should a USB device be plugged into the demo boards 2 Jumpers and switches have been configured at the factory they should not require any changes for immediate operation of the chipset See text on Configuration settings for more details From the Video Decoder board connect a flat cable not supplied to the Serializer board and connect another flat cable not supplied from the De serializer board to the panel Caution The LVCMOS input levels should be within the specified range for optimal performance not to exceed the absolute maximum rating of 0 3V to 0 3V Note For 50 ohm LVCMOS input signal sources add 50 ohm parallel termination resistors R1 R25 on the DS90UH241 Serializer board and provide appropriate 3 3V LVCMOS input signal levels into DIN 23 0 and TCLK 3 Power for the Tx and Rx boards must be supplied externally thr
39. t recommended JP1 RED VSS BLACK wire floating not recommended VDD JP2 VSS Date 5 8 2008 Page 10 of 36 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual Serializer LVCMOS and LVDS Pinout by IDC Connector The following two 2 tables illustrate how the serializer inputs are mapped to the IDC connector J1 the LVDS outputs on the USB connector P2 pinout Note labels also printed on the demo boards for both the T TL input and LVDS outputs LVCMOS INPUT LVDS OUTPUT name P2 pin no National Semiconductor Corporation Date 5 8 2008 Page 11 of 36 SERDES Evaluation Kit DS90UR241 124 USB Version 0 1 User Manual BOM Bill of Materials Serializer PCB DS90UR241 Tx USB Demo Board Board Stackup Revised Friday September 15 2006 DS90UR241 Tx USB Demo Board Bill Of Materials September 15 2006 Item Qty Reference WD k P m 15 16 17 18 19 20 21 22 23 C1 C2 C3 C4 C5 C6 C9 C10 C13 C20 C7 C11 C15 C16 C19 C8 C12 C14 C17 C18 JP2 JP1 JP3 J1 J5 J4 P1 P2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R29 R38 R39 R40 R41 R42 R43 R44 R45 51 U1 VR1 X2 X1 Revision 1 19 21 34 Part 0 1UF 2 2uF 22uF 0 1uF 22uF 0 01uF 0 1uF 3 Pin Header 2 Pin Header IDC2X25 Unshrouded BANANA mini US
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