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User`s Manual 01.97 Microcontroller Family Architecture and

1. 210 2 A BID 44x o0 2 A B D H 4x A EB S N eie es i 444 lji E Index Marking 1 0 6x45 1 Does not include plastic or metal protrusion of 0 25 max per side GPM05622 SMD Surface Mounted Device Dimensions in mm Figure 5 5 P MQFP 44 2 Package Outline Semiconductor Group 5 5 S EMENS Package Information C500 Family P MOFP 80 1 SMD Plastic Metric Quad Flat Package 58 Bey a Qa 2 IH oo x o al Oz KA Y mm ASIR RS IMEEM T Pi 2 35 G aa o 10 08 9 a 0 12 MA B D C 80x TTT a n gl 172 ili i O iji 1 1 Va 80 Index Marking 0 6x45 1 Does not include plastic or metal protrusion of 0 25 max per side GPM05249 SMD Surface Mounted Device Dimensions in mm Figure 5 6 P MQFP 80 1 Package Outline Semiconductor Group 5 6 S EMENS Package Information C500 Family
2. C500 Family 4 4 2 Hexadecimal Ordered Instructions Table 4 4 Instruction List in Hexadecimal Order Op Mnemonic Op Mnemonic Op Mnemonic Code Code Code 00H NOP 20H JB bit rel 404 JC rel 014 AJMP adodril 21H AJMP addr11 414 AJMP addr11 024 LJMP addr16 22H RET 424 ORL direct A 03H IRR A 234 RL A 434 ORL direct data 04H INC A 24H ADD A data 444 ORL A data 054 INC direct 254 ADD Agirect 454 ORL A direct 06H INC RO 264 ADD A RO 46H ORL A RO 074 INC RI 274 ADD A RI 474 ORL A RI 08H INC RO 28H ADD A RO 48H ORL A RO 094 INC R1 29H ADD A RI 494 ORL A R1 OAH INC R2 2AH ADD A R2 4AH ORL A R2 OBy INC R3 2By ADD A R3 4By ORL A R3 OCH INC R4 2CH ADD A R4 4Cy ORL A R4 ODH INC R5 2DH ADD ARS 4Dy ORL A R5 OEy INC R6 2Ey ADD A R6 4Ey ORL A R6 OFH INC R7 2FH ADD A R7 4FH ORL A R7 10H JBC bitrel 304 JNB bit rel 504 JNC rel 11H ACALL addr11 314 ACALL addr11 514 ACALL addr11 12H LCALL addr16 32H RETI 524 ANL direct A 134 RRC A 334 RLC A 53H ANL direct data 144 DEC A 34H ADDC A data 54H ANL A fdata 154 DEC direct 35H ADDC A direct 55H ANL Agirect 164 DEC RO 364 ADDC A R0 56H ANL A RO 174 DEC RI 37H ADDC A RI 574 ANL A RI 184 DEC RO 38H ADDC A RO 58H ANL A R0 19H DEC Ri 39H ADDC A RI 594 ANL A R1 1AH DEC R2 3AY ADDC A R2 SAW ANL A R2 1BH DEC R3 3BH ADDC A R3 5BH ANL A R3 1CH DEC R4 3CH ADDC A R4 5CH ANL A R4 1
3. Encoding 1100 011i Bytes 1 Cycles 1 Semiconductor Group 4 77 S EMENS Instruction Set C500 Family XCHD A Ri Function Description Example Operation Encoding Bytes Cycles Exchange digit XCHD exchanges the low order nibble of the accumulator bits 3 0 generally representing a hexadecimal or BCD digit with that of the internal RAM location indirectly addressed by the specified register The high order nibbles bits 7 4 of each register are not affected No flags are affected RO contains the address 20H The accumulator holds the value 364 00110110p Internal RAM location 204 holds the value 75 4 01110101p The instruction XCHD A RO will leave RAM location 204 holding the value 764 01110110 and 35H 00110101p in the accumulator XCHD A3 0 S Ri 3 0 1101 0111 Semiconductor Group 4 78 S EMENS Instruction Set C500 Family XRL lt dest byte gt lt src byte gt Function Logical Exclusive OR for byte variables Description XRL performs the bitwise logical Exclusive OR operation between the indicated variables storing the results in the destination No flags are affected The two operands allow six addressing mode combinations When the destination is the accumulator the source can use register direct register indirect or immediate addressing when the destination is a direct address the source can be accumulator or i
4. 11x45 m 2421 007 9 5 i 1 0 05 A B D de 1 Does not include plastic or metal protrusion of 0 15 max per side GPL5099 SMD Surface Mounted Device Dimensions in mm Figure 5 3 P LCC 68 4 Package Outline Semiconductor Group 5 3 S EMENS Package Information C500 Family P LCC 84 2 SMD Plastic Leaded Chip Carrier Package 0 5 MIN 3 81405 gt JO A 1 27 i i 3 43101 DE 28 2 105 049 0 18 84x olod ni 25 4 xi I Bla S f F a D N amp 8 tj 84 1 114 x 45 Index Marking 29 31 0076 30 23 0 8 gt 1 Does not include plastic or metal protrusion of 0 25 max per side 2 Dimension from center to center GPM05620 SMD Surface Mounted Device Dimensions inmm Figure 5 4 P LCC 84 2 Package Outline Semiconductor Group 5 4 S EMENS Package Information C500 Family 5 3 MQFP Packages P MQFP 44 2 SMD Plastic Metric Quad Flat Package zl 4 se Sa amp a H FF x I e 1 a A 1 e 3 JAH Str 0 8_ __ M JI 0 880 4015 pe 210 1 BES 610 2 WA B D C 44x
5. Intel Corporation 1980 Semiconductor Group 4 8 S EMENS Instruction Set C500 Family ACALL addr11 Function Description Example Operation Encoding Bytes Cycles Absolute call ACALL unconditionally calls a subroutine located at the indicated address The instruction increments the PC twice to obtain the address of the following instruction then pushes the 16 bit result onto the stack low order byte first and increments the stack pointer twice The destination address is obtained by successively concatenating the five high order bits of the incremented PC op code bits 7 5 and the second byte of the instruction The subroutine called must therefore start within the same 2K block of program memory as the first byte of the instruction following ACALL No flags are affected Initially SP equals 07 4 The label SUBRTN is at program memory location 034514 After executing the instruction ACALL SUBRTN at location 012344 SP will contain 094 internal RAM location 084 and 094 will contain 25y and 01H respectively and the PC will contain 03454 ACALL PC PC 2 SP SP 1 SP PC7 0 SP SP 1 SP PC15 8 PC10 0 page address al0 ad a8 1 000 1 a a6 ab a4 a3 a2 al a0 Semiconductor Group 4 9 S EMENS Instruction Set C500 Family ADD A lt src byte gt Function Add Description ADD adds the byte
6. Move external The MOVX instructions transfer data between the accumulator and a byte of external data memory hence the X appended to MOV There are two types of instructions differing in whether they provide an eight bit or sixteen bit indirect address to the external data RAM In the first type the contents of RO or R1 in the current register bank provide an eight bit address multiplexed with data on PO Eight bits are sufficient for external O expansion decoding or a relatively small RAM array For somewhat larger arrays any output port pins can be used to output higher order address bits These pins would be controlled by an output instruction preceding the MOVX In the second type of MOVX instructions the data pointer generates a sixteen bit address P2 outputs the high order eight address bits the contents of DPH while PO multiplexes the low order eight bits DPL with data The P2 special function register retains its previous contents while the P2 output buffers are emining the contents of DPH This form is faster and more efficient when accessing very large data arrays up to 64 Kbyte since no additional instructions are needed to set up the output ports It is possible in some situations to mix the two MOVX types A large RAM array with its high order address lines driven by P2 can be addressed via the data pointer or with code to output high order address bits to P2 followed by a MOVX instruction using RO or R1 A
7. Initialization Routine MOV DPSEL 06H Initialize DPTR6 with source pointer MOV DPTR 1FFFH MOV DPSEL 07H Initialize DPTR7 with destination pointer MOV DPTR 2FAOH Table Look up Routine under Real Time Conditions Number of cycles PUSH DPSEL Save old source pointer 2 MOV DPSEL 06H Load source pointer 2 INC DPTR Increment and check for end of table execution time CJNE not relevant for this consideration MOVC A DPTR Fetch source data byte from ROM table 2 MOV DPSEL 07H Save source pointer and load destination pointer 2 MOVX DPTR A Transfer byte to destination address 2 POP DPSEL Save destination pointer and restore old datapointer 2 Total execution time machine cycles 12 The above example shows that utilization of the C500 s multiple datapointers can make external bus accesses two times as fast as with a standard 8051 or 8051 derivative Here four data variables in the internal RAM and two additional stack bytes were spared too This means for some applications where all eight datapointers are employed that an C500 program has up to 24 byte 16 variables and 8 stack bytes of the internal RAM free for other use Semiconductor Group 2 8 CPU Functions SIEMENS C500 Family 2 6 Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new innovative way to control the execution of C500 MCUs and to gain extensive information on the intern
8. MOV P1 3 C MOV C P3 3 MOV P1 2 C will leave the carry cleared and change port 1 to 394 00111001p MOV C bit Operation MOV C lt bit Encoding 1010 0010 bit address Bytes 2 Cycles 1 MOV bit C Operation MOV bit C Encoding 1001 0010 bit address Bytes Cycles 2 Semiconductor Group 4 51 SIEMEN Instruction Set x C500 Family MOV DPTR data16 Function Load data pointer with a 16 bit constant Description The data pointer is loaded with the 16 bit constant indicated The 16 bit constant is loaded into the second and third bytes of the instruction The second byte DPH is the high order byte while the third byte DPL holds the low order byte No flags are affected This is the only instruction which moves 16 bits of data at once Example The instruction MOV DPTR 1234H will load the value 1234y into the data pointer DPH will hold 124 and DPL will hold 34H Operation MOV DPTR data15 0 DPH O DPL data15 8 O data7 0 Encoding 1001 0000 immed data 15 8 immed data 7 0 Bytes Cycles Semiconductor Group 4 52 S EMENS Instruction Set C500 Family MOVC A GA lt base reg gt Function Description Example Move code byte The MOVC instructions load the accumulator with a code byte or constant from program memory The address of the byte fetched is the sum of the original unsigned eight bit accumulator contents and the co
9. jumpif bitis not set jump if bit is set and clear bit move bit from to carry Addressable bits or their complements may be logically AND ed or OR ed with the contents of the carry flag The result is returned to the carry register Semiconductor Group 4 2 SIEMEN Instruction Set s C500 Family 4 2 Introduction to the Instruction Set The instruction set is divided into four functional groups data transfer arithmetic logic control transfer 4 2 1 Data Transfer Instructions Data transfer operations are divided into three classes general purpose accumulator specific address object None of these operations affects the PSW flag settings except a POP or MOV directly to the PSW General Purpose Transfers MOV performs a bit or byte transfer from the source operand to the destination operand PUSH increments the SP register and then transfers a byte from the source operand to the stack location currently addressed by SP POP transfers a byte operand from the stack location addressed by the SP to the destination operand and then decrements SP Accumulator Specific Transfers XCH exchanges the byte source operand with register A accumulator XCHD exchanges the low order nibble of the source operand byte with the low order nibble of A MOVX performs a byte move between the external data memory and the accumulator The external address can be specified by the DPTR register 16
10. JMP A DPTR 934 MOVC A A DPTR B3y CPL 74H MOV A data 944 SUBB A data B44 CJNE A data rel 75H MOV direct data 95H SUBB A direct Boy CJNE Agirect rel 76H MOV RO data 96H SUBB A RO B y CJNE RO data rel 77H MOV QhH1 fdata 974 SUBB A RI B7y CJNE RI data rel 784 MOV Ro data 98H SUBB A RO B8y CJNE Ro data rel 794 MOV R1 data 994 SUBB A RI B94 CJNE RI data rel 7AH MOV R2 data 9AH SUBB A R2 BAH CJNE R2 data rel 7BH MOV R3 data 9BH SUBB A R3 BBy CJNE R3 data rel 7CH MOV R4 data 9CH SUBB A R4 BCH CJNE R4 data rel 7DH MOV R5 data 9DH SUBB A R5 BDy CJNE R gt 5 data rel 7EY MOV R6 data 9E SUBB A R6 BEY CJNE R6 data rel 7FH MOV R7 data 9FH SUBB A R7 BFy CJNE R7 data rel Semiconductor Group 4 88 S EMENS Instruction Set C500 Family Table 4 4 Instruction List in Hexadecimal Order cont d Op Mnemonic Op Mnemonic Code Code COH PUSH direct EO MOVX A DPTR Cip AJMP addr11 Ely AJMP addri1 C24 CER bit E24 MOVX A QRO C34 CLR C E34 MOVX A QR1 C4H SWAP A E44 CLR A C5y XCH A direct E5y MOV A direct C64 XCH A RO E6H MOV A RO C74 XCH A RI1 E74 MOV A RI C8H XCH A RO E8H MOV A RO C9H XCH ARI E9H MOV ARI CAH XCH A R2 EAy MOV A R2 CBH XCH A R3 EBy MOV A R3 CCH XCH A R4 ECH MOV A R4 CDH XCH_A R5 EDH MOV A R5 CEH XCH A R amp EEH MOV
11. Register indirect addressing Internal RAM R1 RO SP external data memory R1 RO DPTR Base register plus index register addressing Program memory A DPTR A PC Register Indirect Addressing Register indirect addressing uses the contents of either RO or R1 in the selected register bank as a pointer to locations in a 256 byte block the 256 bytes of internal RAM or the lower 256 bytes of external data memory Note that the special function registers are not accessible by this method The upper half of the internal RAM can be accessed by indirect addressing only Access to the full 64 Kbytes of external data memory address space is accomplished by using the 16 bit data pointer Execution of PUSH and POP instructions also uses register indirect addressing The stack may reside anywhere in the internal RAM Base Register plus Index Register Addressing Base register plus index register addressing allows a byte to be accessed from program memory via an indirect move from the location whose address is the sum of a base register DPTR or PC and index register ACC This mode facilitates look up table accesses Boolean Processor The Boolean processor is a bit processor integrated into the C500 family microcontrollers It has its own instruction set accumulator the carry flag bit addressable RAM and I O The bit manipulation instructions allow setbit clear bit complement bit jump if bit is set
12. S EMENS Instruction Set C500 Family ORL direct data Operation ORL direct direct v data Encoding 0100 0011 direct address immediate data Bytes Cycles 2 Semiconductor Group 4 61 S EMENS Instruction Set C500 Family ORL C lt src bit gt Function Logical OR for bit variables Description Set the carry flag if the Boolean value is a logic 1 leave the carry in its current state otherwise A slash preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value but the source bit itself is not affected No other flags are affected Example Set the carry flag if and only if P1 0 1 ACC 7 2 1 or OV 0 MOV C P1 0 Load carry with input pin P1 0 ORL C ACC 7 OR carry with the accumulator bit 7 ORL C OV OR carry with the inverse of OV ORL C bit Operation ORL C C v bit Encoding 0111 0010 bit address Bytes 2 Cycles 2 ORL C bit Operation ORL C C v bit Encoding 1010 0000 bit address Bytes 2 Cycles 2 Semiconductor Group 4 62 S EMENS Instruction Set C500 Family POP direct Function Pop from stack Description The contents of the internal RAM location addressed by the stack pointer is read and the stack pointer is decremented by one The value read i
13. SIEMEN Instruction Set s C500 Family RET Function Return from subroutine Description RET pops the high and low order bytes of the PC successively from the stack decrementing the stack pointer by two Program execution continues at the resulting address generally the instruction immediately following an ACALL or LCALL No flags are affected Example The stack pointer originally contains the value OBy Internal RAM locations OAH and OBy contain the values 234 and 01 respectively The instruction RET will leave the stack pointer equal to the value 0944 Program execution will continue at location 0123 Operation RET PC15 8 SP SP SP 1 PC7 0 SP SP SP 1 Encoding 0010 0010 Bytes 1 Cycles 2 Semiconductor Group 4 65 S EMENS Instruction Set C500 Family RETI Function Description Example Operation Encoding Bytes Cycles Return from interrupt RETI pops the high and low order bytes of the PC successively from the stack and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed The stack pointer is left decremented by two No other registers are affected the PSW is not automatically restored to its pre interrupt status Program execution continues at the resulting address which is generally the instruction immediately after the point at which the interrupt request was detect
14. ADDC A A C Ri Encoding 0011 0111 Bytes 1 Cycles 1 ADDC A data Operation ADDC A A C data Encoding 0011 0100 Bytes 2 Cycles 1 Semiconductor Group immediate data 4 13 S EMENS Instruction Set C500 Family AJMP addr11 Function Description Example Operation Encoding Bytes Cycles Absolute jump AJMP transfers program execution to the indicated address which is formed at run time by concatenating the high order five bits of the PC after incrementing the PC twice op code bits 7 5 and the second byte of the instruction The destination must therefore be within the same 2K block of program memory as the first byte of the instruction following AJMP The label JMPADR is at program memory location 01234 The instruction AJMP JMPADR is at location 03454 and will load the PC with 0123p AJM P PC PC 2 PC10 0 page address a10 a9 a8 0 0001 a a6 ab a4 a3 a2 al a0 Semiconductor Group 4 14 S EMENS Instruction Set C500 Family ANL lt dest byte gt lt src byte gt Function Logical AND for byte variables Description ANL performs the bitwise logical AND operation between the variables indicated and stores the results in the destination variable No flags are affected The two operands allow six addressing mode co
15. Accessing External Program Memory 3 3 3 2 2 Accessing External Data Memory 3 4 4 Instruction Bel ius iL eki ka Ria 4 1 4 1 Addressing Modes 2455 ns den is hoe atio kei li e AA ut trs 4 1 4 2 Introduction to the Instruction Set 2 24 uie eh emcee e ec Doe ele bie nn c 4 3 4 2 1 Data Transfer S KL See esis doen ge Nae dde ee eire t doe etr doloe 4 3 4 2 2 Arithmetic Instr ctlons ii ve e YE y eee rari id le i e 4 4 4 2 3 EOGIG ISHUCTIONS IH 4 5 4 2 4 Control Transfer Instructions seslilik ekibimle 4 5 4 3 Instruction D finitions 2e deni a e Bale Vee ie ew dns eg 4 7 Dignum hi ico ee al ie ie iaia ayl 4 9 ADD P eSI DUIS act St Gol lic e VA nt ei 4 10 ADDG Aue en e ge ie e sente beats reti repe Pedes a le 4 12 AJMP Add hi cia a le IC bac ed ead A rele ea BERS 4 14 ANL lt dest byte gt STO bYVlOM vara ipe ul gg Go ea Bee bees 4 15 ANL direct dala seo seen n db E ca al alii fast PC a 4 17 ANL C lt lt SGD sab am oe Bek and eee ll Pe Sob ve a n 4 18 CJNE lt dest byte gt lt src byte gt rel 4 19 G NE CORi data el terier elele deye puma bee amd 4 21 CLR Ara EYE e Er A I AAS eNOS 4 22 CLR oM AE eli ki ik iel ei ld een er e MER COTE 4 23 Semiconductor Group 1 1 SIEMENS C500 Table of Contents Page CPL A CRDI EET a DR Benen CE ET OE 4 24 CPL Dil ssa AA Eyy EMU Ne EN EE 4 25 DA te ai
16. BCD digits of the decimal number 24 the low order two digits of the decimal sum of 56 67 and the carry in The carry flag will be set by the decimal adjust instruction indicating that a decimal overflow occurred The true sum 56 67 and 1 is 124 Semiconductor Group 4 26 S EMENS Instruction Set C500 Family Operation Encoding Bytes Cycles BCD variables can be incremented or decremented by adding 014 or 994 If the accumulator initially holds 304 representing the digits of 30 decimal then the instruction sequence ADD A 99H DA A will leave the carry set and 29y in the accumulator since 30 99 129 The low order byte of the sum can be interpreted to mean 30 1 29 DA contents of accumulator are BCD if A3 0 gt 9 v AG 1 then A3 0 A3 0 6 and if A7 4 gt 9 v C 1 then A7 4 A7 4 6 1101 0100 Semiconductor Group 4 27 S EMENS Instruction Set C500 Family DEC byte Function Decrement Description The variable indicated is decremented by 1 An original value of 00 will underflow Example DEC A Operation Encoding Bytes Cycles DEC Rn Operation Encoding Bytes Cycles to OFF No flags are affected Four operand addressing modes are allowed accumulator register direct or register indirect Note When this instruction is used to modify an output port the value used as the original port data
17. Function Description Example Operation Encoding Bytes Cycles Long call LCALL calls a subroutine located at the indicated address The instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16 bit result onto the stack low byte first incrementing the stack pointer by two The high order and low order bytes of the PC are then loaded respectively with the second and third bytes of the LCALL instruction Program execution continues with the instruction at this address The subroutine may therefore begin anywhere in the full 64 Kbyte program memory address space No flags are affected Initially the stack pointer equals 07 The label SUBRTN is assigned to program memory location 12344 After executing the instruction LCALL SUBRTN at location 0123 the stack pointer will contain 094 internal RAM locations 0844 and 09H will contain 264 and 0144 and the PC will contain 12344 LCALL PC PC 3 SP SP 1 SP PC7 0 SP SP 1 SP PC15 8 PC addr15 0 0001 0010 addr15 addr8 addr7 addr0 Semiconductor Group 4 44 S EMENS Instruction Set C500 Family LJMP addr16 Function Long jump Description LUMP causes an unconditional branch to the indicated address by loading the high order and low order bytes of the PC respectively with the second and thi
18. P MOFP 100 2 SMD Plastic Metric Quad Flat Package rectangular 88 25 sto A Bi D 50x Index Marking 2 Does not include dambar protruslon of 0 08 max per side 1 Does not include plastic or metal protrusion of 0 25 max per side GPM05623 SMD Surface Mounted Device Dimensions inmm Figure 5 7 P MQFP 100 2 Package Outline Semiconductor Group 5 7
19. S EMENS Instruction Set C500 Family JB bit rel Function Jump if bit is set Description If the indicated bit is a one jump to the address indicated otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC after incrementing the PC to the first byte of the next instruction The bit tested is not modified No flags are affected Example The data present at input port 1 is 11001010p The accumulator holds 56 01010110p The instruction sequence JB P1 2 LABEL1 JB ACC 2 LABEL2 will cause program execution to branch to the instruction at label LABEL2 Operation JB PC PO 3 if bit 1 then PC PC rel Encoding 0010 0000 bit address rel address Bytes Cycles Semiconductor Group 4 36 S EMENS Instruction Set C500 Family JBC bit rel Function Jump if bit is set and clear bit Description If the indicated bit is one branch to the address indicated otherwise proceed with the next instruction n either case clear the designated bit The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC after incrementing the PC to the first byte of the next instruction No flags are affected Note When this instruction is used to test an output pin the value used as the original
20. Semiconductor Group 4 80 S EMENS Instruction Set C500 Family XRL direct data Operation XRL direct direct v data Encoding 0110 0011 direct address immediate data Bytes Cycles 2 Semiconductor Group 4 81 Instruction Set C500 Family SIEMENS 4 4 Instruction Set Summary Tables The following two tables give a survey about the instruction set of the C500 family microcontrollers In table 4 3 the instructions are ordered in functional groups In table 4 4 the instructions are ordered in the hexadecimal order of their opcode 4 4 1 Functional Groups of Instructions Table 4 3 Instruction Set Summary Mnemonic Description Byte Cycle Arithmetic Operations ADD A Rn Add register to accumulator 1 1 ADD A direct Add direct byte to accumulator 2 1 ADD A Ri Add indirect RAM to accumulator 1 1 ADD A data Add immediate data to accumulator 2 1 ADDC A Rn Add register to accumulator with carry flag 1 1 ADDC A direct Add direct byte to A with carry flag 2 1 ADDC A Ri Add indirect RAM to A with carry flag 1 1 ADDC A data Add immediate data to A with carry flag 2 1 SUBB A Rn Subtract register from A with borrow 1 1 SUBB A direct Subtract direct byte from A with borrow 2 1 SUBB A Ri Subtract indirect RAM from A with borrow 1 1 SUBB A data Subtract immediate data from A with borrow 2 1 INC A
21. also help you get in touch with your nearest sales office By agreement we will take packing material back if it is sorted You must bear the costs of transport For packing material that is returned to us unsorted or which we are not obliged to accept we shall have to invoice you for any costs in curred Components used in life support devices or systems must be expressly authorized for such purpose Critical components of the Semiconductor Group of Siemens AG may only be used in life support devices or systems with the express written approval of the Semiconductor Group of Siemens AG 1 Acritical component is a component used in a life support device or system whose failure can reasonably be expected to cause the failure of that life support device or system or to affect its safety or effectiveness of that device or system 2 Life support devices or systems are intended a to be implanted in the human body or b to support and or maintain and sustain hu man life If they fail it is reasonable to assume that the health of the user may be endangered SIEMENS C500 Table of Contents Page 1 Fundamental Structure 1 1 1 1 110 818 61 9 a karma M kl Bid RR lie GE edi mp pk e le 1 1 1 2 Memory Organization 34104 xU REA RA e Adi ee en bi le ER a 1 2 1 2 1 Program Memory e ki anak ellik a ia ibi aM ad Miren 1 2 1 2 2 Dala Memory so reine e Ye V REDE Qd E E a 1 3 1 221 lmiermalk
22. are sampled in each machine cycle The sampled flags are polled during the following machine cycle If one of the flags was in a set condition in the preceeding cycle the polling cycle will find it and the interrupt controller will cause the CPU to branch to the vector address of the appropriate service routine by generating an internal LCALL This hardware generated LCALL is blocked by any of the following conditions 1 An interrupt of equal or higher priority is already in progress 2 The current polling cycle is not in the final cycle of the instruction in progress 3 The instruction in progress is RETI or any write access to interrupt enable or priority registers Semiconductor Group 2 10 SIEMEN CPU Functions s C500 Family Any of these three conditions will block the generation of the LCALL to the interrupt service routine Condition 2 ensures that the instruction in progress is completed before vectoring to any service routine Condition 3 ensures that if the instruction in progress is RETI or any write access to interrupt enable or interrupt priority registers then at least one more instruction will be executed before any interrupt is vectored too this delay guarantees that changes of the interrupt status can be observed by the interrupt controller The polling cycle is repeated with each machine cycle and the values polled are the values that were present at the previous machine cycle Note that if any interrupt flag is active
23. bit or the R1 or RO register 8 bit MOVC moves a byte from program memory to the accumulator The operand in A is used as an index into a 256 byte table pointed to by the base register DPTR or PC The byte operand accessed is transferred to the accumulator Address Object Transfer MOV DPTR data loads 16 bits of immediate data into a pair of destination registers DPH and DPL Semiconductor Group 4 3 S EMENS Instruction Set C500 Family 4 2 2 Arithmetic Instructions The C500 family microcontrollers have four basic mathematical operations Only 8 bit operations using unsigned arithmetic are supported directly The overflow flag however permits the addition and subtraction operation to serve for both unsigned and signed binary integers Arithmetic can also be performed directly on packed BCD representations Addition INC increment adds one to the source operand and puts the result in the operand flags in PSW are not affected ADD adds A to the source operand and returns the result to A ADDC add with carry adds A and the source operand then adds one 1 if CY is set and puts the result in A DA decimal add adjust for BCD addition corrects the sum which results from the binary addition of two digit decimal operands The packed decimal sum formed by DA is returned to A CY is set if the BCD result is greater than 99 otherwise it is cleared Subtraction SUBB subtract with borrow
24. direct A Exclusive OR accumulator to direct byte 2 1 XRL direct data Exclusive OR immediate data to direct byte 3 2 CLR A Clear accumulator 1 1 CPL A Complement accumulator 1 1 RL A Rotate accumulator left 1 1 RLC A Rotate accumulator left through carry 1 1 RR A Rotate accumulator right 1 1 RRC A Rotate accumulator right through carry 1 1 SWAP A Swap nibbles within the accumulator 1 1 Semiconductor Group 4 83 SIEMENS Instruction Set C500 Family Table 4 3 Instruction Set Summary cont d Mnemonic Description Byte Cycle Data Transfer MOV A Rn Move register to accumulator MOV A direct Move direct byte to accumulator MOV A Ri Move indirect RAM to accumulator MOV A data Move immediate data to accumulator MOV Rn A Move accumulator to register MOV Rngirect Move direct byte to register MOV Rn data Move immediate data to register MOV direct A Move accumulator to direct byte MOV direct Rn Move register to direct byte MOV direct direct Move direct byte to direct byte MOV direct ORi Move indirect RAM to direct byte MOV direct data Move immediate data to direct byte MOV QRiA Move accumulator to indirect RAM MOV Ri direct Move direct byte to indirect RAM MOV Q Ri data Move immediate data to indirect RAM MOV DPTR data16 Load data pointer with a 16 bit constant MOVC A A DPTR Move code byte relative to DPTR to accumulator M
25. from P1 If some other value was input on P1 the program will loop at this point until the P1 data changes to 344 Semiconductor Group 4 19 SIEMENS Instruction Set C500 Family CJNE A direct rel Operation PC PC 3 if A lt gt direct then PC PC relative offset if A lt direct then C 1 else C 0 Encoding 1011 0101 direct address rel address Bytes Cycles CJNE A data rel Operation PC PC 3 if A data then PC PC relative offset if A data then C 1 else C 0 Encoding 1011 0100 immediate data rel address Bytes Cycles CJNE RN data rel Operation PC PC 3 if Rn lt gt data then PC PC relative offset if Rn lt data then C else C 0 Encoding 1011 1rrr immediate data rel address Bytes Cycles 2 Semiconductor Group 4 20 SIEMENS Instruction Set C500 Family CJNE Ri data rel Operation PC PC 3 if Ri lt gt data then PC PC relative offset if Ri lt data then C lt 1 else C 0 Encoding 1011 0111 immediate data rel address Bytes Cycles 2 Semiconductor Group 4 21 SIEMEN Instruction Set s C500 Family CLR A Function Clear accumulator Description The accumulator is cleared a
26. memory configuration for the two cases EA 0 and EA 1 The ROM boundary shown in figure 1 1 applies to the C501 which has 8K byte of internal ROM Other C500 family microcontrollers with different ROM size have different ROM boundaries Semiconductor Group 1 2 SIEMEN Fundamental Structure s C500 Family External Program Memory External Program Memory 2000 TFFF y Internal Boundary Program Memory 0000 0000 The location of the ROM boundary depends on the specific C500 devices MCD02766 Figure 1 1 Program Memory Configuration Example of the C501 1 2 2 Data Memory The data memory area of the C500 family microcontrollers consists of internal and external data memory portions The internal data memory area is addressed using 8 bit addresses The external data memory and the internal XRAM data memory are addressed by 8 bit or16 bit addresses The content of the internal data memory also XRAM is not affected by a reset operation After power up the content is undefined while it remains unchanged during and after a reset as long as the power supply is not turned off The XRAM content is also maintained when the C500 microcontrollers are in power saving modes 1 2 2 1 Internal Data Memory The internal data memory address space is divided into three basic physically separate and distinct blocks the lower 128 byte of internal data RAM the upper 128 byte of internal data RAM and the 128 byte special functi
27. or vice versa otherwise OV is cleared OV is used in two s complement arithmetic because it is set when the signal result cannot be represented in 8 bits Pis set if the modulo 2 sum of the eight bits in the accumulator is 1 odd parity otherwise P is cleared even parity When a value is written to the PSW register the P bit remains unchanged as it always reflects the parity of A Semiconductor Group 4 4 SIEMEN Instruction Set s C500 Family 4 2 3 Logic Instructions The C500 family microcontrollers perform basic logic operations on both bit and byte operands Single Operand Operations CLR sets A or any directly addressable bit to zero 0 SETB sets any directly bit addressable bit to one 1 CPL is used to complement the contents of the A register without affecting any flag or any directly addressable bit location RL RLC RR RRC SWAP are the five operations that can be performed on A RL rotate left RR rotate right RLC rotate left through carry RRC rotate right through carry and SWAP rotate left four For RLC and RRC the CY flag becomes equal to the last bit rotated out SWAP rotates A left four places to exchange bits 3 through 0 with bits 7 through 4 Two Operand Operations ANL performs bitwise logical AND of two operands for both bit and byte operands and returns the result to the location of the first operand ORL performs bitwise logical OR of two source operands for bo
28. the accumulator with the sixteen bit data pointer and load the resulting sum to the program counter This will be the address for subsequent instruction fetches Sixteen bit addition is performed modulo 2 9 a carry out from the low order eight bits propagates through the higher order bits Neither the accumulator nor the data pointer is altered No flags are affected An even number from 0 to 6 is in the accumulator The following sequence of instructions will branch to one of four AJMP instructions in a jump table starting at JMP TBL MOV DPTR JMP TBL JMP A DPTR JMP TBL AJMP LABELO AJMP LABEL AJMP LABEL2 AJMP LABEL3 If the accumulator equals 04H when starting this sequence execution will jump to label LABEL2 Remember that AJMP is a two byte instruction so the jump instructions start at every other address JMP PC A DPTR 0111 0041 1 Semiconductor Group 4 39 S EMENS Instruction Set C500 Family JNB Function Description Example Operation Encoding Bytes Cycles bit rel Jump if bit is not set Ifthe indicated bit is a zero branch to the indicated address otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC after incrementing the PC to the first byte of the next instruction The bit tested is not modified No flags are affected The data present a
29. 0 MCU Semiconductor Group 2 9 S EMENS CPU Functions C500 Family 2 7 Basic Interrupt Handling Each member of the C500 microcontroller family provides several interrupt sources These interrupts are generated typically by external events or by the internal peripheral units If an interrupt is accepted by the CPU the microcontroller interrupts a running program and proceeds the program execution at an interrupt source specific vector address where the interrupt service routine is located After the execution of a RETI return from interrupt instruction the program is continued at the point where it has been interrupted Figure 2 4 shows an example for the interrupt vector addresses of a C500 microcontroller C501 Generally interrupt vector addresses are located in the code memory area starting at address 00034 The minimum distance between two consecutive vector addresses is always 8 bytes Therefore interrupt vectors can be assigned to the following addresses 00034 000BH 00134 001Byy 00234 002B4 0033p OOFBy FFFF he Program Memory Timer 2 Interrupt Serial Port Interrupt Timer 1 Interrupt External Interrupt 1 Timer 0 Interrupt a Bytes External Interrupt 0 MCD02770 Figure 2 4 Interrupt Vector Addresses Example of the C501 An interrupt source indicates to the interrupt controller an interrupt condition by setting an interrupt request flag The interrupt request flags
30. 0p The instruction MUL AB will give the product 12 800 320014 so B is changed to 324 00110010p and the accumulator is cleared The overflow flag is set carry is cleared MUL Semiconductor Group 4 57 S EMENS Instruction Set C500 Family NOP Function Description Example Operation Encoding Bytes Cycles No operation Execution continues at the following instruction Other than the PC no registers or flags are affected It is desired to produce a low going output pulse on bit 7 of port 2 lasting exactly 5 cycles A simple SETB CLR sequence would generate a one cycle pulse so four additional cycles must be inserted This may be done assuming no interrupts are enabled with the instruction sequence CLR P2 7 NOP NOP NOP NOP SETB P2 7 NOP 0000 0000 Semiconductor Group 4 58 S EMENS Instruction Set C500 Family ORL lt dest byte gt lt src byte gt Function Logical OR for byte variables Description ORL performs the bitwise logical OR operation between the indicated variables storing the results in the destination byte No flags are affected The two operands allow six addressing mode combinations When the destination is the accumulator the source can use register direct register indirect or immediate addressing when the destination is a direct address the source can be the accumulator or immediate data Note When t
31. 18 S EMENS Instruction Set C500 Family CJNE lt dest byte gt lt src byte gt rel Function Description Example Compare and jump if not egual CJNE compares the magnitudes of the tirst two operands and branches if their values are not egual The branch destination is computed by adding the signed relative displacement in the last instruction byte to the PC after incrementing the PC to the start of the next instruction The carry flag is set if the unsigned integer value of lt dest byte gt is less than the unsigned integer value of lt src byte gt otherwise the carry is cleared Neither operand is affected The first two operands allow four addressing mode combinations the accumulator may be compared with any directly addressed byte or immediate data and any indirect RAM location or working register can be compared with an immediate constant The accumulator contains 344 Register 7 contains 5614 The first instruction in the sequence CJNE R7 60H NOT EO tk a R7 60H NOT EO JC REG LOW If R7 lt 60H T ehi R7 gt 60H sets the carry flag and branches to the instruction at label NOT_EQ By testing the carry flag this instruction determines whether R7 is greater or less than 60p If the data being presented to port 1 is also 344 then the instruction WAIT CJNE A P1 WAIT clears the carry flag and continues with the next instruction in sequence since the accumulator does equal the data read
32. A R6 CF4 XCH AR7 EFy MOV A R7 Doy POP direct Foy MOVX DPTR A Diy ACALL addr11 Fiy ACALL addr11 D24 SETB bit F24 MOVX RO A D3H SETB C F34 MOVX QR1 A D4 DA A F44 CPL A D5y DJNZ direct rel F5H MOV direct A D6H XCHD A RO F6 MOV GRO A D74 XCHD A RI F7H MOV R1 A D84 DJNZ Ro rel F84 MOV Ro A D94 DJNZ RI rel F94 MOV R1 A DAH DJNZ R2 rel FAW MOV R2 A DBy DJNZ R3 rel FBH MOV R3 A DCH DJNZ R4 rel FCH MOV R4 A DDH DJNZ R5 rel FDH MOV R5 A DE DJNZ R6 rel FEQ MOV R6 A DFH DJNZ R7 rel FFH MOV R7 A Semiconductor Group 4 89 SIEMEN Package Information x C500 Family 5 Package Information This chapter shows typical package outlines of the packages which are actually used for the microcontrollers of the C500 family The appropriate data sheet should always be regarded when the package of a specific C500 microcontroller has to be referenced 5 1 P DIP Package P DIP 40 3 Plastic Dual In line Package 15 24 0 38 13 71 025 1 27 0 05 TT 0 46101 4 83 MAX 38 MIN N 0 33401 10 25 40x 16 0 76 40 do rh dh rh dh h dh dh dh h h h h h h h h h rh rh A hg OA OA RA GA GA GA GA GA GA A GA E oe GA ee 1 20 m 523105 si Index Marking 1 Does not include plastic or metal protrusion of 0 25 max pe
33. Data MemMory s sime eee one gine ae nel lerini eee 1 3 1 2 2 2 nternalDataMemoryXRAM eee 1 5 1 223 External Data Memory sese pk kak da he kee kme EG kaka kei 1 6 1 2 3 Special Function Register Area s Siir ie vee e e e a 1 6 2 CPU Architecture isso Dose des Lande kah id hei pei 2 1 2 1 ACCUMULATOR canes sce oe hee pottea Roe bote o e ei dE REIR RUE la a 2 2 2 2 E RegisiBE Za op seiten ee e et tuno eti pa ure i elele goats Race lo diete eni 2 2 2 3 Program Status Word iier a esse LER RE EE VERE am pace caer fedes 2 2 2 4 lek POINTS ot feed E bd Roco EROS C EU UK Ee eco ud tls eh Garnet 2 3 2 5 EEE N LER 213 cxi Fare lar EROR Mcd drea NN duke Bi empate ah Ana dad wa ant 2 4 2 5 1 The Importance of Additional Datapointers 2 5 2 5 2 How the eight Datapointers of the C500 are realized 2 5 2 5 3 Advantages of Multiple Datapointers 2 6 2 5 4 Application Example and Performance Analysis 2 6 2 6 Enhanced Hooks Emulation Concept 2 9 2 7 Basic Interrupt Handling 2 10 2 8 Interrupt Response Time ha dura oce ie a dye a kcal l g ere ROI RR en org 2 12 3 CPU TINO i ARRE OSE El Be Bante pitas E E e menu e 3 1 3 1 Basie T M scolo gr TUTTI 3 1 3 2 Accessing External Memory erkekle elime ekledik di 3 3 3 2 1
34. Dy DEC R5 3DH ADDC A R5 5SDH ANL A R5 1EH DEC R6 3EH ADDC A R6 SEy ANL A R6 iFy DEC R7 3FH ADDC A R7 5FH ANL A R7 Semiconductor Group 4 87 S EMENS Instruction Set C500 Family Table 4 4 Instruction List in Hexadecimal Order cont d Op Mnemonic Op Mnemonic Op Mnemonic Code Code Code 60H JZ rel 80H SJMP rel Aoy ORL C bit 61H AJMP addr11 81H AJMP addr11 Aly AJMP addr11 624 XRL direct A 824 ANL C bit A24 MOV C bit 634 XRL direct data 834 MOVC A A DPTR _ A3y INC DPTR 644 XRL A data 844 DIV AB A44 MUL AB 65H XRL A direct 85H MOV direct direct ASH 664 XRL A RO 864 MOV direct RO A6H MOV RO direct 674 XRL A RI 874 MOV direct R1 A74 MOV Ri direct 68H XRL A RO 88H MOV direct RO A84 MOV ROgirect 694 XRL A R1 894 MOV direct R1 A94 MOV Rf direct GAY XRL AR2 8AH MOV direct R2 AAH MOV R2 direct 6BH XRL A R3 8BH MOV direct R3 ABH MOV R83 direct 6CH XRL A R4 8CH MOV direct R4 ACH MOV R4 direct 6Dy XRL A R5 8Dy MOV direct R5 ADH MOV R5 direct 6E4 XRL A R6 8EH MOV direct R6 AEH MOV R6 direct 6FH XRL AR7 8FH MOV direci R7 AFH MOV R7 direct 70H JNZ rel 904 MOV DPTR datai6 BOH ANL C bit 71H ACALL addr11 914 ACALL addr11 BiH ACALL addr11 724 ORL C direct 924 MOV bit C B24 CPL bit 734
35. I PI P2 S P1 P2 53 P1 P2 S4 P1 P2 S5 P1 P2 P1 P2 ALE Read Read next on Di 7 Tslslelste a 1 Byte 1 Cycle Instruction e g INC A Read Read 2nd ao Ra Read Read next S6 SI P1 P2 s2 Pi P2 53 PI P2 SA P1 P2 S5 P1 P2 P1 P2 scard Read next i Opcode again b 2 Byte 1 Cycle Instruction e g ADD A 4 Data Read next Opcode again Opcode Discard Opcode Y EEE c 1 Byte 2 Cycle Instruction e g INC DPTR Read Read next Opcode Opcode MOVX Discard Y Y BIEEJEEEJ Read next Opcode again No Fetch No Fetch r No ALE A Y 5TelsToJslsfsIsTsleIsTsT d MOVX 1 Byte 2 Cycle ADDR DATA Access of Exlernal Memory MCD02771 Figure 3 1 Fetch Execute Sequence Semiconductor Group 3 2 SIEMEN CPU Timing gt C500 Family 3 2 Accessing External Memory There are two types of external memory accesses accesses to external program memory and accesses to external data memory Accesses to external program memory use the signal PSEN program store enable as the read strobe Accesses to external data memory use the RD or WR alternate functions of P3 7 and P3 6 to access the memory Fetches from external program memory always use a 16 bit address Accesses to external data memory can use either a 16 bit address MOVX DPTR or an 8 bit address MOVX Ri Whenever a 16 bit address is used the hi
36. Increment accumulator 1 1 INC Hn Increment register 1 1 INC direct Increment direct byte 2 1 INC Ri Increment indirect RAM 1 1 DEC A Decrement accumulator 1 1 DEC Rn Decrement register 1 1 DEC direct Decrement direct byte 2 1 DEC Ri Decrement indirect RAM 1 1 INC DPTR Increment data pointer 1 2 MUL AB Multiply A and B 1 4 DIV AB Divide A by B 1 4 DA A Decimal adjust accumulator 1 1 Semiconductor Group 4 82 SIEMENS Instruction Set C500 Family Table 4 3 Instruction Set Summary cont d Mnemonic Description Byte Cycle Logic Operations ANL A Rn AND register to accumulator 1 1 ANL A direct AND direct byte to accumulator 2 1 ANL A Ri AND indirect RAM to accumulator 1 1 ANL A data AND immediate data to accumulator 2 1 ANL direct A AND accumulator to direct byte 2 1 ANL direct data AND immediate data to direct byte 3 2 ORL A Rn OR register to accumulator 1 1 ORL A direct OR direct byte to accumulator 2 1 ORL A Ri OR indirect RAM to accumulator 1 1 ORL A data OR immediate data to accumulator 2 1 ORL direct A OR accumulator to direct byte 2 1 ORL direct data OR immediate data to direct byte 3 2 XRL A Rn Exclusive OR register to accumulator 1 1 XRL A direct Exclusive OR direct byte to accumulator 2 1 XRL A Ri Exclusive OR indirect RAM to accumulator 1 1 XRL A data Exclusive OR immediate data to accumulator 2 1 XRL
37. LE address latch enable signal is shown for external reference ALE is normally activated twice during each machine cycle once during S1P2 and S2P1 and again during S4P2 and S5P1 The execution of a one cycle instruction begins at S1P2 when the opcode is latched into the instruction register If it is a two byte instruction the second reading takes place during S4 of the same machine cycle If it is a one byte instruction there is still a fetch at S4 but the byte read which would be the next op code is ignored discarded fetch and the program counter is not incremented In any case execution is completed at the end of S6P2 Figures 3 1 a and b show the timing of a 1 byte 1 cycle instruction and for a 2 byte 1 cycle instruction Most C500 instructions are executed in one cycle MUL multiply and DIV divide are the only instructions that take more than two cycles to complete they take four cycles Normally two code bytes are fetched from the program memory during every machine cycle The only exception to this is when a MOVX instruction is executed MOVX is a one byte 2 cycle instruction that accesses external data memory During a MOVX the two fetches in the second cycle are skipped while the external data memory is being addressed and strobed Figure 3 1 c and d show the timing for a normal 1 byte 2 cycle instruction and for a MOVX instruction Semiconductor Group 3 1 SIEMENS CPU Timing C500 Family S6 S
38. OVC A A PC Move code byte relative to PC to accumulator MOVX A Ri Move external RAM 8 bit addr to A MOVX A QDPTR Move external RAM 16 bit addr to A MOVX Ri A Move A to external RAM 8 bit addr MOVX QDPTR A Move A to external RAM 16 bit addr PUSH direct Push direct byte onto stack POP direct Pop direct byte from stack XCH A Rn Exchange register with accumulator XCH A direct Exchange direct byte with accumulator XCH A Qhi Exchange indirect RAM with accumulator XCHD A Ri Exchange low order nibble indir RAM with A N NN A IS OI ININ OI III MO oH ND 2 2 2 2 m mmim vimm mi i imi mim mimi lo mi M l2 1 MOV A ACC is not a valid instruction Semiconductor Group 4 84 S EMENS Instruction Set C500 Family Table 4 3 Instruction Set Summary cont d Mnemonic Description Byte Cycle Boolean Variable Manipulation CLR C Clear carry flag 1 1 CLR bit Clear direct bit 2 1 SETB C Set carry flag 1 1 SETB bit Set direct bit 2 1 CPL C Complement carry flag 1 1 CPL bit Complement direct bit 2 1 ANL C bit AND direct bit to carry flag 2 2 ANL C bit AND complement of direct bit to carry 2 2 ORL C bit OR direct bit to carry flag 2 2 ORL C bit OR complement of direct bit to carry 2 2 MOV C bit Move direct bit to carry flag 2 1 MOV
39. Register SYSCON Address B1p Bit No MSB LSB 7 6 5 4 3 2 1 0 Bit RMAP SYSCON The functions of the shaded bits are not described in this section Bit Function RMAP Special function register map bit RMAP 0 The access to the non mapped standard special function register area is enabled default after reset RMAP 1 The access to the mapped special function register area is enabled As long as bit RMAP is set mapped special function registers can be accessed This bit is not cleared by hardware automatically Thus when non mapped mapped registers are to be accessed the bit RMAP must be cleared set by software respectively each Some registers e g ACC are accessed independently of bit RMAP Two bits in the program status word RSO PSW 3 and RS1 PSW 4 select the active register bank This allows fast context switching which is useful when entering subroutines or interrupt service routines The 8 general purpose registers of the selected register bank may be accessed by register addressing For indirect addressing modes the registers RO and R1 are used as pointer or index register to address internal or external memory e g MOV GRO Semiconductor Group 1 6 S EMENS CPU Functions C500 Family 2 CPU Architecture The typical architecture of a C500 family microcontroller is shown in figure 2 1 This block diagram includes all main functional blocks o
40. SIEMENS C500 Microcontroller Family Architecture and Instruction Set User s Manual 0197 C500 Architecture and Instruction User s Manual Revision History 01 97 Original Version Previous Releases 07 96 Page Subjects changes since last revision Table of Reference to pages of each instruction added content 4 89 Table header corrected Edition 01 97 This edition was realized using the software system FrameMaker Published by Siemens AG Bereich Halbleiter Marketing Kommunikation BalanstraBe 73 81541 M nchen Siemens AG 1997 All Rights Reserved Attention please As far as patents or other rights of third parties are concerned liability is only assumed for components not for applications processes and circuits implemented within components or assemblies The information describes the type of component and shall not be considered as assured characteristics Terms of delivery and rights to change design reserved For questions on technology delivery and prices please contact the Semiconductor Group Offices in Germany orthe Siemens Companies and Representatives worldwide see address list Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Siemens Office Semiconductor Group Siemens AG is an approved CECC manufacturer Packing Please use the recycling operators known to you We can
41. a will be read from the output data latch not the input pins Register 0 contains 7Ey 01111110p Internal RAM locations 7Ey and 7Fy contain OFFH and 404 respectively The instruction sequence INC RO INC RO INC RO will leave register 0 set to 7Fy and internal RAM locations 7EH and 7Fy holding respectively 00H and 41 INC A A 1 00000100 INC Rn e Rn 1 0000 1 r r r Semiconductor Group 4 33 SIEMENS Instruction Set C500 Family INC direct Operation INC direct direct 1 direct address Encoding 0000 0101 Bytes 2 Cycles 1 INC Ri Operation INC Ri Ri 1 Encoding 0000 011i Bytes 1 Cycles 1 Semiconductor Group 4 34 S EMENS Instruction Set C500 Family INC DPTR Function Increment data pointer Description Increment the 16 bit data pointer by 1 A 16 bit increment modulo 216 is performed an overflow of the low order byte of the data pointer DPL from OFF to 00H will increment the high order byte DPH No flags are affected This is the only 16 bit register which can be incremented Example Registers DPH and DPL contain 12 and OFEy respectively The instruction sequence INC DPTR INC DPTR INC DPTR will change DPH and DPL to 134 and 01 Operation INC DPTR DPTR 1 Encoding 1010 0011 Bytes 1 Cycles 2 Semiconductor Group 4 35
42. al operation of the controllers Emulation of on chip ROM based programs is possible too Each production chip has built in logic for the support of the Enhanced Hooks Emulation Concept Therefore no costly bond out chips are necessary for emulation This also ensure that emulation and production chips are identical The Enhanced Hooks Technology which requires embedded logic in the C500 allows the C500 together with an EH IC to function similar to a bond out chip This simplifies the design and reduces costs of an ICE system ICE systems using an EH IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 This includes emulation of ROM ROM with code rollover and ROMless modes of operation It is also able to operate in single step mode and to read the SFRs after a break ICE System Interface to Emulation Hardware SYSCON PCON PCON MCU Optional I O Ports Port3 Port 1 RSYSCON RPCON RPCON Enhanced Hooks Interface Circuit RPort 2 RPort0 TEA TALE TPSEN Target System Interface MCS02647 Figure 2 3 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0 port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware ICE system and the C50
43. ally they are functionally upward compatible to the SAB 80C52 80C32 microcontroller While maintaining all architectural and operational characteristics of the SAB 80C52 80C32 the C500 microcontrollers differ in number and complexity of their peripheral units which have been adapted to the specific application areas The goal of this Architecture and Instruction Set Manual is to summarize the basic architecture and functional characteristics of all members of the C500 microcontroller family This includes the description of the architecture and the description of the complete instruction set Detailed information about the different versions of the C500 microcontrollers are given in the specific User Manuals Semiconductor Group 1 1 SIEMEN Fundamental Structure s C500 Family 1 2 Memory Organization The memory resources of the C500 family microcontrollers are organized in different types of memories data and program memory which further can be located internally on the microcontroller chip or outside of the microcontroller The memory partitioning of the C500 microcontrollers is typical for a Harvard architecture where data and program areas are held in separate memory areas The on chip peripheral units are accessed using an internal special function register memory area The available memory areas have different sizes and are located in the following five address spaces Table 1 1 C500 Address Spaces Ty
44. an internal XRAM area is disabled external data memory can be accessed in the address range of the internal XRAM Semiconductor Group 1 5 SIEMEN Fundamental Structure s C500 Family 1 2 2 3 External Data Memory The 64 Kbyte external data memory can be addressed by instructions that use 8 bit or 16 bit indirect addressing A 16 bit external memory addressing mode is supported by the MOVX instructions using the 16 bit datapointer DPTR for addressing For 8 bit addressing MOVX instructions with the general purpose registers RO R1 are used 1 2 3 Special Function Register Area The registers of a C500 microcontroller except the program counter and the four general purpose register banks reside in the special function register SFR area The special function register area typically provides 128 bytes of direct addressable SFRs The SFRs which are located at addresses with address bit 0 2 equal 0 addresses 80H 884 90H F04 FFH are bitaddressable SFRs see also figure 1 1 For example the SFR with byte address 80H provides the bit locations with bit addresses 80 to 87 The bit addresses of the SFR bits reach from 80y to FFy Due to the limited number of 128 standard SFRs some derivatives of the C500 microcontroller family provide an additional 128 byte SFR area called the mapped SFR area The mapped SFR area provides the same addressing capabilities direct addresses bit addressing as the standard SFR area Special Function
45. and conditional branch instruction AC Auxiliary Carry Flag Used by instructions which execute BCD operations FO General Purpose Flag RSI Register Bank select control bits RSO These bits are used to select one of the four register banks RS1 RSO Function 0 0 Registerbank 0 at data address 0014 0714 selected 0 1 Registerbank 1 at data address 084 0Fy selected 1 0 Registerbank 2 at data address 1044 17 selected 1 1 Registerbank 3 at data address 18H 1Fy selected OV Overflow Flag Used by arithmetic instruction F1 General Purpose Flag P Parity Flag Always set cleared by hardware to indicate an odd even number of one bits in the accumulator i e even parity 2 4 Stack Pointer The stack pointer SP register is 8 bits wide It is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET RETI execution i e it always points to the last valid stack byte While the stack may reside anywhere in the on chip RAM the stack pointer is initialized to 074 after a reset This causes the stack to begin a location 084 above register bank zero The SP can be read or written under software control Semiconductor Group 2 3 S EMENS CPU Functions C500 Family 2 5 Data Pointer 8 bit accesses to the internal XRAM data memory or the external data memory are executed using the data pointer DPTR as an 16 bit address register Normally the C500 family microcontrollers have one da
46. ation ANL direct direct A Encoding 01010101 Bytes 2 Cycles 1 Semiconductor Group immediate data direct address 4 16 S EMENS Instruction Set C500 Family ANL direct data Operation ANL direct direct a data Encoding 01010011 direct address immediate data Bytes Cycles 2 Semiconductor Group 4 17 SIEMEN Instruction Set x C500 Family ANL C lt src bit gt Function Logical AND for bit variables Description If the Boolean value of the source bit is a logic 0 then clear the carry flag otherwise leave the carry flag in its current state A slash preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value but the source bit itself is not affected No other flags are affected Only direct bit addressing is allowed for the source operand Example Set the carry flag if and only if P1 0 1 ACC 7 1 and OV 0 MOV C P1 0 Load carry with input pin state ANL C ACC 7 AND carry with accumulator bit 7 ANL C OV AND with inverse of overflow flag ANL C bit Operation ANL C C bit Encoding 1000 0010 bit address Bytes Cycles 2 ANL C bit Operation ANL C C bit Encoding 1011 0000 bit address Bytes 2 Cycles 2 Semiconductor Group 4
47. bit C Move carry flag to direct bit 2 2 Program and Machine Control ACALL addr11 Absolute subroutine call 2 2 LCALL addr16 Long subroutine call 3 2 RET Return from subroutine 1 2 RETI Return from interrupt 1 2 AJMP addr11 Absolute jump 2 2 LUMP addr16 Long iump 3 2 SJMP rel Short jump relative addr 2 2 JMP A DPTR Jump indirect relative to the DPTR 1 2 JZ rel Jump if accumulator is zero 2 2 JNZ rel Jump if accumulator is not zero 2 2 JC rel Jump if carry flag is set 2 2 JNC rel Jump if carry flag is not set 2 2 JB bit rel Jump if direct bit is set 3 2 JNB bit rel Jump if direct bit is not set 3 2 JBC bit rel Jump if direct bit is set and clear bit 3 2 CJNE A direct rel Compare direct byte to A and jump if not equal 3 2 Semiconductor Group 4 85 S EMENS Instruction Set C500 Family Table 4 3 Instruction Set Summary cont d Mnemonic Description Byte Cycle Program and Machine Control cont d CJNE A data rel Compare immediate to A and jump if not egual 3 2 CJNE Rn data rel Compare immed to reg and jump if not equal 3 2 CJNE Ri data rel Compare immed to ind and jump if not equal 3 2 DJNZ Rn rel Decrement register and jump if not zero 2 2 DJNZ direct rel Decrement direct byte and jump if not zero 3 2 NOP No operation 1 1 Semiconductor Group 4 86 S EMENS Instruction Set
48. but not being responded to for one of the conditions already mentioned or if the flag is no longer active when the blocking condition is removed the denied interrupt will not be serviced In other words the fact that the interrupt flag was once active but not serviced is not remembered Every polling cycle interrogates only the pending interrupt reguests The polling cycle LCALL sequence is illustrated in figure 2 1 C1 gt lt C2 gt lt C3 gt lt C4 lt C5 S5P2 i ca Interrupts Long Call to Interrupt Interrupt Interrupt are polled Vector Address Routine is latched MCT01859 Figure 2 5 Interrupt Detection Entry Diagram Note that if an interrupt of a higher priority level goes active prior to S5P2 in the machine cycle labeled C3 in figure 2 5 then in accordance with the above rules it will be vectored to during C5 and C6 without any instruction for the lower priority routine to be executed Thus the processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate servicing routine In some cases it also clears the flag that generated the interrupt while in other cases it does not then this has to be done by the user s software The program execution proceeds from that location until the RETI instruction is encountered The RETI instruction informs the processor that the interrupt routine is no longer in progress t
49. ceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice The accumulator is not modified No flags are affected The accumulator originally holds 00 The instruction sequence JNZ LABEL1 INC A JNZ LABEL2 will set the accumulator to 01H and continue at label LABEL2 JNZ PC PC 2 if A 0 then PC PC rel 0111 0000 rel address Semiconductor Group 4 42 S EMENS Instruction Set C500 Family JZ rel Function Description Example Operation Encoding Bytes Cycles Jump if accumulator is zero If all bits of the accumulator are zero branch to the address indicated otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice The accumulator is not modified No flags are affected The accumulator originally contains 01H The instruction sequence JZ LABEL DEC A JZ LABEL2 will change the accumulator to 00y and cause program execution to continue at the instruction identified by the label LABEL2 JZ PC PC 2 if A 0 then PC lt PC rel 0110 0000 rel address Semiconductor Group 4 43 S EMENS Instruction Set C500 Family LCALL addr16
50. coding Pade 0 G eee Bytes 1 Cycles 1 MOV A direct Operation MOV A lt direct Encoding 1110 0101 direct address Bytes 2 Cycles 1 MOV A ACC is not a valid instruction The content of the accumulator after the execution of this instruction is undefined Semiconductor Group 4 46 S EMENS Instruction Set C500 Family MOV A Ri Operation MOV A Ri Encoding 11100111 Bytes 1 Cycles 1 MOV A data Operation MOV A data Encoding 0111 0100 immediate data Bytes 2 Cycles 1 MOV Rn A Operation MOV Rn lt A Encoding 1111 1rrr Bytes 1 Cycles 1 MOV Rn direct Operation MOV Rn direct Encoding LOTO irrr direct address Bytes Cycles 2 Semiconductor Group 4 47 S EMENS Instruction Set C500 Family MOV Rn data Operation MOV Rn data Encoding 0111 irrr immediate data Bytes 2 Cycles 1 MOV direct A Operation MOV direct A Encoding 1111 0101 direct address Bytes 2 Cycles 1 MOV direct Rn Operation MOV direct Rn Encoding 1000 1rrr direct address Bytes Cycles MOV direct direct Operation MOV direct direct Encoding 1000 0101 dir addr src dir addr dest Bytes Cyc
51. data will be read from the output data latch not the input pin Example The accumulator holds 56H 01010110p The instruction sequence JBC ACC 3 LABEL1 JBC ACC 2 LABEL2 will cause program execution to continue at the instruction identified by the label LABEL2 with the accumulator modified to 524 01010010p Operation JBC PC PC 3 if bit 1 then bit O PC PC rel Encoding 0001 0000 bit address rel address Bytes Cycles Semiconductor Group 4 37 S EMENS Instruction Set C500 Family JC rel Function Description Example Operation Encoding Bytes Cycles Jump if carry is set If the carry flag is set branch to the address indicated otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice No flags are affected The carry flag is cleared The instruction sequence JC LABEL1 CPL C JC LABEL2 will set the carry and cause program execution to continue at the instruction identified by the label LABEL2 JC PC PC 2 if C 1 then PC PC rel 0100 0000 rel address Semiconductor Group 4 38 S EMENS Instruction Set C500 Family JMP DA DPTR Function Description Example Operation Encoding Bytes Cycles Jump indirect Add the eight bit unsigned contents of
52. ds on the nature of the other interrupt s service routine If the instruction in progress is not in its final cycle the additional wait time cannot be more than 3 cycles since the longest instructions MUL and DIV are only 4 cycles long and if the instruction in progress is RETI or a write access to interrupt enable or interrupt priority registers the additional wait time cannot be more than 5 cycles a maximum of one more cycle to complete the instruction in progress plus 4 cycles to complete the next instruction if the instruction is MUL or DIV Thus a single interrupt system the response time is always more than 3 cycles and less than 9 cycles Semiconductor Group 2 12 SIEMEN CPU Timing gt C500 Family 3 CPU Timing 3 1 Basic Timing A machine cycle consists of 6 states Each state is divided into a phase 1 half during which the phase 1 clock is active and a phase 2 half during which the phase 2 clock is active Thus a machine cycle consists of the states S1P1 state 1 phase 1 through S6P2 state 6 phase 2 Depending on the C500 type of microcontroller each state lasts either one or two periods of the oscillator clock Typically arithmetic and logical operations take place during phase 1 and internal register to register transfers take place during phase 2 The diagrams in figure 3 1 show the fetch execute timing related to the internal states and phases Since these internal clock signals are not user accessible the A
53. ed If a lower or same level interrupt is pending when the RETI instruction is executed that one instruction will be executed before the pending interrupt is processed The stack pointer originally contains the value OBy An interrupt was detected during the instruction ending at location 01224 Internal RAM locations 0AY and OB contain the values 234 and 014 respectively The instruction RETI will leave the stack pointer equal to 09H and return program execution to location 01234 RETI PC15 8 SP SP SP 1 PC7 0 SP SP SP 1 0011 0010 Semiconductor Group 4 66 S EMENS Instruction Set C500 Family RL A Function Description Example Operation Encoding Bytes Cycles Rotate accumulator left The eight bits in the accumulator are rotated one bit to the left Bit 7 is rotated into the bit 0 position No flags are affected The accumulator holds the value OCSH 11000101p The instruction RL A leaves the accumulator holding the value 8By 10001011p with the carry unaffected RL An 1 An n 0 6 AO A7 0010 0011 Semiconductor Group 4 67 S EMENS Instruction Set C500 Family RLC A Function Description Example Operation Encoding Bytes Cycles Rotate accumulator left through carry flag The eight bits in the accumulator and the carry flag are together rotated one bit to the
54. ed from a negative number The source operand allows four addressing modes register direct register indirect or immediate The accumulator holds 0C9y 11001001 p register 2 holds 544 01010100p and the carry flag is set The instruction SUBB A R2 will leave the value 74y 01110100p in the accumulator with the carry flag and AC cleared but OV set Notice that OC9H minus 54 is 75 4 The difference between this and the above result is due to the borrow flag being set before the operation If the state of the carry is not known before starting a single or multiple precision subtraction it should be explicitly cleared by a CLR C instruction SUBB A Rn Operation Encoding Bytes Cycles SUBB A A C Rn 1001 1rrr Semiconductor Group 4 73 S EMENS Instruction Set C500 Family SUBB A direct Operation SUBB Encoding Bytes Cycles SUBB Operation Encoding Bytes Cycles SUBB Operation Encoding Bytes Cycles A A C direct direct address A Ri A data immediate data 1001 0101 2 1 SUBB A A C Ri Locana SUBB A A C data 1001 0100 2 1 Semiconductor Group 4 74 SIEMEN Instruction Set s C500 Family SWAP A Function Swap nibbles within the accumulator Description SWAP A interchanges the
55. en P RR ein e UR ete re a etude M tos Sele le 4 66 RL ek e SO er SOR O O A e i deu 4 67 RLC fonus LA parak rk POI OPERE POTETE ETERO 4 68 RR e a e e e D D MOTOS LE easy Zeca aie 4 de 4 69 RRC i heaton leri High ln mi eek do alin SND ne ed 4 70 SETB sbibE tenus pentes a irene ed eae ba 4 71 IIE gt DENE KA E A EN AA dentiera 4 72 SUBB A STO DVO Si renina ee CS ane al al elinle Ne ala a 4 73 A ER ced E hes Sieh ce E E bu EE n 4 75 XCH A DIS aa Loiri TM Rr e Red T AREAS RR TE 4 76 XGHD AOM S oe ves oT cee Eee tob ES ra tek Go ete m el Rn 4 78 XRL lt dest byte gt lt src byte gt 4 79 4 4 Instruction Set Summary Tables es eR ERES m re te bd 4 82 4 4 1 Functional Groups of Instructions ra Elm RR RE E AR Ba ES 4 82 4 4 2 Hexadecimal Ordered Instructions 4 87 Semiconductor Group l 2 SIEMENS C500 Table of Contents Page 5 Package Information 5 1 5 1 P DIPIPACKAGG RG are e YES ed bin aaa 5 1 5 2 PEGO Packages e susleme da EE Xa DM EE de JE Sli ydi 5 2 5 3 MOP Packages li KER ean ARR D RR S RR S Mam eR a ads 5 5 Semiconductor Group l 3 SIEMENS Fundamental Structure C500 Family 1 Fundamental Structure 1 1 Introduction The members of the C500 Siemens microcontroller family are basically fully compatible in architecture and software to the standard 8051 microcontroller family Especi
56. erefore affect only one of the eight pointers which is addressed by DPSEL at that very moment Figure 5 1 illustrates the addressing mechanism a 3 bit field in register DPSEL points to the currently used DPTRx Any standard 8051 instruction e g MOVX DPTR A transfer a byte from accumulator to an external location addressed by DPTR now uses this activated DPTRx Semiconductor Group 2 5 SIEMENS CPU Functions C500 Family DPSEL 92y DPTR7 DPSEL Selected Data 2 1 0 pointer 0 0 0 DPTR O DPTRO 0 0 1 DPTR 1 0 1 0 DPTR 2 DPH 834 DPL 824 0 1 I DPTR 3 1 0 0 DPTR 4 1 0 1 DPTR 5 External Data Memory 1 1 0 DPTR 6 MCD00779 1 1 1 DPTR 7 Figure 2 2 Accessing of External Data Memory via Multiple Datapointers 2 5 3 Advantages of Multiple Datapointers Using the above addressing mechanism for external data memory results in less code and faster execution of external accesses Whenever the contents of the datapointer must be altered between two or more 16 bit addresses one single instruction which selects a new datapointer does this job If the program uses just one datapointer then it has to save the old value with two 8 bit instructions and load the new address byte by byte This not only takes more time it also requires additional space in the internal RAM 2 5 4 Application Example and Performance Analysis The following example shall demonstrate the invo
57. es NE e ele e ME E 4 26 DEC KA eoo Selina ii ei fusto np e alert sa 4 28 DIV PE s nt ta e NI Reina 4 30 DJNZ lt byte gt lt rel addr gt usas De ha a av edie M e teed 4 31 INC ADVIS cars en acted ee CENE VENERE apis HZ NEI 4 33 INC BI A E oet tuse n geli kli ge emme e e leke 4 35 JB DIETO EA Lot rut bibi i Botan Gp he ain di 4 36 JBC DILLO een eminem DIESE RIS areas tes 4 37 JC Ol ee se itso Nery eh Rig e atis oe wai Re cit OW e S wire O 4 38 JMP GARDPTR utri asd ai e dore delay PEPPER Pene s d 4 39 JNB ong A sale e a Paso Ala ERMEYE ER EEE ee eet KEKE 4 40 JNC DO e TELLE 4 41 JNZ d RC AA e la mala e RIO ENTO IC DIE 4 42 JZ Ne e Moda EEE GO 4 43 EGALE Addio de lenen iii ig 4 44 IMP Ad Er eoe r teri A hoe ee ae ay eee 4 45 MOV lt dest byte gt lt src byte gt pirla 4 46 MOV lt dest bit gt lt src bit gt aaa 4 51 MOV DPTR OAM 4 ond NE EE MERE ORAN eire O 4 52 MOVE A A lt base reg gt iis oss ce adl e fate ey re pa aa e RO at 4 53 MOVX lt desi bytes esrc bylo i e a 4 55 MUL AB eee ilya la e e ri ml sala Rhe dai 4 57 NORT EE ei e ee iii e Ati ROV o At 4 58 ORL dest byles lt src byte gt ab o S Baba ke tob tant eh e dete gt 4 59 ORL GEST DIN Anu hosce a Alena fe a Allie EH M RAE DJE e Rue PO Ef e Mrd 4 62 POP direcl asscilioree ve EC pua RANE ect a Y e a CR ecc e 4 63 PUSH itecb qd IS a ETE PEN IEEE m eR ePi Be pin gie 4 64 RET O emen ei el pg e DUET VEN be bo uud cu TC qd 4 65 RETI uin RD
58. eturn address saved on the stack by a previous call operation and decrements the SP register by two 2 to adjust the SP for the popped address AJMP LUMP and SJMP transfer control to the target operand The operation of AJMP and LUMP are analogous to ACALL and LCALL The SJMP short jump instruction provides for transfers within a 256 byte range centered about the starting address of the next instruction 128 to 127 JMP A DPTR performs a jump relative to the DPTR register The operand in A is used as the offset 0 255 to the address in the DPTR register Thus the effective destination for a jump can be anywhere in the program memory space Conditional Jumps Conditional jumps perform a jump contingent upon a specific condition The destination will be within a 256 byte range centered about the starting address of the next instruction 128 to 127 JZ performs a jump if the accumulator is zero JNZ performs a jump if the accumulator is not zero JC performs a jump if the carry flag is set JNC performs a jump if the carry flag is not set JB performs a jump if the directly addressed bit is set JNB performs a jump if the directly addressed bit is not set JBC performs a jump if the directly addressed bit is set and then clears the directly addressed bit CJNE compares the first operand to the second operand and performs a jump if they are not equal CY is set if the first operand is less than the second operand otherw
59. f the C500 microcontrollers The shaded blocks are basic functional units which are mandatory for each C500 microcontroller The other functional blocks such as XRAM peripheral units and ROM RAM sizes are specific to each C500 microcontroller derivative a 5 2 e TU lt sek 0 Cor Timers es s K K S SE K EE gt o K gt RST EA MDU PSEN ALE XTAL WDU Basic functional blocks MCB02769 Figure 2 1 C500 Microcontroller Architecture Block Diagram The core block represents the CPU Central Processing Unit of the C500 family microcontrollers The CPU consists of the instruction decoder the arithmetic section the CPU registers and the program control section The housekeeper unit generates internal signals for controlling the functions of the individual internal units within the microcontroller Port O and port 2 are required for accessing external code and data memory and for emulation purposes The external control signals and the clock generation are handled in the external control block The access control unit is responsible for the selection of the on chip memory resources The IRAM provides the internal RAM which includes the general purpose registers The interrupt requests from the peripheral units are handled by an interrupt controller unit C500 device specific is the configuration of the on chip periphera
60. gh byte of the address comes out on port 2 where it is held for the duration of the read write or code fetch cycle If an 8 bit address is being used MOVX Ri the contents of the port 2 SFR remain at the port 2 pins throughout the whole external memory cycle In this case port 2 pins can be used to page the external data memory In either case the low byte of the address is time multiplexed with the data byte on port 0 The ADDRESS DATA signal drives both FETS in the port 0 output buffers Thus in external bus mode the port 0 pins are not open drain outputs and do not require external pullups The ALE address latch enable signal should be used to latch the address byte into an external latch The address byte is valid at the negative transition of ALE Then in a write cycle the data byte to be written appears on port 0 just before WR is activated and remains there until WR is deactivated In a read cycle the incoming byte is accepted at port 0 just before the read strobe RD is deactivated During any access to external memory the CPU writes FFy to the port 0 latch the special function register thus obliterating the information in the port 0 SFR Also a MOV PO instruction must not take place during external memory accesses If the user writes to port 0 during an external memory fetch the incoming code byte may be corrupted Therefore do not write to port 0 if external memory is used 3 2 1 Accessing External Program Memory Exte
61. hen pops the two top bytes from the stack and reloads the program counter Execution of the interrupted program continues from the point where it was stopped Note that the RETI instruction is very important because it informs the processor that the program left the current interrupt priority level A simple RET instruction would also have returned execution to the interrupted program but it would have left the interrupt control system thinking an interrupt was still in progress In this case no interrupt of the same or lower priority level would be acknowledged Semiconductor Group 2 11 S EMENS CPU Functions C500 Family 2 8 Interrupt Response Time If an external interrupt is recognized its corresponding request flag is set at S5P2 in every machine cycle The value is not polled by the circuitry until the next machine cycle If the request is active and conditions are right for it to be acknowledged a hardware subroutine call to the requested service routine will be next instruction to be executed The call itself takes two cycles Thus a minimum of three complete machine cycles will elapse between activation and external interrupt request and the beginning of execution of the first instruction of the service routine A longer response time would be obtained if the request was blocked by one of the three previously listed conditions If an interrupt of equal or higher priority is already in progress the additional wait time obviously depen
62. his instruction is used to modify an output port the value used as the original port data will be read from the output data latch not the input pins Example If the accumulator holds 0C3y 11000011 and RO holds 55H 01010101 then the instruction ORL A RO will leave the accumulator holding the value 0D7y 11010111p When the destination is a directly addressed byte the instruction can set combinations of bits in any RAM location or hardware register The pattern of bits to be set is determined by a mask byte which may be either a constant data value in the instruction or a variable computed in the accumulator at run time The instruction ORL P1 00110010p will set bits 5 4 and 1 of output port 1 ORL A Rn Operation ORL A A v Rn Encoding 0100 1rrr Bytes 1 Cycles 1 Semiconductor Group 4 59 S EMENS Instruction Set C500 Family ORL A direct Operation ORL Encoding Bytes Cycles ORL Operation Encoding Bytes Cycles ORL Operation Encoding Bytes Cycles ORL Operation Encoding Bytes Cycles A lt A v direct direct address immediate data 0100 0101 2 1 A Ri ORL A A v Ri 0100 011i 1 1 A data ORL A A v data 0100 0100 2 1 direct A ORL direct direct v A 0100 0010 2 1 Semiconductor Group direct address
63. inary machine language encoding and a symbolic description or restatement of the function is also provided Note Only the carry auxiliary carry and overflow flags are discussed The parity bit is always computed from the actual content of the accumulator Similarly instructions which alter directly addressed registers could affect the other status flags if the instruction is applied to the PSW Status flags can also be modified by bit manipulation Semiconductor Group 4 7 S EMENS Instruction Set C500 Family Notes on Data Addressing Modes Rn direct Ri data data 16 bit A s Working register RO R7 128 internal RAM locations any I O port control or status register Indirect internal or external RAM location addressed by register RO or R1 8 bit constant included in instruction 16 bit constant included as bytes 2 and 3 of instruction 128 software flags any bit addressable I O pin control or status bit Accumulator Notes on Program Addressing Modes addr16 addr11 rel Destination address for LCALL and LUMP may be anywhere within the 64 Kbyte program memory address space Destination address for ACALL and AJMP will be within the same 2 Kbyte page of program memory as the first byte of the following instruction SJMP and all conditional jumps include an 8 bit offset byte Range is 127 128 bytes relative to the first byte of the following instruction All mnemonics copyrighted
64. ise it is cleared Comparisons can be made between A and directly addressable bytes in internal data memory or an immediate value and either A a register in the selected register bank or a register indirectly addressable byte of the internal RAM DJNZ decrements the source operand and returns the result to the operand A jump is performed if the result is not zero The source operand of the DJNZ instruction may be any directly addressable byte in the internal data memory Either direct or register addressing may be used to address the source operand Interrupt Returns RETI transfers control as RET does but additionally enables interrupts of the current priority level Semiconductor Group 4 6 SIEMEN Instruction Set s C500 Family 4 3 Instruction Definitions All 111 instructions of the C500 family microcontrollers can essentially be condensed to 53 basic operations in the following alphabetically ordered according to the operation mnemonic section Table 4 2 PSW Flag Modification CY OV AC Instruction Flag Instruction Flag CY OV AC CY OV AC ADD X X X SETBC 1 ADDC X X X CLRC 0 SUBB X X X CPL C X MUL 0 X ANL C bit X DIV 0 X ANL C bit X DA X ORL C bit X RRC X ORL C bit X RLC X MOV C bit X CJNE X A brief example of how the instruction might be used is given as well as its effect on the PSW flags The number of bytes and machine cycles required the b
65. l units Serial interfaces timers capture compare units A D converters watchdog units or a multiply divide unit are typical examples for on chip peripheral units The external signals of these peripheral units are available at multifunctional parallel I O ports or at dedicated pins Semiconductor Group 2 1 SIEMEN CPU Functions s C500 Family The arithmetic section of the core performs extensive data manipulation and is comprised of the arithmetic logic unit ALU an A register B register and PSW register Further it has extensive facilities for binary and BCD arithmetic and excels in its bit handling capabilities Efficient use of program memory results from an instruction set consisting of 44 one byte 41 two byte and 15 three byte instructions The ALU accepts 8 bit data words from one or two sources and generates an 8 bit result under the control of the instruction decoder The ALU performs the arithmetic operations add substract multiply divide increment decrement BDC decimal add adjust and compare and the logic operations AND OR Exclusive OR complement and rotate right left or swap nibble left four Also included is a Boolean processor performing the bit operations as set clear complement jump if not set jump if set and clear and move to from carry Between any addressable bit or its complement and the carry flag it can perform the bit operations of logical AND or logical OR with the result returned to the carr
66. le way of executing a program loop a given number of times or for adding a moderate time delay from 2 to 512 machine cycles with a single instruction The instruction sequence MOV R2 8 TOGGLE CPL P1 7 DJNZ R2 TOGGLE will toggle P1 7 eight times causing four output pulses to appear at bit 7 of output port 1 Each pulse will last three machine cycles two for DJNZ and one to alter the pin Semiconductor Group 4 31 S EMENS Instruction Set C500 Family DJNZ Rn rel Operation DJNZ PC PC 2 Rn Rn 1 if Rn gt O or Rn lt 0 then PC PC rel Encoding 1101 1rrr rel address Bytes Cycles 2 DJNZ direct rel Operation DJNZ PC PC 2 direct direct 1 if direct gt 0 or direct lt 0 then PC lt PC rel Encoding 1101 0101 direct address rel address Bytes Cycles 2 Semiconductor Group 4 32 S EMENS Instruction Set C500 Family INC lt byte gt Function Increment Description INC increments the indicated variable by 1 An original value of OFF y will overflow Example INC A Operation Encoding Bytes Cycles INC Rn Operation Encoding Bytes Cycles to 00H No flags are affected Three addressing modes are allowed register direct or register indirect Note When this instruction is used to modify an output port the value used as the original port dat
67. left Bit 7 moves into the carry flag the original state of the carry flag moves into the bit 0 position No other flags are affected The accumulator holds the value 0C54 11000101p and the carry is zero The instruction RLC A leaves the accumulator holding the value 8AH 10001010B with the carry set RLC An 1 An n 0 6 AO C C A7 00110011 Semiconductor Group 4 68 S EMENS Instruction Set C500 Family RR A Function Description Example Operation Encoding Bytes Cycles Rotate accumulator right The eight bits in the accumulator are rotated one bit to the right Bit 0 is rotated into the bit 7 position No flags are affected The accumulator holds the value OCSH 11000101p The instruction RR A leaves the accumulator holding the value OE2y 11100010p with the carry unaffected RR An An 1 n 0 6 A7 A0 00000011 Semiconductor Group 4 69 SIEMEN Instruction Set s C500 Family RRC A Function Rotate accumulator right through carry flag Description The eight bits in the accumulator and the carry flag are together rotated one bit to the right Bit 0 moves into the carry flag the original value of the carry flag moves into the bit 7 position No other flags are affected Example The accumulator holds the value 0C54 11000101 p the carry is zero The instruction RRC A leaves the accumulator holding
68. les 2 Semiconductor Group 4 48 S EMENS Instruction Set C500 Family MOV direct Ri Operation MOV Encoding Bytes Cycles MOV Operation Encoding Bytes Cycles MOV Operation Encoding Bytes Cycles MOV Ooeration Encoding Bytes Cycles direct Ri 1000 011i direct address direct Zdata direct address immediate data direct address Semiconductor Group MOV direct data 0111 0101 RI A MOV Ri A 1111 011i 1 1 Ri direct MOV Ri lt direct 1010 0111 2 4 49 SIEMEN Instruction Set 2 C500 Family MOV Ri data Operation MOV Ri data Encoding O 1 01 T1 immediate data Bytes 2 Cycles 1 Semiconductor Group 4 50 S EMENS Instruction Set C500 Family MOV lt dest bit gt lt src bit gt Function Move bit data Description The Boolean variable indicated by the second operand is copied into the location specified by the first operand One of the operands must be the carry flag the other may be any directly addressable bit No other register or flag is affected Example The carry flag is originally set The data present at input port 3 is 11000101 p The data previously written to output port 1 is 354 00110101p
69. ll bits set to zero No flags are affected Example The accumulator contains 5CH 01011100p The instruction CLR A will leave the accumulator set to 004 00000000p Operation CLR A 0 Encoding 1110 0100 Bytes 1 Cycles 1 Semiconductor Group 4 22 SIEMEN Instruction Set x C500 Family CLR bit Function Clear bit Description The indicated bit is cleared reset to zero No other flags are affected CLR can operate on the carry flag or any directly addressable bit Example Port 1 has previously been written with 5Dy 01011101p The instruction CLR P1 2 will leave the port set to 594 01011001 p CLR C Operation CLR C 0 Encoding 1100 0011 Bytes 1 Cycles 1 CLR bit Operation CLR bit 0 Encoding 1100 0010 bit address Bytes 2 Cycles 1 Semiconductor Group 4 23 SIEMEN Instruction Set s C500 Family CPL A Function Complement accumulator Description Each bit of the accumulator is logically complemented one s complement Bits which previously contained a one are changed to zero and vice versa No flags are affected Example The accumulator contains 5CH 01011100p The instruction CPL A will leave the accumulator set to 0A34 10100011p Operation CPL A A Encoding 1111 0100 Bytes 1 Cycles 1 Semiconductor Group 4 24 SIEMEN Instruction Set x C500 Family CPL bit Function Compleme
70. low and high order nibbles four bit fields of the accumulator bits 3 0 and bits 7 4 The operation can also be thought of as a four bit rotate instruction No flags are affected Example The accumulator holds the value 0C54 11000101p The instruction SWAP A leaves the accumulator holding the value 5CH 01011100p Operation SWAP A3 0 s A7 4 A7 4 A3 0 Encoding 1100 0100 Bytes 1 Cycles 1 Semiconductor Group 4 75 S EMENS Instruction Set C500 Family XCH A lt byte gt Function Exchange accumulator with byte variable Description o XCH loads the accumulator with the contents of the indicated variable at the same time writing the original accumulator contents to the indicated variable The source destination operand can use register direct or register indirect addressing Example RO contains the address 20H The accumulator holds the value 3F 00111111p Internal RAM location 204 holds the value 754 01110101p The instruction XCH A RO will leave RAM location 20H holding the value 3Fy 00111111p and 754 01110101p in the accumulator XCH A Rn Operation XCH A S Rn Encoding 1100 irrr Bytes 1 Cycles 1 XCH A direct Operation XCH A S direct Encoding 1100 01041 direct address Bytes 2 Cycles 1 Semiconductor Group 4 76 S EMENS Instruction Set C500 Family XCH A Ri Operation XCH A S Ri
71. lvement of multiple data pointers in a table transfer from the code memory to external data memory Start address of ROM source table Start address of table in external RAM Semiconductor Group 1FFFH 2FAOH 2 6 S EMENS CPU Functions C500 Family Example 1 Using only One Datapointer Code for a C501 Initialization Routine MOV LOW SRC PTR OFFH Initialize shadow variables with source pointer MOV HIGH SRC_PTR 1FH MOV LOW DES PTR 0A0H Initialize shadow variables with destination pointer MOV HIGH DES PTR 2FH Table Look up Routine under Real Time Conditions f Number of cycles PUSH DPL Save old datapointer 2 PUSH DPH 2 MOV DPL LOW SRC PTR Load Source Pointer 2 MOV DPH HIGH SRC PTR 2 INC DPTR Increment and check for end of table execution time CJNE not relevant for this consideration MOVC A DPTR Fetch source data byte from ROM table 2 MOV LOW SRC PTR DPL Save source pointer and 2 MOV HIGH SRC PTR DPH load destination pointer 2 MOV DPL LOW DES_PTR 2 MOV DPH HIGH DES PTR 2 INC DPTR Increment destination pointer ex time not relevant MOVX DPTR A Transfer byte to destination address 2 MOV LOW DES_PTR DPL Save destination pointer 2 MOV HIGH DES PTR DPH 2 POP DPH Restore old datapointer 2 POP DPL 2 Total execution time machine cycles 28 Semiconductor Group 2 7 S EMENS CPU Functions C500 Family Example 2 Using Two Datapointers Code for a C509
72. mbinations When the destination is a accumulator the source can use register direct register indirect or immediate addressing when the destination is a direct address the source can be the accumulator or immediate data Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch not the input pins Example If the accumulator holds 0C3y 1100001 1g and register 0 holds OAAY 10101010p then the instruction ANL A RO will leave 814 10000001p in the accumulator When the destination is a directly addressed byte this instruction will clear combinations of bits in any RAM location or hardware register The mask byte determining the pattern of bits to be cleared would either be a constant contained in the instruction or a value computed in the accumulator at run time The instruction ANL P1 01110011p will clear bits 7 3 and 2 of output port 1 ANL A Rn Operation ANL A A Rn Encoding 0101 1rrr Bytes 1 Cycles 1 ANL A direct Operation ANL A A direct Encoding 0101 0101 direct address Bytes 2 Cycles 1 Semiconductor Group 4 15 SIEMENS Instruction Set C500 Family ANL A Ri Operation ANL A A Ri Encoding 0101 0111 Bytes 1 Cycles 1 ANL A data Operation ANL A A data Encoding 01010100 Bytes 2 Cycles 1 ANL direct A Oper
73. mmediate data Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch not the input pins Example If the accumulator holds 0C3y 11000011p and register 0 holds OAAy 10101010B then the instruction XRL A RO will leave the accumulator holding the value 69H 01101001p When the destination is a directly addressed byte this instruction can complement combinations of bits in any RAM location or hardware register The pattern of bits to be complemented is then determined by a mask byte either a constant contained in the instruction or a variable computed in the accumulator at run time The instruction XRL P1 00110001B will complement bits 5 4 and 0 of output port 1 XRL A Rn Operation XRL2 A A v Rn Encoding 0110 1rrr Bytes 1 Cycles 1 Semiconductor Group 4 79 SIEMEN Instruction Set x C500 Family XRL A direct Operation XRL A A v direct Encoding 0110 0101 direct address Bytes 2 Cycles 1 XRL A Ri Operation XRL A A v Ri Encoding 0110 0111 Bytes 1 Cycles 1 XRL A data Operation XRL A A v data Encoding 0110 0100 immediate data Bytes 2 Cycles 1 XRL direct A Operation XRL direct direct v A Encoding 0110 0010 direct address Bytes 2 Cycles 1
74. n external 256 byte RAM using multiplexed address data lines is connected to the C500 port 0 Port 3 provides control lines for the external RAM Ports 1 and 2 are used for normal I O Registers 0 and 1 contain 124 and 344 Location 34H of the external RAM holds the value 5614 The instruction sequence MOVX A BRI MOVX RO A copies the value 56 into both the accumulator and external RAM location 12 Semiconductor Group 4 55 SIEMENS Instruction Set C500 Family MOVX A Ri Operation MOVX A Ri Encoding 1110 0041i Bytes 1 Cycles 2 MOVX A DPTR Operation MOVX A DPTR Encoding 1110 0000 Bytes 1 Cycles 2 MOVX Ri A Operation MOVX Ri lt A Encoding 11111001 Bytes 1 Cycles 2 MOVX DPTR A Operation MOVX DPTR A Encoding 1111 0000 Bytes 1 Cycles 2 Semiconductor Group 4 56 S EMENS Instruction Set C500 Family MUL AB Function Description Example Operation Encoding Bytes Cycles Multiply MUL AB multiplies the unsigned eight bit integers in the accumulator and register B The low order byte of the sixteen bit product is left in the accumulator and the high order byte in B If the product is greater than 255 0FFH the overflow flag is set otherwise it is cleared The carry flag is always cleared Originally the accumulator holds the value 80 50 4 Register B holds the value 160 0A
75. nt bit Description The bit variable specified is complemented A bit which had been a one is changed to zero and vice versa No other flags are affected CPL can operate on the carry or any directly addressable bit Note When this instruction is used to modify an output pin the value used as the original data will be read from the output data latch not the input pin Example Port 1 has previously been written with 5Dy 010111015 The instruction sequence CPL P1 1 CPL P1 2 will leave the port set to 5B 010110115 CPL C Operation CPL bit C Encoding 1011 0011 Bytes 1 Cycles 1 CPL bit Operation CPL C bit Encoding 1011 0010 bit address Bytes 2 Cycles 1 Semiconductor Group 4 25 S EMENS Instruction Set C500 Family DA A Function Description Example Decimal adjust accumulator for addition DA A adjusts the eight bit value in the accumulator resulting from the earlier addition of two variables each in packed BCD format producing two four bit digits Any ADD or ADDC instruction may have been used to perform the addition If accumulator bits 3 0 are greater than nine xxxx1010 xxxx1111 or if the AC flag is one six is added to the accumulator producing the proper BCD digit in the low order nibble This internal addition would set the carry flag if a carry out of the low order four bit field propagated through all high order bi
76. ntents of a sixteen bit base register which may be either the data pointer or the PC In the latter case the PC is incremented to the address of the following instruction before being added to the accumulator otherwise the base register is not altered Sixteen bit addition is performed so a carry out from the low order eight bits may propagate through higher order bits No flags are affected A value between 0 and 3 is in the accumulator The following instructions will translate the value in the accumulator to one of four values defined by the DB define byte directive REL_PC INC A MOVC A A PC RET DB 66H DB 77H DB 88H DB 99H If the subroutine is called with the accumulator equal to 01 it will return with 774 in the accumulator The INC A before the MOVC instruction is needed to get around the RET instruction above the table If several bytes of code separated the MOVC from the table the corresponding number would be added to the accumulator instead MOVC A A DPTR Operation Encoding Bytes Cycles MOVC A A DPTR 1001 0011 Semiconductor Group 4 53 S EMENS Instruction Set C500 Family MOVC A DA PC Operation MOVC PC PC 1 A A PC Encoding 1000 0011 Bytes 1 Cycles 2 Semiconductor Group 4 54 S EMENS Instruction Set C500 Family MOVX lt dest byte gt lt src byte gt Function Description Example
77. on register SFR area The lower internal data RAM and the SFR area further include 128 bit locations each These bits can be handled by specific bit manipulation instructions Semiconductor Group 1 3 SIEMEN Fundamental Structure s C500 Family Figure 1 2 shows the configuration of the three basic internal RAM areas The lower data RAM is located in the address range 00H 7FH and can be addressed directly e g MOV A direct or indirectly e g MOV A RO with address in RO A bit addressable area of 128 free programmable direct addressable bits is located at byte addresses 20H 2F of the lower data RAM Bit 0 of the internal data byte at 20H has the bit address 00 4 while bit 7 of the internal data byte at 2Fy has the bit address 7Fy The lower 32 locations of the internal lower data RAM are assigned to four banks with eight general purpose registers GPRs each Only one of these banks can be enabled ata time to be used as general purpose registers Upper RAM Area Internal Data RAM 1 indirect addressable 128 Byte Internal Data RAM indirect amp direct addressable 128 Byte 16 Bytes with 128 bitaddressable Bits Registerbank 0 Internal SFR Area direct addressable 128 Byte 1 This internal RAM area is optional Some low end C500 family microcon
78. pe of Memory Location Size Program Memory External max 64 KByte Internal ROM EEPROM Depending on C500 version 2K up to 64KByte Data Memory External max 64 KByte Internal XRAM Depending on C500 version 256 Byte up to 3 KByte Internal 128 or 256 Byte Special Function Register Internal 128 256 Bytes 1 2 1 Program Memory The program memory of the C500 family microcontrollers can be composed of either completely external program memory of only internal program memory on chip ROM EEPROM or of a mixture of internal and external program memory If the EA pin EA External Access is held at low level the C500 microcontrollers execute the program code always out of the external program memory Romless C500 derivatives can use this type of program memory only C500 derivatives with on chip program memory typically use their internal program memory only If the internal program memory is used the EA pin must be put to high level With EA high the microcontroller executes instructions internally unless the address exceeds the upper limit of the internal program memory If the program counter is set to an address e g by a jump instruction which is higher than the internal program memory instructions are executed out of an external program memory When the instruction address again is below the internal program memory size limit internal program memory is accessed again Figure 1 1 shows the typical C500 family microcontroller program
79. r Group 4 11 S EMENS Instruction Set C500 Family ADDC A lt src byte gt Function Add with carry Description o ADDC simultaneously adds the byte variable indicated the carry flag and the accumulator contents leaving the result in the accumulator The carry and auxiliary carry flags are set respectively if there is a carry out of bit 7 or bit 3 and cleared otherwise When adding unsigned integers the carry flag indicates an overflow occurred OV is set if there is a carry out of bit 6 but not out of bit 7 or a carry out of bit 7 but not out of bit 6 otherwise OV is cleared When adding signed integers OV indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands Four source operand addressing modes are allowed register direct register indirect or immediate Example The accumulator holds 0C3y 11000011B and register 0 holds OAAy 10101010p with the carry flag set The instruction ADDC A RO will leave 6E 01101110p in the accumulator with AC cleared and both the carry flag and OV set to 1 ADDC A Rn Operation ADDC A A C Rn Encoding 0011 irrr Bytes 1 Cycles 1 ADDC A direct Operation Encoding Bytes Cycles ADDC A A C direct 0011 0101 direct address 2 1 Semiconductor Group 4 12 SIEMENS Instruction Set C500 Family ADDC A Ri Operation
80. r side GPD05883 SMD Surface Mounted Device Dimensions in mm Figure 5 1 P DIP 40 3 Package Outlines Semiconductor Group 5 1 S EMENS Package Information C500 Family 5 2 PLCC Packages P LCC 44 2 SMD Plastic Leaded Chip Carrier Package zuo 121008 x 45 jaka geje 3 ii e 105 SS e Eo seu A BD 17 53 013 nani OC A q O B Fio JI ma mili i Beene NS q a to q LH TS q Q H 44 1 Index Marking 0 5 MAX x45 si 1140085 x 45 3x t007 bee 110 05 A B D 17 531013 1 Does not include plastic or metal protrusion of 0 15 max per side GPL05102 SMD Surface Mounted Device Dimensions in mm Figure 5 2 P LCC 44 2 Package Outlines Semiconductor Group 5 2 SIEMENS Package Information C500 Family P LCC 68 4 SMD Plastic Leaded Chip Carrier Package zZ 0741007 124015 x 45 up Te e N OTT Ji 1 WR 127 sa 34x 0 43 01 SITE AED 68x Soi I 0 38 WA B D 20 32 110 05 A B D Bla gioa NS Uy 681 Index Marking 0 5 MAX x45
81. rd instruction bytes The destination may therefore be anywhere in the full 64K program memory address space No flags are affected Example The label JMPADR is assigned to the instruction at program memory location 12344 The instruction LUMP JMPADR at location 01234 will load the program counter with 1234p Operation LJMP PC addr15 0 Encoding 0000 0010 addr15 addr8 addr7 addr0 Bytes Cycles Semiconductor Group 4 45 SIEMEN Instruction Set s C500 Family MOV lt dest byte gt lt src byte gt Function Move byte variable Description The byte variable indicated by the second operand is copied into the location specified by the first operand The source byte is not affected No other register or flag is affected This is by far the most flexible operation Fifteen combinations of source and destination addressing modes are allowed Example Internal RAM location 304 holds 4044 The value of RAM location 404 is 10H The data present at input port 1 is 11001010B OCA MOV RO 30H RO lt 30H MOV GRO lt 40H MOV R1 A R1 lt 40H MOV B R1 B lt 10H MOV R1 P1 RAM 40H lt OCAH MOV P2 P1 P2 lt OCAH leaves the value 30H in register 0 40H in both the accumulator and register 1 10H in register B and OCAY 11001010 both in RAM location 40H and output on port 2 MOV A Rn Operation MOV A Rn En
82. rnal program memory is accessed under two conditions 1 Whenever signal EA is active low or 2 Whenever signal EA is inactive high and the program counter PC contains an address greater than the internal ROM size e g 1FFFFy for an 8K internal ROM or 3FFFy for an 16K internal ROM This requires that the ROMless versions have always EA wired to Vss to enable the lower 8K 16K or 32K program bytes to be fetched from external memory When the CPU is executing out from external program memory see timing diagram in figure 3 2 all 8 bits of port 2 are dedicated to an output function and may not be used for general purpose 1 O During external program fetches they output the high byte of the PC with the port 2 drivers using the strong pullups to emit bits that are 1 s Semiconductor Group 3 3 SIEMENS CPU Timing C500 Family 31 32 S3 S4 S5 S6 S1 S2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 ALE Data Data Data Sampled Sampled Sampled P2 PCH Out PCH Out PCH Out MCD02772 Figure 3 2 External Program Memory Fetches 3 2 2 Accessing External Data Memory The port 2 drivers use the strong pullups during the entire time that they are emitting address bits that are 1 s This occurs when the MOVX DPTR instruction is executed and when external program fetches are executed During this time the port 2 latch the special function register does not have to contain 1 s and the contents of the por
83. s the transfer to the directly addressed byte indicated No flags are affected Example The stack pointer originally contains the value 32H and internal RAM locations 304 through 32y contain the values 204 23H and 01p respectively The instruction sequence POP DPH POP DPL will leave the stack pointer equal to the value 304 and the data pointer set to 01234 At this point the instruction POP SP will leave the stack pointer set to 20H Note that in this special case the stack pointer was decremented to 2Fy before being loaded with the value popped 20H Operation POP direct SP SP SP 1 Encoding 1101 0000 direct address Bytes 2 Cycles 2 Semiconductor Group 4 63 S EMENS Instruction Set C500 Family PUSH direct Function Description Example Operation Encoding Bytes Cycles Push onto stack The stack pointer is incremented by one The contents of the indicated variable is then copied into the internal RAM location addressed by the stack pointer Otherwise no flags are affected On entering an interrupt routine the stack pointer contains 09H The data pointer holds the value 01234 The instruction sequence PUSH DPL PUSH DPH will leave the stack pointer set to 0By and store 234 and 01y in internal RAM locations OAy and OBy respectively PUSH SP SP 1 SP direct 1100 0000 direct address 2 2 Semiconductor Group 4 64
84. subtracts the second source operand from the first operand the accumulator subtracts one 1 if CY is set and returns the result to A DEC decrement subtracts one 1 from the source operand and returns the result to the operand flags in PSW are not affected Multiplication MUL performs an unsigned multiplication of the A register by the B register returning a double byte result A receives the low order byte B receives the high order byte OV is cleared if the top half of the result is zero and is set if it is not zero CY is cleared AC is unaffected Division DIV performs an unsigned division of the A register by the B register it returns the integer quotient to the A register and returns the fractional remainder to the B register Division by zero leaves indeterminate data in registers A and B and sets OV otherwise OV is cleared CY is cleared AC remains unaffected Flags Unless otherwise stated in the previous descriptions the flags of PSW are affected as follows CY is set if the operation causes a carry to or a borrow from the resulting high order bit otherwise CY is cleared AC is set if the operation results in a carry from the low order four bits of the result during addition or a borrow from the high order bits to the low order bits during subtraction otherwise AC is cleared OV is set if the operation results in a carry to the high order bit of the result but not a carry from the bit
85. t 2 SFR are not modified If the external memory cycle is not immediately followed by another external memory cycle the undisturbed contents of the port 2 SFR will reappear in the next cycle Figure 3 3 and 3 4 show in detail the timings of the external data memory read and write cycles Semiconductor Group 3 4 S EMENS CPU Timing C500 Family S4 S5 S6 States 31 32 S3 S4 S5 P1 P2 P1P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 ALE RD PCL out if Data program memory Sampled is external DPL or Ri Out PCH or PCH or P2 P2 SFR DPH or P2 SFR Out P2 SFR MCD02773 PO Figure 3 3 External Data Memory Read Cycle Zola pi P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 ALE PCL out if program memory is external PO DPL or Ri Data Out Out Li PCL Out PCH or PCH or P2 P2 SFR DPH or P2 SFR Out P2 SFR MCD02774 Figure 3 4 External Data Memory Write Cycle Semiconductor Group 3 5 SIEMEN Instruction Set x C500 Family 4 Instruction Set The C500 8 bit microcontroller family instruction set includes 111 instructions 49 of which are single byte 45 two byte and 17 three byte instructions The instruction opcode format consists of a function mnemonic followed by a destination source operand field This field specifies the data type and addressing method s to be used Like all other members of the 8051 family the C500 microcontrollers can be programmed with
86. t input port 1 is 11001010p The accumulator holds 564 01010110p The instruction sequence JNB P1 3 LABEL1 JNB ACC 3 LABEL2 will cause program execution to continue at the instruction at label LABEL2 JNB PC lt PC if bit O then PC lt PC rel 0011 0000 bit address rel address Semiconductor Group 4 40 S EMENS Instruction Set C500 Family JNC rel Function Description Example Operation Encoding Bytes Cycles Jump if carry is not set If the carry flag is a zero branch to the address indicated otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice to point to the next instruction The carry flag is not modified The carry flag is set The instruction sequence JNC LABEL1 CPL C JNC LABEL2 will clear the carry and cause program execution to continue at the instruction identified by the label LABEL2 JNC PC PC 2 if C O then PC PC rel 0101 0000 rel address Semiconductor Group 4 41 S EMENS Instruction Set C500 Family JNZ rel Function Description Example Operation Encoding Bytes Cycles Jump if accumulator is not zero If any bit of the accumulator is a one branch to the indicated address otherwise pro
87. ta pointer But some members of the C500 family provide eight data pointers The availability of eight data pointers especially supports the programming in high level languages which have a demand to store data in large external data memory portions Special Function Register DPL Address 82 4 Reset Value 00H Special Function Register DPH Address 83H Reset Value 00H Special Function Register DPSEL Address DO Reset Value 00H MSB LSB Bit No 7 6 5 4 3 2 1 0 82H 7 6 D 4 3 2 LSB DPL 83H MSB 6 m 4 3 2 sl 0 DPH 92H B 2 0 DPSEL Bit Function Reserved bits for future use DPSEL 2 0 Data pointer select bits DPSEL 2 0 defines the number of the actual active data pointer DPTRO 7 DPSEL2 DPSEL1 DPSELO Function Data pointer 0 selected Data pointer 1 selected Data pointer 2 selected Data pointer 3 selected Data pointer 4 selected Data pointer 5 selected Data pointer 6 selected OO ca OO o o o o Data pointer 7 selected Semiconductor Group 2 4 S EMENS CPU Functions C500 Family 2 5 1 The Importance of Additional Datapointers The standard 8051 architecture provides just one 16 bit pointer for indirect addressing of external devices memories peripherals latches etc Except for a 16 bit move immediate to this datapointer and an increment ins
88. th bit and byte operands and returns the result to the location of the first operand XRL performs logical Exclusive OR of two source operands byte operands and returns the result to the location of the first operand 4 2 4 Control Transfer Instructions There are three classes of control transfer operations unconditional calls returns jumps conditional jumps and interrupts All control transfer operations some upon a specific condition cause the program execution to continue a non sequential location in program memory Semiconductor Group 4 5 S EMENS Instruction Set C500 Family Unconditional Calls Returns and Jumps Unconditional calls returns and jumps transfer control from the current value of the program counter to the target address Both direct and indirect transfers are supported ACALL and LCALL push the address of the next instruction onto the stack and then transfer control to the target address ACALL is a 2 byte instruction used when the target address is in the current 2K page LCALL is a 3 byte instruction that addresses the full 64K program space In ACALL immediate data i e an 11 bit address field is concatenated to the five most significant bits of the PC which is pointing to the next instruction If ACALL is in the last 2 bytes of a 2K page then the call will be made to the next page since the PC will have been incremented to the next instruction prior to execution RET transfers control to the r
89. the same instruction set common to the basic member the SAB 8051 Thus the C500 family microcontrollers are 10096 software compatible to the SAB 8051 and may be programmed with 8051 assembler or high level languages 4 1 Addressing Modes The C500 uses five addressing modes register direct immediate register indirect base register plus index register indirect Table 4 1 summarizes the memory spaces which may be accessed by each of the addressing modes Register Addressing Register addressing accesses the eight working registers RO R7 of the selected register bank The least significant bit of the instruction opcode indicates which register is to be used ACC B DPTR and CY the Boolean processor accumulator can also be addressed as registers Direct Addressing Direct addressing is the only method of accessing the special function registers The lower 128 bytes of internal RAM are also directly addressable Immediate Addressing Immediate addressing allows constants to be part of the instruction in program memory Semiconductor Group 4 1 S EMENS Instruction Set C500 Family Table 4 1 Addressing Modes and Associated Memory Spaces Addressing Modes Associated Memory Spaces Register addressing RO through R7 of selected register bank ACC B CY Bit DPTR Direct addressing Lower 128 bytes of internal RAM special function registers Immediate addressing Program memory
90. the value 624 01100010p with the carry set Operation RRC An An 1 n 0 6 A7 C C A0 Encoding 00010011 Bytes 1 Cycles 1 Semiconductor Group 4 70 SIEMEN Instruction Set x C500 Family SETB lt bit gt Function Set bit Description SETB sets the indicated bit to one SETB can operate on the carry flag or any directiy addressable bit No other flags are affected Example The carry flag is cleared Output port 1 has been written with the value 344 00110100p The instructions SETB C SETB P1 0 will leave the carry flag set to 1 and change the data output on port 1 to 35H 001101015 SETB C Operation SETB C 1 Encoding 1101 0011 Bytes 1 Cycles 1 SETB bit Operation SETB bit 1 Encoding 1101 0010 bit address Bytes 2 Cycles 1 Semiconductor Group 4 71 S EMENS Instruction Set C500 Family SJMP rel Function Description Example Operation Encoding Bytes Cycles Short jump Program control branches unconditionally to the address indicated The branch destination is computed by adding the signed displacement in the second instruction byte to the PC after incrementing the PC twice Therefore the range of destinations allowed is from 128 bytes preceding this instruction to 127 bytes following it The label RELADR is assigned to an instruction at program memory location 01234 The ins
91. trollers don t provide this internal RAM area MCD02767 Figure 1 2 Internal Data Memory Organization Semiconductor Group 1 4 SIEMENS Fundamental Structure C500 Family While the SFR area and the upper internal RAM area share the same address locations 804 FFH they must be accessed through different addressing modes The upper internal RAM can only be accessed through indirect addressing while the special function registers SFRs are accessible only by direct addressing instructions The SFRs which are located at addresses with address bit 0 2 equal 0 addresses 80H 88H 90H F04 FFH are bitaddressable SFRs 1 2 2 2 Internal Data Memory XRAM Some members of the C500 family microcontrollers provide an additional internal data memory area called the XRAM This data memory area is logically located at the upper end of the external data memory space except C502 but it is integrated on the chip Because the XRAM is used in the same way as external data memory the same instruction types must be used for accessing the XRAM Figure 1 3 shows a typical 256 byte XRAM address mapping of the C500 microcontrollers Internal XRAM External Data Memory 00004 XRAM is located at the upper end of the external data memory area MCD02768 Figure 1 3 XRAM Memory Mapping 256 Byte Depending on the C500 derivative the size of the XRAM area differs from 128 upto 3K byte Further the XRAM can be enabled or disabled If
92. truction DIV AB will leave 13 in the accumulator 0Dy or 00001101p and the value 17 11H or 00010001 p in B since 251 13x18 17 Carry and OV will both be cleared DIV A15 8 B7 0 lt A B 1000 0100 Semiconductor Group 4 30 S EMENS Instruction Set C500 Family DJNZ lt byte gt lt rel addr gt Function Description Example Decrement and jump if not zero DJNZ decrements the location indicated by 1 and branches to the address indicated by the second operand if the resulting value is not zero An original value of 00H will underflow to OFFy No flags are affected The branch destination would be computed by adding the signed relative displacement value in the last instruction byte to the PC after incrementing the PC to the first byte of the following instruction The location decremented may be a register or directly addressed byte Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch not the input pins Internal RAM locations 404 504 and 60 contain the values 01 704 and 15H respectively The instruction sequence DJNZ 40H LABEL_1 DJNZ 50H LABEL 2 DJNZ 60H LABEL 3 will cause a jump to the instruction at label LABEL 2 with the values 00H 6FH and 15y in the three RAM locations The first jump was nottaken because the result was zero This instruction provides a simp
93. truction SJMP RELADR will assemble into location 01004 After the instruction is executed the PC will contain the value 01234 Note Under the above conditions the instruction following SUMP will be at 1024 Therefore the displacement byte of the instruction will be the relative offset 012314 01024 21H In other words an SUMP with a displacement of OFEH would be a one instruction infinite loop SJMP PC PC 2 PC PC rel 1000 0000 rel address Semiconductor Group 4 72 S EMENS Instruction Set C500 Family SUBB A lt src byte gt Function Description Example Subtract with borrow SUBB subtracts the indicated variable and the carry flag together from the accumulator leaving the result in the accumulator SUBB sets the carry borrow flag if a borrow is needed for bit 7 and clears C otherwise If C was set before executing a SUBB instruction this indicates that a borrow was needed for the previous step in a multiple precision subtraction so the carry is subtracted from the accumulator along with the source operand AC is set if a borrow is needed for bit 3 and cleared otherwise OV is set if a borrow is needed into bit 6 but not into bit 7 or into bit 7 but not bit 6 When subtracting signed integers OV indicates a negative number produced when a negative value is subtracted from a positive value or a positive result when a positive number is subtract
94. truction any other pointer handling is to be done byte by byte For complex applications with peripherals located in the external data memory space e g CAN controller or extended data storage capacity this turned out to be a bottle neck for the 8051 s communication to the external world Especially programming in high level languages PLM51 C51 PASCAL51 requires extended RAM capacity and at the same time a fast access to this additional RAM because of the reduced code efficiency of these languages 2 5 2 How the eight Datapointers of the C500 are realized Simply adding more datapointers is not suitable because of the need to keep up 100 compatibility to the 8051 instruction set This instruction set however allows the handling of only one single 16 bit datapointer DPTR consisting of the two 8 bit SFRs DPH and DPL To meet both of the above requirements speed up external accesses 100 compatibility to 8051 architecture the C500 contains a set of eight 16 bit registers from which the actual datapointer can be selected This means that the user s program may keep up to eight 16 bit addresses resident in these registers but only one register at a time is selected to be the datapointer Thus the datapointer in turn is accessed or selected via indirect addressing This indirect addressing is done through a special function register called DPSEL data pointer select register All instructions of the C500 which handle the datapointer th
95. ts but it would not clear the carry flag otherwise If the carry flag is now set or if the four high order bits now exceed nine 1010xxxx 1111xxxx these high order bits are incremented by six producing the proper BCD digit in the high order nibble Again this would set the carry flag if there was a carry out of the high order bits but wouldn t clear the carry The carry flag thus indicates if the sum of the original two BCD variables is greater than 100 allowing multiple precision decimal addition OV is not affected All of this occurs during the one instruction cycle Essentially this instruction performs the decimal conversion by adding 004 06H 60H or 66H to the accumulator depending on initial accumulator and PSW conditions Note DA A cannot simply convert a hexadecimal number in the accumulator to BCD notation nor does DA A apply to decimal subtraction The accumulator holds the value 564 01010110p representing the packed BCD digits of the decimal number 56 Register 3 contains the value 674 01100111p representing the packed BCD digits of the decimal number 67 The carry flag is set The instruction sequence ADDC A R3 DA A will first perform a standard two s complement binary addition resulting in the value OBEy 10111110p in the accumulator The carry and auxiliary carry flags will be cleared The decimal adjust instruction will then alter the accumulator to the value 244 001001005 indicating the packed
96. variable indicated to the accumulator leaving the result in the accumulator The carry and auxiliary carry flags are set respectively if there is a carry out of bit 7 or bit 3 and cleared otherwise When adding unsigned integers the carry flag indicates an overflow occurred OV is set if there is a carry out of bit 6 but not out of bit 7 or a carry out of bit 7 but not out of bit 6 otherwise OV is cleared When adding signed integers OV indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands Four source operand addressing modes are allowed register direct register indirect or immediate Example The accumulator holds 0C3y 1100001 1g and register 0 holds OAAH 10101010p The instruction ADD A RO will leave 6Dy 01101101p in the accumulator with the AC flag cleared and both the carry flag and OV set to 1 ADD A Rn Operation ADD A A Rn Encoding 0010 irrr Bytes 1 Cycles 1 ADD A direct Operation Encoding Bytes Cycles ADD A A direct 00100101 direct address 2 1 Semiconductor Group 4 10 S EMENS Instruction Set C500 Family ADD A Ri Operation ADD A A Ri Encoding 0010 0111 Bytes 1 Cycles 1 ADD A data Operation ADD A A data Encoding 0010 0100 immediate data Bytes 2 Cycles 1 Semiconducto
97. will be read from the output data latch not the input pins Register 0 contains 7Fy 01111111p Internal RAM locations 7Ey and 7FH contain 00H and 40H respectively The instruction sequence DEC RO DEC RO DEC RO will leave register 0 set to 7Ey and internal RAM locations 7Ey and 7Fy set to OFFH and 3FH DEC A A 1 0001 0100 DEC Rn e Rn 1 0 0 O 1 1 rrr Semiconductor Group 4 28 SIEMENS Instruction Set C500 Family DEC direct Operation DEC direct direct 1 direct address Encoding 00010101 Bytes 2 Cycles 1 DEC Ri Operation DEC Ri Ri 1 Encoding 0001 0111 Bytes 1 Cycles 1 Semiconductor Group 4 29 S EMENS Instruction Set C500 Family DIV AB Function Description Example Operation Encoding Bytes Cycles Divide DIV AB divides the unsigned eight bit integer in the accumulator by the unsigned eight bit integer in register B The accumulator receives the integer part of the quotient register B receives the integer remainder The carry and OV flags will be cleared Exception If B had originally contained 004 the values returned in the accumulator and B register will be undefined and the overflow flag will be set The carry flag is cleared in any case The accumulator contains 251 OFBy or 11111011p and B contains 18 124 or 00010010p The ins
98. y flag The program control section of the core controls the seguence in which the instructions stored in program memory are executed The 16 bit program counter PC holds the address of the next instruction to be executed The conditional branch logic enables internal and external events to the processor to cause a change in the program execution seguence 2 1 Accumulator ACC is the symbol for the accumulator register The mnemonics for accumulator specific instructions however refer to the accumulator simply as A 2 2 B Register The B register is used during multiply and divide and serves as both source and destination For other instructions it can be treated as another scratch pad register 2 3 Program Status Word The Program Status Word PSW contains several status bits that reflect the current state of the CPU The bits of the PSW are used for different functions which are two register bank selection bits two carry flags and an overflow flag for arithmetic instructions a parity bit for the content of the ACC and two general purpose flags The bit definitions of the PSW are shown on the next page Semiconductor Group 2 2 SIEMENS CPU Functions C500 Family Special Function Register PSW Address DO Reset Value 00H Bit No MSB LSB 7 6 5 4 3 2 1 0 DOH CY AC FO RSI RSO OV F1 P PSW Bit Function CY Carry Flag Used by arithmetic

User`s Manual 01.97 Microcontroller Family Architecture and

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