(TKDN-SP6-16/45) Hardware manual
Contents
1. your basebord s usage 7 Copyright 2009 7 7 OH 0000 All rights reserved Chapter 3 Configuring the FPGA 3 1 Howto Configure FPGA is volatile its data is deleted by power off so it should be configured in some way There are two configuration ways First is configuring FPGA directory and second is writing the configuration data to the serial flash ROM See Table 3 Feature Table 3 Configuration ways Direct configure Serial Flash ROM volatile nonvolatile volatile nonvolatile Configuration time Fast about 5 second Late about 1 minute Configuration tool Tokuden s freeware sp6jtag exe MITOUJ TAG XILINX iMPACT can also Tokuden s freeware sp6jtag exe MITOUJ TAG XILINX iMPACT can also Main Purpose Testing Operate standalone After you wrote configuration data to serial flash ROM it works immediately on power on However it takes long times to write the data to serial flash ROM soit is suitable for standalone operating When you configure FPGA directory configuration time is short and it is suitable for prototype developing although the configuration data is erase when the power is turned Off 8 Copyright 2009 OOO0d00 0 All rights reserved 3 2 Using USB Cable On board USB TAG writing is the best way to configure FPGA J TAG is the IC testing standard and also be utilized as F PGA configuration 1 Get the free confi2. 0 All rights reserved Chapter 4 DDR2 SDRAM Quimonda DDR2 SDRAM is on board Memory size is 512M bit data bus width which connects to FPGA is 8bit and maximum clock frequency is 400MHz Connection to FPGA and SDRAM is shown in Table 4 These signals are SSTL 18 interface These pins can be accessed with Memory Controller Block MCB embedded in Spartan 6 Table 4 Connection between DDR2 SDRAM and FPGA FPGA FPGA DDR2 DDR2 f Pin function Pin function Pin name Pin name number number AO H15 DO M16 Al H16 D1 M18 A2 F18 D2 L17 A3 J13 D3 L18 Data Bus A4 E18 D4 H17 A5 L12 D5 H18 A6 L13 D6 J16 Address Bus A7 F17 D7 J18 A8 H12 DQSp K17 Data strobe A9 G13 DQSn K18 A10 E16 RAS K15 All G14 CAS K16 SDRAM A12 D18 WEN K12 Control signal A13 C17 CS BAO H13 ODT K14 Terminating Bank address Resistor ON OFF BA1 H14 DM L16 Data mask CKp G16 Clock CKE D17 Clock Enable CKn Lois ee A ee 11 Copyright 2009 7 7 OH 0000 All rights reserved Chapter 5 Connectors and I O Features 5 1 CNUT 40pin Extender CN1 is the user connecter located on board s under side 36 general purpose O GPIO are available Table 5 shows the pin assign Table 5 CN1 pin assign FPGA f i FPGA l Function Function Pin number Pin number P3 N4 P4 N3 N5 V4 T3 T4 R3 T8 R8 GPIO T9 GPIO B12 GPIO B14 GPIO B15 3 3V Powe
3. C Power J ack 1 for CN3 gt Pinheader 40 pin 2 for CN1 CN2 Attach them on demand 2 2 Power Supply The main source of power is one of the following four ways From USB Short J 1 and the board becomes U SB supply mode This supply line contains 500mA resettable fuse so this board s maximum consumption current is 500mA When you use another power supply you must not short J 1 FromAC adapter Attach DC power J ack to CN3 and supply 5V DC with AC adapter From pinheader 5V Supply 5V from CN6 which is located on the underside of DC power jack From pinheader 3 3V Supply 3 3V from CN1 17th pin CN1 18th pin CN 1 29th pin CN1 30th pin 6 Copyright 2009 7 7 OH 0000 All rights reserved 2 3 J umper Setting This board has three jumper J 1 J 2 3 J2 and J 3 is recommended to short J 1 is connected as necessary J3 vd SCH ERR A 4 d fees Eok O Ps i R Ze oer V f ARVO Os LC J1 J2 i Ee 9088 FTO BEN ZER SBS SERRE LG e Figure 2 Jumper s position Table 2 Description of Jumper Function J 1 enables USB supply mode In case that the board s consumption current exceeds 500mA or the board is supplied from 5V AC adapter open J 1 J 2 enables the USB setting data It is used for restoring in the case of writing failure of USB setting data J 2 is recommended to short in normal use J 3 connects CN2 to 3 3V power supply Choise short or open depend on
4. TOKUDEN Spartan 6 Evalutaion Board TK DN SP6 16 45 Hardware manual Rev 3 August 10 2010 Tokushu Denshi Kairolnc Notes For safety using please note the operating suggestions listed below Failure to use caution may lead to personal injury fire or property damage JI ER 30 4 Take care not to damage shock or be injured in touching the current carrying device When this product is inserted with wrong direction it may have a serious damage Inserting and removing should be done under the power off Take care not to make impact heating or vibrate hardly When some trouble has found power off and check the board This product is intended for education preproduction and testing the FPGA s behavior so that Tokushi Denshi Kairo Inc assumes no responsibility for any results from other usage and couldnt be applied to following high risk application without written pre permission JI 20 30 40 2 el 70 el 94 Instruments associated with human life Medical Equipment Instruments which may affect natural environment someone s health or belonging adversely by malfunction Instruments which may cause fire hazard by malfunction Aerospace instrument and navigation system Tactical weapon system manufacture system or their helping system for military purposes Instruments rerated nuclear power Electric power tools Other instruments which may cause some trouble and damag
5. ble 8 SPI LEDs Switch Cristal Oscillator FPGA Pin number function F13 LEDO lights up at H level LED3 C11 LED1 lights up at H level LE D2 lights up at H level LED3 lights up at H level LED4 LED4 lights up at H level LED5 LED5 lights up at H level LED6 LED6 lights up at H level LED7 LED7 lights up at H level Switch When SW1 is pushed H level signal is input Cristal Oscillator 50MHz Clock 14 Copyright 2009 7 7 OH 0000 All rights reserved Chapter 6 Support Support Additional information reference device driver sample application newest P Core is provided at following URL htt p ww t okudenkai ro co j p sp6brd ht nh About J TAG HIROBA J TAG HIROBA is a community among only our product s user It is intended to provide support technical information and to fix bug You can get secret information which is not published on Web J oin it now htt p ww t okudenkai ro co j p j tag sns ht nh Tokuden Spartan 6 Evaluation Board User Manual Rev3 August 5 2010 Tokusyu Denshi Kairo inc Copyright 2010 Tokusyu Denshi Kairoinc All rights reserved 15 Copyright 2009 7 7 OH 0000 All rights reserved
6. e by occurring malfunction or loss of data 1 Copyright 2009 7 7 OH 0000 All rights reserved Index INErOdUCHON oo ete DUUIDUDDDUDUDDDUDDDDUDDDDUD Chapter We e 4 TI OVE VIEW iini aa Hoek hahah asin ane ahaa 4 1 2 Funcional Description cccccccccccsssssssseeceeecesseseeeeeeeeeceseseessneaeeeeeeeesesesnaneeeeeeeess 4 1 3 Hardware Requirement ccccccccccccccccsssssscreccesscssssssaeeeeeesssseseeeaeeeeeeeesesesnaneeeeeesess 5 Chapter 2 SSCP DE 6 21 Connector Attamen sesiscceaavetsdedcadcsecsvavescieeceveceuanetsseces cecdcauevessdiacy cceusetsduvetenceeesuenes 6 2 2 POWER SUDDIY EE 6 2 3 Jumper Setting 7 Chapter 3 Configuring the FPGA sssssssssssrrrrsssssserrrrrrsrssrnrrrrnnsrsrnrrnrnnsnsnrnrrrrnnsnssrnrrenent 8 3 1 Howto L eu IER 8 SREL ET 9 3 3 Using Other J TAG Cable i ri aera eee eines eenicieeeennniaeeeen 10 34 Reconfigure FRGA wis sissedetccedaabicaesisstectdanssvievesinescananstsavandecedanbessssvavtzeneteasavaveaeretens 10 Chapter 4 DDR2 SDRAM E 11 Chapter 5 Connectors and I O Features 12 5 1 CN1 40pin Extender re 12 5 22 CN2 H 40pin Extender ccccccccscccccecssscssesseeeeeeseesesseseeeeeessesssesseseeeeesessseesaeas 13 5 3 CNS for SPI Writing cciscssectsscesecacisassevsterecsseacsstatutenseredassavavacteansiasvetestereciaes 14 5 4 LEDs Switch Cristal Oscillator essssssssssessrrssssrnssnsrnnntinnnntnnnnnntnnnnnnnnnnnnnnnnnne 14 Chapter 6 SUpPP0rt c cece ececneeee
7. eecnee erences E EEAS SE SARE E MEd Asii rAE EErEE AARAA ER NENTE RER Eai Aie 15 2 Copyright 2009 0000000 All rights reserved Introduction Thank you for purchasing TOKUDEN Spartan 6 Evaluation Board TK DN SP6 16 45 This product helps you a lot to develop your original control device using XILINX s newest FPGA Spartan 6 Notice O O This paper and product s specification may change without preliminary announce because of its improvement 0 O Tokusyu Denshi Kairo Inc put the maximum effort into making this product but if you have detect some problem please contact us 0 O0 Tokusyu Denshi Kairo Inc assumes no responsibility for any results from whatever usage Components This package includes Tokuden Spartan 6 Evaluation Board 1 Accessories gt Pinheader 40 pin 2 gt DC Power J ack This board requires MiniB USB cable to configure FPGA by J TAG You need not to prepare J TAG cable 3 Copyright 2009 7 7 OH 0000 All rights reserved UO TOKUDEN Chapter1 Overview 1 1 Overview Tokuden Spartan 6 Evaluation Board TKDN SP6 16 45 is an evaluation board to evaluate Spartan 6 easily which is the newest F PGA of XILINX 8838885 Z 6 Evduotion Se u3 setifrtiittt1t3 3 STokustw Gone Karo inc gt per fi Figure 1 Top View of the TKDN SP6 16 45 1 2 Features This product has the following features It carries large scale FPGA gt TKDN SP6 16 Spartan 6 XC6SLX16 CSG324 14 579
8. guration tool SP6 TAG exe from our Web site http www tokudenkairo co jp sp6en 2 Connect the PC and board s USB connector via MiniB USB Cable 3 Boot MS DOS prompt and type following command sp6j tag exe aut of enane bi t Configuration will be done in about 3 seconds C CTO ere hem DEn ml eng Figure 3 a Connect via USB Figure 3 b Configuration with SP6 TAG SP6J TAG also supports writing to SPI Flash ROM For SPI Flash ROM writing type following command sp6j tag exe spi autof enane bi t Writing will be done in about 30 seconds You don t need to convert bit stream file to MCS file Write it as it is 9 Copyright 2009 7 7 OH 0000 All rights reserved UU TOKUDEN 3 3 Using Other J TAG Cable Other J TAG cable is available at CN2 which is placed at the upper left side of the board Connect the board pins V C 1 M O G to fry lead wire Vref TCK TDI TMS TDO GND See board s silk and Figure 4 When J 3 is shorted 3 3V power is supplied from CN2 Figure 4 JTAG connetion And write BitStream file bit to FPGA with MITOUJ TAG J Writer or iMPACT and so on 3 4 Reconfigure FPGA To reconfigure FPGA push red switch SW2 which lead FPGA s PROGRAM pin falls to Low and the F PGA is reconfigured ln reconfiguration all I Os are high impedance If any configuration data has already written to SPI ROM the data will boot Figure 5 Reset Switch 10 Copyright 2009 000000
9. logic cells 32 DSP 48 slices and 32 18kB Block RAMs gt TKDN SP6 45 Spartan 6 XC6SL X45 CSG324 43 661 logic cells 58 DSP 48 slices and 116 18kB Block RAMs gt DDR2 SDRAM HYB18T512800BF 2 5 Quimonda company 512Mbit 64M word 8bit width 4 banks Maximum data rate 400M Hz gt Cypress Semiconductor EZ USB FX2LP CY 7C68013A Put together the application transfer and USB J TAG function into only one USB port gt Maximum Effective Transfer Speed ODIN about 40M Bytes sec O0 OUT about 30MBytes sec It depends on your PC specification 4 Copyright 2009 7 7 OH 0000 All rights reserved gt 64user I Os Easy extending 2 54mm pitch pinheader gt FPGA Configuration from Onboard SPI ROM ATMEL SPI Flash Memory AT45DB161D 16M bit memory It can storage FPGA configuration data about 4M bit and user data Another company s memory IC may be applied depend on the product availability gt OnBoard LED Display and Push Switch gt OnBoard Cristal Oscillator 50M Hz 1 3 Hardware Requirements Table 1 Hardware Requirements Condition PC AT compatible machine 1SE11 3 or later is necessary for logic synthesis Windows2000 XP 7 Vista 32bit edition USB device driver doesn t support 64bit edition Pentium I11 800MHz or faster processor recommended 5 Copyright 2009 7 7 OH 0000 All rights reserved Chapter 2 Setup 2 1 Connector Attachment This product contains following parts gt D
10. r 3 3V Power GPIO B16 GPIO B17 GPIO B18 GPIO B19 GPIO B20 GPIO B21 GPIO B22 GPIO B23 GND 12 Copyright 2009 7 7 O0000 All rights reserved 5 2 CNA 40pin Extender CN2 is the user connecter located on board s upper side 28 general purpose 1 O GPIO and signals associated in FPGA configuration are available Table 6 shows the pin assign Pin number FPGA Pin number Table 6 CN2 pin assign Function FPGA Pin number Function V17 DON E 3 3V Power on demand B18 J TAG signal TMS PROGRAM B A17 J TAG signal TCK TAG signal TDO C6 B3 GND J TAG signal TDI B4 CS B6 C7 D8 GPIO A16 GPIO A17 3 3V GPIO A18 Power 3 3V Power GPIO A19 13 Copyright 2009 0000000 All rights reserved 5 3 CN5 for SPI Writing CN5 is used as SPI writing It is done by sending SPI signal to CN5 using XILINX J TAG cable and so on But it is not recommended FPGA Pin number Table 7 CNS pin assign Function 3 3V Reference Output R15 Configuration Clock T13 SPI Data Output V3 SPI Selector R13 Configuration Data Input 5 4 LEDs Switch Cristal Oscillator Table 8 shows a on board component s pin assign Ta
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