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Multimedia Processor for Mobile Applications (EMMA

1. This interrupt is issued when an error response is received during internal bus transfer This interrupt is issued upon a prohibited operation such as writing to the ea eae AI 1 Indicates the status of the DMA completion interrupt This interrupt is issued every time the number of packets specified in the DMA completion interrupt setting register 4015_003CH have been transferred via DMA transfer protected area User s Manual 19267EJ4VOUM 43 CHAPTER 4 DTV2 Details 4 3 4 Interrupt enable set register This register DT2 ENSET 4015 0008H enables issuance of interrupt requests When the bit corresponding to an interrupt source is set to 1 in this register if the interrupt source is set an interrupt request is issued and the corresponding bit of the interrupt status register DT2 STATUS is set to 1 Writing O to this register does not affect the setting The interrupt request issuance enable status can be checked by reading this register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved DTVLP EN DTVSP EN DTVSYNC DTVSTOP_EN DTVOR EN DTVDMA EN DMAERR EN EN 1 2 Reserved R 317 o Reserved Reading returns the unsettled value Writing in is ignored DTVLP EN Indicates whether issuance of packet length excess interrupt request is enabled 0 Not enabled 1 Enabled W Specifies whether to enable issuance of packet length excess
2. ioo lilas 3 4 Function details ii 0 44 Input Signal Timing a eke pins 3 4 2 Data Formal tras 3 4 3 DIV Transfer Processing nee ERI ERI EC eed cervice 3 44 InterruptGontrO mirta crece p t a eed cc ettet rta 3 4 5 Olocks Control 1 RARE dete Ule dee ee ee ed RE edt 3 4 6 Return method from synchronous difference sss eee eee eee CHAPTER 4 DTV2 Details iiie cendo aida 4 1 Function Block DIagram sssssssesssees sees sees sees sees se essere ereenn 4 2 cs L 0 nn gawa A enel CONTENTS User s Manual S19267EJAVOUM 1 3 Module Structure DTV and DTV2 1 4 Clock Supply 1 5 Reset Reset release 1 6 Atthe timing of DTV DTV2 change 43 4 4 Register FUNCHONS io ri 41 4 31 DTV DTV2 change register iii 41 4 3 2 Interface status register tarda 42 4 3 8 Interface raw status register ie 43 4 3 4 Interrupt enable set register scene nitens nnns intentan nete asina ente 44 4 3 5 Interrupt enable clear register enit it ette pec e ng t deck e Ride gen 46 4 3 6 Interrupt source clear register sister 47 4 3 7 Error address register atre tih t ct t ete e E ted 48 4 3 8 Transfer control register sisia ibn eC ABC Re REP REUS 49 4 3 9 Transfer request registered rk anke eese ta ra spe go roa se edere eye re a NGENEH 50 4 3 10 Transfer request cancellation register 51 4 3 11 Start address regida is 52 43 12 B ffer size register itte cte m ditte e p bte he ER e Eo Oo
3. User s Manual S19267EJ4VOUM 17 CHAPTER 3 DTV Details 3 3 3 Interface raw status register This read only register DT RAWSTATUS 4015 0004H can be used to read the status of the interrupt sources regardless of the setting of the interrupt enable set register DT ENSET 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved DTVSTOPRAW DTVORRAW DTVDMARAW DMAERRRAW Reserved R 3t4 o Reserved Don t write in anything but O It s prohibited to write in 1 DTVSTOP 3 Indicates the status of the DMA stop interrupt RAW This interrupt is issued when DMA stops DTVORRAW 2 Indicates the status of the packet overrun error interrupt This interrupt is issued when the internal buffer overruns DTVDMA 1 Indicates the status of the DMA completion interrupt RAW This interrupt is issued every time the number of packets specified in the DMA completion interrupt setting register 4015 003CH have been transferred via DMA DMAERR Indicates the status of the transfer error interrupt RAW This interrupt is issued when an error response is received during internal bus transfer This interrupt is issued upon a prohibited operation such as writing to the transfer protected area 18 User s Manual 19267EJ4VOUM CHAPTER 3 DTV Details 3 3 4 Interrupt enable set register This register DT_ENSET 4015_0008H enables issuance of interrupt r
4. Reset 1 Cancels reset 30 User s Manual 19267EJ4VOUM CHAPTER 3 DTV Details 3 4 Function details 3 4 1 Input Signal Timing 1 DTV I F signal timing Figure 3 5 DTV Interface Signal Timing DTV_BCLK DTV_PSYNC DTV_VLD DTV_DATA 7 0 Tsetup Thold 2 Stream timing Figure 3 6 Stream Timing Burst Serial Output DTV_BCLK DTV_PSYNC DTV_VLD DTV DATA 7 Sync 1 byte Data 187 bytes Parity 16 bytes 44 7 Caution When reception of the parity field is selected a blanking interval of at least 2T DTV BCLK cycles must be inserted between packets User s Manual 19267EJ4VOUM 31 CHAPTER 3 DTV Details 3 4 2 Data Format Figure 3 7 Stream Data Storage Format DTV_PSYNC AA LAC N DTV_DATA 7 0 Data 187 bytes Parity 16 bytes Sync 1 byte Data input as shown in Figure 3 7 is stored in the memory in the following format in accordance with the value set to the DTVENDIAN bit of the transfer control register DT_DMACNT Bit alignment 31to24 231016 15to8 7to0 311024 23t016 15108 7100 50 words P12 48 words 47 words 3 words 2 words 1 word 0 words Little endian Big endian 32 User s Manual 19267EJ4VOUM CHAPTER 3 DTV Details 3 4 3 DTV Transfer Processing Stream data is transferred to t
5. transfer prohibited area CHAPTER 4 DTV2 Details 4 3 3 Interface raw status register This read only register DT2_RAWSTATUS 4015_0004H can be used to read the status of the interrupt sources regardless of the setting of the interrupt enable set register DT2_ENSET 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 DTVLPRAW DTVSPRAW DTVSYNCR DTVSTOPRAW DTVORRAW DTVDMARAW DMAERRRAW AW Reserved R 37 o Reserved Reading returns the unsettled value Writing in is ignored DTVLPRAW Indicates the status of the packet length excess This interrupt is issued when 1 packet exceeded 188byte or 204byte interrupt is generated DTVSPRAW Indicates the status of the packet length short This interrupt is issued transfer data includes SyncByte and the transfer amount of the just before packet data generates interrupt in case of less than 187 bytes or less than 203 bytes DTVSYNCRA 4 Indicates the status of the illegal SyncByte W DTVSTOP RAW DTVDMA RAW DMAERR RAW This interrupt is issued the value of SyncByte generates interrupt in case of 47H or anything but B8H Indicates the status of the DMA stop interrupt This interrupt is issued when DMA stops Indicates the status of the packet overrun error interrupt This interrupt is issued when the internal buffer overruns Indicates the status of the transfer error interrupt
6. 1 Terrestrial Digital TV Interface Pins aa int Data clock SPZ CLK DTV_DATA FAT SP2 Si DTV PSYNC input Packet synchronization signal SP2 SO DTV VLD input Packet data enable SP2 CS0 User s Manual 19267EJ4VOUM 13 CHAPTER 3 DTV Details 3 1 Function Block Diagram 14 o 3 a E 2 D gt a Data Buffer Frame Buffer Packet Stream Interface Lad Control Le Interface Figure 3 1 DTV Block diagram User s Manual S19267EJ4VOUM DTVDATA 7 0 DTVPSYNC DTV_BCLK CHAPTER 3 DTV Details 3 2 Registers Do not access reserved registers Any value written to reserved bits in each register is ignored Base address 4015 0000H Register Name Register Symbol After Reset 0020H DTV DTV2 change register DT SWITCH 0000_0000H DTV DTV2 change register DT_SWITCH 0 can use following register 4015_0000H to 4015_0040H overlaps DTV2 but at DT_SWITCH 0 register operation is reflected by only a DTV register Base address 4015_0000H o reraosan CA n rom ot race anse rpg forranemeus R ooo ooon ow Toenn Taa CTN User s Manual 19267EJ4VOUM 15 CHAPTER 3 DTV Details 3 3 Register Functions 3 3 1 DTV DTV2 change register This register DT SWITCH 4015 0200H changes DTV and DTV2 exclusively 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12
7. 11 10 9 8 Reserved 7 6 5 4 3 2 1 Reserved SWITCH Reserved R sin o Reserved Reading returns the unsettled value Writing in is ignored SWITCH RAN DTV DTV2 change 0 DTV 1 DTV2 3 3 2 Interface status register This read only register DT STATUS 4015_0000H can be used to read the status of the interrupt sources enabled by the interrupt enable set register DT_ENSET 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved DTVSTOP DTVOR DIVDMA DMAERR Reserved R aa o Reserved Don t write in anything but 0 It s prohibited to write in 1 DTVSTOP 3 Indicates the status of the DMA stop interrupt This interrupt is issued when DMA stops 16 Users Manual S19267EJAVOUM DTVOR DTVDMA DMAERR CHAPTER 3 DTV Details Indicates the status of the packet overrun error interrupt This interrupt is issued when the internal buffer overruns Indicates the status of the DMA completion interrupt This interrupt is issued every time the number of packets specified in the DMA completion interrupt setting register 4015 003CH have been transferred via DMA Indicates the status of the transfer error interrupt This interrupt is issued when an error response is received during internal bus transfer This interrupt is issued upon a prohibited operation such as writing to the transfer prohibited area
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9. Interface User s Manual S19265E User s Manual 19267EJ4VOUM 35 CHAPTER 3 DTV Details 2 DTV CLKREQ set timing When the DTV transfer request register is set 3 DTV CLKREQ clear timing When the DTV transfer request cancellation register is set and DMA transfer of the current packet is completed 4 DTV_SWT_CLKREQ output timing The signal 1CLK preceded to transaction is output as CLKREQ for bus switches Signal rising is 1CLK precedence of transaction and a fall is at the timing of an end of the data phase CO IDLE 1 1 DTV CLK f D D f f DTV SWT CLKREQ U r 1 DTV SWT HTRANS DTV_SWT_HADDR 1 I 1 DTV SWT HWDATA 1 1 D 1 1 1 1 1 3 L SWT_DTV_HREADY H i I 1 D 1 n 1 1 1 1 1 i 1 1 1 1 1 Figure 3 12 DMA SWT CLKREO Timing 5 Clock restriction DTV 3 clocks of CLK is need to 32 clocks of DTVBCLK for a data delivery between the external clock and the internal clock 32 DTVBCLK gt 3 DTV CLK DTV_CLK gt 0 093 DTVBCLK Caution Even when a clock stop period occurs in clock changes convert it into a frequency and judge normal movement pros and cons User s Manual S19267EJ4VOUM CHAPTER 3 DTV Details l x x d 2 E E ersion of DTV CLK and DTVBCLK Figure 3 13 Frequency conv 6 Relation between DTVBCLK and input data Supply is also necessary to DTVBCLK by the following case outside the effective
10. bits User s Manual 19267EJ4VOUM 5 Related Documents The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such Caution The related documents listed above are subject to change without notice Be sure to use the latest version of each document when designing 6 User s Manual 19267EJ4VOUM CHAPTER 1 OVERVIEW 1 1 General 1 2 Features CHAPTER 2 PIN FUNCTIONS 2 1 Terrestrial Digital TV Interface Pins CHAPTER 3 DTV Details 3 4 Function Block Diagram 3 2 Registers 3 3 Register Functions 3 81 DTV DTV2 change register einen 3 9 2 Interface st tus register oem cie eter tete Dt pe vete dr 3 3 8 Interface raw status register ire 344 Interrupt enable set register i i eere met tc ec ze ree aa arai 3 3 5 Interrupt enable clear register ss 3 3 6 Interrupt source clear register iii 3 3 7 Erroraddress register ist O 3 3 8 Transfer control register wasana a ede a nn 3 39 Transfer requestregisteriss sien as a 3 3 10 Transfer request cancellation register 33 11 Start address register Akri ria tee pte ade ce a edet erus 3 3 12 Buffer size register besos eee peu boe BOR petes ett iens 3 9 13 Blank size register assistante mne nec t pa a io a deep gluten iva Pee cp a id dub ee 3 3 14 Current packet register issues 3 3 15 DMA completion interrupt setting register 33 16 Module control register
11. circuitry Each unused pin should be connected to Voo or GND via a resistor if there is a possibility that it will be an output pin All handling related to unused pins must be judged separately for each device and according to related specifications governing the device PRECAUTION AGAINST ESD A strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it when it has occurred Environmental control must be adequate When it is dry a humidifier should be used It is recommended to avoid using insulators that easily build up static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON devices with reset functions have not yet been initialized Hence power on does not guarantee output pin levels I O settings or contents of registers A device is not initialized
12. come after restoration from a FIFO overflow by a packet overrun b When next SyncByte has come An excess is repealed after the transfer amount of the data exceeded a packet of effective size c When the transfer amount of the data is a packet of effective size sheep rise and next SyncByte has come The shortage will be unsettled data d When it s different from the expectation value 47H or B8H is established by the DTVMODE bit of the DMA control register in the price of received SyncByte 64 User s Manual 19267EJ4VOUM CHAPTER 4 DTV2 Details Figure 4 20 Stock method of a packet at DTVMODE 0 CLK PSYNC ByteData b1 b2 b3 c0 ci c2 c3 dO di d2 d3 haddr b c hwdata e 1st word 2nd word 3rd word Every time match FIFO 4 1packet bytes DMA is forwarded P 188 188 x N 1 N packet memory image Figure 4 21 Packet stock method when next SyncByte has come at DTVMODE 0 CLK PSYNC ByteData a0 al a2 X a3 bO X bl e0 Cel c2 03 d0 di d2 d3 e0 el Em een A haddr ES b di hwdata 2nd word 3rd word last 2bytes are dummy 188 188 blank 2packet 376 Memory image User s Manual 19267EJ4VOUM 65 CHAPTER 4 DTV2 Details 4 4 4 Interrupt Control DTV2 I F issues 7 kinds of interrupt Control of each interrupt interrupts and it s assigned to each bit of the s
13. operation and application examples The incorporation of these circuits software and information in the design of a customer s equipment shall be done under the full responsibility of the customer NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information e While NEC Electronics endeavors to enhance the quality and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely In addition NEC Electronics products are not taken measures to prevent radioactive rays in the product design When customers use NEC Electronics products with their products customers shall on their own responsibility incorporate sufficient safety measures such as redundancy fire containment and anti failure features to their products in order to avoid risks of the damages to property including public or social property or injury including death to persons as the result of defects of NEC Electronics products NEC Electronics products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to NEC Electronics products developed based on a customer designated quality assurance program for a specific application The recommended applications of an NEC Electronics product depend on its quality grade as indicated be
14. packet overrun occurs packet data input via the channel decoder LSI and data stored in the ring buffer becomes inconsistent In such a case terminate DMA once reserve a sufficient band for the internal bus and then load data again 4 DMA stop interrupt Transfer Request Transfer Request DTV Stream Data output packeto Packet DMA Transfer time AHB Write DMA Status DMA Stop Reguest Figure 3 11 DMA stop interrupt Timing Caution Leave the space for 10 cycles of DTVBCLK by the transfer request register set which resumes DMA after DMA stop interruption 3 4 5 Clocks Control In EM1 supply of the internal bus clock is controlled by each module to save power The internal bus clock is supplied upon requests from modules and upon register access In the DTV interface a clock supply request is set when a DMA transfer is requested through register access and the clock supply request is cleared when transfer of the current DMA is completed with no other transfers requested 1 Clocks used in DTV interface a DTV_BCLK external input clock Used for capturing the DTV data clock and data b DTV CLK DTV internal clock Used for the AHB bus clock and the internal operation of the DTV interface c DTV PCLK APB clock Used for the accessing the APB bus registers For details about clock reset settings see the Multimedia Processor for Mobile Applications System Control General Purpose I O
15. t itp Self iov et det 52 43 13 Blank Size r gist r noii A EIE ee nd 53 4 3 14 Current packet register sisi 54 4 3 15 DMA completion interrupt setting register 55 433 16 Module control register piter ente tr Pre eedem a a eet egere tee pede 56 4 3 17 DTVPSYNC DTVVLD Polarity designation register seen 57 4 3 18 Input pin status monitor register ss 58 la hiniin2clgme ED ET P M 59 44 1 o Ue READ ERUIT d ere rt OR RR a aaa a 59 4 42 4 Data Format AT wi diete dt o aa fe ciTe ut nel 63 443 DIN Transfer Processing si tr ORE e 64 4 4 4 Interruptor dee e E n ee ded ai doe 66 4 45 Clocks Gohlrol 3 iecit etae atest testes tien A ie s eet tes b se tetas are 69 User s Manual S19267EJ4VOUM LIST OF FIGURES Figure No Title Page Figure 151 BlOCK diagram Un AR Re RR RME In ne de ATE eed nine Mains 12 Figure 3 1 DIVWBlock lt T Te Lr T anses iria ape Sete 14 Figure 3 2 DMA Stop Timing iiir me A einen CR Eg 25 Figure 3 2 Current Packet Register Values sisi 28 Figure 3 4 DTV Interface DMA Completion Interrupt Set Timing sese eee eee eee ee eee eee eee eee 29 Figure 3 5 DIV Interface Signal Timing ssi sawa aaa anaa recette T 31 Figure 3 6 Stream Timing Burst Serial Output sienne 31 Figure 3 7 Stream Data Storage Format sise 32 Figure 3 8 Ring Bu ffer Mapping ised 17 iip een rit a ga NG a tas 33 Figure 3 9 Transfer error interrupt
16. to the 1 0 September 30 2009 8 0 Incremental update from comments to the 2 0 4 5 chapters and 4 6 chapters are added October 13 2009 4 0 The item of DTV2 is added chapter 4 User s Manual S19267EJ4VOUM For further information please contact NEC Electronics Corporation 1753 Shimonumabe Nakahara ku Kawasaki Kanagawa 211 8668 Japan Tel 044 435 5111 http www necel com America NEC Electronics America Inc 2880 Scott Blvd Santa Clara CA 95050 2554 U S A Tel 408 588 6000 800 366 9782 http www am necel com Europe NEC Electronics Europe GmbH Arcadiastrasse 10 40472 D sseldorf Germany Tel 0211 65030 http www eu necel com Hanover Office Podbielskistrasse 166 B 30177 Hannover Tel 0511 33 40 2 0 Munich Office Werner Eckert Strasse 9 81829 M nchen Tel 0 89 92 10 03 0 Stuttgart Office Industriestrasse 3 70565 Stuttgart Tel 0 711 99 01 0 0 United Kingdom Branch Cygnus House Sunrise Parkway Linford Wood Milton Keynes MK14 6NP UK Tel 01908 691 133 Succursale Francaise 9 rue Paul Dautier B P 52 78142 Velizy Villacoublay C dex France Tel 01 3067 5800 Sucursal en Espa a Juan Esplandiu 15 28007 Madrid Spain Tel 091 504 2787 Tyskland Filial T by Centrum Entrance S 7th floor 18322 T by Sweden Tel 08 638 72 00 Filiale Italiana Via Fabio Filzi 25 A 20124 Milano Italy Tel 02 667541 Branch The Netherlands Steijgerweg 6 5616
17. until the reset signal is received A reset operation must be executed immediately after power on for devices with reset functions POWER ON OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface as a rule switch on the external power supply after switching on the internal power supply When switching the power supply off as a rule switch off the external power supply and then the internal power supply Use of the reverse power on off sequences may result in the application of an overvoltage to the internal elements of the device causing malfunction and degradation of internal elements due to the passage of an abnormal current The correct power on off sequence must be judged separately for each device and according to related specifications governing the device INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I O pull up power supply while the device is not powered The current injection that results from input of such a signal or I O pull up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device User s Manual S19267EJ4VOUM The names of other companies and products are the registered trademarks or trademarks of the respectiv
18. 0 9 8 Reserved 7 6 5 4 3 2 1 0 DTVLP DTVSP DTVSYNC DTVSTOP DTVOR DTVDMA DMAERR Reserved R 37 o Reserved Reading returns the unsettled value Writing in is ignored DTVLP Indicates the status of the packet length excess This interrupt is issued when 1 packet exceeded 188byte or 204byte interrupt is generated DTVSP Indicates the status of the packet length short This interrupt is issued transfer data includes SyncByte and the transfer amount of the just before packet data generates interrupt in case of less than 187 bytes or less than 203 bytes Indicates the status of the illegal SyncByte This interrupt is issued the value of SyncByte generates interrupt in case of 47H or anything but B8H Indicates the status of the DMA stop interrupt DTVSTOP DTVOR DTVDMA DMAERR 42 Users Manual 19267EJ4VOUM This interrupt is issued when DMA stops Indicates the status of the packet overrun error interrupt This interrupt is issued when the internal buffer overruns EN ala ed 1 Indicates the status of the DMA completion interrupt This interrupt is issued every time the number of packets specified in the DMA completion interrupt setting register 4015 003CH have been transferred via DMA Indicates the status of the transfer error interrupt This interrupt is issued when an error response is received during internal bus transfer This interrupt is issued upon a prohibited operation such as writing to the
19. 1 Figure 4 14 The bit just before the DTVPSYNC arrival was filled in 8bits when don t have that Burst Serial Output A a KKN SEG T OT 62 Figure 4 15 The bit line just before the DTVPSYNC arrival when 8bits non rise and DTVPSYNC are 8bits non rise s est il aaa dat ela 62 Figure 4 16 Until DTVPSYNC comes to the data just after the reset invalid data Burst Serial Output 62 Figure 4 17 It was filled in 8bits just before the reset the data don t have is invalid data Burst Serial Output 63 Figure 4 18 Stream Data Storage Format sise 63 Figure 4 19 Ring Buffer Mapping ree ce lle eee e Ce RN AO aaa NANGEN agawa aces 64 Figure 4 20 Stock method of a packet at DTVMODE 0 ere 65 Figure 4 21 Packet stock method when next SyncByte has come at DITVMODE O eee eee 65 Figure 4 21 Transfer error interrupt timing x ein ree antenne e n ee RUE db a Ep a Be ne 66 Figure 4 23 At the timing of the interruption when DMA transfer is being done and transfer has been reserved to cry s 67 Figure 4 24 At the timing of the interruption when transfer has been reserved during DMA transfer 67 User s Manual 19267EJ4VOUM 9 Figure 4 25 Interrupt timing of the word transfer which includes PSYNC part time work by less than 187 bytes at DIVMODES0 3 RE aga ue et 68 Figure 4 26 Interrupt timing when also not having complete set of word data including SyncByt
20. 2 1 if ERRADR HUETE Stores the HADDR status upon occurrence of an error response Reserved R 1 o Reserved Reading returns the unsettled value Writing in is ignored LOCK R Sets error status 0 Stores the address when an error response occurs 1 An error response occurred and the address was stored W Clear error status 0 Stores the address when an next error response occurs 1 Nothing action Caution If an error response occurs when the LOCK bit is 0 the current HADDR status is stored in the ERRADR bit and the LOCK bit is set to 1 To acquire the error status again set the LOCK bit to 0 Writing 1 to the LOCK bit does not affect the setting 48 User s Manual 19267EJ4VOUM CHAPTER 4 DTV2 Details 4 3 8 Transfer control register This register DT2_DMACNT 4015_0020H controls data transfer Settings can be changed only when DMA transfer is not being performed DT2_DMAREQ register OH The DTVSP bit must be set to 1 after activation 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved DTVSP DTVMODE DTVENDIAN Reserved R 313 o Reserved Reading returns the unsettled value Writing in is ignored DTVSP R W 2 Specifies the data bus type of DTV stream 0 Burst parallel output setting prohibited 1 Burst serial output DTVMODE R W 1 1 Specifies the size of a packet 0 Transfer of synchronization f
21. 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 DTV_INTCONT Reserved R 318 o Reserved Don t write in anything but 0 It s prohibited to write in 1 DTV_ RAW 7 0 Specifies in units of packets the interval at which a DMA transfer completion INTCONT interrupt is issued An interrupt is issued every time the number of packets equal to the set value plus 1 are received Figure 3 4 DTV Interface DMA Completion Interrupt Set Timing Transfer request 1 1 1 1 1 1 I t I DTV stream data output PacketO Packet Packet2 Packet3 Packet4 A Packet 5 1 1 1 1 DMA transfer period AHB_Write DMA completion interrupt 1 1 1 1 Interrupt source clear Remark When the DMA completion interrupt setting register is set to 1H User s Manual 19267EJ4VOUM 29 CHAPTER 3 DTV Details 3 3 16 Module control register This register DT MODULECONT 4015 0040H initializes the operation of the data capturing circuit that synchronizes with DTV BCLK 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 T7 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 Reserved Reserved R ad o Reserved Don t write in anything but O It s prohibited to write in 1 HW RSTZ B HW RSTZ R W Specifies hardware reset Specifies whether to initialize the operation of the data capturing circuit that synchronizes with DTV_BCLK 0
22. 6 25 24 Reserved Reserved 15 14 13 12 11 10 9 8 Reserved 3 2 1 0 Reserved DTVSTOPCLR DTVORCLR DTVDMACLR DMAERRCLR N o al EN Reserved R aa o Reserved Don t write in anything but O It s prohibited to write in 1 DTVSTOPCL W 3 Clears the DMA stop interrupt source R 1 Clears the source W DTVORCLR 2 Clears the packet overrun error interrupt source 1 Clears the source DTVDMACLR Clears the DMA completion interrupt source 1 Clears the source DMAERRCLR Clears the transfer error interrupt source 1 Clears the source User s Manual S19267EJ4VOUM 21 CHAPTER 3 DTV Details 3 3 7 Error address register This register DT ERRORADR 4015 0014H holds the current HADDR status when an internal bus response ERROR RETRY or SPLIT is received during DMA transfer 31 30 29 28 27 26 25 24 ERRADR 23 22 21 20 19 18 17 16 ERRADR 15 14 13 12 11 10 9 8 ERRADR 7 6 5 4 3 2 1 if ERRADR eo ee Stores the HADDR status upon occurrence of an error response Reserved R 1 o Reserved Don t write in anything but 0 It s prohibited to write in 1 LOCK RAW Sets error status 0 Stores the address when an error response occurs 1 An error response occurred and the address was stored Caution If an error response occurs when the LOCK bit is 0 the current HADDR status is stored in the ERRADR bit and the LOCK bit is set to 1 To acquire the error status again set the LOCK bit to 0
23. DTVPSYNC DTVVLD Reserved R 312 o Reserved Reading returns the unsettled value Writing in is ignored DTVPSYNC R W 1 Polarity of DTVPSYNC is assigned 0 Normal 1 Reverse DTVVLD RAW Polarity of DIVVLD is assigned 0 Normal 1 Reverse User s Manual 19267EJ4VOUM 57 CHAPTER 4 DTV2 Details 4 3 18 Input pin status monitor register This register DT2 MONITOR 4015 0048H indicates terminal input status of DTVPSYNC DTVVLD DTVDATA BCLK 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 DTVDATA 2 1 Reserved DTVBCLK DTVPSYNC DTVVLD N o al A wo if Reserved R 31 16 see Reserved Reading returns the unsettled value Writing in is ignored orvoara R 158 o DTVDATA i indicated pev n rs o rend Reading reume o unsoned vane wimani roca preon n o CCT presis a 0 eres incas pre w o o posma SSCS 58 Users Manual S19267EJAVOUM CHAPTER 4 DTV2 Details 4 4 Function details 4 4 1 Input Signal Timing 1 DTV2 I F signal timing Figure 4 5 DTV2 Interface Signal Timing DTV_BCLK DTV_PSYNC DTV_VLD DTV_DATA 7 0 Tsetup Thold 2 Stream timing Figure 4 6 Stream Timing Burst Serial Output DTV_BCLK DTV_PSYNC DTV_VLD DTV DATA 7 Sync 1 byte Data 187 bytes Parity 16 bytes ere Caution Polarity
24. EQ htrans hwadd 2 b g E When DMA transfer hwdata When DMA transfer is A is stopped begun DT2 DMAREG will be 1 DT2 DMAREG Figure 4 2 Change of transfer request register value Caution At the time of a DMA transfer request a data transfer just before DMASTOP it begins from the address location When beginning DMA transfer from the start address do a DMA transfer request after H W is reset 50 Users Manual S19267EJAVOUM CHAPTER 4 DTV2 Details 4 3 10 Transfer request cancellation register This register DT2_DMASTOP 4015 0028H stops DMA transfer It ll be the stop reservation state by setting this register and when not forwarding to the occasion during packet transfer after transfer DMA is stopped immediately The DMA transfer request status can be checked by reading the transfer request register D T2 DMAREQ DMA stop interrupt is issued by the time of a fall of status the lead value of the transfer request register This is a write only register If the register is set to 1 DMA transfer is finished Writing O to this register does not affect the setting 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 DMASTOP Reserved TUR Reserved Reading returns the unsettled value Writing in is ignored 0 P DMASTOP W Stops DMA transfer 1 Transfer stop When DMA transfer is being performed the transf
25. IZE 4015 0030H specifies the size of the DMA transfer destination area in units of packets Settings can be changed only when DMA transfer is not being performed DT DMAREQ register OH 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved DTV BUFSIZE 15 14 13 12 11 10 9 8 DTV BUFSIZE 0 Reserved R 31 20 o Reserved Don t write in anything but 0 It s prohibited to write in 1 DTV_ R W 19 0 Specifies the size of the DMA transfer destination area in units of packets the BUFSIZE lower 2 bits are fixed to 0 26 User s Manual 19267EJ4VOUM CHAPTER 3 DTV Details 3 3 13 Blank size register This register DT BLANK 4015 0034H specifies the blank size between packets during DMA transfer Settings can be changed only when DMA transfer is not being performed DT DMAREQ register 0H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 0 Reserved R 318 o Reserved Don t write in anything but 0 It s prohibited to write in 1 DTV_BLANK rw 70 o Specifies the blank size between packets the lower 2 bits must be set to 0 User s Manual S19267EJ4VOUM 27 CHAPTER 3 DTV Details 3 3 14 Current packet register This register DT CURRENT 4015 0038H indicates the number of packets that have been transferred via DMA This register shows the value from 0 to DT BUFSIZE register value 1 Settings can be changed only when DMA trans
26. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry ENESAS 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted
27. Writing 1 to the LOCK bit does not affect the setting 22 User s Manual 19267EJ4VOUM CHAPTER 3 DTV Details 3 3 8 Transfer control register This register DT_DMACNT 4015 0020H controls data transfer Settings can be changed only when DMA transfer is not being performed DT DMAREQ register OH The DTVSP bit must be set to 1 after activation 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved DTVSP DTVMODE DTVENDIAN Reserved R 313 o Reserved Don t write in anything but O It s prohibited to write in 1 DTVSP R W 2 Specifies the data bus type of DTV stream 0 Burst parallel output setting prohibited 1 Burst serial output DTVMODE R W 1 1 Specifies the size of a packet 0 Transfer of synchronization field data field 188 bytes 47 words 1 Transfer of synchronization field data field parity field 204 bytes 51 words DTVENDIAN R W 1 Specifies the DTV stream data format 0 Big endian 1 Little endian User s Manual 19267EJ4VOUM 23 CHAPTER 3 DTV Details 3 3 9 Transfer request register This register DT DMAREQ 4015 0024H specifies the activation of DMA transfer 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 Reserved Reserved R sin o Reserved Don t write in anything but O It s prohibited to wri
28. ZE 0 Reserved R 31 20 o Reserved Reading returns the unsettled value Writing in is ignored DTV_ R W 19 0 Specifies the size of the DMA transfer destination area in units of packets the BUFSIZE lower 2 bits are fixed to 0 52 User s Manual 19267EJ4VOUM CHAPTER 4 DTV2 Details 4 3 13 Blank size register This register DT2 BLANK 4015 0034H specifies the blank size between packets during DMA transfer Settings can be changed only when DMA transfer is not being performed DT2_DMAREQ register 0H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 0 Reserved R 318 o Reserved Reading returns the unsettled value Writing in is ignored DTV_BLANK rw zo o Specifies the blank size between packets the lower 2 bits must be set to 0 User s Manual 19267EJ4VOUM 53 CHAPTER 4 DTV2 Details 4 3 14 Current packet register This register DT2 CURRENT 4015 0038H indicates the number of packets that have been transferred via DMA This register shows the value from 0 to DT2 BUFSIZE register value 1 Settings can be changed only when DMA transfer is not being performed DT2_DMAREQ register 0H 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved DTV CURRENT Reserved EIE NUI 31 20 E Reserved Reading returns the unsettled value Writing in is ignored 19 0 Stores the number of packets that have been transferred via DMA m
29. a is transferred to the specified buffer area in the memory in units of packets The buffer is used as a ring buffer in which the pointer returns to the beginning of the buffer after the specified number of packets are stored The following three registers are used to set up the buffer e Start address register 32 bits Specifies the ring buffer start address e Buffer size register 20 bits Specifies the ring buffer area by a packet count e Blank size register 8 bits Specifies the blanking interval between packets Figure 4 19 Ring Buffer Mapping Ring buffer area Buffer size x 1 packet size Packet 1 Packet 0 Start address Effective size of 1 packet and data is established by the DTVMODE bit of the transfer control register DT2_DMACNT by 188 bytes or 204 bytes The capacity of 1 packet unit by which the mapping is made a buffer will be the effective size chosen by the DTVMODE bit blank size The total capacity of the ring buffer will be a packet of above mentioned volume x buffer size The DTV flow received from OFDM is the part time work unit and buffering is done by FIFO inside DTV2 and every time it gathers 4 bytes DMA is forwarded to a memory figure 4 20 Data is stocked by new address aligning which made SyncByte the head as come and show in figure 4 21 at the time of the following exception occurrence at the time of SyncByte reception at the time of normal operation a When next SyncByte has
30. asking User s Manual 19267EJ4VOUM 45 CHAPTER 4 DTV2 Details 4 3 5 Interrupt enable clear register This register DT2_ENCLR 4015 000CH disables issuance of interrupt requests When the bit corresponding to an interrupt source is set to 1 in this register an interrupt request is not issued even if an interrupt source occurs The status of the corresponding bit of the interrupt status register DT2 STATUS also remains unchanged Writing O to this register does not affect the setting 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DTVLPMAS DTVSPMAS DTVSYNCM DTVSTOPMASK DTVORMASK DTVDMAMASK DMAERRMASK K K ASK Reserved R 317 o Reserved Reading returns the unsettled value Writing in is ignored DTVLPMASK Disables issuance of packet length excess interrupt requests 1 Disable DTVSPMASK DTVSYNCMA SK Disables issuance of packet length short interrupt requests 1 Disable Disables issuance of illegal SyncByte interrupt requests 1 Disable Disables issuance of packet overrun error interrupt requests DTVOR 1 Disable DTVDMA DMAERR Disables issuance of DMA completion interrupt requests 1 Disable Disables issuance of transfer error requests 1 Disable An EEE Reed DTVSTOP W 3 Disables issuance of DMA stop interrupt requests MASK 1 Disable MIE E prece MEAN 46 User s Manual 19267EJ4VOUM CHAPTER 4 DTV2 Details 4 3 6 Interrupt source c
31. assignation is possible by register setting in DTVSYNC DTVVLD 3 At the timing of a receipt of DTV2 I F signal Burst Serial Output Stream timing When DTVVLD 1 and DTVPSYNC 1 reached for 8 cycles continuously the 8bits data received at that time is made SYNC It s made DATA from 8bits following that Figure 4 7 Judgment of DTVPSYNC data Burst Serial Output DTVBCLK DTVVLD DTVPSYNC DTVDATA Serial User s Manual 19267EJ4VOUM 59 CHAPTER 4 DTV2 Details It s made SYNC continued by the 8bits unit as it indicates on figure 4 8 when DTVVLD 1 and DTVPSYNC 1 reached more than 16 cycles continuously 60 Figure 4 8 When DTVPSYNC reaches continuously Burst Serial Output DTVBCLK DTVVLD DTVPSYNC DTVDATA Serial When it was DTVVLD 0 during reception the effective Data bit is made data using 8bits except for DTVVLD 0 period figure 4 9 In case of DIVPSYNC 1 like it s made SYNC using 8bits except for DTVVLD 0 period figure 4 10 But when changing into DTVPSYNC 0 during DTVVLD 0 period it s made DATA not SYNC figure 4 11 Figure 4 9 When DTVVLD intermits Burst Serial Output DTVBCLK DTVVLD DTVPSYNC DTVDATA Serial Figure 4 10 When DTVVLD intermits while DTVPSYNC is HIGH Burst Serial Output DTVBCLK DTVVLD DTVPSYNC DTVDATA Serial User s Manual S19267EJ4VOUM CHAPTER 4 DTV2 Details Figure 4 11 When DTVPSYNC stan
32. cts or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics RENESAS User s Manual Multimedia Processor for Mobile Applications Terrestrial Digital TV Interface EMMA Mobile 1 Document No S19267EJ4VOUMOO 4th edition Date Published October 2009 NEC Electronics Corporation 2009 Printed in Japan MEMO 2 Users Manual 19267EJ4VOUM NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction If the input of the CMOS device stays in the area between Vi MAX and Vin MIN due to noise etc the device may malfunction Take care to prevent chattering noise from entering the device when the input level is fixed and also in the transition period when the input level passes through the area between Vi MAX and Vin MIN HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction If an input pin is unconnected it is possible that an internal input level may be generated due to noise etc causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using pull up or pull down
33. data area s needed beyond 5 clocks it is input 1 Before a head packet just after the DMA start DMAREQ register 2 It s needed between the packet beyond 10 clocks A clock in front of the head packet is for data fetch preparations and a clock between the packet is necessary to take it in and deliver data to a AHB clock from DTVBCLK Effective data area Do 10 clocks need When taking Parity data in Caution Head packet effective data area 5 clocks need T DTVBCLK DTVPSYNC DTVVLD DTVDATA 7 0 DMA start it s 10 clocks of need after a Parity bustle Figure 3 14 Relation between DTVBCLK and input data 37 User s Manual S19267EJ4VOUM CHAPTER 3 DTV Details 3 4 6 Return method from synchronous difference 38 1 The bit difference chosen at the timing of a start When it s piled in a H period of DTVPSYNC input between 8 clocks at the timing of a DMA start DMAREQ a bit difference occurs to bustle data When a bit difference occurs head packet data after a DMA start is forwarded by the data unit which isn t an original byte boundary To evade that head packet data after a DMA start check a Sync code and please confirm that there are no bit differences When it isn t a Sync code a bit difference occurs so please break packet data A bit difference is canceled automatically and the next packet after a while is forwarded at a normal byte boundary 2 Ret
34. ds up and goes down during a DTVVLD intermission period Burst Serial Output DTVCLK DTVVLD DTVPSYNC DTVDATA Serial Even DTVVLD 1 doesn t receive data in the period when DTVBCLK doesn t enter figure 4 12 4 13 Figure 4 12 When BCLK intermits Burst Serial Output DTVBCLK DTVVLD DTVPSYNC DTVDATA Serial Figure 4 13 When DTVPSYNC stands up and goes down during a BCLK intermission period Burst Serial Output DTVBCLK DTVVLD DTVPSYNC DTVDATA Serial The bit line was filled in 8bits when it was DTVPSYNC 1 in the state don t have it s made Data after that 8 bits in even time When DTVPSYNC continues it 8 cycles just after making the rising of DTVPSYNC a cardinal point it s made SYNC with 8bits figure 4 14 DTVPSYNC 1 was filled in 8 cycles when not having that it s made effective data just before from the bit line 8bits later figure 4 15 User s Manual 19267EJ4VOUM 61 CHAPTER 4 DTV2 Details Figure 4 14 The bit just before the DTVPSYNC arrival was filled in 8bits when don t have that Burst Serial Output DTVBCLK DTVVLD we ee Ris DTVDATA 00000500000 3 GIG 7 Serial E i Figure 4 15 The bit line just before the DTVPSYNC arrival when 8bits non rise and DTVPSYNC are 8bits non rise Burst Serial Output DTVBCLK DTVVLD DTVPSYNC b eria i i i i PSYNO less than e Data Data The bit l
35. e beyond 188byte at DIVMODE20 uno RADEON RES eie 68 Figure 4 27 Interrupt timing when PSYNC part time work is the unjust value at DTVMODE O 69 LIST OF TABLES Table No Title Page iTable 3 1 Interrupt eO ii edere Eee ate ete ER een ca ced a te 34 Table 4 1 Interr upt Sources tc e ee epe ato ER pr e picti i Ere Dette tbe a aaa n 66 10 User s Manual 19267EJ4VOUM CHAPTER 1 OVERVIEW 1 1 General The terrestrial digital television interface DTV interface has a function to transfer stream data sent from an externally connected terrestrial digital TV channel decoder LSI to memory via DMA The DTV interface only supports burst output serial mode 1 2 Features The main features of DTV are as follows The DTV interface only supports serial output O DTV interface signals e DTV_DATA 7 is used in the serial output mode e Packet synchronization pulse DTV_PSYNC e Stream data enable signal DTV_VLD e Bus clock DTV BCLK O DMA transfer destination buffer e Aring buffer area can be specified O Reception data selection e Whether to receive parity fields can be selected O Buffer memory e Abuffer memory of 32 bits x 4 words is incorporated User s Manual S19267EJ4VOUM 11 CHAPTER 1 OVERVIEW 1 3 Module Structure DTV and DTV2 EM1 has 2 of DTV macro DTV2 function module in the following DTV2 and DTV function module in the following DTV A circuit and a register of each module are se
36. e company These commodities technology or software must be exported in accordance with the export administration regulations of the exporting country Diversion contrary to the law of that country is prohibited The information in this document is current as of September 2009 The information is subject to change without notice For actual design in refer to the latest publications of NEC Electronics data sheets etc for the most up to date specifications of NEC Electronics products Not all products and or types are available in every country Please check with an NEC Electronics sales representative for availability and additional information e No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics NEC Electronics assumes no responsibility for any errors that may appear in this document e NEC Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Electronics or others e Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product
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38. e internal bus clock is controlled by each module to save power The internal bus clock is supplied upon requests from modules and upon register access In the DTV interface a clock supply request is set when a DMA transfer is requested through register access and the clock supply request is cleared when transfer of the current DMA is completed with no other transfers requested 1 Clocks used in DTV interface a DTV BCLK external input clock Used for capturing the DTV data clock and data b DTV CLK DTV internal clock Used for the AHB bus clock and the internal operation of the DTV interface c DTV_PCLK APB clock Used for the accessing the APB bus registers For details about clock reset settings see the Multimedia Processor for Mobile Applications System Control General Purpose I O Interface User s Manual S19265E 2 DTV CLKREQ set timing When the DTV transfer request register is set 3 DTV_CLKREQ clear timing When the DTV transfer request cancellation register is set and DMA transfer of the current packet is completed 4 DTV SWT CLKREOQ output timing The signal 1CLK preceded to transaction is output as CLKREQ for bus switches Signal rising is 1CLK precedence of transaction and a fall is at the timing of an end of the data phase User s Manual 19267EJ4VOUM 69 70 Revision History Date Revision Comments February 10 2009 1 0 April 27 2009 2 0 Incremental update from comments
39. eing performed the transfer stops after sending the current packet Otherwise the transfer immediately stops Caution1 That one for 10 cycles of DTVBCLK leave a space by the transfer request register set which resumes DMA after DMA stop interruption Caution2 By DMA stop request fixation time the effective data length that even packet data is forwarded to a memory The data of the buffering way don t have filled in the effective data length is broken Figure 3 2 DMA Stop Timing Transfer Transfer request request i i 1 1 1 1 1 1 1 1 1 1 1 1 1 L 1 1 1 1 1 1 1 1 1 1 1 1 1 DTV stream data output amp Packeto_ X Packet1_ Packt2 Packet 1 1 ta 1 DMA transfer period TA NX L d AHB Write E ii mr i 14 1 DMA status ae M i e 1 1 va 1 1 1 1 ba 1 DMA stop request T T User s Manual 19267EJ4VOUM 25 CHAPTER 3 DTV Details 3 3 11 Start address register This register DT START 4015 002CH specifies the start address of the DMA transfer destination Settings can be changed only when DMA transfer is not being performed DT DMAREQ register 0H 31 30 29 28 27 26 25 24 DTV START 23 22 21 20 19 18 17 16 DTV START 15 14 13 12 11 10 9 8 DTV START 7 6 5 4 3 2 1 0 DTV START R W 31 0 Specifies the start address of the DMA transfer destination the lower 2 bits are fixed to 0 3 3 12 Buffer size register This register DT BUFS
40. equests When the bit corresponding to an interrupt source is set to 1 in this register if the interrupt source is set an interrupt request is issued and the corresponding bit of the interrupt status register DT STATUS is set to 1 Writing O to this register does not affect the setting The interrupt request issuance enable status can be checked by reading this register 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved DTVSTOP_EN DTVOR_EN DTVDMA_EN DMAERR_EN mem E ET Reserved Don t write in anything but O It s prohibited to write in 1 DTVSTOP_ Indicates whether issuance of DMA stop interrupt requests is enabled EN 0 Not enabled 1 Enabled Specifies whether to enable issuance of DMA stop interrupt requests 1 Cancels interrupt masking DTVOR_EN Indicates whether issuance of packet overrun error interrupt requests is enabled 0 Not enabled 1 Enabled Specifies whether to enable issuance packet overrun error interrupt requests 1 Cancels interrupt masking DTVDMA_EN Indicates whether issuance of DMA completion interrupt requests is enabled 0 Not enabled 1 Enabled Specifies whether to enable issuance of DMA completion interrupt requests 1 Cancels interrupt masking DMAERR_EN Indicates whether issuance of transfer error interrupt requests is enabled 0 Not enabled 1 Enabled Specifies whether to enable issua
41. er stops after sending the current packet Otherwise the transfer immediately stops Caution1 The restriction matter in DTV One for 10 cycles of DTVBCLK leave a space by the transfer request register set which resumes DMA after DMA stop interruption please is unnecessary in DTV2 Caution2 Word data until DMA stop request fixation time is forwarded to a memory Transfer data was filled in the effective data length of 1 packet 188byte or 204byte when not having that even a packet next to the stop request fixation after a while will be unsettled data User s Manual 19267EJ4VOUM 51 CHAPTER 4 DTV2 Details 4 3 11 Start address register This register DT2 START 4015 002CH specifies the start address of the DMA transfer destination Settings can be changed only when DMA transfer is not being performed DT2 DMAREQ register 0H 31 30 29 28 27 26 25 24 DTV START 23 22 21 20 19 18 17 16 DTV START 15 14 13 12 11 10 9 8 DTV START 7 6 5 4 3 2 1 0 DTV START R W 31 0 Specifies the start address of the DMA transfer destination the lower 2 bits are fixed to 0 4 3 12 Buffer size register This register DT2 BUFSIZE 4015 0030H specifies the size of the DMA transfer destination area in units of packets Settings can be changed only when DMA transfer is not being performed DT2_DMAREQ register 0H 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved DTV BUFSIZE 15 14 13 12 11 10 9 8 DTV BUFSI
42. erface DMA Completion Interrupt Set Timing Transfer request 1 1 1 1 DTV stream data output amp Packeto X Packet A Packet2 X Packets X Packet4 X Packet 5 1 1 1 1 1 1 1 DMA transfer period L d L AHB Write 1 1 1 1 1 1 1 1 DMA completion interrupt 4 i i 1 1 1 1 1 1 1 1 Interrupt source clear Remark When the DMA completion interrupt setting register is set to 1H User s Manual 19267EJ4VOUM 55 CHAPTER 4 DTV2 Details 4 3 16 Module control register This register DT2 MODULECONT 4015 0040H initializes the operation of the data capturing circuit that synchronizes with DTV_BCLK 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 T7 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 Reserved Reserved R ait o Reserved Reading returns the unsettled value Writing in is ignored HW RSTZ B HW RSTZ R W Specifies hardware reset Specifies whether to initialize the operation of the data capturing circuit that synchronizes with DTV_BCLK 0 Reset 1 Cancels reset 56 User s Manual 19267EJ4VOUM CHAPTER 4 DTV2 Details 4 3 17 DTVPSYNC DTVVLD Polarity designation register This register DT2_SIGNALINVERT 4015_0044H assign polarity of used DTVPSYNC and DTVVLD respectively 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 P Reserved
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44. fer is not being performed DT DMAREQ register 0H 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved DTV CURRENT 15 14 13 12 11 10 9 8 DTV CURRENT DTV CURRENT Reserved EIE le 31 20 a a S Reserved Don t write in anything but 0 It s prohibited to write in 1 y o al IN w D E o 19 0 Stores the number of packets that have been transferred via DMA minus 1 CURRENT Figure 3 2 Current Packet Register Values Transfer request 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LI 1 1 1 1 1 1 1 1 1 1 1 DTV stream data output Packet 0 Packet 1 Packet 2 Packet 3 Packet 4 Packet 5 DMA transfer period i i i l i i i AHB di 1 1 1 1 o c 5 3 o 3 D D Q o Remark When the DTV buffer size is set to 4H Caution Only while the count value is DT_DMAREQ 1 the count value is effective While it s DT_DMAREQ 0 it ll be 0 28 User s Manual 19267EJ4VOUM CHAPTER 3 DTV Details 3 3 15 DMA completion interrupt setting register This register DT_INTCONT 4015 003CH specifies the interval at which a DMA transfer completion interrupt is issued in units of packets A DMA transfer completion interrupt is issued each time DMA transfer of DT_INTCONT register value 1 packets is completed Settings can be changed only when DMA transfer is not being performed DT DMAREQ register OH 31 30 29 28 27 26 25 24 Reserved 23 22
45. fer overruns Bit 2 Bt2 DTVOR DMA completion Issued when the specified number of packets have been transferred Bit 1 DTVDMA interrupt Transfer error interrupt Issued when the ERROR response is received during internal bus Bit 0 DMAERR transfer 1 Transfer error interrupt When a ERROR reply is received during Internal bus transfer interrupt is generated DTVCLK hready htrans SW ee hwaddr O hwdata CT 7 CE 7 2103 hresp OC E XK CIR DTV_INT Figure 3 9 Transfer error interrupt timing 2 DMA completion interrupt Trabsfer A Reguest E V d PacketO DTV Stream Data output DMA Transfer time AHB_Write DTV DMA Transfer Completion Interrupt Factor Clear When DTV DMA completion interrupt setting register is Oxl Figure 3 10 DMA completion interrupt Timing 34 User s Manual 19267EJ4VOUM CHAPTER 3 DTV Details 3 Packet overrun interrupt The DTV interface uses internal memory 32 bits x 128 words as a buffer having two banks Banks are switched for each packet for buffering and the data in the filled bank is transferred to the memory via DMA In stream data transfer via the DTV interface the case where the DMA transfer of the previous packet data is not completed within the period in which a packet is loaded is defined as a packet overrun If a packet overrun occurs the corresponding bit of the interrupt source register is immediately set lf a
46. he specified buffer area in the memory in units of packets The buffer is used as a ring buffer in which the pointer returns to the beginning of the buffer after the specified number of packets are stored The following three registers are used to set up the buffer e Start address register 32 bits Specifies the ring buffer start address e Buffer size register 20 bits Specifies the ring buffer area by a packet count e Blank size register 8 bits Specifies the blanking interval between packets Figure 3 8 Ring Buffer Mapping Ring buffer area Buffer size x 1 packet size Packet 1 1 Blank size Packet 0 Start address The valid size of a packet can be set to 188 or 204 bytes by using the DTVMODE bit of the transfer control register DT DMACNT The size of a packet to be mapped to a buffer is the valid size selected by the DTVMODE bit plus the blank size The total ring buffer size is the above packet size multiplied by the buffer size User s Manual 19267EJ4VOUM 33 CHAPTER 3 DTV Details 3 4 4 Interrupt Control The DTV interface uses four interrupts The bits of the interrupt status register DT STATUS are used to control the interrupts For details see Table 3 1 Table 3 1 Interrupt Sources Interrupt Type When to Issue Bit Assignment DMA aa interrupt Issued when the DMA transfer Po Y ET 3 DTVSTOP Packet overrun overrun Issued when the internal buffer overruns when the internal buf
47. hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document but Ren
48. ield data field 188 bytes 47 words 1 Transfer of synchronization field data field parity field 204 bytes 51 words DTVENDIAN R W 1 Specifies the DTV stream data format 0 Big endian 1 Little endian User s Manual 19267EJ4VOUM 49 CHAPTER 4 DTV2 Details 4 3 9 Transfer request register This register DT2 DMAREQ 4015 0024H specifies the activation of DMA transfer After setting 1 in this register the lead value of this register is O until DMA transfer begins it When DMA transfer begins it the lead value changes into 1 1 is set by a transfer release request cashier and when DMA transfer stops the lead value of this register changes into 0 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 i Reserved DMAREQ Reserved R sin o Reserved Reading returns the unsettled value Writing in is ignored DMAREQ This bit is set to 1 when DMAREQ is acknowledged This bit is cleared when the transfer request cancellation register 4015 0028H is set W Writing 1 to this bit issues a DMA transfer request DMA is repeated until the transfer request cancellation register 4015 0028H is set Writing O to this bit does not affect the setting Transfer clear request 1 is written in transfer request DT2 DMASTOP Transfer request 1 is written in transfer request DT2 DMAREQ Register Write DT_M2H_DMAR
49. ine received just after just after the start and the reset will be an invalid bit and it s made the effective bit from first DTVPSYNC figure 4 16 It was filled in 8bits which has been received at the end in a case with a reset when receiving an effective bit the data don t have is made invalid data figure 4 17 Figure 4 16 Until DTVPSYNC comes to the data just after the reset invalid data Burst Serial Output DTVBCLK SRSTZ DTVVLD DTVPSYNC DTVDATA Serial Invalid data Valid data 62 User s Manual 19267EJ4VOUM CHAPTER 4 DTV2 Details Figure 4 17 It was filled in 8bits just before the reset the data don t have is invalid data Burst Serial Output DTVBCLK SRSTZ DTVVLD DTVPSYNC DTVDATA Serail Invalid data Invalid data Valid data 4 4 2 Data Format Figure 4 18 Stream Data Storage Format DTV_PSYNC DTV_VLD E lt y ES Re UE DTV DATA 7 0 Sync Data 187 bytes Parity 16 bytes 1 byte Data input as shown in Figure 4 18 is stored in the memory in the following format in accordance with the value set to the DTVENDIAN bit of the transfer control register DT2 DMACNT Bit alignment 31to24 23t016 15108 7100 311024 231016 15108 7100 3 words 2 words 1 word 0 words Little endian Big endian User s Manual 19267EJ4VOUM 63 CHAPTER 4 DTV2 Details 4 4 3 DTV Transfer Processing Stream dat
50. interrupt requests 1 Cancels interrupt masking DTVSP_EN Indicates whether issuance of packet length short interrupt request is enabled 0 Not enabled 1 Enabled Specifies whether to enable issuance of packet length short interrupt requests 1 Cancels interrupt masking Indicates whether issuance of illegal SyncByte interrupt request is enabled 0 Not enabled 1 Enabled Specifies whether to enable issuance of illegal SyncByte interrupt requests 1 Cancels interrupt masking Indicates whether issuance of DMA stop interrupt requests is enabled 0 Not enabled DTVSYNC E N DTVSTOP EN DTVOR EN 44 Users Manual 19267EJ4VOUM 1 Enabled Specifies whether to enable issuance of DMA stop interrupt requests 1 Cancels interrupt masking Indicates whether issuance of packet overrun error interrupt requests is enabled 0 Not enabled 1 Enabled Specifies whether to enable issuance packet overrun error interrupt requests 1 Cancels interrupt masking CHAPTER 4 DTV2 Details 2 2 DTVDMA_EN 1 Indicates whether issuance of DMA completion interrupt requests is enabled 0 Not enabled 1 Enabled W Specifies whether to enable issuance of DMA completion interrupt requests 1 Cancels interrupt masking DMAERR_EN Indicates whether issuance of transfer error interrupt requests is enabled 0 Not enabled 1 Enabled W Specifies whether to enable issuance of transfer error interrupt requests 1 Cancels interrupt m
51. inus 1 CURRENT Figure 4 3 Current Packet Register Values Transfer request 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DTV stream data output amp PacketO Packet Packet2 Packet3 Packet4 Packet5 DMA transfer period XA AW ING ING i AHB_Write 0 0 0 D 1 1 1 1 1 1 1 Current packet 0 X 1 X 2 X 3 X 0 Remark When the DTV buffer size is set to 4H Caution The count value is maintained until H W resets 54 User s Manual 19267EJ4VOUM CHAPTER 4 DTV2 Details 4 3 15 DMA completion interrupt setting register This register DT2_INTCONT 4015_003CH specifies the interval at which a DMA transfer completion interrupt is issued in units of packets A DMA transfer completion interrupt is issued each time DMA transfer of DT2_INTCONT register value 1 packets is completed Settings can be changed only when DMA transfer is not being performed DT2_DMAREQ register OH 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 DTV_INTCONT Reserved R mal o Reserved Reading returns the unsettled value Writing in is ignored DTV_ RAW 7 0 Specifies in units of packets the interval at which a DMA transfer completion INTCONT interrupt is issued An interrupt is issued every time the number of packets equal to the set value plus 1 are received Figure 4 4 DTV Int
52. ipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain us
53. lear register This write only register DT2_FFCLR 4015_0010H clears the interrupt source by setting the bit corresponding to the interrupt source to 1 Writing O to this register does not affect the setting 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 DTVLPCLR DTVSPCLR DTVSYNCC DTVSTOPCLR DTVORCLR DTVDMACLR DMAERRCLR LR Reserved R 37 o Reserved Reading returns the unsettled value Writing in is ignored DTVLPCLR W Clears the packet length excess interrupt source 1 Clears the source DTVSPCLR 5 Clears the packet length short interrupt source 1 Clears the source DTVSYNCCL Clears the illegal SyncByte interrupt source 1 Clears the source DTVSTOPCL Clears the DMA stop interrupt source 1 Clears the source Ps m 2 Clears the packet overrun error interrupt source 1 Clears the source pes DTVORCLR DTVDMACLR Clears the DMA completion interrupt source 1 Clears the source DMAERRCLR Clears the transfer error interrupt source 1 Clears the source User s Manual S19267EJ4VOUM 47 CHAPTER 4 DTV2 Details 4 3 7 Error address register This register DT2_ERRORADR 4015_0014H holds the current HADDR status when an internal bus response ERROR RETRY or SPLIT is received during DMA transfer 31 30 29 28 27 26 25 24 ERRADR 23 22 21 20 19 18 17 16 ERRADR 15 14 13 12 11 10 9 8 ERRADR 7 6 5 4 3
54. low Customers must check the quality grade of each NEC Electronics product before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems and medical equipment for life support etc The quality grade of NEC Electronics products is Standard unless otherwise expressly specified in NEC Electronics data sheets or data books etc If customers wish to use NEC Electronics products in applications not intended by NEC Electronics they must contact an NEC Electronics sales representative in advance to determine NEC Electronics willingness to support a given application Note 1 NEC Electronics as used in this statement means NEC Electronics Corporation and also includes its majority owned subsidiaries 2 NEC Electronics products means any product developed or manufactured by or for NEC Electronics as defined above M8E0904E 4 User s Manual 19267EJ4VOUM Readers Purpose Organizatio
55. n How to Read This Manual Conventions PREFACE This manual is intended for hardware software application system designers who wish to understand and use the terrestrial digital TV interface functions of EMMA Mobile EM1 a multimedia processor for mobile applications This manual is intended to explain to users the hardware and software functions of the terrestrial digital TV interface of EM1 and be used as a reference material for developing hardware and software for systems that use EM1 This manual consists of the following chapters e Chapter 1 Overview e Chapter 2 Pin functions e Chapter 3 DTV details e Chapter 4 DTV2 datails It is assumed that the readers of this manual have general knowledge of electricity logic circuits and microcontrollers To understand the functions of the terrestrial digital TV interface of EM1 in detail Read this manual according to the CONTENTS To understand the other functions of EM1 Refer to the user s manual of the respective module To understand the electrical specifications of EM1 Refer to the Data Sheet Data significance Higher digits on the left and lower digits on the right Note Footnote for item marked with Note in the text Caution Information requiring particular attention Remark Supplementary information Numeric representation Binary xxxx or xxxxB Decimal xxxx Hexadecimal xxxxH Data type Word 32 bits Halfword 16 bits Byte 8
56. n a packet overrun occurred the adjustment lessness occurs to the packet data input from DTV and the range stocked in a ring buffer but after return a normal packet bustle is resumed from next Psync from a packet overrun 66 User s Manual 19267EJ4VOUM CHAPTER 4 DTV2 Details 4 DMA stop interrupt When doing DMA transfer of DMA immediately when not forwarding when DMA transfer stop reservation was formed out of register DT2_DMASTOP when the transfer has been completed interrupt is generated Figure 4 23 At the timing of the interruption when DMA transfer is being done and transfer has been reserved to cry DTVCLK dma_stop i E E E E F i i B B htrans UP MVT El APA NEU NEU EUN hwaddr l al 01 S hwdata JC 100 X A O OO i al 01 j hresp Co MOR SS OK DTV INT i05 b ee 1 34 TAA Figure 4 24 At the timing of the interruption when transfer has been reserved during DMA transfer DTVCLK dma stop htrans AE 2 User s Manual 19267EJ4VOUM 67 CHAPTER 4 DTV2 Details 5 Packet length short interrupt When next SyncByte has arrived in less than 203 bytes of state at less than 187 bytes and packet chief effective size 204byte at packet chief effective size 188byte the forwarded data length generates interrupt Effective size is established by the DTVMODE bit of the transfer control register Figure 4 25 Interrupt timing of the word
57. nce of transfer error interrupt requests 1 Cancels interrupt masking Users Manual 19267EJ4VOUM 19 CHAPTER 3 DTV Details 3 3 5 Interrupt enable clear register This register DT_ENCLR 4015 000CH disables issuance of interrupt requests When the bit corresponding to an interrupt source is set to 1 in this register an interrupt request is not issued even if an interrupt source occurs The status of the corresponding bit of the interrupt status register DT STATUS also remains unchanged Writing O to this register does not affect the setting 31 30 29 28 27 26 25 24 Reserved Reserved 15 14 13 12 11 10 9 8 Reserved 3 2 1 0 Reserved DTVSTOPMASK DTVORMASK DTVDMAMASK DMAERRMASK Reserved R 314 o Reserved Don t write in anything but 0 It s prohibited to write in 1 DTVSTOP W 3 Disables issuance of DMA stop interrupt requests MASK 1 Disable Si o al A DTVOR W 2 Disables issuance of packet overrun error interrupt requests MASK 1 Disable DTVDMA W 1 Disables issuance of DMA completion interrupt requests MASK 1 Disable DMAERR W Disables issuance of transfer error requests MASK 1 Disable 20 User s Manual 19267EJ4VOUM CHAPTER 3 DTV Details 3 3 6 Interrupt source clear register This write only register DT_FFCLR 4015 0010H clears the interrupt source by setting the bit corresponding to the interrupt source to 1 Writing O to this register does not affect the setting 31 30 29 28 27 2
58. parate perfectly The register address is common A mutual function module is sharing OFDM interface and AHB bus interface The main features of DTV are as follows Exclusion moves by setting of DTV DTV2 change register SWITCH for each module When 1 is set as DT SWITCH DTV2 is chosen and when 0 is established DTV is chosen Defaults are DT SWITCH 0 and DTV will be in the chosen state Crocus DTV DTVDATA 7 0 DTVPSYNC DTVDATA 7 0 DTVVLD CI gory Baix ODTVPSYNC Y ese System Bus DTV2 DTVDATA 7 0 DTVPSYNC A Pa id PLAN lock M HB PB M DTV_BCLK 4 Reset Figure 1 1 Block diagram 1 4 Clock Supply All clocks are supplied only the function module chosen by DTV DTV2 change register DT SWITCH with It isn t supplied non selection function module with 1 5 Reset Reset release All resets are reflected by only the function module chosen by DTV DTV2 change register DT SWITCH Non choice module will be always in the reset state Next to DTV DTV2 change register DT_SWITCH 0 and DTV become effective just after the hardware reset After reset release it s necessary to establish DTV DTV2 change register DT SWITCH 1 to make DTV2 effective 1 6 Atthe timing of DTV DTV2 change When changing DTV DTV2 be sure to change by the following procedure 1 H W reset 2 H W reset release 3 DT SWITCH setting 12 Users Manual 19267EJ4VOUM CHAPTER 2 PIN FUNCTIONS 2
59. s Do not access reserved registers Any value written to reserved bits in each register is ignored Base address 4015_0000H Register Name Register Symbol After Reset 0020H DTV DTV2 change register DT_SWITCH 0000_0000H DTV DTV2 change register DT_SWITCH 1 can use following register 4015_0000H to 4015_0040H overlaps DTV2 but at DT_SWITCH 1 register operation is reflected by only a DTV2 register Base address 4015_0000H Ctro rr CT n oo ot morceau sas regse ore mawstarus m lma ow Gurentpierepe C comment n Jooo ooon hos ia ss momor regse orevouron n om 40 User s Manual 19267EJ4VOUM CHAPTER 4 DTV2 Details 4 3 Register Functions 4 3 1 DTV DTV2 change register This register DT_SWITCH 4015_0200H changes DTV and DTV2 exclusively 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 Reserved Reserved R a o Reserved Reading returns the unsettled value Writing in is ignored SWITCH SWITCH R W DTV DTV2 change 0 DTV 1 DTV2 User s Manual S19267EJ4VOUM 41 CHAPTER 4 DTV2 Details 4 3 2 Interface status register This read only register DT2 STATUS 4015 0000H can be used to read the status of the interrupt sources enabled by the interrupt enable set register DT ENSET 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 1
60. tatus register Please refer to table 4 1 for details Table 4 1 Interrupt Sources Interrupt Type When to Issue Bit Assignment Packet length excess interrupt Issued when 1 packet exceeded 188byte or 204byte DT2 STATUS 6 DTVLP Packet length short interrupt Issued when DTVPSYNC 1 and reception data are less DT2_STATUS 5 DTVSP daa ieee ee Illegal SyncByte onyerrupt Issued when the price of DIVPSYNC 1 and SyncByte DT2 STATUS 4 DTVSYNC is 47H or anything but B8H DMA stop interrupt Issued when the DMA transfer stops DT2 STATUS 3 DIVSTOP Packet overrun Issued when the internal buffer overruns DT2 STATUS 2 DTVOR DMA completion Issued when the specified number of packets have DT2 STATUS 1 DIVDMA interrupt been transferred Transfer error interrupt Issued when the ERROR response is received during DT2 STATUS 0 DMAERR internal bus transfer 1 Transfer error interrupt When a ERROR reply is received during Internal bus transfer interrupt is generated DTVCLK bur PIE Pob Pd aaa an aan r ar Figure 4 21 Transfer error interrupt timing 2 DMA completion interrupt Every time DMA of the number of packets set as register DT2_INTCONT is completed interrupt is generated 3 Packet overrun interrupt DTV2 I F uses the inner memory 32 bits x 128 words as a buffer A bustle of a word does DMA transfer of completed data When the interior buffer overflows overrun interrupt is generated Whe
61. te in 1 DMAREQ i DMAREQ This bit is set to 1 when DMAREQ is acknowledged This bit is cleared when the transfer request cancellation register 4015 0028H is set W Writing 1 to this bit issues a DMA transfer request DMA is repeated until the transfer request cancellation register 4015_0028H is set Writing 0 to this bit does not affect the setting Caution Data transfer is begun from the start address at the time of a DMA transfer request 24 Users Manual 19267EJ4VOUM CHAPTER 3 DTV Details 3 3 10 Transfer request cancellation register This register DT DMASTOP 4015 0028H stops DMA transfer It ll be the stop reservation state by setting this register and when not forwarding to the occasion during packet transfer after transfer DMA is stopped immediately The DMA transfer request status can be checked by reading the transfer request register DT DMAREQ DMA stop interrupt is issued by the time of a fall of status the lead value of the transfer request register This is a write only register If the register is set to 1 DMA transfer is finished Writing O to this register does not affect the setting 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 L DMASTOP Reserved TUR Reserved Don t write in anything but O It s prohibited to write in 1 0 DMASTOP W Stops DMA transfer 1 Transfer stop When DMA transfer is b
62. timing sise 34 Figure 3 10 DMA completion interrupt Timing sss sese sees eee eee sise 34 Figure 3 1 1 DMA stop interrupt Timing itte e HERR EC ERR RECHRME nant et At aapea paisan Er esei anr az 35 Figure 3 12 DMA SWT CLKREQ Timing cine rete Det Me ce rm Ne emm dede M eed dtd 36 Figure 3 13 Frequency conversion of DTV CLK and DT VBCLK ie 37 Figure 3 14 Relation between DTVBCLK and input data ii 37 Figure 4 1 DTV Sere diagram uei deter tm oi Fete nere trae e nice Ee lire aps 39 Figure 4 2 Change of transfer request register value 50 Figure 4 3 Current Packet Register Values sisi 54 Figure 4 4 DTV Interface DMA Completion Interrupt Set Timing sese sees eee ee eee eee eee eee 55 Figure 4 5 DTV2 Interface Signal Timing ss 59 Figure 4 6 Stream Timing Burst Serial Output sise 59 Figure 4 7 Judgment of DTVPSYNC data Burst Serial Output 59 Figure 4 8 When DTVPSYNC reaches continuously Burst Serial Output 60 Figure 4 9 When DTVVLD intermits Burst Serial Output is 60 Figure 4 10 When DTVVLD intermits while DTVPSYNC is HIGH Burst Serial Output 60 Figure 4 11 When DTVPSYNC stands up and goes down during a DTVVLD intermission period Burst Serial Quip lt 2 teehee AA E eO e EHE OSEE eed 61 Figure 4 12 When BCLK intermits Burst Serial Output enne 61 Figure 4 13 When DTVPSYNC stands up and goes down during a BCLK intermission period Burst Serial Output 6
63. transfer which includes PSYNC part time work by less than 187 bytes at DTVMODE 0 DTVCLK hready htrans hwaddr hwdata DTV_INT 6 Packet length excess interrupt When a packet chief closes beyond effective size 188byte or 204byte interrupt is generated Effective size is designated by the DTVMODE bit of the transfer control register Figure 4 26 Interrupt timing when also not having complete set of word data including SyncByte beyond 188byte at DTVMODE 0 DTVCLK hready i i id TC i E DMA transmission m 188 SU has htrans Wu pe z E but the next data in FIFO doesn t hwaddr E include hwdata DTV INT 68 User s Manual 19267EJ4VOUM CHAPTER 4 DTV2 Details 6 Illegal SyncByte interrupt SyncByte shows 47H or B8H The time 47H the price is decided about by DTVMODE of a transfer control register and which is DIVMODE O0 the B8H is made the expectation value at DTVMODE 1 In case of all except for the expectation value SyncByte of DMA transfer word data including SyncByte brings about unjust SyncByte interrupt Figure 4 27 Interrupt timing when PSYNC part time work is the unjust value at DTVMODE 0 The value which is a word It s a word including SyncByte DTVCLK including but the price of the relevant SyncByte and a relevant byte byte isn t 47H SWTDTV i E EE htrans hwaddr hwdata DTV INT 4 4 5 Clocks Control In EM1 supply of th
64. urn from a synchronous difference by prescritive outside input When the case when a clock DTVBCLK isn t supplied right and at the timing of prescribed input did and were different input such as noise occurred to a clock a same year can t slip and sometimes forward data right It s possible to make them return from a synchronous difference by the next processing Further the data maintained in the circuit is broken 1 Head 1byte data of packet data is checked and a synchronous difference is judged 2 DMA transfer stop DMASTOP register 3 The DMA stop interruption is confirmed 4 The DTV I F is reset in HW of a MODULECONT register RSTZ note b The reset release which is the DTV I F in HW of a MODULECONT register RSTZ 6 Restart of DMA transfer DMAREQ register Note For HW RSTZ to initialize only DTV IF part the circuit which moves in DTVBCLK register setting is maintained Register s readjustment isn t necessary User s Manual S19267EJ4VOUM 4 1 Function Block Diagram o 3 a E g D 2 a DTV_DMA Frame Buffer Interface Processor K Interface CHAPTER 4 DTV2 Details Data Buffer CTI CTI OI DTVIF Internal All Unit gt Serial Parallel IF T Packet Control Stream Interface Figure 4 1 DTV Block diagram User s Manual S19267EJ4VOUM DTVDATA 7 0 9 DTVPSYNC DTV BCLK 39 CHAPTER 4 DTV2 Details 4 2 Register

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