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ST62T32B/ST62E32B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

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1. DATA ROM EPROM DEDICATIONS ACCUMULATOR RESULTS TO DATA SPACE WRITE LINE VR01811 4 CPU REGISTERS Cont d However if the program space contains more than 4096 bytes the additional memory in program space can be addressed by using the Program Bank Switch register The PC value is incremented after reading the ad dress of the current instruction To execute relative jumps the PC and the offset are shifted through the ALU where they are added the result is then shifted back into the PC The program counter can be changed in the following ways JP Jump instructionPC Jump address CALL instructionPC Call address Relative Branch Instruction PC offset Interrupt PC Interrupt vector Reset PC Reset vector RET amp RETI instructionsPC Pop stack Normal instructionPC PC 1 Flags C Z The ST6 CPU includes three pairs of flags Carry and Zero each pair being associated with one of the three normal modes of operation Normal mode Interrupt mode and Non Maskable Interrupt mode Each pair consists of a CARRY flag and a ZERO flag One pair CN ZN is used during Normal operation another pair is used dur ing Interrupt mode ZI and a third pairs used in the Non Maskable Interrupt mode CNMI ZN MI The ST6 CPU uses the pair of flags associated with the current mode as soon as an interrupt or a Non Maskable Interrupt is generated the ST6 CPU uses the I
2. RUNRES OVFIEN OVFFLG OVFMD Bits 7 amp 6 PSC2 PSC1 Clock Prescaler These bits define the prescaler options for the prescaler to the Counter Register according to the following table Clock Disabled prescaler and counter stopped 0 1 Prescale by 1 1 0 Prescale by 4 The Prescaler must be disabled PSC2 0 PSC1 0 before a new prescaler factor is set if the counter is running after a hardware reset the prescaler is automatically disabled To avoid inconsistencies in timing the prescaler factor should be set first and then the counter started Bit 5 RELOAD Reload enabled When set bit enables reload from RLCP register reg ister On the contrary if RELOAD is cleared RLCP is used as target for capture from the coun ter CT register Bit 4 RUNRES Run Reset This bit enables the RUN or RESET operation ofthe AR TIMER If 0 the counter CT is cleared to zero and is stopped Setting this bit to 1 permits the startup of the counter and enables the synchronisation cir cuits for the timer inputs CP1 and CP2 Bit 3 OVFIEN Overflow Int Enable The Over flow Interrupt is masked when this bit is 0 Setting the bit to 1 enables the overflow flag to set the ARTIMER interrupt Bit 2 OVFFLG When this bit is 0 no overflow has occurred since the last clear of this bit If the bit is at 1 an overflow has occurred This bit cannot be set by program only c
3. GALA ENG UR SR ete 65 5 1 ST6 ARCHITECTURE 65 5 2 ADDRESSING MODES isse ONE 65 5 3 INSTRUCTION SET sa Gate y ny aee Rd RC d 66 6 ELECTRICAL 5 71 6 1 ABSOLUTE MAXIMUM 5 71 6 2 RECOMMENDED OPERATING 5 72 6 3 DC ELECTRICAL CHARACTERISTICS 73 6 4 AC ELECTRICAL CHARACTERISTICS 74 6 5 A D CONVERTER 5 5 74 6 6 TIMER 5 75 6 7 SPI CHARACTERISTICS bh dA aa ee ex h dee eee me ead 75 6 8 ARTIMER16 ELECTRICAL 5 75 3 86 Table of Contents Document Page 7 GENERAL 76 7 1 PACKAGE MECHANICAL 76 7 2 ORDERING INFORMATION 78 STO2P32B acer as dre Mees ea ak 79 1 GENERAL DESCRIPTION
4. 2 most 0007h significant 1 is bit 2 0003 amp 000C 0000h 0003 amp 0007 0003 000 Pitan most 0003h significant 1 is bit 1 2 bs most 0001h ANNA N significant 1 is bit O CMP 000Fh 49 86 ST62T32B ST62E32B 4 3 3 TIMINGS MEASUREMENT MODES These modes are based on the capture of the down counter content into either CP or RLCP reg isters Some are used in conjunction with a syn chronisation of the down counter by reload func tions on external event on CPi pins or software RUNRES setting while other modes do not affect the downcounting As long as RELOAD bit is cleared the down counter remains in free running mode RELOAD 7 Reload on CP1 CP2 RUNRES Capture CP2 0 Capture CP1 Capture CP2 4 3 3 1 Timing measurement with startup control Three startup conditions selected by RLDSELi bit can reload the counter from RLCP and initiate the down counting when RELOAD bit is set The first mode is software controlled through the RUNRES bit while the two others are based on external event on pins CP1 and CP2 with configurable polarities External event on CP2 pin with configurable po larities is used as strobe to launch the capture of the CT counter into CP When RELOAD bit is set RLCP cannot be used for capture since it contains the reload value Finally 3 different Reload Capture sequences are available
5. eben ten ee a Se ee nc t e i ge a 44 4 2 3 Application Notes i d UA ERR AY 45 4 2 4 Timer Registers 45 4 3 ARTIMER 16 gt GOES ROO ORO drei Ret a ee a 46 4 3 1 CENTRAL COUNTER 47 4 3 2 SIGNAL GENERATION 48 4 3 8 TIMINGS MEASUREMENT 8 2222 50 4 3 4 INTERRUPT CAPABILITIES Ree m 52 4 3 5 CONTROL REGISTERS 7 messen 53 4 3 6 16 REGISTERS 55 44 A D CONVERTER ADC 0 M elu 57 4 4 1 Application Notes 4 57 4 5 U A R T UNIVERSAL ASYNGHRONOUS RECEIVER TRANSMITTER 59 4 5 1 PORTS INTERFACING eee 59 4 5 2 CLOCK 60 4 5 3 DATA 60 4 5 4 DATA 61 4 5 5 5 61 4 5 6 REGISTERS osse oos teeta ade 61 46 SERIAL PERIPHERAL INTERFACE SPI 63 5 SOFIWAHE och nec ve cee xm
6. September 1998 1 86 Table of Contents Document Page STI621392B S1T62E32B 1 x RR ERR ERE RR A RU 1 1 GENERAL DESCRIPTION oie ects eect rr RR Rf xm 5 Tl INTRODUC TION 5 1 2 PIN DESCRIPTIONS oe rm beled neal deem dala iad eee ee ara 7 1 9 MEMORY cue Hawes Peta pede ee 8 1 8 4 Introduction eee Peri x bae de ee 8 123 2 Program Space ede dee red Ia ODER X i 8 1 3 3 Data Space cx 5 eere ene x 10 1 3 4 Stack Space ee bade gaia 10 1 3 5 Data Window Register 11 1 3 6 Data RAM EEPROM Bank Register 12 1 8 7 EEPROM Description 13 1 4 PROGRAMMING 5 15 LAA Option 1 aseo REPRE eR Rr 15 1 4 2 Program Memory 222222501544 been A RC HR OR ORCI eae d 15 1 4 3 EEPROM Data Memoty ix uide go ee 2 15 1 4 4 EPROM keel Rue dE GR Y Yd dace s 15 2 CENTRAL PROCESSING 5 16 22 INTRODUC
7. Bit 4 DOUT Data Output Data sent to the timer output when TMZ is set high output mode only Input mode selection input mode only Bit 3 PSI Prescaler Initialize Bit Used to initialize the prescaler and inhibit its count ing When 51 0 the prescaler is set to 7Fh and the counter is inhibited When PSIz 1 the prescal er is enabled to count downwards As long as PSIZ 0 both counter and prescaler not run ning Bit 2 1 0 PS2 PS1 PSO Prescaler Mux Se lect These bits select the division ratio of the pres caler register Table 16 Prescaler Division Factors Psa _PS0_ Divided by 1 Of 0 1 0 1 0 1 0 1 Timer Counter Register TCR Address OD3h Read Write 7 0 Bit 7 0 D7 DO Counter Bits Prescaler Register PSC Address 0D2h Read Write 7 0 Bit 7 D7 Always read as 0 Bit 6 0 D6 DO Prescaler Bits 45 86 ST62T32B ST62E32B 4 3 ARTIMER 16 The 16 is a timer module based on 16 bit downcounter with Reload Capture and Com pare features to manage timing requirements Two outputs provide PWM and Overflow OVF output signals each with programmable polarity and two inputs CP1 and CP2 control start up capture and or reload operations on the central counter The ARTIMER16 includes four 16 bit registers CMP RLCP MASK and CP for the Reload Cap ture and compare functions four 8 bit status
8. 80 Tat UNTRODUGTION t oxen e dur ava ies omen rdiet 80 1 2 ORDERINGEINEORMPA TION Bett ed poe dake A 80 1 2 1 Transfer of Customer Code 80 1 2 2 Listing Generation and Verification 80 SIBZS2B 525555 C Ue 83 1GENERAL DESCRIPTION 84 ka INTRODUCTION ae oe Re roba qur perd e e aa dog dbi 84 1 2 ROM READOUT PROTECTION 84 1 8 ORDERING 86 1 3 1 Transfer of Customer 1 86 1 3 2 Listing Generation and Verification 2 2 86 4 4 86 1 GENERAL DESCRIPTION 1 1 INTRODUCTION The ST62T32B and ST62E32B devices are low cost members of the ST62xx 8 bit HCMOS family of microcontrollers which is targeted at low to me dium complexity applications All ST62xx devices are based on a building block approach a com Figure 1 Block Diagram 8 BIT A D CONVERTER DATA ROM USER SELECTABLE PROGRAM Memory DATA RAM 7948 bytes 192 Bytes DATA EEPROM 128 Bytes STACK LEVEL 1 STACK LEVEL 2 STACK LEVEL 8 BIT CORE STACK LEVEL 4 STACK LEVEL 5 STACK LEVEL 6 POWER BOWER OSCILLATOR RESET 1 01 OSCin OSCou
9. CP1 triggered restart mode with CP2 event de tection CP2 triggered restart mode with second CP2 event detection Software triggered restart mode with CP2 event detection CP1 triggered restart mode with CP2 event de tection This mode RLDSEL1 1 External events on CPi pins are enabled as soon as RUNRES bit is set which lets the prescaler and the down counter running Thenext active edge on CP1 causes the counter to be loaded from RLCP the CP1FLG to be set and the downcounting starts from RLCP value Each following active edge on CP1 will cause areload ofthe counter If CP1FLG is notreset before the next reload the CP1ERR flag is set atthe same time as the counter is reloaded Both flags should then be cleared by software While the counter is counting any active edge CP2 will capture the value of the counter at that in stant into the GP Register and setthe CP2FLG bit If CP2FLG is not cleared before the following CP2 event the CP2ERR flag bit is set and no new cap ture can be performed Capturing is re enabled by clearing both CP2FLG and CP2ERR Ifacapture on CP2 and areload on CP1 occur atthe same time the capture ofthe counter to CP is made first and then the counter is reloaded from RLCP is enabled for RLDSEL2 0 and Figure 30 CP1 Triggered Resiart Mode with CP2 Event Detection COUNTER 00h 0000h CT RUNRES Enable the Inputs Disabled Reload and Start Set CP1FLG Reload Set CP1E
10. If it is cleared to O all the prescaler bits are set to 1 and the counter is inhibited from counting The prescaler can be loaded with any value between 0 and 7Fh if bit PSI is set to 1 The prescaler tap is selected by means of the PS2 PS1 PSO bits in the control reg ister Figure 26 ilustrates ihe Timer s working principle DATABUS 8 b7 be 55 b4 STATUS CONTROL REGISTE b2 bi bo MZJETI pour Psi Pst 50 VA00009 43 86 ST62T32B ST62E32B TIMER Cont d 4 2 1 Timer Operating Modes There are three operating modes which are se lected by the TOUT and DOUT bits see TSCR register These three modes correspond to the two clocks which can be connected to the 7 bit prescaler 12 TIMER pin signal and to the output mode 4 2 1 1 Gated Mode TOUT 0 DOUT 41 In this mode the prescaler is decremented by the Timer clock input 12 but ONLY when the signal on the TIMER pin is held high allowing pulse width measurement This mode is selected by clearing the TOUT bit in the TSCR register to 0 i e as input and setting the DOUT bit to 1 4 2 1 2 Event Counter Mode TOUT 0 DOUT 0 In this mode the TIMER pin is the input clock of the prescaler which is decremented on the rising edge 4 2 1 3 Output Mode TOUT 1 DOUT data out The TIMER pin is connected to the DOUT latch hence the Timer prescale
11. SPlantefrujpt Disable Register Write SPI Data Register Read 4 Bit Counter Q4 High after Clock8 8 Bit Data Shift Register Enable to Processor Data Bus VR01504 63 86 ST62T32B ST62E32B SERIAL PERIPHERAL INTERFACE Cont d After 8 clock pulses D7 D0 the output of the 4 bit binary counter becomes low disabling the clock from the counter and the data shift register Q4 enables the clock to generate an interrupt on the 8th clock falling edge as long as no reset of the counter processor write into the 8 bit data shift register takes place After a processor reset the interrupt is disabled The interrupt is active when writing data in the shift register and desactivated when writing any data in the SPI Interrupt Disable register The generation of an interrupt to the Core provides information that new data is available input mode or that transmission is completed output mode allowing the Core to generate an acknowledge on the 9th clock pulse I C bus The interrupt is initiated by a high to low transition and therefore interrupt options must be set accord ingly as defined in the interrupt section After power on reset or after writing the data shift register the counter is reset to zero and the clock is enabled In this condition the data shift register is ready for reception No start condition has to be detected Through the user software the Core may pull down the Sin line Acknowledge and s
12. Write Only Writ ing a 1 to this bit will start a conversion on the se lected channel and automatically reset to 0 the EOC bit If the bit is set again when a conversion is in progress the present conversion is stopped and a new one will take place This bit is write only any attempt to read it will show a logical zero Bit PDS Power Down Selection This bit acti vates the A D converter if set to 1 Writing a 0 to this bit will put the ADC in power down mode idle mode Bit 3 Reserved Must be kept cleared Bit 22 CLSEL Clock Selection When set the ADC is driven by the MCU internal clock divided by 6 and typical conversion time at 8MHz is 35 5 When cleared Reset state MCU clock divided by 12 is used with a typical 70us conversion time at 8MHz Bit 1 0 Reserved Must be kept cleared A D Converter Data Register ADR Address OD0h Read only 7 0 Bit 7 0 07 00 8 Bit A D Conversion Result 4 ST62T32B ST62E32B 4 5 U A R T Universal Asynchronous Receiver Transmitter The UART provides the basic hardware for asyn chronous serial communication which combined with an appropriate software routine gives a serial interface providing communication with common baud rates up to 38 400 Baud with an 8MHz ex ternal oscillator and flexible character formats Operating in Half Duplex mode only the UART uses 11 bit characters comprising 1 start bit 9 data bits and 1 Stop bit P
13. nent high level has to be written onto the I O port in order to achieve a proper stop condition on the TXD line when no transmission is active VR02009 59 86 ST62T32B ST62E32B 4 5 2 CLOCK GENERATION The UART contains a built in divider of the MCU internal clock for most common Baud Rates as shown in Table 20 Other baud rate values can be calculated from the chosen oscillator frequency di vided by the Divisor value shown The divided clock provides a frequency that is 8 times the desired baud rate This allows the Data reception mechanism to provide a 2 to 1 majority voting system to determine the logic state of the asynchronous incoming serial logic bit by taking 3 timed samples within the 8 time states The bits not sampled provide a buffer to compen sate for frequency offsets between sender and re ceiver 4 5 3 DATA TRANSMISSION Transmission is fixed to a format of one start bit nine data bits and one stop bit The start and stop bits are automatically generated by the UART The nine databits are under control of the user and are flexible in use Bits 0 7 are typically used as data bits while bit 9 is typically used as parity but can also be a 9th data bit or an additional Stop bit As parity is not generated by the UART it should be calculated by program and inserted in the appro priate position of the data i e as bit 7 for 7 bit data with Bit 9 set to 1 giving two effective stop biis or as the independent bit
14. such as constants and look up tables in Program Y REGISTER memory 1 3 3 1 Data ROM All read only data is physically stored in program memory which also accommodates the Program Space The program memory consequently con tains the program code to be executed as well as the look up tables required by the The Data Space locations in which the different constants and look up tables are addressed by the processor core may be thought of as a 64 byte window through which it is possible to access the read only data stored in Program memory 1 3 3 2 Data RAM EEPROM In ST6232B and ST62E32B devices the data RESERVED 1 3 4 Stack Space INTERRUPT POLARITY REGISTER i OSCILLATOR CONTROL REGISTER Stack space consists of six 12 bit registers which SPI INTERRUPT DISABLE REGISTER are used to stack subroutine and interrupt return SPI DATA REGISTER space includes 60 bytes of RAM the accumulator A the indirect registers X Y the short direct registers V W the I O port registers the pe ripheral data and control registers the interr pt option register and the Data ROM Window register DRW register Additional RAM and pages can also be addressed using banks f 64 bytes located between addresses OOhand 4 VO INTERRUPT POLARITY REGISTER addresses as well as the current program counter RESERVED contents EEPROM CONTROL REGISTER ARTIM16 COMPARE
15. ter and therefore cannot be accessed using single bit operations This register is used to position the 64 byte read only data window from address 40h to address 7Fh of the Data space in program memory in 64 byte steps The effective address of the byte to be read as data in program memory is obtained by concatenating the 6 least significant bits of the register address given in the instruction as least significant bits and the content of the DWR register as most significant bits as illustrat ed in Figure 6 below For instance when address ing location 0040h of the Data Space with 0 load ed in the DWR register the physical location ad dressed in program memory is 00h The DWR reg ister is not cleared on reset therefore it must be written to prior to the first access to ine Data read only memory window area ST62T32B ST62E32B Data Window Register DWR Address 0C9h Write Only 7 0 E DWR6 DWR5 DWR4 DWR3 DWR2 DWR1 DWRO Bits 7 Not used Bit 6 0 DWR5 DWRO Data read only memory Window Register Bits These are the Data read only memory Window bits that correspond to the upper bits of the data read only memory space Caution This register is undefined on reset Nei ther read nor single bit instructions may be used to address this register Note Care is required when handling the DWR register as it is write only For this reason the DWR contents should not be changed while exe cuting an inter
16. the frequency is con trolled through the and MASK values Fig ure 29 The condition to reset PWMPOL 1 or set back PWMPOL 0 PWM pin is a matched masked comparison to CMP Given a RLCP and MASK values within the Table 17 CMP defines the duty cycle In Toggle mode PWMMD 1 PWM pin changes of state at each positive masked comparison to CMP value The frequency is half the frequency in Set Reset mode and the duty cycle is always 5096 4 3 2 3 Frequency and duty cycles on OVF pin OVF pin activation is directed by the timer overflow occurence and therefore its frequency depends only of the downcounting time from the reload val ue to 0000h This means its period is equal to T RLCP 1 x x Tclk in Set Reset mode and 2 x RLCP 1 x x Tclk in Toggle mode Duty cycle is controlled in Set Reset mode OVFMD cleared by software since OVF pin can be reset only by clearing the OVFFLG bit In toggle mode OVFMD set the duty cycle is always 50 Period in Set Reset mode PWMMD 0 RLCP 1 x Psc x Telk 2 1 1 x Psc x Telk 2 x 2 1 1 x Psc x Telk Period in Toggle mode PWMMD 1 2 x RLCP 1 x x Note n 15 the position of the most significant bit of MA 48 86 value 4 ST62T32B ST62E32B Figure 29 Mask Impact on the Compare Functions in PWM mode PWMD 0 PWMPOL 1 Bit 01 3 XEXEXOXEXEXAKOXEXIXEXOKEXIKEX XOX MASK Paine M most 000Fh significant 1 is bit 3
17. 0 PORT TIM NMI PULL PULLIPULL WDACT OSGEN Bit 7 Reserved Bit 6 PORT PULL This bit must be set high to have pull up input state at reset on the I O port When this bit is low I O ports are in input without pull up high impedance state at reset Bit 5 EXTCNTL This bit selects the External STOP Mode capability When EXTCNIL is high pin NMI controls if the STOP mode can be ac cessed when the watchdog is active When NTL is low the STOP instruction is processed asa WAIT as soon as the watchdog is active Bit 4 PROTECT This bit allows the protection of the software contents against piracy When the bit PROTECT is set high readout of the OTP con tents is prevented by hardware No programming equipment is able to gain access to the user pro gram When this bit is low the user program can be read Bit 3 TIM PULL This bit must be set high to con figure the TIMER pin with a pull up resistor When itis low no pull up is provided Bit 2 NMI PULL This bit must be set high to con figure the NMI pin with a pull up resistor when it is low no pull up is provided Bit 1 WDACT This bit controls the watchdog ac tivation When it is high hardware activation is se lected The software activation is selected when WDACT is low ST62T32B ST62E32B Bit OSGEN This bit must be set high to enable the oscillator Safe Guard When this bit is low the OSG is disab
18. 2 is not sei there will be no programming cycle and the E2PAR will be un affected Consequently the E2PAR1 bit cannot be set 2 is low The 2 1 bit can be set by user only if the 2 and 2 2 bits are also set 14 86 EEPROM Control Register EECTL Address DFh Read Write Reset status 00h 7 0 2 E2PAR1 E2PAR2 E2BUSY Bit 7 D7 Unused Bit 6 E2OFF Stand by Enable Bit WRITE ONLY If this bitis setthe EEPROM is disabled any access willbe meaningless and the power consumption of the EEPROM is reduced to its lowest value Bit 5 4 D5 D4 Reserved MUST be kept reset Bit E2PAR1 Parallel Start Bit WRITE ONLY Once in Parallel Mode as soon as the user software sets the E2PAR1 bit parallel writing of the 8 adja cent registers will start This bit is internally reset at the end of the programming procedure Note that less than 8 can be written if required the un defined bytes being unatfected by the parallel pro gramming cyclesthis 15 explained in greater detail in the Additional Notes on Parallel Mode overleaf Bit 2 lt E2PAR2 Parallel Mode En Bit WRITE ONLY This bit must be set by the user program in order to perform parallel programming If E2PAR2 is set and the parallel start bit E2PAR1 is reset up to 8 adjacent bytes can be written simultane ously These 8 adjacent bytes are considered as a row whose address lines A7 A
19. 9 Figure 36 Data Sampling Points SAMPLES VRO2010 60 86 The character options are summarised in the fol lowing table Table 19 Character Options Start Bit 1 Software Parity 1 Stop Start Bit No Parity 1 Stop Start Bit No Parity 2 Stop Start Bit 1 Software Parity 2 Stop Bit 9 remains in the state programmed for consec utive transmissions until changed by the user or until a character is received when the state of this bit is changed to that of the incoming bit 9 The recommended procedure is thus to set the value of this bit before transmission is started Transmission is started by writing to the Data Reg ister the Baud Rate and Bit 9 should be set before this action The UARTOE signal switches the out put multiplexer to the UART output and a start bit is sent a for one bit time followed by the 8 data values Isb first and the value of the Bit9 bit The output is then set to 1 for a period of one bit time to generate a Stop bit and then the UARTOE signal returns the TXDT line tosits alternate function The end transmission is flagged by setting TXMT to 1 interrupt is generated if ena bled The LXMT flag is reset by writing a 0 to the bit position it is also cleared automatically when a new character is written to the Data Register TXMT can be set to 1 by software to generate a software interrupt so care must be taken in manip ulating the Control Register Figure 37 Charac
20. CT compared with ihe logical AND of the compare Register CMP MASK amp CT MASK amp CMP Masked Counter Zero is the logical AND of the Mask Register MASK with the Counter Register CT compared with zero amp CT 0000h 4 CONTROL REGISTERS Cont d Status Control Register 4 5 4 Address E3h Read Write Clear only 7 0 Bit7 Bit4 2 Reserved set to 0 Bit 3 OVFPOL Overflow Output Polarity This bit defines the polarity for the Overflow Output OVF When 0 OVF is set on every overflow event if en abled in Set mode OVFEN 1 OVFMD 0 The reset state of OVF is 0 When 1 OVF is reset on every overflow event if enabled in Set mode The reset state of OVF is 1 Bit 2 OVFEN Overflow Output Enable This bit enables the Overflow output OVF When 0 the Overflow output is disabled if OVFPOL 0 the state of OVF is 0 if OVFPOL 1 the state of OVF 1 The Overflow Output is enabled when this bit 1 it must be set to use the OVF output Bit 1 PWMPOL PWM Output Polarity This bit defines the polarity for the PWM Output PWM When 0 PWM is set on every Masked Counier Zero event and is reset on a Masked Compare if enabled in Set Reset mode PWMEN 4 PWM MD 0 The reset state of PWM pin is 9 When 1 OVE is set on every Masked Compare event and is reset on a Masked Counter Zero event if enabled in Set Reset mode PWMEN 1 PWIMMD 0 The reset state of PWM is 1 Bit 0 P
21. D is powered and en abled for conversion This bit must be set at least ky ST62T32B ST62E32B one instruction before the beginning of the conver sion to allow stabilisation of the A D converter This action is also needed before entering WAIT mode since the A D comparator is not automati cally disabled in WAIT mode During Reset any conversion in progress is stopped the control register is reset to 40h and the ADC interrupt is masked EAI 0 Figure 34 ADC Block Diagram INTERRUPT CLOCK RESET AVpp Ain s CONVERTER CONTROL REGISTER RESULT REGISTER CORE CONT SIGNALS CORE VA00418 4 4 1 Application Notes The A D converter does not feature a sample and hold circuit The analog voltage to be measured should therefore be stable during the entire con version cycle Voltage variation should not exceed 1 2 LSB for the optimum conversion accuracy A low pass filter may be used at the analog input pins to reduce input voltage variation during con version When selected as an analog channel the input pin is internally connected to a capacitor Cg of typi cally 12pF For maximum accuracy this capacitor must be fully charged at the beginning of conver sion In the worst case conversion starts one in struction 6 5 us after the channel has been se lected In worst case conditions the impedance ASI of the analog voltage source is calculated us ing the following formu
22. High byte D15 D8 of the 16 bit Compare Register Compare Register Low Byte CMP Address EEh Read Write 07 00 These bits are the Low byte 07 00 of the 16 bit Compare Register Mask Register High Byte MASK Address EFh Read Write D7 DO These bits are the High byte D15 D8 of the 16 bit Mask Register Mask Register Low Byte MASK Address EOh Read Write D7 DO These bits are the Low byte D7 DO of the 16 bit Mask Register 4 4 4 A D CONVERTER ADC The A D converter peripheral is an 8 bit analog to digital converter with analog inputs as alternate I O functions the number of which is device depend ent offering 8 bit resolution with a selectable con version time of 70us or 35ys at an oscillator clock frequency of 8MHz The ADC converts the input voltage by a process of successive approximations using a clock fre quency derived from the oscillator with a division factor of 12 or 6 After Reset division by 12 is used by default to insure compatibility with other mem bers of the ST62 MCU family With an oscillator clock frequency less than 1 2MHz conversion ac is decreased Selection of the input pin is done by configuring the related I O line as an analog input via the Op tion and Data registers refer to I O ports descrip tion for additional information Only one I O line must be configured as an analog input atany time The user must avoid any situation in which more than on
23. I O line see Figure 18 to allow its state to be controlled by soft ware The I O line can then be used to keep low while Watchdog protection is required or to avoid noise or key bounce When no more processing 15 required the line is released and the device placed in STOP mode for lowest power consumption When software activation is selected and the Watchdog is not activated the downcounter may be used as a simple 7 bit timer remember that the bits are in reverse order The software activation option should be chosen only when the Watchdog counter is to be used as a timer To ensure the Watchdog has not been un expectedly activated the following instructions should be executed within the first 27 instructions jrr 0 WD 4 3 ldi WD OFDH 27 86 ST62T32B ST62E32B DIGITAL WATCHDOG Cont d These instructions test the C bit and Reset the MCU i e disable the Watchdog if the bit is set i e if the Watchdog is active thus disabling the Watchdog In all modes a minimum of 28 instructions are ex ecuted after activation before the Watchdog can generate a Reset Consequently user software should load the watchdog counter within the first 27 instructions following Watchdog activation software mode or within the first 27 instructions executed following a Reset hardware activation It should be noted that when the GEN bit is low in terrupts disabled the NMI interrupt is active but cannot cause a
24. MASK REG LOW BYTE MASK Table 3 Additional RAM EEPROM Banks 16 2ND STATUS CONTROL REGISTER SCR2 16 STATUSCONTROL REGISTERSCR3 Device EEPROM ARTIMTG 4TH STATUS CONTROL REGISTER SCRA 16 1ST STATUSCONTROL REGISTER SCRI ARTIM16 RELOAD CAPTURE REG HIGH BYTE RLCP ARTIM16 RELOAD CAPTURE REG LOW BYTE RLCP ARTIM16 CAPTURE REGISTER HIGH BYTE CP ARTIM16 CAPTURE REGISTER LOW BYTE CP ARTIM 16 COMPARE MASK REG HIGH BYTE MASK RESERVED PORT E DATA REGISTER PORT E DIRECTION REGISTER PORT E OPTION REGISTER ACCUMULATOR WRITE ONLY REGISTER gt gt DID EE EE olo SE 25 DD mim SP cie mm 20 oe ma ma S mm 43 olo lt lt 70 9 10 86 1 3 5 Data Window Register DWR The Data read only memory window is located from address 0040h to address 007Fh in Data space It allows direct reading of 64 consecutive bytes locat ed anywhere in program memory between ad dress 0000h and 1FFFh top memory address de pends on the specific device All the program memory can therefore be used to store either in structions or read only data Indeed the window can be moved in steps of 64 bytes along the pro gram memory by writing the appropriate code in the Data Window Register DWR The DWR can be addressed like any RAM location in the Data Space it is however a write only regis
25. NMI pin 100 Ta 25 C TWEE EEPROM Write Time Ta 85 C fo Ta 125 C 20 Retention EEPROM Data Retention Capacitance oF Cour Output Capacitance Al Outputs Pins Note 1 Period for which Vpp has to be connected at OV to allow internal Reset function at next power up 6 5 A D CONVERTER CHARACTERISTICS 40 to 125 C unless otherwise specified Value Symbol Parameter Test Conditions O O O Le m wem Res Resolution gt ih EDE Total Accuracy 1 fosc gt 32kHz 4 fosc 8MHz TA lt 85 C 70 Gonversion result when ZIR Zero Input Readin Hex IN VDD Analog Input Current During _ Analog Input O o 5 1 Noise at AVpp AVss 10mV 2 With oscillator frequencies less than 1MHz the A D Converter accuracy is decreased 74 86 ST62T32B ST62E32B 6 6 TIMER CHARACTERISTICS TA 40 to 125 C unless otherwise specified Value Symbol o Parameter Test Conditions Test Conditions ee oe p Vpp 3 0V us 6 7 SPI CHARACTERISTICS TA 40 to 125 C unless otherwise specified Value Symbol Parameter Test Conditions 2 2 C ES fu poe on 1 1 6 8 ARTIMER16 ELECTRICAL CHARACTERISTICS TA 40 to 125 C un
26. ON ek nS Sneek aR Aaa es RR 16 2 2 CPU REGISTERS ue e 16 3 CLOCKS RESET INTERRUPTS AND POWER SAVING 5 18 3 1 CLOCK SYSTEM 1 7 18 3 1 1 Main Oscillator 25 18 3 1 2 Low Frequency Auxiliary Oscillator 19 3 1 3 Oscillator Safe 19 3 2 RESETS 7 22 3 2 1 RESET WA 22 3 2 2 Power On eset 22 3 2 3 Watchdog 23 3 2 4 Application 23 3 2 5 MCU Initialization Sequence 23 3 3 DIGITAL 25 3 3 1 Digital Watchdog Register 27 3 3 2 Application 27 9 4 INTERRUPTS dues rmt Pede mette ur UE E week 29 3 4 1 Interrupt request s s ve eo eed ee d 29 3 4 2 Interrupt Procedure 30 3 4 3 Interrupt O
27. RLCP Reload CT from RLCP Set CP2ERR VR02007C Figure 32 Software Triggered Restart Mode with CP2 Event Detection COUNTER 0000h 0000h CT RUNRES Load Counter from RLCP and Startup CP1 disabled CP2 disabled Set CP1FLG Capture CT into CP Set CP2FLG Software Reset Set CP1ERR CP1 disabled Set CP2ERR VR02007D 51 86 ST62T32B ST62E32B TIMINGS MEASUREMENT MODES Contd 4 3 3 2 Timing measurement without startup control The down counter is in free running mode with RUNRES bit set and RELOAD bit cleared This means counter automatically restarts from FFFFh on zero overflow and signal generation on PWM and OVF pins is not affected Two independent capture paths exist to CP and RLCP which are both Read only registers CP1 is the source Configurable polarity for a capture into RLCP while CP2 is the source Configurable polarity of a capture into CP Independently of CP2 signal if CP1FLG and CP1ERR are cleared the first active edge on CP1 will trigger a capture into RLCP triggering CP1FLG As long as CP1FLG has not been cleared a second following active edge will trig CP1ERR without any capture into neither RLCP nor CP Independently of CP1 signal if CP2FLG and CP2ERR are cleared the first active edge on CP2 will trigger a capture into CP triggering CP2FLG As long as CP2FLG has not been cleared a sec ond following active edge will trig CP2ERR without any capture into neithe
28. ST62xx family of MCUs in order to reduce the product s electrical consumption during idle periods These two power saving modes are described in the following paragraphs 3 5 1 WAIT Mode The MCU goes into WAIT mode as soon as the WAIT instruction is executed The microcontroller can be considered as being in a software frozen state where the core stops processing the pro gram instructions the RAM contents and peripher al registers are preserved as long as the power supply voltage is higher than the RAM retention voltage In this mode the peripherals are still ac tive WAIT mode can be used when the user wants to reduce the MCU power consumption during idle periods while not losing track of time or the capa bility of monitoring external events The active os cillator is not stopped in order to provide a clock signal to the peripherals Timer counting may be enabled as well as the Timer interrupt before en tering the WAIT mode this allows the WAIT mode to be exited when a Timer interrupt occurs The same applies to other peripherals which use the clock signal If the WAIT mode is exited due to a Reset either by activating the external pin or generated by the Watchdog the MCU enters a normal reset proce dure If an interrupt is generated during WAIT mode the MCU s behaviour depends on the state 34 86 of the processor core prior to the WAIT instruction but also on the kind of interrupt request which is generated
29. a RAM location in the Data Space at the address CAh nevertheless it is a write only register that cannot be accessed with single bit operations This regis ter is used to select the 2 Kbyte of the Program Space that will be addressed The number of the page has to be loaded in the PRPR register Refer to the Program Space description for additional information concerning the use of this register The PRPH register is not modified when an interrupt or a subroutine occurs Care is required when handling the PRPR register as it is write only For this reason it is not allowed to change the PRPR contents while executing in terrupt service routine as the service routine cannot save and then restore its previous content This operation may be necessary if common rou tines and interrupt service routines take more than 2K bytes in this case it could be necessary to di vide the interrupt service routine into a minor part in the static page start and end and to a second major part in one of the dynamic pages If it is im possible to avoid the writing of this register in inter rupt service routines an image of this register must be saved in a RAM location and each time the program writes to the PRPR it must write also to the image register The image register must be written before PRPR so if an interrpt occurs between the two instructions the PRPR is not af fected 3 ST62T32B ST62E32B Program ROM Page Regis
30. con trol registers and the associated control logic The 16 bit registers are accessed from the 8 bit inter nal bus The full 16 bit word is written in two bytes the high byte first and then the low byte The high byte is stored in an intermediate register and is written to the target 16 bit register at the same Figure 27 ARTIMER16 Block Diagram em ke 4 16 Bit DATA BUS e a lt lt 2 gt BUS INTERFACE time as the write to the low byte This high byte will remain constant if further writes are made to the low bytes until the high byte is changed Full Read Write access is available to all registers ex cept where mentioned The ARTIMER16 may be placed into the reset mode by resetting RUNRES to 0 in order to achieve lower consumption The contents of RLCP CP MASK and CMP are not affected nor is the previous run mode of the timer changed If RUNRES is subsequently set to 1 the timer re starts in the same RUN mode as previously set if no changes are made to the timer status registers Finally interrupt capabilities are associated to the Reload Capture and Compare features CONTROL LOGIC 46 86 VR02014 4 4 3 1 CENTRAL COUNTER The core of the 16 bit Auto Reload Timer is a 16 bit synchronous downcounter which accepts the MCU internal clock through a prescaler with a pro grammable ratio 1 1 1 4 1 16 The maximum time for downcounting is therefore 216 x Psc x Tel
31. loaded with OFFh while the 7 bit prescaler is load ed with 07Fh and the TSCR register is cleared This means that the Timer is stopped PSI 0 and the timer interrupt is disabled If the Timer is programmed in output mode the DOUT bit is transferred to the TIMER pin when TMZ is set to one by software or due to counter decrement When TMZ is high the latch is trans parent and DOUT is copied to the timer pin When TMZ goes low DOUT is latched A write to the TCR register will predominate over the 8 bit counter decrement to 00h function i e if a write and a TCR register decrement to 00h occur simultaneously the write will take precedence and the TMZ bit is not set until the 8 bit counter reaches 00h again The values of the TCR and the PSC registers can be read accurately at time 4 2 4 Timer Registers Timer Status Control Register T SCR Address 0D4h Read Write 7 0 Bit 7 TMZ Timer Zero bit A low to high transition indicates that the timer count register has decrement to zero This bit must be cleared by user software before starting a new count Bit 6 ETI Enable Timer Interrupt When set enables the timer interrupt request If 0 the timer interrupt is disabled If ETI21 and TMZ 1 an interrupt request is generated Bit 5 TOUT Timers Output Control When low this bit selects the input mode for the TIMER pin When high the output mode is select ed ky ST62T32B ST62E32B
32. lost When a subroutine or interrupt return occurs RET or RETI instructions the first level register is shifted back into the PC and the value of each level is popped back into the previous level Since the accumula tor in common with all other data space registers is not stored in this stack management of these registers should be performed within the subrou tine The stack will remain in its deepest position if more than 6 nested calls or interrupts are execut ed and consequently ihe last return address will be lost It will also remain in its highest position if the stack is empty and a RET or RETI is executed In this case the next instruction will be executed Figure 8 516 CPU Programming Mode INDEX XREG POINTER 50 REGISTER b7 YREG POINTER 50 57 V REGISTER 50 b7 W REGISTER 50 SHORT DIRECT ADDRESSING MODE b7 ACCUMULATOR 50 511 PROGRAM COUNTER 50 SIX LEVELS STACK REGISTER NORMAL FLAGS INTERRUPT FLAGS NMI FLAGS VA000423 17 86 ST62T32B ST62E32B 3 CLOCKS RESET INTERRUPTS AND POWER SAVING MODES 3 1 CLOCK SYSTEM The MCU features a Main Oscillator which can be driven by an external clock or used in conjunction with an AT cut parallel resonant crystal or a suita ble ceramic resonator In addition a Low Frequen cy Auxiliary Oscillator can be switched for security reasons to reduce power consump tion or to offer the benefits of a back up clock sys tem T
33. other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics 1998 STMicroelectronics All Rights Reserved Purchase of Components by STMicroelectronics conveys a license under the Philips C Patent Rights to use these components in an 12 system is granted provided that the system conforms to the 12 Standard Specification as defined by Philips STMicroelectronics Group of Companies Australia Brazil Canada China France Germany Italy Japan Korea Malaysia Malta Mexico Morocco The Netherlands Singapore Spain Sweden Switzerland Taiwan Thailand United Kingdom U S A http www st com 4 86 86
34. space memory One group either sets or clears The other group see Conditional Branch performs the bit test branch operations Table 23 Conditional Branch Instructions JRR b rr ee JRS b rr ee Notes b 3 address 5 bitsigned displacement in the range 15 to 16 lt F128M gt ee 8 bitsigned displacement in the range 126 to 129 Table 24 Bit Manipulation Instructions Control Instructions The control instructions control the MCU operations during program exe cution Jump and Call These two instructions are used to perform long 12 bit jumps or subroutines call inside the whole program space rr Data space register A Affected The tested bit is shifted into carry Not Affected SET b rr Bit Direct 2 4 RES b rr Bit Direct 2 4 Notes b S bit address r Data space register Table 25 Control Instructions Not lt M gt Affected NOP Inherent Inherent Inherent Inherent Inherent Notes 1 This instruction is deactivated lt N gt and a WAIT is automatically executed instead of a STOP if the watchdog function is selected Affected Not Affected Table 26 Jump amp Call Instructions CALL abc Extended 2 4 JP abc Extended 2 4 Notes abc 12 bit address Not Affected 68 86 3 ST62T32B ST62E32B Opcode Map Summary The following table contains an opcode map for the instructions used by the ST6 bO rr ee gt
35. the device which generated the interrupt re quest by polling The user should save the regis ters which are used within the interrupt routine in a software stack After the RETI instruction is exe cuted the MCU returns to the main routine Figure 20 Interrupt Processing Flow Chart INSTRUCTION FETCH INSTRUCTION EXECUTE INSTRUCTION NO WAS THE INS A YES IS THE CORE LOAD PC FROM INTERRUPT VECTOR FFC FFD SET INTERRUPT MASK PUSH THE PC INTO THE STACK ALREADY IN NORMAL MODE SELECT INTERNAL MODE FLAG CHECK IF THERE IS AN INTERRUPT REQUEST AND INTERRUPT MASK VA000014 4 INTERRUPTS 3 4 3 Interrupt Option Register The Interrupt Option Register IOR is used to en able disable the individual interrupt sources and to select the operating mode of the external interrupt inputs This register is write only and cannot be accessed by single bit operations Address 06881 Write Only Reset status 00h 7 0 eon Bit 7 Bits 3 0 Unused Bit 6 LES Level Edge Selection bit When this bit is set to one the interrupt source 1 is level sensitive When cleared to zero the edge sensitive mode for interrupt request is selected Table 11 Interrupt Requests and Mask Bits ST62T32B ST62E32B Bit 5 ESB Edge Selection bit The bit ESB selects the polarity of the interrupt source 2 Bit 4 GEN Global Enable Interrupt When this bit i
36. vided into six different types load store arithme tic logic conditional branch control instructions jump call and bit manipulation The following par agraphs describe the different types All the instructions belonging to a given type are presented in individual tables Table 21 Load amp Store Instructions Addressing Mode Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Direct Direct Indirect Indirect Indirect Indirect Load amp Store These instructions use one two or three bytes in relation with the addressing mode One operand is the Accumulator for LOAD and the other operand is obtained from data memory using one ofthe addressing modes For Load Immediate one operand can be any of the 256 data space bytes while the other is always immediate data 4 L Pags T Low PPA KR HHS A gt gt gt gt gt gt gt gt gt gt gt gt gt gt 1 1 1 1 1 1 1 1 2 2 1 1 1 1 2 AB gt LD Y A LDI A N Immediate LDI rr N Immediate 3 i Notes X Y Indirect Register Pointers V amp W Short Direct Registers 3 Immediate data stored in ROM memory rr Data space register A Affected Not Affected 66 86 A 4 INSTRUCTION SET Cont d Arithmetic and Logic These instructions are used to perform the arithmetic calculations and logic operations In AND ADD CP SU
37. wake up from STOP WAIT modes Figure 19 Digital Watchdog Block Diagram DB1 7 LOAD SET DATA BUS 28 86 Figure 18 A typical circuit making use of the EXERNAL STOP MODE CONTROL feature SWITCH VR02002 OSCILLATOR CLOCK VA00010 4 3 4 INTERRUPTS The CPU can manage four Maskable Interrupt sources in addition to a Non Maskable Interrupt source top priority interrupt Each source is asso ciated with a specific Interrupt Vector which con tains a Jump instruction to the associated interrupt service routine These vectors are located in Pro gram space see Table 9 When an interrupt source generates an interrupt request and interrupt processing is enabled the PC register is loaded with the address of the inter rupt vector i e of the Jump instruction which then causes a Jump to the relevant interrupt serv ice routine thus servicing the interrupt Interrupt sources are linked to events either on ex ternal pins or on chip peripherals Several events can be ORed on the same interrupt source and relevant flags are available to determine which event triggered the interrupt The Non Maskable Interrupt request has the high est priority and can interrupt any interrupt routine at any time the other four interrupts cannot inter rupt each other If more than one interrupt request is pending these are processed by the processor core according to their priority level source 1 has the higher prio
38. which are automatically switched and so do not need to be saved The following list summarizes the interrupt proce dure MCU The interrupt is detected The C and Z flags are replaced by the interrupt flags or by the NMI flags The PC contents are stored in the first level of the stack The normal interrupt lines are inhibited NMI still active The first internal latch is cleared The associated interrupt vectoris loaded inthe PC WARNING In some circumstances when maskable interrupt occurs while the 516 is in NORMAL mode and especially during the execu tion of an Idi IOR 00h instruction disabling all maskable interrupts if the interrupt arrives during the first cycles of the Idi instruction which is 4 cycle instruction the core will switch to interrupt mode BUT the flags CN ZN will NOT switch to the interrupt pair CI and 21 User User selected registers are saved within the in terrupt service routine normally on a software stack The source of the interrupt is found by polling the interrupt flags if more than one source is associ ated with the same vector The interrupt is serviced Return from interrupt RETI 30 86 MCU Automatically the MCU switches back to the nor mal flag set or the interrupt flag set and pops the previous PC value from the stack The interrupt routine usually begins by the identify ing
39. 6 A5 A4 A3 are fixed while A2 A1 and AO are the changing bits as illustrated in Table 6 E2PAR2 is automatically set at the end of any parallel programming proce dure It can be reset by the user software before starting the programming procedure thus leaving the EEPROM registers unchanged Bit 1 2 5 EEPROM Busy Bit READ ON LY This bit is automatically set by the EEPROM control logic when the EEPROM is in program ming mode The user program should test it before any EEPROM read or write operation any attempt to access the EEPROM while the busy bit is set will be aborted and the writing procedure in progress will be completed Bit 0 2 EEPROM Enable Bit WRITE ON LY This bit enables programming of the EEPROM cells It must be set before any write to the EEP ROM register Any attempt to write to the EEP ROM when is low is meaningless and will not trigger a write cycle 4 1 4 PROGRAMMING MODES 1 4 1 Option Byte The Option Byte allows configuration capability to the MCUs Option byte s content is automatically read and the selected options enabled when the chip reset is activated It can only be accessed during the programming mode This access is made either automatically copy from a master device or by selecting the OPTION BYTE PROGRAMMING mode of the pro grammer The option byte is located in a non user map No address has to be specified EPROM Code Option Byte 7
40. 8 6 JRR b4 rr ee JRS b4 rr ee gp o a JRR b2 rr ee B JRS b2 rr ee A z 9 e b6 rr ee 8 5 b6 rr ee A e lt e 9 A z 9 b1 rr ee lt e Q JRNC JRR b5 rr ee per JRNC JRS e b5 rr ee per JRNC JRR e b3 rr ee per JRNC JRS e b3 rr ee per JRNC JRR e b7 rr ee per prc JRNC JRS 2 JRC e b7 rr ee per per bt prc JRC lt E Q o prc JRC prc JRC gt A 5 gt 8 6 prc JRC Abbreviations for Addressing Modes Legend dir Direct Indicates Illegal Instructions sd Short Direct e 5 Bit Displacement oe Mnemonic imm Immediate b 3 Bit Address Operand inh Inherent rr dataspace address ext Extended nn 1 byte immediate data Bytes b d Bit Direct abc 12 bit address Add ing Mod bt Bit Test ee 8 bit Displacement pcr Program Counter Relative Indirect 7572 69 86 ST62T32B ST62E32B Opcode Map Summary Continued 8 9 A 1000 1001 1010 HI JRNZ JRNC 4 RES JR Lc pcr per 2 b d 2 JRNZ JRNC 4 SET JRZ e bO rr pcr pcr 2 JRNZ B 1011 1100 NI 4 JRNC 4 RES JRZ e b4 rr pcr b d JRNC SET e b4 rr b d JRNC RES e b2 rr b d JRNC SET JRZ e b2 rr b d JRNC RES JRZ e b6 rr b d per JR
41. AVss VDDp AVDD Vss VDD TEST Vpp 1 RESET Ain PB7 Ain PB6 Ain PB5 Ain PB4 Ain PB3 35 Nas on EPROM OTP only 6 86 PDO Ain PD1 Ain SCL PD2 Ain Sin PD3 Ain Sout PD4 Ain RXD1 PD5 Ain TXD1 PD6 Ain PD7 Ain PBO Ain VR01375G These compact low cost devices feature a Timer comprising an 8 bit counter and a 7 bit program mable prescaler an 16 bit Auto Reload Timer with 2 input capture channels EEPROM data ca pability a serial synchronous port communication interface SPI a serial asynchronous port inter face UART an 8 bit A D Converter with 21 ana log inputs and a Digital Watchdog timer making them well suited for a wide range of automotive appliance and industrial applications Figure 3 ST62T32B Pin Configuration PA4 Ain CP1 2 PA6 Ain PA7 Ain TIMER NMI AVss AVpp PDO Ain PD1 Ain SCL PD2 Ain Sin PD3 Ain Sout NC 1 s on EPROM OTP only VR02008A 4 1 2 PIN DESCRIPTIONS Vpp and Power is supplied to the MCU via these two pins Vpp is the power connection and Vss is the ground connection Vppp Vssp Power is supplied to the MCU I Os independently from the rest of the chip using these two pins These pins have to be connected to the VDD and VSS pins It is not allowed to leave any of these pins unconnected or to apply different potentials respectively to V5p Vppp and Vss Vssp AVpp and AVsg Power is supplied to the MCUA D converter independently from t
42. B instruc tions one operand is always the accumulator while the other can be either a data space memory con Table 22 Arithmetic amp Logic Instructions ADD A X Indirect ADD A Y Indirect ADD A rr Direct AND A X Indirect AND A Y Indirect AND A rr Direct CLR Short Direct CLRr Direct Indirect Indirect Direct Short Direct Short Direct Short Direct Shori Direct Direct Direct Indirect Indirect Short Direct Short Direct Short Direct Short Direct Direct Direct Indirect Indirect SLA A Inherent SUB A X Indirect SUB A Y Indirect SUB A rr Direct SUBITA Notes X Y Indirect Register Pointers V amp W Short Direct RegistersD Affected Immediate data stored in ROM memory Not Affected rr Data space register ky Bytes 1 1 1 2 2 1 1 1 1 1 1 2 2 1 1 1 1 1 1 2 2 1 1 2 1 1 2 ST62T32B ST62E32B tent or an immediate value in relation with the ad dressing mode In CLR DEC INC instructions the operand can be any of the 256 data space ad dresses In COM RLC SLA the operand is always the accumulator bet 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 67 86 ST62T32B ST62E32B INSTRUCTION SET Cont d Conditional Branch The branch instructions achieve a branch in the program when the select ed condition is met Bit Manipulation Instructions These instruc tions can handle any bit in data
43. Contact Phone No Reference STMicroelectronics references Device 1 ST62P32B Package Dual in Line Plastiq Plastic Quad Flat Tape amp Reel Temperature Range 0 C to 70 40 C to 85 C Watchdog Selection Software Activation Hardware Activation Ports Pull Up Selection Yes No NMI Pull Up Selection Yes Timer Pull Up Selection Yes No External STOP Mode Control Enabled Disabled OSG 1 Enabled 1 Disabled Readout Protection Standard Enabled Comments Supply Operating Range in the application Oscillator Fequency in the application Notes Signature Date 81 86 ST62P32B Notes 82 86 STA ST6232B 8 BIT MCUs WITH A D CONVERTER 3 0 to 6 0V Supply Operating Range 8 MHz Maximum Clock Frequency 40 to 125 C Operating Temperature Range Run Wait and Stop Modes 5 Interrupt Vectors Look up Table capability in Program Memory Data Storage in Program Memory User selectable size Data RAM 192 bytes Data EEPROM 128 bytes 30 pins fully programmable as Input with pull up resistor Input without pull up resistor Input with interrupt generation Open drain or push pull output Analog Input 9 I O lines can sink up to 20mA to drive LEDsvor TRIACS directly 8 bit Timer Counter with 7 bit programmable prescaler 16 bit Auto reload dimer with 7 bit programmable prescaler AR Timer Digit
44. Device ST6232B Package Dual in Line Plastiq Plastic Quad Flat Tape amp Reel Temperature Range 1 0 C to 70 40 C to 85 C Special Marking No Yes Authorized characters are letters digits and spaces only Maximum character count SDIPA2 10 PQFP52 10 Watchdog Selection Software Activation Hardware Activation Ports Pull Up Selection Yes No NMI Pull Up Selection 1 Yes No Timer Pull Up Seleciion 1 Yes External STOP Mode Gontrol Enabled Disabled OSG 1 Enabled Disabled ROM Readout Protection Standard Fuse cannot be blown 1 Enabled Fuse can be blown by the customer Note No part is delivered with protected ROM The fuse must be blown for protection to be effective Comments Supply Operating Range in the application Oscillator Fequency in the application Notes Signature Date 85 86 ST6232B 1 3 ORDERING INFORMATION The following section deals with the procedure for transfer of customer codes to STMicroelectronics 1 3 1 Transfer of Customer Code Customer code is made up of the ROM contents and the list of the selected mask options The ROM contents are to be sent on diskette or by electronic means with the hexadecimal file gener ated by the development tool All unused bytes must be set to FFh The selected mask options are communicated to STMicroelectronics using the correctly filled O
45. IST ST62T32B 77 ST62E32B 8 BIT OTP EPROM MCUs WITH A D CONVERTER 16 BIT AUTO RELOAD TIMER EEPROM SPI AND UART 3 0 to 6 0V Supply Operating Range 8 MHz Maximum Clock Frequency 40 to 125 C Operating Temperature Range Run Wait and Stop Modes 5 Interrupt Vectors Look up Table capability in Program Memory Data Storage in Program Memory User selectable size Data RAM 192 bytes Data EEPROM 128 bytes User Programmable Options 30 pins fully programmable as Input with pull up resistor Input without pull up resistor Input with interrupt generation Open drain or push pull output Analog Input m 9 lines can sink up to 20 to drive LEDs or TRIACs directly m 8 bit Timer Counter with 7 bit programmable prescaler m 16 bit Auto reload Timer with gt 7 bit programmable prescaler AR Timer Digital Watchdog 8 bit A D Converter with 21 analog inputs 8 bit Synchronous Peripheral Interface SPI 8 bit Asynchronous Peripheral Interface UART m On chip Clock oscillator can be driven by Quartz Crystal or Ceramic resonator m Oscillator Safe Guard m One external Non Maskable Interrupt ST623 EMU2 Emulation and Development System connects to an MS DOS PC via a parallel port DEVICE SUMMARY OTP EPROM DEVICE Bytes Pins 7948 52 CDIP42W See end of Datasheet for Ordering Information Rev 2 5
46. P TION LIST appended 1 3 2 Listing Generation and Verification When STMicroelectronics receives the user s ROM contents a computer listing is generated from it This listing refers exactly to the mask which will be used to produce the specified MCU The listing is then returned to the customer who must thoroughly check complete sign and return it to STMicroelectronics The signed listing forms a part of the contractual agreement for the creation of the specific customer mask Table 2 ROM version Ordering Information The STMicroelectronics Sales Organization will be pleased to provide detailed information on con tractual points Table 1 ROM Memory Map for ST6232B 0 0000h 007Fh Reserved 9 0080h 07FFh User ROM 0800h 0F9Fh User ROM OFAOh OFEFh Reserved OFFOh OFF7h Interrupt Vectors OFF8h OFFBh Reserved OFFCh OFFDh NMI Vector OFFEh OFFFh Reset Vector 0000h 000Fh Reserved 0010h 07FFh User ROM Page 3 0000h 900Fh Reserved 9 0019h 07FFh User ROM Page 1 STATIC Sales Type 19 Range ST6232BB1 XXX ST6232BB6 XXX ST6232BB3 XXX ST6232BQ1 XXX ST6232BQ6 XXX 0 to 70 C 40 to 85 C 40 to 125 C 0 to 70 C 40 to 85 C SDIP42 PQFP52 gt ST6232BQ3 XXX 40 to 125 C Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or
47. PB3 PB7 These 6 lines are organised as one I O port B Each line may be configured under software control as inputs with or without internal pull up resistors interrupt generating inputs with pull up resistors open drain or push pull outputs analog inputs for the A D converter PC5 PC7 These lines are organised as 1 0 port C Each line may be configured under soft ware control as input with or without internal pull up resistor interrupt generating input with pull up resistor analog input for the A D converter open drain or push pull output PDO PD7 These 8 lines are organised as one I O port portD Each line may be configured under software control as input with or without internal pull up resistor interrupt generating input with pull up resistor analog input open drain or push pull output adition the pins PD5 TXD1 and PDA RXD1 can be Used as UART output PD5 TXD1 or UART input PD4 RXD1 The pins PD3 Sout PD2 Sin and PD1 SCL can also be used respectively as data out data in and Clock pins forthe on chip SPI PEO PE4 These 5 lines are organised as one I O port PE Each line may be configured under soft ware control as input with or without internal pull up resistor interrupt generation input with pull up resistor open drain or push pull output In output mode these lines can also sink 20mA for direct LED and TRIAC driving TIMER This is the TIMER 1 I O pin In input mode it is connec
48. PI clock pin to the timer pin or by directly applying an external clock to the Scl line The peripheral is composed by an 8 bit Data shift Register and a 4 bit binary counter while the Sin pin is the serial shift input and Sout is the serial shift output These two lines can be tied together to implement two wires protocols I C bus etc When data is serialized the MSB is the first bit Sin has to be programmed as input For serial output Figure 39 SPI Block Diagram Port gt gt Port DOUT Data Reg Direction 4 CP DIN 8 Bit Tristate Data I O ST62T32B ST62E32B operation Sout has to be programmed as open drain output The SCL Sin and Sout SPI clock and data signals are connected to I O lines on the same external pins With these 3 lines the SPI can operate in the following operating modes Software SPI S BUS C bus and as a standard serial I O clock data enable An interrupt request can be generated af ter eight clock pulses Figure 39 shows the SPI block diagram The SCL line clocks on the falling edge the shift register and the counter To allow SPI operation in slave mode the SCL pin must be programmed as input and an external clock must be supplied to this pin to drive the SPI peripheral In master mode SCL is programmed as output a clock signal must be generated by software to set and reset the port line
49. RR Disabled Capture CT into CP Set CP2FLG 50 86 Set CP2ERR Clear all Flags Software Reset Reload Set CP1FLG Disabled First Capture in CP Disabled Then Reload Set CP1ERR CP2FLG VR02007 4 TIMINGS MEASUREMENT MODES Contd CP2 triggered restart mode with CP2 event de tection This mode RLDSEL1 0 As long as RUNRES bit is set an external event on CP2 pin generates both at first the capture into CP and then the reload from RLCP Capture into CP on CP2 event is enabled only if CP2FLG and CP2ERR are cleared otherwise only reload func tions from RLCP are performed An external event on CP1 activates CP1FLG or CP1ERR flags without any impact on the reload or capture functions is enabled for RLDSEL2 1 and ST62T32B ST62E32B Note After Reset the first CP2 event will capture the 0000h state of the counter into CP and then will restart the counter after loading it from RLCP CP2FLG flag must always be cleared to execute another capture into CP Software triggered restart mode with CP2 event detection This mode is enabled for RLDSEL1 0 RUNRES bit setting initiates the reload and startup of the downcounting while CP2 is used as strobe source for the CT capture into CP register RLDSEL2 0 and Figure 31 CP2 Triggered Restart Mode with CP2 Event Detection Set CP1FLG CP2 First Capture CT into CP Then Reload CT from RLCP Set CP2FLG Set CP1ERR No action Reload CT from
50. T data register Bit 5 RXIEN Receive Interrupt Enable When this bit is set to 1 the receive interrupt is enabled 62 86 Writing to RXIEN does not affect the status of the interrupt flag RXRDY Bit 4 TXIEN Transmit Interrupt Enable When this bitis set to 1 the transmit interrupt is enabled Writing to TXIEN does not affect the status of the interrupt flag TXRDY Bit 3 1 BR2 BRO Baudrate select These bits select the operating baud rate of the UART de pending on the frequency of fOSC Care should be taken not to change these bits during communica tion as writing to these bits has an immediate ef fect Bit 0 DATO Parity Data Bit 9 This bit represents the 9th bit of the data character that is received or transmitted A write to this bit sets the level for the bit 9 to be transmitted so it must always be set to the correct level before transmission If used as parity the value has first to be calculated by soft ware Reading this bit will return the 9th bit of the received character 4 4 6 SERIAL PERIPHERAL INTERFACE SPI The on chip SPI is an optimized serial synchro nous interface that supports a wide range of indus try standard SPI specifications The on chip SPI is controlled by small and simple user software to perform serial data exchange The serial shift clock can be implemented either by software us ing the bit set and bit reset instructions with the on chip Timer 1 by externally connecting the S
51. TOP modes when an inter rupt occurs not a Reset It should be noted that the restart sequence depends on the original state of the MCU normal interrupt or non maskable in terrupt mode prior to entering WAIT or STOP mode as well as on the interrupt type Interrupts do not affect the oscillator selection 3 5 3 1 Normal Mode If the MCU was in the main routine when the WAIT or STOP instruction was executed exit from Stop or Wait mode will occur as soon as an interrupt oc curs the related interrupt routine is executed and on completion the instruction which follows the STOP or WAIT instruction is then executed pro viding no other interrupts are pending 3 5 3 2 Non Maskable Interrupt Mode If the STOP or WAIT instruction has been execut ed during execution of the non maskable interrupt routine the MCU exits from the Stop or Wait mode as soon as an interrupt occurs the instruction which follows the STOP or WAIT instruction is ex ecuted and the MCU remains in non maskable in terrupt mode even if another interrupt has been generated 3 5 3 3 Normal Interrupt Mode If the MCU was in interrupt mode before the STOP or WAIT instruction was execuied it exits from STOP or WAIT mode as soon as an interrupt oc curs Nevertheless two cases must be consid ered If the interrupt is anormal the interrupt rou tine in which the WAIT or STOP mode was en 3 ST62T32B 5 62 2 tered will be completed star
52. This is described in the following para graphs The processor core does not generate a delay following the occurrence of the interrupt be cause the oscillator clock is still available and no stabilisation period is necessary 3 5 2 STOP Mode If the Watchdog is disabled STOP mode is availa ble When in STOP mode the MCU is placed in the lowest power consumption mode In this oper ating mode the microcontroller can be considered as being frozen no instruction is executed the oscillator is stopped the RAM contents and pe ripheral registers are preserved as long as the power supply voltage is higher than the RAM re tention voltage and the ST62xx core waits for the occurrence of an external interrupt request or a Reset to exit the STOP state If the STOP state is exited due to a Reset by acti vating the external pin the MCU will enter a nor mal reset procedure Behaviour in response to in terrupts depends on the state of the processor core prior to issuing the STOP instruction and also on the kind of interrupt request that is gener ated This ease will be described in the following para graphs The processor core generates a delay af ter occurrence of the interrupt request in order to wait for complete stabilisation of the oscillator be fore executing the first instruction 4 POWER SAVING MODE Cont d 3 5 3 Exit from WAIT and STOP Modes The following paragraphs describe how the MCU exits from WAIT and S
53. V Vol D 20 mA Sink VO pins 9 Vbp 5 0V lo 7mA 0 8 P pp 5 0V lo 15 1 8 Vou High Level Output Voltage 5 0V Io 10A 4 9 V All Output pins 5 0V lo 3 0mA 3 5 All Input pins 40 100 200 R ulli Resistance a RESET pin 777924 350 900 __ PU Input Leakage Current Vin No Pull Up configured 0 1 10 lu All Input pins but RESET Vin Vpp Input Leakage Current Vin Vsg 16 30 Supply Current in RESET Vreset Vss 7 TA Mode fosc 8MHz Supply C ti o Supply Currentin STOP 0mA Mode 9 5 0V i Notes 1 Hysteresis voltage between switching levels 2 All peripherals running 3 All peripherals in stand by 40 to 85 C unless otherwise specified 1 Low Level Output Voltage Vpp 5 0V lo 104A 0 1 All Output pins 5 0 lo 5mA 0 8 VoL 1 V 8 lt lt Low Level Output Voltage 5 0V lo 10 20 mA Sink I O pins 5 0V lo 10 5 0V lo 20 High Level Output Voltage 5 0 10 All Output pins Supply Current in STOP Mode lt lt lt lt lt 5 0V lg 5 0mA 3 73 86 ST62T32B ST62E32B 6 4 AC ELECTRICAL CHARACTERISTICS 40 to 125 C unless otherwise specified n Too oem Tee Due Supply Recovery Time 100 Minimum Pulse Width Vpp 5V RESET pin 100
54. WMEN PWM Output Enable This bit en ables the PWM output PWM When 0 the PWM output is disabled if PWMPOL 0 the state of PWM is 0 if PWMPOL 1 the state of PWM 1 The PWM Output is enabled when this bit 1 it must be set to use the PWM output Notes A Masked Compare is the logical AND of the Mask Register MASK with the Counter Register CT compared with the logical AND of the compare Register CMP MASK amp CT MASK amp CMP A Masked Counter Zero is the logical AND of the Mask Register MASK with the Counter Register CT compared with zero 5 amp CT 0000h 3 ST62T32B ST62E32B 4 3 6 16 BIT REGISTERS Note Care must be taken when using single bit instructions RES SET INC DEC 16 bit registers RLCP CP CMP 5 since these instructions imply a READ MODIFY WRITE operation on the register As the ST6 is based on a 8 bit architec ture to write a 16 bit register the high byte must be written first to an intermediate register latch register and the whole 16 bit register is loaded at the same time as the low byte is written A WRITE operation ofthe HIGH byte is performed on the in termediate register latch register but a READ op eration of the HIGH byte is directly performed on the 16 bit register last loaded value As a conse quence it is always mandatory to write the LOW byte before any single bit instruction on the HIGH byte in order to load the value set in the intermedi ate registe
55. Z pcr JRZ 2 JRNZ pcr 2 JRNZ pcr 2 JRNZ pcr 2 JRNZ pcr 2 RNZ pcr JRNC SET JRZ e b6 rr b d per JRNC RES42 JRZ e pcr b d per JRNG SEI JRZ g b1 rr per bid per JRNC RES JRZ b5 rr per b d pcr JRNC SET 2 JRZ e b5 rr per b d per JRNC RES JRZ e b3 rr b d JRNC SET JRZ e b3 rr 2 b d pcr JRNC 4 RES JRZ e b7 rr 2 b d pcr 4 e e e e 2 JRNZ e 2 1 1 1 1 1 1 1 1 1 1 1 e 2 JRNZ pcr 2 JRNZ e 2 JRNZ 1 per e 1 per e 1 per 4 JP abc 2 ext 4 JP abc 2 ext 4 JP abc 2 ext 4 JP abc 2 ext 4 JP abc 2 ext 4 JP abc 2 ext 4 JP abc 2 ext 4 JP abc 2 ext 4 JP abc 2 ext 4 JP abc 2 ext 4 abc 2 ext 4 JP abc 2 ext 4 JP abc 2 ext 4 JP abc 2 ext 4 JP abc 2 ext 4 JP abc 2 ext pcr 2 b d pcr 1 2 JRNZ JRNC SET JRZ 4 e e b7 rr 1 pcr 2 d Abbreviations for Addressing Modes Legend dir Direct Indicates Illegal Instructions sd Short Direct e 5 Bit Displacement imm Immediate b 3 Bit Address inh Inherent Ir 1byte dataspace address ext Extended nn 1 byte immediate data b d Bit Direct abc 12 bit address bt Bit Test ee 8 bit Displacement pcr Program Counter Relative ind Indirect 70 86 Cycle Operand Bytes Addressing Mode prc JRC prc JRC prc URC prc JRC prc JRC prc JRC prc JRC
56. ake an implicit read and write back of the entire register In port input mode however the data register reads from the input pins directly and not from the data regis ter latches Since data register information in input mode is used to set the characteristics of the input pin interrupt pull up analog input these may be unintentionally reprogrammed depending on the state of the input pins As a general rule it is better to limit the use of single bit instructions on data registers to when the whole 8 bit port is in output mode In the case of inputs or of mixed inputs and outputs it is advisable to keep a copy of the data register in RAM Single bit instructions may then be used on the RAM copy after which the whole copy register can be written to the port data regis ter SET bit datacopy LD a datacopy LD DRA a Warning Care must also be taken to not use in structions that act on a whole port register INC DEC or read operations when all 8 bits are not available on the device Unavailable bits must be masked by software AND instruction The WAIT and STOP instructions allow the ST62xx to be used in situations where low power consumption is needed The lowest power con sumption is achieved by configuring I Os in input mode with well defined logic levels The user musttake care not to switch outputs with heavy loads during the conversion of one of the analog inputs in order to avoid any disturbance to th
57. al Watchdog 8 bit A D Converter with 21 analog inputs 8 bit Synchronous Peripheral Interface SPI 8 bit Asynchronous Peripheral Interface UART On chip Clock oscillator can be driven by Quartz Crystal or Ceramic resonator Oscillator Safe Guard One external Non Maskable Interrupt ST623x EMU2 Emulation and Development System connects to an MS DOS PC via a parallel port DEVICE SUMMARY ROM DEVICE Bytes Pins 5762528 7948 September 1998 16 bit AUTO RELOAD TIMER EEPROM SPI AND UART PSDIP42 PQFP52 See end of Datasheet for Ordering Information Rev 2 5 83 86 ST6232B 1 GENERAL DESCRIPTION 1 1 INTRODUCTION The ST6232B is mask programmed ROM version of ST62T32B OTP devices They offer the same functionality as OTP devices selecting as ROM options the options defined in the programmable option byte of the OTP version Figure 1 Programming wave form t VR02001 84 86 1 2 ROM READOUT PROTECTION If the ROM READOUT PROTECTION option is selected a protection fuse can be blown to pre vent any access to the program memory content In case the user wants to blow this fuse high volt age must be applied on the TEST pin Figure 2 Programming Circuit PROTECT LL 414v VR02003 Note ZPD 15is used for overvoltage protection 4 ST6232B ST6232B MICROCONTROLLER OPTION LIST Customer Address Contact Phone No Reference STMicroelectronics references
58. ange it the Watchdog is always active When the software option is se lected the Watchdog function is activated by set ting bit C to 1 and cannot then be disabled save by resetting the MCU When C is kept low the counter can be used as a 7 bit timer This bit is cleared to 0 on Reset Bit 1 SR Software Reset bit This bit triggers a Reset when cleared When C 0 Watchdog disabled it is the MSB of the 7 bit timer This bit is set to 1 on Reset Bits 2 7 T5 T0 Downcounter bits It should be noted that the registerbits are re versed and shifted with respect to the physical counter bit 7 TO is the LSB of Watchdog downcounter and bit 2 15 is the These bits are set to 1 on Reset 3 ST62T32B ST62E32B 3 3 2 Application Notes The Watchdog plays an important supporting role in the high noise immunity of ST62xx devices and should be used wherever possible Watchdog re lated options should be selected on the basis of a trade off between application security and STOP mode availability When STOP mode is not required hardware acti vation without EXTERNAL STOP MODE CON TROL should be preferred as it provides maxi mum security especially during power on When STOP mode is required hardware activa tion and EXTERNAL STOP MODE CONTROL should be chosen NMI should be high by default to allow STOP mode to be entered when the MCU is idle The NMI pin can be connected to an
59. arity is supported by software only for transmit and for checking the received par ity bit bit 9 Transmitted data is sent directly while received data is buffered allowing further data characters to be received while the data is being read out of the receive buffer register Data trans mit has priority over data being received The UART is supplied with an MCU internal clock thatis also available in WAIT mode ofthe processor Figure 35 UART Block Diagram DATA SHIFT DOUT REGISTER D7 D6 D5 D4 D3 D2 D1 DO RECEIVE BUFFER REGISTER LO CONTROL REGISTER BAUD RATE 90 EE PROGRAMMABLE DIVIDER BAUD RATE 8 3 4 5 1 5 RXD reception line and TXD emission line are sharing the same external pins as two 1 lines Therefore UART configuration requires to set these two I O lines through the relevant ports reg isters The I O line common with RXD line must be defined as input mode with or without pull up while the I O line common with TXD line must be defined as output mode Push pull or open drain The transmitted data is inverted and can therefore use a single transistor buffering stage Defined as input the RXD line can be read at any time as an I O line during the UART operation The TXD pin follows I O port registers value when UARTOE bit is cleared which means when no serial transmis sion is in progress As a consequence a perma
60. ary Oscilla tor starts faster than the Main Oscillator It there fore feeds the on chip counter generating the POR delay until the Main Oscillator runs The Low Frequency Auxiliary Oscillator is auto matically switched off as soon as the main oscilla tor starts OSCR Address ODBh 7 0 OSC OFF Bit 7 12 These bits are not used and must be kept cleared after reset Bit 0 OSCOFF Main oscillator turn off When low this bit enables main oscillator to run The main oscillator is switched off when OSCOFF is high Read Write ST62T32B ST62E32B 3 1 3 Oscillator Safe Guard The Oscillator Safe Guard OSG affords drastical ly increased operational integrity in ST62xx devic es The OSG circuit provides three basic func tions it filters spikes from the oscillator lines which would result in over frequency to the ST62 CPU it gives access to the Low Frequency Auxiliary Os cillator LFAO used to ensure minimum process ing in case of main oscillator failure to offer re duced power consumption or to provide a fixed fre quency low cost oscillator finally it automatically limits the internal clock frequency as a function of supply voltage in order to ensure correct opera tion even if the power supply should drop The OSG is enabled or disabled by choosing the relevant OSG option It may be viewed as a filter whose cross over frequency is device dependent Spikes on the oscillator lines result in an effectiv
61. as output through the DDR and OR registers to be used as PWM OVF output of the ARTimer16 All output modes are available PA4 CP1 or 5 2 pins must be configured as input through DDR register to allow CP1 or CP2 triggered input capture of the ARTimer16 All input modes are available and l O s can be read inde pendantly of the ARTimer at any time As long as RLDSEL2 RLDSEL1 bits do not enable CP1 or CP2 triggered capture PA4 CP1 5 2 are standard O s configurable through DDR and OR registers 4 1 4 SPI alternate functions PD2 Sin and PD1 Scl pins must be configured as input through the DDR and OR registers to be 40 86 used as data in and data clock Slave mode for the SPI All input modes are available and 5 can be read independantly of the SPI at any time PD3 Sout must be configured in open drain output mode to be used as data out for the SPI In output mode the value present on the pin is the port data register content only if PD3 is defined as push pull output while serial transmission is possible only in open drain mode 4 1 5 UART alternate functions PD4 RXD1 pin must be configured as input through the DDR and OR registers to be used as reception line for the UART All input modes are available and PD4 can be read independantly of the UART at any time PD5 TXD1 pin must be configured as output through the DDR and OR registers to be used as transmission line for the UART Value prese
62. can be read in the PSC register The control logic device is managed in the TSCR register as described in the following paragraphs The 8 bit counter is decremented by the output rising edge coming from the 7 bit prescaler and can be loaded and read under program control When it decrements to zero then the TMZ Timer Zero bit in the TSCR is set to 1 If the ETI Ena ble Timer Interrupt bit in the TSCR is also set to 17 an interrupt request is generated as described in the Interrupt Chapter The Timer interrupt can be used to exit the MCU from WAIT mode Figure 25 Timer Block Diagram SELECT 1 OF7 3 ST62T32B ST62E32B prescaler input can be the internal frequency divided by 12 or an external clock applied to the TIMER pin The prescaler decrements on the rising edge Depending on the division factor pro grammed by PS2 PS1 and PSO bits in the TSCR The clock input of the timer counter register is mul tiplexed to different sources For division factor 1 the clock input of the prescaler is also that of tim er counter for factor 2 bit 0 of the prescaler regis ter is connected to the clock input of TCR This bit changes its state at half the frequency of the pres caler input clock For factor 4 bit 1 of the PSC is connected to the clock input of TCR and so forth The prescaler initialize bit PSI in the TSCR regis ter must be set to 1 to allow the prescaler and hence the counter to start
63. ccurs the flags ZEROFLG and COMPFLG are respectively set By using MASK values reported in Table 17 the MASK register works as counter frequency multi plier for the compare functions In that case posi tive masked comparison occur with a period of 21 x Psc x Telk where n is the position of the most significant bit of MASK value Table 17 Recommended Mask Values FFFFh 011357 19471111 1111 00111111 1111 1111 0001 1111 1111 1111 0000 1111 1111 1111 0000 0000 0000 0111 0000 0000 0000 001 1 0000 0000 0000 0001 gives a period equal riod x Figure 28 Flags Setting in Compare and Reload Functions Counter Value CT x ZEROFLG Software Reset OVFFLG _ ae Software Reset M M COMPFLG 3 Software Reset 47 86 ST62T32B ST62E32B CENTRAL COUNTER Cont d 4 3 1 3 Capture functions Content of the counter CT can always be down loaded captured into the CP register at selecta ble event occurrence on pins CP1 and CP2 while capture in RLCP is possible only when the bit RELOAD is cleared Capture functions with RELOAD cleared are used for period or pulse width measurements with input CP2 or for phase measurements between two signals on CP1 and CP2 with the counter in free running mode In these modes counter values by the two events occurence are stored into RLCP and CP and the counter remains in free running mode Capture functions w
64. ce the last clear of this flag If the bit is at 1 the first CP2 event and capture into CP has occurred This bit cannot be set by program only cleared Bit 4 CMPIEN Compare Int Enable The Com pare Interrupt is masked when this bit is O Setting the bit to 1 enables the Compare flag CMPFLG to set the ARTIMER interrupt Bit 3 CMPFLG Compare Flag When this bit is 0 no Masked Compare True event has occurred since the last clear of this flag f bit is at 1 a 54 86 Masked Compare event has occurred This bit cannot be set by program only cleared Bit 2 ZEROIEN Compare to Zero Int Enable The Masked Counter Zero Interrupt is masked when this bit is 0 Setting the bit to 1 enables the ZEROFLG flag to set the ARTIMER interrupt Bit 1 ZEROFLG Compare to Zero Flag When this bit is 0 no Masked Counter Zero event has occurred since the last clear of this flag If the bit is at 1 a Masked Counter Zero event has occurred as the Masked Counter state equals 0 when run ning or on hold not on Reset Bit 0 PWMMD PWM Output Mode Control The PWM Output mode is set by this bit when 0 the PWM output is run in set reset mode the PWM output is set on a Masked Counter Zero event and is reset when on a Masked Compare event When 1 the PWM output is in toggle mode PWM toggles its state on every Masked Compare event Notes A Masked Compare is the logical AND of the Mask Register MASK with the Counter Register
65. contained in the op code Short direct addressing is a subset of the di rect addressing mode Note that 80h and 81h are also indirect registers Extended In the extended addressing mode the 12 bit address needed to define the instruction is obtained by concatenating the four less significant ky ST62T32B ST62E32B bits of the opcode with the byte following the op code The instructions JP CALL which use the extended addressing mode are able to branch to any address of the 4K bytes Program space An extended addressing mode instruction is two byte long Program Counter Relative The relative address ing mode is only used in conditional branch in structions The instruction is used to perform a test and if the condition is true a branch with a span of 15 to 16 locations around the address of the rel ative instruction If the condition is not true the in struction which follows the relative instruction is executed The relative addressing mode instruc tion is one byte long The opcode is obtained in adding the three most significant bits which char acterize the kind of the test one bit which deter mines whether the branch is a forward when it is 0 or backward when it is 1 branch and the four less significant bits which give the span of the branch Oh to Fh which must be added or sub tracted to the address of the relative instruction to obtain the address of the branch Bit Direct In the bit direct addressin
66. ctors and common subrou tines independently of the PRPR register content This STATIC page is directly addressed in the 0800h OFFFh by the MSB of the Program Counter register PC 11 Note this page can also be ad dressed in the 000 7FFh range It is two different ways of addressing the same physical memory Jump from a dynamic page to another dynamic page is achieved by jumping back to the static page changing contents of PRPR and then jump ing to the new dynamic page Figure 4 8Kbytes Program Space Addressing ROM SPACE PC SPACE 0000h Page 1 Page 0 Static Page 2 Page 3 Page DATA SPACE RAM EEPROM BANKING AREA DATA READ ONLY EMORY WINDOW X REGISTER Y REGISTER V REGISTER W REGISTER DATA READ ONLY MEMORY WINDOW SELECT DATA RAM BANK SELECT ACCUMULATOR VR01568 4 MEMORY MAP Cont d Table 1 ST62E32B T32B Program Memory ROM Page Device Address 0 0000h 007Fh Reserved 9 0080h 07FFh User ROM 0800h 0F9Fh User ROM OFAOh 0FEFh Reserved OFFOh OFF7h Interrupt Vectors OFF8h OFFBh Reserved NMI Vector Reset Vector 0000h 000Fh Reserved Panda 3 0000h 000Fh Reserved 9 0010h 07FFh User ROM Note OTP EPROM devices can be programmed with the development tools available from STMicro electronics ST62E3X EPB ST623X KIT Page 1 STATIC OFFCh OFFDh OFFEh OFFFh 1 3 2 1 Program ROM Page Register PRPR The PRPR register can be addressed like
67. e while in PMODE up to 8 bytes in the same row are programmed simultaneously with conse quent speed and power consumption advantages the latter being particularly important in battery powered circuits General Notes Data should be written directly to the intended dress in EEPROM space There is no buffer mem ory between data RAM and the EEPROM space When the EEPROM is busy E2BUSY 1 EECTL cannot be accessed in write mode it is only possible to read the status of E2BUSY This implies that as long as the EEPROM is busy it is not possible to change the status of the EEPROM Control Register EECTL bits 4 and 5 are reserved and must never be set Care is required when dealing with the EECTL reg ister as some bits are write only For this reason the EECTL contents must not be altered while ex ecuting an interrupt Service routine If it is impossible to avoid writing to this register within interrupt service routine an image of the register must be saved in a RAM location and each time ihe program writes to EECTL it must also write to the image register The image register must be written to first so that if an interrupt oc curs between the two instructions the EECTL will not be affected Table 6 Row Arrangement for Parallel Writing of EEPROM Locations Dataspace addresses Banks 0 and 1 38h 3Fh 30h 37h 28h 2Fh 20h 27h 18h 1Fh 10h 17h 08h OFh 00h 07h Up to 8 bytes in each row may be pro
68. e I O pin is selected as an analog input si multaneously to avoid device malfunction The ADC uses two registers in the data space the ADC data conversion register ADR which stores the conversion result and the ADC control regis ter ADCR used to program the ADC functions A conversion is started by writing a 1 tothe Start bit STA in the ADC control register This auto matically clears resets to O the End sion Bit EOC When a conversion is complete the EOC bit is automatically set to 1 1 order to flag that conversion is complete and that the data in the ADC data conversion register is valid Each conversion has to be separately initiated by writing to the STA bit The STA bit is continuously scanned so that if the user sets it to 1 while a previous conversion is in progress a new conversion is started before com pleting the previous one The start bit STA is a write only bit any attempt to read it will show a log ical O The A D converter features a maskable interrupt associated with the end of conversion The inter rupt request occurs when the bit is set i e when a conversion is completed The interrupt is masked using the EAI interrupt mask bit in the control register The power consumption of the device can be re duced by turning off the ADC peripheral This is done by setting the PDS bit in the ADC control reg ister to 0 If PDS 1 the A
69. e conversiom Figure 23 Diagram showing Safe I O State Transitions Interrupt pull up Reset state Output Open Drain Push pull Note xxx DDR OR DR Bits respectively 38 86 Push pull 4 ST62T32B ST62E32B PORTS Table 14 1 O Port configuration for the ST62T32B E32B AVAILABLE SCHEMATIC PAO PA7 Input PB3 PB7 Reset state if PORT 5 7 PULL option disabled PDO PD7 4 PAO PA7 Input PBO PB3 PB7 R EST Data in eset state i PULL option enabled 7 4 o Interrupt PAO PA7 Input PBO PB3 PB7 with pull up PC5 PC7 with interrupt PDO PD7 4 Data in Interrupt PA4 PA7 PBO PB3 PB7 PC5 PC7 PDO PD7 Analog Input Open drain output PA4 PA7 5mA PBO PB3 PB7 PC5 PC7 PDO PD7 Open drain output PAO PA3 20mA 4 Push pull output PA4 PA7 5mA PBO PB3 PB7 PC5 PC7 PDO PD7 Push pull output 20 4 019924 Note 1 Provided the correct configuration has been selected 1574 39 86 ST62T32B ST62E32B PORTS 4 1 3 ARTimer alternate functions As long as PWMEN resp OVFEN bit is kept low the PA3 PWM resp PA2 OVF pin is used as standard I O pin and therefore can be configured in any mode through the DDR and OR registers If PWMEN resp OVFEN bitis set PA3 PWM re sp PA2 OVF pin must be configured
70. e pages are enabled in parallel pr ducimg errors Table 5 Data RAM Bank Register Set up P Nn EEPROMPA o 08 RAM Page 1 10h RAM Page 2 4 1 3 7 EEPROM Description EEPROM memory is located in 64 byte pages in data space This memory may be used by the user program for non volatile data storage Data space from to 3Fh is paged as described in Table 6 EEPROM locations are accessed di rectly by addressing these paged sections of data space The EEPROM does not require dedicated instruc tions for read or write access Once selected via the Data RAM Bank Register the active EEPROM page is controlled by the EEPROM Control Regis ter EECTL which is described below Bit E20FF of the EECTL register must be reset prior to any write or read access to the EEPROM If no bank has been selected or if is set any ac cess is meaningless Programming must be enabled by setting the E2ENA bit of the EECTL register The E2BUSY bit of the EECTL register is set when the EEPROM is performing a programming cycle Any access to the EEPROM when E2BUSY is set is meaningless Provided E2OFF and E2BUSY are reset an EEP ROM location is read just like any other data loca tion also in terms of access time Writing to the EEPROM may be carried out in two modes Byte Mode BMODE and Paralle Mode ST62T32B ST62E32B PMODE In BMODE one byte is accessed at a tim
71. each pin to be set The Option registers ORx are used to select the different port options available both in input and in output mode All registers can be read or written to just as any other RAM location in Data space so no extra RAM cells are needed for port data storage and manipulation During MCU initialization all I O reg isters are cleared and the input mode with pull ups and nosinterrupt generation is selected for all the pins thus avoidingepin conflicts INPUT OUTP UT VA00413 4 PORTS 4 1 1 Operating Modes Each pin may be individually programmed as input or output with various configurations This is achieved by writing the relevant bit in the Data DR Data Direction DDR and Option reg isters OR Table 13 illustrates the various port configurations which can be selected by user soft ware 4 1 1 1 Input Options Pull up High Impedance Option All input lines can be individually programmed with or without an internal pull up by programming the OR and DR registers accordingly If the pull up option is not selected the input pin will be in the high imped ance state Table 13 1 Port Option Selection ST62T32B ST62E32B 4 1 1 2 Interrupt Options All input lines can be individually connected by software to the interrupt system by programming the OR and DR registers accordingly The inter rupt trigger modes falling edge rising edge and low level can be configured b
72. egister OD6h 24 86 4 3 3 DIGITAL WATCHDOG The digital Watchdog consists of a reloadable downcounter timer which can be used to provide controlled recovery from software upsets The Watchdog circuit generates a Reset when the downcounter reaches zero User software can prevent this reset by reloading the counter and should therefore be written so that the counter is regularly reloaded while the user program runs correctly In the event of a software mishap usual ly caused by externally generated interference the user program will no longer behave in its usual fashion and the timer register will thus not be re loaded periodically Consequently the timer will decrement down to 00h and reset the MCU In or der to maximise the effectiveness of the Watchdog function user software must be written with this concept in mind Watchdog behaviour is governed by two options known as WATCHDOG ACTIVATION HARDWARE or SOFTWARE and EXTERNAL STOP MODE CONTROL see Table 8 In the SOFTWARE option the Watchdog is disa bled until bit C of the DWDR register has been set Table 8 Recommended Option Choices Functions Required Recommended Options Stop Mode amp Watchdog EXTERNAL STOP MODE amp HARDWARE WATCHDOG ST62T32B ST62E32B When the Watchdog is disabled low power Stop mode is available Once activated the Watchdog cannot be disabled except by resetting the MCU In the HARDWARE option the Wa
73. ely increased internal clock frequency In the absence of an OSG circuit this may lead to an over fre quency for a given power supply voltage The OSG filters outssuch spikes as illustrated in Fig ure 10 In all cases when the OSG is active the maximum internal clock frequency fyr is limited which is supply voltage dependent This relationship is illustrated in Figure 13 Whenethe OSG is enabled the Low Frequency Auxiliary Oscillator may be accessed This oscilla tor starts operating after the first missing edge of the main oscillator see Figure 11 Over frequency at a given power supply level is seen by the OSG as spikes it therefore filters out some cycles in order that the internal clock fre quency of the device is kept within the range the particular device can stand depending on V5p and below fosa the maximum authorised frequen cy with OSG enabled Note The OSG should be used wherever possible as it provides maximum safety Care must be tak en however as it can increase power consump tion and reduce the maximum operating frequency to fosa 19 86 ST62T32B ST62E32B CLOCK SYSTEM Figure 10 OSG Filtering Principle Maximum Frequency for the device correctly Actual Quartz Crystal Frequency at OSCin pin Noise from OSCin Resulting Interna Frequency Figure 11 OSG Emergency Oscillator Principle Main Oscillator Emergency Oscillator Internal Fre
74. ent level the oscillator starts to operate whereupon an internal delay is initiated in order to allow the oscillator to fully stabilize before executing the first instruction The initialization sequence is executed immediate ly following the internal delay 22 86 The internal delay is generated by an on chip coun ter The internal reset line is released 2048 internal clock cycles after release of the external reset Notes To ensure correct start up the user should take care that the reset signal is not released before the Vpp level is sufficient to allow MCU operation at the chosen frequency see Recommended Oper ating Conditions A proper reset signal for a slow rising supply can generally be provided by an external RC net work connected to the pin Figure 14 Reset and Interrupt Processing MASK SET INT LATCH CLEARED IFPRESENT SELECT NMI MODE FLAGS PUT FFEH ON ADDRESS BUS S RESET STIL PRESENT LOAD PC FROM RESET LOCATIONS FFE F FF FETCH INSTRUCTION VA000427 4 RESETS 3 2 3 Watchdog Reset The MCU provides a Watchdog timer function in order to ensure graceful recovery from software upsets If the Watchdog register is not refreshed before an end of count condition is reached the internal reset will be activated This amongst oth er things resets the watchdog counter The MCU restarts just as though the Reset had been generated by the RESET pin including t
75. es must be set to FFh The selected options are communicated to STMi croelectronics using the correctly filled OPTION LIST appended 1 2 2 Listing Generation and Verification When STMicroelectronics receives ihe users ROM contents a computer listing is generated Table 2 FASTROM version Ordering Information from it This listing refers exactly to the ROM con tents and options which will be used to produce the specified MCU The listing is then returned to the customer who must thoroughly check com plete sign and return it to STMicroelectronics The signed listing forms a part of the contractual agree V for the production of the specific customer The STMicroelectronics Sales Organization will be pleased to provide detailed information on con tractual points Table 1 ROM Memory Map for ST62P32B 0000h 007Fh Reserved 0800h 0F9Fh User ROM OFAOh OFEFh Reserved OFFOh OFF7h Interrupt Vectors OFF8h OFFBh Reserved OFFCh QFFDh NMI Vector OFFER OFFFh Reset Vector Q000h 000Fh Reserved Q000h 000Fh Reserved Page 1 STATIC 0010h 07FFh Sales Type 7 ROW Temperature Range ST62P32BB1 XXX ST62P32BB6 XXX ST62P32BB3 XXX ST62P32BQ1 XXX ST62P32BQ6 XXX ST62P32BQ3 XXX Advanced information 80 86 0 to 70 C 40 to 85 C 40 to 125 C 0 to 70 C 40 to 85 C 40 to 125 C SDIP42 PQFP52 4 ST62P32B ST62P32B FASTROMMICROCONTROLLER OPTION LIST Customer Address
76. et the MCU internal state and ensure a correct start up procedure The pin is active low and features a Schmitt trigger input The internal Reset signal is generated by adding a delay to the external signal Therefore even short pulses on the RESET pin are acceptable provided V5p has completed its rising phase and that the oscillator is running correctly normal RUN or WAIT modes The MCU is kept in the Reset state as long as the RESET pin is held low If RESET activation occurs in the RUN or WAIT modes processing of the user program is stopped RUN mode only the Inputs and Outputs are con figured as inputs with pull up resistors and the main Oscillator is restarted When the level on the RESET pin then goes high the initializationsse quence is executed following expiry of the internal delay period If RESET pin activation occurs inthe STOP mode the oscillator starts up and ail Inputs and Outputs are configured as inputs with pull up resistors When the level of the RESET pin then goes high the initialization sequence is executed following expiry of the internal delay period 3 2 2 Power on Reset The function of the POR circuit consists in waking up the MCU at an appropriate stage during the power on sequence At the beginning of this se quence the MCU is configured in the Reset state all I O ports are configured as inputs with pull up resistors and no instruction is executed When the power supply voltage rises to a suffici
77. g mode the bit to be set or cleared is part of the opcode and the byte following the opcode points to the ad dress of the byte in which the specified bit must be set or cleared Thus any bit in the 256 locations of Data space memory can be set or cleared Bit Test amp Branch The bit test and branch ad dressing mode is a combination of direct address ing and relative addressing The bit test and branch instruction is three byte long The bit iden tification and the tested condition are included in the opcode byte The address of the byte to be tested follows immediately the opcode in the Pro gram space The third byte is the jump displace ment which is in the range of 127 to 128 This displacement can be determined using a label which is converted by the assembler Indirect In the indirect addressing mode the byte processed by the register indirect instruction is at the address pointed by the content of one of the in direct registers X or Y 80h 81h The indirect reg ister is selected by the bit 4 of the opcode A regis ter indirect instruction is one byte long Inherent In the inherent addressing mode all the information necessary to execute the instruction is contained in the opcode These instructions are one byte long 65 86 ST62T32B ST62bE32B 5 3 INSTRUCTION SET The ST6 core offers a set of 40 basic instructions which when combined with nine addressing modes yield 244 usable opcodes They can be di
78. gister The SR bit must be set to 1 since it is this bit which gen erates the Reset signal when it changes to 0 clearing this bit would generate an immediate Re set It should be noted that the order of the bits in the DWDR register is inverted with respect to the as sociated bits in the down counter bit 7 of the DWDR register corresponds in fact to TO and bit 2 to T5 The user should bear in mind the fact that these bits are inverted and shifted with respect to the physical counter bits when writing to this regis ter The relationship between the DWDR register bits and the physical implementation of the Watch dog timer downcounter is illustrated in Figure 17 Only the 6 most significant bits may be used to de fine the time period since it is bit 6 which triggers the Reset when it changes to 0 This offers the user a choice of 64 timed periods ranging from 3 072 to 196 608 clock cycles with an oscillator frequency of 8MHz this is equivalent to timer peri ods ranging from 3844540 24 576ms 26 86 Figure 17 Watchdog Counter Control oc E 2 I O lt WATCHDOG COUNTER VR02068A 4 DIGITAL WATCHDOG Cont d 3 3 1 Digital Watchdog Register DWDR Address OD8h Read Write Reset status 1111 1110b 0 Bit 0 C Watchdog Control bit If the hardware option is selected this bit is forced high and the user cannot ch
79. grammed simultaneously in Parallel Write mode The number of available 64 byte banks 1 or 2 is device dependent 13 86 ST62T32B ST62E32B MEMORY MAP Cont d Additional Notes on Parallel Mode If the user wishes to perform parallel program ming the first step should be to set the E2PAR2 bit From this time on the EEPROM will be ad dressed in write mode the ROW address will be latched and it will be possible to change it only at the end of the programming cycle or by resetting E2PAR2 without programming the EEPROM Af ter the ROW address is latched the MCU can only see the selected EEPROM row and any attempt to write or read other rows will produce errors The EEPROM should not be read while E2PAR2 is set As soon as the E2PAR2 bit is set the 8 volatile ROW latches are cleared From this moment on the user can load data in all or in part ofthe ROW Setting E2PAR1 will modify the EEPROM regis ters corresponding to the ROW latches accessed after E2PAR2 For example if the software sets E2PAR2 and accesses the EEPROM by writing to addresses 18h 1Ah and 1Bh and then sets E2PAR1 these three registers will be modified si multaneously the remaining bytes in the row will be unaffected Note that E2PAR2 is internally reset at the end of the programming cycle This implies that the user must set the 2 2 bit between two parallel pro gramming cycles Note that if the user tries to set E2PAR1 while 2
80. he built in stabilisation delay period 3 2 4 Application Notes No external resistor is required between and the Reset pin thanks to the built in pull up device The POR circuit operates dynamically in that it triggers MCU initialization on detecting the rising edge of Vpp The typical threshold is in the region of 2 volts but the actual value of the detected threshold depends on the way in which Vp rises The POR circuit is NOT designed to supervise static or slowly rising or falling V5p 3 2 5 MCU Initialization Sequence When reset occurs the stack is reset the is loaded with the address of the Reset Vector ed in program ROM starting at address OFFER A jump to the beginning of the user program must be coded at this address Following a Reset the In terrupt flag is automatically set so that the CPU is in Non Maskable Interrupt mode this prevents the Figure 16 Reset Block Diagram 2 8kQ POWER ON RESET WATCHDOG RESET 3 ST62T32B ST62E32B initialisation routine from being interrupted The in itialisation routine should therefore be terminated by a RETI instruction in order to revert to normal mode and enable interrupts If no pending interrupt is present at the end of the initialisation routine the MCU will continue by processing the instruction immediately following the RETI instruction If how ever a pending interrupt is present it will be serv iced Figure 15 Reset a
81. he Oscillator Safeguard OSG option filters spikes from the oscillator lines provides access to the LFAO to provide a backup oscillator in the event of main oscillator failure and also automati cally limits the internal clock frequency as a function of Vpp in order to guarantee correct oper ation These functions are illustrated in Figure 10 Figure 11 Figure 12and Figure 13 Figure 9 illustrates various possible oscillator con figurations using an external crystal or ceramic res onator an external clock input or the lowest cost so lution using only the LFAO Q should have acapacitance intherange 12to22 pF foranoscillator frequency in the 4 8 MHz range The internal MCU clock frequency is divided by 12 to drive the Timer and the Watchdog timer and by 13 to drive the CPU core while the A D converter is driven by fy divided either by 6 or by 12 as may be seen in Figure 12 With an 8MHz oscillator frequency the fastest ma chine cycle is therefore 1 6255 A machine cycle is the smallest unit of time needed to execute any operation for instance to increment the Program Counter An instruction may require two four or five machine cycles for execution 3 1 1 Main Oscillator The main oscillator can be turned off when the OSG ENABLED option is selected by setting the OSCOFF bit of the OSCR Control Register The Low Frequency Auxiliary Oscillator is automatical ly started 18 86 Figure 9 Osc
82. he rest of the chip using these two pins OSCin and OSCout These pins are internally connected to the on chip oscillator circuit A quartz crystal a ceramic resonator or an external clock signal can be connected between these two pins The OSCin pin is the input pin the OSCout pin is the output pin RESET The active low RESET pin is used to re start the microcontroller TEST Vpp The TEST must be held at Va for nor mal operation If TEST pin is connected to a 12 5V level during the reset phase the EPROM OTP programming Mode is entered NMI The NMI pin provides the capability for asyn chronous interruption by applying an exiernal non maskable interrupt to the MCU ThesNM input is falling edge sensitive with Schmitt trigger charac teristics The user can selecivas option the availa bility of an on chip pull up at this pin PAO PAT These 8 lines are organised as one I O port A Each line may be configured under soft ware control as inputs with or without internal pull up resistors interrupt generating inputs with pull up resistors open drain or push pull outputs PA2 OVF PA3 PWM PA4 CP1 and 2 be used respectively as overflow output pin output compare pin and as two input capture pins for the embedded 16 bit Auto Reload Timer 3 ST62T32B ST62bE32B In addition PA4 PA5 can also be used as analog inputs for the A D converter while PAO PAS can sink 20mA for direct LED or TRIAC drive PBO
83. illator Configurations CRYSTAL RESONATOR CLOCK ST6xxx OSCin OSCout EXTERNAL CLOCK ST6xxx OSC OSCout a INTEGRATE D CLOCK OSG ENABLED option ST6xxx OSC OS VA0016 VA0015A 4 CLOCK SYSTEM Cont d Turning on the main oscillator is achieved by re setting the OSCOFF bit of the OSCR Register or by resetting the MCU Restarting the main oscilla tor implies a delay comprising the oscillator start up delay period plus the duration of the software instruction at clock frequency 3 1 2 Low Frequency Auxiliary Oscillator LFAO The Low Frequency Auxiliary Oscillator has three main purposes Firstly it can be used to reduce power consumption in non timing critical routines Secondly it offers a fully integrated system clock without any external components Lastly it acts as a safety oscillator in case of main oscillator failure This oscillator is available when the OSG ENA BLED option is selected In this case it automati cally starts one of its periods after the first missing edge from the main oscillator whatever the reason main oscillator defective no clock circuitry provid ed main oscillator switched off User code normal interrupts WAIT and STOP in structions are processed as normal at the re duced 1 frequency The A D converter accura Cy is decreased since the internal frequency is be low 1MHz At power on the Low Frequency Auxili
84. individually programmed as any of the following input or output configurations Input without pull up or interrupt Input with pull up and interrupt Input with pull up but without interrupt Analog input Push pull output Open drain output The lines are organised as bytewise Ports Each port is associated with 3 registers in Data space Each bit of these registers is associated with a particular line for instance bits 0 of Port A Data Direction and Option registers are associat ed with the PAO line of Port A The DATA registers DRx are used to read the voltage level values of the lines which have been configured as inputs or to write the logic value of the signal to be output on the lines configured as outputs The port data registers can be read to get the effective logic levels of the pins but they Figure 22 I O Port Block Diagram Si CONTROLS DATA DIRECTION REGISTER REGISTER X Sou T TO INTERRUPT TO ADC 36 86 be also written by user software in conjunction with the related option registers to select the dif ferent input mode options Single bit operations on I O registers are possible but care is necessary because reading in input mode is done from I O pins while writing will direct ly affect the Port data register causing an unde sired change of the input configuration The Data Direction registers DDRx allow the data direction input or output of
85. is kept within the specification 71 86 ST62T32B ST62E32B 6 2 RECOMMENDED OPERATING CONDITIONS 6 Suffix Version TA 1 Suffix Version 3 Suffix Version Operating Supply Voltage Vpp 4 5V 1 amp 6 Suffix Vpp 4 5V Suffix Internal Frequency with OSG Vpp 2 fosc Pin Injection Current positive Vpp 4 5 to 5 5V 5 Pin Injection Current negative Vpp 4 510 5 5V Notes 1 Care mustbe taken in case of negative current injection where adapted impedance must be respected on analog sources to not affect the A D conversion For a 1 injection a maximum 10 is recommended 2 An oscillator frequency above 1MHz is recommended for reliable A D results Figure 40 Maximum Operating Frequency Fia versus Supply Voltage V5 Maximum FREQUENCY MHz FUNCTIONALITY 15 NOT GUARANTEED IN THIS AREA 1 amp 6 Suffix Version 3 Suffix Version SUPPLY VOLTAGE The shaded area is outside the recommended operating range device functionality is not guaranteed under these conditions 4 72 86 ST62T32B ST62E32B 6 3 DC ELECTRICAL CHARACTERISTICS TA 40 to 125 C unless otherwise specified Sm Vi Input Low Level Voltage All Input pins Vin Input High Level Voltage All Input pins Hysteresis Voltage 7 0 2 Hys All Input pins D 0 2 Low Level Output Voltage Vpp 5 0V lo 104A 0 1 All Output pins 5 0V lo 0 8 VoL 5 0 1
86. ith RELOAD set are used for same application purpose but in that case the first event reloads the counter from RLCP while the second event captures the counter content into the CP register Therefore the counter is not in free running mode for other functions since the down counting start is initiated by either CP1 CP2 or RUNRES event according to RLDSEL1 and RLDSEL2 bit 4 3 2 SIGNAL GENERATION MODES 4 3 2 1 Output modes Any positive comparison to 0000h MASK amp CMP and any overflow occurerice can be used to control the OVF or PWM output pins in various modes defined by bits OVFM D PWMPOL PWMEN and PWMMD PWM pin output modes MASIE ONE x x no es yes X 0000h y y MASK amp CT 5 MASK amp CMP per 9 Pano pep 9 Reset Set Set Reset roog e Table 18 Achievable periods on PWM pin OVF pin output modes Zero overflow OVFFLG OVFMD OVF pin HL ae OVF pin is reset by clearing the flag OVF 4 3 2 2 Frequency and duty cycles on PWM pins In Set Reset mode PWMMD 0 the period the PWM pin is the time between two matched masked comparison to 0000h at which PWM pin is set PWMPOL 1 or reset PWMPOL 0 As long as no reload function from RLCP is performed RELOAD bit cleared and no mask is used this value is 2 x x Tclk If on the contrary reload function or a mask are used
87. k where is the prescaler ratio and Tclk the period of the main oscillator This down counter is stopped and its content kept cleared as long as RUNRES bit is cleared 4 3 1 1 Reload functions The 16 bit down counter can be reloaded 3 differ ent ways At a zero overflow occurrence with the bit RELOAD cleared The counter is reloaded to FFFFh At a zero overflow occurrence with the bit RELOAD set The counter is reloaded with the val ue programmed in the RLCP register For each overflow the transition between 0000h and the re load value RLCP or FFFFh is flagged through the OVFFLG bit At an external event on pin CP1 or CP2 with the bit RELOAD set The counter is reloaded with the val ue programmed in the RLCP register As a consequence the time between a timer load and a zero overflow occurrence depends on the value in RLCP when RELOAD bit is This time is equal to RLCP 1 x Psc x when RELOAD bit is set while it is 2 x when RELOAD bit is cleared ST62T32B ST62E32B 4 3 1 2 Compare functions The value in the counter CT is continuously com pared to 0000h and to the value programmed into the Compare Register CMP The comparison range to 0000h and CMP is defined by using the MASK register to select which bits are used there fore the comparisons performed are MASK amp CT 2 MASK amp CMP MASK amp CT 2 0000h When a matched comparison to 0000h or MASK amp CMP o
88. la 6 5us 9 x Cag x ASI capacitor charged to over 99 9 i e 30 in cluding 5095 guardband ASI can be higher if has been charged for a longer period by adding in structions before the start of conversion adding more than 26 CPU cycles is pointless 57 86 ST62T32B ST62E32B A D CONVERTER Cont d Since the ADC is on the same chip as the micro processor the user should not switch heavily load ed output signals during conversion if high preci sion is required Such switching will affect the sup ply voltages used as analog references The accuracy of the conversion depends on the quality of the power supplies and Vss The user must take special care to ensure a well regu lated reference voltage is present on the V5p Vss pins power supply voltage variations must be less than 5V ms This implies in particular that a suitable decoupling capacitor is used at the V5p pin The converter resolution is given by Vop Ves 256 The Input voltage Ain which is to be converted must be constant for 145 before conversion and remain constant during conversion Conversion resolution can be improved if the pow er supply voltage Vpp to the microcontroller is lowered In order to optimise conversion resolution the user can configure the microcontroller in WAIT mode because this mode minimises noise disturbances and power supply variations due to output switch ing Nevertheless the WAIT i
89. leared Bit 1 OVFMD The Overflow Output mode is set by this bit when 0 the overflow output is run in set mode OVF will be set on the first overflow event and will be reset when OVFFLG is cleared When 1 the overflow output is in toggle mode OVF tog gles its state on every overflow event independ ent to the state of OVFFLG ky ST62T32B ST62E32B Bit 0 This bit is reserved and must be set to 0 Status Control Register 2 SCR2 Address E1h Read Write Clear only 7 0 CP2ERR CP1FLG CP1POL RLDSED2 RLDSEL1 Bit 7 Reserved Must be kept cleared Bit 6 CP1ERR Error Flag This bit is set to 1 if a new CP1 event has taken place since CP1FLG was set to signal an error condition it is 0 if there has been no event It is recommended to clear CP1ERR at any time that CP1FLG is cleared as further CP1 events cannot be recognised if CP1ERR is set This bit cannot bet set by write only cleared Bit 5 CP2ERR CP7 Error Flag This bit is set to 1 if a new CP2 event has taken place since CP2FLG was set to signal an error condition it is 0 if there has been no event It is recommended 10 clear CP2ERR at any time that CP2FLG 15 cleared as further CP2 events cannot be recognised if CP2ERR is set This bit Set write only cleared 4 CPAIEN CP1 Interrupt Enable CP1 The Capture Interrupt is masked when this bit is 0 Setting the bit to 1 enables the CP1 e
90. led The Option byte is written during programming ei ther by using the PC menu PC driven Mode or automatically stand alone mode 1 4 2 Program Memory EPROM OTP programming mode is set by a 12 5V voltage applied to the TEST Vep pin The programming flow of the ST62T32B E32B is de scribed in the User Manual of the EPROM Pro gramming Board The MCUs can be programmed with the ST62E3xB EPROM programming tools available from STMicroelectronics 1 4 3 EEPROM Data Memory EEPROM data pages are supplied in the virgin state FFh Partial or total programming of EEP ROM data memory be performed either through the application software or through an ex ternal programmer Any STMicroelectronics tool used forthe program memory OTP EPROM can also be tused to program the EEPROM data mem ory 1 4 4 EPROM Erasing The EPROM of the windowed package of the MCUs may be erased by exposure to Ultra Violet light The erasure characteristic of the MCUs is such that erasure begins when the memory is ex posed to light with a wave lengths shorter than ap proximately 4000 It should be noted that sun lights and some types of fluorescent lamps have wavelengths in the range 3000 4000A It is thus recommended that the window of the MCUS packages be covered by an opaque label to prevent unintentional erasure problems when test ing the application in such an environment The recommended erasure procedure of the MCUs EPROM is the e
91. less otherwise specified Value Symbol mbol Parameter Test Conditions En m nit Symbol CF T Ta 75 86 ST62T32B ST62E32B 7 GENERAL INFORMATION 7 1 PACKAGE MECHANICAL DATA Figure 41 42 Pin Plastic Shrink Dual In Line Package mm f Tuae EX 26 bo sos 57 re 1046 0 roe 023 race nero ors ssss ases oe 1 aao aso aen 0650 Er 276 a2 ran ooo sso o 57o re fale red T pon Ce je ee Pec Ez ise pow 0 PDiPazs pa pens so oco rso o 40 w 4 Figure 42 52 Pin Plastic Quad Flat Package mm bo as Tre Tue i CT T TL es pee T 25s 20 30s ooo op os osofooral Te os ozs pos esso prae poser rer p ee br rsso rao revo oser ss sss feof pessprraoprras oser per e er raso rao vo Joser ss sss pe pel I oss oss ooze ias pos PQFP52 Number of Pins wf 9 76 86 ST62T32B ST62E32B PACKAGE MECHANICAL DATA Figure 43 42 Pin Ceramic Shrink Dual In Line Package mm inches Di Fs Te Tu
92. low down the SCL as long as it is needed to carry out data from the shift register C bus Master Slave Receiver Transmitter When pins Sin and Sout are exiernally connected together itis possible to usethe SPI as a receiver as well as a transmitter Through software routine by using bit set and bit reset on line a clock can be generated allowing C bus to work in mas ter mode When implementing an C bus protocol the start condition can be detected by setting the processor into a wait for start condition by enabling the inter rupt of the I O port used for the Sin line This frees the processor from polling the Sin and SCL lines After the transmission reception the processor has to poll for the STOP condition In slave mode the user software can slow down the SCL clock frequency by simply putting the SCL I O line in output open drain mode and writing a zero into the corresponding data register bit 64 86 As it is possible to directly read the Sin pin directly through the port register the software can detect a difference between internal data and external data master mode Similar condition can be applied to the clock Three Four Wire Serial Bus It is possible to use a single general purpose pin with the corresponding interrupt enabled as a chip enable pin SCL acts as active or passive clock pin Sin as data in and Sout as data out four wire bus Sin and Sout can be connected together externally t
93. nd Interrupt Processing JP 2 5 4 CYCLES VECTOR INITIALIZATION ROUTINE RETI 1 BYTE 2 CYCLES VA00181 ST6 INTERNAL RESET COUNTER RESET VA0200B 23 86 ST62T32B ST62E32B RESETS Table 7 Register Reset Status Addresses commen Oscillator Control Register EEPROM Control Register Port Data Registers Port Direction Register Port Option Register Interrupt Option Register TIMER Status Control AR TIMER Status Control 1 Register AR TIMER Status Control 2 Register AR TIMER Status Control 3 Register AR TIMER Status Control 4 Register SPI Registers X Y V W Register Accumulator Data RAM Data RAM Page REgister Data ROM Window Register EEPROM A D Result Register AR TIMER Capture Register AR TIMER Reload Capture Register ARTIMER Mask Registers ARTIMER Compare Registers TIMER Counter Register TIMER Prescaler Register Watchdog Counter Register A D Control Register ODBh ODFh OCOh to OC2h 0C4h to OC6h OCCh to OCEh 0C8h 0D4h OE8h OE1h OE2h OE3h ODCh to ODDh 080H TO 083H OFFh 084h to OBFh OCBh 0 9 00h to O3Fh ODBh OD9h OEOh OEFh OEDh OE Eh Undefined Main oscillator on EEPROM enabled are Input with or without pull up depending on PORT PULL option Interrupt disabled TIMER disabled AR TIMER stopped SPI disabled As written if programmed Max count loaded A D in Standby UART Control OD7h UART disabled UART Data R
94. nstruction should be executed as soon as possible after ihe beginning of the conversion because execution of the WAIT instruction may cause small variation of the Vp voltage The negative effect of this variation is min imized atthe beginning of the conversion when the converter is less sensitive rather than at the end of conversion when the less significant bits are determined The best configuration from an accuracy stand point is WAIT mode with the Timer stopped In deed only the ADC peripheral and the oscillator are then still working The MCU must be woken up from WAIT mode by the ADC interrupt at the end of the conversion It should be noted that waking up the microcontroller could also be done using the Timer interrupt but in this case the Timer will be working and the resulting noise could affect conversion accuracy 58 86 A D Converter Control Register ADCR Address OD1h Read Write 7 0 Bit 7 EAI Enable A D Interrupt If this bit is set to 1 the A D interrupt is enabled when EAI 0 the interrupt is disabled Bit 6 EOC End of conversion Read Only This read only bit indicates when a conversion has been completed This bit is automatically reset to 0 when the STA bit is written If the user is using the interrupt option then this bit can be used as an interrupt pending bit Data in the data conversion register are valid only when this bit is set to 1 Bit 5 STA Start of Conversion
95. nt on the pin in output mode is the Data register content as long as no transmission is active 4 ST62T32B ST62E32B PORTS Figure 24 Peripheral Interface Configuration of SPI UART and AR Timer16 PD4 RXD1 PD5 TXD1 PD3 Sout IN PD2 Sin SYNCHRONOUS SERIAL I O PD1 Scl PA3 PWM PA4 CP1 ARTIMER 16 5 2 PA2 OVF VR01661D 41 86 ST62T32B ST62E32B PORTS Cont d 4 1 6 I O Port Option Registers ORA B C D E CCh PA CDh PB CEh CFh PD FEh PE Read Write 7 0 ed Bit 7 0 Px7 Px0 Port A B C D and E Option Register bits 4 1 7 Port Data Direction Registers DDRA B C D E C4h PA C5h PB C6h PC C7h PD FDh PE Read Write 7 0 Bit 7 0 Px7 Px0 Port A B C D and E Data Di rection Registers bits 42 86 4 1 8 I O Port Data Registers DRA B C D E COh PA C1h PB C2h PC C3h PD FCh PE Read Write 7 0 Bit 7 0 Px7 Px0 Port A B C D and E Data Registers bits 4 4 2 TIMER The MCU features an on chip Timer peripheral consisting of an 8 bit counter with a 7 bit program mable prescaler giving a maximum count of 2 The peripheral may be configured in three different operating modes Figure 25 shows the Timer Block Diagram The external TIMER pin is available to the user The content of the 8 bit counter can be read written in the Timer Counter register TCR while the state of the 7 bit prescaler
96. nterrupt flags resp the NMI flags instead of the Normal flags When the RETI in struction is executed the previously used set of flags is restored It should be noted that each flag set can only be addressed in its own context Non Maskable Interrupt Normal Interrupt or Main rou tine The flags are not cleared during context switching and thus retain their status The Carry flag is set when a carry or a borrow oc curs during arithmetic operations otherwise it is cleared The Carry flag is also set to the value of the bit tested in a bit test instruction it also partici pates in the rotate left instruction The Zero flag is set if the result of the last arithme tic or logical operation was equal to zero other wise it is cleared Switching between the three sets of flags is per formed automatically when an NMI an interrupt or a RETI instructions occurs As the NMI mode is ky ST62T32B ST62E32B automatically selected after the reset of the MCU the ST6 core uses at first the NMI flags Stack The ST6 CPU includes a true LIFO hard ware stack which eliminates the need for a stack pointer The stack consists of six separate 12 bit RAM locations that do not belong to the data space RAM area When a subroutine call or inter rupt request occurs the contents of each level are shifted into the next higher level while the content of the PC is shifted into the first level the original contents of the sixth stack level are
97. o implement three wire bus Note When the SPI is not used the three 1 0 lines Sin SCL Sout can be used as normal I O with the fol lowing limitation bit Sout cannot be used in open drain mode as this enables the shift register output to the port It is recommended in order to avoid spurious in terrupts from the SPI to disable the SPI interrupt the default state after reset i e no write must be made to the 8 bit shift register An explicit interrupt disable may be made in software by a dummy write to the interrupt disable register SPI Data Shitt Register Address DDh Read Write SDSR 0 jor os os A write into this register enables SPI Interrupt after 8 clock pulses SPI Interrupt Disable Register Address DCh Read Write SIDR 7 0 o oe os o oe o A dummy write to this register disables SPI Inter rupt 4 5 SOFTWARE 5 1 ST6 ARCHITECTURE The ST6 software has been designed to fully use the hardware in the most efficient way possible while keeping byte usage to a minimum in short to provide byte efficient programming capability The ST6 core has the ability to set or clear any register or RAM location bit of the Data space with a single instruction Furthermore the program may branch to a selected address depending on the status of any bit of the Data space The carry bit is stored with the value of the bit when the SET or RES inst
98. prc JRC 4 prc JRC prc JRC prc JRC prc Mnemonic 4 ST62T32B ST62E32B 6 ELECTRICAL CHARACTERISTICS 6 1 ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs Power ConsiderationsThe average chip junc against damage due to high static voltages how tion temperature Tj in Celsius be obtained ever it is advisable to take normal precaution to from avoid application of any voltage higher than the PD x RthJA specified maximum rated voltages Where TA Ambient Temperature For proper operation it is recommended that V and Vo be higher than Vss and lower than Vpp RthJA ROME junc Reliability is enhanced if unused inputs are con ion to ambient nected to an appropriate logic voltage level PD Pint Pport or Vgs Pint 1 x Vpp chip internal power Pport Port power dissipation determined by the user Drain per Pin Excluding Von Ves m Notes Stresses above those listed as absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability 1 Withinthese limits clamping diodes are guarantee to be not conductive Voltages outside these limits are authorised as long as injection current
99. processed If several interrupt requests occurs before completion of the running interrupt routine only the first request is stored Storage of interrupt requests is not available in lev el sensitive mode taken into account the low Jevel must present on the interrupt pin when the MCU samples the line after instruction execu tion At thesend of every instruction the MCU tests the interrupt lines if there is an interrupt request the next instruction is not executed and the appropri ate interrupt service routine is executed instead Table 10 Interrupt Option Register Description Enable all interrupts CLEARED Disable all interrupts SET Rising edge mode on inter rupt source 2 di Falli d d int CLEARED alling edge mode on inter rupt source 2 E LES Level sensitive mode on in SET terrupt source 1 CLEARED Falling edge mode on inter rupt source 1 OTHERS USED 29 86 ST62T32B ST62E32B INTERRUPTS 3 4 2 Interrupt Procedure The interrupt procedure is very similar to a call pro cedure indeed the user can consider the interrupt as an asynchronous call procedure As this is an asynchronous event the user cannot know the context and the time at which it occurred As a re sult the user should save all Data space registers which may be used within the interrupt routines There are separate sets of processor flags for nor mal interrupt and non maskable interrupt modes
100. ption Register 31 3 4 4 Interrupt 31 3 5 POWER SAVING MODES dass c Reto eed en 34 3 54 WAIT Mode aar RE Rr AER Aix EE 34 9 5 2 STOP Ld RP QN aesti dd ass tue c 34 3 5 8 Exit from WAIT and STOP Modes 35 4 2 86 Table of Contents Document Page 4 ON CHIP PERIPHERALS 36 44 5 ue dac EIE Ma pfe i dod EORR ed 36 4 1 1 Operating MOd6S isses feds T Ee E 37 4 1 2 Safe I O State Switching 38 4 1 8 ARTimer alternate functions 40 4 1 4 SPI alternate 5 40 4 1 5 UART alternate 5 40 4 1 6 I O Port Option 5 42 4 1 7 Port Data Direction 5 42 4 1 8 I O Port Data Registers 42 42 MER bx eee a Ghee eae ke eed abla we ee hae T end 43 4 2 1 Timer Operating 44 4 2 2 met Intermipt
101. quency 20 86 VR001932 VR001933 4 ST62T32B ST62E32B CLOCK SYSTEM Figure 12 Clock Circuit Block Diagram POR Core TIMER 1 MAIN Watchdog OSCILLATOR Main Oscillator off Figure 13 Maximum Operating Frequency fyax versus Supply Voltage Maximum FREQUENCY MHz FUNCTIONAL NOT INTHIS AREA SUPPLY VOLTAGE Vpp VR01807 Notes 1 In this area operation is guaranteed at the quartz crystal frequency 2 When the OSG is disabled operation in this area is guaranteed atthe crystal frequency When the OSG is enabled operation in this area is guaranteed at a frequency of at min 3 When the OSG is disabled operation in this area is guaranteed at the quartz crystal frequency When the OSG is enabled access to this area is prevented The internal frequency is kept 4 When the OSG is disabled operation in this area is not guaranteed When the OSG is enabled access to this area is prevented The internal frequency is kept lt 1574 21 86 ST62T32B ST62E32B 3 2 RESETS The MCU can be reset in three ways by the external Reset input being pulled low by Power on Reset by the digital Watchdog peripheral timing out 3 2 1 RESET Input The RESET pin may be connected to a device of the application board in order to reset the MCU if required The pin may be pulled low in RUN WAIT or STOP mode This input can be used to res
102. r Counter with 7 bit programmable prescaler 16 bit Auto reload dimer with 7 bit programmable prescaler AR Timer Digital Watchdog 8 bit A D Converter with 21 analog inputs 8 bit Synchronous Peripheral Interface SPI 8 bit Asynchronous Peripheral Interface UART On chip Clock oscillator can be driven by Quartz Crystal or Ceramic resonator Oscillator Safe Guard One external Non Maskable Interrupt ST623x EMU2 Emulation and Development System connects to an MS DOS PC via a parallel port DEVICE SUMMARY ROM DEVICE Bytes Pins ST62P32B 7948 September 1998 16 bit AUTO RELOAD TIMER EEPROM SPI AND UART PSDIP42 PQFP52 See end of Datasheet for Ordering Information Rev 2 5 79 86 ST62P32B 1 GENERAL DESCRIPTION 1 1 INTRODUCTION The ST62P32B is the Factory Advanced Service Technique ROM FASTROM versions of ST62T32B OTP devices They offer the same functionality as OTP devices selecting as FASTROM options the options de fined in the programmable option byte of the OTP version 1 2 ORDERING INFORMATION The following section deals with the procedure for transfer of customer codes to STMicroelectronics 1 2 1 Transfer of Customer Code Customer code is made up of the ROM contents and the list of the selected FASTROM options The ROM contents are to be sent on diskette or by electronic means with the hexadecimal file generated by the development tool All unused byt
103. r RLCP or CP 4 3 4 INTERRUPT CAPABILITIES The interrupt source latches of the ARTIMER16 are always enabled and set any time the interrupt condition occurs The interrupt output is a logical OR of five logical ANDs INT CP1FLG amp CP1IEN OR CP2FLG amp CP2IEN OR OVFFLG amp OVFIEN OR COMPFLG amp CMPIEN OR ZEROFLG amp ZEROIEN Thus if any enable bit is 1 the interrupt output of the ARTIMER16 goes high when the respective flag is set If no enable bit is 1 and one of the in terrupt flags is set the interrupt output remains 0 but if the respective enable bit is set to 1 through a write operation the interrupt output will go high signalling the interrupt to the Core Figure 33 Positive CP1 to negative CP2 Edge Measurement CP1POL 1 CP2POL 0 Capture into RLCP Set CP1FLG Set CP1ERR TT i Capture into CP Set CP2FLG Application Note Depending on polarity setting for CP1 CP2 and of CP1 CP2 connections phase period and pulse width measurements can be achieved The total independence between CP1 and CP2 captures al lows phase detection by measuring which of 52 86 Set CP2ERR VRO2006F CP1FLG or CP2FLG is set at first following a reset of these flags CP1 CP2 CP1POL CP2POL Pulse width r 4 3 5 CONTROL REGISTERS Status Control Register 1 SCR1 Address E8h Read Write Clear only 7 0 PSC2
104. r is clocked by the pres caler clock input fnr 12 Figure 26 Timer Working Principle 44 86 The user can select the desired prescaler division ratio through the PS2 PS1 PSO bits When the TCR count reaches 0 it sets the TMZ bit in the TSCR The TMZ bit can be tested under program control to perform a timer function whenever it goes high The low to high TMZ bit transition is used to latch the DOUT bit of the TSCR and trans fer itto the TIMER pin This operating mode allows external signal generation on the TIMER pin Table 15 Timer Operating Modes TOUT DOUT 0 0 Event Counter Gated Input Output 0 Output 1 Input Input Output Output 4 2 2 Timer Interrupt When the counter register decrements to zero with the ETI Enable Timer Interrupt bit set to one an interrupt request i5 generated as described in the Interrupt Chapter When the counter decrements to zero the TMZ bit in the TSCR register is set to one VA00186 p TIMER Cont d 4 2 3 Application Notes The user can select the presence of an on chip pull up on the TIMER pin as option TMZ is set when the counter reaches zero howev er it may also be set by writing 00h in the TCR register or by setting bit 7 of the TSCR register The TMZ bit must be cleared by user software when servicing the timer interrupt to avoid unde sired interrupts when leaving the interrupt service routine After reset the 8 bit counter register is
105. r to the 16 bit register refresh the 16 bit register Example The following sequence is NOT GOOD ldi t16 mphyY 055 ldi t A6dmpl 0 00h tlocmp 16 bit register 5500h uf6oemphn OAAh tl6cmp 16 bit register 5500h inc tl6cmph tl6cmp 16 bit register 5500h ldi tl16cmpl 000h tl6cmp 16 bit register 5600h and NOT ABOOh is The CORRECT sequence Idi tl16cmph 055h Idi tl cmpl 000 tl6cmp 16 bit register 5500h ldi tl6cmph OAAh tl6cmp 16 bit register 5500h ldi tl cmpl 000 tl6cmp 16 bit register AAO00h inc tl6cmph tl6cmp 16 bit register AAO00h ldi tl16cmpl 000h tl6cmp 16 bit register ABOOh 55 86 ST62T32B ST62E32B Reload Capture Register High Byte RLCP Address E9h Read Write if RELOAD bit set D7 DO These bits are the High byte D15 D8 of the 16 bit Reload Capture Register Reload Capture Register Low Byte RLCP Address EAh Read Write if RELOAD bit set D7 DO These bits are the Low byte D7 DO of the 16 bit Reload Capture Register Capture Register High Byte CP Address EBh Read Only D7 DO These bits are the High byte D15 D8 of the 16 bit Capture Register Capture Register Low Byte CP Address ECh Read Only D7 DO These bits are the Low byte D7 DO of the 16 bit Capture Register 56 86 Compare Register High Byte CMP Address EDh Read Write D7 DO These bits are the
106. rity while source 4 the lower The priority of each interrupt source is fixed Table 9 Interrupt Vector Map Dntemuptsource i Interrupt source 2 Interrupt source 3 FF 2h FF3h Interrupt source 4 FFOh FF1h 3 4 1 Interrupt request All interrupt sources but the Non Maskable Inter rupt source can be disabled by setting accordingly the GEN bit of the Interrupt Option Register IOR This GEN bit also defines if an interrupt source in cluding the Non Maskable Interrupt source can re start the MCU from STOP WAIT modes Interrupt request from the Non Maskable Interrupt source 0 is latched by flop which is automat amp ST62T32B ST62E32B ically reset by the core at the beginning of the non maskable interrupt service routine Interrupt request from source 1 can be configu red either as edge or level sensitive by setting ac cordingly the LES bit of the Interrupt Option Regis ter IOR Interrupt request from source 2 are always edge sensitive The edge polarity can be configured by setting accordingly the ESB bit of the Interrupt Op tion Register IOR Interrupt request from sources 3 amp 4 are level sensitive In edge sensitive mode a latch is set when a edge occurs on the interrupt source line and is cleared when the associated interrupt routine is started So the occurrence of an interrupt can be stored until completion of the running interrupt routine be fore being
107. ruction is processed 5 2 ADDRESSING MODES The ST6 core offers nine addressing modes which are described in the following paragraphs Three different address spaces are available Pro gram space Data space and Stack space Pro gram space contains the instructions which are to be executed plus the data for immediate mode in structions Data space contains the Accumulator the X Y V and W registers peripheral and In put Output registers the RAM locations and Data ROM locations for storage of tables and con stants Stack space contains six 12 bit RAM cells used to stack the return addresses for subroutines and interrupts Immediate In the immediate addressing mode the operand of the instruction follows the opcode location As the operand is a ROM byte the imme diate addressing mode is used io access con stants which do not change during program execu tion e g a constant used to initialize a loop coun ter Direct the direct addressing mode the address of the byte which is processed by the instruction is stored in the location which follows the opcode Di rect addressing allows the user to directly address the 256 bytes in Data Space memory with a single two byte instruction Short Direct The core can address the four RAM registers X Y V W locations 80h 81h 82h 83h in the short direct addressing mode In this case the instruction is only one byte and the selection of the location to be processed is
108. rupt Polarity Bit 3 Port D Interrupt Polarity Bit 2 Port C Interrupt Polarity Bit 1 Port A Interrupt Polarity Bit 0 Port B Interrupt Polarity Table 12 1 O Interrupts selections according to IPR IOR programming Interrupt Port B occurence Port D occurence falling edge falling edge ling Co lins doe LU aling edge ain ete SEY Interrupt Port A occurence Port E occurence i v oo rising edge rising edge rising edge Trang edge p Lu pt tow evel pf Frit eir tow evel rising edge edge rising edge Interrupt source falling edge 32 86 4 ST62T32B ST62E32B INTERRUPTS Figure 21 Interrupt Block Diagram FROM REGISTER PORT A B C D E SINGLE BIT ENABLE IPR Bit 2 INT 0 NMI FFC D IPR Bit 0 IPR Bit 4 DED IOR bit 6 SERI RESTART IPR Bit 1 FF 5 INT 2 FF4 5 PBE CLR 1 Start IOR bit5 ESB IPR Bit3 CP1FLG CP1IEN CP2FLG INT 3 FF2 3 CP2IEN OVFLG CMPFLG CMPIEN D ZEROFLG ZEROIEN INT 4 FFO 1 bit 4 GEN 3 33 86 ST62T32B ST62E32B 3 5 POWER SAVING MODES The WAIT and STOP modes have been imple mented in the
109. rupt service routine as the service routine cannot save and then restore the register s previous contents If 1146 impossible to avoid writ ing to the DWR during the interrupt service routine an image of the register must be saved in a RAM location and each time the program writes to the DWR it must also write to the image register image register must be written first so that if an in terrupt occurs between the two instructions the DWR is not affected Figure 6 Data read on y memory Window Memory Addressing DATA ROM 13 WINDOW REGISTER 7 CONTENTS DWR Example DWR 28h ROM 0 PROGRAM SPACE ADDRESS READ 0 DATA SPACE ADDRESS 40h 7Fh IN INSTRUCTION DATA SPACE ADDRESS 59h t ADDRESS A19h 1 1 T4 1 3 VROA1573 11 86 ST62T32B ST62E32B MEMORY Cont d 1 3 6 Data RAM EEPROM Bank Register DRBR Address 7 0 BE DRBR4 DRBR3 gB prari Bit 7 5 These bits are not used Bit 4 This bit when set selects RAM Page 2 Bit 3 DRBR3 This bit when set selects RAM Page 1 Bit2 This bit is not used Bit 1 DRBR1 This bit when set selects EEPROM Page 1 Bit 0 DRBRO This bit when set selects EEPROM Page 0 The selection of the bank is made by programming the Data RAM Bank Switch register DRBR regis ter located at address CBh of the Data Space ac cording to Table 1 No more than one bank sho
110. s T o Lee Par fore T po ose vas oss oors pore rozz Cr 12 ooso oss nos ose or a pe oo aer aro 296 Fe cas rss so sro o sso neo pep p pe uz pase raso osse o ses n7 Fer reco ras e zo orae o 7as ss pep ros rro nose OE aes ras Fes sar seo osos o sos ns sens s jes 27 Number ofFins THERMAL CHARACTERISTIC Value Symbol Parameter Test Conditions 2 71 ped 77 86 ST62T32B ST62E32B 7 2 ORDERING INFORMATION Table 27 OTP EPROM VERSION ORDERING INFORMATION Program ST62E32BF1 7948 EPROM 0 to 70 C SDIP42W ST62T32BB6 40 10 85 C ST62T32BB3 30 dp SDIP42W ST62T32BQ6 ae 40 to 85 C 0 PQFP52 4 78 86 STA ST62P32B 8 BIT FASTROM MCUs WITH A D CONVERTER 3 0 to 6 0V Supply Operating Range 8 MHz Maximum Clock Frequency 40 to 125 C Operating Temperature Range Run Wait and Stop Modes 5 Interrupt Vectors Look up Table capability in Program Memory Data Storage in Program Memory User selectable size Data RAM 192 bytes Data EEPROM 128 bytes 30 pins fully programmable as Input with pull up resistor Input without pull up resistor Input with interrupt generation Open drain or push pull output Analog Input 9 I O lines can sink up to 20mA to drive LEDsvor TRIACs directly 8 bit Time
111. s set to one all interrupts are enabled When this bit is cleared to zero all the interrupts excluding NMI are disabled When the GEN bit is low the NMI interrupt is ac tive but cannot cause a wake up from STOP WAIT modes This register is cleared on reset 3 4 4 IInterrupt sources Interrupt sources available on the ST62E32B T32B are summarized in theTable 11 with associated mask bit to enable disable the in terrupt request Address Interrupt GENERAL excluding NM TIMER TCR TIMER Overtiow A D CONVERTER ADCR EOC End of Conversion RXIEN RXRDY Byte received 4 HART UARIGR TXIEN TXMT Byte sent OVFIEN Eih CP2IEN E2h ZEROIEN E2h CMPIEN ARTIMER E2h OVFFLG ARTIMER Overflow CP1FLG CP2FLG source 3 ZEROFLG Compare to zero flag CMPFLG Compare flag 3 31 86 ST62T32B ST62E32B IINTERRUPTS Cont d Interrupt Polarity Register IPR Address DAh Read Write 7 0 Boo In conjunction with IOR register ESB bit the polar ity of I O pins triggered interrupts can be selected by setting accordingly the Interrupt Polarity Regis ter IPR If a bit in IPR is set to one the corre sponding port interrupt is inverted e g IPR bit 2 1 port C generates interrupt on rising edge At re set IPR is cleared and all port interrupts are not in verted e g Port C generates interrupts on falling edges Bit 7 Bits 5 Unused Bit 4 Port E Inter
112. st like any other register in Data space Figure 7 ST6 Core Block Diagram 0 01 TO 8MHz I oscout WE meum NTROLLER FLAG PROGRAM ROM EPROM 16 86 CONTROL SIGNALS Indirect Registers X Y These two indirect reg isters are used as pointers to memory locations in Data space They are used in the register indirect addressing mode These registers can be ad dressed in the data space as RAM locations at ad dresses 80h X and 81h Y They can also be ac cessed with the direct short direct or bit direct ad dressing modes Accordingly the ST6 instruction Set can use the indirect registers as any other reg ister of the data space Short Direct Registers V W These two regis ters are used to save a byte in short direct ad dressing mode They can be addressed in Data space as RAM locations at addresses 82h V and 83h W They can also be accessed using the di rect and bit direct addressing modes Thus the ST6 instruction set can use the short direct regis ters as any other register of the data space Program Counter PC The program counter is a 12 bit register which contains the address of the next ROM location tosbe processed by the core This ROM location may be an opcode an oper and or the address of an operand The 12 bit length allows the direct addressing of 4096 bytes in Program space INTERRUPTS i DATA SPACE 1 1 1 1 1 DATA ADDRESS READ LINE ADDRESS DECODER ES 1
113. t RESET VPP on EPROM OT P versions only ST62T32B ST62E32B mon core is surrounded by a number of on chip peripherals The ST62E32B is the erasable EPROM version of the ST62T32B device which may be used to em ulate the ST62T32B device as well as the respec tive ST6232B ROM devices PAO PA1 20 mA Sink 2 20 mA Sink PA3 PWMI20 mA Sink PORTA d h bAZ AIn CP1 PAS Ain GP2 7 PBO Ain gt PORT B Lp B3 PB7 Ain PORT C lt gt PC5 PC7 Ain PDO PD6 PD7 Ain PD1 Ain Scl PD2 Ain Sin PURI PD3 Ain Sout PD4 Ain RXD1 UART PD5 Ain T XD1 lt gt PEO PE4 AUTORELOAD SPI SERIAL lt gt PERIPHERAL INTERFAC E DIGITAL WATCHDOG VR01823E 5 86 ST62T32B ST62E32B INTRODUCTION OTP and EPROM devices are functionally identi cal The ROM based versions offer the same func tionality selecting as ROM options the options de fined in the programmable option byte of the OTP EPROM versions OTP devices offer all the advantages of user programmability at low cost which make them the ideal choice in a wide range of applications where frequent code changes mul tiple code versions or last minute programmability are required Figure 2 ST62T32B E32B Pin Configuration PE4 PAO PA PE2 PA2 OVF PET PA3 PWM PEO PA4 Ain CP 1 OSCin 2 OSCout Ain CP7 PA7 Ain Ain PC6 TIMER Ain PC5 NMI VSSp
114. tchdog is per manently enabled Since the oscillator will run con tinuously low power mode is not available The STOP instruction is interpreted as a WAIT instruc tion and the Watchdog continues to countdown However when the EXTERNAL STOP MODE CONTROL option has been selected low power consumption may be achieved in Stop Mode Execution of the STOP instruction is then gov erned by a secondary function associated with the NMI pin If a STOP instruction is encountered when the NMI pin is low it is interpreted as WAIT as described above If however the STOP in struction is encountered when the NMI pin is high the Watchdog counter is frozen and the CPU en ters STOP mode When the MCU exits STOP mode i e when an in terrupt is generated the Watchdog resumes its activity Stop Mode SOFTWARE WATCHDOG Watchdog HARDWARE WATCHDOG 25 86 ST62T32B ST62E32B DIGITAL WATCHDOG Cont d The Watchdog is associated with a Data space register Digital WatchDog Register DWDR loca tion OD8h which is described in greater detail in Section 3 3 1 Digital Watchdog Register DWDR This register is set to OFEh on Reset bit C is cleared to 0 which disables the Watchdog the timer downcounter bits TO to T5 and the SR bit are all set to 1 thus selecting the longest Watch dog timer period This time period can be set to the user s requirements by setting the appropriate val ue for bits TO to T5 in the DWDR re
115. ted to the prescaler and acts as ex ternal timer clock or as control gate for the internal timer clock In output mode the TIMER pin outputs the data bit when a time out occurs The user can select as option the availability of an on chip pull up at this pin 7 86 ST62T32B ST62E32B 1 3 1 3 1 Introduction The MCU operates in three separate memory spaces Program space Data space and Stack space Operation in these three memory spaces is described in the following paragraphs Briefly Program space contains user program code in Program memory and user vectors Data space contains user data in RAM and in Program memory and Stack space accommodates six lev els of stack for subroutine and interrupt service routine nesting 1 3 2 Program Space Program Space comprises the instructions to be executed the data required for immediate ad dressing mode instructions the reserved factory test area and the user vectors Program Space is addressed via the 12 bit Program Counter register PC register Program Space is organised in four 2K pages Three of them are addressed in the 000h 7FFh lo cations of the Program Space by the Program Counter and by writing the appropriate code in the Program ROM Page Register PRPR register A Figure 5 Memory Addressing Diagram PROGRAM SPACE PROGRAM MEMORY INTERRUPT amp RESET VECTORS 8 86 common STATIC 2K page is available all the time for interrupt ve
116. ter PRPR Address CAh Write Only 7 0 Bits 2 72 Not used Bit 5 0 PRPR1 PRPRO Program ROM Select These two bits select the corresponding page to be addressed in the lower part of the 4K program address space as specified in Table 2 This register is undefined on Reset Neither read nor single bit instructions may be used to address this register Table 2 8Kbytes Program ROM Page Register Coding PRPRO Siate Page Page 1 LADE mw rato Pass 120 boe 1 3 2 2 Program Memory Protection The Program Memory in OTP or EPROM devices can be protected against external readout of mem ory by selecting the READOUT PROTECTION op tion in the option byte In the EPROM parts READOUT PROTECTION option can be disactivated only by U V erasure that also results into the whole EPROM context erasure Note Once the Readout Protection is activated it is no longer possible even for STMicroelectronics to gain access to the Program memory contents Returned parts with a protection set can therefore not be accepted 9 86 ST62T32B ST62E32B MEMORY MAP Cont d 1 3 3 Data Space Table 4 ST62T32B E32B Data Memory Space Data Space accommodates all the data necessary DATA and EEPROM for processing the user program This space com prises the resource the processor core and DATA ROM WINDOW AREA peripheral registers as well as read only data X REGISTER
117. ter Format STOP BIT lor 8 9 BIT POSITION 10 POSSIBLE NEXT CHARACTER START VR02012 START OF DATA 4 4 5 4 DATA RECEPTION The UART continuously looks for a falling edge on the input pin whenever a transmission is not ac tive Once an edge is detected it waits 1 bit time 8 states to accommodate the Start bit and then as sembles the following serial data stream into the data register The data in the ninth bit position is copied into Bit 9 replacing any previous value set for transmission After all 9 bits have been re ceived the Receiver waits for the duration of one bit for the Stop bit and then transfers the received data into the buffer register allowing a following character to be received The interrupt flag RXRDY is setto 1 as the data is transferred to the buffer register and if enabled will generate an in terrupt If a transmission is started during the course of a reception the transmission takes priority and the reception is stopped to free the resources for the transmission This implies that a handshaking sys tem must be implemented as polling of the UART to detect reception is not available Figure 38 UART Data Output UARTOE PORT DATA OUTPUT VR02011 Table 20 Baud Rate Selection BR fjr Division 6 656 ST62T32B ST62E32B 4 5 5 INTERRUPT CAPABILITIES Both reception and transmission processes can in duce interrupt to the core as defined in the inter r
118. ting with the execution of the instruction which follows the STOP or the WAIT instruction and the MCU is still in the interrupt mode At the end of this rou tine pending interrupts will be serviced in accord ance with their priority n the event of a non maskable interrupt the non maskable interrupt service routine is proc essed first then the routine in which the WAIT or STOP mode was entered will be completed by executing the instruction following the STOP or WAIT instruction The MCU remains in normal interrupt mode Notes To achieve the lowest power consumption during RUN or WAIT modes the user program must take care of configuring unused Os as inputs without pull up these should be externally tied to well defined logic levels placing all peripherals their power down modes before entering STOP mode When the hardware activated Watchdog is select ed or when the software Watchdog is enabled the STOP instruction is disabled and a WAIT instruc tion will be executed in its place If all interrupt sources are disabled GEN low the MCU can only be restarted by a Reset Although setting GEN low does not mask the NMI as an in terrupt it will stop it generating a wake up signal The WAIT and STOP instructions are not execut ed if an enabled interrupt request is pending 35 86 ST62T32B ST62E32B 4 ON CHIP PERIPHERALS 4 1 PORTS The MCU features Input Output lines which may be
119. uld be set at a time Write only The DRBR register can be addressed like Data Space at the address CBh nevertheless it is a write only register that cannot be accessed with single bit operations This register is used to select the desired 64 byte RAM EEPROM of the Data Space The number of banks has to be load ed in the DRBR register and the instruction has to 12 86 point to the selected location as if it was in bank 0 from 00h address to address This register is not cleared during the MCU initiali zation therefore it must be written before the first access to the Data Space bank region Refer to the Data Space description for additional informa tion The DRBR register is not modified when an interrupt or a subroutine occurs Notes Care is required when handling the DRBR register as itis write only For this reason it is not allowed to change the DRBR contents while executing in terrupt service routine as the service routine can not save and then restore its previous content If it is impossible to avoid the writing of this register in interrupt service routine an image of this register must be saved in a RAM location and each time the program writes to DRBR it must write also to the image register The image register must be written first so if an interrupt occurs between the two instructions the DRBR 15 not affected In DRBR Register only 1 bit must be set Other wise two or mor
120. upt section These interrupts are enabled by set ting TXIEN and RXIEN bit in the UARTCR register and TXMT and RXRDY flags are set accordingly to the interrupt source 4 5 6 REGISTERS UART Data Register UARTDR Address D6h Read Write 7 0 o oe os o oe oe o oo Bit7 BitO UART data bits A write to this register loads the data into the transmit shift register and triggers the start of transmission In addition this resets the transmit interrupt flag TXMT A read of this register returns the data from the Receive buffer Warning No Read Write Instructions may be used with this register as both transmit and receive share the same address Baud Rate fint 4MHz 1200 2400 4800 9600 19200 31200 38400 1200 2400 4800 9600 15600 19200 61 86 ST62T32B ST62E32B REGISTERS Cont d UART Control Register UARTCR Address D7h Read Write 7 0 RXRDY TXMT RXIEN TXIEN DAT9 Bit 7 RXRDY Receiver Ready This flag be comes active as soon as a complete byte has been received and copied into the receive buffer It may be cleared by writing a zero to it Writing a one is possible If the interrupt enable bit RXIEN is set to one a software interrupt will be generated Bit 6 TXMT Transmitter Empty This be comes active as soon as a complete byte has been sent It may be cleared by writing a zero to it It is automatically cleared by the action of writing a data value into the UAR
121. vent flag CP1FLG to set the ARTIMER interrupt Bit 3 CP1FLG Interrupt Flag When this bit is 0 no CP1 event has occurred since the last clear of this bit If the bit is at 1 CP1 event has occurred This bit cannot be set by program only cleared Bit 2 CP1POL CP Edge Polarity Select CP1POL defines the polarity for triggering the CP1 event A 0 defines the action on a falling edge on the CP1 input a 1 on a rising edge Bit 1 amp 0 RLDSEL2 RLDSEL1 Reload Source Select These bits define the source for the reload events they do not affect the operation of the cap ture modes Function Reload and startup triggered by Reload triggered by every CP1 1 Reload triggered by every CP2 event 3 53 86 ST62T32B ST62E32B CONTROL REGISTERS Cont d Status Control Register 3 SCR3 Address E2h Read Write Clear only 7 0 CP2POL f CP2FLG CMPEN CMFLG ZEROIEN ZEROFLG PWMMD Bit 7 CP2POL CP2 Edge Polarity Select CP2POL defines the polarity for triggering the CP2 event A 0 defines the action ona falling edge on the CP2 input a 1 on a rising edge Bit 6 CP2IEN CP2 Interrupt Enable The Cap ture 2 Interrupt is masked when this bit is 0 Set ting the bit to 1 enables the CP2 event flag CP2FLG to set the ARTIMER interrupt Bit 5 CP2FLG CP2 Interrupt Flag When this bit is 0 no CP2 event has occurred sin
122. xposure to short wave ul traviolet light which have a wave length 2537A The integrated dose i e U V intensity x exposure time for erasure should be a minimum of 15W sec cm The erasure time with this dosage is ap proximately 15 to 20 using an ultraviolet lamp with 12000uW c power rating The ST62E32B should be placed within 2 5cm 1Inch of the lamp tubes during erasure 15 86 ST62T32B ST62E32B 2 CENTRAL PROCESSING UNIT 2 1 INTRODUCTION The CPU Core of ST6 devices is independent of the or Memory configuration As such it may be thought of as an independent central processor communicating with on chip I O Memory and Pe ripherals via internal address data and control buses In core communication is arranged as shown in Figure 7 the controller being externally linked to both the Reset and Oscillator circuits while the core is linked to the dedicated on chip pe ripherals via the serial data bus and indirectly for interrupt purposes through the control registers 2 2 CPU REGISTERS The ST6 Family CPU core features six registers and three pairs of flags available to the programmer These are described in the following paragraphs Accumulator A The accumulator is an 8 bit general purpose register used in all arithmetic cal culations logical operations and data manipula tions The accumulator can be addressed in Data space as a RAM location at address FFh Thus the ST6 can manipulate the accumulator ju
123. y software as de scribed in the Interrupt Chapter for each port 4 1 1 3 Analog Input Options Some pins can be configured as analog inputs by programming the OR and DR registers according ly These analog inputs are connected to the on chip 8 bit Analog to Digital Converter ONLY ONE pin should be programmed as an analog input at any time since by selecting more than one input simultaneously their pins will be effectively short ed Input With pull up no interrupt oor on m Co 1 ome nop omera With pull up and with interrupt oe cia 1 0 X Oupu Open drain outpuis 20mA sink when available Output Push pull output 20mA sink when available Note X Don t care 37 86 ST62T32B ST62E32B PORTS Cont d 4 1 2 Safe 1 O State Switching Sequence Switching the I O ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur The recom mended safe transitions are illustrated in Figure 23 All other transitions are potentially risky and should be avoided when changing the I O operat ing mode as it is most likely that undesirable side effects will be experienced such as spurious inter rupt generation or two pins shorted together by the analog multiplexer Single bit instructions SET RES INC and DEC should be used with great caution on Ports Data registers since these instructions m

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