XSV Board 1.0 User Manual
Contents
1. LTR ECO NO APPROVED DATE J8 1 18 2 U31A J8 5 J8 6 J8 7 47 4 7 27 U30A 653 48 3 gt 27 x2 B S47 10uH C52 C50 L 51 1 001uF 2 576 10pF E E 054 js 2 WA XTAL UN E 015 ES 27 9 5 7115 XCVBUSt001 2401 o 5247 4 22 XCVBUS116 85 XCVBUSTI7 5 FAND Ween 20 XCVBUSIIB ess 3 H2 XCVBUS125 43 15 XCVBUS126 U30C C55 44 A121 VPO 74 5127 cvbs 3 1 20 VE05 XCVBUS128 5 4 1 T 122 VP06 XCVBUS130 o 27 6 VP07 2 3 ud C49 C48 AGND RTso 25 S 29 4 2247 047uF 0476 37 ck 3750 27 XCVBUSTIO 5 5 mire RIS 25 m XCVBUSII3 4 38 1 36 XCVBUSO92 g 10 LLC 8 3 sc 24 50 40 23 XCVBUSII5 gt uM RESET SDA 1 34 VDDDE1 VDDDE2 43 3V 25 0 15 VDDDA 2 VVDDA 9 VDDAO 5 29 vvVDDA 42 2 FERRITE BEAD VDDA2 4 x CN occu lt 2 ooaaoo 0000070 00 0 00 gt gt gt gt gt gt gt C47 C46 C45 C44 wot ot C42 C43 O tuF O tuF O tuF O tuF T 3 _ 0 tuF O tuF O tuF MEE COMPANY2. XC95108 Flash Video Parallel Serial CPLD LEDs Switches RAM Ethernet Decoder RAMDAC Codec RAM PS 2 USB Port Port Osc Xchecker 35 S3 left D3 TMS MCLK LRCK SCLK SDIN SDOUT VM VP RCV OE CLK VPO DATA VMO FDS MDINT MDC MDIO CRS COL TRSTE TxEN RxDV RS2 TxERR RxERR RS1 TxD4 RSO RxD4 RxD3 D7 RxD2 D6 RxD1 D5 RxDO D4 TxD3 D3 TxD2 D2 TxD1 D1 TxDO DO Connections Between the Virtex FPGA and the Other XSV Board Components XC95108 Flash Video Parallel Serial Prog Virtex FPGA CPLD LEDs Switches RAM Ethernet Decoder RAMDAC Codec RAM PS 2 USB Port Port Osc 46 WR 47 RD 48 HSYNC 49 50 BLANK 51 GND 52 PIXELCLK 53 A9 right 54 A8 right 55 A7 right 56 A6 right 57 A5 right 58 M1 14 59 GND 60 M0 13 61 VCCO 62 M2 15 63 A4 right 64 right 65 A2 right 66 1 right 67 right 68 WE right 69 GND 70 00 right 71 P1 D1 right 72 P2 D2 right 73 P3 D3 right 74 P4 D4 right 75 GND 76 VCCO 77 VCCINT 78 P5 D5 right 79 P6 D6 right 80 P7 D7 right 81 D8 right 82 D9 right 83 GND 84 010 right 85 D11 right 86 D12 right 87 013 right 88 VCCINT 89 PGCK 22 CLK CLKI 90 VCCO
3. Virtex FPGA GND PGCK GND VCCINT VCCO GND GND GND DONE VCCO PROG INIT D7 GND D6 GND Connections Between the Virtex FPGA and the Other XSV Board Components XC95108 Flash Video CPLD LEDs RAM Decoder RAMDAC Codec RAM Xchecker LLCK D14 right D15 right OE right A18 right A17 right A16 right A15 right A14 right A13 right A12 right A11 right A10 right CE right RTS1 RTSO RTCO SCL SDA VPOO VPO1 VPO2 10 DONE 11 PROGRA 9 ANIT 40 S0 right D7 VPO3 VPO4 VPO5 VPO6 VPO7 43 BAR8 WE 16 51 right A0 RT 17 S2 right A1 RD 39 S6 left D6 Virtex FPGA 136 VCCO 137 VCCINT 138 D5 139 140 141 142 143 GND 144 145 04 146 147 148 VCCINT 149 150 VCCO 151 GND 152 153 154 155 156 D3 157 158 GND 159 160 161 162 163 D2 164 VCCINT 165 VCCO 166 GND 167 D1 168 169 170 171 172 GND 173 174 175 176 177 DO DIN 178 BUSY DC 179 CCLK 180 VCCO Connections Between the Virtex FPGA and the Other XSV Board Components XC95108 Flash Video Parallel CPLD LEDs Switches RAM Ethernet Decoder RAMDAC Cod
4. L R25 CEGI 352 4 E33 CFGO x 20 XCYBUSISG 180 LEDC GSR M2 5 M4 715 MDDIS D4 LEDS i2 M4 16 22 EDE 05 158 51_ 2_8 4717 LEDR D6 gt LP2 X us 2 20 T X D6 27 xcvBusi24 X 83 M2 10 M5 3 x a bsy dout 286 5 26 5 70 X L gt LP4 cs_ X 184 8 2 12 U16 M5 5 23 x _ gt LPs init X 2714 _ MA 3 x done X 0710 42 14 XC95108 TQ Maza 5 14 X 5 LP6 program M2 1o vs 56 xX X 5 it gt 18 5169 30 132 welt 61 Lp X gt LPs CVBUSI63 M33 5 14 Tes CVBUSI77 52 3 4 5 15 58 XCVBUSTAO X lt XCVBUS187 33 3 5 T ies X CVBUSISB 35 M3 M 805196 33 LP9 x U32A M39 568 0320 1 45 zv LP14 1 2 42 5 LP6 LB 9 p c 741514 3 700 LP5 22 Ed A 57 741514 Lp2 LP17 VCCINT2 LP4 LP16 LP16 58 2 lt __ ces 2 1 58 VCCIO1 LP15 O 1uF 4 3 51 102 lt U32E O uF o tuF Len lt 8 03 LP1 9 VCCIO4 10 200 741514 o U32B 88823885 6 6 6 68526 74LS14 45 e LP14 C92 C91 C59 C58 C57 C56 9 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF COMPANY 55 TITLE 74LS14 XS
5. ouF L 6 428 5 gt 1 eur DTR zs 428 4 DCD 428 1 5 34 DSR 128 6 RING J28 9 gt COMPANY XESS Corp TITLE XSV Board DRAWN DATED serial port interface CHECKED DATED CODE SIZE DRAWING NO REV QUALITY CONTROL DATED 1 0 RELEASED DATED SCALE steer 12 2 1 XCVBUS 001 240 XCVBUS145 XCVBUS134 XCVBUS138 XCVBUS156 05165 05177 XCVBUS167 XCVBUS141 XCVBUS147 XCVBUS144 XCVBUS139 XCVBUS133 XCVBUS124 XCVBUSI32 g AAA 300 REVISION RECORD LTR ECO NO APPROVED DATE DIA XCVBUS152 utie id DAAAJO 1 bi 20 300 LEDBAR XCVBUS154 eI 2 lt 9 200 LEDBAR DIC XCVBUS157 AU42A 16 300 LEDBAR DID XCVBUS160 DANS 7 300 LEDBAR DIE XCVBUS162 SNA 5 gt 309 LEDBAR XCVBUS169 6 gt 5 300 LEDBAR 016 XCVBUS168 UAE SAAA2 7 gt 14 300 LEDBAR U42F AA XCVBUSUS 6A AA 45 300 LEDBAR DIU 0426 XCVBUSIS ZARA 10 sp 300 LEDBAR DW XCVBUS171 500 LEDBAR 5 001 2401 XESS TITLE XSV Board DRAWN DATED LED section CHECKED DATED CODE SIZE DRAWING N
6. 50 VREF1_6 492 5194 BUSO 58 1 VREFIL3 Figs XCVBUSI95 80506 2 199 5199 239 200 XCVBUS200 eee 3 201 XCVBUS201 182 1705 VREFI 7 50 XCVBUS202 XCVRUSJA 20 XCVBUS203 B 205 XCVBUS205 R20 300 16 VREF1 2 206 XCVBUS206 20 XCVBUS207 208 XCVBUS208 2 5 VCCINT3 VREFI 5 508 XCVBUS209 A VCCINT4 215 XCVBUS215 VCCINT5 VREF0_5 518 XCVBUS216 VCCINT6 217 XCVBUS217 VCCINT7 218 XCVBUS218 VCCINTB _1 226 XCVBUS220 VGENTS 221 XCVBUS221 222 XCVBUS222 VCCINTII _7 253 XCVBUS223 2 224 XCVBUS224 228 XCVBUS228 229 XCVBUS229 3 VCCO3 VREFO_3 230 XCVBUS230 Hon VREFO_6 731 XCVBUS231 232 XCVBUS232 vecos VREFO_2 734 XCVB 7 255 XCVBUS235 236 XCVBUS236 VCCOS 4 237 XCVBUS237 238 XCVBUS238 vccon VCCo13 vcco14 15 vccol6 2 5 433v A C73 C72 C69 C68 C67 C66 C65 C64 C63 C62 C61 O tuF O 1uF O tuF O tuF O tuF O 1uF O 1uF O tuF 0 1uF 0 1uF O 1uF C60 REVISION RECORD LTR ECO NO APPROVED DATE COMPANY XESS Corp XSV Board DRAWN DATED Virtex FPGA CHECKED DATED CODE SIZE DRAWING NO REV QUALITY CONTROL DATED 1 0 RELEASED DATED SCALE SHEET 1 2 1 C0 00 01 02
7. p l SCLK c9 210 2200pF LL RIGHT CHANNEL PWDA 10uF ese L 24 16 CMODE s gt 17 DEMO 5 9 s 3 1 36 00 F AVDD 4 0 047uF DVDD 4 2 VD 20 E vrer tsm He DGND 5 4520 5 AVDD 0 00 FERRITE BEAD ki XESS Corp bot TITLE c93 c15 c18 0 luF O luF LO 87 4 XSV Board DRAWN DATED stereo audio 1 0 section CHECKED DATED CODE SIZE DRAWING NO REV QUALITY CONTROL DATED 1 0 RELEASED DATED SCALE steer 7 2 1 PS 2 MINIDIN 6 CONNECTOR J20 4 J20 1 J20 5 J20 2 J20 6 420 3 420 7 420 8 420 9 REVISION RECORD LTR NO APPROVED DATE XCVBUSI001 2401 55 m 5017 XCVBUSO13 4 gt po COMPANY XESS Corp TITLE XSV Board DRAWN DATED PS 2 interface section CHECKED DATED CODE SIZE DRAWING NO REV QUALITY CONTROL DATED 1 0 RELEASED DATED SCALE steer 8 1 USB Connector D REVISION RECORD LTR APPROVED DATE 3 3V 3 3V XCVBUSL001 2401 n C94 6 tok 0 uf low high 14 J35 1 1353 J18 7 PDIUSBPHA 5 12 XCVBUSO
8. 2608 Sweetgum Drive 27502 Toll free 800 549 9377 International 919 387 0076 orporation FAX 919 387 1302 XSV Board V1 0 Manual How to install and use your new XSV Board XSV BOARD V1 0 MANUAL RELEASE DATE 5 16 2001 Copyright 1999 2001 Engineering Software Systems Corporation XS prefix product designations trademarks of XESS Corp All XC prefix product designations are trademarks of Xilinx All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electronic mechanical photocopying recording or otherwise without the prior written permission of the publisher Printed in the United States of America XSV BOARD V1 0 MANUAL RELEASE DATE 5 16 2001 Table of Contents Preliminaries Getting Help Here are some places to get help if you encounter problems m f you can t get the 540 Board hardware to work send an e mail message describing our problem to help xess com or submit a problem report at http www xess com reghelp html Our web site also has m answers to frequently asked questions m example designs for the XSV Boards m to sign up for our email forum Where you can post questions to other XS Board users m f you can t get your XILINX Foundation software tools installed properly send an e mail message describing your problem to hotline xilinx com or
9. Once the downloading is finished the BIT file name is added to the Recent Files window and the Reload button is enabled You can download the file to the XSV Board again just by clicking on the Reload button Your XSV Board is now configured with the circuit in your BIT file XSV BOARD V1 0 MANUAL 11 5 16 2001 Downloading Virtex Configuration Bitstreams to Flash You can also store a bitstream for the FPGA in the 16 Mb Flash RAM on the XSV Board Once again make sure there is a shunt across pins 2 and 3 of jumper J31 Also make sure that all the DIP switches are in the OFF position Then just drag and drop a EXO file containing the bitstream to the GXSLOAD window GXSLOAD will configure the CPLD with a circuit that lets it program the Flash RAM Then GXSLOAD uses the CPLD to program the Flash with the contents of the EXO file Finally the CPLD is configured with a circuit that loads the FPGA when power is applied Now the Virtex FPGA will be loaded with the circuit you stored in the Flash whenever power is applied to the XSV Board You will have to reprogram the CPLD with the dwnldpar svf file if you want to reconfigure the FPGA with a BIT file using the parallel port The EXO file is generated using the Programmer tool in Foundation The configuration data should start at address 0 and extend upward to higher addresses You can also use the PROMGEN command line utility to generate the EXO file like so PROMGEN u 0 FILE BIT p
10. 03 gt 1 PWRPLUG 1 2 59 PWR IN IN SWITCH ENTER U43 U44 045 5V ouT o 300 932 cie LM317 LM317 Ji J14 ADJ a 2 5 B a Wo 7 u 52 3 amp ST 253 84 3 5 12V 9VDC Power L 24 2 ug COMPANY dis ESS Corp 224 3 TITLE XSV Board DRAWN DATED power input amp regulation Cooling Fan Connector CHECKED DATED CODE SIZE DRAWING NO REV QUALITY CONTROL DATED 1 0 RELEASED DATED SCALE steer 15
11. 138 left 134 56 left 124 580 right 171 BAR9 173 XC95108 CPLD 43 44 45 46 47 48 49 50 51 52 53 54 55 56 GND TDI TMS VCCO VCCINT Virtex FPGA 131 Connections Between the XC95108 CPLD and the Other XSV Board Components LEDs BAR8 Switches Flash Video Parallel Serial Prog RAM Ethernet Decoder RAMDAC Codec RAM PS 2 USB Port Port Osc Xchecker WE 170 CE DIPSW1 DIPSW2 DIPSW3 DIPSW4 DIPSW5 DIPSW6 DIPSW7 DIPSW8 Connections Between the XC95108 CPLD and the Other XSV Board Components Virtex Flash XC95108 CPLD FPGA LEDs Switches Ethernet Decoder RAMDAC Codec RAM PS 2 USB Port Video Parallel Serial Prog Port Osc Xchecker CTS MF4 MF3 MF2 MF1 MFO FDE CFGO MDDIS LEDR LEDT LEDL VCCINT LEDC GND XSV Schematics The following pages show the detailed schematics for the XSV Board XSV BOARD V1 0 MANUAL 35 5 16 2001 1 XCVBUS 001240 72 XCVBUSO72 VREES 8 75 XCVBUS073 VREFS 74 XCVBUSO74 VREF7_4 78 XCVBUSO78 79 XCVBUSO79 CVBUSOBO VRE
12. 03 04 05 06 07 6 7 5 54 C1 53 2 C3 J10 1 J10 2 J10 3 J10 4 J10 5 J10 6 J10 7 J10 8 J10 9 J10 10 Jt0 11 J10 12 J10 13 J10 14 J10 15 10 16 10 17 10 18 10 19 010 20 10 21 010 22 010 23 10 24 10 25 REVISION RECORD LTR NO APPROVED DATE 1222 5 2 XCVBUS 001240 R19 4 7K TREE 7 XEYSUSE CVBUSI41 19 1 1 3 2 5 38 XCVBUSTS4 XCVBUSI001 2401 S losciN 1 0 HL 4 2 15 1 12 40 XCVBUST24 amp XTAL ouro 2 CVBUSI32 16 MI S M314 41 XCVBUSI7I CVBUSISS 317 15 42 XCVBUST73 5 PDN SELX CvBUS139 18 M1 8 M3 15 Tag x 68 CVBUSI52 24 MI 9 13 17 81 x R22 CVBUS 20 M4 3 52 RTS RESET 2 051075 XCVBUSO89 22 iz 2 80 80517043 1 7 XCVBUSI47 23 Wane 85 RD VBUST 329 GE 28F016S5 XCVBUSIBA 2 Maze 55 XCvBUS13130 0 apy 28 XCVBUSI7I 1 2 28 6 1 16 4 9 L88 MES XCVBUSI32 16 10 po 17 XCVBUSI77 5024 86 1 1 3 90 XCVBUSI53 15 20 F8 XCVBUST67 Ext Ose LEDL 372 5 32 5 MFO B D2
13. 17 gt XCVBUS202 XCVBUS203 42 26 XCVBUS205 26 21 XCVBUS206 XCVBUS207 jog 34 XCVBUS208 128 25 gt XCVBUS209 DEM XCVBUS215 XCVBUS216 426 29 gt XCVBUS217 126 30 gt XCVBUS218 426532 XCVBUS220 426 33 XCVBUS221 26 34 gt XCVBUS222 126 36 gt XCVBUS223 426 37 XCVBUS224 126 38 gt XCVBUS228 disco s XCVBUS229 426 41 gt XCVBUS230 disci s XCVBUS231 26 44 gt XCVBUS232 4126 45 gt XCVBUS234 126 46 gt XCVBUS235 126 48 gt XCVBUS236 426 49 XCVBUS237 426 50 XCVBUS238 433v A 426 3 126 11 226 19 196 27 gt 026 35 2 4 426 43 5 426 7 gt 4 426 15 3 426 23 5 3 426 31 2 426 39 5 3 26 47 gt 4 COMPANY XESS Corp TITLE XSV Board DRAWN DATED expansion interface section CHECKED DATED CODE SIZE DRAWING NO REV QUALITY CONTROL DATED 1 0 RELEASED DATED SCALE SHEET 11 5 2 1 089 SERIAL PORT CONNECTOR REVISION RECORD LTR ECO NO APPROVED DATE ces our C83 pur C84 Bue 21 Ch 1 u49 C1 6 y c2 H 62 RTS MAX232A J28 7 RTS 428 3 gt 10 7 lt 01 10 TD 228 8 5 13 13 12 gt CTS RD J28 2 8 E 9 ORD 1
14. 18 MDC 19 MDIO 20 MDDIS 94 MFO 91 MF1 90 MF2 89 MF3 87 MF4 86 CFGO 93 CFG1 2 FDE 92 3 LEDS 1 LEDR 95 LEDT 96 LEDL 97 LEDC 99 XSV BOARD V1 0 MANUAL 22 5 16 2001 Expansion Headers The XSV Board has two 50 pin headers J25 and J26 which connect the FPGA to external systems The arrangement of the headers is shown below J26 Virtex FPGA U18 J25 The connections between the FPGA and the expansion headers are listed below The FPGA pins which connect to the left and right expansion headers are also connected to the left and right banks of SRAM respectively The SRAM bank chip enable should be raised to disable the SRAMs on that side if the associated expansion header is being used for external Expansion Virtex Connector FPGA Pin Pin to Left Connector 1 186 2 187 3 4 188 5 189 6 191 XSV BOARD V1 0 MANUAL Virtex SRAM FPGA Pin Function to Right Connector 109 CE 53 A9 5V 54 A8 55 A7 56 A6 23 5 16 2001 XSV BOARD V1 0 MANUAL 9 193 63 A4 11 5 13 199 66 A1 15 GND 17 202 70 el ae a ee 19 5 Tee 21 206 73 D3 23 GND 25 209 79 D6 27 3 3 29 217 82
15. D9 A 31 GND Seen eee Eee Bares 33 221 86 D12 re ee eee 35 43 3 Se ee ee ee 37 224 94 015 RECEN 39 GND Een EEA 41 230 97 A17 SEE AGE 43 3 3 Be Be Ee Eee 45 234 101 A14 47 GND 49 237 107 11 uc emus 5 16 2001 Pushbuttons and Eight Position DIP Switch The XSV Board has a bank of eight DIP switches and four pushbuttons that are accessible from the FPGA The CPLD is also connected to the DIP switches and one of the pushbuttons When pressed each pushbutton pulls the connected pin of the FPGA and CPLD to ground Otherwise the pin is pulled high through a resistor Likewise each DIP switch pulls the connected pin of the FPGA or CPLD to ground when it is closed or ON When the DIP switch is open or OFF the pin is pulled high through a resistor When not being used the DIP switches should be left in the open or OFF configuration so the pins of the FPGA and CPLD are not tied to ground and can freely move between logic low and high levels A External He 23555335552 Oo e e Oo o 04 e e Oo WI i 01 SW6 Oo Oo 904 7 SW3 SW2 6 91 15 5 XC95108 Virte
16. Output Port Port Port Output XSV BOARD V1 0 MANUAL 7 5 16 2001 Installation Installing the XSVTOOLs Software Run the SETUP EXE file on the XSVTOOLs CDROM This will install the utilities and configuration files for testing and programming your XSV Board If you are running Windows NT or Win2000 then you must also install the parallel port driver using the port95nt exe installation script on the CDROM Unpacking the Board You should place the XSV Board on a non conducting surface Configuring the Jumpers 1 Place a shunt on jumper J23 2 Place a shunt on pins 2 and 3 of jumper J31 3 Place a shunt on pins 2 and 3 of J22 4 Placea shunt on pins 1 and 2 of J36 Applying Power You can supply the XSV Board with power in two ways 1 Recommended Attach an ATX PC power supply to connector J11 Remove any shunts on jumpers J13 and J14 Place a shunt on pins 1 and 2 of jumper J32 2 Attach a 9 VDC power supply with a 2 1mm center positive plug to jack J12 The power supply must be able to source at least 1 5 A Place shunts on jumpers J13 and J14 Place a shunt on pins 1 and 2 of jumper J32 LED D2 will glow when the power is on XSV BOARD V1 0 MANUAL 8 5 16 2001 Connecting to a PC One DB25 connector on the 6 foot cable should be attached to connector J10 on the XSV Board and the other end should plug into the parallel port connector of a PC Testing the XSV Board GXSTEST runs your XSV Board throug
17. XESS Corp TITLE XSV Board DRAWN DATED video decoder section CHECKED DATED CODE SIZE DRAWING NO REV QUALITY CONTROL DATED 1 0 RELEASED DATED SCALE steer 4 6 1 REVISION RECORD 051001 2401 LTR APPROVED __ XCVBUS049 lt J4 14 vsync XCVBUSO48 2 lt J J4 13 FREE VAA Pur H 026 C35 5052 WN 1 182 _ koe L m 5070 210 588 VBUSO71 gt XCVBUSO72 34 XCVBUSO73 35 52 lt gle 05074 3615 014 S 5 SN XCVBUSO78 37 BT481A S S S S 515 55 5 a lt 5 39 5 HELE 3585 8585 8585 898 g 5 SYNC SENSE H VAA 9 95 9676 USUS MS 2 010 of of of aa 5 R16 i 92 30 T T lt 4 7K 5103 E 20 C34 45 T J4 1 red 2 29 vaa 4 lt 5 8 COMP XCVBUS042 8 2 XCVBUSO4T 9 100 5 05040 1007 25 XCVBU5039 11 J6 T 44 2 green BU 12 03 A 5 13 104 26 VBUSOS5 14 105 06 VBUSO34 15 106 VBUSO47 6107 127 9 amp VBUSO46 1682 J7 J4 3 blue e VBUS
18. check their web site at http support xilinx com Packing List Here is what you should have received in your package m an XSV Board m a6 foot 25 wire cable with a male 0825 connector at each end m XSTOOLs CDROM with software utilities and documentation for using the XSV Board XSV BOARD V1 0 MANUAL 5 16 2001 5 Overview The XSV Board brings you the power of the XILINX Virtex FPGA embedded in a framework for processing video and audio signals The XSV Board has a single Virtex FPGA from 50K to 800K gates in size The XSV can digitize PAL SECAM or NTSC video with up to 9 bits of resolution on the red green and blue channels and can output video images through a 110 MHz 24 bit RAMDAC The XSV can also process stereo audio signals with up to 20 bits of resolution and a bandwidth of 50 KHz Two independent banks of 512K x 16 SRAM are provided for local buffering of signals and data The XSV Board has a variety of interfaces for communicating with the outside world parallel and serial ports Xchecker cable a USB port PS 2 mouse and keyboard port and 10 100 Ethernet PHY layer interface There are also two independent expansion ports each with 38 general purpose I O pins connected directly to the Virtex FPGA You can configure the XSV Board through a PC parallel port serial port Xchecker cable or from a bitstream stored in the 16 Mbit Flash RAM The Flash RAM can also store data for use by the FPGA after configura
19. the board 3 J29 5041 d 1 led EG d d d d Parallel Port d Connector gt 5 210 gt S gt 5 gt 5 XC95108 gt s CPLD 3 J31 6G e 1 XSV BOARD V1 0 MANUAL 30 5 16 2001 The table below lists the connections from the parallel port to the general purpose I O pins of the CPLD Parallel XC95108 Port Pin CPLD Pin 1 CO 79 2 00 77 3 D1 74 4 02 72 5 03 70 6 04 68 7 05 67 8 06 66 9 07 65 10 56 64 11 57 63 12 55 61 13 54 60 14 C1 78 15 53 76 16 C2 73 17 3 71 Serial Port The CPLD handles the interface to the serial port The four active lines of the serial port connect to general purpose pins on the CPLD as follows Serial Port 95108 Pin CPLD Pin RTS 82 TD 81 CTS 85 RD 80 XSV BOARD V1 0 MANUAL 31 5 16 2001 MAX232A cts Serial Port Connector id gt 28 XC95108 CPLD rts level shifters Xchecker Interface Header J21 provides an interface between the FPGA and an Xchecker cable The Xchecker cable can be used to perform configuration and readback operations on the FPGA To prevent interference the shunt should be removed from jumper J36 to disconnect the DS1075 and any external clocks from the clock input through the Xchecker cable CLKI You must also make sure the CPLD pins in the table below are in a high impedance state In addition the CPLD should place a hi
20. to two independent banks of SRAM as shown below Each SRAM bank is organized as 512K x 16 bits Each bank is made from two Winbond 57 4096 SRAM Pin Virtex Virtex FPGA Pin FPGA Pin to Left to Right Bank Bank ICE 186 109 OE 228 95 ANE 201 68 DO 202 70 D1 203 71 D2 205 72 D3 206 73 D4 207 74 D5 208 78 D6 209 79 D7 215 80 D8 216 81 D9 217 82 D10 218 84 D11 220 85 012 221 86 013 222 87 014 223 93 015 224 94 XSV BOARD V1 0 MANUAL 16 5 16 2001 SRAM Pin Virtex Virtex FPGA Pin FPGA Pin to Left to Right Bank Bank A0 200 67 A1 199 66 A2 195 65 A3 194 64 4 193 63 5 192 57 6 191 56 189 55 8 188 54 9 187 53 10 238 108 11 237 107 12 236 103 13 235 102 14 234 101 15 232 100 16 231 99 17 230 97 18 229 96 Video Decoder The XSV Board can digitize NTSC SECAM and PAL video signals using the SAA7113 video decoder http www us semiconductors philips com pip SAA7113H The digitized video arrives at the FPGA over the VPO bus The arrival of video data is synchronized with the rising edge of the LLC line locked clock from the video decoder The FPGA programs the video options of the SAA7113 using the bus SCL and SDA 8 S Video ait Connector 3 7113 af2 8 Video T ai RCA Jack Decoder 4 cvbs 9 SAA7113 Virtex Pin FPGA Pin LLC 92 RTSO 111 RTS1 110 XSV
21. 0 XCVBUS034 47 e 10 lt 03 2 XCVBUSO33 46 8 03 23 TX TD s XCVBUS023 64 20 9 23 COL TREF 1 XCVBUSO21 1 ens 19 XCVBUSO24 3 TRSTE EVCCA 1000 22 4136 05019 45 MDIO 24 MDC VCCA T 50 RBIAS 22 A A A EVCCA 2 A d 26 22 K A FERRITE BEAD 50 VCCR 37 2 o otur 0 0 o otuF 628 c29 31 T 25 627 626 10uF 10uF FIBON H amp FlBop HZ I E COMPANY LEDC 39 28 55 53 4 VCCIO 9 vcco FlBIP HZ TITLE 68 XSV Board _ 2 E T 55 3 ERN RISUS DRAWN DATED Ethernet interface section 0 0tuF 7 CHECKED DATED CODE SIZE DRAWING NO REV QUALITY CONTROL DATED 1 0 RELEASED DATED SCALE steer 6 2 1 5 XCVBUS 001 240 AVDD REVISION RECORD LTR ECO NO APPROVED DATE LEFT CHANNEL 22K 22K XCVBUSOO7 JACK3 5 x uz 3 ANL 0007 1 c2 AINL AOUTL SZ 2 Un RIGHT CHANNEL ANR AQUTR 27 avon AINR VCOM 470 MCLK 22uF LRCK
22. 11 512 SL3 514 815 516 SRO SR1 SR2 SR3 SR4 SR5 SR6 BO B1 B2 B3 B4 B5 B6 Virtex FPGA Pin 177 167 163 156 145 138 134 124 132 133 139 141 144 147 152 154 157 160 162 169 168 XC95108 CPLD Pin 27 32 33 34 35 36 37 39 40 16 17 18 19 20 23 24 25 27 28 29 30 49 v Flash RAM Function DO D1 D2 D3 D4 D5 D6 D7 0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 5 16 2001 LED Virtex XC95108 Flash RAM FPGA Pin CPLD Pin Function B7 173 42 B8 131 43 B9 171 41 RDY PS 2 Port The XSV Board provides a PS 2 style interface mini DIN connector J20 to either a keyboard or a mouse The FPGA receives two signals from the PS 2 interface a clock signal and a serial data stream that is synchronized with the falling edges on the clock signal PS 2 Connector J20 The following table shows the connections from the FPGA to the PS 2 interface PS 2 Port Virtex Pin FPGA Pin CLK 13 DATA 17 USB Port The XSV Board has a USB interface J35 that can be connected to a variety of high speed or low speed USB peripherals The FPGA interfaces to the two differential data signals from the USB port through a PDIUSBP11A USB interface chip httpwww s semiconductors philips convpip PDIUSBPT1A 2 XSV BOARD V1 0 MANUAL 28 5 16 2001 J16 J18 high Speed D gt USB 0 gt J35 gt hi
23. 12 U51A v85 12 XCVBUSOI3 435 2 LAAA S 10 viaze oee 3 XCVBUSO17 22 U50 3 5011 ey XCVBUSO10 Mir XCVBUSO09 U518 XCVBUSI76 435 3 o speeo H MODE H 3 22 SUSPND 6 3 3V GND 435 4 gt Qs R23 2 amr d 2 o3 high U478 U47A 15k 15k J35 5 2 J35 6 2 4 XESS C orp TITLE XSV Board DRAWN DATED USB interface section CHECKED DATED CODE SIZE DRAWING NO REV QUALITY CONTROL DATED 1 0 RELEASED DATED SCALE 5 9 5 2 1 HEADER 421 1 921 7 921 9 J21 11 421 13 421 15 421 17 J21 2 J21 4 J21 6 J21 16 J21 18 J21 10 J21 12 J21 14 421 5 421 8 REVISION RECORD LTR ECO APPROVED DATE XCVBUSL001 2401 VCC CCLK XCVBUS179 DONE XCVBUS120 DIN XCVBUS177 PROGRAM XCVBUS122 INIT XCVBUS123 RST XCVBUS144 RT XCVBUS132 RD XCVBUS133 TRIG gt XCVBUS139 CLKI XCVBUS089 CLKO XCVBUS141 TDI XCVBUS167 TCK XCVBUS239 TMS XCVBUS156 NC gt NC gt GND 55 TITLE XSV Board DRAWN DATED XCHECKER interface section CHECKED DATED CODE SIZE DRAWING NO REV QUALITY CONTROL DATED 1 0 RELEASED DATED SCALE steer 10 1 EXPANSION HEADER XCVBUS 001240 J25 1 g
24. BOARD V1 0 MANUAL 17 5 16 2001 SAA7113 Virtex Pin FPGA Pin RTCO 113 116 VPO1 117 VPO2 118 125 4 126 VPO5 127 VPO6 128 VPO7 130 SCL 114 SDA 115 RAMDAC and VGA Monitor Interface The FPGA can generate video signal display on monitor either directly using a 481 RAMDAC http www erc msstate edu reese EE4993 data sheets btl481a c pdf depending upon the arrangement of the shunts on jumpers J5 46 and J7 gt vsync gt hsync 235592 5 5 red red 481 46 1 green 7 9 blue blue When the FPGA is directly generating VGA signals the lower six bits of the P bus provide two bits of red green and blue color information to a simple resistor ladder DAC The outputs of the DAC are sent to a VGA monitor along with the horizontal and vertical sync pulses HSYNC VSYNC from the FPGA When the RAMDAC generates the color signals then the FPGA uses the full eight bit P bus to pass the index of the color for the current pixel The index is used to lookup the 24 bit color value eight bits for the red green and blue components stored in the XSV BOARD V1 0 MANUAL 18 5 16 2001 256 entry colormap of the RAMDAC chip The transfers over the P bus are synchronized with the PIXELCLK generated by the FPGA The F
25. Dal25 XCVBUS221 BUSO 18 05 26 CVBUSO53 18 45 05 26 CVBUS187 18 145 2 05 26 XCVBUS208 X VBUSTB7 18 JAg 8 ps 25 XCVBUS222 05108 209 lt 0529 CVBUS108 20 lt 02129 XCVBUS238 2040 06129 XCVBUS209 AXCVBUS238 2049 lt 05 29 XCVBUS223 CVBUS107 zi B8 06130 CVBUS107 S pE XCVBUS237 21 n 2 p 30 XCVBUS215 5257 21 0580 xCVBUS224 CVBUS105 22h CVBUS105 22 412 VBUS236 22 412 2 XCVBUS236 2242 CVBUS102 23 113 CVBUS102 23 AS XCVBUS235 23 115 XCVBUS235 23 CVBUS101 24 CVBUS101 24 ia XCVBUS234 24 n XCVBUS234 24 i CVBUS100 32 Ms CVBUS100 32 is VBU 32 is XCVBU 32 115 099 33 Me CVBUS099 33 ie XCVBUS231 33 io XCVBUS231 33 io CVBUSO97 34 CVBUS097 34 417 XCVBUS230 3 AP XCVBUS2 30 MAS CVBUSO96 35 22 CVBUS096 35 28 BU 35 22 BU 3518 22 T T C74 C75 C76 C82 C77 C78 0 1uF O 1uF O 1uF 0 tuF O 1uF XESS Corp TITLE XSV Board DRAWN DATED RAM section CHECKED DATED CODE SIZE DRAWING NO REV QUALITY CONTROL DATED 1 0 RELEASED DATED SCALE steer 3 REVISION RECORD 2 1 S Video Connector Composite Video REVISION RECORD
26. F7_1 vnEF5 7 80 XEVEUSQET 82 XCVBUSO8Z VREF7_6 B4 XCVBUSOB4 VREF7_3 VREF5 2 55 XCVBUSOBS 86 XCVBUSO86 87 XCVBUSO87 VREF5_5 93 XCVBUSO9S VREF7_7 5 94 XCVBUSOS 4 VREF4 5 95 05095 96 XCVBUSO96 VREF7_2 era 1 97 XCVBUSO97 VREF 4_1 XCVBUSOSS 100 XCVBUSI00 VREF7_5 101 XCVBUSIO1 VREF 4_7 107 XCVBUS102 103 XCVBUS103 107 XCVBUS107 VREF6_5 5 108 XCVBUSI08 Hos XCVBUSIOS VYREF4 6 XCVBUSTIO VREF6 1 T XCVBUSTIT VREF4 2 XCVBUSIIS 114 XCVBUSII4 VREF6_7 15 XCVBUSII5 VREF4_4 XCVBUSII6 T7 XCVBUSII7 XCVBUSTIB VREF6_3 125 XCVBUSI25 VREF6_6 126 XCVBUSI26 VREF3_4 127 XCVBUSI27 VREF6_2 128 XCVBUSI28 130 XCVBUSI30 VREF3_1 37 XCVBUSTSI VREF6_4 132 XCVBUS132 VREFS 5 155 XCVBUSI33 VREF3_3 459 XCVBUS139 140 XCVBUSI40 VREF3_7 141 XCVBUST41 147 XCVBUSI42 144 XCVBUST44 VREF5_4 VREF3_2 H XCVBUSTE 14 XCVBUST4 VREF3 5 Hag XEVBUSIS 5 1 XCv800 1 5 i XCVBUST 154 XCVI 154 VREF2_5 1 XCVBU GCK2 VREF2 1 525 05159 GCK3 180 XCVBUSI60 T XCVBU DIN DO VREF2 7 He XCVBU Di 5 XCVBU 02 VREF2_3 He XCVBU 03 VREF2_6 170 XCVBUSITO 04 05 VREF2 2 173 XCVBUSI73 06 174 05174 175 05175 BUSY DOUT VREF2 4 175 XCVBUSI76 186 5186 187 05187 INIT VREF1_4 Higa 5188 pone 189 XCVBUSI89 255122 191 XCVBUSIST B 179 VREF1_I Haz 05192 3 60 195 05193
27. M Port LPT1 Your next step is to select the parallel port that your XSV Board is connected to using the Port drop down list GXSLOAD starts with parallel port LPT1 as the default but you can also select LPT2 or LPT3 depending upon the configuration of your PC After setting the parallel port you can download an SVF file to the CPLD on the XSV Board simply by dragging it to the GXSLOAD window To program the CPLD with the parallel port interface drag the dwnldpar svf file from the XSTOOLS directory Once you release the left mouse button and drop the file GXSLOAD will begin sending it to the XSV Board through the parallel port connection During the process GXSLOAD will display the name of the file currently being downloaded Once the CPLD is programmed with the parallel port interface circuit you can remove the shunt from jumper J23 to prevent accidental reprogramming of the CPLD Downloading Virtex Configuration Bitstreams Once the CPLD is programmed with the downloading interface circuit you can download bitstreams into the Virtex FPGA using the GXSLOAD utility Make sure there is a shunt across pins 2 and 3 of jumper J31 Then drag and drop into the GXSLOAD window a BIT configuration bitstream for the type of Virtex FPGA on your XSV Board The bitstream will pass through the parallel port and CPLD and then into the FPGA During the download process you will notice a fluttering of the bottom segment of the left LED digit
28. O REV QUALITY CONTROL DATED 1 0 RELEASED DATED SCALE steer 13 1 XCVBUS 001 240 REVISION RECORD LTR APPROVED _ DATE lt o amp o 6888 8 amp 8 amp 3338 8 8 8 Sz Sx Sx Sz Sx Sx Sx e e 2 2 2 2 2 2 XCVBUS161 USA 16 300 XCVBUS159 0378 15 9 300 XCVBUS155 0376 14 300 XCVBUS153 0370 5 13 300 XCVBUS149 USTE 2 12 300 XCVBUS146 UST z 300 XCVBUS142 0376 10 5 300 XCVBUS140 2 9 300 u g E 8 8 8 5 5 5 5 555555555 XCVBUS174 3 XCVBUSI75 3 XCVBUSI76 3 XCVBUS185 3 COMPANY XESS Corp t XSV Board DRAWN DATED dip switches and pushbuttons CHECKED DATED CODE SIZE DRAWING NO REV QUALITY CONTROL DATED 1 0 RELEASED DATED SCALE SHEET 14 1 JI1 10 1 12 11 18 31 9 5V standby gt 1 3 gt PWR OK 5 p 91 7 D4 Jn 13 D4 51 15 gt Jn 16 gt m p D gt 242 2 D gt DS 5v 4 gt gt 19 D Jn 20 m gt ATX Power Connector 3 5VDC 5VDC PS ON GROUND REVISION RECORD LTR ECO NO APPROVED pate 43 3V 42 5V 43 3V A A A
29. O31 7 MS A 18 VBUSO26 19851 RS2 lt m o 4 RB 829 829 VAA 1 558 558554 VAR Eme UA SS A A 2 3 4 4 FALSA 5 D lt 24 6 FERRITE BEAD 1 py ly 2 5 022 F 24 7 D o 528 XESS Corp __ 637 C36 5 024 rer T 0 tuF 100 T O uF O tuF DNE i 1 XSV Board DRAWN DATED video output section CHECKED DATED CODE DRAWING NO REV QUALITY CONTROL DATED 1 0 RELEASED DATED SCALE steer 5 2 1 REVISION RECORD LTR NO APPROVED DATE C24 0 01uF c19 x c20 c21 43 3 18pF Aul 18pF 0 01uF n 2S aul TLA 6T103 U13E E 9 RD 1525 XCVBUSI001 2401 x TEE 1 UF XCVBUSO27 56 29 X 57 TPIP 2 Q E 75 50 o 58 R2 R3 RX X 59 0 01uF 6 lt J5 6 X 60 VVV 3 RD X 671X01 50 50 leas RXCT 35 1 5 52 UI3C 63 1XD3 30 r TXD4 TPIN x J3 5 5 5028 55 21 XCVBUS21 54 T I XCVBUSO26 ST RX GUK R4 R5 OO 12 XEVBUSLSE 20 WAV 677 m 50 48 RXD LXT970A 50 5
30. PGA lowers the BLANK signal when the pixels fall outside the desired visible area of the monitor screen The colormap of the RAMDAC is initialized by the FPGA using the D bus along with the RS WR RD signals The 24 bit colormap entries are passed in groups of three bytes over the eight bit D bus synchronized by the AWR signal The register select signals RS0 RS1 RS2 select the staging register for writing the colormap The contents of the staging register are written into the colormap after the last byte of color information arrives over the D bus and then the internal colormap address is incremented to point to the next entry The shunt placement to enable the FPGA to generate signals directly or through the RAMDAC is shown below Arar n J7 J6 J5 J7 J6 J5 Direct VGA RAMDAC Shunt Setting Shunt Setting pin assignments for the connection of the FPGA to the signal generation circuitry are shown below Note that the FPGA shares some connections between the RAMDAC and the chip which interfaces to the Ethernet LXT970A The RAMDAC pins are used to load the colormap and should not be active except during system initialization The other connections are used for Ethernet data transmission and reception and are usually only active after system initialization Direct RAMDAC Virtex LXT970A VGA Pin Pin FPGA Pin Function PIXELCLK 52 HSYNC HSYNC 48 NSYNC NSYNC 49 BLANK 50 REDO PO 70
31. RED1 P1 71 GREENO P2 72 GREEN1 P3 73 P4 74 BLUE1 P5 78 P6 79 P7 80 RD 47 46 RS0 31 TXD4 RS1 28 RX ER RS2 26 RX DV 00 42 TXDO XSV BOARD V1 0 MANUAL 19 5 16 2001 Direct RAMDAC Virtex LXT970A VGA Pin Pin FPGA Pin Function D1 41 TXD1 D2 40 TXD2 D3 39 TXD3 04 38 RXD0 D5 36 RXD1 D6 35 RXD2 07 34 RXD3 Stereo Codec The XSV Board has an AK4520A stereo codec that accepts two analog input channels from jack J1 digitizes the analog values and sends the digital values to the as serial bit stream The codec also accepts serial bit stream the 5 Board and converts it into two analog output signals which exit the XSV Board through jack J2 The serial bit streams are synchronized with a clock from the FPGA that enters the codec on SCLK signal The FPGA uses the LRCK signal to select the left or right channel as the source destination of the serial data The master clock from the FPGA MCLK synchronizes all the internal operations of the codec Stereo Jack 1 4520 Stereo Jack 22 FPGA pins which connect to the codec are as follows Stereo Virtex Codec Pin FPGA Pin MCLK 3 LRCK 4 SCLK 5 SDIN 6 SDOUT 7 Ethernet PHY The XSV Board interfaces to an Ethernet LAN at 10 or 100 Mbps The LXT970A Ethernet PHY chip http 128 11 21 45 scripts mardev product Ixt970 asp connects to both the FPGA and the CPLD The FPGA acts as a MAC media access controller and ma
32. V Board DRAWN DATED configuration section CHECKED DATED CODE SIZE DRAWING QUALITY CONTROL DATED 1 0 RELEASED DATED SCALE steer 2 1 XCVBUS 001 2401 LTR ECO NO APPROVED __ 51001 2402 XCVBUSL001 240 XCVBUSL001 2401 XCVBUSE001 2401 R17 R18 4 7K 4 7K EN al of ale 6 B 6 CVBUS186 6 CVBUS186 6 31 88 B 31 E 85 XCVBUS228 31 88 XCVBUS228 31 88 ij gt gt BUSO68 ij gt gt CVBUS201 ij gt gt XCVBUS201 ij gt gt 06 hho CVBUSO67 0 CVBUS200 1 XCVBUS200 1 A0 066 210 us 066 2 M CVBUS199 240 35 99 240 936 06 CVBUS065 21 05195 XCVBUST9 3 06 4142 CVBUSO64 42145 CVBUS194 442 0519 47142 06 ER 0012 063 5 0017 05193 5 2 2 05193 LBW 0017 XCVBUS216 0 14 15 ne CVBUS057 4214 XB XCVBUSOBZ AXCVBUS192 14 Dpi 8 __ 203 XCVBUSI92 141142 LS XCVBUS217 056 15 149 pot CVBUSO56 15149 oH X CVBUS191 15 49 XCVBUS205 05191 15149 9 1 5218 0 16 45 amp 532 CVBUS055 16 45 9 2 05189 16 45 03 12 5206 05185 16 145 032 xXCVBUS220 0 171 102125 5054 17142 p4 25 CVBUS188 17 pal25 XxCVBUS207 AXCVBUSIBB 17 48
33. ch time power is applied to the XSV Board The divisor is set with the GXSSETCLK software utility You start GXSSETCLK by clicking on the icon placed on the desktop during the XSVTOOLs installation This brings up the screen shown below XSV BOARD V1 0 MANUAL 9 5 16 2001 X Set XS Board Clock Frequency 8 Board Type 5954 08 Port Cancel Divisor External Clock Set the XS Board clock frequency by entering a divisor for the 100 MHz master frequency Your next step is to select the parallel port that your XSV Board is connected to from the port pulldown list GXSSETCLK starts with parallel port LPT1 as the default but you can also select LPT2 or LPT3 depending upon the configuration of your PC After selecting the parallel port you select XSV from the pulldown list of XS Board types Next you must enter a divisor between 1 and 2052 into the text box Once programmed the oscillator will output a clock signal generated by dividing its 100 MHz master frequency by the divisor The divisor is stored in non volatile storage in the oscillator chip so you only need to use GXSSETCLK when you want to change the frequency The external clock checkbox is not applicable to the XSV Board because no external clock is connected to the programmable oscillator chip Clicking on the SET button will start the oscillator programming procedure Status messages will be printed at the bottom of the GXSSETCLK window a
34. e Virtex FPGA and XC95108 CPLD as follows gt XC95108 CPLD 8 Flash RAM 4 1 Pid gt 21 Virtex FPGA The CPLD and FPGA both have access to the Flash RAM Typically the CPLD will program the Flash with data passed through the parallel or serial port If the data is an FPGA configuration bitstream then the CPLD can be configured to program the FPGA with the Flash bitstream whenever the XSV Board is powered up After power up the FPGA can read and or write the Flash Of course the CPLD and FPGA have to be programmed such that they do not conflict if both are trying to access the Flash The Flash can be disabled by raising the CE pin to Vcc in which case the lines connected to the Flash can be used for general purpose communication between the FPGA and the CPLD The pins of the FPGA and CPLD connected to the Flash RAM are listed below XSV BOARD V1 0 MANUAL 14 5 16 2001 Flash RAM Virtex XC95108 Pin FPGA Pin CPLD Pin RESET 3 CE 170 46 OE 173 42 131 43 RDY 171 41 DO 177 32 D1 167 33 02 163 34 03 156 35 04 145 36 05 138 37 06 134 39 07 124 40 132 16 A1 133 17 A2 139 18 A3 141 19 4 144 20 5 147 23 152 24 A7 154 25 A8 157 27 A9 160 28 A10 162 29 11 169 30 A12 168 49 A13 161 50 A14 159 52 A15 155 53 A16 153 54 A17 149 55 A18 146 56 A19 142 58 A20 140 59 XSV BOARD V1 0 MANUAL 15 5 16 2001 SRAM Banks The has access
35. ec RAM PS 2 USB Port Xchecker 37 S5 left D5 18 S3 right A2 TRIG 59 DIPSW8 20 19 S4 right A3 CLKO 58 DIPSW7 19 20 S5 right A4 RST 36 S4 left D4 56 DIPSW6 18 23 S6 right A5 55 DIPSW5 17 24 BARO A6 54 DIPSW4 16 25 BAR1 A7 53 DIPSW3 15 35 S3 left D3 TMS 27 BAR2 A8 52 DIPSW2 14 28 BAR3 A9 50 DIPSW1 A13 29 BAR4 10 34 52 left 02 33 1 left 01 TDI 49 BAR6 12 30 5 11 46 41 BAR9 RDY 42 BAR7 OE SW1 SW2 SW3 SUSPND 32 50 left 00 DIN 6 12 CCLK Virtex FPGA 181 TDO 182 GND 183 TDI 184 CS 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 GND 212 VCCO 213 PGCK 214 VCCINT 215 216 217 218 219 220 221 222 223 224 225 GND GND VCCO VCCINT GND GND VCCINT Connections Between the Virtex FPGA and the Other XSV Board Components XC95108 Flash Video Parallel Serial Prog CPLD LEDs Switches RAM Ethernet Decoder RAMDAC Codec RAM PS 2 USB Port Port Osc Xchecker 34 S2 left D2 33 51 left D1 TDI 8 7 SW4 CE left 9 left 8 left A7 left left left left A5 left A4 left left A2 left A1 left AO left WE DO left D1 left left left left D2 left D3 lef
36. epeating symbol transmission scrambling etc Likewise the configurations signals CFGO 1 select the 10 Mbps or 100 Mbps operating speed of the PHY chip MDDIS enables disables the management information interface FDE selects either full duplex or half duplex communication mode The reset RESET and power down PWRDWN signals do exactly what they say The CPLD also gets receives the status outputs from the PHY chip that normally drive LEDs The outputs are active low and indicate when 100 Mbps operation is selected LEDS the receiver is active LEDR the transmitter is active LEDT the link is active LEDL and a collision is detected LEDC The CPLD can relay these signals to the LEDs on the XSV Board if you wish to display the Ethernet status XSV BOARD V1 0 MANUAL 21 5 16 2001 The connections of the PHY chip to the FPGA and CPLD are listed below Note that the FPGA shares some connections between the PHY chip and the RAMDAC The RAMDAC pins are used to load the colormap and should not be active except during system initialization The PHY connections are used for data transmission and reception and are usually only active after system initialization LXT970A Virtex XC95108 RAMDAC Pin FPGAPin CPLD Pin COL 23 CRS 21 TRSTE 24 TX_CLK 210 TX_EN 25 TX_ER 27 42 DO TXD1 41 D1 TXD2 40 D2 TXD3 39 D3 TXD4 31 RSO RX_CLK 213 RX_DV 26 RS2 RX_ER 28 RS1 RXDO 38 D4 RXD1 36 D5 RXD2 35 D6 RXD3 34 D7 RXD4 33 FDS MDINT
37. exo s 2048 This creates a EXO file from the bitstream in FILE BIT The u 0 option causes the first byte of Flash data to be stored at address 0 and subsequent bytes are stored at sequentially higher addresses The p exo option selects Motorola S record format for the generated file The s 2048 option tells PROMGEN the size of the Flash chip on the 5 Board 16 Mbits 2048 KBytes XSV BOARD V1 0 MANUAL 12 5 16 2001 XSV Circuitry This section describes the various sections of the XSV Board and shows how the of the FPGA and CPLD are connected to the rest of the circuitry The schematics which follow are less detailed so as to simplify the descriptions Please refer to the complete schematics at the end of this document if you need more details Programmable logic XCV50 XCV800 Virtex FPGA and XC95108 CPLD The XSV Board contains two programmable logic chips m AXILINX Virtex FPGA in 240 pin QFP package Virtex FPGAs from 57 Kgates XCV50 up to 888 Kgates XCV800 are compatible with the XSV Board The Virtex FPGA is the main repository of programmable logic on the XSV Board m AXILINX XC95108 CPLD that is used to manage the configuration of the Virtex via the parallel port serial port or Flash RAM The CPLD also controls the configuration of the Ethernet PHY chip 100 MHz programmable oscillator A Dallas 051075 programmable oscillator http www dalsemi com DocControl PDFs 1075 pdf provides a clock si
38. gh 2 low 22 speed speed J19 The USB port is set to high 12 Mbps or low speed 1 5 Mbps by shunts on jumpers J18 and J37 A 15K load can be placed on the D and D USB signals by placing shunts across jumpers J33 and J34 If the USB peripheral connected to the port needs to draw power from the XSV Board then a shunt should be placed on jumper J16 The connections of the FPGA to the USB interface chip are listed below Note that the FPGA shares some of its pins between the USB interface the PS 2 interface and one pushbutton switch PDIUSB11A Virtex Other Pin FPGA Pin Functions OE 12 VPO 13 PS 2 CLK 17 PS 2 RCV 11 VP 10 VM 9 SUSPND 176 SW3 Parallel Port The CPLD handles the interface to the parallel port The seventeen active lines of the parallel port connect to general purpose pins on the CPLD Four of the parallel port lines also connect to the JTAG pins through which the CPLD is programmed The TCK signal clocks configuration data in through the TDI pin while the TMS signal steers the actions of the programming state machine The TDO pin outputs XSV BOARD V1 0 MANUAL 29 5 16 2001 information back through the parallel port Removing the shunt from jumper J23 isolates the TCK pin from the parallel port so the CPLD will not be inadvertently reprogrammed during routine parallel port operations The series resistor prevents the TDO output from interfering with the general purpose p
39. gh logic level on the chip enable pin of the Flash RAM to prevent the LSB of its data pins from interfering with the DIN pin of the Xchecker interface Xchecker Pin Virtex FPGA Pin CPLD Pin 1 VCC 5V N A N A 2 RT 132 16 3 GND N A N A 4 RD 133 17 6 TRIG 139 18 7 179 12 9 DONE 120 10 10 TDI 167 33 11 DIN 177 32 12 TCK 239 4 13 PROGRAM 122 11 14 TMS 156 35 15 INIT 123 9 16 CLKI 89 22 17 RST 144 20 18 141 19 XSV BOARD 1 0 MANUAL 32 5 16 2001 If you also want access the JTAG port of the FPGA all the requisite pins are already connected to the Xchecker interface except for TDO The TDO pin of the FPGA connects to pin 34 of the CPLD so you must route the signal through the CPLD and onto the RD pin of the Xchecker interface which the Xchecker uses for TDO You must also make sure that pins 133 and 163 on the FPGA are tristated in your design or else they will override TDO XC95108 163 Virtex FPGA You can get a complete Xchecker interface for the CPLD from http www xess com appnotes an 050101 xsvxchk pdf Power Connectors A standard ATX PC power supply can be connected to the XSV Board through connector J11 The connector is keyed so power cannot be applied with the wrong polarity The shunts should be removed from jumpers J13 and J14 to prevent the 9 VDC converter circuitry from interfering with the ATX power supply We recommend using the ATX powe
40. gnal to both the FPGA and the CPLD The DS1075 has a maximum frequency of 100 MHz that is divided to provide frequencies of 100 MHz 50 MHz 33 3 MHz 25 MHz 48 7 KHz The clock signal is connected to dedicated clock inputs of both the CPLD and FPGA as follows DS1075 Virtex XC95108 Output FPGA Pin CPLD Pin CLK 89 22 To set the divisor value the 0 1075 must be placed in its programming mode This is done by pulling the clock output to Vcc on power up with a shunt across pins 1 and 2 of jumper J22 Then programming commands to set the divisor can be sent to the 051075 by either the CPLD or FPGA The divisor is stored in EEPROM in the DS1075 so it will be restored whenever power is applied to the XSV Board The shunt on jumper J22 must be across pins 2 and 3 to make the oscillator output a clock signal upon power up To get a precise frequency value or to sync the XSV circuitry with an external system you can insert an external clock signal through pin 1 of connector J27 and place a shunt across pins 2 and 3 of jumper J36 This external clock replaces the output from the DS1075 oscillator XSV BOARD V1 0 MANUAL 13 5 16 2001 M 3 i 100 MHz Prog Osc 1 056 0 1075 2 22 89 1 9 J27 External XC95108 Virtex Clock CPLD FPGA L 16 Mbit Flash RAM An Intel 28F016S5 Flash RAM http developer intel com design flcomp datashts 290597 htm with 16 Mbits of storage 2M x 8 is connected to both th
41. h a simple diagnostic routine to validate the operation of the hardware You start GXSTEST by clicking on the icon placed on the desktop during the XSVTOOLs installation This brings up the screen shown below XS Board Test Utility Board Type lt 595 108 Port LPT Cancel Select your X5 Board type and click on TEST Your next step is to select the parallel port that your XS Board is connected to from the port pulldown list GXSTEST starts with parallel port LPT1 as the default but you can also select LPT2 or LPT3 depending upon the configuration of your PC After selecting the parallel port you select the type of XSV Board you are testing from the associated pulldown list Then click on the TEST button to start the testing procedure GXSTEST will program the CPLD on the XSV Board and then use it to program the Virtex FPGA with a test circuit Status messages will be printed at the bottom of the GXSTEST window as the testing proceeds At the end of the test you will receive a message informing you whether your XSV Board passed the test or not Setting the Oscillator Frequency The XSV Board has a programmable oscillator which provides a clock signal to the FPGA and CPLD The oscillator has an internal 100 MHZ frequency source that is scaled by a divisor between 1 and 2052 to generate the clock signal for the rest of the XSV Board The divisor is stored in non volatile memory in the oscillator chip so it will be restored ea
42. in during routine parallel port operations The CPLD can be programmed to act as an interface between the FPGA and the parallel port the dwnldpar svf file is an example of such an interface Schmitt trigger inverters be inserted into the do d4 and signal lines by placing shunts on pins 2 and of jumpers J29 J30 and J31 respectively Along with the parallel port interface circuitry in the CPLD these inverters make the XSV Board compatible with the GXSPORT and GXSLOAD software utilities If your application requires direct access to these signal lines then you can move the shunts on one or more of these jumpers to pins 1 and 2 But GXSLOAD will no longer work if you remove the inverter from the c4 signal line Be careful if you program the CPLD with outputs that drive the c1 c2 c3 and 57 pins of the parallel port These parallel port pins are also connected to the JTAG pins of the CPLD and are used to reprogram the CPLD If you program the CPLD to drive these pins then it will permanently prevent the PC from reprogramming the CPLD As an ultra conservative rule of thumb you should never configure CPLD pins 63 71 73 or 78 as outputs If you must use these pins as outputs then place them in a high impedance mode whenever the Virtex FPGA is unconfigured i e the Virtex DONE pin is atlogic O This will allow you to regain control of the parallel port by toggling the power to
43. nages the transfer of data packets to and from the PHY chip while the CPLD controls the configuration pins that determine the operational mode of the PHY chip XSV BOARD V1 0 MANUAL 20 5 16 2001 mp 5 Virtex Ru45 4 pon G nnector FPGA tpip cto c LXT970A Ethernet PHY 4 2 XC95108 CPLD The FPGA enables the transmitter with TX EN and sends bits on TXD4o in sync with the transmit clock TX CLK generated by the PHY chip The PHY chip is alerted to transmission errors that occur in the MAC when the TX ERR signal is asserted The FPGA also receives an indication when valid data has been received RX DV and the data 4 in sync with the receiver clock RX from the PHY chip Any reception errors are indicated to the FPGA via the RX ER signal The CRS signal indicates when the receiver is non idle The COL signal is asserted when data collides on the Ethernet The FPGA can disable the interface to the PHY chip by asserting the tristate control TRSTE Otherwise the FPGA passes management information to and from the PHY chip over the serial data line MDIO in sync with a clock MDC the FPGA can be alerted to changes in PHY chip status by the FDS MDINT interrupt line The CPLD sets the static values on pins which control the configuration of the PHY chip Pins 4 set the modes for auto negotiation r
44. r supply due to its stability and power capacity The XSV Board can also be powered from a 9 VDC power supply through jack J12 The power supply must have a 2 1mm center positive plug Two voltage regulators will generate the 5V and 3 3V voltages for the other XSV Board components Shunts should be placed on jumpers J13 and J14 to connect the outputs from the voltage regulators to the rest of the XSV Board We do not recommend the 9 VDC power input for general use The 2 5V for the Virtex FPGA core logic can be generated on the XSV Board or supplied from an external source Placing a shunt across pins 1 and 2 of jumper J32 will use the on board regulator to generate the 2 5V from the 5V supply You can inject 2 5V from an external source by attaching the positive terminal to pin 2 of jumper J32 and ground to pin 3 XSV BOARD V1 0 MANUAL 33 5 16 2001 XSV Pin Connections The following tables list the pin numbers of the Virtex FPGA and the XC95108 CPLD along with the pin names of the other chips that they connect to These connections correspond with the pin assignments in the user constraint files VIRTEX UCF and CPLD UCF XSV BOARD V1 0 MANUAL 34 5 16 2001 Virtex FPGA GND TMS GND 14 GND 15 VCCO 16 VCCINT 22 GND 29 GND 30 VCCO 32 VCCINT 37 GND 43 VCCINT 44 VCCO 45 GND Connections Between the Virtex FPGA and the Other XSV Board Components
45. s the programming proceeds You will also receive instructions on how to set the shunts on the XSV Board jumpers to place the oscillator into its programming mode At the end of the programming you will receive a message informing you that your XSV Board clock has been set Note that GXSSETCLK reprograms the CPLD on the XSV Board in order to access the programmable oscillator So you will need to reprogram the CPLD with a parallel port interface circuit if you want to program the FPGA See the next section for details on this Programming the Interface The Virtex FPGA is the main repository of programmable logic on the XSV Board The CPLD manages the configuration of the FPGA via the parallel port or from the Flash memory Therefore the CPLD must be configured so that it implements the necessary interface The CPLD stores its configuration in its internal non volatile memory so the interface is restored each time power is applied to the XSV Board unless the interface circuit is erased The CPLD is enabled for configuration by placing a shunt on jumper J23 The CPLD is configured with an interface by using the GXSLOAD software utility You start GXSLOAD by clicking on the icon placed on the desktop during the XSVTOOLs installation This brings up the screen shown below XSV BOARD V1 0 MANUAL 10 5 16 2001 X gxsload Drop BIT SVF and HEX files here to download to the XS Board Recent Files load EEPRO
46. t D4 left 05 left D6 left TxCLK RxCLK left D7 D8 left D9 left D10 left D11 left D12 left D14 left left left D13 left left left D15 left Connections Between the Virtex FPGA and the Other XSV Board Components XC95108 Flash Video Parallel Serial Prog Virtex FPGA CPLD LEDs Switches RAM Ethernet Decoder RAMDAC Codec RAM PS 2 USB Port Port Osc Xchecker 226 VCCO 227 GND 228 OE left 229 A18 left 230 A17 left 231 A16 left 232 A15 left 233 GND 234 A14 left 235 A13 left 236 A12 left 237 A11 left 238 A10 left 239 4 240 VCCO Connections Between the XC95108 CPLD and the Other XSV Board Components Flash Video Parallel Serial Prog XC95108 CPLD FPGA LEDs Switches RAM Ethernet Decoder RAMDAC Codec RAM PS 2 USB Port Port Osc Xchecker LEDS CFG1 RESET RESET VCCINT 60 58 62 132 51 right 133 S2 right 139 93 right 141 54 right 144 55 right 89 147 56 right 152 BARO 154 BAR1 157 BAR2 160 162 BAR4 169 BARS 177 167 183 left 163 181 left 0 left 1 2 156 2 83 54 55 145 left
47. t XCVBUS109 J25 2 XCVBUS053 J25 4 XCVBUSO54 025 5 gt XCVBUSO55 425 6 XCVBUSO56 J25 8 XCVBUSO57 4125 9 gt XCVBUSO63 12540 XCVBUS064 426212 XCVBUSO65 J25 13 gt XCVBUSO66 pr XCVBUSO67 XCVBUSO6B 925 17 gt XCVBUSO70 925 18 XCvBuso71 J25 20 XCVBUSO072 J25 21 gt XCVBUS073 J25 22 XCVBUSO74 425 24 XCVBUSO78 425 25 XCVBUS079 J25 26 XCVBUSOBO 425 28 XCVBUS081 J25 29 gt XCVBUSOB2 425 30 gt XCVBUSOB4 425 32 XCVBUSOBS 425 33 gt XCVBUSOB6 425 34 gt XCVBUS087 425 36 gt XCVBUSO93 125 37 gt 05094 J25 38 gt XCVBUSO95 J25 40 gt XCVBUSO96 425 41 gt XCVBUS097 425 42 gt XCVBUSO99 425 44 gt XCVBUS100 925 45 gt XCVBUS101 425 46 gt XCVBUS102 J25 48 gt XCVBUS103 125 49 gt XCVBUS107 J25 50 gt XCVBUS108 3 3V 25 3 325 1 J25 19 428 27 S 3 425 38 gt 34 425 43 5 3 5 7 425 15 2 4 428 23 34 325 31 325 39 gt 3 425 47 2 4 EXPANSION HEADER REVISION RECORD LTR ECO NO APPROVED _ DATE XCVBUSI001 2401 dieci gt XCVBUS186 126 2 XCVBUS187 126 4 128 8 gt XCVBUS189 426 6 XCVBUS191 426 8 XCVBUS192 428 8 gt XCVBUSI93 262 XCVBUSI94 XCVBUS195 426 13 gt XCVBUS199 XCVBUS200 XCVBUS201 126
48. tion is complete XSV Board Features The XSV Board includes the following resources m Programmable logic chips XILINX Virtex FPGA Virtex FPGAs from 57 Kgates XCV50 up to 888 Kgates XCV800 in a 240 pin PQFP or HQFP package are compatible with the XSV Board The Virtex FPGA is the main repository of programmable logic on the XSV Board XILINX XC95108 CPLD The CPLD is used to manage the configuration of the Virtex FPGA via the parallel port serial port or Flash RAM The CPLD also controls the configuration of the Ethernet PHY chip m Programmable oscillator that provides a clock signal to FPGA and CPLD derived form a 100 MHz base frequency m 16 Mbit Flash RAM that can store multiple configurations or general purpose data for the FPGA m Two independent 512K x 16 SRAM banks used by the FPGA for general purpose data storage XSV BOARD V1 0 MANUAL 5 5 16 2001 m Video decoder that accepts NTSC PAL SECAM signals through jack or S video connector and outputs the digitized signal to the FPGA m RAMDAC with a 256 entry 24 bit colormap that is used by the FPGA to output video to a VGA monitor m Stereo codec that lets the FPGA digitize and generate 0 50 KHz audio signals with up to 20 bits of resolution m 10BASE T 100BASE TX Ethernet PHY that allows the FPGA to access a LAN at up to 100 Mbps m Two expansion headers interface the FPGA to external circuitry through 76 general purpose I Os m Four pushb
49. uttons and one eight position DIP switch provide general purpose inputs to the FPGA and CPLD m Two LED digits and one LED bargraph let the FPGA and CPLD display status information m Mouse keyboard PS 2 port gives the FPGA access to common PC input devices m Single USB port provides FPGA with a serial I O channel with bandwidths of 1 5 to 12 Mbps m Parallel serial port interfaces let the CPLD send and receive data in a parallel or serial format similar to a PC m Xchecker cable interface allows downloading and readback of the FPGA configuration m ATX power connector or 9 VDC power jack lets the XSV Board receive power from a standard ATX power supply or a 9 VDC power supply The locations of these resources are indicated in the simplified view of the XSV Board shown below Each of these resources will be described in the following section XSV BOARD V1 0 MANUAL 6 5 16 2001 9 VDC Parallel Port Serial RCA S Video Jack Jack ATX Power Connector XC95108 CPLD Xchecker 05600 81 C82 R18 LL 512K x 8 SRAM Virtex FPGA c7 XCV50 800 C753 512K x 8 J 2 512K x 8 SRAM 062 SRAM U18 C78 Pushbuttons SW3 SW2 Stereo Stereo USB PS 2 RJ45 VGA Input
50. x CPLD FPGA The table below lists the connections from the FPGA and CPLD to the switches The DIP Switches also share the same pins as the uppermost eight bits of the Flash RAM address bus If the Flash RAM is programmed with several FPGA bitstreams then the DIP switch can be used to select a particular bitstreams which will be loaded into the FPGA by the CPLD on power up XSV BOARD V1 0 MANUAL 25 5 16 2001 Switch Virtex XC95108 Flash FPGA Pin CPLD Pin Function sw 174 SW2 175 SW3 176 SW4 185 7 DIPSW1 161 50 A13 DIPSW2 159 52 A14 DIPSW3 155 53 A15 DIPSW4 153 54 A16 DIPSW5 149 55 A17 DIPSW6 146 56 A18 DIPSW7 142 58 A19 DIPSW8 140 59 A20 Digit and Bargraph LEDs The XSV Board has a 10 segment bargraph LED and two more 7 segment LED digits for use by the FPGA and CPLD All of these LEDs are active high meaning that an LED segment will glow when a logic high is applied to it The table below lists the connections from the FPGA and CPLD to the LEDs The LEDs also share the same pins as the uppermost eight bits of the Flash RAM address bus If the Flash RAM is programmed with several FPGA bitstreams then the DIP switch can be used to select a particular bitstreams which will be loaded into the FPGA by the CPLD XSV BOARD V1 0 MANUAL 26 5 16 2001 XSV BOARD V1 0 MANUAL Left Digit Right Digit Bargraph 42 ie CD XC95108 CPLD LED SLO 5
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