EVBUM2074 - NB4N507ADEVB Evaluation Board User`s Manual
Contents
1. 190 090 WA NI SLINA ISMAN caisigadS 3SIMY3HLO SS3TNn s l S3O9NV33101 v0 61 1 SdlTllHd NOM QN9 VMS NOll93nONd 3719NV GUYIHL O3SIA 3M 31Vd STVA034ddV ano vws ON9 100 022 u QN9 VAS QqN9 1na 1dO8SWIL0 0LSO 3svo 21 00 000 06 QN9 1nd 0Lz ca qwo vws 9N9 1ng Ant QN9 VAS QN9 VHS QN9 VAS LdO8BSNLOCOLSO asvo 9 QN2 Lng ga v S v l v aaa QN2 VHS 8100x190 1n0x12 sau 9 N 9 N aNd S N ano 30 is os 99 9 N 29 zx 3191 1X gN9 1ng k a au3 1na IdO8SWILOSOISO 9 35v5 QN9 VMS ing QN2 VAS ano A Y aga N 012 QN9 VNS D Figure 5 Evaluation Board Schematic www BD tt tom ON mi co NB4N507ADEVB Table 2 NB4N507A DEMO EVALUATION BOARD BILL OF MATERIALS EATER Comeair vans E 3 C3 C7 C10 C12 Cap Chip 0 010 uF 0805 50 V 1096 ootu 4 C4 C6 C8 C11 Cap Chip 0 1 uF 0805 50 V 10 C5 C9 Cap Chip 22 uF Tant C 16 V 10 C13 Cap Chip 22 uF 1210 10 V Y5V RT er Si eater R A sur Heat Ne Sure Speen Rm Eme Resistor Chip 62 Q 0603 1 10 W 1 ea 2 Resistor Ori 270 Q 06032. b If a split power supply is used connect the CLKOUT outputs to the oscilloscope with matched cables 6 Ensure the oscilloscope is triggered properly Trigger the oscilloscope from the CLKOUT output NB4N507A EVALUATION BOARD PIN DESCRIPTIONS AND FEATURES BY PIN The NB4N507A Evaluation Board was designed to accommodate the test and evaluation of the NBAN507A PECL Clock Synthesizer Detailed board features by device pin are described below Crystal X1 CLK and X2 A through hole or surface mount crystal can be used The metal traces at the crystal pins are intentionally open for crystal use and will have no impedance affect on the crystal pins X1 CLK External Clock An SMA connector is provided for X1 CLK if an external clock source is used on Pin 1 The metal trace at the package pin is intentionally open for crystal use but must be shorted for a connection to Pin 1 for external clock use The unused component pad labeled C2 used for the crystal load capacitor may be used for a 50 Q resistor to ground to terminate an external signal generator SO and S1 The SO and S1 multiplier select pins can be exercised manually with the SO and S1 slide switches when the jumpers are used across JMP2 and JMP5 or they can be controlled externally via the SMA connectors with the jumpers open The H position of the DIP switch asserts a logic HIGH Vcc on the assigned pin and the L asserts a logic LOW DUTGND The SO and S1 device
3. 1 16 W 1 wem ewa OOO o m m Resistor Chip 0 Q 0805 1 8 W 596 og 1 ems we ca Fo rs ONT Crystal ABRACON ABL 25 000MHZ B2F Through Hole 25 MHz CTS FREQ ZATS 250 BSM 1E Surface Mount CTS FREQ ZATS 250 B 3 Through Hole Y1 for Through hole Xtal Pin Receptacle Ampere 140 Ig Maximum Pin 0 021 Tin Gold y ON Semiconductor and are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or f
4. pins have internal pull up and pulldown resistors When left open the SO or S1 switch floats to mid logic level In the M position the slide switch is an open and the pin floats to the mid logic level CLKOUT and CLKOUT The CLKOUT and CLKOUT PECL outputs have equal length 50 Q board traces with SMA connectors Matched cables can connect to an oscilloscope or frequency counter The LV PECL CLKOUT outputs have nonstandard open collector outputs and must be externally DC loaded and terminated Thevenin equivalent load and termination resistors are provided on board at the output s SMA connector OE The Output Enable function can be exercised manually with the OE switch when the JMP4 jumper is used or they can be controlled externally via the SMA connector and the jumper open www BD ff com ON NB4N507ADEVB Q4VOB8 NOILVAIVAS M31S3L 83 10NVH LOSNVEN 39IA3Q z881 8S58 08v xv4 c6co 8c8 08v 91S Z8ZS8 ZV 3dW3l HQ LNOWNIV4 M GYLL ONI S3IL1VI93dS WPN LS4L ONVH QqN9 1na QN9 VNS A au5 1na X9 32v18 VNVNV8 QN9 VS A QN9 VWS 39v18 C CVNYNV8 ZN QN9 VNS any anzz Md gt 69 IVNVNVH 40 81 dSH L 0N 023 0 81 90 var 3SV313M TVILINI 31va 03A03ddV ON 023 Q3023M NOISIA3N 334930 01 319NV 03SV313N 00 0 79
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6. NB4N507ADEVB NB4N507ADEVB Evaluation Board User s Manual Description The NB4N507ADEVB Evaluation Board provides a flexible and convenient platform to quickly evaluate characterize and verify the performance and operation of the NB4NS507A PECL Clock Synthesizer This user s manual provides detailed information on board contents layout and its use It should be used in conjunction with a device datasheet NB4N507A www onsemi com Board Features Accommodates the Electrical Characterization of the NB4N507A in 16 pin 150 mil SOIC Package Supports use of a 10 MHz to 27 MHz Through hole or Surface Mount Crystal Incorporates on Board Slide Switch Controlled Multiplier Select and OE Logic Pins Minimizing Excess Cabling SMA Connectors are Provided for Auxiliary Input and Output Interfaces Differential PECL Outputs Loaded Terminated On board Output Signals are Monitored via SMA Connectors Convenient and Compact Board Layout e 3 3 V or 5 0 V Single or Split Power Supply Operation HB4H597 EVALUATION BOARD 1742 REV B i ON Semiconductor hitp onsemi com EVAL BOARD USER S MANUAL Board Layout The evaluation board is constructed with Getek material with 50 2 trace impedances and is designed to minimize noise achieve high bandwidth and minimize crosstalk The NB4N507A evaluation board is equipped with 3 position slide switches These switches are used to manipulate the static input log
7. NS Power Supply Use high impedance probes of the oscilloscope or frequency counter to monitor the LV PECL CLKOUT outputs Spilt Power Supply Optional For some tests an optional split or dual power supply technique can be used however doing so will double terminate the LV PECL outputs into 50 Qs of an oscilloscope or a frequency counter and will therefore appear to halve the output amplitude Since Vrr Vpp 2 0 V off setting Vpp by 42 0 V yields Vrr 0 V or Ground The Vrr terminal connects to the isolated SMAGND connector ground plane and is not to be confused with the device ground pin or DUTGND Single Supply Spilt Power Supply Optional SMAGND BLACK Vir Vpp 20 V 0V DUTGND BLACK DUTGND 1 3 V or 3 0 V Power Supplies BN Vpp GND 3 3 V Figure 2 Single Power Supply Configuration Dual Power Supplies 3 3 V Figure 3 Split Power Supply Connections www BD ff com ON NB4N507ADEVB Open Traces Intentional For Crystal Use Signal Generator Optional emicenduetor NT HB4H597 EVALUATION BOARD 11742 REV B e DUTGND es e PECL Output Load Termination Resistors so DE Real Time Digital Oscilloscope or Frequency Counter Hi Z or 50 Q CLKOUT Q re Hi Z or 50 Q Figure 4 NB4N507A Evaluation Board LAB SETUP AND MEASUREMENT PROCEDURE Equipment Used Agilent Signal Gene
8. ic levels of the Multiplier Select pins SO and S1 and Output Enable pin OE The H position of the slide switch asserts a logic HIGH on the assigned pin the L asserts a logic LOW and the M is an open where the pin floats to a mid logic level by way of the device s internal pull up and pulldown resistors Multiplier Select pins SO and S1 and Output Enable pin OE also have SMA connector provisions if the application requires them Layer Stack L1 Signal L2 SMA Ground L3 Vcc Positive Power Supply and DUTGND Device Ground Negative Power Supply L4 Signal ON Semiconductor Figure 1 Evaluation Board Semiconductor compo GAZRAT B D I CO m O N Order Number April 2012 Rev 2 e e EVBUM2074 D NB4N507ADEVB LAB SETUP PROCEDURE Power Supply Connections and Output Termination The NB4N507A has a positive supply pin Vpp and a negative supply pin DUTGND SMAGND is the ground plane for the SMA connectors Power supply banana plug connectors for Vpp DUTGND and SMAGND are provided in the corners of the board The LV PECL CLKOUT outputs have non standard open collector outputs and must be externally DC loaded and terminated Thevenin equivalent load and termination resistors are provided on board at the output s SMA connector Single Supply Recommended Connect a single power supply to the evaluation board see Figure 2 Connect Vpp to 43 3 V Connect GND to 0 V Table 1 POWER SUPPLY CONFIGURATIO
9. or any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT N American Technical Support 800 282 9855 Toll Free ON Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 5163 Denver Colorado 80217 USA Europe Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421 33 790 2910 ars Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Japan Customer Focus Center For additional information please contact your local Email orderlit onsemi com Phone 81 3 5817 1050 Sales Representative www BDT
10. rator 433250A for CLK External Clock Source Tektronix or LeCroy with High Impedance Probes or TDS8000 Oscilloscope or Frequency Counter Agilent 46624A DC Power Supply Digital Voltmeter e Matched High speed Cables with SMA Connectors for the PECL CLKOUT Pins In order to get started and demonstrate the NB4N507A perform the following test setup sequence 1 To monitor the CLKOUT outputs on an oscilloscope or frequency counter a Connect a single power supply to the evaluation board see Figure 2 Connect Vpp to 3 3 V Connect GND to 0 V b or Connect a split power supply to the evaluation board see Figure 3 Connect Vcc banana jack to 2 0 V Connect Vrr banana jack to SMA GND 0V Connect GND banana jack to 1 3 V for 3 3 V operation or 3 0 V for 5 0 V operation 2 Determine if a crystal or an external clock reference will be used a For crystal use install a crystal www BD ff com ON NB4N507ADEVB b For external clock reference use short the open trace at Pin 1 and provide an external clock reference from a signal generator 10 27 MHz into the X1 CLK pin Terminate the signal generator with 50 Q to SMA ground 3 Set the programmable SO and S1 pin switches accordingly to achieve the desired function table logic input levels 4 Set the OE pin to a logic HIGH 5 a If a single power supply is used connect the CLKOUT outputs to the oscilloscope with matched high impedance probe cables
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